219 lines
7.6 KiB
C
219 lines
7.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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#ifndef _UAPI_ASM_SW64_FPU_H
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#define _UAPI_ASM_SW64_FPU_H
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/*
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* SW-64 floating-point control register defines:
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*/
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#define FPCR_DNOD (1UL << 47) /* denorm INV trap disable */
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#define FPCR_DNZ (1UL << 48) /* denorms to zero */
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#define FPCR_INVD (1UL << 49) /* invalid op disable (opt.) */
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#define FPCR_DZED (1UL << 50) /* division by zero disable (opt.) */
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#define FPCR_OVFD (1UL << 51) /* overflow disable (optional) */
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#define FPCR_INV (1UL << 52) /* invalid operation */
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#define FPCR_DZE (1UL << 53) /* division by zero */
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#define FPCR_OVF (1UL << 54) /* overflow */
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#define FPCR_UNF (1UL << 55) /* underflow */
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#define FPCR_INE (1UL << 56) /* inexact */
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#define FPCR_IOV (1UL << 57) /* integer overflow */
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#define FPCR_UNDZ (1UL << 60) /* underflow to zero (opt.) */
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#define FPCR_UNFD (1UL << 61) /* underflow disable (opt.) */
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#define FPCR_INED (1UL << 62) /* inexact disable (opt.) */
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#define FPCR_SUM (1UL << 63) /* summary bit */
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#define FPCR_DYN_SHIFT 58 /* first dynamic rounding mode bit */
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#define FPCR_DYN_CHOPPED (0x0UL << FPCR_DYN_SHIFT) /* towards 0 */
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#define FPCR_DYN_MINUS (0x1UL << FPCR_DYN_SHIFT) /* towards -INF */
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#define FPCR_DYN_NORMAL (0x2UL << FPCR_DYN_SHIFT) /* towards nearest */
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#define FPCR_DYN_PLUS (0x3UL << FPCR_DYN_SHIFT) /* towards +INF */
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#define FPCR_DYN_MASK (0x3UL << FPCR_DYN_SHIFT)
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#define FPCR_MASK 0xffff800000000000L
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/* status bit coming from hardware fpcr . definde by fire3 */
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#define FPCR_STATUS_INV0 (1UL << 52)
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#define FPCR_STATUS_DZE0 (1UL << 53)
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#define FPCR_STATUS_OVF0 (1UL << 54)
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#define FPCR_STATUS_UNF0 (1UL << 55)
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#define FPCR_STATUS_INE0 (1UL << 56)
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#define FPCR_STATUS_OVI0 (1UL << 57)
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#define FPCR_STATUS_INV1 (1UL << 36)
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#define FPCR_STATUS_DZE1 (1UL << 37)
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#define FPCR_STATUS_OVF1 (1UL << 38)
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#define FPCR_STATUS_UNF1 (1UL << 39)
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#define FPCR_STATUS_INE1 (1UL << 40)
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#define FPCR_STATUS_OVI1 (1UL << 41)
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#define FPCR_STATUS_INV2 (1UL << 20)
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#define FPCR_STATUS_DZE2 (1UL << 21)
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#define FPCR_STATUS_OVF2 (1UL << 22)
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#define FPCR_STATUS_UNF2 (1UL << 23)
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#define FPCR_STATUS_INE2 (1UL << 24)
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#define FPCR_STATUS_OVI2 (1UL << 25)
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#define FPCR_STATUS_INV3 (1UL << 4)
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#define FPCR_STATUS_DZE3 (1UL << 5)
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#define FPCR_STATUS_OVF3 (1UL << 6)
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#define FPCR_STATUS_UNF3 (1UL << 7)
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#define FPCR_STATUS_INE3 (1UL << 8)
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#define FPCR_STATUS_OVI3 (1UL << 9)
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#define FPCR_STATUS_MASK0 (FPCR_STATUS_INV0 | FPCR_STATUS_DZE0 | \
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FPCR_STATUS_OVF0 | FPCR_STATUS_UNF0 | \
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FPCR_STATUS_INE0 | FPCR_STATUS_OVI0)
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#define FPCR_STATUS_MASK1 (FPCR_STATUS_INV1 | FPCR_STATUS_DZE1 | \
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FPCR_STATUS_OVF1 | FPCR_STATUS_UNF1 | \
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FPCR_STATUS_INE1 | FPCR_STATUS_OVI1)
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#define FPCR_STATUS_MASK2 (FPCR_STATUS_INV2 | FPCR_STATUS_DZE2 | \
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FPCR_STATUS_OVF2 | FPCR_STATUS_UNF2 | \
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FPCR_STATUS_INE2 | FPCR_STATUS_OVI2)
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#define FPCR_STATUS_MASK3 (FPCR_STATUS_INV3 | FPCR_STATUS_DZE3 | \
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FPCR_STATUS_OVF3 | FPCR_STATUS_UNF3 | \
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FPCR_STATUS_INE3 | FPCR_STATUS_OVI3)
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/*
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* IEEE trap enables are implemented in software. These per-thread
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* bits are stored in the "ieee_state" field of "struct thread_info".
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* Thus, the bits are defined so as not to conflict with the
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* floating-point enable bit (which is architected).
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*/
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#define IEEE_TRAP_ENABLE_INV (1UL << 1) /* invalid op */
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#define IEEE_TRAP_ENABLE_DZE (1UL << 2) /* division by zero */
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#define IEEE_TRAP_ENABLE_OVF (1UL << 3) /* overflow */
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#define IEEE_TRAP_ENABLE_UNF (1UL << 4) /* underflow */
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#define IEEE_TRAP_ENABLE_INE (1UL << 5) /* inexact */
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#define IEEE_TRAP_ENABLE_DNO (1UL << 6) /* denorm */
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#define IEEE_TRAP_ENABLE_MASK (IEEE_TRAP_ENABLE_INV | IEEE_TRAP_ENABLE_DZE |\
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IEEE_TRAP_ENABLE_OVF | IEEE_TRAP_ENABLE_UNF |\
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IEEE_TRAP_ENABLE_INE | IEEE_TRAP_ENABLE_DNO)
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/* Denorm and Underflow flushing */
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#define IEEE_MAP_DMZ (1UL << 12) /* Map denorm inputs to zero */
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#define IEEE_MAP_UMZ (1UL << 13) /* Map underflowed outputs to zero */
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#define IEEE_MAP_MASK (IEEE_MAP_DMZ | IEEE_MAP_UMZ)
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/* status bits coming from fpcr: */
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#define IEEE_STATUS_INV (1UL << 17)
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#define IEEE_STATUS_DZE (1UL << 18)
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#define IEEE_STATUS_OVF (1UL << 19)
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#define IEEE_STATUS_UNF (1UL << 20)
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#define IEEE_STATUS_INE (1UL << 21)
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#define IEEE_STATUS_DNO (1UL << 22)
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#define IEEE_STATUS_MASK (IEEE_STATUS_INV | IEEE_STATUS_DZE | \
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IEEE_STATUS_OVF | IEEE_STATUS_UNF | \
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IEEE_STATUS_INE | IEEE_STATUS_DNO)
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#define IEEE_SW_MASK (IEEE_TRAP_ENABLE_MASK | \
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IEEE_STATUS_MASK | IEEE_MAP_MASK)
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#define IEEE_CURRENT_RM_SHIFT 32
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#define IEEE_CURRENT_RM_MASK (3UL << IEEE_CURRENT_RM_SHIFT)
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#define IEEE_STATUS_TO_EXCSUM_SHIFT 16
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#define IEEE_INHERIT (1UL << 63) /* inherit on thread create? */
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/* ieee_state expand to surport simd added by fire3 */
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#define IEEE_STATUS_INV0 (1UL << 17)
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#define IEEE_STATUS_DZE0 (1UL << 18)
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#define IEEE_STATUS_OVF0 (1UL << 19)
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#define IEEE_STATUS_UNF0 (1UL << 20)
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#define IEEE_STATUS_INE0 (1UL << 21)
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#define IEEE_STATUS_DNO0 (1UL << 22)
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#define IEEE_STATUS_MASK0 (IEEE_STATUS_INV0 | IEEE_STATUS_DZE0 | \
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IEEE_STATUS_OVF0 | IEEE_STATUS_UNF0 | \
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IEEE_STATUS_INE0 | IEEE_STATUS_DNO0)
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#define IEEE_STATUS0_TO_EXCSUM_SHIFT 16
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#define IEEE_STATUS_INV1 (1UL << 23)
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#define IEEE_STATUS_DZE1 (1UL << 24)
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#define IEEE_STATUS_OVF1 (1UL << 25)
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#define IEEE_STATUS_UNF1 (1UL << 26)
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#define IEEE_STATUS_INE1 (1UL << 27)
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#define IEEE_STATUS_DNO1 (1UL << 28)
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#define IEEE_STATUS_MASK1 (IEEE_STATUS_INV1 | IEEE_STATUS_DZE1 | \
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IEEE_STATUS_OVF1 | IEEE_STATUS_UNF1 | \
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IEEE_STATUS_INE1 | IEEE_STATUS_DNO1)
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#define IEEE_STATUS1_TO_EXCSUM_SHIFT 22
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#define IEEE_STATUS_INV2 (1UL << 34)
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#define IEEE_STATUS_DZE2 (1UL << 35)
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#define IEEE_STATUS_OVF2 (1UL << 36)
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#define IEEE_STATUS_UNF2 (1UL << 37)
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#define IEEE_STATUS_INE2 (1UL << 38)
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#define IEEE_STATUS_DNO2 (1UL << 39)
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#define IEEE_STATUS_MASK2 (IEEE_STATUS_INV2 | IEEE_STATUS_DZE2 | \
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IEEE_STATUS_OVF2 | IEEE_STATUS_UNF2 | \
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IEEE_STATUS_INE2 | IEEE_STATUS_DNO2)
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#define IEEE_STATUS2_TO_EXCSUM_SHIFT 33
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#define IEEE_STATUS_INV3 (1UL << 40)
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#define IEEE_STATUS_DZE3 (1UL << 41)
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#define IEEE_STATUS_OVF3 (1UL << 42)
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#define IEEE_STATUS_UNF3 (1UL << 43)
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#define IEEE_STATUS_INE3 (1UL << 44)
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#define IEEE_STATUS_DNO3 (1UL << 45)
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#define IEEE_STATUS_MASK3 (IEEE_STATUS_INV3 | IEEE_STATUS_DZE3 | \
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IEEE_STATUS_OVF3 | IEEE_STATUS_UNF3 | \
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IEEE_STATUS_INE3 | IEEE_STATUS_DNO3)
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#define IEEE_STATUS3_TO_EXCSUM_SHIFT 39
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/*
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* Convert the software IEEE trap enable and status bits into the
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* hardware fpcr format.
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*/
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static inline unsigned long
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ieee_swcr_to_fpcr(unsigned long sw)
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{
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unsigned long fp;
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fp = (sw & IEEE_STATUS_MASK0) << 35;
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fp |= (sw & IEEE_STATUS_MASK1) << 13;
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fp |= (sw & IEEE_STATUS_MASK2) >> 14;
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fp |= (sw & IEEE_STATUS_MASK3) >> 36;
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fp |= (sw & IEEE_MAP_DMZ) << 36;
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fp |= (sw & IEEE_STATUS_MASK0 ? FPCR_SUM : 0);
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fp |= (sw & IEEE_STATUS_MASK1 ? FPCR_SUM : 0);
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fp |= (sw & IEEE_STATUS_MASK2 ? FPCR_SUM : 0);
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fp |= (sw & IEEE_STATUS_MASK3 ? FPCR_SUM : 0);
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fp |= (~sw & (IEEE_TRAP_ENABLE_INV
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| IEEE_TRAP_ENABLE_DZE
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| IEEE_TRAP_ENABLE_OVF)) << 48;
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fp |= (~sw & (IEEE_TRAP_ENABLE_UNF | IEEE_TRAP_ENABLE_INE)) << 57;
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fp |= (sw & IEEE_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0);
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fp |= (~sw & IEEE_TRAP_ENABLE_DNO) << 41;
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return fp;
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}
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static inline unsigned long
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ieee_fpcr_to_swcr(unsigned long fp)
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{
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unsigned long sw;
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sw = (fp >> 35) & IEEE_STATUS_MASK;
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sw |= (fp >> 36) & IEEE_MAP_DMZ;
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sw |= (~fp >> 48) & (IEEE_TRAP_ENABLE_INV
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| IEEE_TRAP_ENABLE_DZE
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| IEEE_TRAP_ENABLE_OVF);
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sw |= (~fp >> 57) & (IEEE_TRAP_ENABLE_UNF | IEEE_TRAP_ENABLE_INE);
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sw |= (fp >> 47) & IEEE_MAP_UMZ;
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sw |= (~fp >> 41) & IEEE_TRAP_ENABLE_DNO;
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return sw;
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}
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#endif /* _UAPI_ASM_SW64_FPU_H */
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