186 lines
3.5 KiB
Plaintext
186 lines
3.5 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*
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*/
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/ {
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cam_ircut0: cam_ircut {
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status = "disabled";
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compatible = "rockchip,ircut";
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ircut-open-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
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ircut-close-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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};
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vcc_mipidphy0: vcc-mipidcphy0-regulator {
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status = "disabled";
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compatible = "regulator-fixed";
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gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&mipidphy0_pwr>;
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regulator-name = "vcc_mipidphy0";
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enable-active-high;
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};
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};
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&csi2_dphy0 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipidphy0_in_ucam0: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&xc7160_out0>;
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data-lanes = <1 2 3 4>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csidphy0_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi2_csi2_input>;
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};
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};
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};
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};
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&csi2_dphy0_hw {
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status = "okay";
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};
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&i2c7 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c7m2_xfer>;
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XC7160: XC7160b@1b{
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compatible = "firefly,xc7160";
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reg = <0x1b>;
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clocks = <&cru CLK_MIPI_CAMARAOUT_M1>;
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clock-names = "xvclk";
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pinctrl-names = "default";
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pinctrl-0 = <&mipim1_camera1_clk>;
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power-domains = <&power RK3588_PD_VI>;
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power-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
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reset-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
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pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
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//avdd-supply = <&vcc_mipidcphy0>;
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firefly,clkout-enabled-index = <0>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "NC";
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rockchip,camera-module-lens-name = "NC";
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port {
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xc7160_out0: endpoint {
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remote-endpoint = <&mipidphy0_in_ucam0>;
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data-lanes = <1 2 3 4>;
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};
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};
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};
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};
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&mipi2_csi2 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi2_csi2_input: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&csidphy0_out>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi2_csi2_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&cif_mipi2_in0>;
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};
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};
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};
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};
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&pinctrl {
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cam {
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mipidphy0_pwr: mipidphy0-pwr {
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rockchip,pins =
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/* camera power en */
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<1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&rkcif {
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status = "okay";
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// memory-region = <&cif_reserved>;
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};
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&rkcif_mipi_lvds2 {
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status = "okay";
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port {
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cif_mipi2_in0: endpoint {
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remote-endpoint = <&mipi2_csi2_output>;
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};
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};
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};
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&rkcif_mipi_lvds2_sditf {
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status = "disabled";
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port {
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mipi_lvds2_sditf: endpoint {
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remote-endpoint = <&isp0_vir0>;
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};
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};
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};
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&rkcif_mmu {
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status = "okay";
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};
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&rkisp0 {
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status = "disabled";
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};
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&isp0_mmu {
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status = "disabled";
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};
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&rkisp0_vir0 {
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status = "disabled";
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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isp0_vir0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi_lvds2_sditf>;
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};
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};
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};
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