304 lines
5.4 KiB
Plaintext
304 lines
5.4 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
|
*
|
|
*/
|
|
|
|
&mipi_dcphy0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&route_dsi0 {
|
|
status = "okay";
|
|
connect = <&vp2_out_dsi0>;
|
|
};
|
|
|
|
&dsi0_in_vp2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&dsi0 {
|
|
status = "okay";
|
|
|
|
dsi0_panel: panel@0 {
|
|
status = "okay";
|
|
compatible = "simple-panel-dsi";
|
|
reg = <0>;
|
|
backlight = <&backlight_dsi0>;
|
|
power-supply = <&mipi_dsi0_power>;
|
|
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
|
|
|
|
enable-delay-ms = <35>;
|
|
prepare-delay-ms = <6>;
|
|
reset-delay-ms = <0>;
|
|
init-delay-ms = <20>;
|
|
unprepare-delay-ms = <0>;
|
|
disable-delay-ms = <20>;
|
|
|
|
size,width = <74>;
|
|
size,height = <133>;
|
|
|
|
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
|
|
dsi,format = <MIPI_DSI_FMT_RGB888>;
|
|
dsi,lanes = <4>;
|
|
|
|
panel-init-sequence = [
|
|
39 05 04 FF 98 81 03
|
|
15 05 02 01 00
|
|
15 05 02 02 00
|
|
15 05 02 03 53
|
|
15 05 02 04 D3
|
|
15 05 02 05 00
|
|
15 05 02 06 0D
|
|
15 05 02 07 08
|
|
15 05 02 08 00
|
|
15 05 02 09 00
|
|
15 05 02 0a 00
|
|
15 05 02 0b 00
|
|
15 05 02 0c 00
|
|
15 05 02 0d 00
|
|
15 05 02 0e 00
|
|
15 05 02 0f 28
|
|
15 05 02 10 28
|
|
15 05 02 11 00
|
|
15 05 02 12 00
|
|
15 05 02 13 00
|
|
15 05 02 14 00
|
|
15 05 02 15 00
|
|
15 05 02 16 00
|
|
15 05 02 17 00
|
|
15 05 02 18 00
|
|
15 05 02 19 00
|
|
15 05 02 1a 00
|
|
15 05 02 1b 00
|
|
15 05 02 1d 00
|
|
15 05 02 1e 40
|
|
15 05 02 1f 80
|
|
15 05 02 20 06
|
|
15 05 02 21 01
|
|
15 05 02 22 00
|
|
15 05 02 23 00
|
|
15 05 02 24 00
|
|
15 05 02 25 00
|
|
15 05 02 26 00
|
|
15 05 02 27 00
|
|
15 05 02 28 33
|
|
15 05 02 29 33
|
|
15 05 02 2a 00
|
|
15 05 02 2b 00
|
|
15 05 02 2c 00
|
|
15 05 02 2d 00
|
|
15 05 02 2e 00
|
|
15 05 02 2f 00
|
|
15 05 02 30 00
|
|
15 05 02 31 00
|
|
15 05 02 32 00
|
|
15 05 02 33 00
|
|
15 05 02 34 03
|
|
15 05 02 35 00
|
|
15 05 02 36 00
|
|
15 05 02 37 00
|
|
15 05 02 38 96
|
|
15 05 02 39 00
|
|
15 05 02 3a 00
|
|
15 05 02 3b 00
|
|
15 05 02 3c 00
|
|
15 05 02 3d 00
|
|
15 05 02 3e 00
|
|
15 05 02 3f 00
|
|
15 05 02 40 00
|
|
15 05 02 41 00
|
|
15 05 02 42 00
|
|
15 05 02 43 00
|
|
15 05 02 44 00
|
|
15 05 02 50 00
|
|
15 05 02 51 23
|
|
15 05 02 52 45
|
|
15 05 02 53 67
|
|
15 05 02 54 89
|
|
15 05 02 55 AB
|
|
15 05 02 56 01
|
|
15 05 02 57 23
|
|
15 05 02 58 45
|
|
15 05 02 59 67
|
|
15 05 02 5a 89
|
|
15 05 02 5b AB
|
|
15 05 02 5c CD
|
|
15 05 02 5d EF
|
|
15 05 02 5e 00
|
|
15 05 02 5f 08
|
|
15 05 02 60 08
|
|
15 05 02 61 06
|
|
15 05 02 62 06
|
|
15 05 02 63 01
|
|
15 05 02 64 01
|
|
15 05 02 65 00
|
|
15 05 02 66 00
|
|
15 05 02 67 02
|
|
15 05 02 68 15
|
|
15 05 02 69 15
|
|
15 05 02 6a 14
|
|
15 05 02 6b 14
|
|
15 05 02 6c 0D
|
|
15 05 02 6d 0D
|
|
15 05 02 6e 0C
|
|
15 05 02 6f 0C
|
|
15 05 02 70 0F
|
|
15 05 02 71 0F
|
|
15 05 02 72 0E
|
|
15 05 02 73 0E
|
|
15 05 02 74 02
|
|
15 05 02 75 08
|
|
15 05 02 76 08
|
|
15 05 02 77 06
|
|
15 05 02 78 06
|
|
15 05 02 79 01
|
|
15 05 02 7a 01
|
|
15 05 02 7b 00
|
|
15 05 02 7c 00
|
|
15 05 02 7d 02
|
|
15 05 02 7e 15
|
|
15 05 02 7f 15
|
|
15 05 02 80 14
|
|
15 05 02 81 14
|
|
15 05 02 82 0D
|
|
15 05 02 83 0D
|
|
15 05 02 84 0C
|
|
15 05 02 85 0C
|
|
15 05 02 86 0F
|
|
15 05 02 87 0F
|
|
15 05 02 88 0E
|
|
15 05 02 89 0E
|
|
15 05 02 8A 02
|
|
39 05 04 FF 98 81 04
|
|
15 05 02 6E 2B
|
|
15 05 02 6F 37
|
|
15 05 02 3A 24
|
|
15 05 02 8D 1A
|
|
15 05 02 87 BA
|
|
15 05 02 B2 D1
|
|
15 05 02 88 0B
|
|
15 05 02 38 01
|
|
15 05 02 39 00
|
|
15 05 02 B5 02
|
|
15 05 02 31 25
|
|
15 05 02 3B 98
|
|
39 05 04 FF 98 81 01
|
|
15 05 02 22 0A
|
|
15 05 02 31 00
|
|
15 05 02 53 3D
|
|
15 05 02 55 3D
|
|
15 05 02 50 B5
|
|
15 05 02 51 AD
|
|
15 05 02 60 06
|
|
15 05 02 62 20
|
|
15 05 02 A0 00
|
|
15 05 02 A1 21
|
|
15 05 02 A2 35
|
|
15 05 02 A3 19
|
|
15 05 02 A4 1E
|
|
15 05 02 A5 33
|
|
15 05 02 A6 27
|
|
15 05 02 A7 26
|
|
15 05 02 A8 AF
|
|
15 05 02 A9 1B
|
|
15 05 02 AA 27
|
|
15 05 02 AB 8D
|
|
15 05 02 AC 1A
|
|
15 05 02 AD 1B
|
|
15 05 02 AE 50
|
|
15 05 02 AF 26
|
|
15 05 02 B0 2B
|
|
15 05 02 B1 54
|
|
15 05 02 B2 5E
|
|
15 05 02 B3 23
|
|
15 05 02 C0 00
|
|
15 05 02 C1 21
|
|
15 05 02 C2 35
|
|
15 05 02 C3 19
|
|
15 05 02 C4 1E
|
|
15 05 02 C5 33
|
|
15 05 02 C6 27
|
|
15 05 02 C7 26
|
|
15 05 02 C8 AF
|
|
15 05 02 C9 1B
|
|
15 05 02 CA 27
|
|
15 05 02 CB 8D
|
|
15 05 02 CC 1A
|
|
15 05 02 CD 1B
|
|
15 05 02 CE 50
|
|
15 05 02 CF 26
|
|
15 05 02 D0 2B
|
|
15 05 02 D1 54
|
|
15 05 02 D2 5E
|
|
15 05 02 D3 23
|
|
39 05 04 FF 98 81 00
|
|
15 78 02 11 00
|
|
15 05 02 29 00
|
|
];
|
|
|
|
panel-exit-sequence = [
|
|
05 78 01 28
|
|
05 00 01 10
|
|
];
|
|
|
|
disp0_timings0: display-timings {
|
|
native-mode = <&dsi0_timing0>;
|
|
dsi0_timing0: timing0 {
|
|
clock-frequency = <67000000>;
|
|
hactive = <800>;
|
|
vactive = <1280>;
|
|
hsync-len = <24>;
|
|
hback-porch = <24>;
|
|
hfront-porch = <12>;
|
|
vsync-len = <2>;
|
|
vback-porch = <9>;
|
|
vfront-porch = <7>;
|
|
hsync-active = <0>;
|
|
vsync-active = <0>;
|
|
de-active = <0>;
|
|
pixelclk-active = <0>;
|
|
};
|
|
};
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
port@0 {
|
|
reg = <0>;
|
|
panel_in_dsi0: endpoint {
|
|
remote-endpoint = <&dsi0_out_panel>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
dsi0_out_panel: endpoint {
|
|
remote-endpoint = <&panel_in_dsi0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&i2c2 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2m4_xfer>;
|
|
|
|
gt911_dsi0: gt911@5d {
|
|
status = "okay";
|
|
compatible = "goodix,gt911";
|
|
reg = <0x5d>;
|
|
interrupt-parent = <&gpio3>;
|
|
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
|
|
reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
|
|
irq-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
};
|