246 lines
6.1 KiB
C
246 lines
6.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef CHIP3_SPI_HEADER_H
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#define CHIP3_SPI_HEADER_H
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#include <linux/io.h>
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#include <linux/scatterlist.h>
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#include <linux/gpio.h>
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#include <linux/spi/spi.h>
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/* Register offsets */
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#define CHIP3_SPI_CTRL0 (0x00<<7)
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#define CHIP3_SPI_CTRL1 (0x04<<7)
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#define CHIP3_SPI_SSIENR (0x08<<7)
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#define CHIP3_SPI_MWCR (0x0c<<7)
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#define CHIP3_SPI_SER (0x10<<7)
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#define CHIP3_SPI_BAUDR (0x14<<7)
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#define CHIP3_SPI_TXFLTR (0x18<<7)
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#define CHIP3_SPI_RXFLTR (0x1c<<7)
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#define CHIP3_SPI_TXFLR (0x20<<7)
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#define CHIP3_SPI_RXFLR (0x24<<7)
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#define CHIP3_SPI_SR (0x28<<7)
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#define CHIP3_SPI_IMR (0x2c<<7)
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#define CHIP3_SPI_ISR (0x30<<7)
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#define CHIP3_SPI_RISR (0x34<<7)
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#define CHIP3_SPI_TXOICR (0x38<<7)
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#define CHIP3_SPI_RXOICR (0x3c<<7)
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#define CHIP3_SPI_RXUICR (0x40<<7)
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#define CHIP3_SPI_MSTICR (0x44<<7)
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#define CHIP3_SPI_ICR (0x48<<7)
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#define CHIP3_SPI_DMACR (0x4c<<7)
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#define CHIP3_SPI_DMATDLR (0x50<<7)
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#define CHIP3_SPI_DMARDLR (0x54<<7)
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#define CHIP3_SPI_IDR (0x58<<7)
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#define CHIP3_SPI_VERSION (0x5c<<7)
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#define CHIP3_SPI_DR (0x60<<7)
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/* Bit fields in CTRLR0 */
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#define SPI_DFS_OFFSET 0
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#define SPI_FRF_OFFSET 4
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#define SPI_FRF_SPI 0x0
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#define SPI_FRF_SSP 0x1
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#define SPI_FRF_MICROWIRE 0x2
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#define SPI_FRF_RESV 0x3
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#define SPI_MODE_OFFSET 6
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#define SPI_SCPH_OFFSET 6
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#define SPI_SCOL_OFFSET 7
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#define SPI_TMOD_OFFSET 8
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#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
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#define SPI_TMOD_TR 0x0 /* xmit & recv */
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#define SPI_TMOD_TO 0x1 /* xmit only */
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#define SPI_TMOD_RO 0x2 /* recv only */
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#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
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#define SPI_SLVOE_OFFSET 10
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#define SPI_SRL_OFFSET 11
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#define SPI_CFS_OFFSET 12
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/* Bit fields in SR, 7 bits */
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#define SR_MASK 0x7f /* cover 7 bits */
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#define SR_BUSY (1 << 0)
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#define SR_TF_NOT_FULL (1 << 1)
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#define SR_TF_EMPT (1 << 2)
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#define SR_RF_NOT_EMPT (1 << 3)
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#define SR_RF_FULL (1 << 4)
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#define SR_TX_ERR (1 << 5)
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#define SR_DCOL (1 << 6)
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/* Bit fields in ISR, IMR, RISR, 7 bits */
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#define SPI_INT_TXEI (1 << 0)
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#define SPI_INT_TXOI (1 << 1)
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#define SPI_INT_RXUI (1 << 2)
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#define SPI_INT_RXOI (1 << 3)
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#define SPI_INT_RXFI (1 << 4)
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#define SPI_INT_MSTI (1 << 5)
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/* Bit fields in DMACR */
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#define SPI_DMA_RDMAE (1 << 0)
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#define SPI_DMA_TDMAE (1 << 1)
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/* TX RX interrupt level threshold, max can be 256 */
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#define SPI_INT_THRESHOLD 32
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/* The depth of the FIFO buffer is 256, so the max transfer length is 256. */
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#define MAX_LEN 256
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/* The mode of spi controller. */
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#define SPI_TRANSMIT_RECEIVE 0x0c7
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#define SPI_EEPROM_READ 0x3c7
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#define SPI_TRANSMIT_ONLY 0x1c7
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enum chip3_ssi_type {
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SSI_MOTO_SPI = 0,
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SSI_TI_SSP,
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SSI_NS_MICROWIRE,
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};
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struct chip3_spi;
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struct chip3_spi {
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struct spi_controller *master;
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enum chip3_ssi_type type;
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void __iomem *regs;
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unsigned long paddr;
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int irq;
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u32 fifo_len; /* depth of the FIFO buffer */
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u32 max_freq; /* max bus freq supported */
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u32 reg_io_width; /* DR I/O width in bytes */
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u16 bus_num;
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u16 num_cs; /* supported slave numbers */
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void (*set_cs)(struct spi_device *spi, bool enable);
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/* Current message transfer state info */
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size_t len;
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void *tx;
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unsigned int tx_len;
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void *rx;
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unsigned int rx_len;
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u8 n_bytes; /* current is a 1/2 bytes op */
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u32 current_freq; /* frequency in hz */
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u8 buf[MAX_LEN];
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/* Bus interface info */
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void *priv;
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#ifdef CONFIG_DEBUG_FS
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struct dentry *debugfs;
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#endif
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};
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static inline u32 chip3_readl(struct chip3_spi *dws, u32 offset)
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{
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return __raw_readl(dws->regs + offset);
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}
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static inline u16 chip3_readw(struct chip3_spi *dws, u32 offset)
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{
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return __raw_readw(dws->regs + offset);
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}
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static inline void chip3_writel(struct chip3_spi *dws, u32 offset, u32 val)
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{
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__raw_writel(val, dws->regs + offset);
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}
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static inline void chip3_writew(struct chip3_spi *dws, u32 offset, u16 val)
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{
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__raw_writew(val, dws->regs + offset);
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}
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static inline u32 chip3_read_io_reg(struct chip3_spi *dws, u32 offset)
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{
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switch (dws->reg_io_width) {
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case 2:
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return chip3_readw(dws, offset);
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case 4:
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default:
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return chip3_readl(dws, offset);
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}
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}
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static inline void chip3_write_io_reg(struct chip3_spi *dws, u32 offset, u32 val)
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{
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switch (dws->reg_io_width) {
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case 2:
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chip3_writew(dws, offset, val);
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break;
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case 4:
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default:
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chip3_writel(dws, offset, val);
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break;
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}
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}
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static inline void spi_enable_chip(struct chip3_spi *dws, int enable)
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{
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chip3_writel(dws, CHIP3_SPI_SSIENR, (enable ? 1 : 0));
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}
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static inline void spi_set_clk(struct chip3_spi *dws, u16 div)
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{
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chip3_writel(dws, CHIP3_SPI_BAUDR, div);
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}
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/* Disable IRQ bits */
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static inline void spi_mask_intr(struct chip3_spi *dws, u32 mask)
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{
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u32 new_mask;
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new_mask = chip3_readl(dws, CHIP3_SPI_IMR) & ~mask;
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chip3_writel(dws, CHIP3_SPI_IMR, new_mask);
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}
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/* Enable IRQ bits */
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static inline void spi_umask_intr(struct chip3_spi *dws, u32 mask)
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{
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u32 new_mask;
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new_mask = chip3_readl(dws, CHIP3_SPI_IMR) | mask;
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chip3_writel(dws, CHIP3_SPI_IMR, new_mask);
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}
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/*
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* This does disable the SPI controller, interrupts, and re-enable the
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* controller back. Transmit and receive FIFO buffers are cleared when the
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* device is disabled.
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*/
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static inline void spi_reset_chip(struct chip3_spi *dws)
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{
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spi_enable_chip(dws, 0);
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spi_mask_intr(dws, 0xff);
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spi_enable_chip(dws, 1);
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}
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static inline void spi_shutdown_chip(struct chip3_spi *dws)
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{
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spi_enable_chip(dws, 0);
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spi_set_clk(dws, 0);
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}
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/*
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* Each SPI slave device to work with chip3_api controller should
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* has such a structure claiming its working mode (poll or PIO/DMA),
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* which can be save in the "controller_data" member of the
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* struct spi_device.
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*/
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struct chip3_spi_chip {
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u8 poll_mode; /* 1 for controller polling mode */
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u8 type; /* SPI/SSP/MicroWire */
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u8 chip_select;
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void (*cs_control)(u32 command);
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};
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extern int chip3_spi_add_host(struct device *dev, struct chip3_spi *dws);
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extern void chip3_spi_remove_host(struct chip3_spi *dws);
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extern int chip3_spi_suspend_host(struct chip3_spi *dws);
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extern int chip3_spi_resume_host(struct chip3_spi *dws);
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/* platform related setup */
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extern int chip3_spi_mid_init(struct chip3_spi *dws); /* Intel MID platforms */
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#endif /* CHIP3_SPI_HEADER_H */
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