32 lines
1.3 KiB
C
32 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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// Copyright (c) 2020-2022 Hisilicon Limited.
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#ifndef __HNS3_ROH_REG_H__
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#define __HNS3_ROH_REG_H__
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/* CMDq Reg */
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#define HNS3_ROH_CMDQ_BASE 0x26000
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#define HNS3_ROH_TX_CMDQ_BASEADDR_L_REG (HNS3_ROH_CMDQ_BASE + 0x0)
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#define HNS3_ROH_TX_CMDQ_BASEADDR_H_REG (HNS3_ROH_CMDQ_BASE + 0x4)
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#define HNS3_ROH_TX_CMDQ_DEPTH_REG (HNS3_ROH_CMDQ_BASE + 0x8)
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#define HNS3_ROH_TX_CMDQ_TAIL_REG (HNS3_ROH_CMDQ_BASE + 0x10)
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#define HNS3_ROH_TX_CMDQ_HEAD_REG (HNS3_ROH_CMDQ_BASE + 0x14)
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#define HNS3_ROH_RX_CMDQ_BASEADDR_L_REG (HNS3_ROH_CMDQ_BASE + 0x18)
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#define HNS3_ROH_RX_CMDQ_BASEADDR_H_REG (HNS3_ROH_CMDQ_BASE + 0x1c)
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#define HNS3_ROH_RX_CMDQ_DEPTH_REG (HNS3_ROH_CMDQ_BASE + 0x20)
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#define HNS3_ROH_RX_CMDQ_TAIL_REG (HNS3_ROH_CMDQ_BASE + 0x24)
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#define HNS3_ROH_RX_CMDQ_HEAD_REG (HNS3_ROH_CMDQ_BASE + 0x28)
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/* Vector0 interrupt CMDQ event source register(RW) */
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#define HNS3_ROH_VECTOR0_CMDQ_SRC_REG (HNS3_ROH_CMDQ_BASE + 0x110)
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#define HNS3_ROH_VECTOR0_RX_CMDQ_INT_B 1
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#define HNS3_ROH_VECTOR0_INT_CTRL_REG 0x20404
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#define hns3_roh_write(dev, reg, val) writel((val), (dev)->reg_base + (reg))
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#define hns3_roh_read(dev, reg) readl((dev)->reg_base + (reg))
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#define hns3_roh_raw_write(value, addr) \
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__raw_writel((__force u32)cpu_to_le32(value), (addr))
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#endif /* __HNS3_ROH_REG_H__ */
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