138 lines
3.0 KiB
C
138 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* zhaoxin pinctrl common code
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* Copyright(c) 2023 Shanghai Zhaoxin Corporation. All rights reserved.
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*/
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#ifndef PINCTRL_zhaoxin_H
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#define PINCTRL_zhaoxin_H
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#include <linux/bits.h>
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#include <linux/compiler_types.h>
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#include <linux/gpio/driver.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/pm.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/spinlock_types.h>
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struct platform_device;
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struct device;
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/**
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* struct zhaoxin_pingroup pin define
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*/
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struct zhaoxin_pingroup {
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const char *name;
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const unsigned int *pins;
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size_t npins;
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unsigned short mode;
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const unsigned int *modes;
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};
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/**
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* struct zhaoxin_function
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*/
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struct zhaoxin_function {
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const char *name;
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const char * const *groups;
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size_t ngroups;
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};
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/**
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* struct zhaoxin_pin_map2_gpio
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* @zhaoxin_range_pin_base
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* @size: pin number
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* @zhaoxin_range_gpio_base
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*/
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struct zhaoxin_pin_map2_gpio {
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// unsigned int barno;
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unsigned int zhaoxin_range_pin_base;
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unsigned int zhaoxin_range_pin_size;
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int zhaoxin_range_gpio_base;
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};
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#define MAX_GPIO 256
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struct reg_cal_array {
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int pmio_offset;
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int size;
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};
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struct reg_calibrate {
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const struct reg_cal_array *reg;
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const int reg_cal_size;
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const int *cal_array;
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const int size;
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};
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struct index_cal_array {
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int reg_port_base;
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int reg_data_base;
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int index;
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int *cal_array;
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int size;
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};
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struct zhaoxin_pin_topology {
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const struct reg_calibrate *int_cal;
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const struct reg_calibrate *mod_sel_cal;
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const struct reg_calibrate *status_cal;
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const struct index_cal_array *gpio_in_cal;
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const struct index_cal_array *gpio_out_cal;
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const struct index_cal_array *gpio_dir_cal;
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const struct index_cal_array *trigger_cal;
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};
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#define TRIGGER_FALL_EDGE 0
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#define TRIGGER_RISE_EDGE 1
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#define TRIGGER_BOTH_EDGE 2
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#define TRIGGER_LOW_LEVEL 3
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#define TRIGGER_HIGH_LEVEL 4
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#define ZHAOXIN_GPIO_BASE_NOMAP -1
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struct zhaoxin_pinctrl_soc_data {
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const char *uid;
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const struct pinctrl_pin_desc *pins;
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size_t npins;
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const struct zhaoxin_pingroup *groups;
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size_t ngroups;
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const struct zhaoxin_function *functions;
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size_t nfunctions;
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const struct zhaoxin_pin_topology *pin_topologys;
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const struct zhaoxin_pin_map2_gpio *zhaoxin_pin_maps;
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size_t pin_map_size;
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};
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const struct zhaoxin_pinctrl_soc_data *
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zhaoxin_pinctrl_get_soc_data(struct platform_device *pdev);
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struct zhaoxin_pinctrl {
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struct device *dev;
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raw_spinlock_t lock;
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struct pinctrl_desc pctldesc;
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struct pinctrl_dev *pctldev;
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struct gpio_chip chip;
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struct irq_chip irqchip;
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const struct zhaoxin_pinctrl_soc_data *soc;
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const struct zhaoxin_pin_topology *pin_topologys;
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struct zhaoxin_pin_map2_gpio *pin_maps;
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size_t pin_map_size;
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int irq;
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int pmio_base;
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void __iomem *pm_pmio_base;
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int pmio_rx90;
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int pmio_rx8c;
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};
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int zhaoxin_pinctrl_probe_by_hid(struct platform_device *pdev);
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int zhaoxin_pinctrl_probe_by_uid(struct platform_device *pdev);
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#ifdef CONFIG_PM_SLEEP
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int zhaoxin_pinctrl_suspend_noirq(struct device *dev);
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int zhaoxin_pinctrl_resume_noirq(struct device *dev);
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#endif
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#endif /* PINCTRL_zhaoxin_H */
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