141 lines
3.0 KiB
C
141 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2021 - 2023, Shanghai Yunsilicon Technology Co., Ltd.
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* All rights reserved.
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*/
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#ifndef XSC_DEVICE_H
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#define XSC_DEVICE_H
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#include <linux/types.h>
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#include <rdma/ib_verbs.h>
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enum {
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XSC_MAX_COMMANDS = 32,
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XSC_CMD_DATA_BLOCK_SIZE = 512,
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XSC_PCI_CMD_XPORT = 7,
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};
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enum {
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XSC_PERM_LOCAL_READ = 1 << 0,
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XSC_PERM_LOCAL_WRITE = 1 << 1,
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XSC_PERM_REMOTE_READ = 1 << 2,
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XSC_PERM_REMOTE_WRITE = 1 << 3,
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XSC_PERM_ATOMIC = 1 << 6,
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XSC_PERM_UMR_EN = 1 << 7,
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};
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enum {
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XSC_ACCESS_MODE_PA = 0,
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XSC_ACCESS_MODE_MTT = 1,
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XSC_ACCESS_MODE_KLM = 2
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};
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enum {
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XSC_MKEY_REMOTE_INVAL = 1 << 24,
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XSC_MKEY_FLAG_SYNC_UMR = 1 << 29,
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XSC_MKEY_BSF_EN = 1 << 30,
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XSC_MKEY_LEN64 = 1 << 31,
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};
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enum {
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XSC_BF_REGS_PER_PAGE = 4,
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XSC_MAX_UAR_PAGES = 1 << 8,
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XSC_MAX_UUARS = XSC_MAX_UAR_PAGES * XSC_BF_REGS_PER_PAGE,
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};
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enum {
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XSC_DEV_CAP_FLAG_RC = 1LL << 0,
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XSC_DEV_CAP_FLAG_UC = 1LL << 1,
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XSC_DEV_CAP_FLAG_UD = 1LL << 2,
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XSC_DEV_CAP_FLAG_XRC = 1LL << 3,
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XSC_DEV_CAP_FLAG_SRQ = 1LL << 6,
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XSC_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
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XSC_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
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XSC_DEV_CAP_FLAG_APM = 1LL << 17,
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XSC_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
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XSC_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
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XSC_DEV_CAP_FLAG_RESIZE_SRQ = 1LL << 32,
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XSC_DEV_CAP_FLAG_REMOTE_FENCE = 1LL << 38,
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XSC_DEV_CAP_FLAG_TLP_HINTS = 1LL << 39,
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XSC_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
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XSC_DEV_CAP_FLAG_DCT = 1LL << 41,
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XSC_DEV_CAP_FLAG_CMDIF_CSUM = 1LL << 46,
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};
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enum xsc_event {
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XSC_EVENT_TYPE_COMP = 0x0,
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XSC_EVENT_TYPE_COMM_EST = 0x02,//mad
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XSC_EVENT_TYPE_CQ_ERROR = 0x04,
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XSC_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
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XSC_EVENT_TYPE_INTERNAL_ERROR = 0x08,//tpe私有err，无IB event对应
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XSC_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,//IBV_EVENT_QP_REQ_ERR
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XSC_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,//IBV_EVENT_QP_ACCESS_ERR
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};
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struct xsc_cmd_prot_block {
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u8 data[XSC_CMD_DATA_BLOCK_SIZE];
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u8 rsvd0[48];
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__be64 next;
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__be32 block_num;
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u8 owner_status; //init to 0, dma user should change this val to 1
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u8 token;
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u8 ctrl_sig;
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u8 sig;
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};
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#define XSC_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
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enum xsc_traffic_types {
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XSC_TT_IPV4,
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XSC_TT_IPV4_TCP,
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XSC_TT_IPV4_UDP,
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XSC_TT_IPV6,
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XSC_TT_IPV6_TCP,
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XSC_TT_IPV6_UDP,
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XSC_TT_IPV4_IPSEC_AH,
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XSC_TT_IPV6_IPSEC_AH,
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XSC_TT_IPV4_IPSEC_ESP,
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XSC_TT_IPV6_IPSEC_ESP,
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XSC_TT_ANY,
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XSC_NUM_TT,
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};
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#define XSC_NUM_INDIR_TIRS XSC_NUM_TT
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enum {
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XSC_HASH_FUNC_XOR = 0,
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XSC_HASH_FUNC_TOP = 1,
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XSC_HASH_FUNC_TOP_SYM = 2,
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XSC_HASH_FUNC_RSV = 3,
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};
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enum {
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XSC_L3_PROT_TYPE_IPV4 = 1 << 0,
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XSC_L3_PROT_TYPE_IPV6 = 1 << 1,
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};
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enum {
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XSC_L4_PROT_TYPE_TCP = 1 << 0,
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XSC_L4_PROT_TYPE_UDP = 1 << 1,
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};
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struct xsc_tirc_config {
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u8 l3_prot_type;
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u8 l4_prot_type;
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u32 rx_hash_fields;
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};
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static inline u8 hash_func_type(u8 hash_func)
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{
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switch (hash_func) {
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case ETH_RSS_HASH_TOP:
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return XSC_HASH_FUNC_TOP;
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case ETH_RSS_HASH_XOR:
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return XSC_HASH_FUNC_XOR;
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default:
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return XSC_HASH_FUNC_TOP;
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}
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}
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#endif /* XSC_DEVICE_H */
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