88 lines
2.1 KiB
C
88 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2021 - 2023, Shanghai Yunsilicon Technology Co., Ltd.
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* All rights reserved.
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*/
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#ifndef XSC_CORE_CQ_H
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#define XSC_CORE_CQ_H
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#include <rdma/ib_verbs.h>
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#include "common/driver.h"
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#include "common/xsc_hsi.h"
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#include "common/xsc_core.h"
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struct xsc_core_cq {
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u32 cqn;
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int cqe_sz;
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u64 arm_db;
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u64 ci_db;
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struct xsc_core_device *dev;
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atomic_t refcount;
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struct completion free;
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unsigned int vector;
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int irqn;
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void (*comp)(struct xsc_core_cq *cq);
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void (*event)(struct xsc_core_cq *cq, enum xsc_event);
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u32 cons_index;
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unsigned int arm_sn;
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struct xsc_rsc_debug *dbg;
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int pid;
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u32 reg_next_cid;
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u32 reg_done_pid;
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};
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enum {
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XSC_CQE_OWNER_MASK = 1,
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};
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enum {
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CQE_SIZE_64 = 0,
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CQE_SIZE_128 = 1,
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};
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enum {
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XSC_CQ_DB_REQ_NOT_SOL = 1,
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XSC_CQ_DB_REQ_NOT = 0,
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};
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static inline void xsc_cq_arm(struct xsc_core_cq *cq, u8 solicited)
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{
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union xsc_cq_doorbell db;
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db.val = 0;
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db.cq_next_cid = cq->cons_index;
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db.cq_id = cq->cqn;
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db.arm = solicited;
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/* Make sure that the doorbell record in host memory is
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* written before ringing the doorbell via PCI MMIO.
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*/
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wmb();
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writel(db.val, REG_ADDR(cq->dev, cq->arm_db));
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}
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static inline void xsc_cq_set_ci(struct xsc_core_cq *cq)
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{
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struct xsc_core_device *xdev = cq->dev;
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union xsc_cq_doorbell db;
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db.cq_next_cid = cq->cons_index;
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db.cq_id = cq->cqn;
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/* ensure write val visable before doorbell */
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wmb();
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writel(db.val, REG_ADDR(xdev, cq->ci_db));
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}
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int xsc_core_create_cq(struct xsc_core_device *dev, struct xsc_core_cq *cq,
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struct xsc_create_cq_mbox_in *in, int inlen);
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int xsc_core_destroy_cq(struct xsc_core_device *dev, struct xsc_core_cq *cq);
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int xsc_core_query_cq(struct xsc_core_device *dev, struct xsc_core_cq *cq,
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struct xsc_query_cq_mbox_out *out);
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int xsc_debug_cq_add(struct xsc_core_device *dev, struct xsc_core_cq *cq);
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void xsc_debug_cq_remove(struct xsc_core_device *dev, struct xsc_core_cq *cq);
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void xsc_init_cq_table(struct xsc_core_device *dev);
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void xsc_cleanup_cq_table(struct xsc_core_device *dev);
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#endif /* XSC_CORE_CQ_H */
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