141 lines
5.3 KiB
C
141 lines
5.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2022 - 2024 Mucse Corporation. */
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#ifndef _RNPGBEVF_REGS_H_
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#define _RNPGBEVF_REGS_H_
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enum NIC_MODE {
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MODE_NIC_MODE_2PORT_40G = 0,
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MODE_NIC_MODE_2PORT_10G = 1,
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MODE_NIC_MODE_4PORT_10G = 2,
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MODE_NIC_MODE_8PORT_10G = 3,
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};
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#define RNPGBE_DMA_RING_BASE 0x8000
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#define RNPGBE_DMA_RX_DESC_TIMEOUT_TH 0x8000
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#define RNPGBE_DMA_TX_DESC_FETCH_CTL 0x8004
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#define RNPGBE_DMA_TX_FLOW_CTRL_TM 0x8008
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#define RNPGBE_RING_BASE_N10 (0x8000)
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#define RNPGBE_RING_BASE_N500 (0x1000)
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#define RNPGBE_RING_OFFSET(i) (0x100 * (i))
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#define RNPGBE_DMA_RX_START (0x10)
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#define RNPGBE_DMA_RX_READY (0x14)
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#define RNPGBE_DMA_TX_START (0x18)
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#define RNPGBE_DMA_TX_READY (0x1c)
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#define RNPGBE_DMA_INT_STAT (0x20)
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#define RNPGBE_DMA_INT_MASK (0x24)
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#define TX_INT_MASK (0x1 << 1)
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#define RX_INT_MASK (0x1 << 0)
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#define RNPGBE_DMA_INT_CLR (0x28)
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#define RNPGBE_DMA_INT_TRIG (0x2c)
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#define RNPGBE_DMA_REG_RX_DESC_BUF_BASE_ADDR_HI (0x30)
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#define RNPGBE_DMA_REG_RX_DESC_BUF_BASE_ADDR_LO (0x34)
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#define RNPGBE_DMA_REG_RX_DESC_BUF_LEN (0x38)
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#define RNPGBE_DMA_REG_RX_DESC_BUF_HEAD (0x3c)
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#define RNPGBE_DMA_REG_RX_DESC_BUF_TAIL (0x40)
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#define RNPGBE_DMA_REG_RX_DESC_FETCH_CTRL (0x44)
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#define RNPGBE_DMA_REG_RX_INT_DELAY_TIMER (0x48)
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#define RNPGBE_DMA_REG_RX_INT_DELAY_PKTCNT (0x4c)
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#define RNPGBE_DMA_REG_RX_ARB_DEF_LVL (0x50)
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#define PCI_DMA_REG_RX_DESC_TIMEOUT_TH (0x54)
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#define PCI_DMA_REG_RX_SCATTER_LENGH (0x58)
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#define RNPGBE_DMA_REG_TX_DESC_BUF_BASE_ADDR_HI (0x60)
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#define RNPGBE_DMA_REG_TX_DESC_BUF_BASE_ADDR_LO (0x64)
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#define RNPGBE_DMA_REG_TX_DESC_BUF_LEN (0x68)
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#define RNPGBE_DMA_REG_TX_DESC_BUF_HEAD (0x6c)
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#define RNPGBE_DMA_REG_TX_DESC_BUF_TAIL (0x70)
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#define RNPGBE_DMA_REG_TX_DESC_FETCH_CTRL (0x74)
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#define RNPGBE_DMA_REG_TX_INT_DELAY_TIMER (0x78)
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#define RNPGBE_DMA_REG_TX_INT_DELAY_PKTCNT (0x7c)
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#define RNPGBE_DMA_REG_TX_ARB_DEF_LVL (0x80)
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#define RNPGBE_DMA_REG_TX_FLOW_CTRL_TH (0x84)
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#define RNPGBE_DMA_REG_TX_FLOW_CTRL_TM (0x88)
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#define VEB_TBL_CNTS 64
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#define RNPGBE_DMA_PORT_VBE_MAC_LO_TBL_N10(port, vf) \
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(0x80A0 + 4 * (port) + 0x100 * (vf))
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#define RNPGBE_DMA_PORT_VBE_MAC_HI_TBL_N10(port, vf) \
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(0x80B0 + 4 * (port) + 0x100 * (vf))
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#define RNPGBE_DMA_PORT_VEB_VID_TBL_N10(port, vf) \
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(0x80C0 + 4 * (port) + 0x100 * (vf))
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#define RNPGBE_DMA_PORT_VEB_VF_RING_TBL_N10(port, vf) \
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(0x80D0 + 4 * (port) + \
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0x100 * (vf))
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#define RNPGBE_DMA_PORT_VBE_MAC_LO_TBL_N500 (0x10c0)
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#define RNPGBE_DMA_PORT_VBE_MAC_HI_TBL_N500 (0x10c4)
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#define RNPGBE_DMA_PORT_VEB_VID_TBL_N500 (0x10c8)
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#define RNPGBE_DMA_PORT_VEB_VF_RING_TBL_N500 (0x10cc)
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#define RNPGBE_DMA_STATS_DMA_TO_MAC (0x1a0)
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#define RNPGBE_DMA_STATS_DMA_TO_SWITCH (0x1a4)
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#define RNPGBE_DMA_STATS_MAC_TO_MAC (0x1b0)
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#define RNPGBE_DMA_STATS_SWITCH_TO_SWITCH (0x1a4)
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#define RNPGBE_DMA_STATS_MAC_TO_DMA (0x1a8)
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#define RNPGBE_DMA_STATS_SWITCH_TO_DMA (0x1ac)
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#define RNPVF500_VEB_VFMPRC(i) (0x4018 + 0x100 * (i))
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#define VF_NUM_REG 0xa3000
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#define VF_NUM_REG_N10 0x75f000
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#define VF_NUM_REG_N500 (0xe000)
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/* 8bit: 7:vf_actiove 6:fun0/fun1 [5:0]:vf_num */
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#define VF_NUM(vfnum, fun) ((1 << 7) | (((fun) & 0x1) << 6) | ((vfnum) & 0x3f))
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#define PF_NUM(fun) (((fun) & 0x1) << 6)
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#define RING_VECTOR(n) (0x4000 + 0x04 * (n))
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static inline unsigned int p_rnpgbevf_rd_reg(void *reg)
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{
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unsigned int v = ioread32((void *)(reg));
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printk(KERN_DEBUG " rd-reg: %p ==> 0x%08x\n", reg, v);
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return v;
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}
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#define p_rnpgbevf_wr_reg(reg, val) \
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do { \
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printk(KERN_DEBUG " wr-reg: %p <== 0x%08x \t#%-4d %s\n", (reg), (val), \
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__LINE__, __FILE__); \
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iowrite32((val), (void *)(reg)); \
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} while (0)
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#ifdef IO_PRINT
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#define rnpgbevf_rd_reg(reg) p_rnpgbevf_rd_reg(reg)
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#define rnpgbevf_wr_reg(reg, val) p_rnpgbevf_wr_reg(reg, val)
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#else
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#define rnpgbevf_rd_reg(reg) readl((void *)(reg))
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#define rnpgbevf_wr_reg(reg, val) writel((val), (void *)(reg))
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#endif
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#ifdef CONFIG_RNPGBE_MBX_DEBUG
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#define mbx_rd32(hw, reg) p_rnpgbevf_rd_reg((hw)->hw_addr + (reg))
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#define mbx_wr32(hw, reg, val) p_rnpgbevf_wr_reg((hw)->hw_addr + (reg), (val))
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#else
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#define mbx_rd32(hw, reg) rnpgbevf_rd_reg((hw)->hw_addr + (reg))
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#define mbx_wr32(hw, reg, val) rnpgbevf_wr_reg((hw)->hw_addr + (reg), (val))
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#endif
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#define rd32(hw, off) rnpgbevf_rd_reg((hw)->hw_addr + (off))
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#define wr32(hw, off, val) rnpgbevf_wr_reg((hw)->hw_addr + (off), (val))
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#define ring_rd32(ring, off) rnpgbevf_rd_reg((ring)->ring_addr + (off))
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#define ring_wr32(ring, off, val) \
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rnpgbevf_wr_reg((ring)->ring_addr + (off), (val))
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#define pwr32(hw, reg, val) \
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do { \
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printk(KERN_DEBUG " wr-reg: %p <== 0x%08x \t#%-4d %s\n", \
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(hw)->hw_addr + (reg), (val), __LINE__, __FILE__); \
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iowrite32((val), (hw)->hw_addr + (reg)); \
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} while (0)
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#ifdef DEBUG
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#define hw_dbg(hw, fmt, args...) printk(KERN_DEBUG "hw-dbg : " fmt, ##args)
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#else
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#define hw_dbg(hw, fmt, args...)
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#endif
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#endif /* _RNPGBEVF_REGS_H_ */
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