114 lines
3.9 KiB
C
114 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2022 - 2023 Mucse Corporation. */
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#ifndef _RNP_PHY_H_
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#define _RNP_PHY_H_
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#include "rnp_type.h"
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#define RNP_I2C_EEPROM_DEV_ADDR 0xA0
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#define RNP_I2C_EEPROM_DEV_ADDR2 0xA2
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#define RNP_YT8531_PHY_SPEC_CTRL 0x10
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#define RNP_YT8531_PHY_SPEC_CTRL_FORCE_MDIX 0x0020
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#define RNP_YT8531_PHY_SPEC_CTRL_AUTO_MDI_MDIX 0x0060
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#define RNP_YT8531_PHY_SPEC_CTRL_MDIX_CFG_MASK 0x0060
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/* EEPROM byte offsets */
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#define SFF_MODULE_ID_OFFSET 0x00
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#define SFF_DIAG_SUPPORT_OFFSET 0x5c
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#define SFF_MODULE_ID_SFP 0x3
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#define SFF_MODULE_ID_QSFP 0xc
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#define SFF_MODULE_ID_QSFP_PLUS 0xd
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#define SFF_MODULE_ID_QSFP28 0x11
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/* Bitmasks */
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#define RNP_SFF_DA_PASSIVE_CABLE 0x4
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#define RNP_SFF_DA_ACTIVE_CABLE 0x8
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#define RNP_SFF_DA_SPEC_ACTIVE_LIMITING 0x4
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#define RNP_SFF_1GBASESX_CAPABLE 0x1
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#define RNP_SFF_1GBASELX_CAPABLE 0x2
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#define RNP_SFF_1GBASET_CAPABLE 0x8
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#define RNP_SFF_10GBASESR_CAPABLE 0x10
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#define RNP_SFF_10GBASELR_CAPABLE 0x20
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#define RNP_SFF_ADDRESSING_MODE 0x4
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#define RNP_I2C_EEPROM_READ_MASK 0x100
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#define RNP_I2C_EEPROM_STATUS_MASK 0x3
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#define RNP_I2C_EEPROM_STATUS_NO_OPERATION 0x0
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#define RNP_I2C_EEPROM_STATUS_PASS 0x1
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#define RNP_I2C_EEPROM_STATUS_FAIL 0x2
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#define RNP_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
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/* Flow control defines */
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#define RNP_TAF_SYM_PAUSE 0x400
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#define RNP_TAF_ASM_PAUSE 0x800
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/* Bit-shift macros */
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#define RNP_SFF_VENDOR_OUI_BYTE0_SHIFT 24
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#define RNP_SFF_VENDOR_OUI_BYTE1_SHIFT 16
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#define RNP_SFF_VENDOR_OUI_BYTE2_SHIFT 8
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/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
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#define RNP_SFF_VENDOR_OUI_TYCO 0x00407600
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#define RNP_SFF_VENDOR_OUI_FTL 0x00906500
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#define RNP_SFF_VENDOR_OUI_AVAGO 0x00176A00
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#define RNP_SFF_VENDOR_OUI_INTEL 0x001B2100
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/* I2C SDA and SCL timing parameters for standard mode */
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#define RNP_I2C_T_HD_STA 4
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#define RNP_I2C_T_LOW 5
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#define RNP_I2C_T_HIGH 4
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#define RNP_I2C_T_SU_STA 5
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#define RNP_I2C_T_HD_DATA 5
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#define RNP_I2C_T_SU_DATA 1
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#define RNP_I2C_T_RISE 1
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#define RNP_I2C_T_FALL 1
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#define RNP_I2C_T_SU_STO 4
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#define RNP_I2C_T_BUF 5
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#define RNP_TN_LASI_STATUS_REG 0x9005
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#define RNP_TN_LASI_STATUS_TEMP_ALARM 0x0008
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/* SFP+ SFF-8472 Compliance code */
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#define RNP_SFF_SFF_8472_UNSUP 0x00
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s32 rnp_init_phy_ops_generic(struct rnp_hw *hw);
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s32 rnp_identify_phy_generic(struct rnp_hw *hw);
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s32 rnp_reset_phy_generic(struct rnp_hw *hw);
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s32 rnp_read_phy_reg_generic(struct rnp_hw *hw, u32 reg_addr,
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u32 device_type, u16 *phy_data);
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s32 rnp_write_phy_reg_generic(struct rnp_hw *hw, u32 reg_addr,
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u32 device_type, u16 phy_data);
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s32 rnp_setup_phy_link_generic(struct rnp_hw *hw);
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s32 rnp_setup_phy_link_speed_generic(struct rnp_hw *hw,
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rnp_link_speed speed,
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bool autoneg_wait_to_complete);
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s32 rnp_get_copper_link_capabilities_generic(struct rnp_hw *hw,
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rnp_link_speed *speed,
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bool *autoneg);
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/* PHY specific */
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s32 rnp_check_phy_link_tnx(struct rnp_hw *hw, rnp_link_speed *speed,
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bool *link_up);
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s32 rnp_setup_phy_link_tnx(struct rnp_hw *hw);
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s32 rnp_get_phy_firmware_version_tnx(struct rnp_hw *hw,
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u16 *firmware_version);
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s32 rnp_get_phy_firmware_version_generic(struct rnp_hw *hw,
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u16 *firmware_version);
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s32 rnp_reset_phy_nl(struct rnp_hw *hw);
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s32 rnp_identify_sfp_module_generic(struct rnp_hw *hw);
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s32 rnp_get_sfp_init_sequence_offsets(struct rnp_hw *hw, u16 *list_offset,
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u16 *data_offset);
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s32 rnp_tn_check_overtemp(struct rnp_hw *hw);
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s32 rnp_read_i2c_byte_generic(struct rnp_hw *hw, u8 byte_offset,
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u8 dev_addr, u8 *data);
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s32 rnp_write_i2c_byte_generic(struct rnp_hw *hw, u8 byte_offset,
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u8 dev_addr, u8 data);
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s32 rnp_read_i2c_eeprom_generic(struct rnp_hw *hw, u8 byte_offset,
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u8 *eeprom_data);
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s32 rnp_read_i2c_sff8472_generic(struct rnp_hw *hw, u8 byte_offset,
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u8 *sff8472_data);
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s32 rnp_write_i2c_eeprom_generic(struct rnp_hw *hw, u8 byte_offset,
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u8 eeprom_data);
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#endif /* _RNP_PHY_H_ */
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