923 lines
20 KiB
C
923 lines
20 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2024 Huawei Technologies Co., Ltd */
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#ifndef MAG_MPU_CMD_DEFS_H
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#define MAG_MPU_CMD_DEFS_H
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#include "mpu_cmd_base_defs.h"
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/* serdes cmd struct define */
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#define CMD_ARRAY_BUF_SIZE 64
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#define SERDES_CMD_DATA_BUF_SIZE 512
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struct serdes_in_info {
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u32 chip_id : 16;
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u32 macro_id : 16;
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u32 start_sds_id : 16;
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u32 sds_num : 16;
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u32 cmd_type : 8; /* reserved for iotype */
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u32 sub_cmd : 8;
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u32 rw : 1; /* 0: read, 1: write */
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u32 rsvd : 15;
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u32 val;
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union {
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char field[CMD_ARRAY_BUF_SIZE];
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u32 addr;
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u8 *ex_param;
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};
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};
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struct serdes_out_info {
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u32 str_len; /* out_str length */
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u32 result_offset;
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u32 type; /* 0:data; 1:string */
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char out_str[SERDES_CMD_DATA_BUF_SIZE];
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};
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struct serdes_cmd_in {
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struct mgmt_msg_head head;
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struct serdes_in_info serdes_in;
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};
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struct serdes_cmd_out {
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struct mgmt_msg_head head;
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struct serdes_out_info serdes_out;
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};
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enum mag_cmd_port_speed {
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PORT_SPEED_NOT_SET = 0,
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PORT_SPEED_10MB = 1,
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PORT_SPEED_100MB = 2,
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PORT_SPEED_1GB = 3,
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PORT_SPEED_10GB = 4,
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PORT_SPEED_25GB = 5,
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PORT_SPEED_40GB = 6,
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PORT_SPEED_50GB = 7,
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PORT_SPEED_100GB = 8,
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PORT_SPEED_200GB = 9,
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PORT_SPEED_UNKNOWN
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};
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enum mag_cmd_port_an {
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PORT_AN_NOT_SET = 0,
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PORT_CFG_AN_ON = 1,
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PORT_CFG_AN_OFF = 2
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};
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enum mag_cmd_port_adapt {
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PORT_ADAPT_NOT_SET = 0,
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PORT_CFG_ADAPT_ON = 1,
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PORT_CFG_ADAPT_OFF = 2
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};
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enum mag_cmd_port_sriov {
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PORT_SRIOV_NOT_SET = 0,
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PORT_CFG_SRIOV_ON = 1,
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PORT_CFG_SRIOV_OFF = 2
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};
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enum mag_cmd_port_fec {
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PORT_FEC_NOT_SET = 0,
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PORT_FEC_RSFEC = 1,
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PORT_FEC_BASEFEC = 2,
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PORT_FEC_NOFEC = 3,
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PORT_FEC_LLRSFEC = 4,
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PORT_FEC_AUTO = 5
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};
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enum mag_cmd_port_lanes {
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PORT_LANES_NOT_SET = 0,
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PORT_LANES_X1 = 1,
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PORT_LANES_X2 = 2,
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PORT_LANES_X4 = 4,
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PORT_LANES_X8 = 8 /* reserved for future use */
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};
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enum mag_cmd_port_duplex {
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PORT_DUPLEX_HALF = 0,
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PORT_DUPLEX_FULL = 1
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};
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enum mag_cmd_wire_node {
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WIRE_NODE_UNDEF = 0,
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CABLE_10G = 1,
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FIBER_10G = 2,
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CABLE_25G = 3,
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FIBER_25G = 4,
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CABLE_40G = 5,
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FIBER_40G = 6,
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CABLE_50G = 7,
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FIBER_50G = 8,
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CABLE_100G = 9,
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FIBER_100G = 10,
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CABLE_200G = 11,
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FIBER_200G = 12,
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WIRE_NODE_NUM
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};
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enum mag_cmd_cnt_type {
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MAG_RX_RSFEC_DEC_CW_CNT = 0,
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MAG_RX_RSFEC_CORR_CW_CNT = 1,
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MAG_RX_RSFEC_UNCORR_CW_CNT = 2,
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MAG_RX_PCS_BER_CNT = 3,
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MAG_RX_PCS_ERR_BLOCK_CNT = 4,
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MAG_RX_PCS_E_BLK_CNT = 5,
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MAG_RX_PCS_DEC_ERR_BLK_CNT = 6,
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MAG_RX_PCS_LANE_BIP_ERR_CNT = 7,
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MAG_CNT_NUM
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};
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/* mag_cmd_set_port_cfg config bitmap */
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#define MAG_CMD_SET_SPEED 0x1
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#define MAG_CMD_SET_AUTONEG 0x2
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#define MAG_CMD_SET_FEC 0x4
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#define MAG_CMD_SET_LANES 0x8
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struct mag_cmd_set_port_cfg {
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struct mgmt_msg_head head;
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u8 port_id;
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u8 rsvd0[3];
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u32 config_bitmap;
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u8 speed;
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u8 autoneg;
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u8 fec;
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u8 lanes;
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u8 rsvd1[20];
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};
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/* mag supported/advertised link mode bitmap */
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enum mag_cmd_link_mode {
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LINK_MODE_GE = 0,
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LINK_MODE_10GE_BASE_R = 1,
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LINK_MODE_25GE_BASE_R = 2,
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LINK_MODE_40GE_BASE_R4 = 3,
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LINK_MODE_50GE_BASE_R = 4,
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LINK_MODE_50GE_BASE_R2 = 5,
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LINK_MODE_100GE_BASE_R = 6,
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LINK_MODE_100GE_BASE_R2 = 7,
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LINK_MODE_100GE_BASE_R4 = 8,
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LINK_MODE_200GE_BASE_R2 = 9,
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LINK_MODE_200GE_BASE_R4 = 10,
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LINK_MODE_MAX_NUMBERS,
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LINK_MODE_UNKNOWN = 0xFFFF
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};
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#define LINK_MODE_GE_BIT 0x1u
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#define LINK_MODE_10GE_BASE_R_BIT 0x2u
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#define LINK_MODE_25GE_BASE_R_BIT 0x4u
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#define LINK_MODE_40GE_BASE_R4_BIT 0x8u
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#define LINK_MODE_50GE_BASE_R_BIT 0x10u
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#define LINK_MODE_50GE_BASE_R2_BIT 0x20u
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#define LINK_MODE_100GE_BASE_R_BIT 0x40u
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#define LINK_MODE_100GE_BASE_R2_BIT 0x80u
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#define LINK_MODE_100GE_BASE_R4_BIT 0x100u
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#define LINK_MODE_200GE_BASE_R2_BIT 0x200u
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#define LINK_MODE_200GE_BASE_R4_BIT 0x400u
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#define CABLE_10GE_BASE_R_BIT LINK_MODE_10GE_BASE_R_BIT
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#define CABLE_25GE_BASE_R_BIT (LINK_MODE_25GE_BASE_R_BIT | LINK_MODE_10GE_BASE_R_BIT)
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#define CABLE_40GE_BASE_R4_BIT LINK_MODE_40GE_BASE_R4_BIT
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#define CABLE_50GE_BASE_R_BIT (LINK_MODE_50GE_BASE_R_BIT | LINK_MODE_25GE_BASE_R_BIT | \
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LINK_MODE_10GE_BASE_R_BIT)
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#define CABLE_50GE_BASE_R2_BIT LINK_MODE_50GE_BASE_R2_BIT
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#define CABLE_100GE_BASE_R2_BIT (LINK_MODE_100GE_BASE_R2_BIT | LINK_MODE_50GE_BASE_R2_BIT)
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#define CABLE_100GE_BASE_R4_BIT (LINK_MODE_100GE_BASE_R4_BIT | LINK_MODE_40GE_BASE_R4_BIT)
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#define CABLE_200GE_BASE_R4_BIT (LINK_MODE_200GE_BASE_R4_BIT | LINK_MODE_100GE_BASE_R4_BIT | \
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LINK_MODE_40GE_BASE_R4_BIT)
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struct mag_cmd_get_port_info {
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struct mgmt_msg_head head;
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u8 port_id;
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u8 rsvd0[3];
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u8 wire_type;
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u8 an_support;
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u8 an_en;
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u8 duplex;
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u8 speed;
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u8 fec;
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u8 lanes;
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u8 rsvd1;
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u32 supported_mode;
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u32 advertised_mode;
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u8 rsvd2[8];
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};
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#define MAG_CMD_OPCODE_GET 0
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#define MAG_CMD_OPCODE_SET 1
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struct mag_cmd_set_port_adapt {
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struct mgmt_msg_head head;
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u8 port_id;
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u8 opcode; /* 0:get adapt info 1:set adapt */
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u8 enable;
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u8 rsvd0;
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u32 speed_mode;
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u32 rsvd1[3];
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};
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#define MAG_CMD_LP_MODE_SDS_S_TX2RX 1
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#define MAG_CMD_LP_MODE_SDS_P_RX2TX 2
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#define MAG_CMD_LP_MODE_SDS_P_TX2RX 3
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#define MAG_CMD_LP_MODE_MAC_RX2TX 4
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#define MAG_CMD_LP_MODE_MAC_TX2RX 5
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#define MAG_CMD_LP_MODE_TXDP2RXDP 6
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struct mag_cmd_cfg_loopback_mode {
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struct mgmt_msg_head head;
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u8 port_id;
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u8 opcode; /* 0:get loopback mode 1:set loopback mode */
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u8 lp_mode;
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u8 lp_en; /* 0:disable 1:enable */
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u32 rsvd0[2];
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};
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#define MAG_CMD_PORT_DISABLE 0x0
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#define MAG_CMD_TX_ENABLE 0x1
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#define MAG_CMD_RX_ENABLE 0x2
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/* the physical port is disable only when all pf of the port are set to down,
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* if any pf is enable, the port is enable
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*/
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struct mag_cmd_set_port_enable {
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struct mgmt_msg_head head;
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u16 function_id; /* function_id should not more than the max support pf_id(32) */
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u16 rsvd0;
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u8 state; /* bitmap bit0:tx_en bit1:rx_en */
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u8 rsvd1[3];
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};
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struct mag_cmd_get_port_enable {
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struct mgmt_msg_head head;
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u8 port;
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u8 state; /* bitmap bit0:tx_en bit1:rx_en */
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u8 rsvd0[2];
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};
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#define PMA_FOLLOW_DEFAULT 0x0
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#define PMA_FOLLOW_ENABLE 0x1
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#define PMA_FOLLOW_DISABLE 0x2
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#define PMA_FOLLOW_GET 0x4
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/* the physical port disable link follow only when all pf of the port are set to follow disable */
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struct mag_cmd_set_link_follow {
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struct mgmt_msg_head head;
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u16 function_id; /* function_id should not more than the max support pf_id(32) */
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u16 rsvd0;
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u8 follow;
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u8 rsvd1[3];
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};
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/* firmware also use this cmd report link event to driver */
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struct mag_cmd_get_link_status {
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struct mgmt_msg_head head;
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u8 port_id;
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u8 status; /* 0:link down 1:link up */
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u8 rsvd0[2];
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};
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/* firmware also use this cmd report bond event to driver */
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struct mag_cmd_get_bond_status {
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struct mgmt_msg_head head;
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u8 status; /* 0:bond down 1:bond up */
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u8 rsvd0[3];
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};
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struct mag_cmd_set_pma_enable {
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struct mgmt_msg_head head;
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u16 function_id; /* function_id should not more than the max support pf_id(32) */
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u16 enable;
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};
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struct mag_cmd_cfg_an_type {
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struct mgmt_msg_head head;
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u8 port_id;
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u8 opcode; /* 0:get an type 1:set an type */
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u8 rsvd0[2];
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u32 an_type; /* 0:ieee 1:25G/50 eth consortium */
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};
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struct mag_cmd_get_link_time {
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struct mgmt_msg_head head;
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u8 port_id;
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u8 rsvd0[3];
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u32 link_up_begin;
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u32 link_up_end;
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u32 link_down_begin;
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u32 link_down_end;
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};
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struct mag_cmd_cfg_fec_mode {
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struct mgmt_msg_head head;
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u8 port_id;
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u8 opcode; /* 0:get fec mode 1:set fec mode */
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u8 fec;
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u8 rsvd0;
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};
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/* speed */
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#define PANGEA_ADAPT_10G_BITMAP 0xd
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#define PANGEA_ADAPT_25G_BITMAP 0x72
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#define PANGEA_ADAPT_40G_BITMAP 0x680
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#define PANGEA_ADAPT_100G_BITMAP 0x1900
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/* speed and fec */
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#define PANGEA_10G_NO_BITMAP 0x8
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#define PANGEA_10G_BASE_BITMAP 0x4
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#define PANGEA_25G_NO_BITMAP 0x10
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#define PANGEA_25G_BASE_BITMAP 0x20
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#define PANGEA_25G_RS_BITMAP 0x40
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#define PANGEA_40G_NO_BITMAP 0x400
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#define PANGEA_40G_BASE_BITMAP 0x200
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#define PANGEA_100G_NO_BITMAP 0x800
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#define PANGEA_100G_RS_BITMAP 0x1000
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/* adapt or fec */
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#define PANGEA_ADAPT_ADAPT_BITMAP 0x183
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#define PANGEA_ADAPT_NO_BITMAP 0xc18
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#define PANGEA_ADAPT_BASE_BITMAP 0x224
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#define PANGEA_ADAPT_RS_BITMAP 0x1040
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/* default cfg */
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#define PANGEA_ADAPT_CFG_10G_CR 0x200d
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#define PANGEA_ADAPT_CFG_10G_SRLR 0xd
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#define PANGEA_ADAPT_CFG_25G_CR 0x207f
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#define PANGEA_ADAPT_CFG_25G_SRLR 0x72
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#define PANGEA_ADAPT_CFG_40G_CR4 0x2680
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#define PANGEA_ADAPT_CFG_40G_SRLR4 0x680
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#define PANGEA_ADAPT_CFG_100G_CR4 0x3f80
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#define PANGEA_ADAPT_CFG_100G_SRLR4 0x1900
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union pangea_adapt_bitmap_u {
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struct {
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u32 adapt_10g : 1; /* [0] adapt_10g */
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u32 adapt_25g : 1; /* [1] adapt_25g */
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u32 base_10g : 1; /* [2] base_10g */
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u32 no_10g : 1; /* [3] no_10g */
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u32 no_25g : 1; /* [4] no_25g */
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u32 base_25g : 1; /* [5] base_25g */
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u32 rs_25g : 1; /* [6] rs_25g */
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u32 adapt_40g : 1; /* [7] adapt_40g */
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u32 adapt_100g : 1; /* [8] adapt_100g */
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u32 base_40g : 1; /* [9] base_40g */
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u32 no_40g : 1; /* [10] no_40g */
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u32 no_100g : 1; /* [11] no_100g */
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u32 rs_100g : 1; /* [12] rs_100g */
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u32 auto_neg : 1; /* [13] auto_neg */
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u32 rsvd0 : 18; /* [31:14] reserved */
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} bits;
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u32 value;
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};
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#define PANGEA_ADAPT_GET 0x0
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#define PANGEA_ADAPT_SET 0x1
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struct mag_cmd_set_pangea_adapt {
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struct mgmt_msg_head head;
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u16 port_id;
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u8 opcode; /* 0:get adapt info 1:cfg adapt info */
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u8 wire_type;
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union pangea_adapt_bitmap_u cfg_bitmap;
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union pangea_adapt_bitmap_u cur_bitmap;
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u32 rsvd1[3];
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};
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struct mag_cmd_cfg_bios_link_cfg {
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struct mgmt_msg_head head;
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u8 port_id;
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u8 opcode; /* 0:get bios link info 1:set bios link cfg */
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u8 clear;
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u8 rsvd0;
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u32 wire_type;
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u8 an_en;
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u8 speed;
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u8 fec;
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u8 rsvd1;
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u32 speed_mode;
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u32 rsvd2[3];
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};
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struct mag_cmd_restore_link_cfg {
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struct mgmt_msg_head head;
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u8 port_id;
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u8 rsvd[7];
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};
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struct mag_cmd_activate_bios_link_cfg {
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struct mgmt_msg_head head;
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u32 rsvd[8];
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};
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/* led type */
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enum mag_led_type {
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MAG_CMD_LED_TYPE_ALARM = 0x0,
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MAG_CMD_LED_TYPE_LOW_SPEED = 0x1,
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MAG_CMD_LED_TYPE_HIGH_SPEED = 0x2
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};
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/* led mode */
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enum mag_led_mode {
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MAG_CMD_LED_MODE_DEFAULT = 0x0,
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MAG_CMD_LED_MODE_FORCE_ON = 0x1,
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MAG_CMD_LED_MODE_FORCE_OFF = 0x2,
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MAG_CMD_LED_MODE_FORCE_BLINK_1HZ = 0x3,
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MAG_CMD_LED_MODE_FORCE_BLINK_2HZ = 0x4,
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MAG_CMD_LED_MODE_FORCE_BLINK_4HZ = 0x5,
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MAG_CMD_LED_MODE_1HZ = 0x6,
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MAG_CMD_LED_MODE_2HZ = 0x7,
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MAG_CMD_LED_MODE_4HZ = 0x8
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};
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/* the led is report alarm when any pf of the port is alram */
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struct mag_cmd_set_led_cfg {
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struct mgmt_msg_head head;
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u16 function_id;
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u8 type;
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u8 mode;
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};
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#define XSFP_INFO_MAX_SIZE 640
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/* xsfp wire type, refer to cmis protocol definition */
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enum mag_wire_type {
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MAG_CMD_WIRE_TYPE_UNKNOWN = 0x0,
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MAG_CMD_WIRE_TYPE_MM = 0x1,
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MAG_CMD_WIRE_TYPE_SM = 0x2,
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MAG_CMD_WIRE_TYPE_COPPER = 0x3,
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MAG_CMD_WIRE_TYPE_ACC = 0x4,
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MAG_CMD_WIRE_TYPE_BASET = 0x5,
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MAG_CMD_WIRE_TYPE_AOC = 0x40,
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MAG_CMD_WIRE_TYPE_ELECTRIC = 0x41,
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MAG_CMD_WIRE_TYPE_BACKPLANE = 0x42
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};
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struct mag_cmd_get_xsfp_info {
|
|
struct mgmt_msg_head head;
|
|
|
|
u8 port_id;
|
|
u8 wire_type;
|
|
u16 out_len;
|
|
u32 rsvd;
|
|
u8 sfp_info[XSFP_INFO_MAX_SIZE];
|
|
};
|
|
|
|
#define MAG_CMD_XSFP_DISABLE 0x0
|
|
#define MAG_CMD_XSFP_ENABLE 0x1
|
|
/* the sfp is disable only when all pf of the port are set sfp down,
|
|
* if any pf is enable, the sfp is enable
|
|
*/
|
|
struct mag_cmd_set_xsfp_enable {
|
|
struct mgmt_msg_head head;
|
|
|
|
u32 port_id;
|
|
u32 status; /* 0:on 1:off */
|
|
};
|
|
|
|
#define MAG_CMD_XSFP_PRESENT 0x0
|
|
#define MAG_CMD_XSFP_ABSENT 0x1
|
|
struct mag_cmd_get_xsfp_present {
|
|
struct mgmt_msg_head head;
|
|
|
|
u8 port_id;
|
|
u8 abs_status; /* 0:present, 1:absent */
|
|
u8 rsvd[2];
|
|
};
|
|
|
|
#define MAG_CMD_XSFP_READ 0x0
|
|
#define MAG_CMD_XSFP_WRITE 0x1
|
|
struct mag_cmd_set_xsfp_rw {
|
|
struct mgmt_msg_head head;
|
|
|
|
u8 port_id;
|
|
u8 operation; /* 0: read; 1: write */
|
|
u8 value;
|
|
u8 rsvd0;
|
|
u32 devaddr;
|
|
u32 offset;
|
|
u32 rsvd1;
|
|
};
|
|
|
|
struct mag_cmd_cfg_xsfp_temperature {
|
|
struct mgmt_msg_head head;
|
|
|
|
u8 opcode; /* 0:read 1:write */
|
|
u8 rsvd0[3];
|
|
s32 max_temp;
|
|
s32 min_temp;
|
|
};
|
|
|
|
struct mag_cmd_get_xsfp_temperature {
|
|
struct mgmt_msg_head head;
|
|
|
|
s16 sfp_temp[8];
|
|
u8 rsvd[32];
|
|
s32 max_temp;
|
|
s32 min_temp;
|
|
};
|
|
|
|
/* xsfp plug event */
|
|
struct mag_cmd_wire_event {
|
|
struct mgmt_msg_head head;
|
|
|
|
u8 port_id;
|
|
u8 status; /* 0:present, 1:absent */
|
|
u8 rsvd[2];
|
|
};
|
|
|
|
/* link err type definition */
|
|
#define MAG_CMD_ERR_XSFP_UNKNOWN 0x0
|
|
struct mag_cmd_link_err_event {
|
|
struct mgmt_msg_head head;
|
|
|
|
u8 port_id;
|
|
u8 link_err_type;
|
|
u8 rsvd[2];
|
|
};
|
|
|
|
#define MAG_PARAM_TYPE_DEFAULT_CFG 0x0
|
|
#define MAG_PARAM_TYPE_BIOS_CFG 0x1
|
|
#define MAG_PARAM_TYPE_TOOL_CFG 0x2
|
|
#define MAG_PARAM_TYPE_FINAL_CFG 0x3
|
|
#define MAG_PARAM_TYPE_WIRE_INFO 0x4
|
|
#define MAG_PARAM_TYPE_ADAPT_INFO 0x5
|
|
#define MAG_PARAM_TYPE_MAX_CNT 0x6
|
|
struct param_head {
|
|
u8 valid_len;
|
|
u8 info_type;
|
|
u8 rsvd[2];
|
|
};
|
|
|
|
struct mag_port_link_param {
|
|
struct param_head head;
|
|
|
|
u8 an;
|
|
u8 fec;
|
|
u8 speed;
|
|
u8 rsvd0;
|
|
|
|
u32 used;
|
|
u32 an_fec_ability;
|
|
u32 an_speed_ability;
|
|
u32 an_pause_ability;
|
|
};
|
|
|
|
struct mag_port_wire_info {
|
|
struct param_head head;
|
|
|
|
u8 status;
|
|
u8 rsvd0[3];
|
|
|
|
u8 wire_type;
|
|
u8 default_fec;
|
|
u8 speed;
|
|
u8 rsvd1;
|
|
u32 speed_ability;
|
|
};
|
|
|
|
struct mag_port_adapt_info {
|
|
struct param_head head;
|
|
|
|
u32 adapt_en;
|
|
u32 flash_adapt;
|
|
u32 rsvd0[2];
|
|
|
|
u32 wire_node;
|
|
u32 an_en;
|
|
u32 speed;
|
|
u32 fec;
|
|
};
|
|
|
|
struct mag_port_param_info {
|
|
u8 parameter_cnt;
|
|
u8 lane_id;
|
|
u8 lane_num;
|
|
u8 rsvd0;
|
|
|
|
struct mag_port_link_param default_cfg;
|
|
struct mag_port_link_param bios_cfg;
|
|
struct mag_port_link_param tool_cfg;
|
|
struct mag_port_link_param final_cfg;
|
|
|
|
struct mag_port_wire_info wire_info;
|
|
struct mag_port_adapt_info adapt_info;
|
|
};
|
|
|
|
#define XSFP_VENDOR_NAME_LEN 16
|
|
struct mag_cmd_event_port_info {
|
|
struct mgmt_msg_head head;
|
|
|
|
u8 port_id;
|
|
u8 event_type;
|
|
u8 rsvd0[2];
|
|
|
|
u8 vendor_name[XSFP_VENDOR_NAME_LEN];
|
|
u32 port_type; /* fiber / copper */
|
|
u32 port_sub_type; /* sr / lr */
|
|
u32 cable_length; /* 1/3/5m */
|
|
u8 cable_temp; /* temp */
|
|
u8 max_speed; /* Maximum rate of an optical module */
|
|
u8 sfp_type; /* sfp/qsfp */
|
|
u8 rsvd1;
|
|
u32 power[4]; /* Optical Power */
|
|
|
|
u8 an_state;
|
|
u8 fec;
|
|
u16 speed;
|
|
|
|
u8 gpio_insert; /* 0:present 1:absent */
|
|
u8 alos;
|
|
u8 rx_los;
|
|
u8 pma_ctrl;
|
|
|
|
u32 pma_fifo_reg;
|
|
u32 pma_signal_ok_reg;
|
|
u32 pcs_64_66b_reg;
|
|
u32 rf_lf;
|
|
u8 pcs_link;
|
|
u8 pcs_mac_link;
|
|
u8 tx_enable;
|
|
u8 rx_enable;
|
|
u32 pcs_err_cnt;
|
|
|
|
u8 eq_data[38];
|
|
u8 rsvd2[2];
|
|
|
|
u32 his_link_machine_state;
|
|
u32 cur_link_machine_state;
|
|
u8 his_machine_state_data[128];
|
|
u8 cur_machine_state_data[128];
|
|
u8 his_machine_state_length;
|
|
u8 cur_machine_state_length;
|
|
|
|
struct mag_port_param_info param_info;
|
|
u8 rsvd3[360];
|
|
};
|
|
|
|
struct mag_cmd_port_stats {
|
|
u64 mac_tx_fragment_pkt_num;
|
|
u64 mac_tx_undersize_pkt_num;
|
|
u64 mac_tx_undermin_pkt_num;
|
|
u64 mac_tx_64_oct_pkt_num;
|
|
u64 mac_tx_65_127_oct_pkt_num;
|
|
u64 mac_tx_128_255_oct_pkt_num;
|
|
u64 mac_tx_256_511_oct_pkt_num;
|
|
u64 mac_tx_512_1023_oct_pkt_num;
|
|
u64 mac_tx_1024_1518_oct_pkt_num;
|
|
u64 mac_tx_1519_2047_oct_pkt_num;
|
|
u64 mac_tx_2048_4095_oct_pkt_num;
|
|
u64 mac_tx_4096_8191_oct_pkt_num;
|
|
u64 mac_tx_8192_9216_oct_pkt_num;
|
|
u64 mac_tx_9217_12287_oct_pkt_num;
|
|
u64 mac_tx_12288_16383_oct_pkt_num;
|
|
u64 mac_tx_1519_max_bad_pkt_num;
|
|
u64 mac_tx_1519_max_good_pkt_num;
|
|
u64 mac_tx_oversize_pkt_num;
|
|
u64 mac_tx_jabber_pkt_num;
|
|
u64 mac_tx_bad_pkt_num;
|
|
u64 mac_tx_bad_oct_num;
|
|
u64 mac_tx_good_pkt_num;
|
|
u64 mac_tx_good_oct_num;
|
|
u64 mac_tx_total_pkt_num;
|
|
u64 mac_tx_total_oct_num;
|
|
u64 mac_tx_uni_pkt_num;
|
|
u64 mac_tx_multi_pkt_num;
|
|
u64 mac_tx_broad_pkt_num;
|
|
u64 mac_tx_pause_num;
|
|
u64 mac_tx_pfc_pkt_num;
|
|
u64 mac_tx_pfc_pri0_pkt_num;
|
|
u64 mac_tx_pfc_pri1_pkt_num;
|
|
u64 mac_tx_pfc_pri2_pkt_num;
|
|
u64 mac_tx_pfc_pri3_pkt_num;
|
|
u64 mac_tx_pfc_pri4_pkt_num;
|
|
u64 mac_tx_pfc_pri5_pkt_num;
|
|
u64 mac_tx_pfc_pri6_pkt_num;
|
|
u64 mac_tx_pfc_pri7_pkt_num;
|
|
u64 mac_tx_control_pkt_num;
|
|
u64 mac_tx_err_all_pkt_num;
|
|
u64 mac_tx_from_app_good_pkt_num;
|
|
u64 mac_tx_from_app_bad_pkt_num;
|
|
|
|
u64 mac_rx_fragment_pkt_num;
|
|
u64 mac_rx_undersize_pkt_num;
|
|
u64 mac_rx_undermin_pkt_num;
|
|
u64 mac_rx_64_oct_pkt_num;
|
|
u64 mac_rx_65_127_oct_pkt_num;
|
|
u64 mac_rx_128_255_oct_pkt_num;
|
|
u64 mac_rx_256_511_oct_pkt_num;
|
|
u64 mac_rx_512_1023_oct_pkt_num;
|
|
u64 mac_rx_1024_1518_oct_pkt_num;
|
|
u64 mac_rx_1519_2047_oct_pkt_num;
|
|
u64 mac_rx_2048_4095_oct_pkt_num;
|
|
u64 mac_rx_4096_8191_oct_pkt_num;
|
|
u64 mac_rx_8192_9216_oct_pkt_num;
|
|
u64 mac_rx_9217_12287_oct_pkt_num;
|
|
u64 mac_rx_12288_16383_oct_pkt_num;
|
|
u64 mac_rx_1519_max_bad_pkt_num;
|
|
u64 mac_rx_1519_max_good_pkt_num;
|
|
u64 mac_rx_oversize_pkt_num;
|
|
u64 mac_rx_jabber_pkt_num;
|
|
u64 mac_rx_bad_pkt_num;
|
|
u64 mac_rx_bad_oct_num;
|
|
u64 mac_rx_good_pkt_num;
|
|
u64 mac_rx_good_oct_num;
|
|
u64 mac_rx_total_pkt_num;
|
|
u64 mac_rx_total_oct_num;
|
|
u64 mac_rx_uni_pkt_num;
|
|
u64 mac_rx_multi_pkt_num;
|
|
u64 mac_rx_broad_pkt_num;
|
|
u64 mac_rx_pause_num;
|
|
u64 mac_rx_pfc_pkt_num;
|
|
u64 mac_rx_pfc_pri0_pkt_num;
|
|
u64 mac_rx_pfc_pri1_pkt_num;
|
|
u64 mac_rx_pfc_pri2_pkt_num;
|
|
u64 mac_rx_pfc_pri3_pkt_num;
|
|
u64 mac_rx_pfc_pri4_pkt_num;
|
|
u64 mac_rx_pfc_pri5_pkt_num;
|
|
u64 mac_rx_pfc_pri6_pkt_num;
|
|
u64 mac_rx_pfc_pri7_pkt_num;
|
|
u64 mac_rx_control_pkt_num;
|
|
u64 mac_rx_sym_err_pkt_num;
|
|
u64 mac_rx_fcs_err_pkt_num;
|
|
u64 mac_rx_send_app_good_pkt_num;
|
|
u64 mac_rx_send_app_bad_pkt_num;
|
|
u64 mac_rx_unfilter_pkt_num;
|
|
};
|
|
|
|
struct mag_port_stats {
|
|
u64 tx_frag_pkts_port;
|
|
u64 tx_under_frame_pkts_port;
|
|
u64 tx_under_min_pkts_port;
|
|
u64 tx_64_oct_pkts_port;
|
|
u64 tx_127_oct_pkts_port;
|
|
u64 tx_255_oct_pkts_port;
|
|
u64 tx_511_oct_pkts_port;
|
|
u64 tx_1023_oct_pkts_port;
|
|
u64 tx_1518_oct_pkts_port;
|
|
u64 tx_2047_oct_pkts_port;
|
|
u64 tx_4095_oct_pkts_port;
|
|
u64 tx_8191_oct_pkts_port;
|
|
u64 tx_9216_oct_pkts_port;
|
|
u64 tx_12287_oct_pkts_port;
|
|
u64 tx_16383_oct_pkts_port;
|
|
u64 tx_1519_to_max_bad_pkts_port;
|
|
u64 tx_1519_to_max_good_pkts_port;
|
|
u64 tx_oversize_pkts_port;
|
|
u64 tx_jabber_pkts_port;
|
|
u64 tx_bad_pkts_port;
|
|
u64 tx_bad_octs_port;
|
|
u64 tx_good_pkts_port;
|
|
u64 tx_good_octs_port;
|
|
u64 tx_total_pkts_port;
|
|
u64 tx_total_octs_port;
|
|
u64 tx_unicast_pkts_port;
|
|
u64 tx_multicast_pkts_port;
|
|
u64 tx_broadcast_pkts_port;
|
|
u64 tx_pause_pkts_port;
|
|
u64 tx_pfc_pkts_port;
|
|
u64 tx_pri_0_pkts_port;
|
|
u64 tx_pri_1_pkts_port;
|
|
u64 tx_pri_2_pkts_port;
|
|
u64 tx_pri_3_pkts_port;
|
|
u64 tx_pri_4_pkts_port;
|
|
u64 tx_pri_5_pkts_port;
|
|
u64 tx_pri_6_pkts_port;
|
|
u64 tx_pri_7_pkts_port;
|
|
u64 tx_mac_control_pkts_port;
|
|
u64 tx_y1731_pkts_port;
|
|
u64 tx_1588_pkts_port;
|
|
u64 tx_error_pkts_port;
|
|
u64 tx_app_good_pkts_port;
|
|
u64 tx_app_bad_pkts_port;
|
|
u64 rx_frag_pkts_port;
|
|
u64 rx_under_frame_pkts_port;
|
|
u64 rx_under_min_pkts_port;
|
|
u64 rx_64_oct_pkts_port;
|
|
u64 rx_127_oct_pkts_port;
|
|
u64 rx_255_oct_pkts_port;
|
|
u64 rx_511_oct_pkts_port;
|
|
u64 rx_1023_oct_pkts_port;
|
|
u64 rx_1518_oct_pkts_port;
|
|
u64 rx_2047_oct_pkts_port;
|
|
u64 rx_4095_oct_pkts_port;
|
|
u64 rx_8191_oct_pkts_port;
|
|
u64 rx_9216_oct_pkts_port;
|
|
u64 rx_12287_oct_pkts_port;
|
|
u64 rx_16383_oct_pkts_port;
|
|
u64 rx_1519_to_max_bad_pkts_port;
|
|
u64 rx_1519_to_max_good_pkts_port;
|
|
u64 rx_oversize_pkts_port;
|
|
u64 rx_jabber_pkts_port;
|
|
u64 rx_bad_pkts_port;
|
|
u64 rx_bad_octs_port;
|
|
u64 rx_good_pkts_port;
|
|
u64 rx_good_octs_port;
|
|
u64 rx_total_pkts_port;
|
|
u64 rx_total_octs_port;
|
|
u64 rx_unicast_pkts_port;
|
|
u64 rx_multicast_pkts_port;
|
|
u64 rx_broadcast_pkts_port;
|
|
u64 rx_pause_pkts_port;
|
|
u64 rx_pfc_pkts_port;
|
|
u64 rx_pri_0_pkts_port;
|
|
u64 rx_pri_1_pkts_port;
|
|
u64 rx_pri_2_pkts_port;
|
|
u64 rx_pri_3_pkts_port;
|
|
u64 rx_pri_4_pkts_port;
|
|
u64 rx_pri_5_pkts_port;
|
|
u64 rx_pri_6_pkts_port;
|
|
u64 rx_pri_7_pkts_port;
|
|
u64 rx_mac_control_pkts_port;
|
|
u64 rx_y1731_pkts_port;
|
|
u64 rx_sym_err_pkts_port;
|
|
u64 rx_fcs_err_pkts_port;
|
|
u64 rx_app_good_pkts_port;
|
|
u64 rx_app_bad_pkts_port;
|
|
u64 rx_unfilter_pkts_port;
|
|
};
|
|
|
|
struct mag_cmd_port_stats_info {
|
|
struct mgmt_msg_head head;
|
|
|
|
u8 port_id;
|
|
u8 rsvd0[3];
|
|
};
|
|
|
|
struct mag_cmd_get_port_stat {
|
|
struct mgmt_msg_head head;
|
|
|
|
struct mag_cmd_port_stats counter;
|
|
u64 rsvd1[15];
|
|
};
|
|
|
|
struct mag_cmd_get_pcs_err_cnt {
|
|
struct mgmt_msg_head head;
|
|
|
|
u8 port_id;
|
|
u8 rsvd0[3];
|
|
|
|
u32 pcs_err_cnt;
|
|
};
|
|
|
|
struct mag_cmd_get_mag_cnt {
|
|
struct mgmt_msg_head head;
|
|
|
|
u8 port_id;
|
|
u8 len;
|
|
u8 rsvd0[2];
|
|
|
|
u32 mag_csr[128];
|
|
};
|
|
|
|
struct mag_cmd_dump_antrain_info {
|
|
struct mgmt_msg_head head;
|
|
|
|
u8 port_id;
|
|
u8 len;
|
|
u8 rsvd0[2];
|
|
|
|
u32 antrain_csr[256];
|
|
};
|
|
|
|
#define MAG_SFP_PORT_NUM 24
|
|
struct mag_cmd_sfp_temp_in_info {
|
|
struct mgmt_msg_head head; /* 8B */
|
|
u8 opt_type; /* 0:read operation 1:cfg operation */
|
|
u8 rsv[3];
|
|
s32 max_temp; /* Chip optical module threshold */
|
|
s32 min_temp; /* Chip optical module threshold */
|
|
};
|
|
|
|
struct mag_cmd_sfp_temp_out_info {
|
|
struct mgmt_msg_head head; /* 8B */
|
|
s16 sfp_temp_data[MAG_SFP_PORT_NUM]; /* Temperature read */
|
|
s32 max_temp; /* Chip optical module threshold */
|
|
s32 min_temp; /* Chip optical module threshold */
|
|
};
|
|
|
|
#endif
|