156 lines
3.4 KiB
C
156 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2021 Huawei Technologies Co., Ltd */
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#ifndef HINIC3_RX_H
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#define HINIC3_RX_H
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#include <linux/types.h>
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#include <linux/device.h>
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#include <linux/mm_types.h>
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#include <linux/netdevice.h>
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#include <linux/skbuff.h>
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#include <linux/u64_stats_sync.h>
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#include "hinic3_nic_io.h"
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#include "hinic3_nic_qp.h"
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#include "hinic3_nic_dev.h"
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/* rx cqe checksum err */
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#define HINIC3_RX_CSUM_IP_CSUM_ERR BIT(0)
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#define HINIC3_RX_CSUM_TCP_CSUM_ERR BIT(1)
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#define HINIC3_RX_CSUM_UDP_CSUM_ERR BIT(2)
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#define HINIC3_RX_CSUM_IGMP_CSUM_ERR BIT(3)
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#define HINIC3_RX_CSUM_ICMPV4_CSUM_ERR BIT(4)
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#define HINIC3_RX_CSUM_ICMPV6_CSUM_ERR BIT(5)
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#define HINIC3_RX_CSUM_SCTP_CRC_ERR BIT(6)
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#define HINIC3_RX_CSUM_HW_CHECK_NONE BIT(7)
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#define HINIC3_RX_CSUM_IPSU_OTHER_ERR BIT(8)
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#define HINIC3_HEADER_DATA_UNIT 2
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struct hinic3_rxq_stats {
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u64 packets;
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u64 bytes;
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u64 errors;
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u64 csum_errors;
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u64 other_errors;
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u64 dropped;
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u64 xdp_dropped;
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u64 rx_buf_empty;
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u64 alloc_skb_err;
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u64 alloc_rx_buf_err;
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u64 xdp_large_pkt;
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u64 restore_drop_sge;
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u64 rsvd2;
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#ifdef HAVE_NDO_GET_STATS64
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struct u64_stats_sync syncp;
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#else
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struct u64_stats_sync_empty syncp;
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#endif
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};
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struct hinic3_rx_info {
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dma_addr_t buf_dma_addr;
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struct hinic3_rq_cqe *cqe;
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dma_addr_t cqe_dma;
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struct page *page;
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u32 page_offset;
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u32 rsvd1;
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struct hinic3_rq_wqe *rq_wqe;
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struct sk_buff *saved_skb;
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u32 skb_len;
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u32 rsvd2;
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};
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struct hinic3_rxq {
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struct net_device *netdev;
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u16 q_id;
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u16 rsvd1;
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u32 q_depth;
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u32 q_mask;
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u16 buf_len;
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u16 rsvd2;
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u32 rx_buff_shift;
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u32 dma_rx_buff_size;
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struct hinic3_rxq_stats rxq_stats;
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u32 cons_idx;
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u32 delta;
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u32 irq_id;
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u16 msix_entry_idx;
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u16 rsvd3;
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struct hinic3_rx_info *rx_info;
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struct hinic3_io_queue *rq;
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#ifdef HAVE_XDP_SUPPORT
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struct bpf_prog *xdp_prog;
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#endif
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struct hinic3_irq *irq_cfg;
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u16 next_to_alloc;
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u16 next_to_update;
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struct device *dev; /* device for DMA mapping */
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unsigned long status;
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dma_addr_t cqe_start_paddr;
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void *cqe_start_vaddr;
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u64 last_moder_packets;
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u64 last_moder_bytes;
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u8 last_coalesc_timer_cfg;
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u8 last_pending_limt;
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u16 restore_buf_num;
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u32 rsvd5;
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u64 rsvd6;
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u32 last_sw_pi;
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u32 last_sw_ci;
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u32 last_hw_ci;
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u8 rx_check_err_cnt;
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u8 rxq_print_times;
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u16 restore_pi;
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u64 last_packets;
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} ____cacheline_aligned;
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struct hinic3_dyna_rxq_res {
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u16 next_to_alloc;
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struct hinic3_rx_info *rx_info;
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dma_addr_t cqe_start_paddr;
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void *cqe_start_vaddr;
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};
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int hinic3_alloc_rxqs(struct net_device *netdev);
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void hinic3_free_rxqs(struct net_device *netdev);
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int hinic3_alloc_rxqs_res(struct hinic3_nic_dev *nic_dev, u16 num_rq,
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u32 rq_depth, struct hinic3_dyna_rxq_res *rxqs_res);
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void hinic3_free_rxqs_res(struct hinic3_nic_dev *nic_dev, u16 num_rq,
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u32 rq_depth, struct hinic3_dyna_rxq_res *rxqs_res);
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int hinic3_configure_rxqs(struct hinic3_nic_dev *nic_dev, u16 num_rq,
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u32 rq_depth, struct hinic3_dyna_rxq_res *rxqs_res);
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int hinic3_rx_configure(struct net_device *netdev, u8 dcb_en);
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void hinic3_rx_remove_configure(struct net_device *netdev);
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int hinic3_rx_poll(struct hinic3_rxq *rxq, int budget);
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void hinic3_rxq_get_stats(struct hinic3_rxq *rxq,
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struct hinic3_rxq_stats *stats);
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void hinic3_rxq_clean_stats(struct hinic3_rxq_stats *rxq_stats);
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void hinic3_rxq_check_work_handler(struct work_struct *work);
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#endif
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