527 lines
12 KiB
C
527 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0*/
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/* Huawei HiNIC PCI Express Linux driver
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* Copyright(c) 2017 Huawei Technologies Co., Ltd
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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*/
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#ifndef __CFG_MGT_H__
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#define __CFG_MGT_H__
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#include "hinic_ctx_def.h"
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enum {
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CFG_FREE = 0,
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CFG_BUSY = 1
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};
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/* start position for CEQs allocation, Max number of CEQs is 32 */
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/*lint -save -e849*/
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enum {
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CFG_RDMA_CEQ_BASE = 0
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};
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/*lint -restore*/
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enum {
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CFG_NET_MODE_ETH = 0, /* Eth */
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CFG_NET_MODE_FIC = 1, /* FIC */
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CFG_NET_MODE_FC = 2 /* FC */
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};
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enum {
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SF_SVC_FT_BIT = (1 << 0),
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SF_SVC_RDMA_BIT = (1 << 1),
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};
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/* RDMA resource */
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#define K_UNIT BIT(10)
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#define M_UNIT BIT(20)
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#define G_UNIT BIT(30)
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/* number of PFs and VFs */
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#define HOST_PF_NUM 4
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#define HOST_VF_NUM 0
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#define HOST_OQID_MASK_VAL 2
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/* L2NIC */
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#define L2NIC_SQ_DEPTH (4 * K_UNIT)
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#define L2NIC_RQ_DEPTH (4 * K_UNIT)
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#define HINIC_CFG_MAX_QP 128
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/* RDMA */
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#define RDMA_RSVD_QPS 2
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#define ROCE_MAX_WQES (16 * K_UNIT - 1)
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#define IWARP_MAX_WQES (8 * K_UNIT)
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#define RDMA_MAX_SQ_SGE 8
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#define ROCE_MAX_RQ_SGE 8
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#define IWARP_MAX_RQ_SGE 2
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#define RDMA_MAX_SQ_DESC_SZ (1 * K_UNIT)
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/* (256B(cache_line_len) - 16B(ctrl_seg_len) - 64B(max_task_seg_len)) */
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#define ROCE_MAX_SQ_INLINE_DATA_SZ 192
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#define IWARP_MAX_SQ_INLINE_DATA_SZ 108
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#define ROCE_MAX_RQ_DESC_SZ 128
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#define IWARP_MAX_RQ_DESC_SZ 64
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#define IWARP_MAX_IRQ_DEPTH 1024
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#define IWARP_IRQ_ENTRY_SZ 64
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#define IWARP_MAX_ORQ_DEPTH 1024
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#define IWARP_ORQ_ENTRY_SZ 32
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#define IWARP_MAX_RTOQ_DEPTH 1024
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#define IWARP_RTOQ_ENTRY_SZ 32
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#define IWARP_MAX_ACKQ_DEPTH 1024
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#define IWARP_ACKQ_ENTRY_SZ 16
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#define ROCE_QPC_ENTRY_SZ 512
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#define IWARP_QPC_ENTRY_SZ 1024
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#define WQEBB_SZ 64
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#define ROCE_RDMARC_ENTRY_SZ 32
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#define ROCE_MAX_QP_INIT_RDMA 128
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#define ROCE_MAX_QP_DEST_RDMA 128
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#define ROCE_MAX_SRQ_WQES (16 * K_UNIT - 1)
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#define ROCE_RSVD_SRQS 0
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#define ROCE_MAX_SRQ_SGE 7
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#define ROCE_SRQC_ENTERY_SZ 64
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#define RDMA_MAX_CQES (64 * K_UNIT - 1)
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#define RDMA_RSVD_CQS 0
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#define RDMA_CQC_ENTRY_SZ 128
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#define RDMA_CQE_SZ 32
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#define RDMA_RSVD_MRWS 128
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#define RDMA_MPT_ENTRY_SZ 64
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#define RDMA_NUM_MTTS (1 * G_UNIT)
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#define LOG_MTT_SEG 5
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#define MTT_ENTRY_SZ 8
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#define LOG_RDMARC_SEG 3
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#define LOCAL_ACK_DELAY 15
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#define RDMA_NUM_PORTS 1
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#define ROCE_MAX_MSG_SZ (2 * G_UNIT)
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#define IWARP_MAX_MSG_SZ (1 * G_UNIT)
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#define DB_PAGE_SZ (4 * K_UNIT)
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#define DWQE_SZ 256
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#define NUM_PD (128 * K_UNIT)
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#define RSVD_PD 0
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#define MAX_XRCDS (64 * K_UNIT)
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#define RSVD_XRCDS 0
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#define MAX_GID_PER_PORT 16
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#define GID_ENTRY_SZ 32
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#define RSVD_LKEY ((RDMA_RSVD_MRWS - 1) << 8)
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#define NUM_COMP_VECTORS 32
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#define PAGE_SZ_CAP ((1UL << 12) | (1UL << 13) | (1UL << 14) | \
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(1UL << 16) | (1UL << 18) | (1UL << 20) | \
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(1UL << 22))
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#define ROCE_MODE 1
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#define MAX_FRPL_LEN 511
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#define MAX_PKEYS 1
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/* FCoE */
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#define FCOE_PCTX_SZ 256
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#define FCOE_CCTX_SZ 256
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#define FCOE_SQE_SZ 128
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#define FCOE_SCQC_SZ 64
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#define FCOE_SCQE_SZ 64
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#define FCOE_SRQC_SZ 64
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#define FCOE_SRQE_SZ 32
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/* ToE */
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#define TOE_PCTX_SZ 1024
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#define TOE_CQC_SZ 64
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/* IoE */
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#define IOE_PCTX_SZ 512
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/* FC */
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#define FC_PCTX_SZ 256
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#define FC_CCTX_SZ 256
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#define FC_SQE_SZ 128
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#define FC_SCQC_SZ 64
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#define FC_SCQE_SZ 64
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#define FC_SRQC_SZ 64
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#define FC_SRQE_SZ 32
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/* OVS */
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#define OVS_PCTX_SZ 256
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#define OVS_SCQC_SZ 64
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/* ACL */
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#define ACL_PCTX_SZ 512
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#define ACL_SCQC_SZ 64
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struct dev_sf_svc_attr {
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bool ft_en; /* business enable flag (not include RDMA) */
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bool ft_pf_en; /* In FPGA Test VF resource is in PF or not,
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* 0 - VF, 1 - PF, VF doesn't need this bit.
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*/
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bool rdma_en;
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bool rdma_pf_en;/* In FPGA Test VF RDMA resource is in PF or not,
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* 0 - VF, 1 - PF, VF doesn't need this bit.
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*/
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u8 sf_en_vf; /* SF_EN for PPF/PF's VF */
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};
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struct host_shared_resource_cap {
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u32 host_pctxs; /* Parent Context max 1M, IOE and FCoE max 8K flows */
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u32 host_cctxs; /* Child Context: max 8K */
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u32 host_scqs; /* shared CQ, chip interface module uses 1 SCQ
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* TOE/IOE/FCoE each uses 1 SCQ
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* RoCE/IWARP uses multiple SCQs
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* So 6 SCQ least
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*/
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u32 host_srqs; /* SRQ number: 256K */
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u32 host_mpts; /* MR number:1M */
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};
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/* device capability */
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struct service_cap {
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struct dev_sf_svc_attr sf_svc_attr;
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enum cfg_svc_type_en svc_type; /* user input service type */
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enum cfg_svc_type_en chip_svc_type; /* HW supported service type */
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/* Host global resources */
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u16 host_total_function;
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u8 host_oq_id_mask_val;
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u8 host_id;
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u8 ep_id;
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/* DO NOT get interrupt_type from firmware */
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enum intr_type interrupt_type;
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u8 intr_chip_en;
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u8 max_cos_id; /* PF/VF's max cos id */
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u8 cos_valid_bitmap;
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u8 er_id; /* PF/VF's ER */
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u8 port_id; /* PF/VF's physical port */
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u8 max_vf; /* max VF number that PF supported */
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u8 force_up;
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bool sf_en; /* stateful business status */
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u8 timer_en; /* 0:disable, 1:enable */
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u8 bloomfilter_en; /* 0:disable, 1:enable*/
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u16 max_sqs;
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u16 max_rqs;
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/* For test */
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u32 test_qpc_num;
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u32 test_qpc_resvd_num;
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u32 test_page_size_reorder;
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bool test_xid_alloc_mode;
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bool test_gpa_check_enable;
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u8 test_qpc_alloc_mode;
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u8 test_scqc_alloc_mode;
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u32 test_max_conn_num;
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u32 test_max_cache_conn_num;
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u32 test_scqc_num;
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u32 test_mpt_num;
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u32 test_scq_resvd_num;
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u32 test_mpt_recvd_num;
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u32 test_hash_num;
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u32 test_reorder_num;
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u32 max_connect_num; /* PF/VF maximum connection number(1M) */
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/* The maximum connections which can be stick to cache memory, max 1K */
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u16 max_stick2cache_num;
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/* Starting address in cache memory for bloom filter, 64Bytes aligned */
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u16 bfilter_start_addr;
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/* Length for bloom filter, aligned on 64Bytes. The size is length*64B.
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* Bloom filter memory size + 1 must be power of 2.
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* The maximum memory size of bloom filter is 4M
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*/
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u16 bfilter_len;
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/* The size of hash bucket tables, align on 64 entries.
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* Be used to AND (&) the hash value. Bucket Size +1 must be power of 2.
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* The maximum number of hash bucket is 4M
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*/
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u16 hash_bucket_num;
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u8 net_port_mode; /* 0:ETH,1:FIC,2:4FC */
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u32 pf_num;
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u32 pf_id_start;
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u32 vf_num; /* max numbers of vf in current host */
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u32 vf_id_start;
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struct host_shared_resource_cap shared_res_cap; /* shared capability */
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struct dev_version_info dev_ver_info; /* version */
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struct nic_service_cap nic_cap; /* NIC capability */
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struct rdma_service_cap rdma_cap; /* RDMA capability */
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struct fcoe_service_cap fcoe_cap; /* FCoE capability */
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struct toe_service_cap toe_cap; /* ToE capability */
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struct fc_service_cap fc_cap; /* FC capability */
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struct ovs_service_cap ovs_cap; /* OVS capability */
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struct acl_service_cap acl_cap; /* ACL capability */
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};
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struct cfg_eq {
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enum hinic_service_type type;
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int eqn;
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int free; /* 1 - alocated, 0- freed */
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};
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struct cfg_eq_info {
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struct cfg_eq *eq;
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u8 num_ceq;
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u8 num_ceq_remain;
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/* mutex used for allocate EQs */
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struct mutex eq_mutex;
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};
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struct irq_alloc_info_st {
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enum hinic_service_type type;
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int free; /* 1 - alocated, 0- freed */
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struct irq_info info;
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};
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struct cfg_irq_info {
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struct irq_alloc_info_st *alloc_info;
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u16 num_total;
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u16 num_irq_remain;
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u16 num_irq_hw; /* device max irq number */
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/* mutex used for allocate EQs */
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struct mutex irq_mutex;
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};
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#define VECTOR_THRESHOLD 2
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struct cfg_mgmt_info {
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struct hinic_hwdev *hwdev;
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struct service_cap svc_cap;
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struct cfg_eq_info eq_info; /* EQ */
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struct cfg_irq_info irq_param_info; /* IRQ */
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u32 func_seq_num; /* temporary */
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};
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enum cfg_sub_cmd {
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/* PPF(PF) <-> FW */
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HINIC_CFG_NIC_CAP = 0,
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CFG_FW_VERSION,
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CFG_UCODE_VERSION,
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HINIC_CFG_FUNC_CAP,
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HINIC_CFG_MBOX_CAP = 6,
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};
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struct hinic_dev_cap {
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u8 status;
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u8 version;
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u8 rsvd0[6];
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/* Public resource */
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u8 sf_svc_attr;
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u8 host_id;
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u8 sf_en_pf;
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u8 sf_en_vf;
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u8 ep_id;
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u8 intr_type;
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u8 max_cos_id;
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u8 er_id;
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u8 port_id;
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u8 max_vf;
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u16 svc_cap_en;
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u16 host_total_func;
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u8 host_oq_id_mask_val;
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u8 max_vf_cos_id;
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u32 max_conn_num;
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u16 max_stick2cache_num;
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u16 max_bfilter_start_addr;
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u16 bfilter_len;
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u16 hash_bucket_num;
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u8 cfg_file_ver;
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u8 net_port_mode;
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u8 valid_cos_bitmap; /* every bit indicate cos is valid */
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u8 force_up;
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u32 pf_num;
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u32 pf_id_start;
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u32 vf_num;
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u32 vf_id_start;
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/* shared resource */
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u32 host_pctx_num;
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u8 host_sf_en;
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u8 rsvd2[3];
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u32 host_ccxt_num;
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u32 host_scq_num;
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u32 host_srq_num;
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u32 host_mpt_num;
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/* l2nic */
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u16 nic_max_sq;
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u16 nic_max_rq;
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u16 nic_vf_max_sq;
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u16 nic_vf_max_rq;
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u8 nic_lro_en;
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u8 nic_lro_sz;
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u8 nic_tso_sz;
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u8 max_queue_allowed;
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/* RoCE */
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u32 roce_max_qp;
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u32 roce_max_cq;
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u32 roce_max_srq;
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u32 roce_max_mpt;
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u32 roce_vf_max_qp;
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u32 roce_vf_max_cq;
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u32 roce_vf_max_srq;
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u32 roce_vf_max_mpt;
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u32 roce_cmtt_cl_start;
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u32 roce_cmtt_cl_end;
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u32 roce_cmtt_cl_size;
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u32 roce_dmtt_cl_start;
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u32 roce_dmtt_cl_end;
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u32 roce_dmtt_cl_size;
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u32 roce_wqe_cl_start;
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u32 roce_wqe_cl_end;
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u32 roce_wqe_cl_size;
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/* IWARP */
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u32 iwarp_max_qp;
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u32 iwarp_max_cq;
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u32 iwarp_max_mpt;
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u32 iwarp_vf_max_qp;
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u32 iwarp_vf_max_cq;
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u32 iwarp_vf_max_mpt;
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u32 iwarp_cmtt_cl_start;
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u32 iwarp_cmtt_cl_end;
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u32 iwarp_cmtt_cl_size;
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u32 iwarp_dmtt_cl_start;
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u32 iwarp_dmtt_cl_end;
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u32 iwarp_dmtt_cl_size;
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u32 iwarp_wqe_cl_start;
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u32 iwarp_wqe_cl_end;
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u32 iwarp_wqe_cl_size;
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/* FCoE */
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u32 fcoe_max_qp;
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u32 fcoe_max_cq;
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u32 fcoe_max_srq;
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u32 fcoe_max_cctx;
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u32 fcoe_cctx_id_start;
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u8 fcoe_vp_id_start;
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u8 fcoe_vp_id_end;
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u8 rsvd4[2];
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/* OVS */
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u32 ovs_max_qpc;
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u8 ovs_dq_en;
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u8 rsvd5[3];
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/* ToE */
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u32 toe_max_pctx;
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u32 toe_max_cq;
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u32 toe_max_srq;
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u32 toe_srq_id_start;
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/* FC */
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u32 fc_max_pctx;
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u32 fc_max_scq;
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u32 fc_max_srq;
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u32 fc_max_cctx;
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u32 fc_cctx_id_start;
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u8 fc_vp_id_start;
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u8 fc_vp_id_end;
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u16 func_id;
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};
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#define VSW_UP_CFG_TIMEOUT (0xFF00000)
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#define VSW_SET_STATEFUL_BITS_TOE(flag) \
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((flag) << VSW_STATEFUL_TOE_EN)
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#define VSW_SET_STATEFUL_BITS_FCOE(flag) \
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((flag) << VSW_STATEFUL_FCOE_EN)
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#define VSW_SET_STATEFUL_BITS_IWARP(flag) \
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((flag) << VSW_STATEFUL_IWARP_EN)
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#define VSW_SET_STATEFUL_BITS_ROCE(flag) \
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((flag) << VSW_STATEFUL_ROCE_EN)
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#define VSW_GET_STATEFUL_BITS_TOE(flag) \
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((bool)(((flag) >> VSW_STATEFUL_TOE_EN) & 0x1U))
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#define VSW_GET_STATEFUL_BITS_FCOE(flag) \
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((bool)(((flag) >> VSW_STATEFUL_FCOE_EN) & 0x1U))
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#define VSW_GET_STATEFUL_BITS_IWARP(flag) \
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((bool)(((flag) >> VSW_STATEFUL_IWARP_EN) & 0x1U))
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#define VSW_GET_STATEFUL_BITS_ROCE(flag) \
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((bool)(((flag) >> VSW_STATEFUL_ROCE_EN) & 0x1U))
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enum tag_vsw_major_cmd {
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VSW_MAJOR_MISC = 10, /* 0~9 reserved for driver */
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VSW_MAJOR_L2SWITCH,
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VSW_MAJOR_L2MULTICAST,
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VSW_MAJOR_QOS,
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VSW_MAJOR_PKTSUPS,
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VSW_MAJOR_VLANFILTER,
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VSW_MAJOR_MACFILTER,
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VSW_MAJOR_IPFILTER,
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VSW_MAJOR_VLANMAPPING,
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VSW_MAJOR_ETHTRUNK,
|
|
VSW_MAJOR_MIRROR,
|
|
VSW_MAJOR_DFX,
|
|
VSW_MAJOR_ACL,
|
|
};
|
|
|
|
enum tag_vsw_minor_misc_cmd {
|
|
VSW_MINOR_MISC_INIT_FUNC = 0,
|
|
VSW_MINOR_MISC_SET_FUNC_SF_ENBITS,
|
|
VSW_MINOR_MISC_GET_FUNC_SF_ENBITS,
|
|
VSW_MINOR_MISC_CMD_MAX,
|
|
};
|
|
|
|
/* vswitch eth-trunk sub-command */
|
|
enum tag_nic_stateful_enbits {
|
|
VSW_STATEFUL_TOE_EN = 0,
|
|
VSW_STATEFUL_FCOE_EN = 1,
|
|
VSW_STATEFUL_IWARP_EN = 2,
|
|
VSW_STATEFUL_ROCE_EN = 3,
|
|
};
|
|
|
|
/* function stateful enable parameters */
|
|
struct nic_misc_func_sf_enbits {
|
|
u8 status;
|
|
u8 version;
|
|
u8 rsvd0[6];
|
|
u32 function_id;
|
|
u32 stateful_enbits; /* b0:toe, b1:fcoe, b2:iwarp, b3:roce */
|
|
u32 stateful_enmask; /* b0:toe, b1:fcoe, b2:iwarp, b3:roce */
|
|
};
|
|
|
|
#endif
|