122 lines
2.7 KiB
C
122 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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// Copyright (c) 2023 Hisilicon Limited.
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#ifndef __HNAE3_EXT_H
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#define __HNAE3_EXT_H
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enum hnae3_event_type_custom {
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HNAE3_VF_RESET_CUSTOM,
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HNAE3_VF_FUNC_RESET_CUSTOM,
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HNAE3_VF_PF_FUNC_RESET_CUSTOM,
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HNAE3_VF_FULL_RESET_CUSTOM,
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HNAE3_FLR_RESET_CUSTOM,
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HNAE3_FUNC_RESET_CUSTOM,
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HNAE3_GLOBAL_RESET_CUSTOM,
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HNAE3_IMP_RESET_CUSTOM,
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HNAE3_UNKNOWN_RESET_CUSTOM,
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HNAE3_NONE_RESET_CUSTOM,
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HNAE3_PORT_FAULT,
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HNAE3_RESET_DONE_CUSTOM,
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HNAE3_FUNC_RESET_FAIL_CUSTOM,
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HNAE3_GLOBAL_RESET_FAIL_CUSTOM,
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HNAE3_IMP_RESET_FAIL_CUSTOM,
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HNAE3_PPU_POISON_CUSTOM,
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HNAE3_IMP_RD_POISON_CUSTOM,
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HNAE3_ROCEE_AXI_RESP_CUSTOM,
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HNAE3_INVALID_EVENT_CUSTOM,
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};
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enum hnae3_ext_opcode {
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HNAE3_EXT_OPC_RESET,
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HNAE3_EXT_OPC_EVENT_CALLBACK,
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HNAE3_EXT_OPC_GET_PFC_STORM_PARA,
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HNAE3_EXT_OPC_SET_PFC_STORM_PARA,
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HNAE3_EXT_OPC_SET_NOTIFY_PARAM,
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HNAE3_EXT_OPC_SET_NOTIFY_START,
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HNAE3_EXT_OPC_SET_TORUS_PARAM,
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HNAE3_EXT_OPC_GET_TORUS_PARAM,
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HNAE3_EXT_OPC_CLEAN_STATS64,
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HNAE3_EXT_OPC_GET_PORT_EXT_ID_INFO,
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HNAE3_EXT_OPC_GET_PORT_EXT_NUM_INFO,
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HNAE3_EXT_OPC_GET_PORT_NUM,
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HNAE3_EXT_OPC_GET_PRESENT,
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HNAE3_EXT_OPC_SET_SFP_STATE,
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HNAE3_EXT_OPC_DISABLE_LANE,
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HNAE3_EXT_OPC_GET_LANE_STATUS,
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HNAE3_EXT_OPC_DISABLE_CLOCK,
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HNAE3_EXT_OPC_SET_PFC_TIME,
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HNAE3_EXT_OPC_GET_HILINK_REF_LOS,
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HNAE3_EXT_OPC_GET_PORT_FAULT_STATUS,
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HNAE3_EXT_OPC_GET_PORT_TYPE,
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HNAE3_EXT_OPC_SET_MAC_STATE,
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HNAE3_EXT_OPC_SET_LED,
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HNAE3_EXT_OPC_GET_LED_SIGNAL,
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HNAE3_EXT_OPC_GET_PHY_REG,
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HNAE3_EXT_OPC_SET_PHY_REG,
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};
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struct hnae3_led_state_para {
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u32 type;
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u32 status;
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};
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struct hnae3_phy_para {
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u32 page_select_addr;
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u32 reg_addr;
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u16 page;
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u16 data;
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};
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struct hnae3_lamp_signal {
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u8 error;
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u8 locate;
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u8 activity;
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};
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struct hnae3_pfc_storm_para {
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u32 dir;
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u32 enable;
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u32 period_ms;
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u32 times;
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u32 recovery_period_ms;
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};
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enum hnae3_port_fault_type {
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HNAE3_FAULT_TYPE_CDR_FLASH,
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HNAE3_FAULT_TYPE_9545_ERR,
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HNAE3_FAULT_TYPE_CDR_CORE,
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HNAE3_FAULT_TYPE_HILINK_REF_LOS,
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HNAE3_FAULT_TYPE_INVALID
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};
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struct hnae3_port_fault {
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u32 fault_type;
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u32 fault_status;
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};
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struct hnae3_notify_pkt_param {
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u32 ipg; /* inter-packet gap of sending, the unit is one cycle of clock */
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u16 num; /* packet number of sending */
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u8 enable; /* send enable, 0=Disable, 1=Enable */
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u8 init; /* initialization flag, product does not need to set value */
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u8 data[64]; /* note packet data */
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};
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struct hnae3_torus_param {
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u32 enable; /* 1d torus mode enable */
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u32 mac_id; /* export mac id of port */
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u8 is_node0; /* if current node is node0 */
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};
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struct hane3_port_ext_id_info {
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u32 chip_id;
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u32 mac_id;
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u32 io_die_id;
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};
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struct hane3_port_ext_num_info {
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u32 chip_num;
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u32 io_die_num;
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};
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#endif
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