256 lines
6.4 KiB
C
256 lines
6.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2020 - 2024, Chengdu BeiZhongWangXin Technology Co., Ltd. */
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#ifndef _NE6X_COMM_REG_H
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#define _NE6X_COMM_REG_H
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#include <asm/types.h>
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#define NE6X_BAR2_VP_TDQ(__vp, __reg) \
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((((__vp) & 0x7f) << 12) | (0 << 11) | (((__reg) & 0xff) << 3))
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#define NE6X_BAR2_VP_RDQ(__vp, __reg) \
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((((__vp) & 0x7f) << 12) | (1 << 11) | (((__reg) & 0xff) << 3))
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/* CIU */
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#define NE6X_VP_BASE_ADDR 0x0
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#define NE6X_VPINT_DYN_CTLN(_VPID, _OFFSET) \
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(((_VPID) << 12) + ((_OFFSET) << 4)) /* _i=0...64 * Reset: PFR */
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#define NE6X_PF_BASE_ADDR 0x138ULL
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#define NE6X_PFINT_DYN_CTLN(_PFID, _OFFSET) \
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(((NE6X_PF_BASE_ADDR + (_PFID)) << 12) + ((_OFFSET) << 4))
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/* _i=0...7 */ /* Reset: PFR */
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#define NE6X_VP_INT 0x00
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#define NE6X_VP_INT_SET 0x01
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#define NE6X_VP_INT_MASK 0x02
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#define NE6X_VP_CQ_INTSHIFT 16
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#define NE6X_CQ_BASE_ADDR 0x03
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#define NE6X_CQ_HD_POINTER 0x04
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#define NE6X_CQ_CFG 0x05
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#define NE6X_RQ_BASE_ADDR 0x07
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#define NE6X_RQ_CFG 0x08
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#define NE6X_RQ_TAIL_POINTER 0x09
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#define NE6X_VP_RELOAD 0x0a
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#define NE6X_SQ_BASE_ADDR 0x0b
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#define NE6X_SQ_CFG 0x0c
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#define NE6X_SQ_TAIL_POINTER 0x0d
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#define NE6X_CQ_TAIL_POINTER 0x11
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#define NE6X_RQ_BUFF_OFST 0x12
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#define NE6X_RQ_HD_POINTER 0x13
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#define NE6X_SQ_BUFF_OFST 0x14
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#define NE6X_SQ_HD_POINTER 0x15
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#define NE6X_RQ_OFST 0x16
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#define NE6X_SQ_OFST 0x17
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#define NE6X_RQ_BLOCK_CFG 0x1b
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#define NE6X_SQ_METER_CFG0 0x1c
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#define NE6X_SQ_METER_CFG1 0x1d
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#define NE6X_SQ_METER_CFG2 0x1e
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#define NE6X_SQ_METER_CFG3 0x1f
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#define NE6X_INT_CFG 0x21
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#define NE6X_CIU_TIME_OUT_CFG 0x45
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#define NE6X_ALL_CQ_CFG 0x46
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#define NE6X_ALL_SQ_CFG 0x47
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#define NE6X_ALL_RQ_CFG 0x48
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#define NE6X_MERGE_CFG 0x49
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#define NE6X_BFD_RECV_CNT 0x4a
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#define NE6X_ETH_RECV_CNT 0x4b
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#define NE6X_PF_CON_ADDR(_OFST) \
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(((NE6X_PF_BASE_ADDR) << 12) + ((_OFST) << 4))
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#define NE6X_PF_MAILBOX_DATA 0x40
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#define NE6X_VF_MAILBOX_DATA 0x80
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#define NE6X_PF_MAILBOX_ADDR(_VP) \
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(((NE6X_PF_BASE_ADDR) << 12) + ((NE6X_PF_MAILBOX_DATA + (_VP)) << 4))
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#define NE6X_VF_MAILBOX_ADDR(_VP) \
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(((NE6X_PF_BASE_ADDR) << 12) + ((NE6X_VF_MAILBOX_DATA + (_VP)) << 4))
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#define NE6X_PF_DB_INT_REQ 0xC0
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#define NE6X_PF_DB_INT_ACK 0xC1
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#define NE6X_PF_DB_DREQ_INT 0xC2
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#define NE6X_PF_DB_DREQ_INT_SET 0xC3
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#define NE6X_PF_DB_DREQ_INT_MASK 0xC4
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#define NE6X_PF_DB_DACK_INT 0xC5
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#define NE6X_PF_DB_DACK_INT_SET 0xC6
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#define NE6X_PF_DB_DACK_INT_MASK 0xC7
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union ne6x_vp_int {
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struct vp_int {
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u64 csr_ciu_int_vp : 64;
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} reg;
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u64 val;
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};
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union ne6x_vp_int_mask {
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struct vp_int_mask {
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u64 csr_ciu_mask_vp : 64;
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} reg;
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u64 val;
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};
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union ne6x_cq_base_addr {
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struct cq_base_addr {
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u64 csr_cq_base_addr_vp : 64;
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} reg;
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u64 val;
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};
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union ne6x_cq_cfg {
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struct cq_cfg {
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u64 csr_cq_len_vp : 16;
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u64 csr_cq_merge_time_vp : 16;
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u64 csr_cq_merge_size_vp : 4;
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u64 rsv0 : 28;
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} reg;
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u64 val;
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};
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union ne6x_rq_base_addr {
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struct rq_base_addr {
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u64 csr_rq_base_addr_vp : 64;
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} reg;
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u64 val;
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};
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union ne6x_rq_cfg {
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struct rq_cfg {
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u64 csr_rq_len_vp : 16;
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u64 csr_rdq_pull_en : 1;
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u64 csr_rqevt_write_back_vp : 1;
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u64 csr_recv_pd_type_vp : 2;
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u64 csr_recv_pd_revers_en : 1;
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u64 rsv0 : 11;
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u64 rsv1 : 32;
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} reg;
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u64 val;
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};
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union ne6x_sq_base_addr {
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struct sq_base_addr {
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u64 csr_sq_base_addr_vp : 64;
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} reg;
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u64 val;
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};
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union ne6x_sq_cfg {
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struct sq_cfg {
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u64 csr_sq_len_vp : 16;
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u64 csr_tdq_pull_en : 1;
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u64 csr_sqevt_write_back_vp : 1;
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u64 csr_send_pd_revers_en : 1;
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u64 rsv0 : 13;
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u64 rsv1 : 32;
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} reg;
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u64 val;
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};
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union ne6x_rq_block_cfg {
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struct rq_block_cfg {
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u64 csr_rdq_mop_len : 16;
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u64 csr_rdq_sop_len : 16;
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u64 rsv0 : 32;
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} reg;
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u64 val;
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};
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union ne6x_sq_meter_cfg0 {
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struct sq_meter_cfg0 {
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u64 csr_meter_pkt_token_num_vp : 16;
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u64 csr_meter_ipg_len_vp : 8;
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u64 csr_meter_refresh_en_vp : 1;
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u64 csr_meter_rate_limit_en_vp : 1;
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u64 csr_meter_packet_mode_vp : 1;
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u64 reserved : 37;
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} reg;
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u64 val;
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};
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union ne6x_sq_meter_cfg1 {
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struct sq_meter_cfg1 {
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u64 csr_meter_refresh_count_vp : 28;
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u64 reserved : 4;
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u64 csr_meter_refresh_interval_vp : 32;
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} reg;
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u64 val;
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};
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union ne6x_sq_meter_cfg2 {
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struct sq_meter_cfg2 {
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u64 csr_meter_resume_threshold_vp : 32;
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u64 reserved : 32;
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} reg;
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u64 val;
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};
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union ne6x_sq_meter_cfg3 {
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struct sq_meter_cfg3 {
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u64 csr_meter_pause_threshold_vp : 32;
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u64 reserved : 32;
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} reg;
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u64 val;
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};
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union ne6x_int_cfg {
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struct int_cfg {
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u64 csr_sq_hdle_half_int_cnt_vp : 16;
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u64 csr_rq_hdle_half_int_cnt_vp : 16;
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u64 csr_cq_hdle_half_int_cnt_vp : 16;
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u64 rsv0 : 16;
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} reg;
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u64 val;
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};
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union ne6x_ciu_time_out_cfg {
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struct ciu_time_out_cfg {
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u64 csr_int_timer_out_cnt : 12;
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u64 rsv0 : 52;
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} reg;
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u64 val;
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};
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union ne6x_all_cq_cfg {
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struct all_cq_cfg {
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u64 csr_allcq_merge_size : 4;
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u64 rsv0 : 4;
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u64 csr_allcq_wt_rr_cnt : 7;
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u64 csr_allcq_wt_rr_flag : 1;
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u64 rsv1 : 48;
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} reg;
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u64 val;
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};
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union ne6x_all_sq_cfg {
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struct all_sq_cfg {
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u64 csr_allsq_wb_trigger_info : 8;
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u64 csr_allsq_csum_zero_negate : 1;
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u64 csr_allsq_pull_merge_cfg : 5;
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u64 rsv0 : 50;
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} reg;
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u64 val;
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};
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union ne6x_all_rq_cfg {
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struct all_rq_cfg {
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u64 csr_allrq_wb_trigger_info : 8;
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u64 csr_allrq_pull_merge_cfg : 5;
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u64 rsv0 : 51;
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} reg;
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u64 val;
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};
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union ne6x_merge_cfg {
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struct merge_cfg {
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u64 csr_merge_clk_cnt : 16;
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u64 rsv0 : 48;
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} reg;
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u64 val;
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};
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union ne6x_eth_recv_cnt {
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struct eth_recv_cnt {
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u64 csr_eth_pkt_drop_cnt : 32;
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u64 csr_eth_rdq_drop_cnt : 32;
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} reg;
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u64 val;
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};
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#endif
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