80 lines
2.1 KiB
C
80 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This file contains declarations and inline functions for interfacing
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* with the PCI initialization routines.
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*/
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#include <linux/iommu.h>
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#include <linux/iova.h>
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#include <linux/spinlock_types.h>
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#include <linux/mutex.h>
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struct sunway_iommu_bypass_id {
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unsigned int vendor;
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unsigned int device;
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};
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struct sunway_iommu {
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int index;
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bool enabled;
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unsigned long *iommu_dtbr;
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spinlock_t dt_lock; /* Device Table Lock */
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int node; /* NUMA node */
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struct pci_controller *hose_pt;
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struct iommu_device iommu; /* IOMMU core code handle */
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};
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struct sunway_iommu_dev {
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struct list_head list; /* For domain->dev_list */
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struct llist_node dev_data_list; /* Global device list */
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u16 devid;
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int alias;
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unsigned int passthrough;
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struct sunway_iommu *iommu;
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struct pci_dev *pdev;
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spinlock_t lock; /* Lock the page table mainly */
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struct sunway_iommu_domain *domain; /* Domain device is bound to */
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};
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struct sunway_iommu_domain {
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unsigned int type;
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spinlock_t lock;
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struct mutex api_lock;
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u16 id; /* Domain ID */
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struct list_head list; /* For list of all SW domains */
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struct list_head dev_list; /* List of devices in this domain */
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struct iommu_domain domain; /* IOMMU domain handle */
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unsigned long *pt_root; /* Page Table root */
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unsigned int dev_cnt; /* Number of devices in this domain */
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};
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struct sw64dev_table_entry {
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u64 data;
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};
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struct sunway_iommu_group {
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struct pci_dev *dev;
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struct iommu_group *group;
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};
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#define SW64_IOMMU_ENTRY_VALID ((1UL) << 63)
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#define SW64_PTE_LAST_MASK ((1UL) << 8) /*last stage valid*/
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#define SW64_DMA_START 0x1000000
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#define SW64_PTE_GRN_MASK ((0x3UL) << 4)
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#define PAGE_8M_SHIFT 23
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#define PAGE_512M_SHIFT 29
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#define PAGE_8G_SHIFT 33
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#define SW64_IOMMU_ENABLE 3
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#define SW64_IOMMU_DISABLE 0
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#define SW64_IOMMU_LEVEL1_OFFSET 0x1ff
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#define SW64_IOMMU_LEVEL2_OFFSET 0x3ff
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#define SW64_IOMMU_LEVEL3_OFFSET 0x3ff
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#define SW64_IOMMU_BYPASS 0x1
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#define SW64_IOMMU_MAP_FLAG ((0x1UL) << 20)
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#define PAGE_SHIFT_IOMMU 18
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#define PAGE_SIZE_IOMMU (_AC(1, UL) << PAGE_SHIFT_IOMMU)
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#define PCACHE_FLUSHPADDR_MASK 0xffffffffff80UL
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