202 lines
4.3 KiB
C
202 lines
4.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2024 Huawei Technologies Co., Ltd */
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#ifndef ROCE_SRQ_H
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#define ROCE_SRQ_H
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#include <linux/types.h>
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#include <rdma/ib_verbs.h>
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#include "hinic3_rdma.h"
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#include "hinic3_cqm.h"
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#include "roce.h"
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#include "roce_pd.h"
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#include "roce_db.h"
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#include "rdma_context_format.h"
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#define ROCE_SRQ_MAX_SGE 15
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#define ROCE_SRQ_MID_SGE 7
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#define ROCE_SRQ_MIN_SGE 3
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#define ROCE_SRQN_INVLD 0XFFFFFFFF
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#define ROCE_SRQ_CONTAINER_LWM_MASK 0xFFFF
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#define ROCE_SRQ_CONTAINER_WARTH_MASK 0xF
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#define MAX_SUPPORT_CONTAINER_MODE 3
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#define DWORD_LEN 32
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#define XRC_CQN_FIRST_LEN 10
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#define XRC_CQN_SECOND_LEN 3
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#define SRQ_GPA_SIG_LEN 3
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/* (2^rq_wqebb_size)*16B => divide 16 means shift need to minus 4 */
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#define SRQ_WQEBB_SIZE_CAL_SECTTOR 4
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#define RDMA_PREFETCH_WQE_MAX 7
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#define RDMA_PREFETCH_MTT_LEN_MAX 3
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#define ROCE_WQE_BB_SIZE_MIN 64
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/*
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* Lbit:0 - The next SGE is present in the list
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* Lbit:1 - The last SGE, no SGE is present in the list
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*/
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#define LAST_SGE_NO_PRESENT 0x80000000UL
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/*
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* Ebit:b0 - Normal format, without extension.
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* Ebit:b1 - The pointer inside of SGE points to the next SGL.
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* "Length" and "Key" fields are
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*/
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#define NORMAL_FMT_AND_NEXT_SGE_PRESENT 0x3FFFFFFFUL
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#define NORMAL_FMT_AND_LAST_SGE_NO_PRESENT 0xBFFFFFFFUL
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/**
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* container_mode:
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* mode: 0 -> container_size: 16
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* mode: 1 -> container_size: 8
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* mode: 2 -> container_size: 4
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* mode: 3 -> container_size: 2
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*/
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enum roce3_srq_mode {
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ROCE_SRQ_MODE_0 = 0,
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ROCE_SRQ_MODE_1,
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ROCE_SRQ_MODE_2,
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ROCE_SRQ_MODE_3
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};
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/**
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* CHIP container_mode:
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* chip mode: 0 -> Not container
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* chip mode: 1 -> container_size: 2
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* chip mode: 2 -> container_size: 4
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* chip mode: 3 -> container_size: 8
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* chip mode: 4 -> container_size: 16
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*/
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enum roce3_chip_srq_mode {
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ROCE_CHIP_SRQ_MODE_N = 0,
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ROCE_CHIP_SRQ_MODE_1,
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ROCE_CHIP_SRQ_MODE_2,
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ROCE_CHIP_SRQ_MODE_3,
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ROCE_CHIP_SRQ_MODE_4
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};
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enum roce3_srq_cont_num_mode {
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ROCE_SRQ_CONT_NUM_MODE3 = 2,
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ROCE_SRQ_CONT_NUM_MODE2 = 4,
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ROCE_SRQ_CONT_NUM_MODE1 = 8,
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ROCE_SRQ_CONT_NUM_MODE0 = 16
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};
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enum srq_state {
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ROCE_SRQ_STATE_INVALID = 0x0,
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ROCE_SRQ_STATE_ERR = 0x1,
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ROCE_SRQ_STATE_VALID = 0xf,
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ROCE_SRQ_STATE_MEM_INIT = 0xa
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};
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#define ROCE_SRQ_STATE_CHECK_VALUE 0x0
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struct roce3_srq_query_outbuf {
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struct roce_srq_context srqc;
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u32 srq_ctr_vld;
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u32 srq_empty_ctr;
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u32 reserved[6];
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};
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struct roce3_wqe_srq_next_seg {
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u16 reserved1;
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__be16 pcnt; /* indicate the pi */
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u8 signature;
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u8 reserved2;
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__be16 next_wqe_index;
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u32 reserved3[2];
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};
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struct roce3_wqe_container_srq_next_seg {
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u32 next_gpa_h;
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struct {
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u32 rsvd : 11;
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u32 next_gpa_vd : 1;
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u32 next_gpa_h : 20; /* indicate the pi */
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} dw1;
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struct {
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u32 next_idx : 16;
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u32 rsvd : 16;
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} dw2;
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struct {
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u32 rsvd2 : 30;
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u32 link_flag : 1;
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u32 rsvd : 1;
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} dw3;
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struct {
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u32 osd_next_idx : 16;
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u32 osd_cur_idx : 16;
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} dw4;
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};
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#define ROCE_SRQ_SGE_LAST 1
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#define ROCE_SRQ_SGE_NLAST 0
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#define ROCE_SRQ_SGE_LKEY_NOEXT 0
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#define ROCE_SRQ_SGE_LKEY_EXT 1
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struct roce3_srq {
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struct ib_srq ibsrq; /* ibsrq */
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struct tag_cqm_queue *cqm_srq;
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u32 srqn;
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int max_depth;
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int max_gs;
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int wqe_shift;
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struct tag_cqm_buf *buf;
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struct roce3_db db;
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u64 *wrid;
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spinlock_t lock;
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int head;
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int tail;
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u16 wqe_ctr;
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u8 xrc_en;
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u8 rsvd;
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struct ib_umem *umem;
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struct rdma_mtt mtt;
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struct mutex mutex;
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u32 rqe_cnt_th;
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u8 container_flag;
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u8 container_size;
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u8 container_mode;
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u8 container_warn_th;
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int buf_sz;
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};
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static inline struct roce3_srq *to_roce3_srq(const struct ib_srq *ibsrq)
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{
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return container_of(ibsrq, struct roce3_srq, ibsrq);
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}
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static inline struct roce3_srq *cqmobj_to_roce3_srq(const struct tag_cqm_object *object)
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{
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struct tag_cqm_queue *cqm_srq;
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cqm_srq = container_of(object, struct tag_cqm_queue, object);
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return (struct roce3_srq *)cqm_srq->priv;
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}
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void roce3_free_srq_wqe(struct roce3_srq *srq, int wqe_index);
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void roce3_srq_async_event(struct roce3_device *rdev, struct roce3_srq *srq, int type);
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void *roce3_srq_get_wqe(struct roce3_srq *srq, int n);
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u8 roce3_get_container_sz(u32 container_mode);
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u8 roce3_calculate_cont_th(u32 srq_limit);
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u8 roce3_srq_mode_chip_adapt(u8 cfg_mode);
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u32 roce3_srq_max_avail_wr_set(struct roce3_srq *rsrq);
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int roce3_create_srq_common(struct roce3_device *rdev, struct roce3_srq *rsrq, struct roce3_pd *pd,
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struct ib_srq_init_attr *init_attr, struct ib_udata *udata, u32 index);
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#endif // ROCE_SRQ_H
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