210 lines
7.5 KiB
C
210 lines
7.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Phytium Pe220x display engine register
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*
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* Copyright (C) 2021-2023, Phytium Technology Co., Ltd.
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*/
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#ifndef __PE220X_REG_H__
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#define __PE220X_REG_H__
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#include "phytium_reg.h"
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/* dc register */
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#define PE220X_DC_CLOCK_CONTROL 0x0000
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#define DC1_CORE_RESET (1<<18)
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#define DC0_CORE_RESET (1<<17)
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#define AXI_RESET (1<<16)
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#define AHB_RESET (1<<12)
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#define PE220X_DC_CMD_REGISTER(pipe) (PE220X_DC_BASE(0) + 0x00F0 + 0x4*(pipe))
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#define FLAG_REPLY (1<<31)
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#define FLAG_REQUEST (1<<30)
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#define CMD_PIXEL_CLOCK (0x0 << 28)
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#define CMD_BACKLIGHT (0x1 << 28)
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#define CMD_DC_DP_RESET (0x3 << 28)
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#define BACKLIGHT_SHIFT 21
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#define BACKLIGHT_MASK 0x7f
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#define BACKLIGHT_MAX 100
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#define BACKLIGHT_ENABLE (101 << BACKLIGHT_SHIFT)
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#define BACKLIGHT_DISABLE (102 << BACKLIGHT_SHIFT)
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#define PANEL_POWER_ENABLE (103 << BACKLIGHT_SHIFT)
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#define PANEL_POWER_DISABLE (104 << BACKLIGHT_SHIFT)
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#define PIXEL_CLOCK_MASK (0x1fffff)
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#define PE220X_DC_FRAMEBUFFER_Y_HI_ADDRESS 0x1404
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#define PREFIX_MASK 0xff
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#define PREFIX_SHIFT 32
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#define PE220X_DC_CURSOR_HI_ADDRESS 0x1490
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#define CURSOR_PREFIX_MASK 0xff
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#define CURSOR_PREFIX_SHIFT 32
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#define PE220X_DC_FRAMEBUFFER_U_HI_ADDRESS 0x1534
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#define U_PREFIX_MASK 0xff
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#define U_PREFIX_SHIFT 32
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#define PE220X_DC_FRAMEBUFFER_V_HI_ADDRESS 0x153c
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#define V_PREFIX_MASK 0xff
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#define V_PREFIX_SHIFT 32
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/* dp register */
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#define PE220X_DP_CONTROLLER_RESET 0x0850
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#define DP_RESET 0x1
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/* address transform register */
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#define PE220X_DC_ADDRESS_TRANSFORM_SRC_ADDR 0x0
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#define SRC_ADDR_OFFSET 22
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#define SRC_ADDR_MASK 0xffffffffff
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#define PE220X_DC_ADDRESS_TRANSFORM_SIZE 0x4
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#define ADDRESS_TRANSFORM_ENABLE (0x1 << 31)
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#define SIZE_OFFSET 22
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#define PE220X_DC_ADDRESS_TRANSFORM_DST_ADDR 0x8
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#define DST_ADDR_OFFSET 22
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#define PE220X_DC_ADDRESS_TRANSFORM_DP_RESET_STATUS 0x48
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#define DC_DP_RESET_STATUS(pipe) (1 << pipe)
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#define DP_SPREAD_ENABLE(pipe) (0x8 << pipe)
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#define PE220X_DC_ADDRESS_TRANSFORM_BACKLIGHT_VALUE 0x4c
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#define BACKLIGHT_VALUE_MASK (0x7f)
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#define BACKLIGHT_VALUE_SHIFT 16
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/* phy register start */
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#define PE220X_PHY_BASE(pipe) (0x100000*pipe)
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#define PE220X_PHY_PIPE_RESET(pipe) (PE220X_PHY_BASE(pipe) + 0x40254)
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#define RESET 0x0
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#define RESET_DEASSERT 0x1
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#define PE220X_PHY_MODE(pipe) (PE220X_PHY_BASE(pipe) + 0x40034)
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#define LANE_BIT (0x3)
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#define LANE_BIT_SHIFT 0x2
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#define PE220X_PHY_LINK_CFG(pipe) (PE220X_PHY_BASE(pipe) + 0x40044)
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#define LANE_MASTER 0x1
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#define LANE_MASTER_SHIFT 1
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#define PE220X_PHY_PLL_EN(pipe) (PE220X_PHY_BASE(pipe) + 0x40214)
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#define PLL_EN 0x1
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#define PLL_EN_SHIFT 1
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#define PE220X_PHY_PMA_WIDTH(pipe) (PE220X_PHY_BASE(pipe) + 0x4021c)
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#define BIT_20 0x5
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#define BIT_20_SHIFT 4
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#define PE220X_PHY_PLL_SOURCE_SEL(pipe) (PE220X_PHY_BASE(pipe) + 0x4004C)
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#define PE220X_PHY_PMA0_POWER(pipe) (PE220X_PHY_BASE(pipe) + 0x402bc)
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#define A0_ACTIVE 0x1
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#define A0_ACTIVE_SHIFT 8
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#define A3_POWERDOWN3 0x8
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#define A3_POWERDOWN3_SHIFT 8
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#define PE220X_PHY_LINK_RESET(pipe) (PE220X_PHY_BASE(pipe) + 0x40258)
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#define LINK_RESET 0x1
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#define LINK_RESET_MASK 0x1
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#define LINTK_RESET_SHIFT 0x1
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#define PE220X_PHY_SGMII_DPSEL_INIT(pipe) (PE220X_PHY_BASE(pipe) + 0x40260)
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#define DP_SEL 0x1
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#define PE220X_PHY_APB_RESET(pipe) (PE220X_PHY_BASE(pipe) + 0x40250)
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#define APB_RESET 0x1
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/* phy origin register */
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#define PE220X_PHY_PLL_CFG(pipe) (PE220X_PHY_BASE(pipe) + 0x30038)
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#define SINGLE_LINK 0x0
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#define PE220X_PHY_PMA_CONTROL(pipe) (PE220X_PHY_BASE(pipe) + 0x3800c)
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#define CONTROL_ENABLE 0x1
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#define CONTROL_ENABLE_MASK 0x1
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#define CONTROL_ENABLE_SHIFT 0x1
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#define PE220X_PHY_PMA_CONTROL2(pipe) (PE220X_PHY_BASE(pipe) + 0x38004)
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#define PLL0_LOCK_DONE (0x1 << 6)
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#define PE220X_PHY_PLL0_CLK_SEL(pipe) (PE220X_PHY_BASE(pipe) + 0X684)
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#define PLL_LINK_RATE_162000 0xf01
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#define PLL_LINK_RATE_270000 0x701
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#define PLL_LINK_RATE_540000 0x301
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#define PLL_LINK_RATE_810000 0x200
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#define PE220X_PHY_HSCLK0_SEL(pipe) (PE220X_PHY_BASE(pipe) + 0x18398)
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#define HSCLK_LINK_0 0x0
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#define HSCLK_LINK_1 0x1
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#define PE220X_PHY_HSCLK0_DIV(pipe) (PE220X_PHY_BASE(pipe) + 0x1839c)
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#define HSCLK_LINK_RATE_162000 0x2
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#define HSCLK_LINK_RATE_270000 0x1
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#define HSCLK_LINK_RATE_540000 0x0
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#define HSCLK_LINK_RATE_810000 0x0
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#define PE220X_PHY_PLLDRC0_CTRL(pipe) (PE220X_PHY_BASE(pipe) + 0x18394)
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#define PLLDRC_LINK0 0x1
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#define PLLDRC_LINK1 0x9
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#define PE220X_PHY_PLL0_DSM_M0(pipe) (PE220X_PHY_BASE(pipe) + 0x250)
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#define PLL0_DSM_M0 0x4
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#define PE220X_PHY_PLL0_VCOCAL_START(pipe) (PE220X_PHY_BASE(pipe) + 0x218)
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#define PLL0_VCOCAL_START 0xc5e
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#define PE220X_PHY_PLL0_VCOCAL_CTRL(pipe) (PE220X_PHY_BASE(pipe) + 0x208)
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#define PLL0_VCOCAL_CTRL 0x3
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#define PE220X_PHY_PLL0_CP_PADJ(pipe) (PE220X_PHY_BASE(pipe) + 0x690)
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#define PE220X_PHY_PLL0_CP_IADJ(pipe) (PE220X_PHY_BASE(pipe) + 0x694)
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#define PE220X_PHY_PLL0_CP_FILT_PADJ(pipe) (PE220X_PHY_BASE(pipe) + 0x698)
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#define PE220X_PHY_PLL0_INTDIV(pipe) (PE220X_PHY_BASE(pipe) + 0x240)
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#define PE220X_PHY_PLL0_FRACDIVL(pipe) (PE220X_PHY_BASE(pipe) + 0x244)
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#define PE220X_PHY_PLL0_FRACDIVH(pipe) (PE220X_PHY_BASE(pipe) + 0x248)
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#define PE220X_PHY_PLL0_HIGH_THR(pipe) (PE220X_PHY_BASE(pipe) + 0x24c)
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#define PE220X_PHY_PLL0_PDIAG_CTRL(pipe) (PE220X_PHY_BASE(pipe) + 0x680)
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#define PE220X_PHY_PLL0_VCOCAL_PLLCNT_START(pipe) (PE220X_PHY_BASE(pipe) + 0x220)
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#define PE220X_PHY_PLL0_LOCK_PEFCNT(pipe) (PE220X_PHY_BASE(pipe) + 0x270)
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#define PE220X_PHY_PLL0_LOCK_PLLCNT_START(pipe) (PE220X_PHY_BASE(pipe) + 0x278)
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#define PE220X_PHY_PLL0_LOCK_PLLCNT_THR(pipe) (PE220X_PHY_BASE(pipe) + 0x27c)
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#define PE220X_PHY_PLL0_TX_PSC_A0(pipe) (PE220X_PHY_BASE(pipe) + 0x18400)
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#define PLL0_TX_PSC_A0 0xfb
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#define PE220X_PHY_PLL0_TX_PSC_A2(pipe) (PE220X_PHY_BASE(pipe) + 0x18408)
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#define PLL0_TX_PSC_A2 0x4aa
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#define PE220X_PHY_PLL0_TX_PSC_A3(pipe) (PE220X_PHY_BASE(pipe) + 0x1840c)
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#define PLL0_TX_PSC_A3 0x4aa
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#define PE220X_PHY_PLL0_RX_PSC_A0(pipe) (PE220X_PHY_BASE(pipe) + 0x28000)
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#define PLL0_RX_PSC_A0 0x0
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#define PE220X_PHY_PLL0_RX_PSC_A2(pipe) (PE220X_PHY_BASE(pipe) + 0x28008)
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#define PLL0_RX_PSC_A2 0x0
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#define PE220X_PHY_PLL0_RX_PSC_A3(pipe) (PE220X_PHY_BASE(pipe) + 0x2800C)
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#define PLL0_RX_PSC_A3 0x0
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#define PE220X_PHY_PLL0_RX_PSC_CAL(pipe) (PE220X_PHY_BASE(pipe) + 0x28018)
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#define PLL0_RX_PSC_CAL 0x0
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#define PE220X_PHY_PLL0_XCVR_CTRL(pipe) (PE220X_PHY_BASE(pipe) + 0x183a8)
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#define PLL0_XCVR_CTRL 0xf
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#define PE220X_PHY_PLL0_RX_GCSM1_CTRL(pipe) (PE220X_PHY_BASE(pipe) + 0x28420)
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#define PLL0_RX_GCSM1_CTRL 0x0
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#define PE220X_PHY_PLL0_RX_GCSM2_CTRL(pipe) (PE220X_PHY_BASE(pipe) + 0x28440)
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#define PLL0_RX_GCSM2_CTRL 0x0
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#define PE220X_PHY_PLL0_RX_PERGCSM_CTRL(pipe) (PE220X_PHY_BASE(pipe) + 0x28460)
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#define PLL0_RX_PERGCSM_CTRL 0x0
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/* swing and emphasis */
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#define PE220X_PHY_PLL0_TX_DIAG_ACYA(pipe) (PE220X_PHY_BASE(pipe) + 0x1879c)
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#define LOCK 1
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#define UNLOCK 0
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#define PE220X_PHY_PLL0_TX_TXCC_CTRL(pipe) (PE220X_PHY_BASE(pipe) + 0x18100)
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#define TX_TXCC_CTRL 0x8a4
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#define PE220X_PHY_PLL0_TX_DRV(pipe) (PE220X_PHY_BASE(pipe) + 0x18318)
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#define TX_DRV 0x3
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#define PE220X_PHY_PLL0_TX_MGNFS(pipe) (PE220X_PHY_BASE(pipe) + 0x18140)
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#define PE220X_PHY_PLL0_TX_CPOST(pipe) (PE220X_PHY_BASE(pipe) + 0x18130)
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#endif /* __PE220X_REG_H__ */
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