122 lines
2.9 KiB
C
122 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Resource Director Technology(RDT)
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* - Cache Allocation code.
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*
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* Copyright (C) 2016 Intel Corporation
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*
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* Authors:
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* Fenghua Yu <fenghua.yu@intel.com>
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* Tony Luck <tony.luck@intel.com>
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*
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* More information about RDT be found in the Intel (R) x86 Architecture
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* Software Developer Manual June 2016, volume 3, section 17.17.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/cpu.h>
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#include <linux/kernfs.h>
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include <linux/tick.h>
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#include "internal.h"
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static bool apply_config(struct rdt_hw_domain *hw_dom,
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struct resctrl_staged_config *cfg, u32 idx,
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cpumask_var_t cpu_mask)
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{
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struct rdt_domain *dom = &hw_dom->d_resctrl;
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if (cfg->new_ctrl != hw_dom->ctrl_val[idx]) {
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cpumask_set_cpu(cpumask_any(&dom->cpu_mask), cpu_mask);
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hw_dom->ctrl_val[idx] = cfg->new_ctrl;
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return true;
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}
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return false;
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}
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int resctrl_arch_update_one(struct rdt_resource *r, struct rdt_domain *d,
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u32 closid, enum resctrl_conf_type t, u32 cfg_val)
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{
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struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);
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struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d);
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u32 idx = resctrl_get_config_index(closid, t);
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struct msr_param msr_param;
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if (!cpumask_test_cpu(smp_processor_id(), &d->cpu_mask))
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return -EINVAL;
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hw_dom->ctrl_val[idx] = cfg_val;
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msr_param.res = r;
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msr_param.low = idx;
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msr_param.high = idx + 1;
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hw_res->msr_update(d, &msr_param, r);
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return 0;
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}
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int resctrl_arch_update_domains(struct rdt_resource *r, u32 closid)
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{
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struct resctrl_staged_config *cfg;
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struct rdt_hw_domain *hw_dom;
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struct msr_param msr_param;
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enum resctrl_conf_type t;
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cpumask_var_t cpu_mask;
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struct rdt_domain *d;
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u32 idx;
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/* Walking r->domains, ensure it can't race with cpuhp */
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lockdep_assert_cpus_held();
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if (!zalloc_cpumask_var(&cpu_mask, GFP_KERNEL))
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return -ENOMEM;
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msr_param.res = NULL;
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list_for_each_entry(d, &r->domains, list) {
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hw_dom = resctrl_to_arch_dom(d);
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for (t = 0; t < CDP_NUM_TYPES; t++) {
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cfg = &hw_dom->d_resctrl.staged_config[t];
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if (!cfg->have_new_ctrl)
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continue;
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idx = resctrl_get_config_index(closid, t);
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if (!apply_config(hw_dom, cfg, idx, cpu_mask))
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continue;
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if (!msr_param.res) {
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msr_param.low = idx;
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msr_param.high = msr_param.low + 1;
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msr_param.res = r;
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} else {
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msr_param.low = min(msr_param.low, idx);
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msr_param.high = max(msr_param.high, idx + 1);
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}
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}
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}
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if (cpumask_empty(cpu_mask))
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goto done;
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/* Update resource control msr on all the CPUs. */
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on_each_cpu_mask(cpu_mask, rdt_ctrl_update, &msr_param, 1);
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done:
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free_cpumask_var(cpu_mask);
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return 0;
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}
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u32 resctrl_arch_get_config(struct rdt_resource *r, struct rdt_domain *d,
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u32 closid, enum resctrl_conf_type type)
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{
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struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d);
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u32 idx = resctrl_get_config_index(closid, type);
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return hw_dom->ctrl_val[idx];
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}
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