85 lines
1.5 KiB
C
85 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* SW64 specific irq code.
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*/
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <asm/dma.h>
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#include <asm/irq_impl.h>
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void __init
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init_IRQ(void)
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{
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/*
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* Just in case the platform init_irq() causes interrupts/mchecks
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* (as is the case with RAWHIDE, at least).
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*/
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if (is_in_host()) {
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write_csr(0xffffffffffffffffUL, CSR_PCIE_MSI0_INTEN);
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write_csr(0xffffffffffffffffUL, CSR_PCIE_MSI1_INTEN);
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write_csr(0xffffffffffffffffUL, CSR_PCIE_MSI2_INTEN);
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write_csr(0xffffffffffffffffUL, CSR_PCIE_MSI3_INTEN);
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}
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wrent(entInt, 0);
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sw64_init_irq();
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irqchip_init();
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}
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DEFINE_SPINLOCK(irq_lock);
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static void
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__enable_irq(struct irq_data *d)
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{
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}
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static void
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__disable_irq(struct irq_data *d)
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{
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}
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static unsigned int
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__startup_irq(struct irq_data *d)
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{
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__enable_irq(d);
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return 0;
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}
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static void
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__mask_and_ack_irq(struct irq_data *d)
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{
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spin_lock(&irq_lock);
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__disable_irq(d);
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spin_unlock(&irq_lock);
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}
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struct irq_chip sw64_irq_chip = {
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.name = "SW64_NODE",
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.irq_startup = __startup_irq,
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.irq_unmask = __enable_irq,
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.irq_mask = __disable_irq,
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.irq_mask_ack = __mask_and_ack_irq,
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};
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void __weak arch_init_msi_domain(struct irq_domain *parent) {}
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int __init arch_early_irq_init(void)
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{
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int i;
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for (i = 0; i < NR_IRQS; ++i) {
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irq_set_chip_and_handler(i, &sw64_irq_chip, handle_level_irq);
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irq_set_status_flags(i, IRQ_LEVEL);
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}
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arch_init_msi_domain(NULL);
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return 0;
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}
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int __init arch_probe_nr_irqs(void)
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{
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return NR_IRQS_LEGACY;
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}
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