48 lines
1.2 KiB
C
48 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_SW64_EXTABLE_H
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#define _ASM_SW64_EXTABLE_H
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/*
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* About the exception table:
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*
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* - insn is a 32-bit pc-relative offset from the faulting insn.
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* - nextinsn is a 16-bit offset off of the faulting instruction
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* (not off of the *next* instruction as branches are).
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* - errreg is the register in which to place -EFAULT.
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* - valreg is the final target register for the load sequence
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* and will be zeroed.
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*
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* Either errreg or valreg may be $31, in which case nothing happens.
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*
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* The exception fixup information "just so happens" to be arranged
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* as in a MEM format instruction. This lets us emit our three
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* values like so:
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*
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* lda valreg, nextinsn(errreg)
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*
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*/
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struct exception_table_entry {
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signed int insn;
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union exception_fixup {
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unsigned int unit;
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struct {
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signed int nextinsn : 16;
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unsigned int errreg : 5;
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unsigned int valreg : 5;
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} bits;
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} fixup;
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};
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#define ARCH_HAS_RELATIVE_EXTABLE
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extern int fixup_exception(struct pt_regs *regs, unsigned long pc);
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#define swap_ex_entry_fixup(a, b, tmp, delta) \
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do { \
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(a)->fixup.unit = (b)->fixup.unit; \
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(b)->fixup.unit = (tmp).fixup.unit; \
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} while (0)
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#endif /* _ASM_SW64_EXTABLE_H */
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