487 lines
14 KiB
C
487 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Huawei Hifc PCI Express Linux driver
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* Copyright(c) 2017 Huawei Technologies Co., Ltd
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*
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*/
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#ifndef __HIFC_WQE_H__
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#define __HIFC_WQE_H__
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#include "hifcoe_wqe.h"
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#include "hifcoe_parent_context.h"
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/* TGT WQE type */
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/* DRV->uCode via Root or Parent SQ */
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#define HIFC_SQE_FCP_TRD HIFCOE_TASK_T_TREAD
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#define HIFC_SQE_FCP_TWR HIFCOE_TASK_T_TWRITE
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#define HIFC_SQE_FCP_TRSP HIFCOE_TASK_T_TRESP
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#define HIFC_SQE_FCP_TACK HIFCOE_TASK_T_TACK
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#define HIFC_SQE_ELS_CMND HIFCOE_TASK_T_ELS
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#define HIFC_SQE_ELS_RSP HIFCOE_TASK_T_ELS_RSP
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#define HIFC_SQE_GS_CMND HIFCOE_TASK_T_GS
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#define HIFC_SQE_BLS_CMND HIFCOE_TASK_T_ABTS
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#define HIFC_SQE_FCP_IREAD HIFCOE_TASK_T_IREAD
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#define HIFC_SQE_FCP_IWRITE HIFCOE_TASK_T_IWRITE
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#define HIFC_SQE_FCP_ITMF HIFCOE_TASK_T_ITMF
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#define HIFC_SQE_SESS_RST HIFCOE_TASK_T_SESS_RESET
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#define HIFC_SQE_FCP_TMF_TRSP HIFCOE_TASK_T_TMF_RESP
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/* DRV->uCode Via CMDQ */
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#define HIFC_CMDQE_ABTS_RSP HIFCOE_TASK_T_ABTS_RSP
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#define HIFC_CMDQE_ABORT HIFCOE_TASK_T_ABORT
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#define HIFC_CMDQE_SESS_DIS HIFCOE_TASK_T_SESS_DIS
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#define HIFC_CMDQE_SESS_DEL HIFCOE_TASK_T_SESS_DEL
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/* uCode->Drv Via CMD SCQ */
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#define HIFC_SCQE_FCP_TCMND HIFCOE_TASK_T_RCV_TCMND
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#define HIFC_SCQE_ELS_CMND HIFCOE_TASK_T_RCV_ELS_CMD
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#define HIFC_SCQE_ABTS_CMD HIFCOE_TASK_T_RCV_ABTS_CMD
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#define HIFC_SCQE_FCP_IRSP HIFCOE_TASK_T_IRESP
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#define HIFC_SCQE_FCP_ITMF_RSP HIFCOE_TASK_T_ITMF_RESP
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/* uCode->Drv Via STS SCQ */
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#define HIFC_SCQE_FCP_TSTS HIFCOE_TASK_T_TSTS
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#define HIFC_SCQE_GS_RSP HIFCOE_TASK_T_RCV_GS_RSP
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#define HIFC_SCQE_ELS_RSP HIFCOE_TASK_T_RCV_ELS_RSP
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#define HIFC_SCQE_ABTS_RSP HIFCOE_TASK_T_RCV_ABTS_RSP
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#define HIFC_SCQE_ELS_RSP_STS HIFCOE_TASK_T_ELS_RSP_STS
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#define HIFC_SCQE_ABTS_RSP_STS HIFCOE_TASK_T_ABTS_RSP_STS
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#define HIFC_SCQE_ABORT_STS HIFCOE_TASK_T_ABORT_STS
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#define HIFC_SCQE_SESS_EN_STS HIFCOE_TASK_T_SESS_EN_STS
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#define HIFC_SCQE_SESS_DIS_STS HIFCOE_TASK_T_SESS_DIS_STS
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#define HIFC_SCQE_SESS_DEL_STS HIFCOE_TASK_T_SESS_DEL_STS
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#define HIFC_SCQE_SESS_RST_STS HIFCOE_TASK_T_SESS_RESET_STS
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#define HIFC_SCQE_ITMF_MARKER_STS HIFCOE_TASK_T_ITMF_MARKER_STS
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#define HIFC_SCQE_ABTS_MARKER_STS HIFCOE_TASK_T_ABTS_MARKER_STS
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#define HIFC_SCQE_FLUSH_SQ_STS HIFCOE_TASK_T_FLUSH_SQ_STS
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#define HIFC_SCQE_BUF_CLEAR_STS HIFCOE_TASK_T_BUFFER_CLEAR_STS
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#define HIFC_SCQE_CLEAR_SRQ_STS HIFCOE_TASK_T_CLEAR_SRQ_STS
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#define HIFC_LOW_32_BITS(__addr) \
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((unsigned int)((unsigned long long)(__addr) & 0xffffffff))
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#define HIFC_HIGH_32_BITS(__addr)\
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((unsigned int)(((unsigned long long)(__addr) >> 32) & 0xffffffff))
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/* Error Code from SCQ */
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#define HIFC_COMPLETION_STATUS_SUCCESS FCOE_CQE_COMPLETED
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#define HIFC_COMPLETION_STATUS_ABORTED_SETUP_FAIL FCOE_IMMI_CMDPKT_SETUP_FAIL
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#define HIFC_COMPLETION_STATUS_TIMEOUT FCOE_ERROR_CODE_E_D_TIMER_EXPIRE
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#define HIFC_COMPLETION_STATUS_DIF_ERROR FCOE_ERROR_CODE_DATA_DIFX_FAILED
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#define HIFC_COMPLETION_STATUS_DATA_OOO FCOE_ERROR_CODE_DATA_OOO_RO
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#define HIFC_COMPLETION_STATUS_DATA_OVERFLOW \
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FCOE_ERROR_CODE_DATA_EXCEEDS_DATA2TRNS
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#define HIFC_SCQE_INVALID_CONN_ID 0xffff
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#define HIFC_GET_SCQE_TYPE(scqe) ((scqe)->common.ch.wd0.task_type)
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#define HIFC_GET_SCQE_STATUS(scqe) ((scqe)->common.ch.wd0.err_code)
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#define HIFC_GET_SCQE_REMAIN_CNT(scqe) ((scqe)->common.ch.wd0.cqe_remain_cnt)
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#define HIFC_GET_SCQE_CONN_ID(scqe) ((scqe)->common.conn_id)
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#define HIFC_GET_WQE_TYPE(wqe) ((wqe)->ts_sl.task_type)
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#define HIFC_WQE_IS_IO(wqe) \
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(HIFC_GET_WQE_TYPE(wqe) != HIFC_SQE_SESS_RST)
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#define HIFC_SCQE_HAS_ERRCODE(scqe) \
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(HIFC_GET_SCQE_STATUS(scqe) != HIFC_COMPLETION_STATUS_SUCCESS)
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#define HIFC_SCQE_ERR_TO_CM(scqe)\
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(HIFC_GET_SCQE_STATUS(scqe) != FCOE_ELS_GS_RSP_EXCH_CHECK_FAIL)
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#define HIFC_SCQE_CONN_ID_VALID(scqe) \
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(HIFC_GET_SCQE_CONN_ID(scqe) != HIFC_SCQE_INVALID_CONN_ID)
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#define HIFC_WQE_SECTION_CHUNK_SIZE 8 /* 8 bytes' chunk */
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#define HIFC_T_RESP_WQE_CTR_TSL_SIZE 15 /* 8 bytes' chunk */
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#define HIFC_T_RD_WR_WQE_CTR_TSL_SIZE 9 /* 8 bytes' chunk */
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#define HIFC_T_RD_WR_WQE_CTR_BDSL_SIZE 4 /* 8 bytes' chunk */
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#define HIFC_T_RD_WR_WQE_CTR_CTRLSL_SIZE 1 /* 8 bytes' chunk */
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#define HIFC_WQE_SGE_ENTRY_NUM 2 /* BD SGE and DIF SGE count */
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#define HIFC_WQE_SGE_DIF_ENTRY_NUM 1 /* DIF SGE count */
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#define HIFC_WQE_SGE_LAST_FLAG 1
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#define HIFC_WQE_SGE_NOT_LAST_FLAG 0
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#define HIFC_WQE_SGE_EXTEND_FLAG 1
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#define HIFC_WQE_SGE_NOT_EXTEND_FLAG 0
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#define HIFC_FCP_TMF_PORT_RESET 0
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#define HIFC_FCP_TMF_LUN_RESET 1
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#define HIFC_FCP_TMF_TGT_RESET 2
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#define HIFC_FCP_TMF_RSVD 3
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#define HIFC_NO_OFFLOAD 0
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#define HIFC_HAVE_OFFLOAD 1
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#define HIFC_QID_SQ 0
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#define HIFC_ADJUST_DATA(old_val, new_val) ((old_val) = (new_val))
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#define HIFC_GET_RESET_TYPE(tmf_flag, reset_flag) \
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do { \
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switch (tmf_flag) { \
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case UNF_FCP_TM_ABORT_TASK_SET: \
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case UNF_FCP_TM_LOGICAL_UNIT_RESET: \
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reset_flag = HIFC_FCP_TMF_LUN_RESET; \
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break; \
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case UNF_FCP_TM_TARGET_RESET: \
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reset_flag = HIFC_FCP_TMF_TGT_RESET; \
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break; \
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case UNF_FCP_TM_CLEAR_TASK_SET: \
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reset_flag = HIFC_FCP_TMF_PORT_RESET; \
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break; \
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default: \
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reset_flag = HIFC_FCP_TMF_RSVD; \
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} \
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} while (0)
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/*
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* nic_wqe_ctrl_sec table define
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*/
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struct nic_wqe_ctrl_sec {
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union {
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struct {
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#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
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/* marks ownership of WQE */
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u32 owner : 1;
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/* Control Section Length */
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u32 ctrl_sec_len : 2;
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/* Completion Section Length */
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u32 completion_sec_len : 2;
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/* DIF Section Length */
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u32 dif_sec_len : 3;
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/*
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* Completion is Required - marks CQE generation request
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* per WQE
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*/
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u32 cr : 1;
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/* Data Format - format of BDS */
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u32 df : 1;
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/* Virtual Address */
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u32 va : 1;
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/* Task Section Length */
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u32 task_sec_len : 5;
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/* Completion Format */
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u32 cf : 1;
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u32 wf : 1;
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/* reserved */
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u32 rsvd : 4;
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/* Driver Section Length */
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u32 drv_sec_len : 2;
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/* Buffer Descriptors Section Length */
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u32 buf_desc_sec_len : 8;
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#else
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/* Buffer Descriptors Section Length */
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u32 buf_desc_sec_len : 8;
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/* Driver Section Length */
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u32 drv_sec_len : 2;
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/* reserved */
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u32 rsvd : 4;
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u32 wf : 1;
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/* Completion Format */
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u32 cf : 1;
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/* Task Section Length */
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u32 task_sec_len : 5;
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/* Virtual Address */
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u32 va : 1;
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/* Data Format - format of BDS */
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u32 df : 1;
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/*
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* Completion is Required - marks CQE generation request
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* per WQE
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*/
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u32 cr : 1;
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/* DIF Section Length */
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u32 dif_sec_len : 3;
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/* Completion Section Length */
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u32 completion_sec_len : 2;
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/* Control Section Length */
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u32 ctrl_sec_len : 2;
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/* marks ownership of WQE */
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u32 owner : 1;
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#endif
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} bs;
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u32 dw;
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};
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};
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/*
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* nic_rq_sge_sec table define
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*/
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struct nic_rq_sge_sec {
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/* packet buffer address high */
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u32 wb_addr_high;
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/* packet buffer address low */
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u32 wb_addr_low;
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union {
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struct {
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#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
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u32 rsvd : 1;
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/* SGE length */
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u32 length : 31;
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#else
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/* SGE length */
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u32 length : 31;
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u32 rsvd : 1;
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#endif
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} bs0;
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u32 dw0;
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};
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union {
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struct {
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#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
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/* 0:list,1:last */
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u32 list : 1;
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/* 0:normal,1:pointer to next SGE */
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u32 extension : 1;
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/* key or unsed */
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u32 key : 30;
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#else
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/* key or unsed */
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u32 key : 30;
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/* 0:normal,1:pointer to next SGE */
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u32 extension : 1;
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/* 0:list,1:last */
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u32 list : 1;
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#endif
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} bs1;
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u32 dw1;
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};
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};
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/*
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* nic_rq_bd_sec table define
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*/
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struct nic_rq_bd_sec {
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/* packet buffer address high */
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u32 pkt_buf_addr_high;
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/* packet buffer address low */
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u32 pkt_buf_addr_low;
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};
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/*
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* nic_rq_wqe table define
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*/
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struct nic_rq_wqe {
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struct nic_wqe_ctrl_sec rq_wqe_ctrl_sec;
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u32 rsvd;
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struct nic_rq_sge_sec rx_sge;
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struct nic_rq_bd_sec pkt_buf_addr;
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};
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/* Link WQE structure */
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struct hifc_link_wqe_s {
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union {
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struct {
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unsigned int rsv1 : 14;
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unsigned int wf : 1;
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unsigned int rsv2 : 14;
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unsigned int ctrlsl : 2;
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unsigned int o : 1;
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} wd0;
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u32 val_wd0;
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};
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union {
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struct {
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unsigned int msn : 16;
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unsigned int dump_msn : 15;
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/* lp means whether O bit is overturn */
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unsigned int lp : 1;
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} wd1;
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unsigned int val_wd1;
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};
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unsigned int next_page_addr_hi;
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unsigned int next_page_addr_lo;
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};
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struct hifc_root_rq_complet_info_s {
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#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
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unsigned int done : 1; /* done bit,ucode will set to 1 */
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unsigned int rsvd1 : 6;
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unsigned int fc_pkt : 1; /* Marks whether the packet is fc type */
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unsigned int rsvd2 : 24;
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#else
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unsigned int rsvd2 : 24;
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unsigned int fc_pkt : 1; /* Marks whether the packet is fc type */
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unsigned int rsvd1 : 6;
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unsigned int done : 1; /* done bit,ucode will set to 1 */
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#endif
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#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
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unsigned short buf_length;
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unsigned short exch_id;
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#else
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unsigned short exch_id;
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unsigned short buf_length;
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#endif
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#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
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unsigned short sts_only; /* If only CMPL SECTION */
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unsigned short status; /* 0:no err;!0:others */
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#else
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unsigned short status; /* 0:no err;!0:others */
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unsigned short sts_only; /* If only CMPL SECTION */
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#endif
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unsigned int magic_num;
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unsigned int rsvd[4];
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};
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/* Parent SQ WQE */
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struct hifc_root_sge_s {
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unsigned int buf_addr_hi;
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unsigned int buf_addr_lo;
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struct {
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#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
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unsigned int ext_flag : 1;
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unsigned int buf_len : 31;
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#else
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unsigned int buf_len : 31;
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unsigned int ext_flag : 1;
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#endif
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} wd0;
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struct {
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unsigned int rsvd;
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} wd1;
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};
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/* Root SQ WQE Task Section structure for FC */
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struct hifc_root_sqe_task_section_s {
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struct {
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#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
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unsigned int task_type : 8;
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/* 1:offload enable,0:offload disable. */
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unsigned int off_load : 1;
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unsigned int port_id : 4;
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unsigned int host_id : 2;
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unsigned int rsvd1 : 1;
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unsigned int exch_id : 16;
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#else
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unsigned int exch_id : 16;
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unsigned int rsvd1 : 1;
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unsigned int host_id : 2;
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unsigned int port_id : 4;
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unsigned int off_load : 1;
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unsigned int task_type : 8;
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#endif
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} fc_dw0;
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union {
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unsigned int context_gpa_hi;
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unsigned int magic_num;
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} fc_dw1;
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struct {
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unsigned int context_gpa_lo;
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} fc_dw2;
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struct {
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#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
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unsigned short scq_num; /* SCQ num */
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unsigned short rport_index; /* RPort */
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#else
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unsigned short rport_index; /* RPort */
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unsigned short scq_num; /* SCQ num */
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#endif
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} fc_dw3;
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struct {
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#if (__BYTE_ORDER__ == __BIG_ENDIAN__)
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unsigned int pkt_type : 1; /* pkt type 0:ETH, 1:FC */
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unsigned int pkt_cos : 3;
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unsigned int rsvd2 : 1;
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unsigned int csize : 2;
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unsigned int service_type : 5;
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unsigned int parent_xid : 20;
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#else
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unsigned int parent_xid : 20;
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unsigned int service_type : 5;
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unsigned int csize : 2;
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unsigned int rsvd2 : 1;
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unsigned int pkt_cos : 3; /* pkt cos,4:ETH, 0:FC */
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unsigned int pkt_type : 1; /* pkt type 0:ETH, 1:FC */
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#endif
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} fc_dw4;
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struct {
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unsigned int rsvd;
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} fc_dw5;
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};
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/* Root SQ WQE */
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struct hifc_root_sqe_s {
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/* Control Section */
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struct hifcoe_wqe_ctrl_s ctrl_section;
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struct hifc_root_sqe_task_section_s task_section;
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struct hifc_root_sge_s sge;
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struct hifc_root_sge_s ctx_sge;
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};
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/* Parent SQ WQE and Root SQ WQE Related function */
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void hifc_build_service_wqe_ctrl_section(struct hifcoe_wqe_ctrl_s *v_wqe_cs,
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unsigned int ts_size,
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unsigned int bdsl);
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void hifc_build_service_wqe_ts_common(struct hifcoe_sqe_ts_s *v_sqe_ts,
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unsigned int rport_index,
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unsigned short local_xid,
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unsigned short remote_xid,
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unsigned short data_len);
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void hifc_build_els_gs_wqe_sge(struct hifcoe_sqe_s *v_sqe, void *v_buf_addr,
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unsigned long long v_phyaddr,
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unsigned int buf_len,
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unsigned int xid, void *v_hba);
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void hifc_build_els_wqe_ts_req(struct hifcoe_sqe_s *v_sqe,
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void *v_sq_info, unsigned short cmnd,
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unsigned int v_scqn, void *v_frame_pld);
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void hifc_build_els_wqe_ts_rsp(struct hifcoe_sqe_s *v_sqe, void *v_sq_info,
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void *v_frame_pld, unsigned short type,
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unsigned short cmnd, unsigned int v_scqn);
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void hifc_build_els_wqe_ts_magic_num(struct hifcoe_sqe_s *v_sqe,
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unsigned short els_cmnd_type,
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unsigned int v_magic_num);
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void hifc_build_gs_wqe_ts_req(struct hifcoe_sqe_s *v_sqe,
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unsigned int magic_num);
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void hifc_build_bls_wqe_ts_req(struct hifcoe_sqe_s *v_sqe,
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unsigned int abts_param,
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unsigned int magic_num);
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void hifc_build_service_wqe_root_ts(void *v_hba,
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struct hifc_root_sqe_s *v_rt_sqe,
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unsigned int rx_id, unsigned int rport_id,
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unsigned int scq_num);
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void hifc_build_service_wqe_root_sge(struct hifc_root_sqe_s *v_rt_sqe,
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void *v_buf_addr,
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unsigned long long v_phyaddr,
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unsigned int buf_len,
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void *v_hba);
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void hifc_build_els_wqe_root_offload(struct hifc_root_sqe_s *v_rt_sqe,
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dma_addr_t ctx_addr,
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unsigned int xid);
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void hifc_build_wqe_owner_pmsn(struct hifcoe_wqe_ctrl_s *v_wqe_cs,
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unsigned short owner,
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unsigned short pmsn);
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void hifc_convert_parent_wqe_to_big_endian(struct hifcoe_sqe_s *v_sqe);
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void hifc_convert_root_wqe_to_big_endian(struct hifc_root_sqe_s *v_sqe);
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void hifc_build_icmnd_wqe_ts(void *v_hba, struct unf_frame_pkg_s *v_pkg,
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struct hifcoe_sqe_ts_s *v_sqe_ts);
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void hifc_build_icmnd_wqe_ts_header(struct unf_frame_pkg_s *v_pkg,
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struct hifcoe_sqe_s *v_sqe,
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unsigned char v_task_type,
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unsigned short v_exi_base,
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unsigned char v_port_idx);
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void hifc_build_cmdqe_common(union hifc_cmdqe_u *cmdqe,
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enum hifcoe_task_type_e task_type,
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unsigned short rx_id);
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void hifc_build_srq_wqe_ctrls(struct hifcoe_rqe_s *v_rqe, unsigned short owner,
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unsigned short pmsn);
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void hifc_build_common_wqe_ctrls(struct hifcoe_wqe_ctrl_s *v_ctrl_sl,
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unsigned char v_task_len);
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void hifc_build_service_wqe_ctx_sge(struct hifc_root_sqe_s *v_rt_sqe,
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unsigned long long v_ctx_addr,
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unsigned int buf_len);
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void hifc_build_trd_twr_wqe_ctrls(struct unf_frame_pkg_s *v_pkg,
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struct hifcoe_sqe_s *v_sqe);
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#endif
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