183 lines
3.3 KiB
C
183 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Huawei Hifc PCI Express Linux driver
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* Copyright(c) 2017 Huawei Technologies Co., Ltd
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*
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*/
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#ifndef __CHIPIF_SML_COUNTER_H__
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#define __CHIPIF_SML_COUNTER_H__
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#define CHIPIF_FUNC_PF 0
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#define CHIPIF_FUNC_VF 1
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#define CHIPIF_FUNC_PPF 2
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#define CHIPIF_ACK 1
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#define CHIPIF_NOACK 0
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#define CHIPIF_SM_CTR_OP_READ 0x2
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#define CHIPIF_SM_CTR_OP_READ_CLEAR 0x6
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#define CHIPIF_SM_CTR_OP_WRITE 0x3
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#define SMALL_CNT_READ_RSP_SIZE 16
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/* request head */
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union chipif_sml_ctr_req_head_u {
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struct {
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u32 pad:15;
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u32 ack:1;
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u32 op_id:5;
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u32 instance:6;
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u32 src:5;
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} bs;
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u32 value;
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};
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/* counter read request struct */
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struct chipif_sml_ctr_rd_req_s {
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u32 extra;
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union chipif_sml_ctr_req_head_u head;
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u32 ctr_id;
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u32 initial;
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u32 pad;
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};
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/* counter read response union */
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union ctr_rd_rsp_u {
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struct {
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u32 value1:16;
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u32 pad0:16;
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u32 pad1[3];
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} bs_ss16_rsp;
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struct {
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u32 value1;
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u32 pad[3];
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} bs_ss32_rsp;
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struct {
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u32 value1:20;
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u32 pad0:12;
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u32 value2:12;
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u32 pad1:20;
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u32 pad2[2];
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} bs_sp_rsp;
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struct {
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u32 value1;
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u32 value2;
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u32 pad[2];
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} bs_bs64_rsp;
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struct {
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u32 val1_h;
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u32 val1_l;
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u32 val2_h;
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u32 val2_l;
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} bs_bp64_rsp;
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};
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/* resopnse head */
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union sml_ctr_rsp_head_u {
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struct {
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u32 pad:30; /* reserve */
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u32 code:2; /* error code */
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} bs;
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u32 value;
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};
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/* counter write request struct */
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struct chipif_sml_ctr_wr_req_s {
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u32 extra;
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union chipif_sml_ctr_req_head_u head;
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u32 ctr_id;
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u32 rsv1;
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u32 rsv2;
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u32 value1_h;
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u32 value1_l;
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u32 value2_h;
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u32 value2_l;
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};
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/* counter write response struct */
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struct chipif_sml_ctr_wr_rsp_s {
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union sml_ctr_rsp_head_u head;
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u32 pad[3];
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};
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enum HIFC_CSR_API_DATA_OPERATION_ID {
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HIFC_CSR_OPERATION_WRITE_CSR = 0x1E,
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HIFC_CSR_OPERATION_READ_CSR = 0x1F
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};
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enum HIFC_CSR_API_DATA_NEED_RESPONSE_DATA {
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HIFC_CSR_NO_RESP_DATA = 0,
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HIFC_CSR_NEED_RESP_DATA = 1
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};
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enum HIFC_CSR_API_DATA_DATA_SIZE {
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HIFC_CSR_DATA_SZ_32 = 0,
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HIFC_CSR_DATA_SZ_64 = 1
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};
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struct hifc_csr_request_api_data {
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u32 dw0;
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union {
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struct {
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u32 reserved1:13;
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/* this field indicates the write/read data size:
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* 2'b00: 32 bits
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* 2'b01: 64 bits
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* 2'b10~2'b11:reserved
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*/
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u32 data_size:2;
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/* this field indicates that requestor expect receive a
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* response data or not.
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* 1'b0: expect not to receive a response data.
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* 1'b1: expect to receive a response data.
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*/
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u32 need_response:1;
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/* this field indicates the operation that the requestor
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* expected.
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* 5'b1_1110: write value to csr space.
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* 5'b1_1111: read register from csr space.
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*/
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u32 operation_id:5;
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u32 reserved2:6;
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/* this field specifies the Src node ID for this API
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* request message.
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*/
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u32 src_node_id:5;
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} bits;
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u32 val32;
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} dw1;
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union {
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struct {
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/* it specifies the CSR address. */
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u32 csr_addr:26;
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u32 reserved3:6;
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} bits;
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u32 val32;
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} dw2;
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/* if data_size=2'b01, it is high 32 bits of write data. else, it is
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* 32'hFFFF_FFFF.
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*/
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u32 csr_write_data_h;
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/* the low 32 bits of write data. */
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u32 csr_write_data_l;
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};
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int hifc_sm_ctr_rd32(void *hwdev, u8 node, u8 instance, u32 ctr_id, u32 *value);
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int hifc_sm_ctr_rd64(void *hwdev, u8 node, u8 instance, u32 ctr_id, u64 *value);
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int hifc_sm_ctr_rd64_pair(void *hwdev, u8 node, u8 instance,
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u32 ctr_id, u64 *value1, u64 *value2);
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#endif
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