235 lines
6.8 KiB
C
235 lines
6.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Huawei Hifc PCI Express Linux driver
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* Copyright(c) 2017 Huawei Technologies Co., Ltd
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*
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*/
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#ifndef __HIFC_HBA_H__
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#define __HIFC_HBA_H__
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#include "unf_common.h"
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#include "hifc_queue.h"
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#include "hifc_api_cmd.h"
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#include "hifc_mgmt.h"
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#define HIFC_PCI_VENDOR_ID_MASK (0xffff)
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#define HIFC_LOWLEVEL_DEFAULT_LOOP_BB_CREDIT 8
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#define HIFC_LOWLEVEL_DEFAULT_32G_BB_CREDIT 255
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#define HIFC_LOWLEVEL_DEFAULT_16G_BB_CREDIT 255
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#define HIFC_LOWLEVEL_DEFAULT_842G_BB_CREDIT 255
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#define HIFC_LOWLEVEL_DEFAULT_BB_SCN 0
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#define HIFC_LOWLEVEL_DEFAULT_32G_ESCH_VALUE 28081
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#define HIFC_LOWLEVEL_DEFAULT_16G_ESCH_VALUE 14100
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#define HIFC_LOWLEVEL_DEFAULT_842G_ESCH_VALUE 7000
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#define HIFC_LOWLEVEL_DEFAULT_ESCH_BUS_SIZE 0x2000
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#define HIFC_SMARTIO_WORK_MODE_FC 0x1
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#define UNF_FUN_ID_MASK 0x07
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#define UNF_HIFC_FC 0x01
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#define UNF_HIFC_MAXNPIV_NUM 64
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#define HIFC_MAX_COS_NUM 8
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#define HIFC_PCI_VENDOR_ID_HUAWEI 0x19e5
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#define HIFC_SCQ_CNTX_SIZE 32
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#define HIFC_SRQ_CNTX_SIZE 64
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#define HIFC_PORT_INIT_TIME_SEC_MAX 1
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#define HIFC_PORT_NAME_LABEL "hifc"
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#define HIFC_PORT_NAME_STR_LEN 16
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#define HIFC_MAX_PROBE_PORT_NUM 64
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#define HIFC_PORT_NUM_PER_TABLE 64
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#define HIFC_MAX_CARD_NUM 32
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#define HIFC_HBA_PORT_MAX_NUM HIFC_MAX_PROBE_PORT_NUM
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/* Heart Lost Flag */
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#define HIFC_EVENT_HEART_LOST 0
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#define HIFC_GET_HBA_PORT_ID(__hba) ((__hba)->port_index)
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#define HIFC_HBA_NOT_PRESENT(__hba) ((__hba)->dev_present == UNF_FALSE)
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struct hifc_port_cfg_s {
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unsigned int port_id; /* Port ID */
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unsigned int port_mode; /* Port mode:INI(0x20) TGT(0x10) BOTH(0x30) */
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unsigned int port_topology; /* Port topo:0x3:loop,0xc:p2p,0xf:auto */
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unsigned int port_alpa; /* Port ALPA */
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unsigned int max_queue_depth;/* Max Queue depth Registration to SCSI */
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unsigned int sest_num; /* IO burst num:512-4096 */
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unsigned int max_login; /* Max Login Session. */
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unsigned int node_name_hi; /* nodename high 32 bits */
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unsigned int node_name_lo; /* nodename low 32 bits */
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unsigned int port_name_hi; /* portname high 32 bits */
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unsigned int port_name_lo; /* portname low 32 bits */
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/* Port speed 0:auto 4:4Gbps 8:8Gbps 16:16Gbps */
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unsigned int port_speed;
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unsigned int interrupt_delay; /* Delay times(ms) in interrupt */
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unsigned int tape_support; /* tape support */
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};
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#define HIFC_VER_INFO_SIZE 128
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struct hifc_drv_version_s {
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char ver[HIFC_VER_INFO_SIZE];
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};
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struct hifc_card_info_s {
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unsigned int card_num : 8;
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unsigned int func_num : 8;
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unsigned int base_func : 8;
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/*
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* Card type:UNF_FC_SERVER_BOARD_32_G(6) 32G mode,
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* UNF_FC_SERVER_BOARD_16_G(7)16G mode
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*/
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unsigned int card_type : 8;
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};
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struct hifc_card_num_manage_s {
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int is_removing;
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unsigned int port_count;
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unsigned long long card_number;
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};
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struct hifc_led_state_s {
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unsigned char green_speed_led;
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unsigned char yellow_speed_led;
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unsigned char ac_led;
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unsigned char reserved;
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};
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enum hifc_queue_set_stage_e {
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HIFC_QUEUE_SET_STAGE_INIT = 0,
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HIFC_QUEUE_SET_STAGE_SCANNING,
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HIFC_QUEUE_SET_STAGE_FLUSHING,
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HIFC_QUEUE_SET_STAGE_FLUSHDONE,
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HIFC_QUEUE_SET_STAGE_BUTT
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};
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struct hifc_srq_delay_info_s {
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unsigned char srq_delay_flag; /* Check whether need to delay */
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unsigned char root_rq_rcvd_flag;
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unsigned short rsd;
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spinlock_t srq_lock;
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struct unf_frame_pkg_s pkg;
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struct delayed_work del_work;
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};
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struct hifc_fw_ver_detail_s {
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unsigned char ucode_ver[HIFC_VER_LEN];
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unsigned char ucode_compile_time[HIFC_COMPILE_TIME_LEN];
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unsigned char up_ver[HIFC_VER_LEN];
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unsigned char up_compile_time[HIFC_COMPILE_TIME_LEN];
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unsigned char boot_ver[HIFC_VER_LEN];
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unsigned char boot_compile_time[HIFC_COMPILE_TIME_LEN];
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};
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/* get wwpn and wwnn */
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struct hifc_chip_info_s {
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unsigned char work_mode;
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unsigned char tape_support;
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unsigned long long wwpn;
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unsigned long long wwnn;
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};
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struct hifc_hba_s {
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struct pci_dev *pci_dev;
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void *hw_dev_handle;
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struct fc_service_cap fc_service_cap;
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struct hifc_scq_info_s scq_info[HIFC_TOTAL_SCQ_NUM];
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struct hifc_srq_info_s els_srq_info;
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/* PCI IO Memory */
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void __iomem *bar0;
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unsigned int bar0_len;
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struct hifc_root_info_s root_info;
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struct hifc_parent_queue_mgr_s *parent_queue_mgr;
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/* Link list Sq WqePage Pool */
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struct hifc_sq_wqe_page_pool_s sq_wpg_pool;
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enum hifc_queue_set_stage_e q_set_stage;
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unsigned int next_clearing_sq;
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unsigned int default_sq_id;
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/* Port parameters, Obtained through firmware */
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unsigned short q_s_max_count;
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unsigned char port_type; /* FC Port */
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unsigned char port_index; /* Phy Port */
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unsigned int default_scqn;
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unsigned char chip_type; /* chiptype:Smart or fc */
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unsigned char work_mode;
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struct hifc_card_info_s card_info;
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char port_name[HIFC_PORT_NAME_STR_LEN];
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unsigned int probe_index;
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unsigned short exit_base;
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unsigned short exit_count;
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unsigned short image_count;
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unsigned char vpid_start;
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unsigned char vpid_end;
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spinlock_t flush_state_lock;
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int in_flushing;
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struct hifc_port_cfg_s port_cfg; /* Obtained through Config */
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void *lport; /* Used in UNF level */
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unsigned char sys_node_name[UNF_WWN_LEN];
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unsigned char sys_port_name[UNF_WWN_LEN];
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struct completion hba_init_complete;
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struct completion mbox_complete;
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unsigned short removing;
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int sfp_on;
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int dev_present;
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int heart_status;
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spinlock_t hba_lock;
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unsigned int port_topo_cfg;
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unsigned int port_bbscn_cfg;
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unsigned int port_loop_role;
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unsigned int port_speed_cfg;
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unsigned int max_support_speed;
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unsigned char remote_rttov_tag;
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unsigned char remote_edtov_tag;
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unsigned short compared_bbscn;
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unsigned short remote_bbcredit;
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unsigned int compared_edtov_val;
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unsigned int compared_ratov_val;
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enum unf_act_topo_e active_topo;
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unsigned int active_port_speed;
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unsigned int active_rx_bb_credit;
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unsigned int active_bb_scn;
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unsigned int phy_link;
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unsigned int fcp_conf_cfg;
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/* loop */
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unsigned char active_al_pa;
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unsigned char loop_map_valid;
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unsigned char loop_map[UNF_LOOPMAP_COUNT];
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unsigned int cos_bit_map;
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atomic_t cos_rport_cnt[HIFC_MAX_COS_NUM];
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struct hifc_led_state_s led_states;
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unsigned int fec_status;
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struct workqueue_struct *work_queue;
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unsigned long long reset_time;
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struct hifc_srq_delay_info_s delay_info;
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};
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enum drv_port_entity_type_e {
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DRV_PORT_ENTITY_TYPE_PHYSICAL = 0,
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DRV_PORT_ENTITY_TYPE_VIRTUAL = 1,
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DRV_PORT_ENTITY_TYPE_BUTT
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};
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extern struct hifc_hba_s *hifc_hba[HIFC_HBA_PORT_MAX_NUM];
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extern spinlock_t probe_spin_lock;
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extern unsigned long probe_bit_map[HIFC_MAX_PROBE_PORT_NUM /
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HIFC_PORT_NUM_PER_TABLE];
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unsigned int hifc_port_reset(struct hifc_hba_s *v_hba);
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void hifc_flush_scq_ctx(struct hifc_hba_s *v_hba);
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void hifc_set_hba_flush_state(struct hifc_hba_s *v_hba, int in_flush);
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void hifc_get_total_probed_num(unsigned int *v_probe_cnt);
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#endif
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