644 lines
16 KiB
C
644 lines
16 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Huawei Hifc PCI Express Linux driver
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* Copyright(c) 2017 Huawei Technologies Co., Ltd
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*
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*/
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#ifndef __HIFC_CHIPITF_H__
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#define __HIFC_CHIPITF_H__
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#include "unf_log.h"
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#include "hifc_utils.h"
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#include "hifc_module.h"
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#include "hifc_service.h"
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/* CONF_API_CMND */
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#define HIFC_MBOX_CONFIG_API 0x00
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#define HIFC_MBOX_CONFIG_API_STS 0xA0
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/* GET_CHIP_INFO_API_CMD */
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#define HIFC_MBOX_GET_CHIP_INFO 0x01
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#define HIFC_MBOX_GET_CHIP_INFO_STS 0xA1
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/* PORT_RESET */
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#define HIFC_MBOX_PORT_RESET 0x02
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#define HIFC_MBOX_PORT_RESET_STS 0xA2
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/* SFP_SWITCH_API_CMND */
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#define HIFC_MBOX_PORT_SWITCH 0x03
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#define HIFC_MBOX_PORT_SWITCH_STS 0xA3
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/* GET_SFP_INFO */
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#define HIFC_MBOX_GET_SFP_INFO 0x04
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#define HIFC_MBOX_GET_SFP_INFO_STS 0xA4
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/* CONF_AF_LOGIN_API_CMND */
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#define HIFC_MBOX_CONFIG_LOGIN_API 0x06
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#define HIFC_MBOX_CONFIG_LOGIN_API_STS 0xA6
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/* BUFFER_CLEAR_DONE_CMND */
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#define HIFC_MBOX_BUFFER_CLEAR_DONE 0x07
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#define HIFC_MBOX_BUFFER_CLEAR_DONE_STS 0xA7
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#define HIFC_MBOX_GET_ERR_CODE 0x08
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#define HIFC_MBOX_GET_ERR_CODE_STS 0xA8
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#define HIFC_MBOX_GET_UP_STATE 0x09
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#define HIFC_MBOX_GET_UP_STATE_STS 0xA9
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/* LOOPBACK MODE */
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#define HIFC_MBOX_LOOPBACK_MODE 0x0A
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#define HIFC_MBOX_LOOPBACK_MODE_STS 0xAA
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/* REG RW MODE */
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#define HIFC_MBOX_REG_RW_MODE 0x0B
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#define HIFC_MBOX_REG_RW_MODE_STS 0xAB
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/* GET CLEAR DONE STATE */
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#define HIFC_MBOX_GET_CLEAR_STATE 0x0E
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#define HIFC_MBOX_GET_CLEAR_STATE_STS 0xAE
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/* GET UP & UCODE VER */
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#define HIFC_MBOX_GET_FW_VERSION 0x0F
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#define HIFC_MBOX_GET_FW_VERSION_STS 0xAF
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/* CONFIG TIMER */
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#define HIFC_MBOX_CONFIG_TIMER 0x10
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#define HIFC_MBOX_CONFIG_TIMER_STS 0xB0
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/* CONFIG SRQC */
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#define HIFC_MBOX_CONFIG_SRQC 0x11
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#define HIFC_MBOX_CONFIG_SRQC_STS 0xB1
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/* Led Test */
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#define HIFC_MBOX_LED_TEST 0x12
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#define HIFC_MBOX_LED_TEST_STS 0xB2
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/* set esch */
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#define HIFC_MBOX_SET_ESCH 0x13
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#define HIFC_MBOX_SET_ESCH_STS 0xB3
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/* set get tx serdes */
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#define HIFC_MBOX_SET_GET_SERDES_TX 0x14
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#define HIFC_MBOX_SET_GET_SERDES_TX_STS 0xB4
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/* get rx serdes */
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#define HIFC_MBOX_GET_SERDES_RX 0x15
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#define HIFC_MBOX_GET_SERDES_RX_STS 0xB5
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/* i2c read write */
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#define HIFC_MBOX_I2C_WR_RD 0x16
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#define HIFC_MBOX_I2C_WR_RD_STS 0xB6
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/* Set FEC Enable */
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#define HIFC_MBOX_CONFIG_FEC 0x17
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#define HIFC_MBOX_CONFIG_FEC_STS 0xB7
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/* GET UCODE STATS CMD */
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#define HIFC_MBOX_GET_UCODE_STAT 0x18
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#define HIFC_MBOX_GET_UCODE_STAT_STS 0xB8
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/* gpio read write */
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#define HIFC_MBOX_GPIO_WR_RD 0x19
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#define HIFC_MBOX_GPIO_WR_RD_STS 0xB9
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/* GET PORT INFO CMD */
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#define HIFC_MBOX_GET_PORT_INFO 0x20
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#define HIFC_MBOX_GET_PORT_INFO_STS 0xC0
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/* save hba info CMD */
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#define HIFC_MBOX_SAVE_HBA_INFO 0x24
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#define HIFC_MBOX_SAVE_HBA_INFO_STS 0xc4
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#define HIFC_MBOX_FLASH_DATA_MGMT 0x25
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#define HIFC_MBOX_FLASH_DATA_MGMT_STS 0xc5
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/* FCOE: DRV->UP */
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#define HIFC_MBOX_SEND_ELS_CMD 0x2A
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#define HIFC_MBOX_SEND_VPORT_INFO 0x2B
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/* FC: UP->DRV */
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#define HIFC_MBOX_RECV_FC_LINKUP 0x40
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#define HIFC_MBOX_RECV_FC_LINKDOWN 0x41
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#define HIFC_MBOX_RECV_FC_DELCMD 0x42
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#define HIFC_MBOX_RECV_FC_ERROR 0x43
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#define LOOP_MAP_VALID 1
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#define LOOP_MAP_INVALID 0
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#define HIFC_MBOX_SIZE 1024
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#define HIFC_MBOX_HEADER_SIZE 4
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#define ATUOSPEED 1
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#define FIXEDSPEED 0
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#define UNDEFINEOPCODE 0
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#define VALUEMASK_L 0x00000000FFFFFFFF
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#define VALUEMASK_H 0xFFFFFFFF00000000
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#define STATUS_OK 0
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#define STATUS_FAIL 1
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enum hifc_drv_2_up_unblock_msg_cmd_code_e {
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HIFC_SEND_ELS_CMD,
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HIFC_SEND_ELS_CMD_FAIL,
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HIFC_RCV_ELS_CMD_RSP,
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HIFC_SEND_CONFIG_LOGINAPI,
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HIFC_SEND_CONFIG_LOGINAPI_FAIL,
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HIFC_RCV_CONFIG_LOGIN_API_RSP,
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HIFC_SEND_CLEAR_DONE,
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HIFC_SEND_CLEAR_DONE_FAIL,
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HIFC_RCV_CLEAR_DONE_RSP,
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HIFC_SEND_VPORT_INFO_DONE,
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HIFC_SEND_VPORT_INFO_FAIL,
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HIFC_SEND_VPORT_INFO_RSP,
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HIFC_MBOX_CMD_BUTT
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};
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/* up to driver handle templete */
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struct hifc_up_2_drv_msg_handle_s {
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unsigned char cmd;
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unsigned int (*pfn_hifc_msg_up2drv_handler)(struct hifc_hba_s *v_hba,
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void *v_buf_in);
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};
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/* Mbox Common Header */
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struct hifc_mbox_header_s {
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unsigned char cmnd_type;
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unsigned char length;
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unsigned char port_id;
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unsigned char reserved;
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};
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/* open or close the sfp */
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struct hifc_inbox_port_switch_s {
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struct hifc_mbox_header_s header;
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unsigned char op_code;
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unsigned char port_type;
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unsigned short reserved;
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unsigned char host_id;
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unsigned char pf_id;
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unsigned char fcoe_mode;
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unsigned char reserved2;
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unsigned short conf_vlan;
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unsigned short reserved3;
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unsigned long long sys_port_wwn;
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unsigned long long sys_node_name;
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};
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struct hifc_outbox_port_switch_sts_s {
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struct hifc_mbox_header_s header;
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unsigned short reserved;
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unsigned char reserved2;
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unsigned char status;
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};
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/* config API */
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struct hifc_inbox_config_api_s {
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struct hifc_mbox_header_s header;
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unsigned int op_code : 8;
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unsigned int reserved1 : 24;
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unsigned char topy_mode;
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unsigned char sfp_speed;
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unsigned char max_speed;
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unsigned char hard_alpa;
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unsigned char port_name[UNF_WWN_LEN];
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unsigned int slave : 1;
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unsigned int auto_sneg : 1;
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unsigned int reserved2 : 30;
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unsigned int rx_bbcredit_32g : 16; /* 160 */
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unsigned int rx_bbcredit_16g : 16; /* 80 */
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unsigned int rx_bbcredit_842g : 16; /* 50 */
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unsigned int rdy_cnt_bf_fst_frm : 16; /* 8 */
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unsigned int esch_value_32g;
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unsigned int esch_value_16g;
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unsigned int esch_value_8g;
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unsigned int esch_value_4g;
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unsigned int esch_value_2g;
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unsigned int esch_bust_size;
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};
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struct hifc_outbox_config_api_sts_s {
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struct hifc_mbox_header_s header;
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unsigned short reserved;
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unsigned char reserved2;
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unsigned char status;
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};
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/* Get chip info */
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struct hifc_inbox_get_chip_info_s {
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struct hifc_mbox_header_s header;
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};
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struct hifc_outbox_get_chip_info_sts_s {
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struct hifc_mbox_header_s header;
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unsigned char status;
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unsigned char board_type;
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unsigned char rvsd;
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unsigned char tape_support : 1;
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unsigned char reserved : 7;
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unsigned long long wwpn;
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unsigned long long wwnn;
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unsigned long long sys_mac;
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};
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/* Get reg info */
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struct hifc_inmbox_get_reg_info_s {
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struct hifc_mbox_header_s header;
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unsigned int op_code : 1;
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unsigned int reg_len : 8;
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unsigned int rsvd : 23;
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unsigned int reg_addr;
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unsigned int reg_value_l32;
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unsigned int reg_value_h32;
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unsigned int rvsd[27];
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};
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/* Get reg info sts */
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struct hifc_outmbox_get_reg_info_sts_s {
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struct hifc_mbox_header_s header;
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unsigned short rvsd0;
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unsigned char rvsd1;
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unsigned char status;
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unsigned int reg_value_l32;
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unsigned int reg_value_h32;
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unsigned int rvsd[28];
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};
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/* Config login API */
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struct hifc_inmbox_config_login_s {
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struct hifc_mbox_header_s header;
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unsigned int op_code : 8;
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unsigned int reserved1 : 24;
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unsigned short tx_bb_credit;
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unsigned short reserved2;
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unsigned int rtov;
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unsigned int etov;
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unsigned int rt_tov_tag : 1;
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unsigned int ed_tov_tag : 1;
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unsigned int bb_credit : 6;
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unsigned int bbscn : 8;
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unsigned int lr_flag : 16;
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};
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struct hifc_outmbox_config_login_sts_s {
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struct hifc_mbox_header_s header;
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unsigned short reserved;
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unsigned char reserved2;
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unsigned char status;
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};
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/* port reset */
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#define HIFC_MBOX_SUBTYPE_LIGHT_RESET 0x0
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#define HIFC_MBOX_SUBTYPE_HEAVY_RESET 0x1
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struct hifc_inmbox_port_reset_s {
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struct hifc_mbox_header_s header;
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unsigned int op_code : 8;
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unsigned int reserved1 : 24;
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};
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struct hifc_outmbox_port_reset_sts_s {
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struct hifc_mbox_header_s header;
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unsigned short reserved;
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unsigned char reserved2;
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unsigned char status;
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};
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struct hifc_inmbox_get_sfp_info_s {
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struct hifc_mbox_header_s header;
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};
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struct hifc_outmbox_get_sfp_info_sts_s {
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struct hifc_mbox_header_s header;
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unsigned int rcvd : 8;
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unsigned int length : 16;
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unsigned int status : 8;
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};
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/* get and clear error code */
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struct hifc_inmbox_get_err_code_s {
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struct hifc_mbox_header_s header;
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};
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struct hifc_outmbox_get_err_code_sts_s {
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struct hifc_mbox_header_s header;
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unsigned short rsvd;
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unsigned char rsvd2;
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unsigned char status;
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unsigned int err_code[8];
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};
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/* uP-->Driver asyn event API */
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struct hifc_link_event_s {
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struct hifc_mbox_header_s header;
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unsigned char link_event;
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unsigned char reason;
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unsigned char speed;
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unsigned char top_type;
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unsigned char alpa_value;
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unsigned char reserved1;
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unsigned short paticpate : 1;
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unsigned short acled : 1;
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unsigned short yellow_speed_led : 1;
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unsigned short green_speed_led : 1;
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unsigned short reserved : 12;
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unsigned char loop_map_info[128];
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};
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enum hifc_up_err_type_e {
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HIFC_UP_ERR_DRV_PARA = 0,
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HIFC_UP_ERR_SFP = 1,
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HIFC_UP_ERR_32G_PUB = 2,
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HIFC_UP_ERR_32G_UA = 3,
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HIFC_UP_ERR_32G_MAC = 4,
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HIFC_UP_ERR_NON32G_DFX = 5,
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HIFC_UP_ERR_NON32G_MAC = 6,
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HIFC_UP_ERR_BUTT
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};
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enum hifc_up_err_value_e {
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/* ERR type 0 */
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HIFC_DRV_2_UP_PARA_ERR = 0,
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/* ERR type 1 */
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HIFC_SFP_SPEED_ERR,
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/* ERR type 2 */
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HIFC_32GPUB_UA_RXESCH_FIFO_OF,
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HIFC_32GPUB_UA_RXESCH_FIFO_UCERR,
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/* ERR type 3 */
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HIFC_32G_UA_UATX_LEN_ABN,
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HIFC_32G_UA_RXAFIFO_OF,
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HIFC_32G_UA_TXAFIFO_OF,
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HIFC_32G_UA_RXAFIFO_UCERR,
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HIFC_32G_UA_TXAFIFO_UCERR,
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/* ERR type 4 */
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HIFC_32G_MAC_RX_BBC_FATAL,
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HIFC_32G_MAC_TX_BBC_FATAL,
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HIFC_32G_MAC_TXFIFO_UF,
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HIFC_32G_MAC_PCS_TXFIFO_UF,
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HIFC_32G_MAC_RXBBC_CRDT_TO,
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HIFC_32G_MAC_PCS_RXAFIFO_OF,
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HIFC_32G_MAC_PCS_TXFIFO_OF,
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HIFC_32G_MAC_FC2P_RXFIFO_OF,
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HIFC_32G_MAC_FC2P_TXFIFO_OF,
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HIFC_32G_MAC_FC2P_CAFIFO_OF,
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HIFC_32G_MAC_PCS_RXRSFECM_UCEER,
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HIFC_32G_MAC_PCS_RXAFIFO_UCEER,
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HIFC_32G_MAC_PCS_TXFIFO_UCEER,
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HIFC_32G_MAC_FC2P_RXFIFO_UCEER,
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HIFC_32G_MAC_FC2P_TXFIFO_UCEER,
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/* ERR type 5 */
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HIFC_NON32G_DFX_FC1_DFX_BF_FIFO,
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HIFC_NON32G_DFX_FC1_DFX_BP_FIFO,
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HIFC_NON32G_DFX_FC1_DFX_RX_AFIFO_ERR,
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HIFC_NON32G_DFX_FC1_DFX_TX_AFIFO_ERR,
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HIFC_NON32G_DFX_FC1_DFX_DIRQ_RXBUF_FIFO1,
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HIFC_NON32G_DFX_FC1_DFX_DIRQ_RXBBC_TO,
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HIFC_NON32G_DFX_FC1_DFX_DIRQ_TXDAT_FIFO,
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HIFC_NON32G_DFX_FC1_DFX_DIRQ_TXCMD_FIFO,
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HIFC_NON32G_DFX_FC1_ERR_R_RDY,
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/* ERR type 6 */
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HIFC_NON32G_MAC_FC1_FAIRNESS_ERROR,
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HIFC_ERR_VALUE_BUTT
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};
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struct hifc_up_error_event_s {
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struct hifc_mbox_header_s header;
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unsigned char link_event;
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unsigned char error_level;
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unsigned char error_type;
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unsigned char error_value;
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};
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struct hifc_inmbx_clear_node_s {
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struct hifc_mbox_header_s header;
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};
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struct hifc_inmbox_get_clear_state_s {
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struct hifc_mbox_header_s header;
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unsigned int resvd[31];
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};
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struct hifc_outmbox_get_clear_state_sts_s {
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struct hifc_mbox_header_s header;
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unsigned short rsvd;
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unsigned char state; /* 1--clear doing. 0---clear done. */
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unsigned char status; /* 0--ok,!0---fail */
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unsigned int resvd[30];
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};
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#define HIFC_FIP_MODE_VN2VF 0
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#define HIFC_FIP_MODE_VN2VN 1
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/* get port state */
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struct hifc_inmbox_get_port_info_s {
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struct hifc_mbox_header_s header;
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};
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/* save hba info */
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struct hifc_inmbox_save_hba_info_s {
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struct hifc_mbox_header_s header;
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unsigned int hba_save_info[254];
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};
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struct hifc_outmbox_get_port_info_sts_s {
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struct hifc_mbox_header_s header;
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unsigned int status : 8;
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unsigned int fec_vis_tts_16g : 8;
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unsigned int bbscn : 8;
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unsigned int loop_credit : 8;
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unsigned int non_loop_rx_credit : 8;
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unsigned int non_loop_tx_credit : 8;
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unsigned int sfp_speed : 8;
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unsigned int present : 8;
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};
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struct hifc_outmbox_save_hba_info_sts_s {
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struct hifc_mbox_header_s header;
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unsigned short rsvd1;
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unsigned char rsvd2;
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unsigned char status;
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unsigned int rsvd3;
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unsigned int save_hba_info[252];
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};
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|
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#define HIFC_VER_ADDR_OFFSET (8)
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struct hifc_inmbox_get_fw_version_s {
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struct hifc_mbox_header_s header;
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};
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|
|
|
struct hifc_outmbox_get_fw_version_sts_s {
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|
struct hifc_mbox_header_s header;
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|
|
|
unsigned char status;
|
|
unsigned char rsv[3];
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|
|
|
unsigned char ucode_ver[HIFC_VER_LEN];
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|
unsigned char ucode_compile_time[HIFC_COMPILE_TIME_LEN];
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|
|
|
unsigned char up_ver[HIFC_VER_LEN];
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|
unsigned char up_compile_time[HIFC_COMPILE_TIME_LEN];
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|
|
|
unsigned char boot_ver[HIFC_VER_LEN];
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|
unsigned char boot_compile_time[HIFC_COMPILE_TIME_LEN];
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|
};
|
|
|
|
/* Set Fec Enable */
|
|
struct hifc_inmbox_config_fec_s {
|
|
struct hifc_mbox_header_s header;
|
|
|
|
unsigned char fec_op_code;
|
|
unsigned char rsv0;
|
|
unsigned short rsv1;
|
|
};
|
|
|
|
struct hifc_outmbox_config_fec_sts_s {
|
|
struct hifc_mbox_header_s header;
|
|
|
|
unsigned short usrsv0;
|
|
unsigned char ucrsv1;
|
|
unsigned char status;
|
|
};
|
|
|
|
struct hifc_inmbox_config_timer_s {
|
|
struct hifc_mbox_header_s header;
|
|
|
|
unsigned short op_code;
|
|
unsigned short fun_id;
|
|
unsigned int user_data;
|
|
};
|
|
|
|
struct hifc_outmbox_config_timer_sts_s {
|
|
struct hifc_mbox_header_s header;
|
|
|
|
unsigned char status;
|
|
unsigned char rsv[3];
|
|
};
|
|
|
|
union hifc_outmbox_generic_u {
|
|
struct {
|
|
struct hifc_mbox_header_s header;
|
|
unsigned int rsvd[(HIFC_MBOX_SIZE - HIFC_MBOX_HEADER_SIZE) /
|
|
sizeof(unsigned int)];
|
|
} generic;
|
|
|
|
struct hifc_outbox_port_switch_sts_s port_switch_sts;
|
|
struct hifc_outbox_config_api_sts_s config_api_sts;
|
|
struct hifc_outbox_get_chip_info_sts_s get_chip_info_sts;
|
|
struct hifc_outmbox_get_reg_info_sts_s get_reg_info_sts;
|
|
struct hifc_outmbox_config_login_sts_s config_login_sts;
|
|
struct hifc_outmbox_port_reset_sts_s port_reset_sts;
|
|
struct hifc_outmbox_get_sfp_info_sts_s get_sfp_info_sts;
|
|
struct hifc_outmbox_get_err_code_sts_s get_err_code_sts;
|
|
struct hifc_outmbox_get_clear_state_sts_s get_clr_state_sts;
|
|
struct hifc_outmbox_get_fw_version_sts_s get_fw_ver_sts;
|
|
struct hifc_outmbox_config_fec_sts_s config_fec_sts;
|
|
struct hifc_outmbox_config_timer_sts_s timer_config_sts;
|
|
struct hifc_outmbox_get_port_info_sts_s get_port_info_sts;
|
|
struct unf_flash_data_mgmt_sts_s flash_data_sts;
|
|
};
|
|
|
|
unsigned int hifc_get_chip_msg(void *v_hba, void *v_mac);
|
|
unsigned int hifc_config_port_table(struct hifc_hba_s *v_hba);
|
|
unsigned int hifc_port_switch(struct hifc_hba_s *v_hba, int turn_on);
|
|
unsigned int hifc_get_speed_act(void *v_hba, void *v_speed_act);
|
|
unsigned int hifc_get_speed_cfg(void *v_hba, void *v_speed_cfg);
|
|
unsigned int hifc_get_loop_map(void *v_hba, void *v_buf);
|
|
unsigned int hifc_get_firmware_version(void *v_fc_port, void *v_ver);
|
|
unsigned int hifc_get_work_bale_bbcredit(void *v_hba, void *v_bb_credit);
|
|
unsigned int hifc_get_work_bale_bbscn(void *v_hba, void *v_bbscn);
|
|
unsigned int hifc_get_and_clear_port_error_code(void *v_hba, void *v_err_code);
|
|
unsigned int hifc_get_port_current_info(void *v_hba, void *v_port_info);
|
|
unsigned int hifc_get_port_fec(void *v_hba, void *v_para_out);
|
|
unsigned int hifc_get_software_version(void *v_fc_port, void *v_ver);
|
|
unsigned int hifc_get_port_info(void *v_hba);
|
|
unsigned int hifc_rw_reg(void *v_hba, void *v_params);
|
|
unsigned int hifc_clear_port_error_code(void *v_hba, void *v_err_code);
|
|
unsigned int hifc_get_sfp_info(void *v_fc_port, void *v_sfp_info);
|
|
unsigned int hifc_get_hardware_version(void *v_fc_port, void *v_ver);
|
|
unsigned int hifc_get_lport_led(void *v_hba, void *v_led_state);
|
|
unsigned int hifc_get_loop_alpa(void *v_hba, void *v_alpa);
|
|
unsigned int hifc_get_topo_act(void *v_hba, void *v_topo_act);
|
|
unsigned int hifc_get_topo_cfg(void *v_hba, void *v_topo_cfg);
|
|
unsigned int hifc_config_login_api(
|
|
struct hifc_hba_s *v_hba,
|
|
struct unf_port_login_parms_s *v_login_parms);
|
|
unsigned int hifc_mb_send_and_wait_mbox(struct hifc_hba_s *v_hba,
|
|
const void *v_in_mbox,
|
|
unsigned short in_size,
|
|
union hifc_outmbox_generic_u
|
|
*v_out_mbox);
|
|
void hifc_up_msg_2_driver_proc(void *v_hwdev_handle,
|
|
void *v_pri_handle,
|
|
unsigned char v_cmd,
|
|
void *v_buf_in,
|
|
unsigned short v_in_size,
|
|
void *v_buf_out,
|
|
unsigned short *v_out_size);
|
|
|
|
unsigned int hifc_mbox_reset_chip(struct hifc_hba_s *v_hba,
|
|
unsigned char v_sub_type);
|
|
unsigned int hifc_clear_sq_wqe_done(struct hifc_hba_s *v_hba);
|
|
unsigned int hifc_update_fabric_param(void *v_hba, void *v_para_in);
|
|
unsigned int hifc_update_port_param(void *v_hba, void *v_para_in);
|
|
unsigned int hifc_mbx_get_fw_clear_stat(struct hifc_hba_s *v_hba,
|
|
unsigned int *v_clear_state);
|
|
unsigned short hifc_get_global_base_qpn(void *v_handle);
|
|
unsigned int hifc_mbx_set_fec(struct hifc_hba_s *v_hba,
|
|
unsigned int v_fec_opcode);
|
|
unsigned int hifc_notify_up_config_timer(struct hifc_hba_s *v_hba,
|
|
int v_opcode,
|
|
unsigned int v_user_data);
|
|
unsigned int hifc_save_hba_info(void *v_hba, void *v_para_in);
|
|
unsigned int hifc_get_chip_capability(void *hw_dev_handle,
|
|
struct hifc_chip_info_s *v_chip_info);
|
|
unsigned int hifc_get_flash_data(void *v_hba, void *v_flash_data);
|
|
unsigned int hifc_set_flash_data(void *v_hba, void *v_flash_data);
|
|
|
|
#endif
|