172 lines
3.2 KiB
C
172 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Huawei Hifc PCI Express Linux driver
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* Copyright(c) 2017 Huawei Technologies Co., Ltd
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*
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*/
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#ifndef __CFG_MGT_H__
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#define __CFG_MGT_H__
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enum {
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CFG_FREE = 0,
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CFG_BUSY = 1
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};
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/* FC */
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#define FC_PCTX_SZ 256
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#define FC_CCTX_SZ 256
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#define FC_SQE_SZ 128
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#define FC_SCQC_SZ 64
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#define FC_SCQE_SZ 64
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#define FC_SRQC_SZ 64
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#define FC_SRQE_SZ 32
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/* device capability */
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struct service_cap {
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/* Host global resources */
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u16 host_total_function;
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u8 host_oq_id_mask_val;
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/* DO NOT get interrupt_type from firmware */
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enum intr_type interrupt_type;
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u8 intr_chip_en;
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u8 port_id; /* PF/VF's physical port */
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u8 force_up;
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u8 timer_en; /* 0:disable, 1:enable */
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u16 max_sqs;
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u16 max_rqs;
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/* For test */
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bool test_xid_alloc_mode;
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bool test_gpa_check_enable;
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u32 max_connect_num; /* PF/VF maximum connection number(1M) */
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/* The maximum connections which can be stick to cache memory, max 1K */
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u16 max_stick2cache_num;
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struct nic_service_cap nic_cap; /* NIC capability */
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struct fc_service_cap fc_cap; /* FC capability */
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};
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struct hifc_sync_time_info {
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u8 status;
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u8 version;
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u8 rsvd0[6];
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u64 mstime;
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};
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struct cfg_eq {
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enum hifc_service_type type;
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int eqn;
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int free; /* 1 - alocated, 0- freed */
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};
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struct cfg_eq_info {
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struct cfg_eq *eq;
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u8 num_ceq;
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u8 num_ceq_remain;
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/* mutex used for allocate EQs */
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struct mutex eq_mutex;
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};
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struct irq_alloc_info_st {
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enum hifc_service_type type;
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int free; /* 1 - alocated, 0- freed */
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struct irq_info info;
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};
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struct cfg_irq_info {
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struct irq_alloc_info_st *alloc_info;
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u16 num_total;
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u16 num_irq_remain;
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u16 num_irq_hw; /* device max irq number */
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/* mutex used for allocate EQs */
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struct mutex irq_mutex;
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};
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#define VECTOR_THRESHOLD 2
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struct cfg_mgmt_info {
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struct hifc_hwdev *hwdev;
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struct service_cap svc_cap;
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struct cfg_eq_info eq_info; /* EQ */
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struct cfg_irq_info irq_param_info; /* IRQ */
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u32 func_seq_num; /* temporary */
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};
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enum cfg_sub_cmd {
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/* PPF(PF) <-> FW */
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HIFC_CFG_NIC_CAP = 0,
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CFG_FW_VERSION,
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CFG_UCODE_VERSION,
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HIFC_CFG_FUNC_CAP,
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HIFC_CFG_MBOX_CAP = 6,
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};
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struct hifc_dev_cap {
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u8 status;
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u8 version;
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u8 rsvd0[6];
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/* Public resource */
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u8 sf_svc_attr;
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u8 host_id;
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u8 sf_en_pf;
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u8 sf_en_vf;
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u8 ep_id;
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u8 intr_type;
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u8 max_cos_id;
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u8 er_id;
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u8 port_id;
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u8 max_vf;
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u16 svc_cap_en;
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u16 host_total_func;
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u8 host_oq_id_mask_val;
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u8 max_vf_cos_id;
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u32 max_conn_num;
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u16 max_stick2cache_num;
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u16 max_bfilter_start_addr;
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u16 bfilter_len;
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u16 hash_bucket_num;
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u8 cfg_file_ver;
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u8 net_port_mode;
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u8 valid_cos_bitmap; /* every bit indicate cos is valid */
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u8 force_up;
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u32 pf_num;
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u32 pf_id_start;
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u32 vf_num;
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u32 vf_id_start;
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/* shared resource */
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u32 host_pctx_num;
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u8 host_sf_en;
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u8 rsvd2[3];
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u32 host_ccxt_num;
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u32 host_scq_num;
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u32 host_srq_num;
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u32 host_mpt_num;
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/* l2nic */
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u16 nic_max_sq;
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u16 nic_max_rq;
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u32 rsvd[46];
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/* FC */
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u32 fc_max_pctx;
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u32 fc_max_scq;
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u32 fc_max_srq;
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u32 fc_max_cctx;
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u32 fc_cctx_id_start;
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u8 fc_vp_id_start;
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u8 fc_vp_id_end;
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u16 func_id;
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};
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#endif
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