229 lines
8.4 KiB
C
229 lines
8.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_ARM64_MPAM_RESOURCE_H
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#define _ASM_ARM64_MPAM_RESOURCE_H
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#include <linux/bitops.h>
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#define MPAMF_IDR 0x0000
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#define MPAMF_SIDR 0x0008
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#define MPAMF_MSMON_IDR 0x0080
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#define MPAMF_IMPL_IDR 0x0028
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#define MPAMF_CPOR_IDR 0x0030
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#define MPAMF_CCAP_IDR 0x0038
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#define MPAMF_MBW_IDR 0x0040
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#define MPAMF_PRI_IDR 0x0048
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#define MPAMF_CSUMON_IDR 0x0088
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#define MPAMF_MBWUMON_IDR 0x0090
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#define MPAMF_PARTID_NRW_IDR 0x0050
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#define MPAMF_IIDR 0x0018
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#define MPAMF_AIDR 0x0020
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#define MPAMCFG_PART_SEL 0x0100
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#define MPAMCFG_CPBM 0x1000
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#define MPAMCFG_CMAX 0x0108
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#define MPAMCFG_MBW_MIN 0x0200
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#define MPAMCFG_MBW_MAX 0x0208
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#define MPAMCFG_MBW_WINWD 0x0220
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#define MPAMCFG_MBW_PBM 0x2000
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#define MPAMCFG_PRI 0x0400
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#define MPAMCFG_MBW_PROP 0x0500
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#define MPAMCFG_INTPARTID 0x0600
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#define MSMON_CFG_MON_SEL 0x0800
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#define MSMON_CFG_CSU_FLT 0x0810
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#define MSMON_CFG_CSU_CTL 0x0818
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#define MSMON_CFG_MBWU_FLT 0x0820
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#define MSMON_CFG_MBWU_CTL 0x0828
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#define MSMON_CSU 0x0840
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#define MSMON_CSU_CAPTURE 0x0848
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#define MSMON_MBWU 0x0860
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#define MSMON_MBWU_CAPTURE 0x0868
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#define MSMON_CAPT_EVNT 0x0808
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#define MPAMF_ESR 0x00F8
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#define MPAMF_ECR 0x00F0
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#define HAS_CCAP_PART BIT(24)
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#define HAS_CPOR_PART BIT(25)
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#define HAS_MBW_PART BIT(26)
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#define HAS_PRI_PART BIT(27)
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#define HAS_IMPL_IDR BIT(29)
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#define HAS_MSMON BIT(30)
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#define HAS_PARTID_NRW BIT(31)
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/* MPAMF_IDR */
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#define MPAMF_IDR_PMG_MAX_MASK ((BIT(8) - 1) << 16)
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#define MPAMF_IDR_PMG_MAX_SHIFT 16
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#define MPAMF_IDR_PARTID_MAX_MASK (BIT(16) - 1)
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#define MPAMF_IDR_PMG_MAX_GET(v) ((v & MPAMF_IDR_PMG_MAX_MASK) >> 16)
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#define MPAMF_IDR_PARTID_MAX_GET(v) (v & MPAMF_IDR_PARTID_MAX_MASK)
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#define MPAMF_IDR_HAS_CCAP_PART(v) ((v) & HAS_CCAP_PART)
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#define MPAMF_IDR_HAS_CPOR_PART(v) ((v) & HAS_CPOR_PART)
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#define MPAMF_IDR_HAS_MBW_PART(v) ((v) & HAS_MBW_PART)
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#define MPAMF_IDR_HAS_MSMON(v) ((v) & HAS_MSMON)
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#define MPAMF_IDR_PARTID_MASK GENMASK(15, 0)
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#define MPAMF_IDR_PMG_MASK GENMASK(23, 16)
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#define MPAMF_IDR_PMG_SHIFT 16
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#define MPAMF_IDR_HAS_PARTID_NRW(v) ((v) & HAS_PARTID_NRW)
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#define NUM_MON_MASK (BIT(16) - 1)
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#define MPAMF_IDR_NUM_MON(v) ((v) & NUM_MON_MASK)
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#define CPBM_WD_MASK 0xFFFF
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#define CPBM_MASK 0x7FFF
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#define MBW_MAX_HARDLIM BIT(31)
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#define MBW_PROP_HARDLIM BIT(31)
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#define MBW_MAX_MASK GENMASK(15, 0)
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#define MBW_MAX_BWA_FRACT(w) GENMASK(w - 1, 0)
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#define MBW_MAX_SET(v, w) (v << (16 - w))
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/* MPAMCFG_MBW_PROP */
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#define MBW_PROP_SET_HDL(r) (r | MBW_PROP_HARDLIM)
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/* MPAMCFG_MBW_MAX */
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#define MBW_MAX_SET_HDL(r) (r | MBW_MAX_HARDLIM)
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#define MBW_MAX_GET_HDL(r) ((r & MBW_MAX_HARDLIM) >> 31)
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#define MBW_MAX_GET(v, w) (((v) & MBW_MAX_MASK) >> (16 - w))
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#define MSMON_MATCH_PMG BIT(17)
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#define MSMON_MATCH_PARTID BIT(16)
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#define MSMON_CFG_CTL_EN BIT(31)
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#define MSMON_CFG_FLT_SET(r, p) ((r) << 16|(p))
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#define MBWU_SUBTYPE_DEFAULT (3 << 20)
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#define MSMON_CFG_MBWU_CTL_SET(m) (BIT(31)|MBWU_SUBTYPE_DEFAULT|(m))
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#define MSMON_CFG_CSU_CTL_SET(m) (BIT(31)|(m))
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#define MSMON_CFG_CSU_TYPE 0x43
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#define MSMON_CFG_MBWU_TYPE 0x42
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/*
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* Set MPAMCFG_INTPARTID internal bit
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*/
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#define MPAMCFG_INTPARTID_INTERNAL BIT(16)
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#define INTPARTID_INTPARTID_MASK (BIT(15) - 1)
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#define MPAMCFG_INTPARTID_INTPARTID_GET(r) (r & INTPARTID_INTPARTID_MASK)
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/*
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* Set MPAMCFG_PART_SEL internal bit
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*/
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#define MPAMCFG_PART_SEL_INTERNAL BIT(16)
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/* MPAMF_ESR - MPAM Error Status Register */
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#define MPAMF_ESR_PARTID_OR_MON GENMASK(15, 0)
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#define MPAMF_ESR_PMG GENMASK(23, 16)
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#define MPAMF_ESR_ERRCODE GENMASK(27, 24)
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#define MPAMF_ESR_ERRCODE_SHIFT 24
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#define MPAMF_ESR_OVRWR BIT(31)
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#define MPAMF_ESR_ERRCODE_MASK ((BIT(4) - 1) << 24)
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/* MPAMF_ECR - MPAM Error Control Register */
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#define MPAMF_ECR_INTEN BIT(0)
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/*
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* Size of the memory mapped registers: 4K of feature page then 2 x 4K
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* bitmap registers
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*/
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#define SZ_MPAM_DEVICE (3 * SZ_4K)
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/*
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* MSMON_CSU - Memory system performance monitor cache storage usage monitor
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* register
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* MSMON_CSU_CAPTURE - Memory system performance monitor cache storage usage
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* capture register
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* MSMON_MBWU - Memory system performance monitor memory bandwidth usage
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* monitor register
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* MSMON_MBWU_CAPTURE - Memory system performance monitor memory bandwidth usage
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* capture register
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*/
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#define MSMON___VALUE GENMASK(30, 0)
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#define MSMON___NRDY BIT(31)
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/*
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* MSMON_CAPT_EVNT - Memory system performance monitoring capture event
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* generation register
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*/
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#define MSMON_CAPT_EVNT_NOW BIT(0)
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/*
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* MPAMCFG_MBW_MAX SET - temp Hard code
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*/
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#define MPAMCFG_PRI_DSPRI_SHIFT 16
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#define MPAMCFG_INTPRI_GET(r) (r & GENMASK(15, 0))
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#define MPAMCFG_DSPRI_GET(r) ((r & GENMASK(31, 16)) >> 16)
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/* Always same if both supported */
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#define MPAMCFG_PRI_GET(r) (MPAMCFG_DSPRI_GET(r) | MPAMCFG_INTPRI_GET(r))
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/* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */
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#define MPAMF_PRI_IDR_HAS_INTPRI BIT(0)
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#define MPAMF_PRI_IDR_INTPRI_0_IS_LOW BIT(1)
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#define MPAMF_PRI_IDR_INTPRI_WD_SHIFT 4
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#define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4)
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#define MPAMF_PRI_IDR_HAS_DSPRI BIT(16)
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#define MPAMF_PRI_IDR_DSPRI_0_IS_LOW BIT(17)
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#define MPAMF_PRI_IDR_DSPRI_WD_SHIFT 20
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#define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20)
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/* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */
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#define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0)
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#define MPAMF_CSUMON_IDR_HAS_CAPTURE BIT(31)
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/* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */
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#define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0)
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#define MPAMF_MBWUMON_IDR_HAS_CAPTURE BIT(31)
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/* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */
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#define MPAMF_CPOR_IDR_CPBM_WD GENMASK(15, 0)
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/* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register */
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#define MPAMF_CCAP_IDR_CMAX_WD GENMASK(5, 0)
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/* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */
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#define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0)
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#define MPAMF_MBW_IDR_HAS_MIN BIT(10)
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#define MPAMF_MBW_IDR_HAS_MAX BIT(11)
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#define MPAMF_MBW_IDR_HAS_PBM BIT(12)
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#define MPAMF_MBW_IDR_HAS_PROP BIT(13)
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#define MPAMF_MBW_IDR_WINDWR BIT(14)
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#define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16)
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#define MPAMF_MBW_IDR_BWPBM_WD_SHIFT 16
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/* MPAMF_PARTID_NRW_IDR - MPAM features partid narrow ID register */
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#define MPAMF_PARTID_NRW_IDR_MASK (BIT(16) - 1)
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#define MSMON_CFG_CTL_TYPE GENMASK(7, 0)
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#define MSMON_CFG_CTL_MATCH_PARTID BIT(16)
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#define MSMON_CFG_CTL_MATCH_PMG BIT(17)
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#define MSMON_CFG_CTL_SUBTYPE GENMASK(23, 20)
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#define MSMON_CFG_CTL_SUBTYPE_SHIFT 20
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#define MSMON_CFG_CTL_OFLOW_FRZ BIT(24)
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#define MSMON_CFG_CTL_OFLOW_INTR BIT(25)
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#define MSMON_CFG_CTL_OFLOW_STATUS BIT(26)
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#define MSMON_CFG_CTL_CAPT_RESET BIT(27)
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#define MSMON_CFG_CTL_CAPT_EVNT GENMASK(30, 28)
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#define MSMON_CFG_CTL_CAPT_EVNT_SHIFT 28
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#define MSMON_CFG_CTL_EN BIT(31)
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#define MPAMF_IDR_HAS_PRI_PART(v) (v & BIT(27))
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/* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */
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#define MPAMF_MSMON_IDR_MSMON_CSU BIT(16)
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#define MPAMF_MSMON_IDR_MSMON_MBWU BIT(17)
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#define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT BIT(31)
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/*
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* MSMON_CFG_MBWU_FLT - Memory system performance monitor configure memory
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* bandwidth usage monitor filter register
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*/
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#define MSMON_CFG_MBWU_FLT_PARTID GENMASK(15, 0)
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#define MSMON_CFG_MBWU_FLT_PMG_SHIFT 16
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#define MSMON_CFG_MBWU_FLT_PMG GENMASK(23, 16)
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#define MSMON_CFG_MBWU_TYPE 0x42
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/*
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* MSMON_CFG_CSU_FLT - Memory system performance monitor configure cache storage
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* usage monitor filter register
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*/
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#define MSMON_CFG_CSU_FLT_PARTID GENMASK(15, 0)
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#define MSMON_CFG_CSU_FLT_PMG GENMASK(23, 16)
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#define MSMON_CFG_CSU_FLT_PMG_SHIFT 16
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#define MSMON_CFG_CSU_TYPE 0x43
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/* hard code for mbw_max max-percentage's cresponding masks */
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#define MBA_MAX_WD 63u
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#endif /* _ASM_ARM64_MPAM_RESOURCE_H */
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