577 lines
18 KiB
C
577 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2021 Arm Ltd.
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#ifndef MPAM_INTERNAL_H
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#define MPAM_INTERNAL_H
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#include <linux/arm_mpam.h>
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#include <linux/atomic.h>
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#include <linux/cpumask.h>
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#include <linux/io.h>
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#include <linux/jump_label.h>
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#include <linux/mailbox_client.h>
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#include <linux/mutex.h>
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#include <linux/resctrl.h>
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#include <linux/sizes.h>
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#include <linux/srcu.h>
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DECLARE_STATIC_KEY_FALSE(mpam_enabled);
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/* Value to indicate the allocated monitor is derived from the RMID index. */
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#define USE_RMID_IDX (U16_MAX + 1)
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/*
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* Only these event configuration bits are supported. MPAM can't know if
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* data is being written back, these will show up as a write.
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*/
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#define MPAM_RESTRL_EVT_CONFIG_VALID (READS_TO_LOCAL_MEM | NON_TEMP_WRITE_TO_LOCAL_MEM)
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static inline bool mpam_is_enabled(void)
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{
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return static_branch_likely(&mpam_enabled);
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}
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struct mpam_msc
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{
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/* member of mpam_all_msc */
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struct list_head glbl_list;
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int id;
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struct platform_device *pdev;
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/* Not modified after mpam_is_enabled() becomes true */
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enum mpam_msc_iface iface;
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u32 pcc_subspace_id;
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struct mbox_client pcc_cl;
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struct pcc_mbox_chan *pcc_chan;
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u32 nrdy_usec;
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cpumask_t accessibility;
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bool has_extd_esr;
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int reenable_error_ppi;
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struct mpam_msc * __percpu *error_dev_id;
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atomic_t online_refs;
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struct mutex lock;
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bool probed;
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bool error_irq_requested;
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bool error_irq_hw_enabled;
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u16 partid_max;
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u8 pmg_max;
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unsigned long ris_idxs[128 / BITS_PER_LONG];
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u32 ris_max;
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/* mpam_msc_ris of this component */
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struct list_head ris;
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/*
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* part_sel_lock protects access to the MSC hardware registers that are
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* affected by MPAMCFG_PART_SEL. (including the ID registers)
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* If needed, take msc->lock first.
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*/
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spinlock_t part_sel_lock;
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spinlock_t mon_sel_lock;
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void __iomem * mapped_hwpage;
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size_t mapped_hwpage_sz;
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};
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/*
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* When we compact the supported features, we don't care what they are.
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* Storing them as a bitmap makes life easy.
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*/
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typedef u32 mpam_features_t;
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/* Bits for mpam_features_t */
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enum mpam_device_features {
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mpam_feat_ccap_part = 0,
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mpam_feat_cpor_part,
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mpam_feat_mbw_part,
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mpam_feat_mbw_min,
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mpam_feat_mbw_max,
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mpam_feat_mbw_prop,
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mpam_feat_intpri_part,
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mpam_feat_intpri_part_0_low,
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mpam_feat_dspri_part,
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mpam_feat_dspri_part_0_low,
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mpam_feat_msmon,
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mpam_feat_msmon_csu,
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mpam_feat_msmon_csu_capture,
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/*
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* Having mpam_feat_msmon_mbwu set doesn't mean the regular 31 bit MBWU
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* counter would be used. The exact counter used is decided based on the
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* status of mpam_feat_msmon_mbwu_l/mpam_feat_msmon_mbwu_lwd as well.
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*/
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mpam_feat_msmon_mbwu,
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mpam_feat_msmon_mbwu_44counter,
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mpam_feat_msmon_mbwu_63counter,
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mpam_feat_msmon_mbwu_capture,
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mpam_feat_msmon_mbwu_rwbw,
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mpam_feat_msmon_capt,
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mpam_feat_partid_nrw,
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MPAM_FEATURE_LAST,
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};
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#define MPAM_ALL_FEATURES ((1<<MPAM_FEATURE_LAST) - 1)
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struct mpam_props
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{
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mpam_features_t features;
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u16 cpbm_wd;
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u16 mbw_pbm_bits;
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u8 bwa_wd;
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u16 cmax_wd;
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u16 intpri_wd;
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u16 dspri_wd;
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u16 num_csu_mon;
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u16 num_mbwu_mon;
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};
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#define mpam_has_feature(_feat, x) ((1<<_feat) & (x)->features)
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#define mpam_set_feature(_feat, x) ((x)->features |= (1<<_feat))
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static inline void mpam_clear_feature(enum mpam_device_features feat,
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mpam_features_t *supported)
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{
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*supported &= ~(1<<feat);
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}
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struct mpam_class
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{
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/* mpam_components in this class */
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struct list_head components;
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cpumask_t affinity;
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struct mpam_props props;
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u32 nrdy_usec;
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u8 level;
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enum mpam_class_types type;
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/* member of mpam_classes */
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struct list_head classes_list;
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struct ida ida_csu_mon;
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struct ida ida_mbwu_mon;
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};
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struct mpam_config {
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/* Which configuration values are valid. 0 is used for reset */
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mpam_features_t features;
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u32 cpbm;
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u32 mbw_pbm;
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u16 mbw_max;
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};
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struct mpam_component
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{
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u32 comp_id;
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/* mpam_msc_ris in this component */
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struct list_head ris;
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cpumask_t affinity;
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/*
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* Array of configuration values, indexed by partid.
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* Read from cpuhp callbacks, hold the cpuhp lock when writing.
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*/
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struct mpam_config *cfg;
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/* member of mpam_class:components */
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struct list_head class_list;
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/* parent: */
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struct mpam_class *class;
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};
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/* The values for MSMON_CFG_MBWU_FLT.RWBW */
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enum mon_filter_options {
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COUNT_BOTH = 0,
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COUNT_WRITE = 1,
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COUNT_READ = 2,
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};
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struct mon_cfg {
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u16 mon;
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u8 pmg;
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bool match_pmg;
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u32 partid;
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enum mon_filter_options opts;
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};
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/*
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* Changes to enabled and cfg are protected by the msc->lock.
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* Changes to reset_on_next_read, prev_val and correction are protected by the
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* msc's mon_sel_lock.
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*/
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struct msmon_mbwu_state {
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bool enabled;
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bool reset_on_next_read;
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struct mon_cfg cfg;
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/* The value last read from the hardware. Used to detect overflow. */
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u64 prev_val;
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/*
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* The value to add to the new reading to account for power management,
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* and shifts to trigger the overflow interrupt.
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*/
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u64 correction;
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};
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struct mpam_msc_ris {
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u8 ris_idx;
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u64 idr;
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struct mpam_props props;
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bool in_reset_state;
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cpumask_t affinity;
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/* member of mpam_component:ris */
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struct list_head comp_list;
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/* member of mpam_msc:ris */
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struct list_head msc_list;
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/* parents: */
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struct mpam_msc *msc;
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struct mpam_component *comp;
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/* msmon mbwu configuration is preserved over reset */
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struct msmon_mbwu_state *mbwu_state;
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};
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struct mpam_resctrl_dom {
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struct mpam_component *comp;
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struct rdt_domain resctrl_dom;
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u32 mbm_local_evt_cfg;
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};
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struct mpam_resctrl_res {
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struct mpam_class *class;
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struct rdt_resource resctrl_res;
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};
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static inline int mpam_alloc_csu_mon(struct mpam_class *class)
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{
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struct mpam_props *cprops = &class->props;
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if (!mpam_has_feature(mpam_feat_msmon_csu, cprops))
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return -EOPNOTSUPP;
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return ida_alloc_range(&class->ida_csu_mon, 0, cprops->num_csu_mon - 1,
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GFP_KERNEL);
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}
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static inline void mpam_free_csu_mon(struct mpam_class *class, int csu_mon)
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{
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ida_free(&class->ida_csu_mon, csu_mon);
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}
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static inline int mpam_alloc_mbwu_mon(struct mpam_class *class)
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{
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struct mpam_props *cprops = &class->props;
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if (!mpam_has_feature(mpam_feat_msmon_mbwu, cprops))
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return -EOPNOTSUPP;
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return ida_alloc_range(&class->ida_mbwu_mon, 0,
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cprops->num_mbwu_mon - 1, GFP_KERNEL);
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}
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static inline void mpam_free_mbwu_mon(struct mpam_class *class, int mbwu_mon)
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{
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ida_free(&class->ida_mbwu_mon, mbwu_mon);
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}
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/* List of all classes */
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extern struct list_head mpam_classes;
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extern struct srcu_struct mpam_srcu;
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/* System wide partid/pmg values */
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extern u16 mpam_partid_max;
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extern u8 mpam_pmg_max;
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/* Scheduled work callback to enable mpam once all MSC have been probed */
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void mpam_enable(struct work_struct *work);
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void mpam_disable(struct work_struct *work);
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void mpam_reset_class(struct mpam_class *class);
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int mpam_apply_config(struct mpam_component *comp, u16 partid,
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struct mpam_config *cfg);
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int mpam_msmon_read(struct mpam_component *comp, struct mon_cfg *ctx,
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enum mpam_device_features, u64 *val);
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void mpam_msmon_reset_mbwu(struct mpam_component *comp, struct mon_cfg *ctx);
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void mpam_msmon_reset_all_mbwu(struct mpam_component *comp);
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int mpam_resctrl_online_cpu(unsigned int cpu);
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int mpam_resctrl_offline_cpu(unsigned int cpu);
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int mpam_resctrl_setup(void);
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void mpam_resctrl_exit(void);
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/*
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* MPAM MSCs have the following register layout. See:
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* Arm Architecture Reference Manual Supplement - Memory System Resource
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* Partitioning and Monitoring (MPAM), for Armv8-A. DDI 0598A.a
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*/
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#define MPAM_ARCHITECTURE_V1 0x10
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/* Memory mapped control pages: */
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/* ID Register offsets in the memory mapped page */
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#define MPAMF_IDR 0x0000 /* features id register */
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#define MPAMF_MSMON_IDR 0x0080 /* performance monitoring features */
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#define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */
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#define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */
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#define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */
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#define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */
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#define MPAMF_PRI_IDR 0x0048 /* priority partitioning */
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#define MPAMF_CSUMON_IDR 0x0088 /* cache-usage monitor */
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#define MPAMF_MBWUMON_IDR 0x0090 /* mem-bw usage monitor */
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#define MPAMF_PARTID_NRW_IDR 0x0050 /* partid-narrowing */
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#define MPAMF_IIDR 0x0018 /* implementer id register */
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#define MPAMF_AIDR 0x0020 /* architectural id register */
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/* Configuration and Status Register offsets in the memory mapped page */
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#define MPAMCFG_PART_SEL 0x0100 /* partid to configure: */
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#define MPAMCFG_CPBM 0x1000 /* cache-portion config */
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#define MPAMCFG_CMAX 0x0108 /* cache-capacity config */
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#define MPAMCFG_MBW_MIN 0x0200 /* min mem-bw config */
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#define MPAMCFG_MBW_MAX 0x0208 /* max mem-bw config */
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#define MPAMCFG_MBW_WINWD 0x0220 /* mem-bw accounting window config */
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#define MPAMCFG_MBW_PBM 0x2000 /* mem-bw portion bitmap config */
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#define MPAMCFG_PRI 0x0400 /* priority partitioning config */
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#define MPAMCFG_MBW_PROP 0x0500 /* mem-bw stride config */
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#define MPAMCFG_INTPARTID 0x0600 /* partid-narrowing config */
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#define MSMON_CFG_MON_SEL 0x0800 /* monitor selector */
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#define MSMON_CFG_CSU_FLT 0x0810 /* cache-usage monitor filter */
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#define MSMON_CFG_CSU_CTL 0x0818 /* cache-usage monitor config */
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#define MSMON_CFG_MBWU_FLT 0x0820 /* mem-bw monitor filter */
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#define MSMON_CFG_MBWU_CTL 0x0828 /* mem-bw monitor config */
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#define MSMON_CSU 0x0840 /* current cache-usage */
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#define MSMON_CSU_CAPTURE 0x0848 /* last cache-usage value captured */
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#define MSMON_MBWU 0x0860 /* current mem-bw usage value */
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#define MSMON_MBWU_CAPTURE 0x0868 /* last mem-bw value captured */
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#define MSMON_MBWU_L 0x0880 /* current long mem-bw usage value */
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#define MSMON_MBWU_CAPTURE_L 0x0890 /* last long mem-bw value captured */
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#define MSMON_CAPT_EVNT 0x0808 /* signal a capture event */
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#define MPAMF_ESR 0x00F8 /* error status register */
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#define MPAMF_ECR 0x00F0 /* error control register */
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/* MPAMF_IDR - MPAM features ID register */
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#define MPAMF_IDR_PARTID_MAX GENMASK(15, 0)
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#define MPAMF_IDR_PMG_MAX GENMASK(23, 16)
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#define MPAMF_IDR_HAS_CCAP_PART BIT(24)
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#define MPAMF_IDR_HAS_CPOR_PART BIT(25)
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#define MPAMF_IDR_HAS_MBW_PART BIT(26)
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#define MPAMF_IDR_HAS_PRI_PART BIT(27)
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#define MPAMF_IDR_HAS_EXT BIT(28)
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#define MPAMF_IDR_HAS_IMPL_IDR BIT(29)
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#define MPAMF_IDR_HAS_MSMON BIT(30)
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#define MPAMF_IDR_HAS_PARTID_NRW BIT(31)
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#define MPAMF_IDR_HAS_RIS BIT(32)
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#define MPAMF_IDR_HAS_EXT_ESR BIT(38)
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#define MPAMF_IDR_HAS_ESR BIT(39)
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#define MPAMF_IDR_RIS_MAX GENMASK(59, 56)
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/* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */
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#define MPAMF_MSMON_IDR_MSMON_CSU BIT(16)
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#define MPAMF_MSMON_IDR_MSMON_MBWU BIT(17)
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#define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT BIT(31)
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/* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */
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#define MPAMF_CPOR_IDR_CPBM_WD GENMASK(15, 0)
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/* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register */
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#define MPAMF_CCAP_IDR_CMAX_WD GENMASK(5, 0)
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/* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */
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#define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0)
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#define MPAMF_MBW_IDR_HAS_MIN BIT(10)
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#define MPAMF_MBW_IDR_HAS_MAX BIT(11)
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#define MPAMF_MBW_IDR_HAS_PBM BIT(12)
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#define MPAMF_MBW_IDR_HAS_PROP BIT(13)
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#define MPAMF_MBW_IDR_WINDWR BIT(14)
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#define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16)
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/* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */
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#define MPAMF_PRI_IDR_HAS_INTPRI BIT(0)
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#define MPAMF_PRI_IDR_INTPRI_0_IS_LOW BIT(1)
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#define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4)
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#define MPAMF_PRI_IDR_HAS_DSPRI BIT(16)
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#define MPAMF_PRI_IDR_DSPRI_0_IS_LOW BIT(17)
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#define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20)
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/* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */
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#define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0)
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#define MPAMF_CSUMON_IDR_HAS_CAPTURE BIT(31)
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/* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */
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#define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0)
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#define MPAMF_MBWUMON_IDR_HAS_RWBW BIT(28)
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#define MPAMF_MBWUMON_IDR_LWD BIT(29)
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#define MPAMF_MBWUMON_IDR_HAS_LONG BIT(30)
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#define MPAMF_MBWUMON_IDR_HAS_CAPTURE BIT(31)
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/* MPAMF_PARTID_NRW_IDR - MPAM PARTID narrowing ID register */
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#define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX GENMASK(15, 0)
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/* MPAMF_IIDR - MPAM implementation ID register */
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#define MPAMF_IIDR_PRODUCTID GENMASK(31, 20)
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#define MPAMF_IIDR_PRODUCTID_SHIFT 20
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#define MPAMF_IIDR_VARIANT GENMASK(19, 16)
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#define MPAMF_IIDR_VARIANT_SHIFT 16
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#define MPAMF_IIDR_REVISON GENMASK(15, 12)
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#define MPAMF_IIDR_REVISON_SHIFT 12
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#define MPAMF_IIDR_IMPLEMENTER GENMASK(11, 0)
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#define MPAMF_IIDR_IMPLEMENTER_SHIFT 0
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/* MPAMF_AIDR - MPAM architecture ID register */
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#define MPAMF_AIDR_ARCH_MAJOR_REV GENMASK(7, 4)
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#define MPAMF_AIDR_ARCH_MINOR_REV GENMASK(3, 0)
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/* MPAMCFG_PART_SEL - MPAM partition configuration selection register */
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#define MPAMCFG_PART_SEL_PARTID_SEL GENMASK(15, 0)
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#define MPAMCFG_PART_SEL_INTERNAL BIT(16)
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#define MPAMCFG_PART_SEL_RIS GENMASK(27, 24)
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/* MPAMCFG_CMAX - MPAM cache portion bitmap partition configuration register */
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#define MPAMCFG_CMAX_CMAX GENMASK(15, 0)
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/*
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* MPAMCFG_MBW_MIN - MPAM memory minimum bandwidth partitioning configuration
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* register
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*/
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#define MPAMCFG_MBW_MIN_MIN GENMASK(15, 0)
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/*
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* MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning configuration
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* register
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*/
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#define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0)
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#define MPAMCFG_MBW_MAX_HARDLIM BIT(31)
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/*
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* MPAMCFG_MBW_WINWD - MPAM memory bandwidth partitioning window width
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* register
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*/
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#define MPAMCFG_MBW_WINWD_US_FRAC GENMASK(7, 0)
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#define MPAMCFG_MBW_WINWD_US_INT GENMASK(23, 8)
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/* MPAMCFG_PRI - MPAM priority partitioning configuration register */
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#define MPAMCFG_PRI_INTPRI GENMASK(15, 0)
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#define MPAMCFG_PRI_DSPRI GENMASK(31, 16)
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/*
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* MPAMCFG_MBW_PROP - Memory bandwidth proportional stride partitioning
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* configuration register
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*/
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#define MPAMCFG_MBW_PROP_STRIDEM1 GENMASK(15, 0)
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#define MPAMCFG_MBW_PROP_EN BIT(31)
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/*
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* MPAMCFG_INTPARTID - MPAM internal partition narrowing configuration register
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*/
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#define MPAMCFG_INTPARTID_INTPARTID GENMASK(15, 0)
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#define MPAMCFG_INTPARTID_INTERNAL BIT(16)
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/* MSMON_CFG_MON_SEL - Memory system performance monitor selection register */
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#define MSMON_CFG_MON_SEL_MON_SEL GENMASK(7, 0)
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#define MSMON_CFG_MON_SEL_RIS GENMASK(27, 24)
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/* MPAMF_ESR - MPAM Error Status Register */
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#define MPAMF_ESR_PARTID_OR_MON GENMASK(15, 0)
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#define MPAMF_ESR_PMG GENMASK(23, 16)
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#define MPAMF_ESR_ERRCODE GENMASK(27, 24)
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#define MPAMF_ESR_OVRWR BIT(31)
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#define MPAMF_ESR_RIS GENMASK(35, 32)
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/* MPAMF_ECR - MPAM Error Control Register */
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#define MPAMF_ECR_INTEN BIT(0)
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/* Error conditions in accessing memory mapped registers */
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#define MPAM_ERRCODE_NONE 0
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#define MPAM_ERRCODE_PARTID_SEL_RANGE 1
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#define MPAM_ERRCODE_REQ_PARTID_RANGE 2
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#define MPAM_ERRCODE_MSMONCFG_ID_RANGE 3
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#define MPAM_ERRCODE_REQ_PMG_RANGE 4
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#define MPAM_ERRCODE_MONITOR_RANGE 5
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#define MPAM_ERRCODE_INTPARTID_RANGE 6
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#define MPAM_ERRCODE_UNEXPECTED_INTERNAL 7
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/*
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* MSMON_CFG_CSU_FLT - Memory system performance monitor configure cache storage
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* usage monitor filter register
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*/
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#define MSMON_CFG_CSU_FLT_PARTID GENMASK(15, 0)
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#define MSMON_CFG_CSU_FLT_PMG GENMASK(23, 16)
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/*
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* MSMON_CFG_CSU_CTL - Memory system performance monitor configure cache storage
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* usage monitor control register
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* MSMON_CFG_MBWU_CTL - Memory system performance monitor configure memory
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* bandwidth usage monitor control register
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*/
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#define MSMON_CFG_x_CTL_TYPE GENMASK(7, 0)
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#define MSMON_CFG_x_CTL_MATCH_PARTID BIT(16)
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#define MSMON_CFG_x_CTL_MATCH_PMG BIT(17)
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#define MSMON_CFG_x_CTL_SCLEN BIT(19)
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#define MSMON_CFG_x_CTL_SUBTYPE GENMASK(23, 20)
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#define MSMON_CFG_x_CTL_OFLOW_FRZ BIT(24)
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#define MSMON_CFG_x_CTL_OFLOW_INTR BIT(25)
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#define MSMON_CFG_x_CTL_OFLOW_STATUS BIT(26)
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#define MSMON_CFG_x_CTL_CAPT_RESET BIT(27)
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#define MSMON_CFG_x_CTL_CAPT_EVNT GENMASK(30, 28)
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#define MSMON_CFG_x_CTL_EN BIT(31)
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#define MSMON_CFG_MBWU_CTL_TYPE_MBWU 0x42
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#define MSMON_CFG_MBWU_CTL_TYPE_CSU 0x43
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#define MSMON_CFG_MBWU_CTL_SUBTYPE_NONE 0
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#define MSMON_CFG_MBWU_CTL_SUBTYPE_READ 1
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#define MSMON_CFG_MBWU_CTL_SUBTYPE_WRITE 2
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#define MSMON_CFG_MBWU_CTL_SUBTYPE_BOTH 3
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#define MSMON_CFG_MBWU_CTL_SUBTYPE_MAX 3
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#define MSMON_CFG_MBWU_CTL_SUBTYPE_MASK 0x3
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/*
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* MSMON_CFG_MBWU_FLT - Memory system performance monitor configure memory
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* bandwidth usage monitor filter register
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*/
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#define MSMON_CFG_MBWU_FLT_PARTID GENMASK(15, 0)
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#define MSMON_CFG_MBWU_FLT_PMG GENMASK(23, 16)
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#define MSMON_CFG_MBWU_FLT_RWBW GENMASK(31, 30)
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/*
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* MSMON_CSU - Memory system performance monitor cache storage usage monitor
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* register
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* MSMON_CSU_CAPTURE - Memory system performance monitor cache storage usage
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* capture register
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* MSMON_MBWU - Memory system performance monitor memory bandwidth usage
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* monitor register
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* MSMON_MBWU_CAPTURE - Memory system performance monitor memory bandwidth usage
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* capture register
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*/
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#define MSMON___VALUE GENMASK(30, 0)
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#define MSMON___NRDY BIT(31)
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#define MSMON___NRDY_L BIT(63)
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#define MSMON___L_VALUE GENMASK(43, 0)
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#define MSMON___LWD_VALUE GENMASK(62, 0)
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/*
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* MSMON_CAPT_EVNT - Memory system performance monitoring capture event
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* generation register
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*/
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#define MSMON_CAPT_EVNT_NOW BIT(0)
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#endif /* MPAM_INTERNAL_H */
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