168 lines
3.1 KiB
C
168 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2024 Huawei Technologies Co., Ltd */
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#ifndef ROCE_POST_H
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#define ROCE_POST_H
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#include <linux/types.h>
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#include <rdma/ib_verbs.h>
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#include "roce_wqe_format.h"
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#include "roce_xqe_format.h"
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#define ROCE_SQ_DB_TYPE 2
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#define ROCE_UD_MTU_SHIFT 3 /* 4K mtu */
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#define ROCE_IMM_EXT_LEN 4
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#define ROCE_TASK_SEG_ALIGN 8
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#define ROCE_ATOMIC_WR atomic_wr
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#define ROCE_RDMA_WR rdma_wr
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#define ROCE_REG_WR reg_wr
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#define ROCE_UD_WR ud_wr
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enum roce_tsl_8_byte_aligned_size_e {
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ROCE_SEND_LOCAL_WQE_TSL = 2,
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ROCE_RDMA_WQE_TSL = 4,
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ROCE_ATOMIC_CWP_WQE_TSL = 6,
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ROCE_UD_WQE_COM_TSL = 8
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};
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enum {
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ROCE_WQE_OPCODE_SEND = 0x00,
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ROCE_WQE_OPCODE_SEND_INVAL = 0x01,
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ROCE_WQE_OPCODE_SEND_IMM = 0x02,
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ROCE_WQE_OPCODE_RDMA_WRITE = 0x04,
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ROCE_WQE_OPCODE_RDMA_WRITE_IMM = 0x05,
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ROCE_WQE_OPCODE_RDMA_READ = 0x08,
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ROCE_WQE_OPCODE_ATOMIC_CMP_SWP = 0x0c,
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ROCE_WQE_OPCODE_ATOMIC_FETCH_ADD = 0x0d,
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ROCE_WQE_OPCODE_MASKED_ATOMIC_CMP_SWP = 0x0e,
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ROCE_WQE_OPCODE_MASKED_ATOMIC_FETCH_ADD = 0x0f,
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ROCE_WQE_OPCODE_FRMR = 0x10,
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ROCE_WQE_OPCODE_LOCAL_INVAL = 0x11,
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ROCE_WQE_OPCODE_BIND_MW = 0x12,
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ROCE_WQE_OPCODE_REG_SIG_MR = 0x13 /* Extended for further local opreation */
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};
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enum {
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ROCE_DWQE_DB_SUBTYPE_SEND = 0x1,
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ROCE_DWQE_DB_SUBTYPE_SEND_IMM = 0x2,
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ROCE_DWQE_DB_SUBTYPE_RDMA_WRITE = 0x3,
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ROCE_DWQE_DB_SUBTYPE_RDMA_WRITE_IMM = 0x4,
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ROCE_DWQE_DB_SUBTYPE_RDMA_READ = 0x5,
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ROCE_DWQE_DB_SUBTYPE_ATOMIC_CMP_SWP = 0x6,
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ROCE_DWQE_DB_SUBTYPE_ATOMIC_FETCH_ADD = 0x7
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};
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/* UD send WQE task seg1 */
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struct roce3_wqe_ud_tsk_seg_cycle1 {
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union roce3_wqe_tsk_com_seg common;
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/* DW0 */
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u32 data_len;
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/* DW1 */
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u32 immdata_invkey;
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/* DW2 */
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/*
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* 0: No limit on the static rate (100% port speed)
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* 1-6: reserved
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* 7: 2.5 Gb/s. 8: 10 Gb/s. 9: 30 Gb/s. 10: 5 Gb/s. 11: 20 Gb/s.
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* 12: 40 Gb/s. 13: 60 Gb/s. 14: 80 Gb/s.15: 120 Gb/s.
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*/
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union {
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struct {
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u32 pd : 18;
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u32 rsvd0 : 6;
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u32 stat_rate : 4;
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u32 rsvd1 : 3;
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u32 fl : 1;
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} bs;
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u32 value;
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} dw2;
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/* DW3 */
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union {
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struct {
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u32 hop_limit : 8;
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u32 sgid_idx : 7;
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u32 rsvd0 : 1;
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u32 port : 4;
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u32 rsvd1 : 4;
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u32 tc : 8;
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} bs;
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u32 value;
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} dw3;
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/* DW4 */
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union {
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struct {
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u32 flow_label : 20;
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u32 rsvd0 : 4;
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u32 smac_index : 3;
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u32 rsvd1 : 5;
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} bs;
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u32 value;
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} dw4;
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/* DW5~8 */
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u8 dgid[16];
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/* DW9 */
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union {
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struct {
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u32 dst_qp : 24;
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u32 rsvd : 8;
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} bs;
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u32 value;
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} dw9;
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/* DW10 */
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u32 qkey;
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};
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/* UD send WQE task seg2; */
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struct roce3_wqe_ud_tsk_seg_cycle2 {
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/* DW0 */
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union {
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struct {
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u32 dmac_h16 : 16;
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u32 vlan_id : 12;
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u32 cfi : 1;
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u32 vlan_prio : 3;
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} bs;
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u32 value;
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} dw0;
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/* DW1 */
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u32 dmac_l32;
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};
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struct roce3_post_send_normal_param {
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struct roce3_wqe_ctrl_seg *ctrl_seg;
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union roce3_wqe_tsk_com_seg *tsk_com_seg;
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u32 wqe_size;
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u8 *wqe;
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struct roce3_wqe_data_seg *dseg;
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union roce_sq_db sq_db;
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u32 wr_num; /* record posted WR numbers */
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u32 index; /* WQEBB id */
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int inline_flag; /* Inline flag */
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u32 data_len;
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u32 *data_len_addr;
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u32 sq_rmd_size;
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s32 opcode;
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s32 cycle;
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struct roce3_wqe_ctrl_seg ctrl_seg_tmp;
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unsigned long flags;
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};
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#endif /* ROCE_POST_H */
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