56 lines
1.2 KiB
C
56 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Definitions for use with the sw64 PMC interface.
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*/
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#ifndef _ASM_SW64_PMC_H
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#define _ASM_SW64_PMC_H
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#define PMC_PC0 0
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#define PMC_PC1 1
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/* Following commands are implemented on all CPUs */
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#define PMC_CMD_DISABLE 0
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#define PMC_CMD_ENABLE 1
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#define PMC_CMD_EVENT_BASE 2
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#define PMC_CMD_PM 4
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#define PMC_CMD_READ 5
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#define PMC_CMD_READ_CLEAR 6
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#define PMC_CMD_WRITE_BASE 7
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#define PMC_DISABLE_BASE 1
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#define PMC_ENABLE_BASE 1
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#define PC0_RAW_BASE 0x0
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#define PC1_RAW_BASE 0x100
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#define PC0_MAX 0xF
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#define PC1_MAX 0x3D
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#define SW64_PERFCTRL_KM 2
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#define SW64_PERFCTRL_UM 3
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#define SW64_PERFCTRL_AM 4
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/* pc0 events */
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#define PC0_INSTRUCTIONS 0x0
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#define PC0_BRANCH_INSTRUCTIONS 0x3
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#define PC0_CPU_CYCLES 0x8
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#define PC0_ITB_READ 0x9
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#define PC0_DTB_READ 0xA
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#define PC0_ICACHE_READ 0xB
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#define PC0_DCACHE_READ 0xC
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#define PC0_SCACHE_REFERENCES 0xD
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/* pc1 events */
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#define PC1_BRANCH_MISSES 0xB
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#define PC1_SCACHE_MISSES 0x10
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#define PC1_ICACHE_READ_MISSES 0x16
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#define PC1_ITB_MISSES 0x17
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#define PC1_DTB_SINGLE_MISSES 0x30
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#define PC1_DCACHE_MISSES 0x32
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#define MAX_HWEVENTS 2
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#define PMC_COUNT_MASK ((1UL << 58) - 1)
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#endif /* _ASM_SW64_PMC_H */
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