168 lines
4.9 KiB
C
168 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2021 Arm Ltd. */
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#ifndef __ASM__MPAM_H
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#define __ASM__MPAM_H
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#include <linux/arm_mpam.h>
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#include <linux/bitops.h>
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#include <linux/bitfield.h>
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#include <linux/init.h>
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#include <linux/jump_label.h>
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#include <linux/percpu.h>
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#include <linux/sched.h>
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#include <asm/cpucaps.h>
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#include <asm/cpufeature.h>
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#include <asm/sysreg.h>
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/* CPU Registers */
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#define MPAM_SYSREG_EN BIT_ULL(63)
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#define MPAM_SYSREG_TRAP_IDR BIT_ULL(58)
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#define MPAM_SYSREG_TRAP_MPAM0_EL1 BIT_ULL(49)
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#define MPAM_SYSREG_TRAP_MPAM1_EL1 BIT_ULL(48)
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#define MPAM_SYSREG_PMG_D GENMASK(47, 40)
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#define MPAM_SYSREG_PMG_I GENMASK(39, 32)
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#define MPAM_SYSREG_PARTID_D GENMASK(31, 16)
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#define MPAM_SYSREG_PARTID_I GENMASK(15, 0)
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#define MPAMIDR_PMG_MAX GENMASK(40, 32)
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#define MPAMIDR_PMG_MAX_SHIFT 32
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#define MPAMIDR_PMG_MAX_LEN 8
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#define MPAMIDR_VPMR_MAX GENMASK(20, 18)
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#define MPAMIDR_VPMR_MAX_SHIFT 18
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#define MPAMIDR_VPMR_MAX_LEN 3
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#define MPAMIDR_HAS_HCR BIT(17)
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#define MPAMIDR_HAS_HCR_SHIFT 17
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#define MPAMIDR_PARTID_MAX GENMASK(15, 0)
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#define MPAMIDR_PARTID_MAX_SHIFT 0
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#define MPAMIDR_PARTID_MAX_LEN 15
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#define MPAMHCR_EL0_VPMEN BIT_ULL(0)
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#define MPAMHCR_EL1_VPMEN BIT_ULL(1)
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#define MPAMHCR_GSTAPP_PLK BIT_ULL(8)
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#define MPAMHCR_TRAP_MPAMIDR BIT_ULL(31)
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/* Properties of the VPM registers */
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#define MPAM_VPM_NUM_REGS 8
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#define MPAM_VPM_PARTID_LEN 16
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#define MPAM_VPM_PARTID_MASK 0xffff
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#define MPAM_VPM_REG_LEN 64
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#define MPAM_VPM_PARTIDS_PER_REG (MPAM_VPM_REG_LEN / MPAM_VPM_PARTID_LEN)
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#define MPAM_VPM_MAX_PARTID (MPAM_VPM_NUM_REGS * MPAM_VPM_PARTIDS_PER_REG)
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DECLARE_STATIC_KEY_FALSE(arm64_mpam_has_hcr);
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DECLARE_STATIC_KEY_FALSE(mpam_enabled);
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DECLARE_PER_CPU(u64, arm64_mpam_default);
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DECLARE_PER_CPU(u64, arm64_mpam_current);
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/* check whether all CPUs have MPAM support */
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static __always_inline bool mpam_cpus_have_feature(void)
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{
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if (IS_ENABLED(CONFIG_ARM64_MPAM))
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return cpus_have_final_cap(ARM64_MPAM);
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return false;
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}
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/* check whether all CPUs have MPAM virtualisation support */
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static __always_inline bool mpam_cpus_have_mpam_hcr(void)
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{
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if (IS_ENABLED(CONFIG_ARM64_MPAM))
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return static_branch_unlikely(&arm64_mpam_has_hcr);
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return false;
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}
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/* enable MPAM virtualisation support */
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static inline void __init __enable_mpam_hcr(void)
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{
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if (IS_ENABLED(CONFIG_ARM64_MPAM))
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static_branch_enable(&arm64_mpam_has_hcr);
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}
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/*
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* The resctrl filesystem writes to the partid/pmg values for threads and CPUs,
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* which may race with reads in __mpam_sched_in(). Ensure only one of the old
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* or new values are used. Particular care should be taken with the pmg field
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* as __mpam_sched_in() may read a partid and pmg that don't match, causing
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* this value to be stored with cache allocations, despite being considered
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* 'free' by resctrl.
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*
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* A value in struct thread_info is used instead of struct task_struct as the
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* cpu's u64 register format is used, but struct task_struct has two u32'.
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*/
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static inline void mpam_set_cpu_defaults(int cpu, u16 partid_d, u16 partid_i,
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u8 pmg_d, u8 pmg_i)
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{
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u64 default_val;
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default_val = FIELD_PREP(MPAM_SYSREG_PARTID_D, partid_d);
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default_val |= FIELD_PREP(MPAM_SYSREG_PARTID_I, partid_i);
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default_val |= FIELD_PREP(MPAM_SYSREG_PMG_D, pmg_d);
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default_val |= FIELD_PREP(MPAM_SYSREG_PMG_I, pmg_i);
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WRITE_ONCE(per_cpu(arm64_mpam_default, cpu), default_val);
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}
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static inline void mpam_set_task_partid_pmg(struct task_struct *tsk,
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u16 partid_d, u16 partid_i,
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u8 pmg_d, u8 pmg_i)
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{
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#ifdef CONFIG_ARM64_MPAM
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u64 regval;
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regval = FIELD_PREP(MPAM_SYSREG_PARTID_D, partid_d);
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regval |= FIELD_PREP(MPAM_SYSREG_PARTID_I, partid_i);
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regval |= FIELD_PREP(MPAM_SYSREG_PMG_D, pmg_d);
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regval |= FIELD_PREP(MPAM_SYSREG_PMG_I, pmg_i);
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WRITE_ONCE(task_thread_info(tsk)->mpam_partid_pmg, regval);
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#endif
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}
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static inline u64 mpam_get_regval(struct task_struct *tsk)
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{
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#ifdef CONFIG_ARM64_MPAM
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return READ_ONCE(task_thread_info(tsk)->mpam_partid_pmg);
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#else
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return 0;
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#endif
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}
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static inline void resctrl_arch_set_rmid(struct task_struct *tsk, u32 rmid)
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{
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#ifdef CONFIG_ARM64_MPAM
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u64 regval = mpam_get_regval(tsk);
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regval &= ~MPAM_SYSREG_PMG_D;
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regval &= ~MPAM_SYSREG_PMG_I;
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regval |= FIELD_PREP(MPAM_SYSREG_PMG_D, rmid);
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regval |= FIELD_PREP(MPAM_SYSREG_PMG_I, rmid);
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WRITE_ONCE(task_thread_info(tsk)->mpam_partid_pmg, regval);
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#endif
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}
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static inline void mpam_thread_switch(struct task_struct *tsk)
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{
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u64 oldregval;
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int cpu = smp_processor_id();
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u64 regval = mpam_get_regval(tsk);
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if (!IS_ENABLED(CONFIG_ARM64_MPAM) ||
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!static_branch_likely(&mpam_enabled))
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return;
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if (regval == READ_ONCE(mpam_resctrl_default_group))
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regval = READ_ONCE(per_cpu(arm64_mpam_default, cpu));
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oldregval = READ_ONCE(per_cpu(arm64_mpam_current, cpu));
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if (oldregval == regval)
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return;
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/* Synchronising this write is left until the ERET to EL0 */
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write_sysreg_s(regval, SYS_MPAM0_EL1);
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WRITE_ONCE(per_cpu(arm64_mpam_current, cpu), regval);
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}
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#endif /* __ASM__MPAM_H */
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