146 lines
3.7 KiB
C
146 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_SW64_PCI_H
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#define _ASM_SW64_PCI_H
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#ifdef __KERNEL__
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#include <linux/spinlock.h>
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#include <linux/dma-mapping.h>
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#include <linux/scatterlist.h>
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/*
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* The following structure is used to manage multiple PCI busses.
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*/
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struct pci_dev;
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struct pci_bus;
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struct resource;
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struct sunway_iommu;
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struct page;
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/* A controller. Used to manage multiple PCI busses. */
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struct pci_controller {
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struct pci_controller *next;
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struct pci_bus *bus;
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struct resource *io_space;
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struct resource *mem_space;
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struct resource *pre_mem_space;
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struct resource *busn_space;
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unsigned long sparse_mem_base;
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unsigned long dense_mem_base;
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unsigned long sparse_io_base;
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unsigned long dense_io_base;
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/* This one's for the kernel only. It's in KSEG somewhere. */
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unsigned long ep_config_space_base;
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unsigned long rc_config_space_base;
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unsigned long index;
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unsigned long node;
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DECLARE_BITMAP(piu_msiconfig, 256);
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int int_irq;
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int service_irq;
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/* For compatibility with current (as of July 2003) pciutils
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* and XFree86. Eventually will be removed.
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*/
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unsigned int need_domain_info;
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bool iommu_enable;
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struct sunway_iommu *pci_iommu;
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int first_busno;
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int last_busno;
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int self_busno;
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void *sysdata;
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};
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/* Override the logic in pci_scan_bus for skipping already-configured
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* bus numbers.
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*/
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#define pcibios_assign_all_busses() 1
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#define PCIBIOS_MIN_IO 0
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#define PCIBIOS_MIN_MEM 0
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/* generic pci stuff */
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#include <asm-generic/pci.h>
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extern void __init sw64_init_pci(void);
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extern void __init sw64_device_interrupt(unsigned long vector);
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extern void __init sw64_init_irq(void);
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extern void __init sw64_init_arch(void);
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extern struct pci_ops sw64_pci_ops;
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extern int sw64_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
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extern struct pci_controller *hose_head;
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#ifdef CONFIG_SUNWAY_IOMMU
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extern struct syscore_ops iommu_cpu_syscore_ops;
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#endif
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#ifdef CONFIG_PCI_DOMAINS
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static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
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static inline int pci_proc_domain(struct pci_bus *bus)
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{
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struct pci_controller *hose = bus->sysdata;
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return hose->need_domain_info;
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}
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#endif
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#ifdef CONFIG_NUMA
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static inline int __pcibus_to_node(const struct pci_bus *bus)
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{
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struct pci_controller *hose;
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hose = bus->sysdata;
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if (!node_online(hose->node))
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return next_node_in(hose->node, node_online_map);
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else
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return hose->node;
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}
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#define pcibus_to_node(bus) __pcibus_to_node(bus)
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#endif
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#endif /* __KERNEL__ */
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/* Values for the `which' argument to sys_pciconfig_iobase. */
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#define IOBASE_HOSE 0
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#define IOBASE_SPARSE_MEM 1
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#define IOBASE_DENSE_MEM 2
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#define IOBASE_SPARSE_IO 3
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#define IOBASE_DENSE_IO 4
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#define IOBASE_ROOT_BUS 5
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#define IOBASE_FROM_HOSE 0x10000
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extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val,
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size_t count);
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extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val,
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size_t count);
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extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
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struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state);
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extern void pci_adjust_legacy_attr(struct pci_bus *bus,
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enum pci_mmap_state mmap_type);
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#define HAVE_PCI_LEGACY 1
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extern int pci_create_resource_files(struct pci_dev *dev);
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extern void pci_remove_resource_files(struct pci_dev *dev);
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extern void __init reserve_mem_for_pci(void);
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extern int chip_pcie_configure(struct pci_controller *hose);
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#define PCI_VENDOR_ID_JN 0x5656
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#define PCI_DEVICE_ID_CHIP3 0x3231
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#define PCI_DEVICE_ID_JN_PCIESW 0x1000
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#define PCI_DEVICE_ID_JN_PCIEUSIP 0x1200
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#define PCI_DEVICE_ID_JN_PCIE2PCI 0x1314
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#define NR_IRQ_VECTORS NR_IRQS
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#define LAST_DEVICE_VECTOR 31
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#define PCITODMA_OFFSET 0x0 /*0 offset*/
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#endif /* _ASM_SW64_PCI_H */
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