292 lines
7.7 KiB
C
292 lines
7.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_SW64_IO_H
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#define _ASM_SW64_IO_H
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#ifdef __KERNEL__
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <asm/compiler.h>
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#include <asm/pgtable.h>
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/* The generic header contains only prototypes. Including it ensures that
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* the implementation we have here matches that interface.
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*/
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#include <asm-generic/iomap.h>
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/* We don't use IO slowdowns on the sw64, but.. */
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#define __SLOW_DOWN_IO do { } while (0)
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#define SLOW_DOWN_IO do { } while (0)
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/*
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* Change virtual addresses to physical addresses and vv.
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*/
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static inline unsigned long virt_to_phys(void *address)
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{
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return __pa(address);
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}
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static inline void *phys_to_virt(unsigned long address)
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{
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return __va(address);
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}
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#define page_to_phys(page) page_to_pa(page)
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/* Maximum PIO space address supported? */
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#define IO_SPACE_LIMIT 0xffffffffffffffff
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/*
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* Change addresses as seen by the kernel (virtual) to addresses as
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* seen by a device (bus), and vice versa.
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*
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* Note that this only works for a limited range of kernel addresses,
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* and very well may not span all memory. Consider this interface
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* deprecated in favour of the DMA-mapping API.
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*/
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static inline unsigned long __deprecated virt_to_bus(void *address)
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{
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return virt_to_phys(address);
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}
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#define isa_virt_to_bus virt_to_bus
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static inline void * __deprecated bus_to_virt(unsigned long address)
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{
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void *virt;
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/* This check is a sanity check but also ensures that bus address 0
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* maps to virtual address 0 which is useful to detect null pointers
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* (the NCR driver is much simpler if NULL pointers are preserved).
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*/
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virt = phys_to_virt(address);
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return (long)address <= 0 ? NULL : virt;
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}
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#define isa_bus_to_virt bus_to_virt
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/*
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* There are different chipsets to interface the sw64 CPUs to the world.
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*/
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#define IO_CONCAT(a, b) _IO_CONCAT(a, b)
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#define _IO_CONCAT(a, b) a ## _ ## b
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#include <asm/sw64io.h>
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/*
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* Generic IO read/write. These perform native-endian accesses.
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*/
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#define __raw_writeb __raw_writeb
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static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
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{
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asm volatile("stb %0, 0(%1)" : : "r" (val), "r" (addr));
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}
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#define __raw_writew __raw_writew
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static inline void __raw_writew(u16 val, volatile void __iomem *addr)
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{
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asm volatile("sth %0, 0(%1)" : : "r" (val), "r" (addr));
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}
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#define __raw_writel __raw_writel
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static inline void __raw_writel(u32 val, volatile void __iomem *addr)
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{
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asm volatile("stw %0, 0(%1)" : : "r" (val), "r" (addr));
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}
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#define __raw_writeq __raw_writeq
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static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
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{
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asm volatile("stl %0, 0(%1)" : : "r" (val), "r" (addr));
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}
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#define __raw_readb __raw_readb
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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u8 val;
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asm volatile("ldbu %0, 0(%1)" : "=r" (val) : "r" (addr));
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return val;
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}
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#define __raw_readw __raw_readw
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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u16 val;
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asm volatile("ldhu %0, 0(%1)" : "=r" (val) : "r" (addr));
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return val;
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}
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#define __raw_readl __raw_readl
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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u32 val;
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asm volatile("ldw %0, 0(%1)\n"
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"zapnot %0, 0xf, %0\n"
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: "=r" (val) : "r" (addr));
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return val;
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}
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#define __raw_readq __raw_readq
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static inline u64 __raw_readq(const volatile void __iomem *addr)
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{
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u64 val;
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asm volatile("ldl %0, 0(%1)" : "=r" (val) : "r" (addr));
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return val;
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}
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/* IO barriers */
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#define __iormb() rmb()
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#define __iowmb() wmb()
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#define mmiowb() do { } while (0)
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/*
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* Relaxed I/O memory access primitives. These follow the Device memory
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* ordering rules but do not guarantee any ordering relative to Normal memory
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* accesses.
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*/
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#define readb_relaxed(c) __raw_readb(c)
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#define readw_relaxed(c) __raw_readw(c)
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#define readl_relaxed(c) __raw_readl(c)
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#define readq_relaxed(c) __raw_readq(c)
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#define writeb_relaxed(v, c) __raw_writeb((v), (c))
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#define writew_relaxed(v, c) __raw_writew((v), (c))
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#define writel_relaxed(v, c) __raw_writel((v), (c))
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#define writeq_relaxed(v, c) __raw_writeq((v), (c))
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/*
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* I/O memory access primitives. Reads are ordered relative to any
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* following Normal memory access. Writes are ordered relative to any prior
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* Normal memory access.
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*/
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#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
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#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
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#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
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#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
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#define writeb(v, c) ({ __iowmb(); writeb_relaxed((v), (c)); })
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#define writew(v, c) ({ __iowmb(); writew_relaxed((v), (c)); })
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#define writel(v, c) ({ __iowmb(); writel_relaxed((v), (c)); })
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#define writeq(v, c) ({ __iowmb(); writeq_relaxed((v), (c)); })
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/*
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* We always have external versions of these routines.
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*/
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extern u8 inb(unsigned long port);
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extern u16 inw(unsigned long port);
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extern u32 inl(unsigned long port);
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extern void outb(u8 b, unsigned long port);
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extern void outw(u16 b, unsigned long port);
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extern void outl(u32 b, unsigned long port);
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/*
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* Mapping from port numbers to __iomem space is pretty easy.
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*/
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static inline void __iomem *ioportmap(unsigned long addr)
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{
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return sw64_platform->ioportmap(addr);
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}
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static inline void __iomem *__ioremap(phys_addr_t addr, size_t size,
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pgprot_t prot)
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{
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unsigned long tmp = addr | PAGE_OFFSET;
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return (void __iomem *)(tmp);
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}
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#define ioremap(addr, size) __ioremap((addr), (size), PAGE_KERNEL)
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#define ioremap_nocache(addr, size) __ioremap((addr), (size), PAGE_KERNEL)
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#define ioremap_cache(addr, size) __ioremap((addr), (size), PAGE_KERNEL)
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#define ioremap_uc ioremap_nocache
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static inline void __iounmap(volatile void __iomem *addr)
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{
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}
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#define iounmap __iounmap
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static inline int __is_ioaddr(unsigned long addr)
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{
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return addr >= (PAGE_OFFSET | IO_BASE);
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}
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#define __is_ioaddr(a) __is_ioaddr((unsigned long)(a))
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static inline int __is_mmio(const volatile void __iomem *xaddr)
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{
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unsigned long addr = (unsigned long)xaddr;
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return (addr & 0x100000000UL) == 0;
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}
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#define ioread16be(p) be16_to_cpu(ioread16(p))
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#define ioread32be(p) be32_to_cpu(ioread32(p))
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#define iowrite16be(v, p) iowrite16(cpu_to_be16(v), (p))
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#define iowrite32be(v, p) iowrite32(cpu_to_be32(v), (p))
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#define inb_p inb
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#define inw_p inw
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#define inl_p inl
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#define outb_p outb
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#define outw_p outw
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#define outl_p outl
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/*
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* String version of IO memory access ops:
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*/
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extern void memcpy_fromio(void *, const volatile void __iomem *, long);
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extern void memcpy_toio(volatile void __iomem *, const void *, long);
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extern void _memset_c_io(volatile void __iomem *, unsigned long, long);
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static inline void memset_io(volatile void __iomem *addr, u8 c, long len)
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{
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_memset_c_io(addr, 0x0101010101010101UL * c, len);
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}
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#define __HAVE_ARCH_MEMSETW_IO
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static inline void memsetw_io(volatile void __iomem *addr, u16 c, long len)
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{
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_memset_c_io(addr, 0x0001000100010001UL * c, len);
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}
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/*
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* String versions of in/out ops:
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*/
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extern void insb(unsigned long port, void *dst, unsigned long count);
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extern void insw(unsigned long port, void *dst, unsigned long count);
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extern void insl(unsigned long port, void *dst, unsigned long count);
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extern void outsb(unsigned long port, const void *src, unsigned long count);
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extern void outsw(unsigned long port, const void *src, unsigned long count);
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extern void outsl(unsigned long port, const void *src, unsigned long count);
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/*
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* These defines will override the defaults when doing RTC queries
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*/
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#define RTC_PORT(x) (0x70 + (x))
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#define RTC_ALWAYS_BCD 0
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem
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* access
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*/
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#define xlate_dev_mem_ptr(p) __va(p)
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/*
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* Convert a virtual cached pointer to an uncached pointer
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*/
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#define xlate_dev_kmem_ptr(p) p
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#endif /* __KERNEL__ */
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#endif /* _ASM_SW64_IO_H */
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