318 lines
9.1 KiB
C
318 lines
9.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_SW64_CHIP3_IO_H
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#define _ASM_SW64_CHIP3_IO_H
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#include <asm/platform.h>
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#define IO_BASE (0x1UL << 47)
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#define PCI_BASE (0x1UL << 43)
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#define PCI_IOR0_BASE (0x2UL << 32)
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#define PCI_IOR1_BASE (0x3UL << 32)
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#ifdef CONFIG_SW64_FPGA
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#define PCI_RC_CFG (0x4UL << 32)
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#else
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#define PCI_RC_CFG (0x5UL << 32)
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#endif
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#define PCI_EP_CFG (0x3UL << 33)
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#define PCI_LEGACY_IO (0x1UL << 32)
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#define PCI_LEGACY_IO_SIZE (0x100000000UL)
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#define PCI_MEM_UNPRE 0x0UL
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#define PCI_32BIT_MEMIO (0xe0000000UL)
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#define PCI_32BIT_MEMIO_SIZE (0x20000000UL)
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#define PCI_64BIT_MEMIO (0x1UL << 39)
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#define PCI_64BIT_MEMIO_SIZE (0x8000000000UL)
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#define IO_RC_SHIFT 40
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#define IO_NODE_SHIFT 44
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#define IO_MARK_BIT 47
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/* MSIConfig */
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#define MSICONFIG_VALID (0x1UL << 63)
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#define MSICONFIG_EN (0x1UL << 62)
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#define MSICONFIG_VECTOR_SHIFT 10
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#define SW64_PCI_IO_BASE(m, n) \
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(IO_BASE | ((m) << IO_NODE_SHIFT) | PCI_BASE | ((n) << IO_RC_SHIFT))
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#define SW64_IO_BASE(x) (IO_BASE | ((x) << IO_NODE_SHIFT))
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#define SW64_PCI0_BUS 0
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#define PCI0_BUS SW64_PCI0_BUS
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#define MAX_NR_NODES 0x2
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#define MAX_NR_RCS 0x6
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#define SW64_PCI_DEBUG 0
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#if SW64_PCI_DEBUG
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#define PCIINFO(fmt, args...) printk(fmt, ##args)
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#else
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#define PCIINFO(fmt, args...)
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#endif
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#define MCU_BASE (0x3UL << 36)
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#define CAB0_BASE (0x10UL << 32)
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#define INTPU_BASE (0x2aUL << 32)
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#define IIC0_BASE (0x31UL << 32)
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#define SPI_BASE (0x32UL << 32)
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#define UART_BASE (0x33UL << 32)
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#define IIC1_BASE (0x34UL << 32)
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#define IIC2_BASE (0x35UL << 32)
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#define GPIO_BASE (0x36UL << 32)
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#define LPC_BASE (0x37UL << 32)
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#define LPC_LEGACY_IO (0x1UL << 28 | IO_BASE | LPC_BASE)
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#define LPC_MEM_IO (0x2UL << 28 | IO_BASE | LPC_BASE)
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#define LPC_FIRMWARE_IO (0x3UL << 28 | IO_BASE | LPC_BASE)
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#define DLIA_BASE (0x20UL << 32)
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#define DLIB_BASE (0x21UL << 32)
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#define DLIC_BASE (0x22UL << 32)
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#define DLI_PHY_CTL (0x10UL << 24)
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#define PCI_VT_LEGACY_IO (IO_BASE | PCI_BASE | PCI_LEGACY_IO)
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#define PME_ENABLE_INTD_CORE0 (0x1UL << 62 | 0x1UL << 10)
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#define AER_ENABLE_INTD_CORE0 (0x1UL << 62 | 0x1UL << 10)
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/*-----------------------addr-----------------------*/
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/* CAB0 REG */
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enum {
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TRKMODE = CAB0_BASE | 0x80UL,
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};
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/* DLIA IO REG */
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enum {
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DLIA_BWTEST_PAT = DLIA_BASE | 0x100980UL,
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DLIA_PHY_VLDLANE = DLIA_BASE | DLI_PHY_CTL | 0x300UL,
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};
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/* DLIB IO REG */
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enum {
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DLIB_BWTEST_PAT = DLIB_BASE | 0x100980UL,
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DLIB_PHY_VLDLANE = DLIB_BASE | DLI_PHY_CTL | 0x300UL,
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};
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/* DLIC IO REG */
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enum {
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DLIC_BWTEST_PAT = DLIC_BASE | 0x100980UL,
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DLIC_PHY_VLDLANE = DLIC_BASE | DLI_PHY_CTL | 0x300UL,
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};
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/* INTPU REG */
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enum {
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LCORE_SLEEPY = INTPU_BASE | 0x0UL,
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LCORE_SLEEP = INTPU_BASE | 0x80UL,
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DEVICE_MISS = INTPU_BASE | 0x100UL,
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LONG_TIME = INTPU_BASE | 0x180UL,
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LCORE_IDLE = INTPU_BASE | 0x280UL,
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MT_INT_CONFIG = INTPU_BASE | 0x300UL,
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DEV_INT_CONFIG = INTPU_BASE | 0x480UL,
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FMT_ERR = INTPU_BASE | 0x700UL,
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FAULT_INT_CONFIG = INTPU_BASE | 0x780UL,
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SERR_CNTTH = INTPU_BASE | 0x880UL,
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MCUSERR_CNT = INTPU_BASE | 0x900UL,
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IRUSERR_CNT = INTPU_BASE | 0xa80UL,
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ERRRPT_EN = INTPU_BASE | 0xb00UL,
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IINT_MISS_VECTOR = INTPU_BASE | 0x1100UL,
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IINT_MIS = INTPU_BASE | 0x1180UL,
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IINT_MISS_RPTEN = INTPU_BASE | 0x1200UL,
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DEVINT_MISS_RPTEN = INTPU_BASE | 0x1280UL,
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ECCSERR = INTPU_BASE | 0x1300UL,
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ECCSERR_RPTEN = INTPU_BASE | 0x1380UL,
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ECCMERR = INTPU_BASE | 0x1400UL,
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ECCMERR_RPTEN = INTPU_BASE | 0x1480UL,
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DEVINT_WKEN = INTPU_BASE | 0x1500UL,
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NMI_INT_CONFIG = INTPU_BASE | 0x1580UL,
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DEVINTWK_INTEN = INTPU_BASE | 0x1600UL,
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};
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/* MC IO REG */
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enum {
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CFGDEC = 0x400UL,
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CFGCR = 0x480UL,
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INIT_CTRL = 0x580UL,
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CFGERR = 0xd00UL,
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FSMSTAT = 0xe00UL,
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PUB_INTERFACE = 0x1000UL,
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POWERCTRL = 0x1080UL,
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CFGMR0 = 0x1280UL,
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CFGMR1 = 0x1300UL,
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CFGMR2 = 0x1380UL,
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CFGMR3 = 0x1400UL,
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PERF_CTRL = 0x1480UL,
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MC_PERF0 = 0x1500UL,
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CFGMR4 = 0x1800UL,
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CFGMR5 = 0x1880UL,
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CFGMR6 = 0x1900UL,
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MC_CTRL = 0x1c00UL,
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MEMSERR_P = 0x1c80UL,
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MEMSERR = 0x1d00UL,
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};
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/* MCU CSR */
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enum {
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INIT_CTL = MCU_BASE | 0x680UL,
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MT_STATE = MCU_BASE | 0x700UL,
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CORE_ONLINE = MCU_BASE | 0x780UL,
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MT_INT = MCU_BASE | 0x800UL,
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MT_INT_END = MCU_BASE | 0x880UL,
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CPU_ID = MCU_BASE | 0x900UL,
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DLI_RLTD_FAULT = MCU_BASE | 0x980UL,
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DLI_RLTD_FAULT_EN = MCU_BASE | 0xa00UL,
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DLI_RLTD_FAULT_INTEN = MCU_BASE | 0xa80UL,
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FAULT_SOURCE = MCU_BASE | 0xb00UL,
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INT_SOURCE = MCU_BASE | 0xb80UL,
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CORE_STATE0 = MCU_BASE | 0xc00UL,
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CORE_STATE1 = MCU_BASE | 0xc80UL,
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CFG_INFO = MCU_BASE | 0x1100UL,
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MC_CAP_CFG = MCU_BASE | 0x1180UL,
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IO_START = MCU_BASE | 0x1300UL,
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UART_ONLINE = MCU_BASE | 0x1780UL,
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MCU_DVC_INT = MCU_BASE | 0x3000UL,
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MCU_DVC_INT_EN = MCU_BASE | 0x3080UL,
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SI_FAULT_STAT = MCU_BASE | 0x3100UL,
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SI_FAULT_EN = MCU_BASE | 0x3180UL,
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SI_FAULT_INT_EN = MCU_BASE | 0x3200UL,
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FIFO_SYNSEL = MCU_BASE | 0x3400UL,
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CPU_INFO = MCU_BASE | 0x3480UL,
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WAKEUP_CTL = MCU_BASE | 0x3500UL,
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FLAGREG = MCU_BASE | 0x3580UL,
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NMI_CTL = MCU_BASE | 0x3600UL,
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PIUPLL_CNT = MCU_BASE | 0x3680UL,
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MC_ONLINE = MCU_BASE | 0x3780UL,
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FLASH_INFO = MCU_BASE | 0x3800UL,
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RTPUSROMCNT = MCU_BASE | 0x3880UL,
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CLU_LV1_SEL = MCU_BASE | 0x3a80UL,
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CLU_LV2_SEL = MCU_BASE | 0x3b00UL,
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CLK_CTL = MCU_BASE | 0x3b80UL,
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SLEEP_WAIT_CNT = MCU_BASE | 0x4980UL,
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CHIP_ID = MCU_BASE | 0x4b00UL,
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PIU_TOP0_CONFIG = MCU_BASE | 0x4c80UL,
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PIU_TOP1_CONFIG = MCU_BASE | 0x4d00UL,
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LVDS_CTL = MCU_BASE | 0x4d80UL,
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LPC_DMAREQ_TOTH = MCU_BASE | 0x5100UL,
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DLI_ONLINE = MCU_BASE | 0x6180UL,
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LPC_DMAREQ_HADR = MCU_BASE | 0x6200UL,
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PIU_PHY_SRST_H = MCU_BASE | 0x6280UL,
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CLK_SEL_PCIE0 = MCU_BASE | 0x6280UL,
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CLK_SEL_PCIE1 = MCU_BASE | 0x6300UL,
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CLK_SEL_PCIE2 = MCU_BASE | 0x6380UL,
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CLK_SEL_PCIE3 = MCU_BASE | 0x6400UL,
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CLK_SEL_PCIE4 = MCU_BASE | 0x6480UL,
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CLK_SEL_PCIE5 = MCU_BASE | 0x6500UL,
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PERST_N_PCIE0 = MCU_BASE | 0x6680UL,
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PERST_N_PCIE1 = MCU_BASE | 0x6700UL,
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PERST_N_PCIE2 = MCU_BASE | 0x6780UL,
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PERST_N_PCIE3 = MCU_BASE | 0x6800UL,
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PERST_N_PCIE4 = MCU_BASE | 0x6880UL,
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PERST_N_PCIE5 = MCU_BASE | 0x6900UL,
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BUTTON_RST_N_PCIE0 = MCU_BASE | 0x6a80UL,
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BUTTON_RST_N_PCIE1 = MCU_BASE | 0x6b00UL,
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BUTTON_RST_N_PCIE2 = MCU_BASE | 0x6b80UL,
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BUTTON_RST_N_PCIE3 = MCU_BASE | 0x6c00UL,
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BUTTON_RST_N_PCIE4 = MCU_BASE | 0x6c80UL,
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BUTTON_RST_N_PCIE5 = MCU_BASE | 0x6d00UL,
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DUAL_CG0_FAULT = MCU_BASE | 0x6d80UL,
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DUAL_CG1_FAULT = MCU_BASE | 0x6e00UL,
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DUAL_CG2_FAULT = MCU_BASE | 0x6e80UL,
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DUAL_CG3_FAULT = MCU_BASE | 0x6f00UL,
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DUAL_CG4_FAULT = MCU_BASE | 0x6f80UL,
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DUAL_CG5_FAULT = MCU_BASE | 0x7000UL,
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DUAL_CG6_FAULT = MCU_BASE | 0x7080UL,
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DUAL_CG7_FAULT = MCU_BASE | 0x7100UL,
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DUAL_CG0_FAULT_EN = MCU_BASE | 0x7180UL,
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DUAL_CG1_FAULT_EN = MCU_BASE | 0x7200UL,
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DUAL_CG2_FAULT_EN = MCU_BASE | 0x7280UL,
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DUAL_CG3_FAULT_EN = MCU_BASE | 0x7300UL,
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DUAL_CG4_FAULT_EN = MCU_BASE | 0x7380UL,
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DUAL_CG5_FAULT_EN = MCU_BASE | 0x7400UL,
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DUAL_CG6_FAULT_EN = MCU_BASE | 0x7480UL,
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DUAL_CG7_FAULT_EN = MCU_BASE | 0x7500UL,
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DUAL_CG0_FAULT_INTEN = MCU_BASE | 0x7580UL,
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DUAL_CG1_FAULT_INTEN = MCU_BASE | 0x7600UL,
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DUAL_CG2_FAULT_INTEN = MCU_BASE | 0x7680UL,
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DUAL_CG3_FAULT_INTEN = MCU_BASE | 0x7700UL,
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DUAL_CG4_FAULT_INTEN = MCU_BASE | 0x7780UL,
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DUAL_CG5_FAULT_INTEN = MCU_BASE | 0x7800UL,
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DUAL_CG6_FAULT_INTEN = MCU_BASE | 0x7880UL,
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DUAL_CG7_FAULT_INTEN = MCU_BASE | 0x7900UL,
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SOFT_INFO0 = MCU_BASE | 0x7f00UL,
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LONG_TIME_START_EN = MCU_BASE | 0x9000UL,
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};
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/*--------------------------offset-----------------------------------*/
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/* PIU IOR0 */
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enum {
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PIUCONFIG0 = 0x0UL,
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EPDMABAR = 0x80UL,
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IOMMUSEGITEM0 = 0x100UL,
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IOMMUEXCPT_CTRL = 0x2100UL,
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MSIADDR = 0x2180UL,
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MSICONFIG0 = 0x2200UL,
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INTACONFIG = 0xa200UL,
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INTBCONFIG = 0xa280UL,
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INTCCONFIG = 0xa300UL,
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INTDCONFIG = 0xa380UL,
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AERERRINTCONFIG = 0xa400UL,
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AERERRMSICONFIG = 0xa480UL,
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PMEINTCONFIG = 0xa500UL,
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PMEMSICONFIG = 0xa580UL,
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HPINTCONFIG = 0xa600UL,
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HPMSICONFIG = 0xa680UL,
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DTBASEADDR = 0xb000UL,
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DTLB_FLUSHALL = 0xb080UL,
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DTLB_FLUSHDEV = 0xb100UL,
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PTLB_FLUSHALL = 0xb180UL,
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PTLB_FLUSHDEV = 0xb200UL,
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PTLB_FLUSHVADDR = 0xb280UL,
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PCACHE_FLUSHALL = 0xb300UL,
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PCACHE_FLUSHDEV = 0xb380UL,
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PCACHE_FLUSHPADDR = 0xb400UL,
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TIMEOUT_CONFIG = 0xb480UL,
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IOMMUEXCPT_STATUS = 0xb500UL,
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IOMMUPAGE_PADDR1 = 0xb580UL,
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IOMMUPAGE_PADDR2 = 0xb600UL,
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IOMMUPAGE_PADDR3 = 0xb680UL,
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PTLB_ACCESS = 0xb700UL,
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PTLB_ITEM_TAG = 0xb780UL,
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PTLB_ITEM_DATA = 0xb800UL,
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PCACHE_ACCESS = 0xb880UL,
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PCACHE_ITEM_TAG = 0xb900UL,
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PCACHE_ITEM_DATA0 = 0xb980UL,
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};
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/* PIU IOR1 */
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enum {
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PIUCONFIG1 = 0x0UL,
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ERRENABLE = 0x880UL,
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RCDEBUGINF1 = 0xc80UL,
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DCACONTROL = 0x1a00UL,
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DEVICEID0 = 0x1a80UL,
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};
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/* RC */
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enum {
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RC_VENDOR_ID = 0x0UL,
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RC_COMMAND = 0x80UL,
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RC_REVISION_ID = 0x100UL,
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RC_PRIMARY_BUS = 0x300UL,
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RC_MSI_CONTROL = 0xa00UL,
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RC_EXP_DEVCAP = 0xe80UL,
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RC_EXP_DEVCTL = 0xf00UL,
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RC_SLOT_CTRL = 0x1100UL,
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RC_LINK_STAT = 0x1000UL,
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RC_CONTROL = 0X1180UL,
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RC_STATUS = 0X1200UL,
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RC_EXP_DEVCTL2 = 0x1300UL,
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RC_PORT_LINK_CTL = 0xe200UL,
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RC_ORDER_RULE_CTL = 0x11680UL,
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RC_MISC_CONTROL_1 = 0x11780UL,
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RC_PHY_INT_REG = 0x80000UL,
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RC_PHY_EXT_GEN1 = 0x82400UL,
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RC_PHY_EXT_GEN2 = 0x82480UL,
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};
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/* GPIO */
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enum {
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GPIO_SWPORTA_DR = GPIO_BASE | 0x0UL,
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GPIO_SWPORTA_DDR = GPIO_BASE | 0x200UL,
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};
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/*--------------------------------------------------------------------------*/
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#endif
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