/dts-v1/;
/ {
	#address-cells = <2>;
	#size-cells = <2>;
	compatible = "microchip,polarfire,icicle", "microchip,polarfire";
	model = "microchip,polarfire,icicle-kit";

	chosen {
		bootargs = "root=/dev/mmcblk0p3 rootwait earlycon=sbi console=ttyS0";
		stdout-path = &serial0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <1000000>;

		cpu@0 {
			clock-frequency = <0>;
			compatible = "sifive,rocket0", "riscv";
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <128>;
			i-cache-size = <16384>;
			reg = <0>;
			riscv,isa = "rv64imac";
			status = "disabled";

			cpu0_intc: interrupt-controller {
				#interrupt-cells = <1>;
				compatible = "riscv,cpu-intc";
				interrupt-controller;
			};
		};

		cpu@1 {
			clock-frequency = <0>;
			compatible = "sifive,rocket0", "riscv";
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <32>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <64>;
			i-cache-size = <32768>;
			i-tlb-sets = <1>;
			i-tlb-size = <32>;
			mmu-type = "riscv,sv39";
			reg = <1>;
			riscv,isa = "rv64imafdc";
			tlb-split;
			status = "okay";

			cpu1_intc: interrupt-controller {
				#interrupt-cells = <1>;
				compatible = "riscv,cpu-intc";
				interrupt-controller;
			};
		};

		cpu@2 {
			clock-frequency = <0>;
			compatible = "sifive,rocket0", "riscv";
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <32>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <64>;
			i-cache-size = <32768>;
			i-tlb-sets = <1>;
			i-tlb-size = <32>;
			mmu-type = "riscv,sv39";
			reg = <2>;
			riscv,isa = "rv64imafdc";
			tlb-split;
			status = "okay";

			cpu2_intc: interrupt-controller {
				#interrupt-cells = <1>;
				compatible = "riscv,cpu-intc";
				interrupt-controller;
			};
		};

		cpu@3 {
			clock-frequency = <0>;
			compatible = "sifive,rocket0", "riscv";
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <32>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <64>;
			i-cache-size = <32768>;
			i-tlb-sets = <1>;
			i-tlb-size = <32>;
			mmu-type = "riscv,sv39";
			reg = <3>;
			riscv,isa = "rv64imafdc";
			tlb-split;
			status = "okay";

			cpu3_intc: interrupt-controller {
				#interrupt-cells = <1>;
				compatible = "riscv,cpu-intc";
				interrupt-controller;
			};
		};

		cpu@4 {
			clock-frequency = <0>;
			compatible = "sifive,rocket0", "riscv";
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <32>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <64>;
			i-cache-size = <32768>;
			i-tlb-sets = <1>;
			i-tlb-size = <32>;
			mmu-type = "riscv,sv39";
			reg = <4>;
			riscv,isa = "rv64imafdc";
			tlb-split;
			status = "okay";
			cpu4_intc: interrupt-controller {
				#interrupt-cells = <1>;
				compatible = "riscv,cpu-intc";
				interrupt-controller;
			};
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x40000000>;
		clocks = <&clkcfg 26>;
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		cache-controller@2010000 {
			compatible = "sifive,fu540-c000-ccache", "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-sets = <1024>;
			cache-size = <2097152>;
			cache-unified;
			interrupt-parent = <&plic>;
			interrupts = <1 2 3>;
			reg = <0x0 0x2010000 0x0 0x1000>;
		};

		clint@2000000 {
			compatible = "riscv,clint0";
			reg = <0x0 0x2000000 0x0 0xC000>;
			interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
						&cpu1_intc 3 &cpu1_intc 7
						&cpu2_intc 3 &cpu2_intc 7
						&cpu3_intc 3 &cpu3_intc 7
						&cpu4_intc 3 &cpu4_intc 7>;
		};

		plic: interrupt-controller@c000000 {
			#interrupt-cells = <1>;
			compatible = "sifive,plic-1.0.0", "riscv,plic0";
			reg = <0x0 0xc000000 0x0 0x4000000>;
			riscv,ndev = <53>;
			interrupt-controller;
			interrupts-extended = <&cpu0_intc 11
					&cpu1_intc 11 &cpu1_intc 9
					&cpu2_intc 11 &cpu2_intc 9
					&cpu3_intc 11 &cpu3_intc 9
					&cpu4_intc 11 &cpu4_intc 9>;
		};

		dma@3000000 {
			compatible = "sifive,fu540-c000-pdma";
			reg = <0x0 0x3000000 0x0 0x8000>;
			interrupt-parent = <&plic>;
			interrupts = <23 24 25 26 27 28 29 30>;
			#dma-cells = <1>;
		};

		refclk: refclk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <600000000>;
			clock-output-names = "msspllclk";
		};

		clkcfg: clkcfg@20002000 {
			compatible = "microchip,pfsoc-clkcfg";
			reg = <0x0 0x20002000 0x0 0x1000>;
			reg-names = "mss_sysreg";
			clocks = <&refclk>;
			#clock-cells = <1>;
			clock-output-names = "cpuclk", "axiclk", "ahbclk", "ENVMclk", "MAC0clk", "MAC1clk", "MMCclk", "TIMERclk", "MMUART0clk", "MMUART1clk", "MMUART2clk", "MMUART3clk", "MMUART4clk", "SPI0clk", "SPI1clk", "I2C0clk", "I2C1clk", "CAN0clk", "CAN1clk", "USBclk", "RESERVED", "RTCclk", "QSPIclk", "GPIO0clk", "GPIO1clk", "GPIO2clk", "DDRCclk", "FIC0clk", "FIC1clk", "FIC2clk", "FIC3clk", "ATHENAclk", "CFMclk";
		};

		serial0: serial@20000000 {
			compatible = "ns16550a";
			reg = <0x0 0x20000000 0x0 0x400>;
			reg-io-width = <4>;
			reg-shift = <2>;
			interrupt-parent = <&plic>;
			interrupts = <90>;
			current-speed = <115200>;
			clocks = <&clkcfg 8>;
			status = "okay";
		};

		serial1: serial@20100000 {
			compatible = "ns16550a";
			reg = <0x0 0x20100000 0x0 0x400>;
			reg-io-width = <4>;
			reg-shift = <2>;
			interrupt-parent = <&plic>;
			interrupts = <91>;
			current-speed = <115200>;
			clocks = <&clkcfg 9>;
			status = "okay";
		};

		serial2: serial@20102000 {
			compatible = "ns16550a";
			reg = <0x0 0x20102000 0x0 0x400>;
			reg-io-width = <4>;
			reg-shift = <2>;
			interrupt-parent = <&plic>;
			interrupts = <92>;
			current-speed = <115200>;
			clocks = <&clkcfg 10>;
			status = "okay";
		};

		serial3: serial@20104000 {
			compatible = "ns16550a";
			reg = <0x0 0x20104000 0x0 0x400>;
			reg-io-width = <4>;
			reg-shift = <2>;
			interrupt-parent = <&plic>;
			interrupts = <93>;
			current-speed = <115200>;
			clocks = <&clkcfg 11>;
			status = "okay";
		};

		sdcard: sdhc@20008000 {
			compatible = "cdns,sd4hc";
			reg = <0x0 0x20008000 0x0 0x1000>;
			interrupt-parent = <&plic>;
			interrupts = <88>;
			pinctrl-names = "default";
			clocks = <&clkcfg 6>;
			bus-width = <4>;
			disable-wp;
			no-1-8-v;
			cap-mmc-highspeed;
			cap-sd-highspeed;
			card-detect-delay = <200>;
			sd-uhs-sdr12;
			sd-uhs-sdr25;
			sd-uhs-sdr50;
			sd-uhs-sdr104;
			max-frequency = <200000000>;
			status = "okay";
		};

		emac1: ethernet@20112000 {
			compatible = "cdns,macb";
			reg = <0x0 0x20112000 0x0 0x2000>;
			interrupt-parent = <&plic>;
			interrupts = <70 71 72 73>;
			mac-address = [56 34 12 00 FC 00];
			phy-mode = "sgmii";
			clocks = <&clkcfg 5>, <&clkcfg 2>;
			clock-names = "pclk", "hclk";
			#address-cells = <1>;
			#size-cells = <0>;
			phy1: ethernet-phy@9 {
				reg = <9>;
				ti,fifo-depth = <0x01>;
			};
		};

		uio_axi_lsram@2030000000 {
			compatible = "generic-uio";
			reg = <0x20 0x30000000 0 0x80000000 >;
			status = "okay";
		};
	};
};