From 77bfb67c43c09cae163e6ee6973d0b6ae385e996 Mon Sep 17 00:00:00 2001 From: ardu <1775956414@qq.com> Date: Tue, 27 Jan 2026 16:02:44 +0800 Subject: [PATCH] change dts 1 enable uart1 to uart1_m1 --- arch/arm64/boot/dts/Makefile | 31 +- arch/arm64/boot/dts/actions/Makefile | 5 - .../boot/dts/actions/s700-cubieboard7.dts | 92 - arch/arm64/boot/dts/actions/s700.dtsi | 263 - .../boot/dts/actions/s900-bubblegum-96.dts | 314 - arch/arm64/boot/dts/actions/s900.dtsi | 333 -- arch/arm64/boot/dts/allwinner/Makefile | 37 - arch/arm64/boot/dts/allwinner/axp803.dtsi | 155 - .../allwinner/sun50i-a100-allwinner-perf1.dts | 180 - .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 364 -- .../allwinner/sun50i-a64-amarula-relic.dts | 320 - .../dts/allwinner/sun50i-a64-bananapi-m64.dts | 382 -- .../dts/allwinner/sun50i-a64-cpu-opp.dtsi | 75 - .../dts/allwinner/sun50i-a64-nanopi-a64.dts | 263 - .../sun50i-a64-oceanic-5205-5inmfd.dts | 89 - .../allwinner/sun50i-a64-olinuxino-emmc.dts | 25 - .../dts/allwinner/sun50i-a64-olinuxino.dts | 347 -- .../dts/allwinner/sun50i-a64-orangepi-win.dts | 413 -- .../dts/allwinner/sun50i-a64-pine64-lts.dts | 14 - .../dts/allwinner/sun50i-a64-pine64-plus.dts | 35 - .../boot/dts/allwinner/sun50i-a64-pine64.dts | 320 - .../dts/allwinner/sun50i-a64-pinebook.dts | 416 -- .../allwinner/sun50i-a64-pinephone-1.0.dts | 11 - .../allwinner/sun50i-a64-pinephone-1.1.dts | 30 - .../allwinner/sun50i-a64-pinephone-1.2.dts | 40 - .../dts/allwinner/sun50i-a64-pinephone.dtsi | 429 -- .../boot/dts/allwinner/sun50i-a64-pinetab.dts | 457 -- .../allwinner/sun50i-a64-sopine-baseboard.dts | 205 - .../boot/dts/allwinner/sun50i-a64-sopine.dtsi | 137 - .../boot/dts/allwinner/sun50i-a64-teres-i.dts | 382 -- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1319 ----- .../sun50i-h5-bananapi-m2-plus-v1.2.dts | 12 - .../allwinner/sun50i-h5-bananapi-m2-plus.dts | 11 - .../boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi | 79 - .../sun50i-h5-emlid-neutis-n5-devboard.dts | 71 - .../allwinner/sun50i-h5-emlid-neutis-n5.dtsi | 11 - .../sun50i-h5-libretech-all-h3-cc.dts | 17 - .../sun50i-h5-libretech-all-h3-it.dts | 11 - .../sun50i-h5-libretech-all-h5-cc.dts | 61 - .../allwinner/sun50i-h5-nanopi-neo-plus2.dts | 163 - .../dts/allwinner/sun50i-h5-nanopi-neo2.dts | 120 - .../dts/allwinner/sun50i-h5-orangepi-pc2.dts | 232 - .../allwinner/sun50i-h5-orangepi-prime.dts | 213 - .../sun50i-h5-orangepi-zero-plus.dts | 140 - .../sun50i-h5-orangepi-zero-plus2.dts | 143 - arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 257 - .../dts/allwinner/sun50i-h6-beelink-gs1.dts | 314 - .../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 117 - .../dts/allwinner/sun50i-h6-orangepi-3.dts | 345 -- .../allwinner/sun50i-h6-orangepi-lite2.dts | 74 - .../allwinner/sun50i-h6-orangepi-one-plus.dts | 43 - .../dts/allwinner/sun50i-h6-orangepi.dtsi | 268 - .../allwinner/sun50i-h6-pine-h64-model-b.dts | 21 - .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 333 -- .../dts/allwinner/sun50i-h6-tanix-tx6.dts | 124 - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 1026 ---- arch/arm64/boot/dts/altera/Makefile | 3 - .../boot/dts/altera/socfpga_stratix10.dtsi | 623 -- .../dts/altera/socfpga_stratix10_socdk.dts | 191 - .../altera/socfpga_stratix10_socdk_nand.dts | 224 - arch/arm64/boot/dts/amazon/Makefile | 3 - arch/arm64/boot/dts/amazon/alpine-v2-evp.dts | 53 - arch/arm64/boot/dts/amazon/alpine-v2.dtsi | 236 - arch/arm64/boot/dts/amazon/alpine-v3-evp.dts | 24 - arch/arm64/boot/dts/amazon/alpine-v3.dtsi | 408 -- arch/arm64/boot/dts/amd/Makefile | 4 - .../boot/dts/amd/amd-overdrive-rev-b0.dts | 88 - .../boot/dts/amd/amd-overdrive-rev-b1.dts | 92 - arch/arm64/boot/dts/amd/amd-overdrive.dts | 66 - arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi | 55 - arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 251 - .../boot/dts/amd/amd-seattle-xgbe-b.dtsi | 118 - arch/arm64/boot/dts/amd/husky.dts | 84 - arch/arm64/boot/dts/amlogic/Makefile | 50 - .../arm64/boot/dts/amlogic/meson-a1-ad401.dts | 30 - arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 161 - .../arm64/boot/dts/amlogic/meson-axg-s400.dts | 592 -- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 1826 ------ .../boot/dts/amlogic/meson-g12-common.dtsi | 2431 -------- arch/arm64/boot/dts/amlogic/meson-g12.dtsi | 385 -- .../boot/dts/amlogic/meson-g12a-sei510.dts | 558 -- .../boot/dts/amlogic/meson-g12a-u200.dts | 308 - .../boot/dts/amlogic/meson-g12a-x96-max.dts | 481 -- arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 135 - .../amlogic/meson-g12b-a311d-khadas-vim3.dts | 41 - .../boot/dts/amlogic/meson-g12b-a311d.dtsi | 109 - .../dts/amlogic/meson-g12b-gtking-pro.dts | 125 - .../boot/dts/amlogic/meson-g12b-gtking.dts | 145 - .../dts/amlogic/meson-g12b-khadas-vim3.dtsi | 107 - .../dts/amlogic/meson-g12b-odroid-n2-plus.dts | 31 - .../boot/dts/amlogic/meson-g12b-odroid-n2.dts | 15 - .../dts/amlogic/meson-g12b-odroid-n2.dtsi | 625 -- .../amlogic/meson-g12b-s922x-khadas-vim3.dts | 41 - .../boot/dts/amlogic/meson-g12b-s922x.dtsi | 99 - .../boot/dts/amlogic/meson-g12b-ugoos-am6.dts | 184 - .../boot/dts/amlogic/meson-g12b-w400.dtsi | 425 -- arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 141 - .../dts/amlogic/meson-gx-libretech-pc.dtsi | 447 -- .../boot/dts/amlogic/meson-gx-mali450.dtsi | 61 - .../boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 324 -- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 667 --- .../boot/dts/amlogic/meson-gxbb-kii-pro.dts | 82 - .../boot/dts/amlogic/meson-gxbb-nanopi-k2.dts | 375 -- .../dts/amlogic/meson-gxbb-nexbox-a95x.dts | 291 - .../boot/dts/amlogic/meson-gxbb-odroidc2.dts | 378 -- .../boot/dts/amlogic/meson-gxbb-p200.dts | 100 - .../boot/dts/amlogic/meson-gxbb-p201.dts | 26 - .../boot/dts/amlogic/meson-gxbb-p20x.dtsi | 250 - .../dts/amlogic/meson-gxbb-vega-s95-meta.dts | 18 - .../dts/amlogic/meson-gxbb-vega-s95-pro.dts | 18 - .../dts/amlogic/meson-gxbb-vega-s95-telos.dts | 18 - .../boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 276 - .../boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 18 - .../dts/amlogic/meson-gxbb-wetek-play2.dts | 60 - .../boot/dts/amlogic/meson-gxbb-wetek.dtsi | 289 - arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 856 --- .../boot/dts/amlogic/meson-gxl-mali.dtsi | 17 - .../amlogic/meson-gxl-s805x-libretech-ac.dts | 319 - .../boot/dts/amlogic/meson-gxl-s805x-p241.dts | 222 - .../boot/dts/amlogic/meson-gxl-s805x.dtsi | 23 - .../amlogic/meson-gxl-s905d-libretech-pc.dts | 16 - .../boot/dts/amlogic/meson-gxl-s905d-p230.dts | 111 - .../boot/dts/amlogic/meson-gxl-s905d-p231.dts | 28 - .../amlogic/meson-gxl-s905d-phicomm-n1.dts | 35 - .../dts/amlogic/meson-gxl-s905d-sml5442tw.dts | 80 - .../boot/dts/amlogic/meson-gxl-s905d.dtsi | 12 - .../boot/dts/amlogic/meson-gxl-s905w-p281.dts | 26 - .../dts/amlogic/meson-gxl-s905w-tx3-mini.dts | 30 - .../meson-gxl-s905x-hwacom-amazetv.dts | 164 - .../amlogic/meson-gxl-s905x-khadas-vim.dts | 213 - .../meson-gxl-s905x-libretech-cc-v2.dts | 318 - .../amlogic/meson-gxl-s905x-libretech-cc.dts | 356 -- .../amlogic/meson-gxl-s905x-nexbox-a95x.dts | 224 - .../boot/dts/amlogic/meson-gxl-s905x-p212.dts | 66 - .../dts/amlogic/meson-gxl-s905x-p212.dtsi | 208 - .../boot/dts/amlogic/meson-gxl-s905x.dtsi | 18 - arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 925 --- .../dts/amlogic/meson-gxm-khadas-vim2.dts | 386 -- .../boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 185 - .../arm64/boot/dts/amlogic/meson-gxm-q200.dts | 81 - .../arm64/boot/dts/amlogic/meson-gxm-q201.dts | 28 - .../boot/dts/amlogic/meson-gxm-rbox-pro.dts | 205 - .../amlogic/meson-gxm-s912-libretech-pc.dts | 62 - .../boot/dts/amlogic/meson-gxm-vega-s96.dts | 45 - .../dts/amlogic/meson-gxm-wetek-core2.dts | 87 - arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 196 - .../boot/dts/amlogic/meson-khadas-vim3.dtsi | 497 -- .../dts/amlogic/meson-sm1-khadas-vim3l.dts | 100 - .../boot/dts/amlogic/meson-sm1-odroid-c4.dts | 490 -- .../boot/dts/amlogic/meson-sm1-sei610.dts | 608 -- arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 508 -- arch/arm64/boot/dts/apm/Makefile | 3 - arch/arm64/boot/dts/apm/apm-merlin.dts | 87 - arch/arm64/boot/dts/apm/apm-mustang.dts | 90 - arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 818 --- arch/arm64/boot/dts/apm/apm-storm.dtsi | 1098 ---- arch/arm64/boot/dts/arm/Makefile | 8 - .../boot/dts/arm/foundation-v8-gicv2.dtsi | 19 - .../boot/dts/arm/foundation-v8-gicv3-psci.dts | 9 - .../boot/dts/arm/foundation-v8-gicv3.dts | 10 - .../boot/dts/arm/foundation-v8-gicv3.dtsi | 29 - .../arm64/boot/dts/arm/foundation-v8-psci.dts | 9 - .../boot/dts/arm/foundation-v8-psci.dtsi | 28 - .../dts/arm/foundation-v8-spin-table.dtsi | 25 - arch/arm64/boot/dts/arm/foundation-v8.dts | 10 - arch/arm64/boot/dts/arm/foundation-v8.dtsi | 231 - arch/arm64/boot/dts/arm/fvp-base-revc.dts | 270 - arch/arm64/boot/dts/arm/juno-base.dtsi | 840 --- arch/arm64/boot/dts/arm/juno-clocks.dtsi | 45 - arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi | 85 - arch/arm64/boot/dts/arm/juno-motherboard.dtsi | 295 - arch/arm64/boot/dts/arm/juno-r1.dts | 311 - arch/arm64/boot/dts/arm/juno-r2.dts | 317 - arch/arm64/boot/dts/arm/juno.dts | 297 - arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 193 - .../boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi | 27 - .../boot/dts/arm/rtsm_ve-motherboard.dtsi | 250 - .../boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 205 - arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi | 1 - arch/arm64/boot/dts/bitmain/Makefile | 3 - .../boot/dts/bitmain/bm1880-sophon-edge.dts | 184 - arch/arm64/boot/dts/bitmain/bm1880.dtsi | 226 - arch/arm64/boot/dts/broadcom/Makefile | 9 - .../boot/dts/broadcom/bcm2711-rpi-4-b.dts | 2 - .../dts/broadcom/bcm2837-rpi-3-a-plus.dts | 2 - .../dts/broadcom/bcm2837-rpi-3-b-plus.dts | 2 - .../boot/dts/broadcom/bcm2837-rpi-3-b.dts | 2 - .../boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts | 2 - .../boot/dts/broadcom/northstar2/Makefile | 3 - .../dts/broadcom/northstar2/ns2-clock.dtsi | 105 - .../boot/dts/broadcom/northstar2/ns2-svk.dts | 236 - .../boot/dts/broadcom/northstar2/ns2-xmc.dts | 191 - .../boot/dts/broadcom/northstar2/ns2.dtsi | 765 --- .../arm64/boot/dts/broadcom/stingray/Makefile | 5 - .../dts/broadcom/stingray/bcm958742-base.dtsi | 176 - .../boot/dts/broadcom/stingray/bcm958742k.dts | 86 - .../boot/dts/broadcom/stingray/bcm958742t.dts | 48 - .../dts/broadcom/stingray/bcm958802a802x.dts | 26 - .../stingray/stingray-board-base.dtsi | 51 - .../dts/broadcom/stingray/stingray-clock.dtsi | 182 - .../dts/broadcom/stingray/stingray-fs4.dtsi | 118 - .../dts/broadcom/stingray/stingray-pcie.dtsi | 54 - .../broadcom/stingray/stingray-pinctrl.dtsi | 346 -- .../dts/broadcom/stingray/stingray-sata.dtsi | 278 - .../dts/broadcom/stingray/stingray-usb.dtsi | 77 - .../boot/dts/broadcom/stingray/stingray.dtsi | 722 --- arch/arm64/boot/dts/cavium/Makefile | 3 - arch/arm64/boot/dts/cavium/thunder-88xx.dts | 67 - arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 415 -- arch/arm64/boot/dts/cavium/thunder2-99xx.dts | 30 - arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 145 - arch/arm64/boot/dts/exynos/Makefile | 5 - .../arm64/boot/dts/exynos/exynos5433-bus.dtsi | 194 - .../boot/dts/exynos/exynos5433-pinctrl.dtsi | 790 --- .../dts/exynos/exynos5433-tm2-common.dtsi | 1333 ----- arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 93 - .../arm64/boot/dts/exynos/exynos5433-tm2e.dts | 80 - .../arm64/boot/dts/exynos/exynos5433-tmu.dtsi | 305 - arch/arm64/boot/dts/exynos/exynos5433.dtsi | 1850 ------ .../boot/dts/exynos/exynos7-espresso.dts | 418 -- .../boot/dts/exynos/exynos7-pinctrl.dtsi | 702 --- .../boot/dts/exynos/exynos7-trip-points.dtsi | 50 - arch/arm64/boot/dts/exynos/exynos7.dtsi | 685 --- arch/arm64/boot/dts/freescale/Makefile | 54 - .../boot/dts/freescale/fsl-ls1012a-frdm.dts | 98 - .../boot/dts/freescale/fsl-ls1012a-frwy.dts | 40 - .../boot/dts/freescale/fsl-ls1012a-oxalis.dts | 100 - .../boot/dts/freescale/fsl-ls1012a-qds.dts | 152 - .../boot/dts/freescale/fsl-ls1012a-rdb.dts | 55 - .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 540 -- .../fsl-ls1028a-kontron-kbox-a-230-ls.dts | 109 - .../fsl-ls1028a-kontron-sl28-var2.dts | 74 - .../fsl-ls1028a-kontron-sl28-var3-ads2.dts | 126 - .../fsl-ls1028a-kontron-sl28-var4.dts | 50 - .../freescale/fsl-ls1028a-kontron-sl28.dts | 317 - .../boot/dts/freescale/fsl-ls1028a-qds.dts | 330 -- .../boot/dts/freescale/fsl-ls1028a-rdb.dts | 269 - .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1062 ---- .../boot/dts/freescale/fsl-ls1043-post.dtsi | 46 - .../boot/dts/freescale/fsl-ls1043a-qds.dts | 155 - .../boot/dts/freescale/fsl-ls1043a-rdb.dts | 219 - .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 942 --- .../boot/dts/freescale/fsl-ls1046-post.dtsi | 48 - .../boot/dts/freescale/fsl-ls1046a-frwy.dts | 163 - .../boot/dts/freescale/fsl-ls1046a-qds.dts | 179 - .../boot/dts/freescale/fsl-ls1046a-rdb.dts | 182 - .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 902 --- .../boot/dts/freescale/fsl-ls1088a-qds.dts | 172 - .../boot/dts/freescale/fsl-ls1088a-rdb.dts | 125 - .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 825 --- .../boot/dts/freescale/fsl-ls2080a-qds.dts | 25 - .../boot/dts/freescale/fsl-ls2080a-rdb.dts | 25 - .../boot/dts/freescale/fsl-ls2080a-simu.dts | 29 - .../arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 151 - .../boot/dts/freescale/fsl-ls2088a-qds.dts | 24 - .../boot/dts/freescale/fsl-ls2088a-rdb.dts | 24 - .../arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 155 - .../boot/dts/freescale/fsl-ls208xa-qds.dtsi | 166 - .../boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 136 - .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 925 --- .../boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 164 - .../dts/freescale/fsl-lx2160a-clearfog-cx.dts | 15 - .../freescale/fsl-lx2160a-clearfog-itx.dtsi | 57 - .../dts/freescale/fsl-lx2160a-honeycomb.dts | 15 - .../boot/dts/freescale/fsl-lx2160a-qds.dts | 179 - .../boot/dts/freescale/fsl-lx2160a-rdb.dts | 189 - .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 1425 ----- .../freescale/imx8mm-beacon-baseboard.dtsi | 285 - .../boot/dts/freescale/imx8mm-beacon-kit.dts | 19 - .../boot/dts/freescale/imx8mm-beacon-som.dtsi | 412 -- .../boot/dts/freescale/imx8mm-ddr4-evk.dts | 57 - arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 128 - arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 475 -- .../arm64/boot/dts/freescale/imx8mm-pinfunc.h | 645 -- .../dts/freescale/imx8mm-var-som-symphony.dts | 255 - .../boot/dts/freescale/imx8mm-var-som.dtsi | 558 -- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 983 ---- .../boot/dts/freescale/imx8mn-ddr4-evk.dts | 160 - arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 128 - arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 346 -- .../arm64/boot/dts/freescale/imx8mn-pinfunc.h | 646 --- .../dts/freescale/imx8mn-var-som-symphony.dts | 240 - .../boot/dts/freescale/imx8mn-var-som.dtsi | 548 -- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 858 --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 270 - .../arm64/boot/dts/freescale/imx8mp-pinfunc.h | 799 --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 756 --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 575 -- .../freescale/imx8mq-hummingboard-pulse.dts | 264 - .../dts/freescale/imx8mq-librem5-devkit.dts | 1000 ---- .../boot/dts/freescale/imx8mq-librem5-r2.dts | 29 - .../boot/dts/freescale/imx8mq-librem5-r3.dts | 31 - .../boot/dts/freescale/imx8mq-librem5.dtsi | 1106 ---- .../boot/dts/freescale/imx8mq-nitrogen.dts | 407 -- .../boot/dts/freescale/imx8mq-phanbell.dts | 481 -- .../boot/dts/freescale/imx8mq-pico-pi.dts | 418 -- .../arm64/boot/dts/freescale/imx8mq-pinfunc.h | 623 -- .../boot/dts/freescale/imx8mq-sr-som.dtsi | 317 - .../boot/dts/freescale/imx8mq-thor96.dts | 581 -- .../dts/freescale/imx8mq-zii-ultra-rmb3.dts | 95 - .../dts/freescale/imx8mq-zii-ultra-zest.dts | 24 - .../boot/dts/freescale/imx8mq-zii-ultra.dtsi | 771 --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1339 ----- .../boot/dts/freescale/imx8qxp-ai_ml.dts | 253 - .../dts/freescale/imx8qxp-colibri-eval-v3.dts | 15 - .../freescale/imx8qxp-colibri-eval-v3.dtsi | 62 - .../boot/dts/freescale/imx8qxp-colibri.dtsi | 598 -- arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 272 - arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 632 -- .../dts/freescale/qoriq-bman-portals.dtsi | 77 - .../dts/freescale/qoriq-fman3-0-10g-0.dtsi | 42 - .../dts/freescale/qoriq-fman3-0-10g-1.dtsi | 42 - .../dts/freescale/qoriq-fman3-0-1g-0.dtsi | 41 - .../dts/freescale/qoriq-fman3-0-1g-1.dtsi | 41 - .../dts/freescale/qoriq-fman3-0-1g-2.dtsi | 41 - .../dts/freescale/qoriq-fman3-0-1g-3.dtsi | 41 - .../dts/freescale/qoriq-fman3-0-1g-4.dtsi | 41 - .../dts/freescale/qoriq-fman3-0-1g-5.dtsi | 41 - .../boot/dts/freescale/qoriq-fman3-0.dtsi | 86 - .../dts/freescale/qoriq-qman-portals.dtsi | 87 - arch/arm64/boot/dts/freescale/s32v234-evb.dts | 25 - arch/arm64/boot/dts/freescale/s32v234.dtsi | 139 - arch/arm64/boot/dts/hisilicon/Makefile | 8 - .../boot/dts/hisilicon/hi3660-coresight.dtsi | 456 -- .../boot/dts/hisilicon/hi3660-hikey960.dts | 697 --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 1194 ---- .../boot/dts/hisilicon/hi3670-hikey970.dts | 448 -- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 713 --- .../boot/dts/hisilicon/hi3798cv200-poplar.dts | 206 - .../arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 620 -- .../boot/dts/hisilicon/hi6220-coresight.dtsi | 482 -- .../arm64/boot/dts/hisilicon/hi6220-hikey.dts | 545 -- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 1066 ---- .../boot/dts/hisilicon/hikey-pinctrl.dtsi | 706 --- .../boot/dts/hisilicon/hikey960-pinctrl.dtsi | 1060 ---- .../boot/dts/hisilicon/hikey970-pinctrl.dtsi | 359 -- arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 84 - arch/arm64/boot/dts/hisilicon/hip05.dtsi | 365 -- arch/arm64/boot/dts/hisilicon/hip06-d03.dts | 58 - arch/arm64/boot/dts/hisilicon/hip06.dtsi | 754 --- arch/arm64/boot/dts/hisilicon/hip07-d05.dts | 90 - arch/arm64/boot/dts/hisilicon/hip07.dtsi | 1887 ------ .../boot/dts/hisilicon/poplar-pinctrl.dtsi | 98 - arch/arm64/boot/dts/intel/Makefile | 4 - arch/arm64/boot/dts/intel/keembay-evm.dts | 37 - arch/arm64/boot/dts/intel/keembay-soc.dtsi | 123 - arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 631 -- .../boot/dts/intel/socfpga_agilex_socdk.dts | 142 - .../dts/intel/socfpga_agilex_socdk_nand.dts | 135 - arch/arm64/boot/dts/lg/Makefile | 3 - arch/arm64/boot/dts/lg/lg1312-ref.dts | 37 - arch/arm64/boot/dts/lg/lg1312.dtsi | 352 -- arch/arm64/boot/dts/lg/lg1313-ref.dts | 37 - arch/arm64/boot/dts/lg/lg1313.dtsi | 352 -- arch/arm64/boot/dts/marvell/Makefile | 18 - arch/arm64/boot/dts/marvell/armada-371x.dtsi | 17 - .../arm64/boot/dts/marvell/armada-3720-db.dts | 220 - .../marvell/armada-3720-espressobin-emmc.dts | 44 - .../armada-3720-espressobin-v7-emmc.dts | 67 - .../marvell/armada-3720-espressobin-v7.dts | 44 - .../dts/marvell/armada-3720-espressobin.dts | 20 - .../dts/marvell/armada-3720-espressobin.dtsi | 185 - .../dts/marvell/armada-3720-turris-mox.dts | 869 --- .../boot/dts/marvell/armada-3720-uDPU.dts | 188 - arch/arm64/boot/dts/marvell/armada-372x.dtsi | 27 - arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 520 -- arch/arm64/boot/dts/marvell/armada-7020.dtsi | 16 - .../arm64/boot/dts/marvell/armada-7040-db.dts | 302 - arch/arm64/boot/dts/marvell/armada-7040.dtsi | 40 - arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 64 - arch/arm64/boot/dts/marvell/armada-8020.dtsi | 26 - .../marvell/armada-8040-clearfog-gt-8k.dts | 483 -- .../arm64/boot/dts/marvell/armada-8040-db.dts | 358 -- .../marvell/armada-8040-mcbin-singleshot.dts | 29 - .../boot/dts/marvell/armada-8040-mcbin.dts | 45 - .../boot/dts/marvell/armada-8040-mcbin.dtsi | 372 -- arch/arm64/boot/dts/marvell/armada-8040.dtsi | 61 - .../arm64/boot/dts/marvell/armada-8080-db.dts | 28 - arch/arm64/boot/dts/marvell/armada-8080.dtsi | 14 - arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 108 - .../boot/dts/marvell/armada-ap806-dual.dtsi | 61 - .../boot/dts/marvell/armada-ap806-quad.dtsi | 93 - arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 30 - .../boot/dts/marvell/armada-ap807-quad.dtsi | 93 - arch/arm64/boot/dts/marvell/armada-ap807.dtsi | 29 - arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 461 -- .../marvell/armada-ap810-ap0-octa-core.dtsi | 65 - .../boot/dts/marvell/armada-ap810-ap0.dtsi | 124 - .../arm64/boot/dts/marvell/armada-common.dtsi | 11 - arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 12 - arch/arm64/boot/dts/marvell/armada-cp115.dtsi | 12 - arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 568 -- arch/arm64/boot/dts/marvell/cn9130-db.dts | 403 -- arch/arm64/boot/dts/marvell/cn9130.dtsi | 52 - arch/arm64/boot/dts/marvell/cn9131-db.dts | 202 - arch/arm64/boot/dts/marvell/cn9132-db.dts | 221 - arch/arm64/boot/dts/mediatek/Makefile | 15 - arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 235 - arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h | 1123 ---- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 1127 ---- arch/arm64/boot/dts/mediatek/mt6358.dtsi | 360 -- arch/arm64/boot/dts/mediatek/mt6380.dtsi | 86 - arch/arm64/boot/dts/mediatek/mt6755-evb.dts | 30 - arch/arm64/boot/dts/mediatek/mt6755.dtsi | 145 - arch/arm64/boot/dts/mediatek/mt6795-evb.dts | 33 - arch/arm64/boot/dts/mediatek/mt6795.dtsi | 175 - arch/arm64/boot/dts/mediatek/mt6797-evb.dts | 30 - .../boot/dts/mediatek/mt6797-x20-dev.dts | 84 - arch/arm64/boot/dts/mediatek/mt6797.dtsi | 483 -- .../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 599 -- arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 563 -- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 950 --- .../dts/mediatek/mt8173-elm-hana-rev7.dts | 27 - .../boot/dts/mediatek/mt8173-elm-hana.dts | 14 - .../boot/dts/mediatek/mt8173-elm-hana.dtsi | 70 - arch/arm64/boot/dts/mediatek/mt8173-elm.dts | 14 - arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 1174 ---- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 534 -- arch/arm64/boot/dts/mediatek/mt8173-pinfunc.h | 674 --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 1468 ----- arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 394 -- .../mediatek/mt8183-kukui-krane-sku176.dts | 18 - .../boot/dts/mediatek/mt8183-kukui-krane.dtsi | 343 -- .../arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 818 --- arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h | 1120 ---- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 816 --- arch/arm64/boot/dts/mediatek/mt8516-pinfunc.h | 663 --- .../boot/dts/mediatek/mt8516-pumpkin.dts | 20 - arch/arm64/boot/dts/mediatek/mt8516.dtsi | 474 -- .../boot/dts/mediatek/pumpkin-common.dtsi | 255 - arch/arm64/boot/dts/microchip/Makefile | 4 - arch/arm64/boot/dts/microchip/sparx5.dtsi | 294 - .../arm64/boot/dts/microchip/sparx5_nand.dtsi | 31 - .../boot/dts/microchip/sparx5_pcb125.dts | 74 - .../boot/dts/microchip/sparx5_pcb134.dts | 18 - .../dts/microchip/sparx5_pcb134_board.dtsi | 284 - .../boot/dts/microchip/sparx5_pcb134_emmc.dts | 40 - .../boot/dts/microchip/sparx5_pcb135.dts | 18 - .../dts/microchip/sparx5_pcb135_board.dtsi | 124 - .../boot/dts/microchip/sparx5_pcb135_emmc.dts | 40 - .../boot/dts/microchip/sparx5_pcb_common.dtsi | 19 - arch/arm64/boot/dts/nvidia/Makefile | 12 - .../arm64/boot/dts/nvidia/tegra132-norrin.dts | 1197 ---- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 1241 ---- .../boot/dts/nvidia/tegra186-p2771-0000.dts | 368 -- .../arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 425 -- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1744 ------ .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 357 -- .../boot/dts/nvidia/tegra194-p2972-0000.dts | 349 -- .../nvidia/tegra194-p3509-0000+p3668-0000.dts | 345 -- .../boot/dts/nvidia/tegra194-p3668-0000.dtsi | 306 - arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2382 -------- .../arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 350 -- .../boot/dts/nvidia/tegra210-p2371-0000.dts | 10 - .../boot/dts/nvidia/tegra210-p2371-2180.dts | 130 - .../arm64/boot/dts/nvidia/tegra210-p2530.dtsi | 71 - arch/arm64/boot/dts/nvidia/tegra210-p2571.dts | 1303 ----- .../arm64/boot/dts/nvidia/tegra210-p2595.dtsi | 1273 ---- .../arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 1715 ------ .../dts/nvidia/tegra210-p2894-0050-a08.dts | 9 - .../arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 1832 ------ .../boot/dts/nvidia/tegra210-p3450-0000.dts | 873 --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 1879 ------ arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1856 ------ .../boot/dts/nvidia/tegra234-sim-vdk.dts | 40 - arch/arm64/boot/dts/nvidia/tegra234.dtsi | 189 - arch/arm64/boot/dts/qcom/Makefile | 45 - arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 13 - arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 831 --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 13 - arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 1102 ---- arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts | 385 -- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 64 - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 533 -- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 112 - arch/arm64/boot/dts/qcom/ipq8074.dtsi | 693 --- .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 224 - arch/arm64/boot/dts/qcom/msm8916-mtp.dts | 14 - arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi | 21 - arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 562 -- arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi | 79 - .../qcom/msm8916-samsung-a2015-common.dtsi | 349 -- .../boot/dts/qcom/msm8916-samsung-a3u-eur.dts | 62 - .../boot/dts/qcom/msm8916-samsung-a5u-eur.dts | 53 - arch/arm64/boot/dts/qcom/msm8916.dtsi | 1921 ------ .../dts/qcom/msm8992-bullhead-rev-101.dts | 279 - .../dts/qcom/msm8992-msft-lumia-talkman.dts | 39 - .../boot/dts/qcom/msm8992-xiaomi-libra.dts | 364 -- arch/arm64/boot/dts/qcom/msm8992.dtsi | 619 -- .../boot/dts/qcom/msm8994-angler-rev-101.dts | 38 - .../msm8994-sony-xperia-kitakami-sumire.dts | 13 - .../qcom/msm8994-sony-xperia-kitakami.dtsi | 240 - arch/arm64/boot/dts/qcom/msm8994.dtsi | 715 --- arch/arm64/boot/dts/qcom/msm8996-mtp.dts | 13 - arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi | 22 - arch/arm64/boot/dts/qcom/msm8996-pins.dtsi | 653 --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2454 -------- .../dts/qcom/msm8998-asus-novago-tp370ql.dts | 47 - .../boot/dts/qcom/msm8998-clamshell.dtsi | 343 -- .../boot/dts/qcom/msm8998-hp-envy-x2.dts | 30 - .../boot/dts/qcom/msm8998-lenovo-miix-630.dts | 35 - arch/arm64/boot/dts/qcom/msm8998-mtp.dts | 13 - arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 411 -- arch/arm64/boot/dts/qcom/msm8998-pins.dtsi | 108 - arch/arm64/boot/dts/qcom/msm8998.dtsi | 2118 ------- arch/arm64/boot/dts/qcom/pm6150.dtsi | 72 - arch/arm64/boot/dts/qcom/pm6150l.dtsi | 31 - arch/arm64/boot/dts/qcom/pm660.dtsi | 50 - arch/arm64/boot/dts/qcom/pm660l.dtsi | 36 - arch/arm64/boot/dts/qcom/pm8004.dtsi | 26 - arch/arm64/boot/dts/qcom/pm8005.dtsi | 32 - arch/arm64/boot/dts/qcom/pm8009.dtsi | 37 - arch/arm64/boot/dts/qcom/pm8150.dtsi | 125 - arch/arm64/boot/dts/qcom/pm8150b.dtsi | 114 - arch/arm64/boot/dts/qcom/pm8150l.dtsi | 108 - arch/arm64/boot/dts/qcom/pm8916.dtsi | 168 - arch/arm64/boot/dts/qcom/pm8994.dtsi | 93 - arch/arm64/boot/dts/qcom/pm8998.dtsi | 112 - arch/arm64/boot/dts/qcom/pmi8994.dtsi | 36 - arch/arm64/boot/dts/qcom/pmi8998.dtsi | 41 - arch/arm64/boot/dts/qcom/pms405.dtsi | 149 - arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts | 12 - arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts | 94 - arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 395 -- arch/arm64/boot/dts/qcom/qcs404.dtsi | 1642 ------ arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 693 --- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 601 -- .../boot/dts/qcom/sc7180-trogdor-lazor-r0.dts | 24 - .../dts/qcom/sc7180-trogdor-lazor-r1-kb.dts | 17 - .../dts/qcom/sc7180-trogdor-lazor-r1-lte.dts | 18 - .../boot/dts/qcom/sc7180-trogdor-lazor-r1.dts | 15 - .../boot/dts/qcom/sc7180-trogdor-lazor.dtsi | 192 - .../boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi | 15 - .../boot/dts/qcom/sc7180-trogdor-r1-lte.dts | 14 - .../arm64/boot/dts/qcom/sc7180-trogdor-r1.dts | 191 - arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 1404 ----- arch/arm64/boot/dts/qcom/sc7180.dtsi | 4184 ------------- .../qcom/sdm630-sony-xperia-ganges-kirin.dts | 13 - .../dts/qcom/sdm630-sony-xperia-ganges.dtsi | 40 - .../sdm630-sony-xperia-nile-discovery.dts | 13 - .../qcom/sdm630-sony-xperia-nile-pioneer.dts | 13 - .../qcom/sdm630-sony-xperia-nile-voyager.dts | 20 - .../dts/qcom/sdm630-sony-xperia-nile.dtsi | 136 - arch/arm64/boot/dts/qcom/sdm630.dtsi | 1243 ---- .../sdm636-sony-xperia-ganges-mermaid.dts | 20 - .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 46 - arch/arm64/boot/dts/qcom/sdm660.dtsi | 372 -- arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts | 238 - arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts | 238 - arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts | 174 - arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 1316 ----- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 1195 ---- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 636 -- .../boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 380 -- arch/arm64/boot/dts/qcom/sdm845.dtsi | 5162 ----------------- .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 620 -- arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 431 -- arch/arm64/boot/dts/qcom/sm8150.dtsi | 1998 ------- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 424 -- arch/arm64/boot/dts/qcom/sm8250.dtsi | 3120 ---------- arch/arm64/boot/dts/realtek/Makefile | 15 - .../arm64/boot/dts/realtek/rtd1293-ds418j.dts | 30 - arch/arm64/boot/dts/realtek/rtd1293.dtsi | 55 - .../boot/dts/realtek/rtd1295-mele-v9.dts | 31 - .../boot/dts/realtek/rtd1295-probox2-ava.dts | 31 - .../boot/dts/realtek/rtd1295-xnano-x5.dts | 30 - .../boot/dts/realtek/rtd1295-zidoo-x9s.dts | 35 - arch/arm64/boot/dts/realtek/rtd1295.dtsi | 65 - arch/arm64/boot/dts/realtek/rtd1296-ds418.dts | 30 - arch/arm64/boot/dts/realtek/rtd1296.dtsi | 65 - arch/arm64/boot/dts/realtek/rtd129x.dtsi | 195 - .../arm64/boot/dts/realtek/rtd1395-bpi-m4.dts | 30 - .../boot/dts/realtek/rtd1395-lionskin.dts | 36 - arch/arm64/boot/dts/realtek/rtd1395.dtsi | 65 - arch/arm64/boot/dts/realtek/rtd139x.dtsi | 193 - .../boot/dts/realtek/rtd1619-mjolnir.dts | 44 - arch/arm64/boot/dts/realtek/rtd1619.dtsi | 12 - arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 229 - arch/arm64/boot/dts/renesas/Makefile | 58 - .../aistarvision-mipi-adapter-2.1.dtsi | 94 - .../dts/renesas/beacon-renesom-baseboard.dtsi | 758 --- .../boot/dts/renesas/beacon-renesom-som.dtsi | 316 - arch/arm64/boot/dts/renesas/cat875.dtsi | 65 - .../arm64/boot/dts/renesas/hihope-common.dtsi | 380 -- arch/arm64/boot/dts/renesas/hihope-rev2.dtsi | 86 - arch/arm64/boot/dts/renesas/hihope-rev4.dtsi | 124 - .../boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi | 52 - .../boot/dts/renesas/hihope-rzg2-ex.dtsi | 93 - .../dts/renesas/r8a774a1-beacon-rzg2m-kit.dts | 32 - .../r8a774a1-hihope-rzg2m-ex-idk-1110wr.dts | 15 - .../dts/renesas/r8a774a1-hihope-rzg2m-ex.dts | 21 - ...a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dts | 15 - .../renesas/r8a774a1-hihope-rzg2m-rev2-ex.dts | 20 - .../renesas/r8a774a1-hihope-rzg2m-rev2.dts | 37 - .../dts/renesas/r8a774a1-hihope-rzg2m.dts | 37 - arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 2845 --------- .../r8a774b1-hihope-rzg2n-ex-idk-1110wr.dts | 15 - .../dts/renesas/r8a774b1-hihope-rzg2n-ex.dts | 21 - ...a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dts | 15 - .../renesas/r8a774b1-hihope-rzg2n-rev2-ex.dts | 15 - .../renesas/r8a774b1-hihope-rzg2n-rev2.dts | 41 - .../dts/renesas/r8a774b1-hihope-rzg2n.dts | 41 - arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 2685 --------- .../boot/dts/renesas/r8a774c0-cat874.dts | 422 -- .../dts/renesas/r8a774c0-ek874-idk-2121wr.dts | 116 - .../dts/renesas/r8a774c0-ek874-mipi-2.1.dts | 72 - .../arm64/boot/dts/renesas/r8a774c0-ek874.dts | 14 - arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 1979 ------- .../r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts | 15 - .../dts/renesas/r8a774e1-hihope-rzg2h-ex.dts | 20 - .../dts/renesas/r8a774e1-hihope-rzg2h.dts | 41 - arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 2967 ---------- .../boot/dts/renesas/r8a77950-salvator-x.dts | 157 - .../boot/dts/renesas/r8a77950-ulcb-kf.dts | 16 - arch/arm64/boot/dts/renesas/r8a77950-ulcb.dts | 37 - arch/arm64/boot/dts/renesas/r8a77950.dtsi | 319 - .../boot/dts/renesas/r8a77951-salvator-x.dts | 157 - .../boot/dts/renesas/r8a77951-salvator-xs.dts | 206 - .../boot/dts/renesas/r8a77951-ulcb-kf.dts | 16 - arch/arm64/boot/dts/renesas/r8a77951-ulcb.dts | 50 - arch/arm64/boot/dts/renesas/r8a77951.dtsi | 3340 ----------- .../boot/dts/renesas/r8a77960-salvator-x.dts | 83 - .../boot/dts/renesas/r8a77960-salvator-xs.dts | 83 - .../boot/dts/renesas/r8a77960-ulcb-kf.dts | 16 - arch/arm64/boot/dts/renesas/r8a77960-ulcb.dts | 38 - arch/arm64/boot/dts/renesas/r8a77960.dtsi | 2983 ---------- .../boot/dts/renesas/r8a77961-salvator-xs.dts | 88 - arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts | 32 - arch/arm64/boot/dts/renesas/r8a77961.dtsi | 2234 ------- .../boot/dts/renesas/r8a77965-salvator-x.dts | 77 - .../boot/dts/renesas/r8a77965-salvator-xs.dts | 91 - .../boot/dts/renesas/r8a77965-ulcb-kf.dts | 16 - arch/arm64/boot/dts/renesas/r8a77965-ulcb.dts | 33 - arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2670 --------- .../arm64/boot/dts/renesas/r8a77970-eagle.dts | 273 - .../arm64/boot/dts/renesas/r8a77970-v3msk.dts | 293 - arch/arm64/boot/dts/renesas/r8a77970.dtsi | 1224 ---- .../boot/dts/renesas/r8a77980-condor.dts | 357 -- .../arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 282 - arch/arm64/boot/dts/renesas/r8a77980.dtsi | 1622 ------ .../arm64/boot/dts/renesas/r8a77990-ebisu.dts | 753 --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 2066 ------- .../arm64/boot/dts/renesas/r8a77995-draak.dts | 520 -- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 1153 ---- .../boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 46 - .../boot/dts/renesas/r8a779a0-falcon.dts | 22 - arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 129 - .../rzg2-advantech-idk-1110wr-panel.dtsi | 41 - .../boot/dts/renesas/salvator-common.dtsi | 935 --- arch/arm64/boot/dts/renesas/salvator-x.dtsi | 29 - arch/arm64/boot/dts/renesas/salvator-xs.dtsi | 29 - arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 383 -- arch/arm64/boot/dts/renesas/ulcb.dtsi | 487 -- .../boot/dts/rockchip/rk-stb-ir-keymap.dtsi | 394 -- .../rockchip/rk1808-dram-default-timing.dtsi | 302 - .../boot/dts/rockchip/rk1808-evb-v10.dts | 305 - .../dts/rockchip/rk1808-evb-x4-second.dts | 272 - .../arm64/boot/dts/rockchip/rk1808-evb-x4.dts | 271 - arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi | 717 --- arch/arm64/boot/dts/rockchip/rk1808-fpga.dts | 58 - arch/arm64/boot/dts/rockchip/rk1808.dtsi | 3039 ---------- arch/arm64/boot/dts/rockchip/rk1808k.dtsi | 51 - arch/arm64/boot/dts/rockchip/rk3588-amp.dtsi | 31 - .../boot/dts/rockchip/rk3588-android.dtsi | 143 - .../boot/dts/rockchip/rk3588-cpu-swap.dtsi | 87 - arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi | 1250 ---- .../boot/dts/rockchip/rk3588-evb1-cam-6x.dtsi | 766 --- .../boot/dts/rockchip/rk3588-evb1-imx415.dtsi | 158 - .../rk3588-evb1-lp4-v10-dsi-dsc-MV2100UZ1.dts | 200 - .../rk3588-evb1-lp4-v10-ipc-6x-linux.dts | 232 - .../rk3588-evb1-lp4-v10-linux-ipc.dts | 16 - .../rockchip/rk3588-evb1-lp4-v10-linux.dts | 46 - .../rk3588-evb1-lp4-v10-lt6911uxe.dts | 277 - .../boot/dts/rockchip/rk3588-evb1-lp4-v10.dts | 28 - .../boot/dts/rockchip/rk3588-evb1-lp4.dtsi | 775 --- .../boot/dts/rockchip/rk3588-evb2-imx415.dtsi | 176 - .../dts/rockchip/rk3588-evb2-lp4-v10-edp.dts | 137 - .../rockchip/rk3588-evb2-lp4-v10-edp2dp.dts | 73 - .../rockchip/rk3588-evb2-lp4-v10-linux.dts | 15 - .../boot/dts/rockchip/rk3588-evb2-lp4-v10.dts | 16 - .../boot/dts/rockchip/rk3588-evb2-lp4.dtsi | 541 -- .../boot/dts/rockchip/rk3588-evb3-imx415.dtsi | 176 - .../rk3588-evb3-lp5-v10-edp-linux.dts | 110 - .../dts/rockchip/rk3588-evb3-lp5-v10-edp.dts | 110 - .../rockchip/rk3588-evb3-lp5-v10-linux.dts | 16 - .../boot/dts/rockchip/rk3588-evb3-lp5-v10.dts | 16 - .../boot/dts/rockchip/rk3588-evb3-lp5.dtsi | 1232 ---- .../rockchip/rk3588-evb4-lp4-v10-linux.dts | 15 - .../boot/dts/rockchip/rk3588-evb4-lp4-v10.dts | 15 - .../boot/dts/rockchip/rk3588-evb4-lp4.dtsi | 495 -- .../rockchip/rk3588-evb5-lp4-v10-linux.dts | 15 - .../boot/dts/rockchip/rk3588-evb5-lp4-v10.dts | 15 - .../boot/dts/rockchip/rk3588-evb5-lp4.dtsi | 290 - .../rockchip/rk3588-evb6-lp4-v10-linux.dts | 15 - .../boot/dts/rockchip/rk3588-evb6-lp4-v10.dts | 15 - .../boot/dts/rockchip/rk3588-evb6-lp4.dtsi | 518 -- .../boot/dts/rockchip/rk3588-evb7-cam-8x.dtsi | 1198 ---- .../boot/dts/rockchip/rk3588-evb7-imx415.dtsi | 176 - .../rockchip/rk3588-evb7-lp4-v10-linux.dts | 16 - ...k3588-evb7-lp4-v10-rk1608-ipc-8x-linux.dts | 192 - .../boot/dts/rockchip/rk3588-evb7-lp4-v10.dts | 16 - .../rk3588-evb7-lp4-v11-linux-ipc.dts | 16 - .../boot/dts/rockchip/rk3588-evb7-lp4.dtsi | 846 --- .../dts/rockchip/rk3588-evb7-v11-imx415.dtsi | 176 - .../dts/rockchip/rk3588-evb7-v11-linux.dts | 16 - .../boot/dts/rockchip/rk3588-evb7-v11.dts | 16 - .../boot/dts/rockchip/rk3588-evb7-v11.dtsi | 949 --- arch/arm64/boot/dts/rockchip/rk3588-ipc.dtsi | 48 - .../dts/rockchip/rk3588-lubancat-5-v2.dts | 6 + .../boot/dts/rockchip/rk3588-lubancat-5.dts | 2 +- .../rockchip/rk3588-nvr-demo-v10-android.dts | 107 - .../rockchip/rk3588-nvr-demo-v10-cam-4x.dtsi | 565 -- .../rk3588-nvr-demo-v10-ipc-4x-linux.dts | 213 - .../rockchip/rk3588-nvr-demo-v10-spi-nand.dts | 31 - .../boot/dts/rockchip/rk3588-nvr-demo-v10.dts | 15 - .../boot/dts/rockchip/rk3588-nvr-demo.dtsi | 840 --- .../rockchip/rk3588-nvr-demo1-v21-android.dts | 84 - .../dts/rockchip/rk3588-nvr-demo1-v21.dts | 15 - .../dts/rockchip/rk3588-nvr-demo1-v21.dtsi | 215 - .../rockchip/rk3588-nvr-demo3-v10-android.dts | 84 - .../dts/rockchip/rk3588-nvr-demo3-v10.dts | 15 - .../dts/rockchip/rk3588-nvr-demo3-v10.dtsi | 70 - arch/arm64/boot/dts/rockchip/rk3588-nvr.dtsi | 336 -- arch/arm64/boot/dts/rockchip/rk3588-pc.dtsi | 351 -- .../rk3588-pcie-ep-demo-v11-linux.dts | 42 - .../dts/rockchip/rk3588-pcie-ep-demo-v11.dts | 15 - .../dts/rockchip/rk3588-pcie-ep-demo.dtsi | 641 -- .../boot/dts/rockchip/rk3588-rk806-dual.dtsi | 782 --- .../dts/rockchip/rk3588-rk806-single.dtsi | 396 -- .../dts/rockchip/rk3588-toybrick-edp-x0.dtsi | 770 --- .../dts/rockchip/rk3588-toybrick-imx258.dtsi | 323 -- .../rockchip/rk3588-toybrick-x0-android.dts | 16 - .../dts/rockchip/rk3588-toybrick-x0-linux.dts | 15 - .../boot/dts/rockchip/rk3588-toybrick-x0.dtsi | 754 --- .../boot/dts/rockchip/rk3588-toybrick.dtsi | 1267 ---- .../rk3588-vehicle-evb-image-reverse.dtsi | 211 - .../rk3588-vehicle-evb-maxim-max96712.dtsi | 157 - .../rk3588-vehicle-evb-mipi-nvp6188.dtsi | 135 - .../rk3588-vehicle-evb-thine_thcv244.dtsi | 134 - .../dts/rockchip/rk3588-vehicle-evb-v10.dts | 48 - .../dts/rockchip/rk3588-vehicle-evb-v20.dts | 125 - .../dts/rockchip/rk3588-vehicle-evb-v20.dtsi | 383 -- .../dts/rockchip/rk3588-vehicle-evb-v21.dts | 108 - .../dts/rockchip/rk3588-vehicle-evb-v21.dtsi | 398 -- .../boot/dts/rockchip/rk3588-vehicle-evb.dtsi | 672 --- .../rockchip/rk3588-vehicle-maxim-serdes.dtsi | 864 --- .../rk3588-vehicle-serdes-display-v20.dtsi | 1943 ------- .../rk3588-vehicle-serdes-display-v21.dtsi | 2095 ------- .../rk3588-vehicle-serdes-display.dtsi | 1943 ------- .../boot/dts/rockchip/rk3588-vehicle-v20.dtsi | 458 -- .../boot/dts/rockchip/rk3588-vehicle.dtsi | 535 -- arch/arm64/boot/dts/rockchip/rk3588m.dtsi | 27 - arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi | 1153 ---- .../rk3588s-evb1-lp4x-v10-camera.dtsi | 345 -- .../rockchip/rk3588s-evb1-lp4x-v10-linux.dts | 16 - .../dts/rockchip/rk3588s-evb1-lp4x-v10.dts | 16 - .../boot/dts/rockchip/rk3588s-evb1-lp4x.dtsi | 870 --- .../rockchip/rk3588s-evb2-lp5-v10-linux.dts | 15 - .../dts/rockchip/rk3588s-evb2-lp5-v10.dts | 15 - .../boot/dts/rockchip/rk3588s-evb2-lp5.dtsi | 952 --- .../rockchip/rk3588s-evb3-lp4x-v10-linux.dts | 15 - ...8s-evb3-lp4x-v10-nvp6158-ahd-to-bt1120.dts | 79 - ...588s-evb3-lp4x-v10-rk630-bt656-to-cvbs.dts | 72 - ...s-evb3-lp4x-v10-sii9022-bt1120-to-hdmi.dts | 85 - .../dts/rockchip/rk3588s-evb3-lp4x-v10.dts | 15 - .../boot/dts/rockchip/rk3588s-evb3-lp4x.dtsi | 367 -- .../rockchip/rk3588s-evb4-lp4x-v10-linux.dts | 15 - .../dts/rockchip/rk3588s-evb4-lp4x-v10.dts | 15 - .../boot/dts/rockchip/rk3588s-evb4-lp4x.dtsi | 946 --- .../dts/rockchip/rk3588s-evb8-lp4x-v10.dts | 16 - .../boot/dts/rockchip/rk3588s-evb8-lp4x.dtsi | 831 --- .../boot/dts/rockchip/rk3588s-rk806-dual.dtsi | 777 --- .../rk3588s-tablet-rk806-single-camera.dtsi | 180 - .../rk3588s-tablet-rk806-single-v10.dts | 15 - .../rockchip/rk3588s-tablet-rk806-single.dtsi | 1674 ------ .../dts/rockchip/rk3588s-tablet-single.dtsi | 1393 ----- .../boot/dts/rockchip/rk3588s-tablet-v10.dts | 14 - .../boot/dts/rockchip/rk3588s-tablet-v11.dts | 14 - .../boot/dts/rockchip/rk3588s-tablet.dtsi | 1320 ----- arch/arm64/boot/dts/socionext/Makefile | 8 - .../dts/socionext/uniphier-ld11-global.dts | 171 - .../boot/dts/socionext/uniphier-ld11-ref.dts | 86 - .../boot/dts/socionext/uniphier-ld11.dtsi | 663 --- .../dts/socionext/uniphier-ld20-akebi96.dts | 189 - .../dts/socionext/uniphier-ld20-global.dts | 155 - .../boot/dts/socionext/uniphier-ld20-ref.dts | 86 - .../boot/dts/socionext/uniphier-ld20.dtsi | 982 ---- .../boot/dts/socionext/uniphier-pinctrl.dtsi | 1 - .../boot/dts/socionext/uniphier-pxs3-ref.dts | 154 - .../boot/dts/socionext/uniphier-pxs3.dtsi | 861 --- .../dts/socionext/uniphier-ref-daughter.dtsi | 1 - .../dts/socionext/uniphier-support-card.dtsi | 1 - arch/arm64/boot/dts/sprd/Makefile | 4 - arch/arm64/boot/dts/sprd/sc2731.dtsi | 258 - arch/arm64/boot/dts/sprd/sc9836-openphone.dts | 49 - arch/arm64/boot/dts/sprd/sc9836.dtsi | 224 - arch/arm64/boot/dts/sprd/sc9860.dtsi | 716 --- arch/arm64/boot/dts/sprd/sc9863a.dtsi | 589 -- arch/arm64/boot/dts/sprd/sharkl3.dtsi | 242 - arch/arm64/boot/dts/sprd/sharkl64.dtsi | 65 - arch/arm64/boot/dts/sprd/sp9860g-1h10.dts | 74 - arch/arm64/boot/dts/sprd/sp9863a-1h10.dts | 39 - arch/arm64/boot/dts/sprd/whale2.dtsi | 310 - arch/arm64/boot/dts/synaptics/Makefile | 4 - arch/arm64/boot/dts/synaptics/as370.dtsi | 173 - .../boot/dts/synaptics/berlin4ct-dmp.dts | 29 - .../boot/dts/synaptics/berlin4ct-stb.dts | 29 - arch/arm64/boot/dts/synaptics/berlin4ct.dtsi | 314 - arch/arm64/boot/dts/ti/Makefile | 13 - arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 934 --- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 272 - arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 108 - arch/arm64/boot/dts/ti/k3-am65.dtsi | 124 - .../arm64/boot/dts/ti/k3-am654-base-board.dts | 488 -- .../dts/ti/k3-am654-industrial-thermal.dtsi | 45 - arch/arm64/boot/dts/ti/k3-am654.dtsi | 115 - .../dts/ti/k3-j7200-common-proc-board.dts | 215 - arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 455 -- .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 273 - arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 65 - arch/arm64/boot/dts/ti/k3-j7200.dtsi | 173 - .../dts/ti/k3-j721e-common-proc-board.dts | 645 -- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 1626 ------ .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 356 -- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 227 - arch/arm64/boot/dts/ti/k3-j721e.dtsi | 185 - arch/arm64/boot/dts/toshiba/Makefile | 2 - .../boot/dts/toshiba/tmpv7708-rm-mbrc.dts | 43 - arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 390 -- .../arm64/boot/dts/toshiba/tmpv7708_pins.dtsi | 93 - arch/arm64/boot/dts/xilinx/Makefile | 17 - .../boot/dts/xilinx/avnet-ultra96-rev1.dts | 19 - .../arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 217 - .../boot/dts/xilinx/zynqmp-zc1232-revA.dts | 54 - .../boot/dts/xilinx/zynqmp-zc1254-revA.dts | 42 - .../boot/dts/xilinx/zynqmp-zc1275-revA.dts | 42 - .../dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 132 - .../dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 170 - .../dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 150 - 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+= intel -subdir-y += lg -subdir-y += marvell -subdir-y += mediatek -subdir-y += microchip -subdir-y += nvidia -subdir-y += qcom -subdir-y += realtek -subdir-y += renesas subdir-y += rockchip -subdir-y += socionext -subdir-y += sprd -subdir-y += synaptics -subdir-y += ti -subdir-y += toshiba -subdir-y += xilinx -subdir-y += zte + diff --git a/arch/arm64/boot/dts/actions/Makefile b/arch/arm64/boot/dts/actions/Makefile deleted file mode 100644 index b57fd2372..000000000 --- a/arch/arm64/boot/dts/actions/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ - -dtb-$(CONFIG_ARCH_ACTIONS) += s700-cubieboard7.dtb - -dtb-$(CONFIG_ARCH_ACTIONS) += s900-bubblegum-96.dtb diff --git a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts deleted file mode 100644 index 63e375cd9..000000000 --- a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Andreas Färber - */ - -/dts-v1/; - -#include "s700.dtsi" - -/ { - compatible = "cubietech,cubieboard7", "actions,s700"; - model = "CubieBoard7"; - - aliases { - serial3 = &uart3; - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - memory@1,e0000000 { - device_type = "memory"; - reg = <0x1 0xe0000000 0x0 0x0>; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_default>; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_default>; -}; - -&i2c2 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_default>; -}; - -&pinctrl { - i2c0_default: i2c0_default { - pinmux { - groups = "i2c0_mfp"; - function = "i2c0"; - }; - pinconf { - pins = "i2c0_sclk", "i2c0_sdata"; - bias-pull-up; - }; - }; - - i2c1_default: i2c1_default { - pinmux { - groups = "i2c1_dummy"; - function = "i2c1"; - }; - pinconf { - pins = "i2c1_sclk", "i2c1_sdata"; - bias-pull-up; - }; - }; - - i2c2_default: i2c2_default { - pinmux { - groups = "i2c2_dummy"; - function = "i2c2"; - }; - pinconf { - pins = "i2c2_sclk", "i2c2_sdata"; - bias-pull-up; - }; - }; -}; - -&timer { - clocks = <&hosc>; -}; - -&uart3 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi deleted file mode 100644 index 2c78caebf..000000000 --- a/arch/arm64/boot/dts/actions/s700.dtsi +++ /dev/null @@ -1,263 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Andreas Färber - */ - -#include -#include -#include -#include - -/ { - compatible = "actions,s700"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secmon@1f000000 { - reg = <0x0 0x1f000000 0x0 0x1000000>; - no-map; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - hosc: hosc { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - - losc: losc { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gic: interrupt-controller@e00f1000 { - compatible = "arm,gic-400"; - reg = <0x0 0xe00f1000 0x0 0x1000>, - <0x0 0xe00f2000 0x0 0x2000>, - <0x0 0xe00f4000 0x0 0x2000>, - <0x0 0xe00f6000 0x0 0x2000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - - uart0: serial@e0120000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe0120000 0x0 0x2000>; - clocks = <&cmu CLK_UART0>; - interrupts = ; - status = "disabled"; - }; - - uart1: serial@e0122000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe0122000 0x0 0x2000>; - clocks = <&cmu CLK_UART1>; - interrupts = ; - status = "disabled"; - }; - - uart2: serial@e0124000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe0124000 0x0 0x2000>; - clocks = <&cmu CLK_UART2>; - interrupts = ; - status = "disabled"; - }; - - uart3: serial@e0126000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe0126000 0x0 0x2000>; - clocks = <&cmu CLK_UART3>; - interrupts = ; - status = "disabled"; - }; - - uart4: serial@e0128000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe0128000 0x0 0x2000>; - clocks = <&cmu CLK_UART4>; - interrupts = ; - status = "disabled"; - }; - - uart5: serial@e012a000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe012a000 0x0 0x2000>; - clocks = <&cmu CLK_UART5>; - interrupts = ; - status = "disabled"; - }; - - uart6: serial@e012c000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe012c000 0x0 0x2000>; - clocks = <&cmu CLK_UART6>; - interrupts = ; - status = "disabled"; - }; - - cmu: clock-controller@e0168000 { - compatible = "actions,s700-cmu"; - reg = <0x0 0xe0168000 0x0 0x1000>; - clocks = <&hosc>, <&losc>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - i2c0: i2c@e0170000 { - compatible = "actions,s700-i2c"; - reg = <0 0xe0170000 0 0x1000>; - clocks = <&cmu CLK_I2C0>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@e0174000 { - compatible = "actions,s700-i2c"; - reg = <0 0xe0174000 0 0x1000>; - clocks = <&cmu CLK_I2C1>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e0178000 { - compatible = "actions,s700-i2c"; - reg = <0 0xe0178000 0 0x1000>; - clocks = <&cmu CLK_I2C2>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@e017c000 { - compatible = "actions,s700-i2c"; - reg = <0 0xe017c000 0 0x1000>; - clocks = <&cmu CLK_I2C3>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sps: power-controller@e01b0100 { - compatible = "actions,s700-sps"; - reg = <0x0 0xe01b0100 0x0 0x100>; - #power-domain-cells = <1>; - }; - - timer: timer@e024c000 { - compatible = "actions,s700-timer"; - reg = <0x0 0xe024c000 0x0 0x4000>; - interrupts = ; - interrupt-names = "timer1"; - }; - - pinctrl: pinctrl@e01b0000 { - compatible = "actions,s700-pinctrl"; - reg = <0x0 0xe01b0000 0x0 0x100>; - clocks = <&cmu CLK_GPIO>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 136>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - , - ; - }; - - dma: dma-controller@e0230000 { - compatible = "actions,s700-dma"; - reg = <0x0 0xe0230000 0x0 0x1000>; - interrupts = , - , - , - ; - #dma-cells = <1>; - dma-channels = <10>; - dma-requests = <44>; - clocks = <&cmu CLK_DMAC>; - power-domains = <&sps S700_PD_DMA>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts deleted file mode 100644 index 59291e0ea..000000000 --- a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts +++ /dev/null @@ -1,314 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Andreas Färber - */ - -/dts-v1/; - -#include "s900.dtsi" - -/ { - compatible = "ucrobotics,bubblegum-96", "actions,s900"; - model = "Bubblegum-96"; - - aliases { - mmc0 = &mmc0; - mmc1 = &mmc1; - mmc2 = &mmc2; - serial5 = &uart5; - }; - - chosen { - stdout-path = "serial5:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - /* Fixed regulator used in the absence of PMIC */ - vcc_3v1: vcc-3v1 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.1V"; - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - regulator-always-on; - }; - - /* Fixed regulator used in the absence of PMIC */ - sd_vcc: sd-vcc { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.1V"; - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - regulator-always-on; - }; -}; - -&i2c0 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_default>; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_default>; -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_default>; -}; - -/* - * GPIO name legend: proper name = the GPIO line is used as GPIO - * NC = not connected (pin out but not routed from the chip to - * anything the board) - * "[PER]" = pin is muxed for [peripheral] (not GPIO) - * LSEC = Low Speed External Connector - * HSEC = High Speed External Connector - * - * Line names are taken from the schematic "Schematics Bubblegum96" - * version v1.0 - * - * For the lines routed to the external connectors the - * lines are named after the 96Boards CE Specification 1.0, - * Appendix "Expansion Connector Signal Description". - * - * When the 96Boards naming of a line and the schematic name of - * the same line are in conflict, the 96Boards specification - * takes precedence, which means that the external UART on the - * LSEC is named UART0 while the schematic and SoC names this - * UART2. Only exception is the I2C lines for which the schematic - * naming has been preferred. This is only for the informational - * lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L" - * are the only ones actually used for GPIO. - */ - -&pinctrl { - gpio-line-names = - "GPIO-A", /* GPIO_0, LSEC pin 23 */ - "GPIO-B", /* GPIO_1, LSEC pin 24 */ - "GPIO-C", /* GPIO_2, LSEC pin 25 */ - "GPIO-D", /* GPIO_3, LSEC pin 26 */ - "GPIO-E", /* GPIO_4, LSEC pin 27 */ - "GPIO-F", /* GPIO_5, LSEC pin 28 */ - "GPIO-G", /* GPIO_6, LSEC pin 29 */ - "GPIO-H", /* GPIO_7, LSEC pin 30 */ - "GPIO-I", /* GPIO_8, LSEC pin 31 */ - "GPIO-J", /* GPIO_9, LSEC pin 32 */ - "NC", /* GPIO_10 */ - "NC", /* GPIO_11 */ - "SIRQ2_1V8", /* GPIO_12 */ - "PCM0_OUT", /* GPIO_13 */ - "WIFI_LED", /* GPIO_14 */ - "PCM0_SYNC", /* GPIO_15 */ - "PCM0_CLK", /* GPIO_16 */ - "PCM0_IN", /* GPIO_17 */ - "BT_LED", /* GPIO_18 */ - "LED0", /* GPIO_19 */ - "LED1", /* GPIO_20 */ - "JTAG_TCK", /* GPIO_21 */ - "JTAG_TMS", /* GPIO_22 */ - "JTAG_TDI", /* GPIO_23 */ - "JTAG_TDO", /* GPIO_24 */ - "[UART1_RxD]", /* GPIO_25, LSEC pin 13 */ - "NC", /* GPIO_26 */ - "[UART1_TxD]", /* GPIO_27, LSEC pin 11 */ - "SD0_D0", /* GPIO_28 */ - "SD0_D1", /* GPIO_29 */ - "SD0_D2", /* GPIO_30 */ - "SD0_D3", /* GPIO_31 */ - "SD1_D0", /* GPIO_32 */ - "SD1_D1", /* GPIO_33 */ - "SD1_D2", /* GPIO_34 */ - "SD1_D3", /* GPIO_35 */ - "SD0_CMD", /* GPIO_36 */ - "SD0_CLK", /* GPIO_37 */ - "SD1_CMD", /* GPIO_38 */ - "SD1_CLK", /* GPIO_39 */ - "SPI0_SCLK", /* GPIO_40, LSEC pin 8 */ - "SPI0_CS", /* GPIO_41, LSEC pin 12 */ - "SPI0_DIN", /* GPIO_42, LSEC pin 10 */ - "SPI0_DOUT", /* GPIO_43, LSEC pin 14 */ - "I2C5_SDATA", /* GPIO_44, HSEC pin 36 */ - "I2C5_SCLK", /* GPIO_45, HSEC pin 38 */ - "UART0_RX", /* GPIO_46, LSEC pin 7 */ - "UART0_TX", /* GPIO_47, LSEC pin 5 */ - "UART0_RTSB", /* GPIO_48, LSEC pin 9 */ - "UART0_CTSB", /* GPIO_49, LSEC pin 3 */ - "I2C4_SCLK", /* GPIO_50, HSEC pin 32 */ - "I2C4_SDATA", /* GPIO_51, HSEC pin 34 */ - "I2C0_SCLK", /* GPIO_52 */ - "I2C0_SDATA", /* GPIO_53 */ - "I2C1_SCLK", /* GPIO_54, LSEC pin 15 */ - "I2C1_SDATA", /* GPIO_55, LSEC pin 17 */ - "I2C2_SCLK", /* GPIO_56, LSEC pin 19 */ - "I2C2_SDATA", /* GPIO_57, LSEC pin 21 */ - "CSI0_DN0", /* GPIO_58, HSEC pin 10 */ - "CSI0_DP0", /* GPIO_59, HSEC pin 8 */ - "CSI0_DN1", /* GPIO_60, HSEC pin 16 */ - "CSI0_DP1", /* GPIO_61, HSEC pin 14 */ - "CSI0_CN", /* GPIO_62, HSEC pin 4 */ - "CSI0_CP", /* GPIO_63, HSEC pin 2 */ - "CSI0_DN2", /* GPIO_64, HSEC pin 22 */ - "CSI0_DP2", /* GPIO_65, HSEC pin 20 */ - "CSI0_DN3", /* GPIO_66, HSEC pin 28 */ - "CSI0_DP3", /* GPIO_67, HSEC pin 26 */ - "[CLK0]", /* GPIO_68, HSEC pin 15 */ - "CSI1_DN0", /* GPIO_69, HSEC pin 44 */ - "CSI1_DP0", /* GPIO_70, HSEC pin 42 */ - "CSI1_DN1", /* GPIO_71, HSEC pin 50 */ - "CSI1_DP1", /* GPIO_72, HSEC pin 48 */ - "CSI1_CN", /* GPIO_73, HSEC pin 56 */ - "CSI1_CP", /* GPIO_74, HSEC pin 54 */ - "[CLK1]", /* GPIO_75, HSEC pin 17 */ - "[GPIOD0]", /* GPIO_76 */ - "[GPIOD1]", /* GPIO_77 */ - "BT_RST_N", /* GPIO_78 */ - "EXT_DC_EN", /* GPIO_79 */ - "[PCM_DI]", /* GPIO_80, LSEC pin 22 */ - "[PCM_DO]", /* GPIO_81, LSEC pin 20 */ - "[PCM_CLK]", /* GPIO_82, LSEC pin 18 */ - "[PCM_FS]", /* GPIO_83, LSEC pin 16 */ - "WAKE_BT", /* GPIO_84 */ - "WL_REG_ON", /* GPIO_85 */ - "NC", /* GPIO_86 */ - "NC", /* GPIO_87 */ - "NC", /* GPIO_88 */ - "NC", /* GPIO_89 */ - "NC", /* GPIO_90 */ - "WIFI_WAKE", /* GPIO_91 */ - "BT_WAKE", /* GPIO_92 */ - "NC", /* GPIO_93 */ - "OTG_EN2", /* GPIO_94 */ - "OTG_EN", /* GPIO_95 */ - "DSI_DP3", /* GPIO_96, HSEC pin 45 */ - "DSI_DN3", /* GPIO_97, HSEC pin 47 */ - "DSI_DP1", /* GPIO_98, HSEC pin 33 */ - "DSI_DN1", /* GPIO_99, HSEC pin 35 */ - "DSI_CP", /* GPIO_100, HSEC pin 21 */ - "DSI_CN", /* GPIO_101, HSEC pin 23 */ - "DSI_DP0", /* GPIO_102, HSEC pin 27 */ - "DSI_DN0", /* GPIO_103, HSEC pin 29 */ - "DSI_DP2", /* GPIO_104, HSEC pin 39 */ - "DSI_DN2", /* GPIO_105, HSEC pin 41 */ - "N0_D0", /* GPIO_106 */ - "N0_D1", /* GPIO_107 */ - "N0_D2", /* GPIO_108 */ - "N0_D3", /* GPIO_109 */ - "N0_D4", /* GPIO_110 */ - "N0_D5", /* GPIO_111 */ - "N0_D6", /* GPIO_112 */ - "N0_D7", /* GPIO_113 */ - "N0_DQS", /* GPIO_114 */ - "N0_DQSN", /* GPIO_115 */ - "NC", /* GPIO_116 */ - "NC", /* GPIO_117 */ - "NC", /* GPIO_118 */ - "N0_CEB1", /* GPIO_119 */ - "CARD_DT", /* GPIO_120 */ - "N0_CEB3", /* GPIO_121 */ - "SD_DAT0", /* GPIO_122, HSEC pin 1 */ - "SD_DAT1", /* GPIO_123, HSEC pin 3 */ - "SD_DAT2", /* GPIO_124, HSEC pin 5 */ - "SD_DAT3", /* GPIO_125, HSEC pin 7 */ - "NC", /* GPIO_126 */ - "NC", /* GPIO_127 */ - "[PWR_BTN_N]", /* GPIO_128, LSEC pin 4 */ - "[RST_BTN_N]", /* GPIO_129, LSEC pin 6 */ - "NC", /* GPIO_130 */ - "SD_CMD", /* GPIO_131 */ - "GPIO-L", /* GPIO_132, LSEC pin 34 */ - "GPIO-K", /* GPIO_133, LSEC pin 33 */ - "NC", /* GPIO_134 */ - "SD_SCLK", /* GPIO_135 */ - "NC", /* GPIO_136 */ - "JTAG_TRST", /* GPIO_137 */ - "I2C3_SCLK", /* GPIO_138 */ - "LED2", /* GPIO_139 */ - "LED3", /* GPIO_140 */ - "I2C3_SDATA", /* GPIO_141 */ - "UART3_RX", /* GPIO_142 */ - "UART3_TX", /* GPIO_143 */ - "UART3_RTSB", /* GPIO_144 */ - "UART3_CTSB"; /* GPIO_145 */ - - i2c0_default: i2c0-default { - pinmux { - groups = "i2c0_mfp"; - function = "i2c0"; - }; - pinconf { - pins = "i2c0_sclk", "i2c0_sdata"; - bias-pull-up; - }; - }; - - i2c1_default: i2c1-default { - pinconf { - pins = "i2c1_sclk", "i2c1_sdata"; - bias-pull-up; - }; - }; - - i2c2_default: i2c2-default { - pinconf { - pins = "i2c2_sclk", "i2c2_sdata"; - bias-pull-up; - }; - }; - - mmc0_default: mmc0_default { - pinmux { - groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp", - "sd0_cmd_mfp", "sd0_clk_mfp"; - function = "sd0"; - }; - }; - - mmc2_default: mmc2_default { - pinmux { - groups = "nand0_d0_ceb3_mfp"; - function = "sd2"; - }; - }; -}; - -/* uSD */ -&mmc0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_default>; - no-sdio; - no-mmc; - no-1-8-v; - cd-gpios = <&pinctrl 120 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <&sd_vcc>; - vqmmc-supply = <&sd_vcc>; -}; - -/* eMMC */ -&mmc2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_default>; - no-sdio; - no-sd; - non-removable; - bus-width = <8>; - vmmc-supply = <&vcc_3v1>; -}; - -&timer { - clocks = <&hosc>; -}; - -&uart5 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi deleted file mode 100644 index eb35cf78a..000000000 --- a/arch/arm64/boot/dts/actions/s900.dtsi +++ /dev/null @@ -1,333 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Andreas Färber - */ - -#include -#include -#include -#include - -/ { - compatible = "actions,s900"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secmon@1f000000 { - reg = <0x0 0x1f000000 0x0 0x1000000>; - no-map; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - hosc: hosc { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - - losc: losc { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - diff24M: diff24M { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gic: interrupt-controller@e00f1000 { - compatible = "arm,gic-400"; - reg = <0x0 0xe00f1000 0x0 0x1000>, - <0x0 0xe00f2000 0x0 0x2000>, - <0x0 0xe00f4000 0x0 0x2000>, - <0x0 0xe00f6000 0x0 0x2000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - - uart0: serial@e0120000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe0120000 0x0 0x2000>; - clocks = <&cmu CLK_UART0>; - interrupts = ; - status = "disabled"; - }; - - uart1: serial@e0122000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe0122000 0x0 0x2000>; - clocks = <&cmu CLK_UART1>; - interrupts = ; - status = "disabled"; - }; - - uart2: serial@e0124000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe0124000 0x0 0x2000>; - clocks = <&cmu CLK_UART2>; - interrupts = ; - status = "disabled"; - }; - - uart3: serial@e0126000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe0126000 0x0 0x2000>; - clocks = <&cmu CLK_UART3>; - interrupts = ; - status = "disabled"; - }; - - uart4: serial@e0128000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe0128000 0x0 0x2000>; - clocks = <&cmu CLK_UART4>; - interrupts = ; - status = "disabled"; - }; - - uart5: serial@e012a000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe012a000 0x0 0x2000>; - clocks = <&cmu CLK_UART5>; - interrupts = ; - status = "disabled"; - }; - - uart6: serial@e012c000 { - compatible = "actions,s900-uart", "actions,owl-uart"; - reg = <0x0 0xe012c000 0x0 0x2000>; - clocks = <&cmu CLK_UART6>; - interrupts = ; - status = "disabled"; - }; - - sps: power-controller@e012e000 { - compatible = "actions,s900-sps"; - reg = <0x0 0xe012e000 0x0 0x2000>; - #power-domain-cells = <1>; - }; - - cmu: clock-controller@e0160000 { - compatible = "actions,s900-cmu"; - reg = <0x0 0xe0160000 0x0 0x1000>; - clocks = <&hosc>, <&losc>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - i2c0: i2c@e0170000 { - compatible = "actions,s900-i2c"; - reg = <0 0xe0170000 0 0x1000>; - clocks = <&cmu CLK_I2C0>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@e0172000 { - compatible = "actions,s900-i2c"; - reg = <0 0xe0172000 0 0x1000>; - clocks = <&cmu CLK_I2C1>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e0174000 { - compatible = "actions,s900-i2c"; - reg = <0 0xe0174000 0 0x1000>; - clocks = <&cmu CLK_I2C2>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@e0176000 { - compatible = "actions,s900-i2c"; - reg = <0 0xe0176000 0 0x1000>; - clocks = <&cmu CLK_I2C3>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@e0178000 { - compatible = "actions,s900-i2c"; - reg = <0 0xe0178000 0 0x1000>; - clocks = <&cmu CLK_I2C4>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@e017a000 { - compatible = "actions,s900-i2c"; - reg = <0 0xe017a000 0 0x1000>; - clocks = <&cmu CLK_I2C5>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pinctrl: pinctrl@e01b0000 { - compatible = "actions,s900-pinctrl"; - reg = <0x0 0xe01b0000 0x0 0x1000>; - clocks = <&cmu CLK_GPIO>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 146>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - , - , - , - ; - }; - - timer: timer@e0228000 { - compatible = "actions,s900-timer"; - reg = <0x0 0xe0228000 0x0 0x8000>; - interrupts = ; - interrupt-names = "timer1"; - }; - - dma: dma-controller@e0260000 { - compatible = "actions,s900-dma"; - reg = <0x0 0xe0260000 0x0 0x1000>; - interrupts = , - , - , - ; - #dma-cells = <1>; - dma-channels = <12>; - dma-requests = <46>; - clocks = <&cmu CLK_DMAC>; - }; - - mmc0: mmc@e0330000 { - compatible = "actions,owl-mmc"; - reg = <0x0 0xe0330000 0x0 0x4000>; - interrupts = ; - clocks = <&cmu CLK_SD0>; - resets = <&cmu RESET_SD0>; - dmas = <&dma 2>; - dma-names = "mmc"; - status = "disabled"; - }; - - mmc1: mmc@e0334000 { - compatible = "actions,owl-mmc"; - reg = <0x0 0xe0334000 0x0 0x4000>; - interrupts = ; - clocks = <&cmu CLK_SD1>; - resets = <&cmu RESET_SD1>; - dmas = <&dma 3>; - dma-names = "mmc"; - status = "disabled"; - }; - - mmc2: mmc@e0338000 { - compatible = "actions,owl-mmc"; - reg = <0x0 0xe0338000 0x0 0x4000>; - interrupts = ; - clocks = <&cmu CLK_SD2>; - resets = <&cmu RESET_SD2>; - dmas = <&dma 4>; - dma-names = "mmc"; - status = "disabled"; - }; - - mmc3: mmc@e033c000 { - compatible = "actions,owl-mmc"; - reg = <0x0 0xe033c000 0x0 0x4000>; - interrupts = ; - clocks = <&cmu CLK_SD3>; - resets = <&cmu RESET_SD3>; - dmas = <&dma 46>; - dma-names = "mmc"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile deleted file mode 100644 index 211d1e9d4..000000000 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ /dev/null @@ -1,37 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-amarula-relic.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-oceanic-5205-5inmfd.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-emmc.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-lts.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.0.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.1.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.2.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a100-allwinner-perf1.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus-v1.2.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-emlid-neutis-n5-devboard.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-cc.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-it.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h5-cc.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-beelink-gs1.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb -dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi b/arch/arm64/boot/dts/allwinner/axp803.dtsi deleted file mode 100644 index 10e9186a7..000000000 --- a/arch/arm64/boot/dts/allwinner/axp803.dtsi +++ /dev/null @@ -1,155 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright 2017 Icenowy Zheng - -/* - * AXP803 Integrated Power Management Chip - * http://files.pine64.org/doc/datasheet/pine64/AXP803_Datasheet_V1.0.pdf - */ - -&axp803 { - interrupt-controller; - #interrupt-cells = <1>; - - ac_power_supply: ac-power-supply { - compatible = "x-powers,axp803-ac-power-supply", - "x-powers,axp813-ac-power-supply"; - status = "disabled"; - }; - - axp_adc: adc { - compatible = "x-powers,axp803-adc", "x-powers,axp813-adc"; - #io-channel-cells = <1>; - }; - - axp_gpio: gpio { - compatible = "x-powers,axp803-gpio", "x-powers,axp813-gpio"; - gpio-controller; - #gpio-cells = <2>; - - gpio0_ldo: gpio0-ldo { - pins = "GPIO0"; - function = "ldo"; - }; - - gpio1_ldo: gpio1-ldo { - pins = "GPIO1"; - function = "ldo"; - }; - }; - - battery_power_supply: battery-power-supply { - compatible = "x-powers,axp803-battery-power-supply", - "x-powers,axp813-battery-power-supply"; - status = "disabled"; - }; - - regulators { - /* Default work frequency for buck regulators */ - x-powers,dcdc-freq = <3000>; - - reg_aldo1: aldo1 { - regulator-name = "aldo1"; - }; - - reg_aldo2: aldo2 { - regulator-name = "aldo2"; - }; - - reg_aldo3: aldo3 { - regulator-name = "aldo3"; - }; - - reg_dc1sw: dc1sw { - regulator-name = "dc1sw"; - }; - - reg_dcdc1: dcdc1 { - regulator-name = "dcdc1"; - }; - - reg_dcdc2: dcdc2 { - regulator-name = "dcdc2"; - }; - - reg_dcdc3: dcdc3 { - regulator-name = "dcdc3"; - }; - - reg_dcdc4: dcdc4 { - regulator-name = "dcdc4"; - }; - - reg_dcdc5: dcdc5 { - regulator-name = "dcdc5"; - }; - - reg_dcdc6: dcdc6 { - regulator-name = "dcdc6"; - }; - - reg_dldo1: dldo1 { - regulator-name = "dldo1"; - }; - - reg_dldo2: dldo2 { - regulator-name = "dldo2"; - }; - - reg_dldo3: dldo3 { - regulator-name = "dldo3"; - }; - - reg_dldo4: dldo4 { - regulator-name = "dldo4"; - }; - - reg_eldo1: eldo1 { - regulator-name = "eldo1"; - }; - - reg_eldo2: eldo2 { - regulator-name = "eldo2"; - }; - - reg_eldo3: eldo3 { - regulator-name = "eldo3"; - }; - - reg_fldo1: fldo1 { - regulator-name = "fldo1"; - }; - - reg_fldo2: fldo2 { - regulator-name = "fldo2"; - }; - - reg_ldo_io0: ldo-io0 { - regulator-name = "ldo-io0"; - status = "disabled"; - }; - - reg_ldo_io1: ldo-io1 { - regulator-name = "ldo-io1"; - status = "disabled"; - }; - - reg_rtc_ldo: rtc-ldo { - /* RTC_LDO is a fixed, always-on regulator */ - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "rtc-ldo"; - }; - - reg_drivevbus: drivevbus { - regulator-name = "drivevbus"; - status = "disabled"; - }; - }; - - usb_power_supply: usb-power-supply { - compatible = "x-powers,axp803-usb-power-supply", - "x-powers,axp813-usb-power-supply"; - status = "disabled"; - }; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts deleted file mode 100644 index d34c2bb10..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) -/* - * Copyright (c) 2020 Yangtao Li - */ - -/dts-v1/; - -#include "sun50i-a100.dtsi" - -/{ - model = "Allwinner A100 Perf1"; - compatible = "allwinner,a100-perf1", "allwinner,sun50i-a100"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&pio { - vcc-pb-supply = <®_dcdc1>; - vcc-pc-supply = <®_eldo1>; - vcc-pd-supply = <®_dcdc1>; - vcc-pe-supply = <®_dldo2>; - vcc-pf-supply = <®_dcdc1>; - vcc-pg-supply = <®_dldo1>; - vcc-ph-supply = <®_dcdc1>; -}; - -&r_pio { - /* - * FIXME: We can't add that supply for now since it would - * create a circular dependency between pinctrl, the regulator - * and the RSB Bus. - * - * vcc-pl-supply = <®_aldo3>; - */ -}; - -&r_i2c0 { - status = "okay"; - - axp803: pmic@34 { - compatible = "x-powers,axp803"; - reg = <0x34>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ - }; -}; - -#include "axp803.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-dram-1"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-usb-pl"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-io-usb-pd-emmc-nand-card"; -}; - -®_dcdc2 { - regulator-always-on; - /* - * FIXME: update min and max before support dvfs. - */ - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpux"; -}; - -/* DCDC3 is polyphased with DCDC2 */ - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <950000>; - regulator-name = "vdd-sys-usb-dram"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram-2"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pg-dcxo-wifi"; -}; - -®_dldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vcc-pe-csi"; -}; - -®_dldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "ldo-avdd-csi"; -}; - -®_dldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "avcc-csi"; -}; - -®_eldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pc-lvds-csi-efuse-emmc-nand"; -}; - -®_eldo2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1800000>; - regulator-name = "dvdd-csi"; -}; - -®_eldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-mipi-lcd"; -}; - -®_fldo1 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdd-cpus-usb"; -}; - -®_ldo_io0 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-ctp"; - status = "okay"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi deleted file mode 100644 index f6d7d7f7f..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +++ /dev/null @@ -1,364 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) -/* - * Copyright (c) 2020 Yangtao Li - */ - -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0>; - enable-method = "psci"; - }; - - cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x1>; - enable-method = "psci"; - }; - - cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x2>; - enable-method = "psci"; - }; - - cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x3>; - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - dcxo24M: dcxo24M-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "dcxo24M"; - #clock-cells = <0>; - }; - - iosc: internal-osc-clk { - compatible = "fixed-clock"; - clock-frequency = <16000000>; - clock-accuracy = <300000000>; - clock-output-names = "iosc"; - #clock-cells = <0>; - }; - - osc32k: osc32k-clk { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - #clock-cells = <0>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0x3fffffff>; - - ccu: clock@3001000 { - compatible = "allwinner,sun50i-a100-ccu"; - reg = <0x03001000 0x1000>; - clocks = <&dcxo24M>, <&osc32k>, <&iosc>; - clock-names = "hosc", "losc", "iosc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - gic: interrupt-controller@3021000 { - compatible = "arm,gic-400"; - reg = <0x03021000 0x1000>, <0x03022000 0x2000>, - <0x03024000 0x2000>, <0x03026000 0x2000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - - efuse@3006000 { - compatible = "allwinner,sun50i-a100-sid", - "allwinner,sun50i-a64-sid"; - reg = <0x03006000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - ths_calibration: calib@14 { - reg = <0x14 8>; - }; - }; - - pio: pinctrl@300b000 { - compatible = "allwinner,sun50i-a100-pinctrl"; - reg = <0x0300b000 0x400>; - interrupts = , - , - , - , - , - , - ; - clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&osc32k>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - uart0_pb_pins: uart0-pb-pins { - pins = "PB9", "PB10"; - function = "uart0"; - }; - }; - - uart0: serial@5000000 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - status = "disabled"; - }; - - uart1: serial@5000400 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - status = "disabled"; - }; - - uart2: serial@5000800 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - status = "disabled"; - }; - - uart3: serial@5000c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - resets = <&ccu RST_BUS_UART3>; - status = "disabled"; - }; - - uart4: serial@5001000 { - compatible = "snps,dw-apb-uart"; - reg = <0x05001000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART4>; - resets = <&ccu RST_BUS_UART4>; - status = "disabled"; - }; - - i2c0: i2c@5002000 { - compatible = "allwinner,sun50i-a100-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05002000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@5002400 { - compatible = "allwinner,sun50i-a100-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05002400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@5002800 { - compatible = "allwinner,sun50i-a100-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05002800 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c3: i2c@5002c00 { - compatible = "allwinner,sun50i-a100-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05002c00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C3>; - resets = <&ccu RST_BUS_I2C3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ths: thermal-sensor@5070400 { - compatible = "allwinner,sun50i-a100-ths"; - reg = <0x05070400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_THS>; - clock-names = "bus"; - resets = <&ccu RST_BUS_THS>; - nvmem-cells = <&ths_calibration>; - nvmem-cell-names = "calibration"; - #thermal-sensor-cells = <1>; - }; - - r_ccu: clock@7010000 { - compatible = "allwinner,sun50i-a100-r-ccu"; - reg = <0x07010000 0x300>; - clocks = <&dcxo24M>, <&osc32k>, <&iosc>, - <&ccu CLK_PLL_PERIPH0>; - clock-names = "hosc", "losc", "iosc", "pll-periph"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - r_intc: interrupt-controller@7010320 { - compatible = "allwinner,sun50i-a100-nmi", - "allwinner,sun9i-a80-nmi"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x07010320 0xc>; - interrupts = ; - }; - - r_pio: pinctrl@7022000 { - compatible = "allwinner,sun50i-a100-r-pinctrl"; - reg = <0x07022000 0x400>; - interrupts = ; - clocks = <&r_ccu CLK_R_APB1>, <&dcxo24M>, <&osc32k>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - r_i2c0_pins: r-i2c0-pins { - pins = "PL0", "PL1"; - function = "s_i2c0"; - }; - - r_i2c1_pins: r-i2c1-pins { - pins = "PL8", "PL9"; - function = "s_i2c1"; - }; - }; - - r_uart: serial@7080000 { - compatible = "snps,dw-apb-uart"; - reg = <0x07080000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&r_ccu CLK_R_APB2_UART>; - resets = <&r_ccu RST_R_APB2_UART>; - status = "disabled"; - }; - - r_i2c0: i2c@7081400 { - compatible = "allwinner,sun50i-a100-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x07081400 0x400>; - interrupts = ; - clocks = <&r_ccu CLK_R_APB2_I2C0>; - resets = <&r_ccu RST_R_APB2_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&r_i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - r_i2c1: i2c@7081800 { - compatible = "allwinner,sun50i-a100-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x07081800 0x400>; - interrupts = ; - clocks = <&r_ccu CLK_R_APB2_I2C1>; - resets = <&r_ccu RST_R_APB2_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&r_i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 0>; - }; - - ddr-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 2>; - }; - - gpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 1>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts deleted file mode 100644 index c7bd73f35..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts +++ /dev/null @@ -1,320 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2018 Amarula Solutions B.V. -// Author: Jagan Teki - -/dts-v1/; - -#include "sun50i-a64.dtsi" -#include "sun50i-a64-cpu-opp.dtsi" - -#include - -/ { - model = "Amarula A64-Relic"; - compatible = "amarula,a64-relic", "allwinner,sun50i-a64"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - i2c { - compatible = "i2c-gpio"; - sda-gpios = <&pio 4 13 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pio 4 12 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <5>; - #address-cells = <1>; - #size-cells = <0>; - - ov5640: camera@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&csi_mclk_pin>; - clocks = <&ccu CLK_CSI_MCLK>; - clock-names = "xclk"; - - AVDD-supply = <®_aldo1>; - DOVDD-supply = <®_dldo3>; - DVDD-supply = <®_eldo3>; - reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; /* CSI-RST-R: PE14 */ - powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* CSI-STBY-R: PE15 */ - - port { - ov5640_ep: endpoint { - remote-endpoint = <&csi_ep>; - bus-width = <8>; - hsync-active = <1>; /* Active high */ - vsync-active = <0>; /* Active low */ - data-active = <1>; /* Active high */ - pclk-sample = <1>; /* Rising */ - }; - }; - }; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; - clock-names = "ext_clock"; - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* WL-PMU-EN: PL2 */ - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu1 { - cpu-supply = <®_dcdc2>; -}; - -&cpu2 { - cpu-supply = <®_dcdc2>; -}; - -&cpu3 { - cpu-supply = <®_dcdc2>; -}; - -&csi { - status = "okay"; - - port { - csi_ep: endpoint { - remote-endpoint = <&ov5640_ep>; - bus-width = <8>; - hsync-active = <1>; /* Active high */ - vsync-active = <0>; /* Active low */ - data-active = <1>; /* Active high */ - pclk-sample = <1>; /* Rising */ - }; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - sensor@48 { - compatible = "st,stlm75"; - reg = <0x48>; - }; -}; - -&i2c0_pins { - bias-pull-up; -}; - -&i2c1 { - status = "okay"; - - touchscreen@5d { - compatible = "goodix,gt5663"; - reg = <0x5d>; - AVDD28-supply = <®_ldo_io0>; /* VCC-CTP: GPIO0-LDO */ - interrupt-parent = <&pio>; - interrupts = <7 4 IRQ_TYPE_EDGE_FALLING>; - irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* CTP-INT: PH4 */ - reset-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* CTP-RST: PH8 */ - touchscreen-inverted-x; - touchscreen-inverted-y; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_dcdc1>; - /* - * Schematic shows both dldo4 and eldo1 connected for vcc-io-wifi, but - * dldo4 connection shows DNP(Do Not Populate) and eldo1 connected with - * 0Ohm register to vcc-io-wifi so eldo1 is used. - */ - vqmmc-supply = <®_eldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* WL-WAKE-AP: PL3 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp803: pmic@3a3 { - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ - }; -}; - -#include "axp803.dtsi" - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "avdd-csi"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1040000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpux"; -}; - -/* DCDC3 is polyphased with DCDC2 */ - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-hdmi-dsi-sensor"; -}; - -®_dldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-mipi"; -}; - -®_dldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "dovdd-csi"; -}; - -®_dldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-io"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_eldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "cpvdd"; -}; - -®_eldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "dvdd-csi"; -}; - -®_fldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -/* - * The A64 chip cannot work without this regulator off, although - * it seems to be only driving the AR100 core. - * Maybe we don't still know well about CPUs domain. - */ -®_fldo2 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_ldo_io0 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vcc-ctp"; - status = "okay"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ - usb0_vbus-supply = <®_drivevbus>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts deleted file mode 100644 index e5e840b9f..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ /dev/null @@ -1,382 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2016 ARM Ltd. - -/dts-v1/; - -#include "sun50i-a64.dtsi" -#include "sun50i-a64-cpu-opp.dtsi" - -#include - -/ { - model = "BananaPi-M64"; - compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr-led { - label = "bananapi-m64:red:pwr"; - gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ - default-state = "on"; - }; - - green { - label = "bananapi-m64:green:user"; - gpios = <&pio 4 14 GPIO_ACTIVE_HIGH>; /* PE14 */ - }; - - blue { - label = "bananapi-m64:blue:user"; - gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */ - }; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ - clocks = <&rtc 1>; - clock-names = "ext_clock"; - }; -}; - -&codec { - status = "okay"; -}; - -&codec_analog { - cpvdd-supply = <®_eldo1>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu1 { - cpu-supply = <®_dcdc2>; -}; - -&cpu2 { - cpu-supply = <®_dcdc2>; -}; - -&cpu3 { - cpu-supply = <®_dcdc2>; -}; - -&dai { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii-id"; - phy-handle = <&ext_rgmii_phy>; - phy-supply = <®_dc1sw>; - status = "okay"; -}; - -&hdmi { - hvcc-supply = <®_dldo1>; - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c1_pins { - bias-pull-up; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - disable-wp; - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_dldo2>; - vqmmc-supply = <®_dldo4>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp803: pmic@3a3 { - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ - }; -}; - -#include "axp803.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - /* - * This regulator also drives the PE pingroup GPIOs, - * which also controls two LEDs. - */ - regulator-always-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "afvcc-csi"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dc1sw { - /* - * This regulator also indirectly drives the PD pingroup GPIOs, - * which also controls the power LED. - */ - regulator-always-on; - regulator-name = "vcc-phy"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1040000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpux"; -}; - -/* DCDC3 is polyphased with DCDC2 */ - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-hdmi-dsi"; -}; - -®_dldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_dldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-io"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_eldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "cpvdd"; -}; - -®_fldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -/* - * The A64 chip cannot work without this regulator off, although - * it seems to be only driving the AR100 core. - * Maybe we don't still know well about CPUs domain. - */ -®_fldo2 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&simplefb_hdmi { - vcc-hdmi-supply = <®_dldo1>; -}; - -&sound { - status = "okay"; - simple-audio-card,widgets = "Headphone", "Headphone Jack", - "Microphone", "Microphone Jack", - "Microphone", "Onboard Microphone"; - simple-audio-card,routing = - "Left DAC", "DACL", - "Right DAC", "DACR", - "ADCL", "Left ADC", - "ADCR", "Right ADC", - "Headphone Jack", "HP", - "MIC2", "Microphone Jack", - "Onboard Microphone", "MBIAS", - "MIC1", "Onboard Microphone"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rtc 1>; - clock-names = "lpo"; - vbat-supply = <®_dldo2>; - vddio-supply = <®_dldo4>; - device-wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ - shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ - }; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-cpu-opp.dtsi deleted file mode 100644 index e39db51eb..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-cpu-opp.dtsi +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020 Vasily khoruzhick - */ - -/ { - cpu0_opp_table: opp-table-cpu { - compatible = "operating-points-v2"; - opp-shared; - - opp-648000000 { - opp-hz = /bits/ 64 <648000000>; - opp-microvolt = <1040000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-912000000 { - opp-hz = /bits/ 64 <912000000>; - opp-microvolt = <1120000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-960000000 { - opp-hz = /bits/ 64 <960000000>; - opp-microvolt = <1160000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1200000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-microvolt = <1240000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1104000000 { - opp-hz = /bits/ 64 <1104000000>; - opp-microvolt = <1260000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1152000000 { - opp-hz = /bits/ 64 <1152000000>; - opp-microvolt = <1300000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - }; -}; - -&cpu0 { - operating-points-v2 = <&cpu0_opp_table>; -}; - -&cpu1 { - operating-points-v2 = <&cpu0_opp_table>; -}; - -&cpu2 { - operating-points-v2 = <&cpu0_opp_table>; -}; - -&cpu3 { - operating-points-v2 = <&cpu0_opp_table>; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts deleted file mode 100644 index e58db8a6c..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts +++ /dev/null @@ -1,263 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2017 Jagan Teki - -/dts-v1/; - -#include "sun50i-a64.dtsi" -#include "sun50i-a64-cpu-opp.dtsi" - -#include - -/ { - model = "FriendlyARM NanoPi A64"; - compatible = "friendlyarm,nanopi-a64", "allwinner,sun50i-a64"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "nanopi-a64:blue:status"; - gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */ - }; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; - clock-names = "ext_clock"; - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu1 { - cpu-supply = <®_dcdc2>; -}; - -&cpu2 { - cpu-supply = <®_dcdc2>; -}; - -&cpu3 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; - phy-supply = <®_dcdc1>; - status = "okay"; -}; - -&hdmi { - hvcc-supply = <®_dldo1>; - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -/* i2c1 connected with gpio headers like pine64, bananapi */ -&i2c1_pins { - bias-pull-up; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <7>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - disable-wp; - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dldo4>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - rtl8189etv: wifi@1 { - reg = <1>; - interrupt-parent = <&r_pio>; - interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp803: pmic@3a3 { - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp803.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1040000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpux"; -}; - -/* DCDC3 is polyphased with DCDC2 */ - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys"; -}; - -®_dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-hdmi-dsi"; -}; - -®_dldo4 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pg-wifi-io"; -}; - -®_eldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "cpvdd"; -}; - -®_fldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -/* - * The A64 chip cannot work without this regulator off, although - * it seems to be only driving the AR100 core. - * Maybe we don't still know well about CPUs domain. - */ -®_fldo2 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&simplefb_hdmi { - vcc-hdmi-supply = <®_dldo1>; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts deleted file mode 100644 index 577f9e1d0..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2019 Oceanic Systems (UK) Ltd. -// Copyright (C) 2019 Amarula Solutions B.V. -// Author: Jagan Teki - -/dts-v1/; - -#include "sun50i-a64-sopine.dtsi" - -/ { - model = "Oceanic 5205 5inMFD"; - compatible = "oceanic,5205-5inmfd", "allwinner,sun50i-a64"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; - phy-supply = <®_dc1sw>; - allwinner,tx-delay-ps = <600>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - touchscreen@5d { - compatible = "goodix,gt911"; - reg = <0x5d>; - AVDD28-supply = <®_ldo_io0>; /* VDD_CTP: GPIO0-LDO */ - interrupt-parent = <&pio>; - interrupts = <7 4 IRQ_TYPE_EDGE_FALLING>; - irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* CTP-INT: PH4 */ - reset-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* CTP-RST: PH11 */ - touchscreen-inverted-x; - touchscreen-inverted-y; - }; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&ohci0 { - status = "okay"; -}; - -®_dc1sw { - regulator-name = "vcc-phy"; -}; - -®_ldo_io0 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vdd-ctp"; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts deleted file mode 100644 index efb20846d..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2018 Martin Ayotte -// Copyright (C) 2019 Sunil Mohan Adapa - -#include "sun50i-a64-olinuxino.dts" - -/ { - model = "Olimex A64-Olinuxino-eMMC"; - compatible = "olimex,a64-olinuxino-emmc", "allwinner,sun50i-a64"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_eldo1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&pio { - vcc-pc-supply = <®_eldo1>; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts deleted file mode 100644 index f3f8e177a..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +++ /dev/null @@ -1,347 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2017 Jagan Teki - -/dts-v1/; - -#include "sun50i-a64.dtsi" -#include "sun50i-a64-cpu-opp.dtsi" - -#include - -/ { - model = "Olimex A64-Olinuxino"; - compatible = "olimex,a64-olinuxino", "allwinner,sun50i-a64"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "a64-olinuxino:red:user"; - gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ - }; - }; - - reg_usb1_vbus: usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 6 9 GPIO_ACTIVE_HIGH>; /* PG9 */ - status = "okay"; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu1 { - cpu-supply = <®_dcdc2>; -}; - -&cpu2 { - cpu-supply = <®_dcdc2>; -}; - -&cpu3 { - cpu-supply = <®_dcdc2>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; - phy-supply = <®_dcdc1>; - allwinner,tx-delay-ps = <600>; - status = "okay"; -}; - -&hdmi { - hvcc-supply = <®_dldo1>; - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - disable-wp; - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dldo4>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - rtl8723bs: wifi@1 { - reg = <1>; - interrupt-parent = <&r_pio>; - interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pio { - vcc-pc-supply = <®_dcdc1>; - vcc-pd-supply = <®_dcdc1>; - vcc-pe-supply = <®_aldo1>; - vcc-pg-supply = <®_dldo4>; -}; - -&r_pio { - /* - * FIXME: We can't add that supply for now since it would - * create a circular dependency between pinctrl, the regulator - * and the RSB Bus. - * - * vcc-pl-supply = <®_aldo2>; - */ -}; - -&pio { - vcc-pa-supply = <®_dcdc1>; - vcc-pb-supply = <®_dcdc1>; - vcc-pc-supply = <®_dcdc1>; - vcc-pd-supply = <®_dcdc1>; - vcc-pe-supply = <®_aldo1>; - vcc-pf-supply = <®_dcdc1>; - vcc-pg-supply = <®_dldo4>; - vcc-ph-supply = <®_dcdc1>; -}; - -&r_rsb { - status = "okay"; - - axp803: pmic@3a3 { - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ - }; -}; - -/* VCC-PL is powered by aldo2 but we cannot add it as the RSB */ -/* interface used to talk to the PMIC in on the PL pins */ -/* &r_pio { */ -/* vcc-pl-supply = <®_aldo2>; */ -/* }; */ - -#include "axp803.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vcc-pe"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1040000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpux"; -}; - -/* DCDC3 is polyphased with DCDC2 */ - -/* - * The board uses DDR3L DRAM chips. 1.36V is the closest to the nominal - * 1.35V that the PMIC can drive. - */ -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1360000>; - regulator-max-microvolt = <1360000>; - regulator-name = "vcc-ddr3"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-hdmi"; -}; - -®_dldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-mipi"; -}; - -®_dldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vcc-avdd-csi"; -}; - -®_dldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-io"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_eldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "cpvdd"; -}; - -®_eldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-dvdd-csi"; -}; - -®_fldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -/* - * The A64 chip cannot work without this regulator off, although - * it seems to be only driving the AR100 core. - * Maybe we don't still know well about CPUs domain. - */ -®_fldo2 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&simplefb_hdmi { - vcc-hdmi-supply = <®_dldo1>; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - status = "okay"; - usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ - usb0_vbus-supply = <®_drivevbus>; - usb1_vbus-supply = <®_usb1_vbus>; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts deleted file mode 100644 index 70e31743f..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +++ /dev/null @@ -1,413 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2017 Jagan Teki -// Copyright (C) 2017-2018 Samuel Holland - -/dts-v1/; - -#include "sun50i-a64.dtsi" -#include "sun50i-a64-cpu-opp.dtsi" - -#include - -/ { - model = "OrangePi Win/Win Plus"; - compatible = "xunlong,orangepi-win", "allwinner,sun50i-a64"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - status { - label = "orangepi:green:status"; - gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 3 14 GPIO_ACTIVE_HIGH>; /* PD14 */ - status = "okay"; - }; - - reg_usb1_vbus: usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - enable-active-high; - gpio = <&pio 3 7 GPIO_ACTIVE_HIGH>; /* PD7 */ - status = "okay"; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ - clocks = <&rtc 1>; - clock-names = "ext_clock"; - }; -}; - -&codec { - status = "okay"; -}; - -&codec_analog { - cpvdd-supply = <®_eldo1>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu1 { - cpu-supply = <®_dcdc2>; -}; - -&cpu2 { - cpu-supply = <®_dcdc2>; -}; - -&cpu3 { - cpu-supply = <®_dcdc2>; -}; - -&dai { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii-id"; - phy-handle = <&ext_rgmii_phy>; - phy-supply = <®_gmac_3v3>; - status = "okay"; -}; - -&hdmi { - hvcc-supply = <®_dldo1>; - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - disable-wp; - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_dldo2>; - vqmmc-supply = <®_dldo4>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */ - interrupt-names = "host-wake"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&r_ir { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp803: pmic@3a3 { - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ - }; -}; - -#include "axp803.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "afvcc-csi"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1040000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpux"; -}; - -/* DCDC3 is polyphased with DCDC2 */ - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-hdmi-dsi"; -}; - -®_dldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_dldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avdd-csi"; -}; - -®_dldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-io"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_eldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "cpvdd"; -}; - -®_eldo3 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1800000>; - regulator-name = "dvdd-csi"; -}; - -®_fldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -/* - * The A64 chip cannot work without this regulator off, although - * it seems to be only driving the AR100 core. - * Maybe we don't still know well about CPUs domain. - */ -®_fldo2 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&simplefb_hdmi { - vcc-hdmi-supply = <®_dldo1>; -}; - -&sound { - status = "okay"; - simple-audio-card,widgets = "Headphone", "Headphone Jack", - "Microphone", "Microphone Jack", - "Microphone", "Onboard Microphone"; - simple-audio-card,routing = - "Left DAC", "DACL", - "Right DAC", "DACR", - "ADCL", "Left ADC", - "ADCR", "Right ADC", - "Headphone Jack", "HP", - "MIC2", "Microphone Jack", - "Onboard Microphone", "MBIAS", - "MIC1", "Onboard Microphone"; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - compatible = "mxicy,mx25l1606e", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <80000000>; - m25p,fast-read; - status = "okay"; - }; -}; - -/* On debug connector */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -/* Bluetooth */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <1500000>; - clocks = <&rtc 1>; - clock-names = "lpo"; - vbat-supply = <®_dldo2>; - vddio-supply = <®_dldo4>; - device-wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ - shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ - }; -}; - -/* On Pi-2 connector, RTS/CTS optional */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -/* On Pi-2 connector, RTS/CTS optional */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "disabled"; -}; - -/* On Pi-2 connector (labeled for SPI1), RTS/CTS optional */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - status = "disabled"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ - usb0_vbus-supply = <®_drivevbus>; - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts deleted file mode 100644 index 358df6d92..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2018 ARM Ltd. - -#include "sun50i-a64-sopine-baseboard.dts" - -/ { - model = "Pine64 LTS"; - compatible = "pine64,pine64-lts", "allwinner,sun50i-r18", - "allwinner,sun50i-a64"; -}; - -&mmc0 { - broken-cd; /* card detect is broken on *some* boards */ -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts deleted file mode 100644 index b54099b65..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2016 ARM Ltd. - -#include "sun50i-a64-pine64.dts" - -/ { - model = "Pine64+"; - compatible = "pine64,pine64-plus", "allwinner,sun50i-a64"; - - /* TODO: Camera, touchscreen, etc. */ -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii-txid"; - phy-handle = <&ext_rgmii_phy>; - status = "okay"; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -®_dc1sw { - /* - * Ethernet PHY needs 30ms to properly power up and some more - * to initialize. 100ms should be plenty of time to finish - * whole process. - */ - regulator-enable-ramp-delay = <100000>; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts deleted file mode 100644 index 329cf2765..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +++ /dev/null @@ -1,320 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2016 ARM Ltd. - -/dts-v1/; - -#include "sun50i-a64.dtsi" -#include "sun50i-a64-cpu-opp.dtsi" - -#include - -/ { - model = "Pine64"; - compatible = "pine64,pine64", "allwinner,sun50i-a64"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; -}; - -&codec { - status = "okay"; -}; - -&codec_analog { - cpvdd-supply = <®_eldo1>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu1 { - cpu-supply = <®_dcdc2>; -}; - -&cpu2 { - cpu-supply = <®_dcdc2>; -}; - -&cpu3 { - cpu-supply = <®_dcdc2>; -}; - -&dai { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&rmii_pins>; - phy-mode = "rmii"; - phy-handle = <&ext_rmii_phy1>; - phy-supply = <®_dc1sw>; - status = "okay"; - -}; - -&hdmi { - hvcc-supply = <®_dldo1>; - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c1_pins { - bias-pull-up; -}; - -&mdio { - ext_rmii_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - disable-wp; - bus-width = <4>; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp803: pmic@3a3 { - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp803.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-phy"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1040000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpux"; -}; - -/* DCDC3 is polyphased with DCDC2 */ - -/* - * The DRAM chips used by Pine64 boards are DDR3L-compatible, so they can - * work at 1.35V with less power consumption. - * As AXP803 DCDC5 cannot reach 1.35V accurately, use 1.36V instead. - */ -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1360000>; - regulator-max-microvolt = <1360000>; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-hdmi"; -}; - -®_dldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-mipi"; -}; - -®_dldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_eldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "cpvdd"; -}; - -®_fldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -/* - * The A64 chip cannot work without this regulator off, although - * it seems to be only driving the AR100 core. - * Maybe we don't still know well about CPUs domain. - */ -®_fldo2 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&simplefb_hdmi { - vcc-hdmi-supply = <®_dldo1>; -}; - -&sound { - simple-audio-card,aux-devs = <&codec_analog>; - simple-audio-card,widgets = "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Left DAC", "DACL", - "Right DAC", "DACR", - "Headphone Jack", "HP", - "ADCL", "Left ADC", - "ADCR", "Right ADC", - "MIC2", "Microphone Jack"; - status = "okay"; -}; - -/* On Euler connector */ -&spdif { - status = "disabled"; -}; - -/* On Exp and Euler connectors */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -/* On Wifi/BT connector, with RTS/CTS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - status = "disabled"; -}; - -/* On Pi-2 connector */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -/* On Euler connector */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "disabled"; -}; - -/* On Euler connector, RTS/CTS optional */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - status = "disabled"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts deleted file mode 100644 index 7ae16541d..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ /dev/null @@ -1,416 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2017 Icenowy Zheng -// Copyright (C) 2018 Vasily Khoruzhick - -/dts-v1/; - -#include "sun50i-a64.dtsi" -#include "sun50i-a64-cpu-opp.dtsi" - -#include -#include -#include -#include - -/ { - model = "Pinebook"; - compatible = "pine64,pinebook", "allwinner,sun50i-a64"; - - aliases { - serial0 = &uart0; - ethernet0 = &rtl8723cs; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 0>; - brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>; - default-brightness-level = <2>; - enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ - power-supply = <®_vbklt>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio_keys { - compatible = "gpio-keys"; - - lid_switch { - label = "Lid Switch"; - gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */ - linux,input-type = ; - linux,code = ; - linux,can-disable; - wakeup-source; - wakeup-event-action = ; - }; - }; - - panel_edp: panel-edp { - compatible = "neweast,wjfh116008a"; - backlight = <&backlight>; - power-supply = <®_dc1sw>; - - port { - panel_edp_in: endpoint { - remote-endpoint = <&anx6345_out_edp>; - }; - }; - }; - - reg_vbklt: vbklt { - compatible = "regulator-fixed"; - regulator-name = "vbklt"; - regulator-min-microvolt = <18000000>; - regulator-max-microvolt = <18000000>; - gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - enable-active-high; - }; - - reg_vcc5v0: vcc5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ - }; - - speaker_amp: audio-amplifier { - compatible = "simple-audio-amplifier"; - VCC-supply = <®_vcc5v0>; - enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ - sound-name-prefix = "Speaker Amp"; - }; - -}; - -&codec { - status = "okay"; -}; - -&codec_analog { - cpvdd-supply = <®_eldo1>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu1 { - cpu-supply = <®_dcdc2>; -}; - -&cpu2 { - cpu-supply = <®_dcdc2>; -}; - -&cpu3 { - cpu-supply = <®_dcdc2>; -}; - -&dai { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&mixer0 { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - disable-wp; - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_dldo4>; - vqmmc-supply = <®_eldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - rtl8723cs: wifi@1 { - reg = <1>; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_eldo1>; - max-frequency = <200000000>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - mmc-hs200-1_8v; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pio { - vcc-pc-supply = <®_eldo1>; - vcc-pd-supply = <®_dcdc1>; - vcc-pe-supply = <®_aldo1>; - vcc-pg-supply = <®_eldo1>; -}; - -&pwm { - status = "okay"; -}; - -&r_i2c { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&r_i2c_pl89_pins>; - status = "okay"; - - anx6345: anx6345@38 { - compatible = "analogix,anx6345"; - reg = <0x38>; - reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */ - dvdd25-supply = <®_dldo2>; - dvdd12-supply = <®_fldo1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - anx6345_in: port@0 { - reg = <0>; - anx6345_in_tcon0: endpoint { - remote-endpoint = <&tcon0_out_anx6345>; - }; - }; - - anx6345_out: port@1 { - reg = <1>; - anx6345_out_edp: endpoint { - remote-endpoint = <&panel_edp_in>; - }; - }; - }; - }; -}; - -&r_pio { - /* - * FIXME: We can't add that supply for now since it would - * create a circular dependency between pinctrl, the regulator - * and the RSB Bus. - * - * vcc-pl-supply = <®_aldo2>; - */ -}; - -&r_rsb { - status = "okay"; - - axp803: pmic@3a3 { - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp803.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-name = "vcc-pe"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpux"; -}; - -/* DCDC3 is polyphased with DCDC2 */ - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-hdmi"; -}; - -®_dldo2 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc-edp"; -}; - -®_dldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_eldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "cpvdd"; -}; - -®_fldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -®_fldo2 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&simplefb_lcd { - panel-supply = <®_dc1sw>; - dvdd25-supply = <®_dldo2>; - dvdd12-supply = <®_fldo1>; -}; - -&simplefb_hdmi { - vcc-hdmi-supply = <®_dldo1>; -}; - -&sound { - status = "okay"; - simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; - simple-audio-card,widgets = "Microphone", "Internal Microphone Left", - "Microphone", "Internal Microphone Right", - "Headphone", "Headphone Jack", - "Speaker", "Internal Speaker"; - simple-audio-card,routing = - "Left DAC", "DACL", - "Right DAC", "DACR", - "Speaker Amp INL", "LINEOUT", - "Speaker Amp INR", "LINEOUT", - "Internal Speaker", "Speaker Amp OUTL", - "Internal Speaker", "Speaker Amp OUTR", - "Headphone Jack", "HP", - "ADCL", "Left ADC", - "ADCR", "Right ADC", - "Internal Microphone Left", "MBIAS", - "MIC1", "Internal Microphone Left", - "Internal Microphone Right", "HBIAS", - "MIC2", "Internal Microphone Right"; -}; - -&tcon0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rgb666_pins>; - - status = "okay"; -}; - -&tcon0_out { - tcon0_out_anx6345: endpoint { - remote-endpoint = <&anx6345_in_tcon0>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; -}; - -&usbphy { - usb0_vbus-supply = <®_vcc5v0>; - usb1_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts deleted file mode 100644 index 0c4227210..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2020 Ondrej Jirman - -/dts-v1/; - -#include "sun50i-a64-pinephone.dtsi" - -/ { - model = "Pine64 PinePhone Developer Batch (1.0)"; - compatible = "pine64,pinephone-1.0", "allwinner,sun50i-a64"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts deleted file mode 100644 index 3e99a87e9..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2020 Ondrej Jirman - -/dts-v1/; - -#include "sun50i-a64-pinephone.dtsi" - -/ { - model = "Pine64 PinePhone Braveheart (1.1)"; - compatible = "pine64,pinephone-1.1", "allwinner,sun50i-a64"; -}; - -&backlight { - power-supply = <®_ldo_io0>; - /* - * PWM backlight circuit on this PinePhone revision was changed since - * 1.0, and the lowest PWM duty cycle that doesn't lead to backlight - * being off is around 20%. Duty cycle for the lowest brightness level - * also varries quite a bit between individual boards, so the lowest - * value here was chosen as a safe default. - */ - brightness-levels = < - 774 793 814 842 - 882 935 1003 1088 - 1192 1316 1462 1633 - 1830 2054 2309 2596 - 2916 3271 3664 4096>; - num-interpolated-steps = <50>; - default-brightness-level = <400>; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts deleted file mode 100644 index a9f5b670c..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2020 Ondrej Jirman - -/dts-v1/; - -#include "sun50i-a64-pinephone.dtsi" - -/ { - model = "Pine64 PinePhone (1.2)"; - compatible = "pine64,pinephone-1.2", "allwinner,sun50i-a64"; -}; - -&backlight { - power-supply = <®_ldo_io0>; - /* - * PWM backlight circuit on this PinePhone revision was changed since 1.0, - * and the lowest PWM duty cycle that doesn't lead to backlight being off - * is around 10%. Duty cycle for the lowest brightness level also varries - * quite a bit between individual boards, so the lowest value here was - * chosen as a safe default. - */ - brightness-levels = < - 5000 5248 5506 5858 6345 - 6987 7805 8823 10062 11543 - 13287 15317 17654 20319 23336 - 26724 30505 34702 39335 44427 - 50000 - >; - num-interpolated-steps = <50>; - default-brightness-level = <500>; -}; - -&lis3mdl { - /* - * Board revision 1.2 fixed routing of the interrupt to DRDY pin, - * enable interrupts. - */ - interrupt-parent = <&pio>; - interrupts = <1 1 IRQ_TYPE_EDGE_RISING>; /* PB1 */ -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi deleted file mode 100644 index 5780713b0..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ /dev/null @@ -1,429 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2019 Icenowy Zheng -// Copyright (C) 2020 Martijn Braam -// Copyright (C) 2020 Ondrej Jirman - -#include "sun50i-a64.dtsi" -#include "sun50i-a64-cpu-opp.dtsi" - -#include -#include -#include -#include - -/ { - aliases { - serial0 = &uart0; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&r_pwm 0 50000 PWM_POLARITY_INVERTED>; - enable-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */ - /* Backlight configuration differs per PinePhone revision. */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - blue { - function = LED_FUNCTION_INDICATOR; - color = ; - gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ - }; - - green { - function = LED_FUNCTION_INDICATOR; - color = ; - gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */ - }; - - red { - function = LED_FUNCTION_INDICATOR; - color = ; - gpios = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */ - }; - }; - - speaker_amp: audio-amplifier { - compatible = "simple-audio-amplifier"; - enable-gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */ - sound-name-prefix = "Speaker Amp"; - }; - - vibrator { - compatible = "gpio-vibrator"; - enable-gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */ - vcc-supply = <®_dcdc1>; - }; -}; - -&codec { - status = "okay"; -}; - -&codec_analog { - cpvdd-supply = <®_eldo1>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu1 { - cpu-supply = <®_dcdc2>; -}; - -&cpu2 { - cpu-supply = <®_dcdc2>; -}; - -&cpu3 { - cpu-supply = <®_dcdc2>; -}; - -&dai { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&dphy { - status = "okay"; -}; - -&dsi { - vcc-dsi-supply = <®_dldo1>; - status = "okay"; - - panel@0 { - compatible = "xingbangda,xbd599"; - reg = <0>; - reset-gpios = <&pio 3 23 GPIO_ACTIVE_LOW>; /* PD23 */ - iovcc-supply = <®_dldo2>; - vcc-supply = <®_ldo_io0>; - backlight = <&backlight>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - touchscreen@5d { - compatible = "goodix,gt917s"; - reg = <0x5d>; - interrupt-parent = <&pio>; - interrupts = <7 4 IRQ_TYPE_LEVEL_HIGH>; /* PH4 */ - irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - reset-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ - AVDD28-supply = <®_ldo_io0>; - VDDIO-supply = <®_ldo_io0>; - touchscreen-size-x = <720>; - touchscreen-size-y = <1440>; - }; -}; - -&i2c1 { - status = "okay"; - - /* Magnetometer */ - lis3mdl: lis3mdl@1e { - compatible = "st,lis3mdl-magn"; - reg = <0x1e>; - vdd-supply = <®_dldo1>; - vddio-supply = <®_dldo1>; - }; - - /* Accelerometer/gyroscope */ - mpu6050@68 { - compatible = "invensense,mpu6050"; - reg = <0x68>; - interrupt-parent = <&pio>; - interrupts = <7 5 IRQ_TYPE_EDGE_RISING>; /* PH5 */ - vdd-supply = <®_dldo1>; - vddio-supply = <®_dldo1>; - }; -}; - -/* Connected to pogo pins (external spring based pinheader for user addons) */ -&i2c2 { - status = "okay"; -}; - -&lradc { - vref-supply = <®_aldo3>; - status = "okay"; - - button-200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button-400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - disable-wp; - bus-width = <4>; - status = "okay"; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pio { - vcc-pb-supply = <®_dcdc1>; - vcc-pc-supply = <®_dcdc1>; - vcc-pd-supply = <®_dcdc1>; - vcc-pe-supply = <®_aldo1>; - vcc-pf-supply = <®_dcdc1>; - vcc-pg-supply = <®_dldo4>; - vcc-ph-supply = <®_dcdc1>; -}; - -&r_pio { - /* - * FIXME: We can't add that supply for now since it would - * create a circular dependency between pinctrl, the regulator - * and the RSB Bus. - * - * vcc-pl-supply = <®_aldo2>; - */ -}; - -&r_pwm { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp803: pmic@3a3 { - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -#include "axp803.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "dovdd-csi"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pl"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpux"; -}; - -/* DCDC3 is polyphased with DCDC2 */ - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-dsi-sensor"; -}; - -®_dldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-mipi-io"; -}; - -®_dldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "avdd-csi"; -}; - -®_dldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-wifi-io"; -}; - -®_eldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-lpddr"; -}; - -®_eldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "dvdd-1v8-csi"; -}; - -®_fldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -®_fldo2 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_ldo_io0 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-lcd-ctp-stk"; - status = "okay"; -}; - -®_ldo_io1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-1v8-typec"; - status = "okay"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&sound { - status = "okay"; - simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; - simple-audio-card,widgets = "Microphone", "Headset Microphone", - "Microphone", "Internal Microphone", - "Headphone", "Headphone Jack", - "Speaker", "Internal Earpiece", - "Speaker", "Internal Speaker"; - simple-audio-card,routing = - "Headphone Jack", "HP", - "Internal Earpiece", "EARPIECE", - "Internal Speaker", "Speaker Amp OUTL", - "Internal Speaker", "Speaker Amp OUTR", - "Speaker Amp INL", "LINEOUT", - "Speaker Amp INR", "LINEOUT", - "Left DAC", "DACL", - "Right DAC", "DACR", - "ADCL", "Left ADC", - "ADCR", "Right ADC", - "Internal Microphone", "MBIAS", - "MIC1", "Internal Microphone", - "Headset Microphone", "HBIAS", - "MIC2", "Headset Microphone"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -/* Connected to the modem (hardware flow control can't be used) */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts deleted file mode 100644 index 0494bfaf2..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts +++ /dev/null @@ -1,457 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Icenowy Zheng - * - */ - -/dts-v1/; - -#include "sun50i-a64.dtsi" -#include "sun50i-a64-cpu-opp.dtsi" - -#include -#include -#include - -/ { - model = "PineTab"; - compatible = "pine64,pinetab", "allwinner,sun50i-a64"; - - aliases { - serial0 = &uart0; - ethernet0 = &rtl8723cs; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 16 18 20 22 24 26 29 32 35 38 42 46 51 56 62 68 75 83 91 100>; - default-brightness-level = <15>; - enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ - power-supply = <&vdd_bl>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - i2c-csi { - compatible = "i2c-gpio"; - sda-gpios = <&pio 4 13 GPIO_ACTIVE_HIGH>; /* PE13 */ - scl-gpios = <&pio 4 12 GPIO_ACTIVE_HIGH>; /* PE12 */ - i2c-gpio,delay-us = <5>; - #address-cells = <1>; - #size-cells = <0>; - - /* Rear camera */ - ov5640: camera@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&csi_mclk_pin>; - clocks = <&ccu CLK_CSI_MCLK>; - clock-names = "xclk"; - - AVDD-supply = <®_dldo3>; - DOVDD-supply = <®_aldo1>; - DVDD-supply = <®_eldo3>; - reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; /* PE14 */ - powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */ - - port { - ov5640_ep: endpoint { - remote-endpoint = <&csi_ep>; - bus-width = <8>; - hsync-active = <1>; /* Active high */ - vsync-active = <0>; /* Active low */ - data-active = <1>; /* Active high */ - pclk-sample = <1>; /* Rising */ - }; - }; - }; - }; - - speaker_amp: audio-amplifier { - compatible = "simple-audio-amplifier"; - enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ - sound-name-prefix = "Speaker Amp"; - }; - - vdd_bl: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "bl-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - enable-active-high; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ - post-power-on-delay-ms = <200>; - }; -}; - -&codec { - status = "okay"; -}; - -&codec_analog { - cpvdd-supply = <®_eldo1>; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu1 { - cpu-supply = <®_dcdc2>; -}; - -&cpu2 { - cpu-supply = <®_dcdc2>; -}; - -&cpu3 { - cpu-supply = <®_dcdc2>; -}; - -&csi { - status = "okay"; - - port { - csi_ep: endpoint { - remote-endpoint = <&ov5640_ep>; - bus-width = <8>; - hsync-active = <1>; /* Active high */ - vsync-active = <0>; /* Active low */ - data-active = <1>; /* Active high */ - pclk-sample = <1>; /* Rising */ - }; - }; -}; - -&dai { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&dphy { - status = "okay"; -}; - -&dsi { - vcc-dsi-supply = <®_dldo1>; - status = "okay"; - - panel@0 { - compatible = "feixin,k101-im2ba02"; - reg = <0>; - avdd-supply = <®_dc1sw>; - dvdd-supply = <®_dc1sw>; - cvdd-supply = <®_ldo_io1>; - reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ - backlight = <&backlight>; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - touchscreen@5d { - compatible = "goodix,gt9271"; - reg = <0x5d>; - interrupt-parent = <&pio>; - interrupts = <7 4 IRQ_TYPE_LEVEL_HIGH>; /* PH4 */ - irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - reset-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ - AVDD28-supply = <®_ldo_io1>; - }; -}; - -&i2c0_pins { - bias-pull-up; -}; - -&i2c1 { - status = "okay"; - - /* TODO: add Bochs BMA223 accelerometer here */ -}; - -&lradc { - vref-supply = <®_aldo3>; - status = "okay"; - - button-200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button-400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; -}; - -&mixer1 { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - disable-wp; - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_dldo4>; - vqmmc-supply = <®_eldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - rtl8723cs: wifi@1 { - reg = <1>; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&pwm { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp803: pmic@3a3 { - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - x-powers,drive-vbus-en; - }; -}; - -#include "axp803.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "dovdd-csi"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpux"; -}; - -/* DCDC3 is polyphased with DCDC2 */ - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys"; -}; - -®_dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-hdmi-dsi-sensor"; -}; - -®_dldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "avdd-csi"; -}; - -®_dldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - -®_eldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "cpvdd"; -}; - -®_eldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca-1v8"; -}; - -®_eldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "dvdd-1v8-csi"; -}; - -®_fldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -®_fldo2 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_ldo_io0 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-usb"; - status = "okay"; -}; - -®_ldo_io1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <3500000>; - regulator-name = "vcc-touchscreen"; - status = "okay"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&sound { - status = "okay"; - simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; - simple-audio-card,widgets = "Microphone", "Internal Microphone Left", - "Microphone", "Internal Microphone Right", - "Headphone", "Headphone Jack", - "Speaker", "Internal Speaker"; - simple-audio-card,routing = - "Left DAC", "DACL", - "Right DAC", "DACR", - "Speaker Amp INL", "LINEOUT", - "Speaker Amp INR", "LINEOUT", - "Internal Speaker", "Speaker Amp OUTL", - "Internal Speaker", "Speaker Amp OUTR", - "Headphone Jack", "HP", - "ADCL", "Left ADC", - "ADCR", "Right ADC", - "Internal Microphone Left", "MBIAS", - "MIC1", "Internal Microphone Left", - "Internal Microphone Right", "HBIAS", - "MIC2", "Internal Microphone Right"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - usb1_vbus-supply = <®_ldo_io0>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts deleted file mode 100644 index 068cbd955..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +++ /dev/null @@ -1,205 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2017 Icenowy Zheng -// Based on sun50i-a64-pine64.dts, which is: -// Copyright (c) 2016 ARM Ltd. - -/dts-v1/; - -#include "sun50i-a64-sopine.dtsi" - -/ { - model = "SoPine with baseboard"; - compatible = "pine64,sopine-baseboard", "pine64,sopine", - "allwinner,sun50i-a64"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - reg_vcc1v8: vcc1v8 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; -}; - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -&codec { - status = "okay"; -}; - -&codec_analog { - status = "okay"; -}; - -&dai { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii-txid"; - phy-handle = <&ext_rgmii_phy>; - phy-supply = <®_dc1sw>; - status = "okay"; -}; - -&hdmi { - hvcc-supply = <®_dldo1>; - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_vcc1v8>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -®_dc1sw { - /* - * Ethernet PHY needs 30ms to properly power up and some more - * to initialize. 100ms should be plenty of time to finish - * whole process. - */ - regulator-enable-ramp-delay = <100000>; - regulator-name = "vcc-phy"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-hdmi"; -}; - -®_dldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-mipi"; -}; - -®_dldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -&simplefb_hdmi { - vcc-hdmi-supply = <®_dldo1>; -}; - -&sound { - simple-audio-card,aux-devs = <&codec_analog>; - simple-audio-card,widgets = "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Left DAC", "DACL", - "Right DAC", "DACR", - "Headphone Jack", "HP", - "ADCL", "Left ADC", - "ADCR", "Right ADC", - "MIC2", "Microphone Jack"; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -/* On Pi-2 connector */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -/* On Euler connector */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "disabled"; -}; - -/* On Euler connector, RTS/CTS optional */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - status = "disabled"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi deleted file mode 100644 index df62044ff..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2017 Icenowy Zheng -// Based on sun50i-a64-pine64.dts, which is: -// Copyright (c) 2016 ARM Ltd. - -#include "sun50i-a64.dtsi" -#include "sun50i-a64-cpu-opp.dtsi" - -#include - -&codec_analog { - cpvdd-supply = <®_eldo1>; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu1 { - cpu-supply = <®_dcdc2>; -}; - -&cpu2 { - cpu-supply = <®_dcdc2>; -}; - -&cpu3 { - cpu-supply = <®_dcdc2>; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - disable-wp; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 push-pull switch */ - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp803: pmic@3a3 { - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -#include "axp803.dtsi" - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1040000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpux"; -}; - -/* DCDC3 is polyphased with DCDC2 */ - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dram"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys"; -}; - -®_eldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vdd-1v8-lpddr"; -}; - -®_fldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -/* - * The A64 chip cannot work without this regulator off, although - * it seems to be only driving the AR100 core. - * Maybe we don't still know well about CPUs domain. - */ -®_fldo2 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts deleted file mode 100644 index a1864a89f..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts +++ /dev/null @@ -1,382 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// Copyright (C) Harald Geyer -// based on sun50i-a64-olinuxino.dts by Jagan Teki - -/dts-v1/; - -#include "sun50i-a64.dtsi" -#include "sun50i-a64-cpu-opp.dtsi" - -#include -#include -#include - -/ { - model = "Olimex A64 Teres-I"; - compatible = "olimex,a64-teres-i", "allwinner,sun50i-a64"; - - aliases { - serial0 = &uart0; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 0>; - power-supply = <®_dcdc1>; - brightness-levels = <0 5 7 10 14 20 28 40 56 80 112>; - default-brightness-level = <5>; - enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - - framebuffer-lcd { - eDP25-supply = <®_dldo2>; - eDP12-supply = <®_dldo3>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - lid-switch { - label = "Lid Switch"; - gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ - linux,input-type = ; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - - capslock { - label = "teres-i:green:capslock"; - gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */ - }; - - numlock { - label = "teres-i:green:numlock"; - gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */ - }; - }; - - reg_usb1_vbus: usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ - status = "okay"; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ - }; - - speaker_amp: audio-amplifier { - compatible = "simple-audio-amplifier"; - enable-gpios = <&r_pio 0 12 GPIO_ACTIVE_HIGH>; /* PL12 */ - sound-name-prefix = "Speaker Amp"; - }; -}; - -&codec { - status = "okay"; -}; - -&codec_analog { - cpvdd-supply = <®_eldo1>; - status = "okay"; -}; - -&dai { - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&cpu1 { - cpu-supply = <®_dcdc2>; -}; - -&cpu2 { - cpu-supply = <®_dcdc2>; -}; - -&cpu3 { - cpu-supply = <®_dcdc2>; -}; - -&ehci1 { - status = "okay"; -}; - - -&i2c0 { - clock-frequency = <100000>; - status = "okay"; - - anx6345: anx6345@38 { - compatible = "analogix,anx6345"; - reg = <0x38>; - reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */ - dvdd25-supply = <®_dldo2>; - dvdd12-supply = <®_dldo3>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - anx6345_in: endpoint { - remote-endpoint = <&tcon0_out_anx6345>; - }; - }; - }; - }; -}; - -&mixer0 { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - disable-wp; - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_aldo2>; - vqmmc-supply = <®_dldo4>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - rtl8723bs: wifi@1 { - reg = <1>; - interrupt-parent = <&r_pio>; - interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <®_dcdc1>; - vqmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pwm { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp803: pmic@3a3 { - compatible = "x-powers,axp803"; - reg = <0x3a3>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - wakeup-source; - }; -}; - -#include "axp803.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vcc-pe"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1040000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd-cpux"; -}; - -/* DCDC3 is polyphased with DCDC2 */ - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-ddr3"; -}; - -®_dcdc6 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-hdmi"; -}; - -®_dldo2 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc-pd"; -}; - -®_dldo3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vdd-edp"; -}; - -®_dldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-io"; -}; - -®_eldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "cpvdd"; -}; - -®_eldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-dvdd-csi"; -}; - -®_fldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-1v2-hsic"; -}; - -/* - * The A64 chip cannot work with this regulator off, although - * it seems to be only driving the AR100 core. - * Maybe we don't still know well about CPUs domain. - */ -®_fldo2 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&simplefb_hdmi { - vcc-hdmi-supply = <®_dldo1>; -}; - -&sound { - simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>; - simple-audio-card,widgets = "Headphone", "Headphone Jack", - "Microphone", "Headset Microphone", - "Microphone", "Internal Microphone", - "Speaker", "Internal Speaker"; - simple-audio-card,routing = - "Left DAC", "DACL", - "Right DAC", "DACR", - "ADCL", "Left ADC", - "ADCR", "Right ADC", - "Headphone Jack", "HP", - "Speaker Amp INL", "LINEOUT", - "Speaker Amp INR", "LINEOUT", - "Internal Speaker", "Speaker Amp OUTL", - "Internal Speaker", "Speaker Amp OUTR", - "Internal Microphone", "MBIAS", - "MIC1", "Internal Microphone", - "Headset Microphone", "HBIAS", - "MIC2", "Headset Microphone"; - status = "okay"; -}; - -&tcon0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rgb666_pins>; - - status = "okay"; -}; - -&tcon0_out { - tcon0_out_anx6345: endpoint@0 { - reg = <0>; - remote-endpoint = <&anx6345_in>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pb_pins>; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi deleted file mode 100644 index 7a41015a9..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ /dev/null @@ -1,1319 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2016 ARM Ltd. -// based on the Allwinner H3 dtsi: -// Copyright (C) 2015 Jens Kuske - -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - simplefb_lcd: framebuffer-lcd { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "mixer0-lcd0"; - clocks = <&ccu CLK_TCON0>, - <&display_clocks CLK_MIXER0>; - status = "disabled"; - }; - - simplefb_hdmi: framebuffer-hdmi { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "mixer1-lcd1-hdmi"; - clocks = <&display_clocks CLK_MIXER1>, - <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; - status = "disabled"; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0>; - enable-method = "psci"; - next-level-cache = <&L2>; - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <1>; - enable-method = "psci"; - next-level-cache = <&L2>; - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <2>; - enable-method = "psci"; - next-level-cache = <&L2>; - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <3>; - enable-method = "psci"; - next-level-cache = <&L2>; - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - #cooling-cells = <2>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - de: display-engine { - compatible = "allwinner,sun50i-a64-display-engine"; - allwinner,pipelines = <&mixer0>, - <&mixer1>; - status = "disabled"; - }; - - osc24M: osc24M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc32k: osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "ext-osc32k"; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - sound: sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "sun50i-a64-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&cpudai>; - simple-audio-card,bitclock-master = <&cpudai>; - simple-audio-card,mclk-fs = <128>; - simple-audio-card,aux-devs = <&codec_analog>; - simple-audio-card,routing = - "Left DAC", "DACL", - "Right DAC", "DACR", - "ADCL", "Left ADC", - "ADCR", "Right ADC"; - status = "disabled"; - - cpudai: simple-audio-card,cpu { - sound-dai = <&dai>; - }; - - link_codec: simple-audio-card,codec { - sound-dai = <&codec>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - allwinner,erratum-unknown1; - arm,no-tick-in-suspend; - interrupts = , - , - , - ; - }; - - thermal-zones { - cpu_thermal: cpu0-thermal { - /* milliseconds */ - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 0>; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - cpu_alert0: cpu_alert0 { - /* milliCelsius */ - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_alert1: cpu_alert1 { - /* milliCelsius */ - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_crit: cpu_crit { - /* milliCelsius */ - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - gpu0_thermal: gpu0-thermal { - /* milliseconds */ - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 1>; - }; - - gpu1_thermal: gpu1-thermal { - /* milliseconds */ - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 2>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - bus@1000000 { - compatible = "allwinner,sun50i-a64-de2"; - reg = <0x1000000 0x400000>; - allwinner,sram = <&de2_sram 1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1000000 0x400000>; - - display_clocks: clock@0 { - compatible = "allwinner,sun50i-a64-de2-clk"; - reg = <0x0 0x10000>; - clocks = <&ccu CLK_BUS_DE>, - <&ccu CLK_DE>; - clock-names = "bus", - "mod"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - rotate: rotate@20000 { - compatible = "allwinner,sun50i-a64-de2-rotate", - "allwinner,sun8i-a83t-de2-rotate"; - reg = <0x20000 0x10000>; - interrupts = ; - clocks = <&display_clocks CLK_BUS_ROT>, - <&display_clocks CLK_ROT>; - clock-names = "bus", - "mod"; - resets = <&display_clocks RST_ROT>; - }; - - mixer0: mixer@100000 { - compatible = "allwinner,sun50i-a64-de2-mixer-0"; - reg = <0x100000 0x100000>; - clocks = <&display_clocks CLK_BUS_MIXER0>, - <&display_clocks CLK_MIXER0>; - clock-names = "bus", - "mod"; - resets = <&display_clocks RST_MIXER0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mixer0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - mixer0_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_mixer0>; - }; - - mixer0_out_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_in_mixer0>; - }; - }; - }; - }; - - mixer1: mixer@200000 { - compatible = "allwinner,sun50i-a64-de2-mixer-1"; - reg = <0x200000 0x100000>; - clocks = <&display_clocks CLK_BUS_MIXER1>, - <&display_clocks CLK_MIXER1>; - clock-names = "bus", - "mod"; - resets = <&display_clocks RST_MIXER1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mixer1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - mixer1_out_tcon0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon0_in_mixer1>; - }; - - mixer1_out_tcon1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon1_in_mixer1>; - }; - }; - }; - }; - }; - - syscon: syscon@1c00000 { - compatible = "allwinner,sun50i-a64-system-control"; - reg = <0x01c00000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_c: sram@18000 { - compatible = "mmio-sram"; - reg = <0x00018000 0x28000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00018000 0x28000>; - - de2_sram: sram-section@0 { - compatible = "allwinner,sun50i-a64-sram-c"; - reg = <0x0000 0x28000>; - }; - }; - - sram_c1: sram@1d00000 { - compatible = "mmio-sram"; - reg = <0x01d00000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x01d00000 0x40000>; - - ve_sram: sram-section@0 { - compatible = "allwinner,sun50i-a64-sram-c1", - "allwinner,sun4i-a10-sram-c1"; - reg = <0x000000 0x40000>; - }; - }; - }; - - dma: dma-controller@1c02000 { - compatible = "allwinner,sun50i-a64-dma"; - reg = <0x01c02000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DMA>; - dma-channels = <8>; - dma-requests = <27>; - resets = <&ccu RST_BUS_DMA>; - #dma-cells = <1>; - }; - - tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun50i-a64-tcon-lcd", - "allwinner,sun8i-a83t-tcon-lcd"; - reg = <0x01c0c000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; - clock-names = "ahb", "tcon-ch0"; - clock-output-names = "tcon-pixel-clock"; - #clock-cells = <0>; - resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; - reset-names = "lcd", "lvds"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon0_in_mixer0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mixer0_out_tcon0>; - }; - - tcon0_in_mixer1: endpoint@1 { - reg = <1>; - remote-endpoint = <&mixer1_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon0_out_dsi: endpoint@1 { - reg = <1>; - remote-endpoint = <&dsi_in_tcon0>; - allwinner,tcon-channel = <1>; - }; - }; - }; - }; - - tcon1: lcd-controller@1c0d000 { - compatible = "allwinner,sun50i-a64-tcon-tv", - "allwinner,sun8i-a83t-tcon-tv"; - reg = <0x01c0d000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; - clock-names = "ahb", "tcon-ch1"; - resets = <&ccu RST_BUS_TCON1>; - reset-names = "lcd"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon1_in_mixer0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mixer0_out_tcon1>; - }; - - tcon1_in_mixer1: endpoint@1 { - reg = <1>; - remote-endpoint = <&mixer1_out_tcon1>; - }; - }; - - tcon1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon1_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint = <&hdmi_in_tcon1>; - }; - }; - }; - }; - - video-codec@1c0e000 { - compatible = "allwinner,sun50i-a64-video-engine"; - reg = <0x01c0e000 0x1000>; - clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, - <&ccu CLK_DRAM_VE>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_BUS_VE>; - interrupts = ; - allwinner,sram = <&ve_sram 1>; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun50i-a64-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - interrupts = ; - max-frequency = <150000000>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun50i-a64-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = ; - max-frequency = <150000000>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun50i-a64-emmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - interrupts = ; - max-frequency = <150000000>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - sid: eeprom@1c14000 { - compatible = "allwinner,sun50i-a64-sid"; - reg = <0x1c14000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - - ths_calibration: thermal-sensor-calibration@34 { - reg = <0x34 0x8>; - }; - }; - - crypto: crypto@1c15000 { - compatible = "allwinner,sun50i-a64-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_CE>; - }; - - msgbox: mailbox@1c17000 { - compatible = "allwinner,sun50i-a64-msgbox", - "allwinner,sun6i-a31-msgbox"; - reg = <0x01c17000 0x1000>; - clocks = <&ccu CLK_BUS_MSGBOX>; - resets = <&ccu RST_BUS_MSGBOX>; - interrupts = ; - #mbox-cells = <1>; - }; - - usb_otg: usb@1c19000 { - compatible = "allwinner,sun8i-a33-musb"; - reg = <0x01c19000 0x0400>; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - interrupts = ; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - dr_mode = "otg"; - status = "disabled"; - }; - - usbphy: phy@1c19400 { - compatible = "allwinner,sun50i-a64-usb-phy"; - reg = <0x01c19400 0x14>, - <0x01c1a800 0x4>, - <0x01c1b800 0x4>; - reg-names = "phy_ctrl", - "pmu0", - "pmu1"; - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY1>; - clock-names = "usb0_phy", - "usb1_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>; - reset-names = "usb0_reset", - "usb1_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci0: usb@1c1a000 { - compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; - reg = <0x01c1a000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_BUS_EHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_OHCI0>, - <&ccu RST_BUS_EHCI0>; - phys = <&usbphy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@1c1a400 { - compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; - reg = <0x01c1a400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_OHCI0>; - phys = <&usbphy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci1: usb@1c1b000 { - compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; - reg = <0x01c1b000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_BUS_EHCI1>, - <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_BUS_OHCI1>, - <&ccu RST_BUS_EHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@1c1b400 { - compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; - reg = <0x01c1b400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_BUS_OHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ccu: clock@1c20000 { - compatible = "allwinner,sun50i-a64-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc 0>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pio: pinctrl@1c20800 { - compatible = "allwinner,sun50i-a64-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = , - , - ; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - csi_pins: csi-pins { - pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", - "PE7", "PE8", "PE9", "PE10", "PE11"; - function = "csi"; - }; - - /omit-if-no-ref/ - csi_mclk_pin: csi-mclk-pin { - pins = "PE1"; - function = "csi"; - }; - - i2c0_pins: i2c0-pins { - pins = "PH0", "PH1"; - function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - pins = "PH2", "PH3"; - function = "i2c1"; - }; - - i2c2_pins: i2c2-pins { - pins = "PE14", "PE15"; - function = "i2c2"; - }; - - /omit-if-no-ref/ - lcd_rgb666_pins: lcd-rgb666-pins { - pins = "PD0", "PD1", "PD2", "PD3", "PD4", - "PD5", "PD6", "PD7", "PD8", "PD9", - "PD10", "PD11", "PD12", "PD13", - "PD14", "PD15", "PD16", "PD17", - "PD18", "PD19", "PD20", "PD21"; - function = "lcd0"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc1_pins: mmc1-pins { - pins = "PG0", "PG1", "PG2", "PG3", - "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_pins: mmc2-pins { - pins = "PC5", "PC6", "PC8", "PC9", - "PC10","PC11", "PC12", "PC13", - "PC14", "PC15", "PC16"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_ds_pin: mmc2-ds-pin { - pins = "PC1"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - pwm_pin: pwm-pin { - pins = "PD22"; - function = "pwm"; - }; - - rmii_pins: rmii-pins { - pins = "PD10", "PD11", "PD13", "PD14", "PD17", - "PD18", "PD19", "PD20", "PD22", "PD23"; - function = "emac"; - drive-strength = <40>; - }; - - rgmii_pins: rgmii-pins { - pins = "PD8", "PD9", "PD10", "PD11", "PD12", - "PD13", "PD15", "PD16", "PD17", "PD18", - "PD19", "PD20", "PD21", "PD22", "PD23"; - function = "emac"; - drive-strength = <40>; - }; - - spdif_tx_pin: spdif-tx-pin { - pins = "PH8"; - function = "spdif"; - }; - - spi0_pins: spi0-pins { - pins = "PC0", "PC1", "PC2", "PC3"; - function = "spi0"; - }; - - spi1_pins: spi1-pins { - pins = "PD0", "PD1", "PD2", "PD3"; - function = "spi1"; - }; - - uart0_pb_pins: uart0-pb-pins { - pins = "PB8", "PB9"; - function = "uart0"; - }; - - uart1_pins: uart1-pins { - pins = "PG6", "PG7"; - function = "uart1"; - }; - - uart1_rts_cts_pins: uart1-rts-cts-pins { - pins = "PG8", "PG9"; - function = "uart1"; - }; - - uart2_pins: uart2-pins { - pins = "PB0", "PB1"; - function = "uart2"; - }; - - uart3_pins: uart3-pins { - pins = "PD0", "PD1"; - function = "uart3"; - }; - - uart4_pins: uart4-pins { - pins = "PD2", "PD3"; - function = "uart4"; - }; - - uart4_rts_cts_pins: uart4-rts-cts-pins { - pins = "PD4", "PD5"; - function = "uart4"; - }; - }; - - spdif: spdif@1c21000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun50i-a64-spdif", - "allwinner,sun8i-h3-spdif"; - reg = <0x01c21000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; - resets = <&ccu RST_BUS_SPDIF>; - clock-names = "apb", "spdif"; - dmas = <&dma 2>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "disabled"; - }; - - lradc: lradc@1c21800 { - compatible = "allwinner,sun50i-a64-lradc", - "allwinner,sun8i-a83t-r-lradc"; - reg = <0x01c21800 0x400>; - interrupts = ; - status = "disabled"; - }; - - i2s0: i2s@1c22000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun50i-a64-i2s", - "allwinner,sun8i-h3-i2s"; - reg = <0x01c22000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; - clock-names = "apb", "mod"; - resets = <&ccu RST_BUS_I2S0>; - dma-names = "rx", "tx"; - dmas = <&dma 3>, <&dma 3>; - status = "disabled"; - }; - - i2s1: i2s@1c22400 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun50i-a64-i2s", - "allwinner,sun8i-h3-i2s"; - reg = <0x01c22400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; - clock-names = "apb", "mod"; - resets = <&ccu RST_BUS_I2S1>; - dma-names = "rx", "tx"; - dmas = <&dma 4>, <&dma 4>; - status = "disabled"; - }; - - dai: dai@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun50i-a64-codec-i2s"; - reg = <0x01c22c00 0x200>; - interrupts = ; - clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; - clock-names = "apb", "mod"; - resets = <&ccu RST_BUS_CODEC>; - dmas = <&dma 15>, <&dma 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - codec: codec@1c22e00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun50i-a64-codec", - "allwinner,sun8i-a33-codec"; - reg = <0x01c22e00 0x600>; - interrupts = ; - clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; - clock-names = "bus", "mod"; - status = "disabled"; - }; - - ths: thermal-sensor@1c25000 { - compatible = "allwinner,sun50i-a64-ths"; - reg = <0x01c25000 0x100>; - clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; - clock-names = "bus", "mod"; - interrupts = ; - resets = <&ccu RST_BUS_THS>; - nvmem-cells = <&ths_calibration>; - nvmem-cell-names = "calibration"; - #thermal-sensor-cells = <1>; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - status = "disabled"; - }; - - uart3: serial@1c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - resets = <&ccu RST_BUS_UART3>; - status = "disabled"; - }; - - uart4: serial@1c29000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c29000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART4>; - resets = <&ccu RST_BUS_UART4>; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@1c2b400 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@1c68000 { - compatible = "allwinner,sun8i-h3-spi"; - reg = <0x01c68000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma 23>, <&dma 23>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - resets = <&ccu RST_BUS_SPI0>; - status = "disabled"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@1c69000 { - compatible = "allwinner,sun8i-h3-spi"; - reg = <0x01c69000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - dmas = <&dma 24>, <&dma 24>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - resets = <&ccu RST_BUS_SPI1>; - status = "disabled"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - emac: ethernet@1c30000 { - compatible = "allwinner,sun50i-a64-emac"; - syscon = <&syscon>; - reg = <0x01c30000 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - resets = <&ccu RST_BUS_EMAC>; - reset-names = "stmmaceth"; - clocks = <&ccu CLK_BUS_EMAC>; - clock-names = "stmmaceth"; - status = "disabled"; - - mdio: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - mali: gpu@1c40000 { - compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; - reg = <0x01c40000 0x10000>; - interrupts = , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pmu"; - clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; - clock-names = "bus", "core"; - resets = <&ccu RST_BUS_GPU>; - }; - - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x2000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - - pwm: pwm@1c21400 { - compatible = "allwinner,sun50i-a64-pwm", - "allwinner,sun5i-a13-pwm"; - reg = <0x01c21400 0x400>; - clocks = <&osc24M>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - mbus: dram-controller@1c62000 { - compatible = "allwinner,sun50i-a64-mbus"; - reg = <0x01c62000 0x1000>; - clocks = <&ccu 112>; - #address-cells = <1>; - #size-cells = <1>; - dma-ranges = <0x00000000 0x40000000 0xc0000000>; - #interconnect-cells = <1>; - }; - - csi: csi@1cb0000 { - compatible = "allwinner,sun50i-a64-csi"; - reg = <0x01cb0000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_CSI>, - <&ccu CLK_CSI_SCLK>, - <&ccu CLK_DRAM_CSI>; - clock-names = "bus", "mod", "ram"; - resets = <&ccu RST_BUS_CSI>; - pinctrl-names = "default"; - pinctrl-0 = <&csi_pins>; - status = "disabled"; - }; - - dsi: dsi@1ca0000 { - compatible = "allwinner,sun50i-a64-mipi-dsi"; - reg = <0x01ca0000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_MIPI_DSI>; - resets = <&ccu RST_BUS_MIPI_DSI>; - phys = <&dphy>; - phy-names = "dphy"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - - port { - dsi_in_tcon0: endpoint { - remote-endpoint = <&tcon0_out_dsi>; - }; - }; - }; - - dphy: d-phy@1ca1000 { - compatible = "allwinner,sun50i-a64-mipi-dphy", - "allwinner,sun6i-a31-mipi-dphy"; - reg = <0x01ca1000 0x1000>; - clocks = <&ccu CLK_BUS_MIPI_DSI>, - <&ccu CLK_DSI_DPHY>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_MIPI_DSI>; - status = "disabled"; - #phy-cells = <0>; - }; - - deinterlace: deinterlace@1e00000 { - compatible = "allwinner,sun50i-a64-deinterlace", - "allwinner,sun8i-h3-deinterlace"; - reg = <0x01e00000 0x20000>; - clocks = <&ccu CLK_BUS_DEINTERLACE>, - <&ccu CLK_DEINTERLACE>, - <&ccu CLK_DRAM_DEINTERLACE>; - clock-names = "bus", "mod", "ram"; - resets = <&ccu RST_BUS_DEINTERLACE>; - interrupts = ; - interconnects = <&mbus 9>; - interconnect-names = "dma-mem"; - }; - - hdmi: hdmi@1ee0000 { - compatible = "allwinner,sun50i-a64-dw-hdmi", - "allwinner,sun8i-a83t-dw-hdmi"; - reg = <0x01ee0000 0x10000>; - reg-io-width = <1>; - interrupts = ; - clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu CLK_HDMI>; - clock-names = "iahb", "isfr", "tmds"; - resets = <&ccu RST_BUS_HDMI1>; - reset-names = "ctrl"; - phys = <&hdmi_phy>; - phy-names = "phy"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - reg = <0>; - - hdmi_in_tcon1: endpoint { - remote-endpoint = <&tcon1_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - hdmi_phy: hdmi-phy@1ef0000 { - compatible = "allwinner,sun50i-a64-hdmi-phy"; - reg = <0x01ef0000 0x10000>; - clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, - <&ccu CLK_PLL_VIDEO0>; - clock-names = "bus", "mod", "pll-0"; - resets = <&ccu RST_BUS_HDMI0>; - reset-names = "phy"; - #phy-cells = <0>; - }; - - rtc: rtc@1f00000 { - compatible = "allwinner,sun50i-a64-rtc", - "allwinner,sun8i-h3-rtc"; - reg = <0x01f00000 0x400>; - interrupts = , - ; - clock-output-names = "osc32k", "osc32k-out", "iosc"; - clocks = <&osc32k>; - #clock-cells = <1>; - }; - - r_intc: interrupt-controller@1f00c00 { - compatible = "allwinner,sun50i-a64-r-intc", - "allwinner,sun6i-a31-r-intc"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x01f00c00 0x400>; - interrupts = ; - }; - - r_ccu: clock@1f01400 { - compatible = "allwinner,sun50i-a64-r-ccu"; - reg = <0x01f01400 0x100>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, - <&ccu CLK_PLL_PERIPH0>; - clock-names = "hosc", "losc", "iosc", "pll-periph"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - codec_analog: codec-analog@1f015c0 { - compatible = "allwinner,sun50i-a64-codec-analog"; - reg = <0x01f015c0 0x4>; - status = "disabled"; - }; - - r_i2c: i2c@1f02400 { - compatible = "allwinner,sun50i-a64-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x01f02400 0x400>; - interrupts = ; - clocks = <&r_ccu CLK_APB0_I2C>; - resets = <&r_ccu RST_APB0_I2C>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - r_ir: ir@1f02000 { - compatible = "allwinner,sun50i-a64-ir", - "allwinner,sun6i-a31-ir"; - reg = <0x01f02000 0x400>; - clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; - clock-names = "apb", "ir"; - resets = <&r_ccu RST_APB0_IR>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "disabled"; - }; - - r_pwm: pwm@1f03800 { - compatible = "allwinner,sun50i-a64-pwm", - "allwinner,sun5i-a13-pwm"; - reg = <0x01f03800 0x400>; - clocks = <&osc24M>; - pinctrl-names = "default"; - pinctrl-0 = <&r_pwm_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - r_pio: pinctrl@1f02c00 { - compatible = "allwinner,sun50i-a64-r-pinctrl"; - reg = <0x01f02c00 0x400>; - interrupts = ; - clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - r_i2c_pl89_pins: r-i2c-pl89-pins { - pins = "PL8", "PL9"; - function = "s_i2c"; - }; - - r_ir_rx_pin: r-ir-rx-pin { - pins = "PL11"; - function = "s_cir_rx"; - }; - - r_pwm_pin: r-pwm-pin { - pins = "PL10"; - function = "s_pwm"; - }; - - r_rsb_pins: r-rsb-pins { - pins = "PL0", "PL1"; - function = "s_rsb"; - }; - }; - - r_rsb: rsb@1f03400 { - compatible = "allwinner,sun8i-a23-rsb"; - reg = <0x01f03400 0x400>; - interrupts = ; - clocks = <&r_ccu 6>; - clock-frequency = <3000000>; - resets = <&r_ccu 2>; - pinctrl-names = "default"; - pinctrl-0 = <&r_rsb_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - wdt0: watchdog@1c20ca0 { - compatible = "allwinner,sun50i-a64-wdt", - "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = ; - clocks = <&osc24M>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts deleted file mode 100644 index 8857a3791..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2018 Chen-Yu Tsai - -/dts-v1/; -#include "sun50i-h5.dtsi" -#include "sun50i-h5-cpu-opp.dtsi" -#include - -/ { - model = "Banana Pi BPI-M2-Plus v1.2 H5"; - compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun50i-h5"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts deleted file mode 100644 index 77661006d..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2018 Chen-Yu Tsai - -/dts-v1/; -#include "sun50i-h5.dtsi" -#include - -/ { - model = "Banana Pi BPI-M2-Plus H5"; - compatible = "sinovoip,bpi-m2-plus", "allwinner,sun50i-h5"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi deleted file mode 100644 index 1afad8b43..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2020 Chen-Yu Tsai - -/ { - cpu_opp_table: opp-table-cpu { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <1000000 1000000 1310000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-648000000 { - opp-hz = /bits/ 64 <648000000>; - opp-microvolt = <1040000 1040000 1310000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1080000 1080000 1310000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-912000000 { - opp-hz = /bits/ 64 <912000000>; - opp-microvolt = <1120000 1120000 1310000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-960000000 { - opp-hz = /bits/ 64 <960000000>; - opp-microvolt = <1160000 1160000 1310000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1200000 1200000 1310000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-microvolt = <1240000 1240000 1310000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1104000000 { - opp-hz = /bits/ 64 <1104000000>; - opp-microvolt = <1260000 1260000 1310000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - - opp-1152000000 { - opp-hz = /bits/ 64 <1152000000>; - opp-microvolt = <1300000 1300000 1310000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - }; - }; -}; - -&cpu0 { - operating-points-v2 = <&cpu_opp_table>; -}; - -&cpu1 { - operating-points-v2 = <&cpu_opp_table>; -}; - -&cpu2 { - operating-points-v2 = <&cpu_opp_table>; -}; - -&cpu3 { - operating-points-v2 = <&cpu_opp_table>; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts deleted file mode 100644 index 076a0b983..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -// Copyright (C) 2018 Aleksandr Aleksandrov - -/* - * DTS for Emlid Neutis N5 Dev board. - */ - -/dts-v1/; - -#include "sun50i-h5-emlid-neutis-n5.dtsi" - -/ { - model = "Emlid Neutis N5 Developer board"; - compatible = "emlid,neutis-n5-devboard", - "emlid,neutis-n5", - "allwinner,sun50i-h5"; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - vdd_cpux: gpio-regulator { - compatible = "regulator-gpio"; - regulator-name = "vdd-cpux"; - regulator-type = "voltage"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-ramp-delay = <50>; /* 4ms */ - gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ - gpios-states = <0x1>; - states = <1100000 0>, <1300000 1>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_cpux>; -}; - -&codec { - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - allwinner,leds-active-low; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&i2c1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi deleted file mode 100644 index fc5700114..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -// Copyright (C) 2018 Aleksandr Aleksandrov - -/* - * DTSI for Emlid Neutis N5 SoM. - */ - -/dts-v1/; - -#include "sun50i-h5.dtsi" -#include diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts deleted file mode 100644 index d811df332..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2018 BayLibre, SAS -// Author: Neil Armstrong - -/dts-v1/; -#include "sun50i-h5.dtsi" -#include "sun50i-h5-cpu-opp.dtsi" -#include - -/ { - model = "Libre Computer Board ALL-H3-CC H5"; - compatible = "libretech,all-h3-cc-h5", "allwinner,sun50i-h5"; -}; - -&mmc2 { - mmc-ddr-3_3v; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts deleted file mode 100644 index e59d68b52..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h3-it.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2019 Chen-Yu Tsai - -/dts-v1/; -#include "sun50i-h5.dtsi" -#include - -/ { - model = "Libre Computer Board ALL-H3-IT H5"; - compatible = "libretech,all-h3-it-h5", "allwinner,sun50i-h5"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h5-cc.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h5-cc.dts deleted file mode 100644 index 6e30a564c..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h5-cc.dts +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2020 Chen-Yu Tsai - -#include "sun50i-h5-libretech-all-h3-cc.dts" - -/ { - model = "Libre Computer Board ALL-H5-CC H5"; - compatible = "libretech,all-h5-cc-h5", "allwinner,sun50i-h5"; - - aliases { - spi0 = &spi0; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <5000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; - vin-supply = <®_vcc5v0>; - }; -}; - -&codec { - /* No line out; only onboard microphone */ - allwinner,audio-routing = - "MIC1", "Mic", - "Mic", "MBIAS"; -}; - -/* This board has external PHY */ -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii-id"; - /delete-property/ allwinner,leds-active-low; - status = "okay"; -}; - -&external_mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - }; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts deleted file mode 100644 index 9d93fe153..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts +++ /dev/null @@ -1,163 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2017 Antony Antony -// Copyright (C) 2016 ARM Ltd. - -/dts-v1/; -#include "sun50i-h5.dtsi" - -#include -#include -#include - -/ { - model = "FriendlyARM NanoPi NEO Plus2"; - compatible = "friendlyarm,nanopi-neo-plus2", "allwinner,sun50i-h5"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - pwr { - label = "nanopi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - status { - label = "nanopi:red:status"; - gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_cpux: gpio-regulator { - compatible = "regulator-gpio"; - regulator-name = "vdd-cpux"; - regulator-type = "voltage"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-ramp-delay = <50>; /* 4ms */ - gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; - gpios-states = <0x1>; - states = <1100000 0>, <1300000 1>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ - post-power-on-delay-ms = <200>; - }; -}; - -&codec { - allwinner,audio-routing = - "Line Out", "LINEOUT", - "MIC1", "Mic", - "Mic", "MBIAS"; - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&external_mdio { - ext_rgmii_phy: ethernet-phy@7 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <7>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - /* USB Type-A ports' VBUS is always on */ - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts deleted file mode 100644 index e8ab8c2df..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts +++ /dev/null @@ -1,120 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2017 Icenowy Zheng - -/dts-v1/; -#include "sun50i-h5.dtsi" - -#include - -/ { - model = "FriendlyARM NanoPi NEO 2"; - compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - pwr { - label = "nanopi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - status { - label = "nanopi:blue:status"; - gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usb0_vbus: usb0-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ - status = "okay"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&external_mdio { - ext_rgmii_phy: ethernet-phy@7 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <7>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - /* USB Type-A port's VBUS is always on */ - usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - usb0_vbus-supply = <®_usb0_vbus>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts deleted file mode 100644 index 8bf2db9dc..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2016 ARM Ltd. - -/dts-v1/; -#include "sun50i-h5.dtsi" - -#include -#include -#include - -/ { - model = "Xunlong Orange Pi PC 2"; - compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5"; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr { - label = "orangepi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - status { - label = "orangepi:red:status"; - gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>; - }; - }; - - r-gpio-keys { - compatible = "gpio-keys"; - - sw4 { - label = "sw4"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; - }; - - reg_usb0_vbus: usb0-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ - status = "okay"; - }; -}; - -&codec { - allwinner,audio-routing = - "Line Out", "LINEOUT", - "MIC1", "Mic", - "Mic", "MBIAS"; - status = "okay"; -}; - -&cpu0 { - cpu-supply = <®_vdd_cpux>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&external_mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&r_i2c { - status = "okay"; - - reg_vdd_cpux: regulator@65 { - compatible = "silergy,sy8106a"; - reg = <0x65>; - regulator-name = "vdd-cpux"; - silergy,fixed-microvolt = <1100000>; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-ramp-delay = <200>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - /* USB Type-A ports' VBUS is always on */ - usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - usb0_vbus-supply = <®_usb0_vbus>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts deleted file mode 100644 index 33ab44072..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts +++ /dev/null @@ -1,213 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2017 Icenowy Zheng -// Based on sun50i-h5-orangepi-pc2.dts, which is: -// Copyright (C) 2016 ARM Ltd. - -/dts-v1/; -#include "sun50i-h5.dtsi" - -#include -#include - -/ { - model = "Xunlong Orange Pi Prime"; - compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr { - label = "orangepi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - status { - label = "orangepi:red:status"; - gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>; - }; - }; - - r-gpio-keys { - compatible = "gpio-keys"; - - sw4 { - label = "sw4"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usb0_vbus: usb0-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ - status = "okay"; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 2 14 GPIO_ACTIVE_LOW>; /* PC14 */ - }; -}; - -&codec { - allwinner,audio-routing = - "Line Out", "LINEOUT", - "MIC1", "Mic", - "Mic", "MBIAS"; - status = "okay"; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&external_mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&ir { - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - /* USB Type-A ports' VBUS is always on */ - usb0_id_det-gpios = <&pio 0 21 GPIO_ACTIVE_HIGH>; /* PA21 */ - usb0_vbus-supply = <®_usb0_vbus>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts deleted file mode 100644 index de448ca51..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts +++ /dev/null @@ -1,140 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2016 ARM Ltd. -// Copyright (C) 2018 Hauke Mehrtens - -/dts-v1/; -#include "sun50i-h5.dtsi" - -#include -#include -#include - -/ { - model = "Xunlong Orange Pi Zero Plus"; - compatible = "xunlong,orangepi-zero-plus", "allwinner,sun50i-h5"; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - aliases { - ethernet0 = &emac; - ethernet1 = &rtl8189ftv; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - pwr { - label = "orangepi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ - default-state = "on"; - }; - - status { - label = "orangepi:red:status"; - gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */ - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&external_mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - non-removable; - status = "okay"; - - /* - * Explicitly define the sdio device, so that we can add an ethernet - * alias for it (which e.g. makes u-boot set a mac-address). - */ - rtl8189ftv: sdio_wifi@1 { - reg = <1>; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25l1606e", "winbond,w25q128"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - /* USB Type-A ports' VBUS is always on */ - usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts deleted file mode 100644 index de19e68eb..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts +++ /dev/null @@ -1,143 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2017 Jagan Teki - -/dts-v1/; - -#include "sun50i-h5.dtsi" - -#include - -/ { - model = "OrangePi Zero Plus2"; - compatible = "xunlong,orangepi-zero-plus2", "allwinner,sun50i-h5"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - pwr { - label = "orangepi:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - status { - label = "orangepi:red:status"; - gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ - post-power-on-delay-ms = <200>; - }; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pa_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - status = "okay"; -}; - -&usb_otg { - /* - * According to schematics CN1 MicroUSB port can be used to take - * external 5V to power up the board VBUS. On the contrary CN1 MicroUSB - * port cannot provide power externally even if the board is powered - * via GPIO pins. It thus makes sense to force peripheral mode. - */ - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi deleted file mode 100644 index 0ee8a5adf..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ /dev/null @@ -1,257 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2016 ARM Ltd. - -#include - -#include - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <1>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <2>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <3>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ - #cooling-cells = <2>; - }; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - arm,no-tick-in-suspend; - interrupts = , - , - , - ; - }; - - soc { - syscon: system-control@1c00000 { - compatible = "allwinner,sun50i-h5-system-control"; - reg = <0x01c00000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_c1: sram@18000 { - compatible = "mmio-sram"; - reg = <0x00018000 0x1c000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00018000 0x1c000>; - - ve_sram: sram-section@0 { - compatible = "allwinner,sun50i-h5-sram-c1", - "allwinner,sun4i-a10-sram-c1"; - reg = <0x000000 0x1c000>; - }; - }; - }; - - video-codec@1c0e000 { - compatible = "allwinner,sun50i-h5-video-engine"; - reg = <0x01c0e000 0x1000>; - clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, - <&ccu CLK_DRAM_VE>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_BUS_VE>; - interrupts = ; - allwinner,sram = <&ve_sram 1>; - }; - - crypto: crypto@1c15000 { - compatible = "allwinner,sun50i-h5-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_CE>; - }; - - mali: gpu@1e80000 { - compatible = "allwinner,sun50i-h5-mali", "arm,mali-450"; - reg = <0x01e80000 0x30000>; - /* - * While the datasheet lists an interrupt for the - * PMU, the actual silicon does not have the PMU - * block. Reads all return zero, and writes are - * ignored. - */ - interrupts = , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pp2", - "ppmmu2", - "pp3", - "ppmmu3"; - clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; - clock-names = "bus", "core"; - resets = <&ccu RST_BUS_GPU>; - - assigned-clocks = <&ccu CLK_GPU>; - assigned-clock-rates = <384000000>; - }; - - ths: thermal-sensor@1c25000 { - compatible = "allwinner,sun50i-h5-ths"; - reg = <0x01c25000 0x400>; - interrupts = ; - resets = <&ccu RST_BUS_THS>; - clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; - clock-names = "bus", "mod"; - nvmem-cells = <&ths_calibration>; - nvmem-cell-names = "calibration"; - #thermal-sensor-cells = <1>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 0>; - - trips { - cpu_hot_trip: cpu-hot { - temperature = <80000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_very_hot_trip: cpu-very-hot { - temperature = <100000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - cpu-hot-limit { - trip = <&cpu_hot_trip>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 1>; - }; - }; -}; - -&ccu { - compatible = "allwinner,sun50i-h5-ccu"; -}; - -&display_clocks { - compatible = "allwinner,sun50i-h5-de2-clk"; -}; - -&mmc0 { - compatible = "allwinner,sun50i-h5-mmc", - "allwinner,sun50i-a64-mmc"; - clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; - clock-names = "ahb", "mmc"; -}; - -&mmc1 { - compatible = "allwinner,sun50i-h5-mmc", - "allwinner,sun50i-a64-mmc"; - clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; - clock-names = "ahb", "mmc"; -}; - -&mmc2 { - compatible = "allwinner,sun50i-h5-emmc", - "allwinner,sun50i-a64-emmc"; - clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; - clock-names = "ahb", "mmc"; -}; - -&pio { - interrupts = , - , - ; - compatible = "allwinner,sun50i-h5-pinctrl"; -}; - -&rtc { - compatible = "allwinner,sun50i-h5-rtc"; -}; - -&sid { - compatible = "allwinner,sun50i-h5-sid"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts deleted file mode 100644 index e8163c572..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts +++ /dev/null @@ -1,314 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2019 Clément Péron - -/dts-v1/; - -#include "sun50i-h6.dtsi" -#include "sun50i-h6-cpu-opp.dtsi" - -#include - -/ { - model = "Beelink GS1"; - compatible = "azw,beelink-gs1", "allwinner,sun50i-h6"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - ext_osc32k: ext_osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "ext_osc32k"; - }; - - leds { - compatible = "gpio-leds"; - - power { - label = "beelink:white:power"; - gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ - default-state = "on"; - }; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the DC jack */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - sound-spdif { - compatible = "simple-audio-card"; - simple-audio-card,name = "sun50i-h6-spdif"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_out>; - }; - }; - - spdif_out: spdif-out { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdca>; -}; - -&de { - status = "okay"; -}; - -&dwc3 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&ext_rgmii_pins>; - phy-mode = "rgmii-id"; - phy-handle = <&ext_rgmii_phy>; - phy-supply = <®_aldo2>; - status = "okay"; -}; - -&gpu { - mali-supply = <®_dcdcc>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_cldo1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&mmc2 { - vmmc-supply = <®_cldo1>; - vqmmc-supply = <®_bldo2>; - non-removable; - cap-mmc-hw-reset; - bus-width = <8>; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&pio { - vcc-pd-supply = <®_cldo1>; - vcc-pg-supply = <®_aldo1>; -}; - -&r_i2c { - status = "okay"; - - axp805: pmic@36 { - compatible = "x-powers,axp805", "x-powers,axp806"; - reg = <0x36>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - x-powers,self-working-mode; - vina-supply = <®_vcc5v>; - vinb-supply = <®_vcc5v>; - vinc-supply = <®_vcc5v>; - vind-supply = <®_vcc5v>; - vine-supply = <®_vcc5v>; - aldoin-supply = <®_vcc5v>; - bldoin-supply = <®_vcc5v>; - cldoin-supply = <®_vcc5v>; - - regulators { - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; - }; - - reg_aldo2: aldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-ac200"; - regulator-enable-ramp-delay = <100000>; - }; - - reg_aldo3: aldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc25-dram"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-bias-pll"; - }; - - reg_bldo2: bldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-efuse-pcie-hdmi-io"; - }; - - reg_bldo3: bldo3 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-dcxoio"; - }; - - bldo4 { - /* unused */ - }; - - reg_cldo1: cldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; - }; - - reg_cldo2: cldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-1"; - }; - - reg_cldo3: cldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-2"; - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1160000>; - regulator-ramp-delay = <2500>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdcc: dcdcc { - regulator-enable-ramp-delay = <32000>; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; - regulator-ramp-delay = <2500>; - regulator-name = "vdd-gpu"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <960000>; - regulator-max-microvolt = <960000>; - regulator-name = "vdd-sys"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dram"; - }; - - sw { - /* unused */ - }; - }; - }; -}; - -&r_ir { - linux,rc-map-name = "rc-beelink-gs1"; - status = "okay"; -}; - -&r_pio { - /* - * PL0 and PL1 are used for PMIC I2C - * don't enable the pl-supply else - * it will fail at boot - * - * vcc-pl-supply = <®_aldo1>; - */ - vcc-pm-supply = <®_aldo1>; -}; - -&spdif { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usb2otg { - dr_mode = "host"; - status = "okay"; -}; - -&usb2phy { - usb0_vbus-supply = <®_vcc5v>; - status = "okay"; -}; - -&usb3phy { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi deleted file mode 100644 index 653452926..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2020 Ondrej Jirman -// Copyright (C) 2020 Clément Péron - -/ { - cpu_opp_table: opp-table-cpu { - compatible = "allwinner,sun50i-h6-operating-points"; - nvmem-cells = <&cpu_speed_grade>; - opp-shared; - - opp@480000000 { - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-hz = /bits/ 64 <480000000>; - - opp-microvolt-speed0 = <880000 880000 1200000>; - opp-microvolt-speed1 = <820000 820000 1200000>; - opp-microvolt-speed2 = <820000 820000 1200000>; - }; - - opp@720000000 { - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-hz = /bits/ 64 <720000000>; - - opp-microvolt-speed0 = <880000 880000 1200000>; - opp-microvolt-speed1 = <820000 820000 1200000>; - opp-microvolt-speed2 = <820000 820000 1200000>; - }; - - opp@816000000 { - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-hz = /bits/ 64 <816000000>; - - opp-microvolt-speed0 = <880000 880000 1200000>; - opp-microvolt-speed1 = <820000 820000 1200000>; - opp-microvolt-speed2 = <820000 820000 1200000>; - }; - - opp@888000000 { - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-hz = /bits/ 64 <888000000>; - - opp-microvolt-speed0 = <880000 880000 1200000>; - opp-microvolt-speed1 = <820000 820000 1200000>; - opp-microvolt-speed2 = <820000 820000 1200000>; - }; - - opp@1080000000 { - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-hz = /bits/ 64 <1080000000>; - - opp-microvolt-speed0 = <940000 940000 1200000>; - opp-microvolt-speed1 = <880000 880000 1200000>; - opp-microvolt-speed2 = <880000 880000 1200000>; - }; - - opp@1320000000 { - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-hz = /bits/ 64 <1320000000>; - - opp-microvolt-speed0 = <1000000 1000000 1200000>; - opp-microvolt-speed1 = <940000 940000 1200000>; - opp-microvolt-speed2 = <940000 940000 1200000>; - }; - - opp@1488000000 { - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-hz = /bits/ 64 <1488000000>; - - opp-microvolt-speed0 = <1060000 1060000 1200000>; - opp-microvolt-speed1 = <1000000 1000000 1200000>; - opp-microvolt-speed2 = <1000000 1000000 1200000>; - }; - - opp@1608000000 { - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-hz = /bits/ 64 <1608000000>; - - opp-microvolt-speed0 = <1090000 1090000 1200000>; - opp-microvolt-speed1 = <1030000 1030000 1200000>; - opp-microvolt-speed2 = <1030000 1030000 1200000>; - }; - - opp@1704000000 { - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-hz = /bits/ 64 <1704000000>; - - opp-microvolt-speed0 = <1120000 1120000 1200000>; - opp-microvolt-speed1 = <1060000 1060000 1200000>; - opp-microvolt-speed2 = <1060000 1060000 1200000>; - }; - - opp@1800000000 { - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-hz = /bits/ 64 <1800000000>; - - opp-microvolt-speed0 = <1160000 1160000 1200000>; - opp-microvolt-speed1 = <1100000 1100000 1200000>; - opp-microvolt-speed2 = <1100000 1100000 1200000>; - }; - }; -}; - -&cpu0 { - operating-points-v2 = <&cpu_opp_table>; -}; - -&cpu1 { - operating-points-v2 = <&cpu_opp_table>; -}; - -&cpu2 { - operating-points-v2 = <&cpu_opp_table>; -}; - -&cpu3 { - operating-points-v2 = <&cpu_opp_table>; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts deleted file mode 100644 index 15c9dd8c4..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +++ /dev/null @@ -1,345 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2019 OndÅ™ej Jirman - -/dts-v1/; - -#include "sun50i-h6.dtsi" -#include "sun50i-h6-cpu-opp.dtsi" - -#include - -/ { - model = "OrangePi 3"; - compatible = "xunlong,orangepi-3", "allwinner,sun50i-h6"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - ext_osc32k: ext_osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "ext_osc32k"; - }; - - leds { - compatible = "gpio-leds"; - - power { - label = "orangepi:red:power"; - gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ - default-state = "on"; - }; - - status { - label = "orangepi:green:status"; - gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ - }; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the DC jack */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_vcc33_wifi: vcc33-wifi { - /* Always on 3.3V regulator for WiFi and BT */ - compatible = "regulator-fixed"; - regulator-name = "vcc33-wifi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <®_vcc5v>; - }; - - reg_vcc_wifi_io: vcc-wifi-io { - /* Always on 1.8V/300mA regulator for WiFi and BT IO */ - compatible = "regulator-fixed"; - regulator-name = "vcc-wifi-io"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <®_vcc33_wifi>; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; - clock-names = "ext_clock"; - reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ - post-power-on-delay-ms = <200>; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdca>; -}; - -&de { - status = "okay"; -}; - -&dwc3 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&gpu { - mali-supply = <®_dcdcc>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - vmmc-supply = <®_cldo1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc33_wifi>; - vqmmc-supply = <®_vcc_wifi_io>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcm: sdio-wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ - interrupt-names = "host-wake"; - }; -}; - -&mmc2 { - vmmc-supply = <®_cldo1>; - vqmmc-supply = <®_bldo2>; - cap-mmc-hw-reset; - non-removable; - bus-width = <8>; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&pio { - vcc-pc-supply = <®_bldo2>; - vcc-pd-supply = <®_cldo1>; - vcc-pg-supply = <®_vcc_wifi_io>; -}; - -&r_i2c { - status = "okay"; - - axp805: pmic@36 { - compatible = "x-powers,axp805", "x-powers,axp806"; - reg = <0x36>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - x-powers,self-working-mode; - vina-supply = <®_vcc5v>; - vinb-supply = <®_vcc5v>; - vinc-supply = <®_vcc5v>; - vind-supply = <®_vcc5v>; - vine-supply = <®_vcc5v>; - aldoin-supply = <®_vcc5v>; - bldoin-supply = <®_vcc5v>; - cldoin-supply = <®_vcc5v>; - - regulators { - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl-led-ir"; - }; - - reg_aldo2: aldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33-audio-tv-ephy-mac"; - }; - - /* ALDO3 is shorted to CLDO1 */ - reg_aldo3: aldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-1"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18-dram-bias-pll"; - }; - - reg_bldo2: bldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-efuse-pcie-hdmi-pc"; - }; - - bldo3 { - /* unused */ - }; - - bldo4 { - /* unused */ - }; - - reg_cldo1: cldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2"; - }; - - cldo2 { - /* unused */ - }; - - cldo3 { - /* unused */ - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1160000>; - regulator-ramp-delay = <2500>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdcc: dcdcc { - regulator-enable-ramp-delay = <32000>; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; - regulator-ramp-delay = <2500>; - regulator-name = "vdd-gpu"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <960000>; - regulator-max-microvolt = <960000>; - regulator-name = "vdd-sys"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dram"; - }; - - sw { - /* unused */ - }; - }; - }; -}; - -&r_ir { - status = "okay"; -}; - -&rtc { - clocks = <&ext_osc32k>; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -/* There's the BT part of the AP6256 connected to that UART */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4345c5"; - clocks = <&rtc 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ - host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ - shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ - max-speed = <1500000>; - }; -}; - -&usb2otg { - /* - * This board doesn't have a controllable VBUS even though it - * does have an ID pin. Using it as anything but a USB host is - * unsafe. - */ - dr_mode = "host"; - status = "okay"; -}; - -&usb2phy { - usb0_id_det-gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */ - usb0_vbus-supply = <®_vcc5v>; - usb3_vbus-supply = <®_vcc5v>; - status = "okay"; -}; - -&usb3phy { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts deleted file mode 100644 index e8770858b..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2018 Jagan Teki - -#include "sun50i-h6-orangepi.dtsi" - -/ { - model = "OrangePi Lite2"; - compatible = "xunlong,orangepi-lite2", "allwinner,sun50i-h6"; - - aliases { - serial1 = &uart1; /* BT-UART */ - }; - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; - clock-names = "ext_clock"; - reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ - post-power-on-delay-ms = <200>; - }; -}; - -&mmc1 { - vmmc-supply = <®_cldo2>; - vqmmc-supply = <®_bldo3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - brcm: sdio-wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&r_pio>; - interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ - interrupt-names = "host-wake"; - }; -}; - -®_cldo2 { - /* - * This regulator is connected with CLDO3. - * Before the kernel can support synchronized - * enable of coupled regulators, keep them - * both always on as a ugly hack. - */ - regulator-always-on; -}; - -®_cldo3 { - /* - * This regulator is connected with CLDO2. - * See the comments for CLDO2. - */ - regulator-always-on; -}; - -/* There's the BT part of the AP6255 connected to that UART */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm4345c5"; - clocks = <&rtc 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ - host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ - shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ - max-speed = <1500000>; - }; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts deleted file mode 100644 index 29a081e72..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2018 Amarula Solutions -// Author: Jagan Teki - -#include "sun50i-h6-orangepi.dtsi" - -/ { - model = "OrangePi One Plus"; - compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6"; - - aliases { - ethernet0 = &emac; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc-gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ - vin-supply = <®_aldo2>; - }; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&ext_rgmii_pins>; - phy-mode = "rgmii-id"; - phy-handle = <&ext_rgmii_phy>; - phy-supply = <®_gmac_3v3>; - allwinner,rx-delay-ps = <200>; - allwinner,tx-delay-ps = <200>; - status = "okay"; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi deleted file mode 100644 index ebc120a92..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +++ /dev/null @@ -1,268 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2018 Amarula Solutions -// Author: Jagan Teki - -/dts-v1/; - -#include "sun50i-h6.dtsi" - -#include - -/ { - model = "OrangePi One Plus"; - compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - type = "a"; - ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - ext_osc32k: ext_osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "ext_osc32k"; - }; - - leds { - compatible = "gpio-leds"; - - power { - label = "orangepi:red:power"; - gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ - default-state = "on"; - }; - - status { - label = "orangepi:green:status"; - gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ - }; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the DC jack */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&gpu { - mali-supply = <®_dcdcc>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - vmmc-supply = <®_cldo1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&pio { - vcc-pc-supply = <®_bldo2>; - vcc-pd-supply = <®_cldo1>; - vcc-pg-supply = <®_aldo1>; -}; - -&r_i2c { - status = "okay"; - - axp805: pmic@36 { - compatible = "x-powers,axp805", "x-powers,axp806"; - reg = <0x36>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - x-powers,self-working-mode; - vina-supply = <®_vcc5v>; - vinb-supply = <®_vcc5v>; - vinc-supply = <®_vcc5v>; - vind-supply = <®_vcc5v>; - vine-supply = <®_vcc5v>; - aldoin-supply = <®_vcc5v>; - bldoin-supply = <®_vcc5v>; - cldoin-supply = <®_vcc5v>; - - regulators { - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; - }; - - reg_aldo2: aldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-ac200"; - }; - - reg_aldo3: aldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc25-dram"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-bias-pll"; - }; - - reg_bldo2: bldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-efuse-pcie-hdmi-io"; - }; - - reg_bldo3: bldo3 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-dcxoio"; - }; - - bldo4 { - /* unused */ - }; - - reg_cldo1: cldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; - }; - - reg_cldo2: cldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-1"; - }; - - reg_cldo3: cldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-2"; - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdcc: dcdcc { - regulator-enable-ramp-delay = <32000>; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; - regulator-name = "vdd-gpu"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <960000>; - regulator-max-microvolt = <960000>; - regulator-name = "vdd-sys"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dram"; - }; - - sw { - /* unused */ - }; - }; - }; -}; - -&r_ir { - status = "okay"; -}; - -&r_pio { - vcc-pm-supply = <®_bldo3>; -}; - -&rtc { - clocks = <&ext_osc32k>; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usb2otg { - /* - * OrangePi Lite 2 and One Plus, where this DT is used, don't - * have a controllable VBUS even though they do have an ID pin. - * Using it as anything but a USB host is unsafe. - */ - dr_mode = "host"; - status = "okay"; -}; - -&usb2phy { - usb0_id_det-gpios = <&pio 2 6 GPIO_ACTIVE_HIGH>; /* PC6 */ - usb0_vbus-supply = <®_vcc5v>; - usb3_vbus-supply = <®_vcc5v>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts deleted file mode 100644 index f4c8966a6..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) -/* - * Copyright (C) 2019 Corentin LABBE - */ - -#include "sun50i-h6-pine-h64.dts" - -/ { - model = "Pine H64 model B"; - compatible = "pine64,pine-h64-model-b", "allwinner,sun50i-h6"; - - /delete-node/ reg_gmac_3v3; -}; - -&hdmi_connector { - /delete-property/ ddc-en-gpios; -}; - -&emac { - phy-supply = <®_aldo2>; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts deleted file mode 100644 index 961732c52..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +++ /dev/null @@ -1,333 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2017 Icenowy Zheng - -/dts-v1/; - -#include "sun50i-h6.dtsi" -#include "sun50i-h6-cpu-opp.dtsi" - -#include - -/ { - model = "Pine H64 model A"; - compatible = "pine64,pine-h64", "allwinner,sun50i-h6"; - - aliases { - ethernet0 = &emac; - serial0 = &uart0; - spi0 = &spi0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - ext_osc32k: ext_osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "ext_osc32k"; - }; - - hdmi_connector: connector { - compatible = "hdmi-connector"; - type = "a"; - ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - heartbeat { - label = "pine-h64:green:heartbeat"; - gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ - }; - - link { - label = "pine-h64:white:link"; - gpios = <&r_pio 0 3 GPIO_ACTIVE_HIGH>; /* PL3 */ - }; - - status { - label = "pine-h64:blue:status"; - gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ - }; - }; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc-gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_vbus: vbus { - compatible = "regulator-fixed"; - regulator-name = "usb-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <100000>; - gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdca>; -}; - -&de { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&emac { - pinctrl-names = "default"; - pinctrl-0 = <&ext_rgmii_pins>; - phy-mode = "rgmii-id"; - phy-handle = <&ext_rgmii_phy>; - phy-supply = <®_gmac_3v3>; - allwinner,rx-delay-ps = <200>; - allwinner,tx-delay-ps = <200>; - status = "okay"; -}; - -&gpu { - mali-supply = <®_dcdcc>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - vmmc-supply = <®_cldo1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&mmc2 { - vmmc-supply = <®_cldo1>; - vqmmc-supply = <®_bldo2>; - non-removable; - cap-mmc-hw-reset; - bus-width = <8>; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&pio { - vcc-pc-supply = <®_bldo2>; - vcc-pd-supply = <®_cldo1>; - vcc-pg-supply = <®_aldo1>; -}; - -&r_i2c { - status = "okay"; - - axp805: pmic@36 { - compatible = "x-powers,axp805", "x-powers,axp806"; - reg = <0x36>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - x-powers,self-working-mode; - - regulators { - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pl"; - }; - - reg_aldo2: aldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-ac200"; - regulator-enable-ramp-delay = <100000>; - }; - - reg_aldo3: aldo3 { - /* This regulator is connected with CLDO1 */ - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3-1"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-bias-pll"; - }; - - reg_bldo2: bldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-efuse-pcie-hdmi-io"; - }; - - reg_bldo3: bldo3 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-dcxoio"; - }; - - bldo4 { - /* unused */ - }; - - reg_cldo1: cldo1 { - /* This regulator is connected with ALDO3 */ - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3-2"; - }; - - reg_cldo2: cldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-1"; - }; - - reg_cldo3: cldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi-2"; - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1160000>; - regulator-ramp-delay = <2500>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdcc: dcdcc { - regulator-enable-ramp-delay = <32000>; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; - regulator-ramp-delay = <2500>; - regulator-name = "vdd-gpu"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <960000>; - regulator-max-microvolt = <960000>; - regulator-name = "vdd-sys"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dram"; - }; - - sw { - /* unused */ - }; - }; - }; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - interrupt-parent = <&r_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - #clock-cells = <0>; - }; -}; - -&r_ir { - status = "okay"; -}; - -&r_pio { - vcc-pm-supply = <®_aldo1>; -}; - -&rtc { - clocks = <&ext_osc32k>; -}; - -/* - * The CS pin is shared with the MMC2 CMD pin, so we cannot have the SPI - * flash and eMMC at the same time, as one of them would fail probing. - * Disable SPI0 in here, to prefer the more useful eMMC. U-Boot can - * fix this up in no eMMC is connected. - */ -&spi0 { - pinctrl-0 = <&spi0_pins>, <&spi0_cs_pin>; - pinctrl-names = "default"; - status = "disabled"; - - flash@0 { - compatible = "winbond,w25q128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <4000000>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usb2otg { - dr_mode = "host"; - status = "okay"; -}; - -&usb2phy { - usb0_vbus-supply = <®_usb_vbus>; - usb3_vbus-supply = <®_usb_vbus>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts deleted file mode 100644 index 026411916..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2019 Jernej Skrabec - -/dts-v1/; - -#include "sun50i-h6.dtsi" -#include "sun50i-h6-cpu-opp.dtsi" - -#include - -/ { - model = "Tanix TX6"; - compatible = "oranth,tanix-tx6", "allwinner,sun50i-h6"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - connector { - compatible = "hdmi-connector"; - ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - reg_vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_vdd_cpu_gpu: regulator-vdd-cpu-gpu { - compatible = "regulator-fixed"; - regulator-name = "vdd-cpu-gpu"; - regulator-min-microvolt = <1135000>; - regulator-max-microvolt = <1135000>; - }; -}; - -&cpu0 { - cpu-supply = <®_vdd_cpu_gpu>; -}; - -&de { - status = "okay"; -}; - -&dwc3 { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&gpu { - mali-supply = <®_vdd_cpu_gpu>; - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_vcc3v3>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&r_ir { - linux,rc-map-name = "rc-tanix-tx5max"; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usb2otg { - dr_mode = "host"; - status = "okay"; -}; - -&usb2phy { - status = "okay"; -}; - -&usb3phy { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi deleted file mode 100644 index 4592fb7a6..000000000 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ /dev/null @@ -1,1026 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2017 Icenowy Zheng - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <1>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <2>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <3>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ - #cooling-cells = <2>; - }; - }; - - de: display-engine { - compatible = "allwinner,sun50i-h6-display-engine"; - allwinner,pipelines = <&mixer0>; - status = "disabled"; - }; - - osc24M: osc24M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - arm,no-tick-in-suspend; - interrupts = , - , - , - ; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - bus@1000000 { - compatible = "allwinner,sun50i-h6-de3", - "allwinner,sun50i-a64-de2"; - reg = <0x1000000 0x400000>; - allwinner,sram = <&de2_sram 1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1000000 0x400000>; - - display_clocks: clock@0 { - compatible = "allwinner,sun50i-h6-de3-clk"; - reg = <0x0 0x10000>; - clocks = <&ccu CLK_DE>, - <&ccu CLK_BUS_DE>; - clock-names = "mod", - "bus"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - mixer0: mixer@100000 { - compatible = "allwinner,sun50i-h6-de3-mixer-0"; - reg = <0x100000 0x100000>; - clocks = <&display_clocks CLK_BUS_MIXER0>, - <&display_clocks CLK_MIXER0>; - clock-names = "bus", - "mod"; - resets = <&display_clocks RST_MIXER0>; - iommus = <&iommu 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mixer0_out: port@1 { - reg = <1>; - - mixer0_out_tcon_top_mixer0: endpoint { - remote-endpoint = <&tcon_top_mixer0_in_mixer0>; - }; - }; - }; - }; - }; - - video-codec@1c0e000 { - compatible = "allwinner,sun50i-h6-video-engine"; - reg = <0x01c0e000 0x2000>; - clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, - <&ccu CLK_MBUS_VE>; - clock-names = "ahb", "mod", "ram"; - resets = <&ccu RST_BUS_VE>; - interrupts = ; - allwinner,sram = <&ve_sram 1>; - iommus = <&iommu 3>; - }; - - gpu: gpu@1800000 { - compatible = "allwinner,sun50i-h6-mali", - "arm,mali-t720"; - reg = <0x01800000 0x4000>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; - clock-names = "core", "bus"; - resets = <&ccu RST_BUS_GPU>; - status = "disabled"; - }; - - crypto: crypto@1904000 { - compatible = "allwinner,sun50i-h6-crypto"; - reg = <0x01904000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>; - clock-names = "bus", "mod", "ram"; - resets = <&ccu RST_BUS_CE>; - }; - - syscon: syscon@3000000 { - compatible = "allwinner,sun50i-h6-system-control", - "allwinner,sun50i-a64-system-control"; - reg = <0x03000000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_c: sram@28000 { - compatible = "mmio-sram"; - reg = <0x00028000 0x1e000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00028000 0x1e000>; - - de2_sram: sram-section@0 { - compatible = "allwinner,sun50i-h6-sram-c", - "allwinner,sun50i-a64-sram-c"; - reg = <0x0000 0x1e000>; - }; - }; - - sram_c1: sram@1a00000 { - compatible = "mmio-sram"; - reg = <0x01a00000 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x01a00000 0x200000>; - - ve_sram: sram-section@0 { - compatible = "allwinner,sun50i-h6-sram-c1", - "allwinner,sun4i-a10-sram-c1"; - reg = <0x000000 0x200000>; - }; - }; - }; - - ccu: clock@3001000 { - compatible = "allwinner,sun50i-h6-ccu"; - reg = <0x03001000 0x1000>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; - clock-names = "hosc", "losc", "iosc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - dma: dma-controller@3002000 { - compatible = "allwinner,sun50i-h6-dma"; - reg = <0x03002000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; - clock-names = "bus", "mbus"; - dma-channels = <16>; - dma-requests = <46>; - resets = <&ccu RST_BUS_DMA>; - #dma-cells = <1>; - }; - - msgbox: mailbox@3003000 { - compatible = "allwinner,sun50i-h6-msgbox", - "allwinner,sun6i-a31-msgbox"; - reg = <0x03003000 0x1000>; - clocks = <&ccu CLK_BUS_MSGBOX>; - resets = <&ccu RST_BUS_MSGBOX>; - interrupts = ; - #mbox-cells = <1>; - }; - - sid: efuse@3006000 { - compatible = "allwinner,sun50i-h6-sid"; - reg = <0x03006000 0x400>; - #address-cells = <1>; - #size-cells = <1>; - - ths_calibration: thermal-sensor-calibration@14 { - reg = <0x14 0x8>; - }; - - cpu_speed_grade: cpu-speed-grade@1c { - reg = <0x1c 0x4>; - }; - }; - - watchdog: watchdog@30090a0 { - compatible = "allwinner,sun50i-h6-wdt", - "allwinner,sun6i-a31-wdt"; - reg = <0x030090a0 0x20>; - interrupts = ; - clocks = <&osc24M>; - /* Broken on some H6 boards */ - status = "disabled"; - }; - - pwm: pwm@300a000 { - compatible = "allwinner,sun50i-h6-pwm"; - reg = <0x0300a000 0x400>; - clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; - clock-names = "mod", "bus"; - resets = <&ccu RST_BUS_PWM>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pio: pinctrl@300b000 { - compatible = "allwinner,sun50i-h6-pinctrl"; - reg = <0x0300b000 0x400>; - interrupts = , - , - , - ; - clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - ext_rgmii_pins: rgmii-pins { - pins = "PD0", "PD1", "PD2", "PD3", "PD4", - "PD5", "PD7", "PD8", "PD9", "PD10", - "PD11", "PD12", "PD13", "PD19", "PD20"; - function = "emac"; - drive-strength = <40>; - }; - - hdmi_pins: hdmi-pins { - pins = "PH8", "PH9", "PH10"; - function = "hdmi"; - }; - - i2c0_pins: i2c0-pins { - pins = "PD25", "PD26"; - function = "i2c0"; - }; - - i2c1_pins: i2c1-pins { - pins = "PH5", "PH6"; - function = "i2c1"; - }; - - i2c2_pins: i2c2-pins { - pins = "PD23", "PD24"; - function = "i2c2"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - /omit-if-no-ref/ - mmc1_pins: mmc1-pins { - pins = "PG0", "PG1", "PG2", "PG3", - "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_pins: mmc2-pins { - pins = "PC1", "PC4", "PC5", "PC6", - "PC7", "PC8", "PC9", "PC10", - "PC11", "PC12", "PC13", "PC14"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - /omit-if-no-ref/ - spi0_pins: spi0-pins { - pins = "PC0", "PC2", "PC3"; - function = "spi0"; - }; - - /* pin shared with MMC2-CMD (eMMC) */ - /omit-if-no-ref/ - spi0_cs_pin: spi0-cs-pin { - pins = "PC5"; - function = "spi0"; - }; - - /omit-if-no-ref/ - spi1_pins: spi1-pins { - pins = "PH4", "PH5", "PH6"; - function = "spi1"; - }; - - /omit-if-no-ref/ - spi1_cs_pin: spi1-cs-pin { - pins = "PH3"; - function = "spi1"; - }; - - spdif_tx_pin: spdif-tx-pin { - pins = "PH7"; - function = "spdif"; - }; - - uart0_ph_pins: uart0-ph-pins { - pins = "PH0", "PH1"; - function = "uart0"; - }; - - uart1_pins: uart1-pins { - pins = "PG6", "PG7"; - function = "uart1"; - }; - - uart1_rts_cts_pins: uart1-rts-cts-pins { - pins = "PG8", "PG9"; - function = "uart1"; - }; - }; - - gic: interrupt-controller@3021000 { - compatible = "arm,gic-400"; - reg = <0x03021000 0x1000>, - <0x03022000 0x2000>, - <0x03024000 0x2000>, - <0x03026000 0x2000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - - iommu: iommu@30f0000 { - compatible = "allwinner,sun50i-h6-iommu"; - reg = <0x030f0000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_BUS_IOMMU>; - resets = <&ccu RST_BUS_IOMMU>; - #iommu-cells = <1>; - }; - - mmc0: mmc@4020000 { - compatible = "allwinner,sun50i-h6-mmc", - "allwinner,sun50i-a64-mmc"; - reg = <0x04020000 0x1000>; - clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - max-frequency = <150000000>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@4021000 { - compatible = "allwinner,sun50i-h6-mmc", - "allwinner,sun50i-a64-mmc"; - reg = <0x04021000 0x1000>; - clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - max-frequency = <150000000>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@4022000 { - compatible = "allwinner,sun50i-h6-emmc", - "allwinner,sun50i-a64-emmc"; - reg = <0x04022000 0x1000>; - clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - max-frequency = <150000000>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart0: serial@5000000 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - status = "disabled"; - }; - - uart1: serial@5000400 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000400 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - status = "disabled"; - }; - - uart2: serial@5000800 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000800 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - status = "disabled"; - }; - - uart3: serial@5000c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000c00 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - resets = <&ccu RST_BUS_UART3>; - status = "disabled"; - }; - - i2c0: i2c@5002000 { - compatible = "allwinner,sun50i-h6-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05002000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@5002400 { - compatible = "allwinner,sun50i-h6-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05002400 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@5002800 { - compatible = "allwinner,sun50i-h6-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05002800 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@5010000 { - compatible = "allwinner,sun50i-h6-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x05010000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma 22>, <&dma 22>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_SPI0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@5011000 { - compatible = "allwinner,sun50i-h6-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x05011000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - dmas = <&dma 23>, <&dma 23>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_SPI1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emac: ethernet@5020000 { - compatible = "allwinner,sun50i-h6-emac", - "allwinner,sun50i-a64-emac"; - syscon = <&syscon>; - reg = <0x05020000 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - resets = <&ccu RST_BUS_EMAC>; - reset-names = "stmmaceth"; - clocks = <&ccu CLK_BUS_EMAC>; - clock-names = "stmmaceth"; - status = "disabled"; - - mdio: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - spdif: spdif@5093000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun50i-h6-spdif"; - reg = <0x05093000 0x400>; - interrupts = ; - clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; - clock-names = "apb", "spdif"; - resets = <&ccu RST_BUS_SPDIF>; - dmas = <&dma 2>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - status = "disabled"; - }; - - usb2otg: usb@5100000 { - compatible = "allwinner,sun50i-h6-musb", - "allwinner,sun8i-a33-musb"; - reg = <0x05100000 0x0400>; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - interrupts = ; - interrupt-names = "mc"; - phys = <&usb2phy 0>; - phy-names = "usb"; - extcon = <&usb2phy 0>; - status = "disabled"; - }; - - usb2phy: phy@5100400 { - compatible = "allwinner,sun50i-h6-usb-phy"; - reg = <0x05100400 0x24>, - <0x05101800 0x4>, - <0x05311800 0x4>; - reg-names = "phy_ctrl", - "pmu0", - "pmu3"; - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY3>; - clock-names = "usb0_phy", - "usb3_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY3>; - reset-names = "usb0_reset", - "usb3_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci0: usb@5101000 { - compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; - reg = <0x05101000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_BUS_EHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_OHCI0>, - <&ccu RST_BUS_EHCI0>; - phys = <&usb2phy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@5101400 { - compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; - reg = <0x05101400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_OHCI0>; - phys = <&usb2phy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - dwc3: dwc3@5200000 { - compatible = "snps,dwc3"; - reg = <0x05200000 0x10000>; - interrupts = ; - clocks = <&ccu CLK_BUS_XHCI>, - <&ccu CLK_BUS_XHCI>, - <&rtc 0>; - clock-names = "ref", "bus_early", "suspend"; - resets = <&ccu RST_BUS_XHCI>; - /* - * The datasheet of the chip doesn't declare the - * peripheral function, and there's no boards known - * to have a USB Type-B port routed to the port. - * In addition, no one has tested the peripheral - * function yet. - * So set the dr_mode to "host" in the DTSI file. - */ - dr_mode = "host"; - phys = <&usb3phy>; - phy-names = "usb3-phy"; - status = "disabled"; - }; - - usb3phy: phy@5210000 { - compatible = "allwinner,sun50i-h6-usb3-phy"; - reg = <0x5210000 0x10000>; - clocks = <&ccu CLK_USB_PHY1>; - resets = <&ccu RST_USB_PHY1>; - #phy-cells = <0>; - status = "disabled"; - }; - - ehci3: usb@5311000 { - compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; - reg = <0x05311000 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI3>, - <&ccu CLK_BUS_EHCI3>, - <&ccu CLK_USB_OHCI3>; - resets = <&ccu RST_BUS_OHCI3>, - <&ccu RST_BUS_EHCI3>; - phys = <&usb2phy 3>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci3: usb@5311400 { - compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; - reg = <0x05311400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_OHCI3>, - <&ccu CLK_USB_OHCI3>; - resets = <&ccu RST_BUS_OHCI3>; - phys = <&usb2phy 3>; - phy-names = "usb"; - status = "disabled"; - }; - - hdmi: hdmi@6000000 { - compatible = "allwinner,sun50i-h6-dw-hdmi"; - reg = <0x06000000 0x10000>; - reg-io-width = <1>; - interrupts = ; - clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, - <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, - <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; - clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", - "hdcp-bus"; - resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; - reset-names = "ctrl", "hdcp"; - phys = <&hdmi_phy>; - phy-names = "phy"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pins>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in: port@0 { - reg = <0>; - - hdmi_in_tcon_top: endpoint { - remote-endpoint = <&tcon_top_hdmi_out_hdmi>; - }; - }; - - hdmi_out: port@1 { - reg = <1>; - }; - }; - }; - - hdmi_phy: hdmi-phy@6010000 { - compatible = "allwinner,sun50i-h6-hdmi-phy"; - reg = <0x06010000 0x10000>; - clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_HDMI>; - reset-names = "phy"; - #phy-cells = <0>; - }; - - tcon_top: tcon-top@6510000 { - compatible = "allwinner,sun50i-h6-tcon-top"; - reg = <0x06510000 0x1000>; - clocks = <&ccu CLK_BUS_TCON_TOP>, - <&ccu CLK_TCON_TV0>; - clock-names = "bus", - "tcon-tv0"; - clock-output-names = "tcon-top-tv0"; - resets = <&ccu RST_BUS_TCON_TOP>; - #clock-cells = <1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon_top_mixer0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tcon_top_mixer0_in_mixer0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mixer0_out_tcon_top_mixer0>; - }; - }; - - tcon_top_mixer0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon_top_mixer0_out_tcon_tv: endpoint@2 { - reg = <2>; - remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>; - }; - }; - - tcon_top_hdmi_in: port@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - tcon_top_hdmi_in_tcon_tv: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon_tv_out_tcon_top>; - }; - }; - - tcon_top_hdmi_out: port@5 { - reg = <5>; - - tcon_top_hdmi_out_hdmi: endpoint { - remote-endpoint = <&hdmi_in_tcon_top>; - }; - }; - }; - }; - - tcon_tv: lcd-controller@6515000 { - compatible = "allwinner,sun50i-h6-tcon-tv", - "allwinner,sun8i-r40-tcon-tv"; - reg = <0x06515000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_TCON_TV0>, - <&tcon_top CLK_TCON_TOP_TV0>; - clock-names = "ahb", - "tcon-ch1"; - resets = <&ccu RST_BUS_TCON_TV0>; - reset-names = "lcd"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon_tv_in: port@0 { - reg = <0>; - - tcon_tv_in_tcon_top_mixer0: endpoint { - remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>; - }; - }; - - tcon_tv_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tcon_tv_out_tcon_top: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>; - }; - }; - }; - }; - - rtc: rtc@7000000 { - compatible = "allwinner,sun50i-h6-rtc"; - reg = <0x07000000 0x400>; - interrupts = , - ; - clock-output-names = "osc32k", "osc32k-out", "iosc"; - #clock-cells = <1>; - }; - - r_ccu: clock@7010000 { - compatible = "allwinner,sun50i-h6-r-ccu"; - reg = <0x07010000 0x400>; - clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, - <&ccu CLK_PLL_PERIPH0>; - clock-names = "hosc", "losc", "iosc", "pll-periph"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - r_watchdog: watchdog@7020400 { - compatible = "allwinner,sun50i-h6-wdt", - "allwinner,sun6i-a31-wdt"; - reg = <0x07020400 0x20>; - interrupts = ; - clocks = <&osc24M>; - }; - - r_intc: interrupt-controller@7021000 { - compatible = "allwinner,sun50i-h6-r-intc", - "allwinner,sun6i-a31-r-intc"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x07021000 0x400>; - interrupts = ; - }; - - r_pio: pinctrl@7022000 { - compatible = "allwinner,sun50i-h6-r-pinctrl"; - reg = <0x07022000 0x400>; - interrupts = , - ; - clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - r_i2c_pins: r-i2c-pins { - pins = "PL0", "PL1"; - function = "s_i2c"; - }; - - r_ir_rx_pin: r-ir-rx-pin { - pins = "PL9"; - function = "s_cir_rx"; - }; - }; - - r_ir: ir@7040000 { - compatible = "allwinner,sun50i-h6-ir", - "allwinner,sun6i-a31-ir"; - reg = <0x07040000 0x400>; - interrupts = ; - clocks = <&r_ccu CLK_R_APB1_IR>, - <&r_ccu CLK_IR>; - clock-names = "apb", "ir"; - resets = <&r_ccu RST_R_APB1_IR>; - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_rx_pin>; - status = "disabled"; - }; - - r_i2c: i2c@7081400 { - compatible = "allwinner,sun50i-h6-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x07081400 0x400>; - interrupts = ; - clocks = <&r_ccu CLK_R_APB2_I2C>; - resets = <&r_ccu RST_R_APB2_I2C>; - pinctrl-names = "default"; - pinctrl-0 = <&r_i2c_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - ths: thermal-sensor@5070400 { - compatible = "allwinner,sun50i-h6-ths"; - reg = <0x05070400 0x100>; - interrupts = ; - clocks = <&ccu CLK_BUS_THS>; - clock-names = "bus"; - resets = <&ccu RST_BUS_THS>; - nvmem-cells = <&ths_calibration>; - nvmem-cell-names = "calibration"; - #thermal-sensor-cells = <1>; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 0>; - - trips { - cpu_alert: cpu-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu-crit { - temperature = <100000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 1>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/altera/Makefile b/arch/arm64/boot/dts/altera/Makefile deleted file mode 100644 index 10119c7ab..000000000 --- a/arch/arm64/boot/dts/altera/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -dtb-$(CONFIG_ARCH_STRATIX10) += socfpga_stratix10_socdk.dtb \ - socfpga_stratix10_socdk_nand.dtb diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi deleted file mode 100644 index 0f893984c..000000000 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ /dev/null @@ -1,623 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright Altera Corporation (C) 2015. All rights reserved. - */ - -/dts-v1/; -#include -#include -#include - -/ { - compatible = "altr,socfpga-stratix10"; - #address-cells = <2>; - #size-cells = <2>; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - service_reserved: svcbuffer@0 { - compatible = "shared-dma-pool"; - reg = <0x0 0x0 0x0 0x1000000>; - alignment = <0x1000>; - no-map; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x1>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x3>; - }; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <0 170 4>, - <0 171 4>, - <0 172 4>, - <0 173 4>; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - interrupt-parent = <&intc>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - intc: interrupt-controller@fffc1000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0xfffc1000 0x0 0x1000>, - <0x0 0xfffc2000 0x0 0x2000>, - <0x0 0xfffc4000 0x0 0x2000>, - <0x0 0xfffc6000 0x0 0x2000>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - device_type = "soc"; - interrupt-parent = <&intc>; - ranges = <0 0 0 0xffffffff>; - - base_fpga_region { - #address-cells = <0x1>; - #size-cells = <0x1>; - - compatible = "fpga-region"; - fpga-mgr = <&fpga_mgr>; - }; - - clkmgr: clock-controller@ffd10000 { - compatible = "intel,stratix10-clkmgr"; - reg = <0xffd10000 0x1000>; - #clock-cells = <1>; - }; - - clocks { - cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - cb_intosc_ls_clk: cb-intosc-ls-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - f2s_free_clk: f2s-free-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - osc1: osc1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - qspi_clk: qspi-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; - }; - - gmac0: ethernet@ff800000 { - compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; - reg = <0xff800000 0x2000>; - interrupts = <0 90 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; - clock-names = "stmmaceth", "ptp_ref"; - tx-fifo-depth = <16384>; - rx-fifo-depth = <16384>; - snps,multicast-filter-bins = <256>; - iommus = <&smmu 1>; - altr,sysmgr-syscon = <&sysmgr 0x44 0>; - status = "disabled"; - }; - - gmac1: ethernet@ff802000 { - compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; - reg = <0xff802000 0x2000>; - interrupts = <0 91 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; - clock-names = "stmmaceth", "ptp_ref"; - tx-fifo-depth = <16384>; - rx-fifo-depth = <16384>; - snps,multicast-filter-bins = <256>; - iommus = <&smmu 2>; - altr,sysmgr-syscon = <&sysmgr 0x48 8>; - status = "disabled"; - }; - - gmac2: ethernet@ff804000 { - compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; - reg = <0xff804000 0x2000>; - interrupts = <0 92 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; - clock-names = "stmmaceth", "ptp_ref"; - tx-fifo-depth = <16384>; - rx-fifo-depth = <16384>; - snps,multicast-filter-bins = <256>; - iommus = <&smmu 3>; - altr,sysmgr-syscon = <&sysmgr 0x4c 16>; - status = "disabled"; - }; - - gpio0: gpio@ffc03200 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc03200 0x100>; - resets = <&rst GPIO0_RESET>; - status = "disabled"; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <24>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 110 4>; - }; - }; - - gpio1: gpio@ffc03300 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc03300 0x100>; - resets = <&rst GPIO1_RESET>; - status = "disabled"; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <24>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 111 4>; - }; - }; - - i2c0: i2c@ffc02800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02800 0x100>; - interrupts = <0 103 4>; - resets = <&rst I2C0_RESET>; - clocks = <&clkmgr STRATIX10_L4_SP_CLK>; - status = "disabled"; - }; - - i2c1: i2c@ffc02900 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02900 0x100>; - interrupts = <0 104 4>; - resets = <&rst I2C1_RESET>; - clocks = <&clkmgr STRATIX10_L4_SP_CLK>; - status = "disabled"; - }; - - i2c2: i2c@ffc02a00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02a00 0x100>; - interrupts = <0 105 4>; - resets = <&rst I2C2_RESET>; - clocks = <&clkmgr STRATIX10_L4_SP_CLK>; - status = "disabled"; - }; - - i2c3: i2c@ffc02b00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02b00 0x100>; - interrupts = <0 106 4>; - resets = <&rst I2C3_RESET>; - clocks = <&clkmgr STRATIX10_L4_SP_CLK>; - status = "disabled"; - }; - - i2c4: i2c@ffc02c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02c00 0x100>; - interrupts = <0 107 4>; - resets = <&rst I2C4_RESET>; - clocks = <&clkmgr STRATIX10_L4_SP_CLK>; - status = "disabled"; - }; - - mmc: dwmmc0@ff808000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "altr,socfpga-dw-mshc"; - reg = <0xff808000 0x1000>; - interrupts = <0 96 4>; - fifo-depth = <0x400>; - resets = <&rst SDMMC_RESET>; - reset-names = "reset"; - clocks = <&clkmgr STRATIX10_L4_MP_CLK>, - <&clkmgr STRATIX10_SDMMC_CLK>; - clock-names = "biu", "ciu"; - iommus = <&smmu 5>; - status = "disabled"; - }; - - nand: nand-controller@ffb90000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "altr,socfpga-denali-nand"; - reg = <0xffb90000 0x10000>, - <0xffb80000 0x1000>; - reg-names = "nand_data", "denali_reg"; - interrupts = <0 97 4>; - clocks = <&clkmgr STRATIX10_NAND_CLK>, - <&clkmgr STRATIX10_NAND_X_CLK>, - <&clkmgr STRATIX10_NAND_ECC_CLK>; - clock-names = "nand", "nand_x", "ecc"; - resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; - status = "disabled"; - }; - - ocram: sram@ffe00000 { - compatible = "mmio-sram"; - reg = <0xffe00000 0x100000>; - }; - - pdma: pdma@ffda0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xffda0000 0x1000>; - interrupts = <0 81 4>, - <0 82 4>, - <0 83 4>, - <0 84 4>, - <0 85 4>, - <0 86 4>, - <0 87 4>, - <0 88 4>, - <0 89 4>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; - clock-names = "apb_pclk"; - resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; - reset-names = "dma", "dma-ocp"; - }; - - rst: rstmgr@ffd11000 { - #reset-cells = <1>; - compatible = "altr,stratix10-rst-mgr"; - reg = <0xffd11000 0x1000>; - }; - - smmu: iommu@fa000000 { - compatible = "arm,mmu-500", "arm,smmu-v2"; - reg = <0xfa000000 0x40000>; - #global-interrupts = <2>; - #iommu-cells = <1>; - clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; - clock-names = "iommu"; - interrupt-parent = <&intc>; - interrupts = <0 128 4>, /* Global Secure Fault */ - <0 129 4>, /* Global Non-secure Fault */ - /* Non-secure Context Interrupts (32) */ - <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, - <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, - <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, - <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, - <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, - <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, - <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, - <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; - stream-match-mask = <0x7ff0>; - status = "disabled"; - }; - - spi0: spi@ffda4000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xffda4000 0x1000>; - interrupts = <0 99 4>; - resets = <&rst SPIM0_RESET>; - reset-names = "spi"; - reg-io-width = <4>; - num-cs = <4>; - clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; - status = "disabled"; - }; - - spi1: spi@ffda5000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xffda5000 0x1000>; - interrupts = <0 100 4>; - resets = <&rst SPIM1_RESET>; - reset-names = "spi"; - reg-io-width = <4>; - num-cs = <4>; - clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; - status = "disabled"; - }; - - sysmgr: sysmgr@ffd12000 { - compatible = "altr,sys-mgr-s10","altr,sys-mgr"; - reg = <0xffd12000 0x228>; - }; - - /* Local timer */ - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - timer0: timer0@ffc03000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 113 4>; - reg = <0xffc03000 0x100>; - clocks = <&clkmgr STRATIX10_L4_SP_CLK>; - clock-names = "timer"; - }; - - timer1: timer1@ffc03100 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 114 4>; - reg = <0xffc03100 0x100>; - clocks = <&clkmgr STRATIX10_L4_SP_CLK>; - clock-names = "timer"; - }; - - timer2: timer2@ffd00000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 115 4>; - reg = <0xffd00000 0x100>; - clocks = <&clkmgr STRATIX10_L4_SP_CLK>; - clock-names = "timer"; - }; - - timer3: timer3@ffd00100 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 116 4>; - reg = <0xffd00100 0x100>; - clocks = <&clkmgr STRATIX10_L4_SP_CLK>; - clock-names = "timer"; - }; - - uart0: serial@ffc02000 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02000 0x100>; - interrupts = <0 108 4>; - reg-shift = <2>; - reg-io-width = <4>; - resets = <&rst UART0_RESET>; - clocks = <&clkmgr STRATIX10_L4_SP_CLK>; - status = "disabled"; - }; - - uart1: serial@ffc02100 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02100 0x100>; - interrupts = <0 109 4>; - reg-shift = <2>; - reg-io-width = <4>; - resets = <&rst UART1_RESET>; - clocks = <&clkmgr STRATIX10_L4_SP_CLK>; - status = "disabled"; - }; - - usbphy0: usbphy@0 { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - status = "okay"; - }; - - usb0: usb@ffb00000 { - compatible = "snps,dwc2"; - reg = <0xffb00000 0x40000>; - interrupts = <0 93 4>; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; - reset-names = "dwc2", "dwc2-ecc"; - clocks = <&clkmgr STRATIX10_USB_CLK>; - iommus = <&smmu 6>; - status = "disabled"; - }; - - usb1: usb@ffb40000 { - compatible = "snps,dwc2"; - reg = <0xffb40000 0x40000>; - interrupts = <0 94 4>; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; - reset-names = "dwc2", "dwc2-ecc"; - clocks = <&clkmgr STRATIX10_USB_CLK>; - iommus = <&smmu 7>; - status = "disabled"; - }; - - watchdog0: watchdog@ffd00200 { - compatible = "snps,dw-wdt"; - reg = <0xffd00200 0x100>; - interrupts = <0 117 4>; - resets = <&rst WATCHDOG0_RESET>; - clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; - status = "disabled"; - }; - - watchdog1: watchdog@ffd00300 { - compatible = "snps,dw-wdt"; - reg = <0xffd00300 0x100>; - interrupts = <0 118 4>; - resets = <&rst WATCHDOG1_RESET>; - clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; - status = "disabled"; - }; - - watchdog2: watchdog@ffd00400 { - compatible = "snps,dw-wdt"; - reg = <0xffd00400 0x100>; - interrupts = <0 125 4>; - resets = <&rst WATCHDOG2_RESET>; - clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; - status = "disabled"; - }; - - watchdog3: watchdog@ffd00500 { - compatible = "snps,dw-wdt"; - reg = <0xffd00500 0x100>; - interrupts = <0 126 4>; - resets = <&rst WATCHDOG3_RESET>; - clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; - status = "disabled"; - }; - - sdr: sdr@f8011100 { - compatible = "altr,sdr-ctl", "syscon"; - reg = <0xf8011100 0xc0>; - }; - - eccmgr { - compatible = "altr,socfpga-s10-ecc-manager", - "altr,socfpga-a10-ecc-manager"; - altr,sysmgr-syscon = <&sysmgr>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = <0 15 4>; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - sdramedac { - compatible = "altr,sdram-edac-s10"; - altr,sdr-syscon = <&sdr>; - interrupts = <16 4>; - }; - - ocram-ecc@ff8cc000 { - compatible = "altr,socfpga-s10-ocram-ecc", - "altr,socfpga-a10-ocram-ecc"; - reg = <0xff8cc000 0x100>; - altr,ecc-parent = <&ocram>; - interrupts = <1 4>; - }; - - usb0-ecc@ff8c4000 { - compatible = "altr,socfpga-s10-usb-ecc", - "altr,socfpga-usb-ecc"; - reg = <0xff8c4000 0x100>; - altr,ecc-parent = <&usb0>; - interrupts = <2 4>; - }; - - emac0-rx-ecc@ff8c0000 { - compatible = "altr,socfpga-s10-eth-mac-ecc", - "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0000 0x100>; - altr,ecc-parent = <&gmac0>; - interrupts = <4 4>; - }; - - emac0-tx-ecc@ff8c0400 { - compatible = "altr,socfpga-s10-eth-mac-ecc", - "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0400 0x100>; - altr,ecc-parent = <&gmac0>; - interrupts = <5 4>; - }; - - }; - - qspi: spi@ff8d2000 { - compatible = "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff8d2000 0x100>, - <0xff900000 0x100000>; - interrupts = <0 3 4>; - cdns,fifo-depth = <128>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x00000000>; - clocks = <&qspi_clk>; - - status = "disabled"; - }; - - firmware { - svc { - compatible = "intel,stratix10-svc"; - method = "smc"; - memory-region = <&service_reserved>; - - fpga_mgr: fpga-mgr { - compatible = "intel,stratix10-soc-fpga-mgr"; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts deleted file mode 100644 index 46e558ab7..000000000 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ /dev/null @@ -1,191 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright Altera Corporation (C) 2015. All rights reserved. - */ - -#include "socfpga_stratix10.dtsi" - -/ { - model = "SoCFPGA Stratix 10 SoCDK"; - - aliases { - serial0 = &uart0; - ethernet0 = &gmac0; - ethernet1 = &gmac1; - ethernet2 = &gmac2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - hps0 { - label = "hps_led0"; - gpios = <&portb 20 GPIO_ACTIVE_HIGH>; - }; - - hps1 { - label = "hps_led1"; - gpios = <&portb 19 GPIO_ACTIVE_HIGH>; - }; - - hps2 { - label = "hps_led2"; - gpios = <&portb 21 GPIO_ACTIVE_HIGH>; - }; - }; - - memory { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; - }; - - ref_033v: 033-v-ref { - compatible = "regulator-fixed"; - regulator-name = "0.33V"; - regulator-min-microvolt = <330000>; - regulator-max-microvolt = <330000>; - }; - - soc { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - - eccmgr { - sdmmca-ecc@ff8c8c00 { - compatible = "altr,socfpga-s10-sdmmc-ecc", - "altr,socfpga-sdmmc-ecc"; - reg = <0xff8c8c00 0x100>; - altr,ecc-parent = <&mmc>; - interrupts = <14 4>, - <15 4>; - }; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - - max-frame-size = <9000>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <4>; - - txd0-skew-ps = <0>; /* -420ps */ - txd1-skew-ps = <0>; /* -420ps */ - txd2-skew-ps = <0>; /* -420ps */ - txd3-skew-ps = <0>; /* -420ps */ - rxd0-skew-ps = <420>; /* 0ps */ - rxd1-skew-ps = <420>; /* 0ps */ - rxd2-skew-ps = <420>; /* 0ps */ - rxd3-skew-ps = <420>; /* 0ps */ - txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <900>; /* 0ps */ - rxdv-skew-ps = <420>; /* 0ps */ - rxc-skew-ps = <1680>; /* 780ps */ - }; - }; -}; - -&mmc { - status = "okay"; - cap-sd-highspeed; - cap-mmc-highspeed; - broken-cd; - bus-width = <4>; -}; - -&uart0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - disable-over-current; -}; - -&watchdog0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <100000>; - i2c-sda-falling-time-ns = <890>; /* hcnt */ - i2c-sdl-falling-time-ns = <890>; /* lcnt */ - - adc@14 { - compatible = "lltc,ltc2497"; - reg = <0x14>; - vref-supply = <&ref_033v>; - }; - - temp@4c { - compatible = "maxim,max1619"; - reg = <0x4c>; - }; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; - - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&qspi { - status = "okay"; - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,mt25qu02g", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <100000000>; - - m25p,fast-read; - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <1>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - qspi_boot: partition@0 { - label = "Boot and fpga data"; - reg = <0x0 0x03FE0000>; - }; - - qspi_rootfs: partition@3FE0000 { - label = "Root Filesystem - JFFS2"; - reg = <0x03FE0000 0x0C020000>; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts deleted file mode 100644 index f9b4a3968..000000000 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts +++ /dev/null @@ -1,224 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright Altera Corporation (C) 2015. All rights reserved. - */ - -#include "socfpga_stratix10.dtsi" - -/ { - model = "SoCFPGA Stratix 10 SoCDK"; - - aliases { - serial0 = &uart0; - ethernet0 = &gmac0; - ethernet1 = &gmac1; - ethernet2 = &gmac2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - hps0 { - label = "hps_led0"; - gpios = <&portb 20 GPIO_ACTIVE_HIGH>; - }; - - hps1 { - label = "hps_led1"; - gpios = <&portb 19 GPIO_ACTIVE_HIGH>; - }; - - hps2 { - label = "hps_led2"; - gpios = <&portb 21 GPIO_ACTIVE_HIGH>; - }; - }; - - memory { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; - }; - - ref_033v: 033-v-ref { - compatible = "regulator-fixed"; - regulator-name = "0.33V"; - regulator-min-microvolt = <330000>; - regulator-max-microvolt = <330000>; - }; - - soc { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - - eccmgr { - sdmmca-ecc@ff8c8c00 { - compatible = "altr,socfpga-s10-sdmmc-ecc", - "altr,socfpga-sdmmc-ecc"; - reg = <0xff8c8c00 0x100>; - altr,ecc-parent = <&mmc>; - interrupts = <14 4>, - <15 4>; - }; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&gmac2 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - - max-frame-size = <9000>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <4>; - - txd0-skew-ps = <0>; /* -420ps */ - txd1-skew-ps = <0>; /* -420ps */ - txd2-skew-ps = <0>; /* -420ps */ - txd3-skew-ps = <0>; /* -420ps */ - rxd0-skew-ps = <420>; /* 0ps */ - rxd1-skew-ps = <420>; /* 0ps */ - rxd2-skew-ps = <420>; /* 0ps */ - rxd3-skew-ps = <420>; /* 0ps */ - txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <900>; /* 0ps */ - rxdv-skew-ps = <420>; /* 0ps */ - rxc-skew-ps = <1680>; /* 780ps */ - }; - }; -}; - -&nand { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - nand-bus-width = <16>; - - partition@0 { - label = "u-boot"; - reg = <0 0x200000>; - }; - - partition@200000 { - label = "env"; - reg = <0x200000 0x40000>; - }; - - partition@240000 { - label = "dtb"; - reg = <0x240000 0x40000>; - }; - - partition@280000 { - label = "kernel"; - reg = <0x280000 0x2000000>; - }; - - partition@2280000 { - label = "misc"; - reg = <0x2280000 0x2000000>; - }; - - partition@4280000 { - label = "rootfs"; - reg = <0x4280000 0x3bd80000>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - disable-over-current; -}; - -&watchdog0 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - clock-frequency = <100000>; - i2c-sda-falling-time-ns = <890>; /* hcnt */ - i2c-sdl-falling-time-ns = <890>; /* lcnt */ - - adc@14 { - compatible = "lltc,ltc2497"; - reg = <0x14>; - vref-supply = <&ref_033v>; - }; - - temp@4c { - compatible = "maxim,max1619"; - reg = <0x4c>; - }; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; - - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&qspi { - status = "okay"; - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,mt25qu02g", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <100000000>; - - m25p,fast-read; - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <1>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - qspi_boot: partition@0 { - label = "Boot and fpga data"; - reg = <0x0 0x03FE0000>; - }; - - qspi_rootfs: partition@3FE0000 { - label = "Root Filesystem - JFFS2"; - reg = <0x03FE0000 0x0C020000>; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/amazon/Makefile b/arch/arm64/boot/dts/amazon/Makefile deleted file mode 100644 index ba9e11544..000000000 --- a/arch/arm64/boot/dts/amazon/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -dtb-$(CONFIG_ARCH_ALPINE) += alpine-v2-evp.dtb -dtb-$(CONFIG_ARCH_ALPINE) += alpine-v3-evp.dtb diff --git a/arch/arm64/boot/dts/amazon/alpine-v2-evp.dts b/arch/arm64/boot/dts/amazon/alpine-v2-evp.dts deleted file mode 100644 index a079d7b30..000000000 --- a/arch/arm64/boot/dts/amazon/alpine-v2-evp.dts +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Antoine Tenart - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the - * BSD license below: - * - * Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * - Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * - * - Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#include "alpine-v2.dtsi" - -/ { - model = "Annapurna Labs Alpine v2 EVP"; - compatible = "al,alpine-v2-evp", "al,alpine-v2"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi deleted file mode 100644 index 4eb2cd14e..000000000 --- a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi +++ /dev/null @@ -1,236 +0,0 @@ -/* - * Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Antoine Tenart - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the - * BSD license below: - * - * Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * - Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * - * - Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -/dts-v1/; - -#include - -/ { - model = "Annapurna Labs Alpine v2"; - compatible = "al,alpine-v2"; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a57"; - device_type = "cpu"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu@1 { - compatible = "arm,cortex-a57"; - device_type = "cpu"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu@2 { - compatible = "arm,cortex-a57"; - device_type = "cpu"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu@3 { - compatible = "arm,cortex-a57"; - device_type = "cpu"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-0.2", "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000001>; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; - }; - - sbclk: sbclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - - interrupt-parent = <&gic>; - ranges; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - }; - - gic: interrupt-controller@f0200000 { - compatible = "arm,gic-v3"; - reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */ - <0x0 0xf0280000 0x0 0x200000>, /* GICR */ - <0x0 0xf0100000 0x0 0x2000>, /* GICC */ - <0x0 0xf0110000 0x0 0x2000>, /* GICV */ - <0x0 0xf0120000 0x0 0x2000>; /* GICH */ - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - - pci@fbc00000 { - compatible = "pci-host-ecam-generic"; - device_type = "pci"; - #size-cells = <2>; - #address-cells = <3>; - #interrupt-cells = <1>; - reg = <0x0 0xfbc00000 0x0 0x100000>; - interrupt-map-mask = <0xf800 0 0 7>; - /* add legacy interrupts for SATA only */ - interrupt-map = <0x4000 0 0 1 &gic 0 53 4>, - <0x4800 0 0 1 &gic 0 54 4>; - /* 32 bit non prefetchable memory space */ - ranges = <0x2000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>; - bus-range = <0x00 0x00>; - msi-parent = <&msix>; - }; - - msix: msix@fbe00000 { - compatible = "al,alpine-msix"; - reg = <0x0 0xfbe00000 0x0 0x100000>; - interrupt-controller; - msi-controller; - al,msi-base-spi = <160>; - al,msi-num-spis = <160>; - }; - - io-fabric { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0xfc000000 0x2000000>; - - uart0: serial@1883000 { - compatible = "ns16550a"; - device_type = "serial"; - reg = <0x1883000 0x1000>; - interrupts = ; - clock-frequency = <500000000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: serial@1884000 { - compatible = "ns16550a"; - device_type = "serial"; - reg = <0x1884000 0x1000>; - interrupts = ; - clock-frequency = <500000000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@1885000 { - compatible = "ns16550a"; - device_type = "serial"; - reg = <0x1885000 0x1000>; - interrupts = ; - clock-frequency = <500000000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart3: serial@1886000 { - compatible = "ns16550a"; - device_type = "serial"; - reg = <0x1886000 0x1000>; - interrupts = ; - clock-frequency = <500000000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - timer0: timer@1890000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x1890000 0x1000>; - interrupts = ; - clocks = <&sbclk>; - }; - - timer1: timer@1891000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x1891000 0x1000>; - interrupts = ; - clocks = <&sbclk>; - status = "disabled"; - }; - - timer2: timer@1892000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x1892000 0x1000>; - interrupts = ; - clocks = <&sbclk>; - status = "disabled"; - }; - - timer3: timer@1893000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x1893000 0x1000>; - interrupts = ; - clocks = <&sbclk>; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/amazon/alpine-v3-evp.dts b/arch/arm64/boot/dts/amazon/alpine-v3-evp.dts deleted file mode 100644 index 48078f5ea..000000000 --- a/arch/arm64/boot/dts/amazon/alpine-v3-evp.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. - */ - -#include "alpine-v3.dtsi" - -/ { - model = "Amazon's Annapurna Labs Alpine v3 Evaluation Platform (EVP)"; - compatible = "amazon,al-alpine-v3-evp", "amazon,al-alpine-v3"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi deleted file mode 100644 index 73a352ea8..000000000 --- a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi +++ /dev/null @@ -1,408 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2020, Amazon.com, Inc. or its affiliates. All Rights Reserved - */ - -/dts-v1/; - -#include - -/ { - model = "Amazon's Annapurna Labs Alpine v3"; - compatible = "amazon,al-alpine-v3"; - - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0>; - enable-method = "psci"; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - next-level-cache = <&cluster0_l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x1>; - enable-method = "psci"; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - next-level-cache = <&cluster0_l2>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x2>; - enable-method = "psci"; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - next-level-cache = <&cluster0_l2>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x3>; - enable-method = "psci"; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - next-level-cache = <&cluster0_l2>; - }; - - cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x100>; - enable-method = "psci"; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - next-level-cache = <&cluster1_l2>; - }; - - cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x101>; - enable-method = "psci"; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - next-level-cache = <&cluster1_l2>; - }; - - cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x102>; - enable-method = "psci"; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - next-level-cache = <&cluster1_l2>; - }; - - cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x103>; - enable-method = "psci"; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - next-level-cache = <&cluster1_l2>; - }; - - cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x200>; - enable-method = "psci"; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - next-level-cache = <&cluster2_l2>; - }; - - cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x201>; - enable-method = "psci"; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - next-level-cache = <&cluster2_l2>; - }; - - cpu@202 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x202>; - enable-method = "psci"; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - next-level-cache = <&cluster2_l2>; - }; - - cpu@203 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x203>; - enable-method = "psci"; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - next-level-cache = <&cluster2_l2>; - }; - - cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x300>; - enable-method = "psci"; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - next-level-cache = <&cluster3_l2>; - }; - - cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x301>; - enable-method = "psci"; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - next-level-cache = <&cluster3_l2>; - }; - - cpu@302 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x302>; - enable-method = "psci"; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - next-level-cache = <&cluster3_l2>; - }; - - cpu@303 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x303>; - enable-method = "psci"; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - next-level-cache = <&cluster3_l2>; - }; - - cluster0_l2: cache@0 { - compatible = "cache"; - cache-size = <0x200000>; - cache-line-size = <64>; - cache-sets = <2048>; - cache-level = <2>; - }; - - cluster1_l2: cache@100 { - compatible = "cache"; - cache-size = <0x200000>; - cache-line-size = <64>; - cache-sets = <2048>; - cache-level = <2>; - }; - - cluster2_l2: cache@200 { - compatible = "cache"; - cache-size = <0x200000>; - cache-line-size = <64>; - cache-sets = <2048>; - cache-level = <2>; - }; - - cluster3_l2: cache@300 { - compatible = "cache"; - cache-size = <0x200000>; - cache-line-size = <64>; - cache-sets = <2048>; - cache-level = <2>; - }; - - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secmon@0 { - reg = <0x0 0x0 0x0 0x100000>; - no-map; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a72-pmu"; - interrupts = ; - }; - - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gic: interrupt-controller@f0000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0xf0800000 0 0x10000>, /* GICD */ - <0x0 0xf0a00000 0 0x200000>, /* GICR */ - <0x0 0xf0000000 0 0x2000>, /* GICC */ - <0x0 0xf0010000 0 0x1000>, /* GICH */ - <0x0 0xf0020000 0 0x2000>; /* GICV */ - interrupts = ; - }; - - pcie@fbd00000 { - compatible = "pci-host-ecam-generic"; - device_type = "pci"; - #size-cells = <2>; - #address-cells = <3>; - #interrupt-cells = <1>; - reg = <0x0 0xfbd00000 0x0 0x100000>; - interrupt-map-mask = <0xf800 0 0 7>; - /* 8 x legacy interrupts for SATA only */ - interrupt-map = <0x4000 0 0 1 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>, - <0x4800 0 0 1 &gic 0 58 IRQ_TYPE_LEVEL_HIGH>, - <0x5000 0 0 1 &gic 0 59 IRQ_TYPE_LEVEL_HIGH>, - <0x5800 0 0 1 &gic 0 60 IRQ_TYPE_LEVEL_HIGH>, - <0x6000 0 0 1 &gic 0 61 IRQ_TYPE_LEVEL_HIGH>, - <0x6800 0 0 1 &gic 0 62 IRQ_TYPE_LEVEL_HIGH>, - <0x7000 0 0 1 &gic 0 63 IRQ_TYPE_LEVEL_HIGH>, - <0x7800 0 0 1 &gic 0 64 IRQ_TYPE_LEVEL_HIGH>; - ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>; - bus-range = <0x00 0x00>; - msi-parent = <&msix>; - }; - - msix: msix@fbe00000 { - compatible = "al,alpine-msix"; - reg = <0x0 0xfbe00000 0x0 0x100000>; - interrupt-controller; - msi-controller; - al,msi-base-spi = <336>; - al,msi-num-spis = <959>; - interrupt-parent = <&gic>; - }; - - io-fabric { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0xfc000000 0x2000000>; - - uart0: serial@1883000 { - compatible = "ns16550a"; - reg = <0x1883000 0x1000>; - interrupts = ; - clock-frequency = <0>; /* Filled by firmware */ - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: serial@1884000 { - compatible = "ns16550a"; - reg = <0x1884000 0x1000>; - interrupts = ; - clock-frequency = <0>; /* Filled by firmware */ - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@1885000 { - compatible = "ns16550a"; - reg = <0x1885000 0x1000>; - interrupts = ; - clock-frequency = <0>; /* Filled by firmware */ - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart3: serial@1886000 { - compatible = "ns16550a"; - reg = <0x1886000 0x1000>; - interrupts = ; - clock-frequency = <0>; /* Filled by firmware */ - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile deleted file mode 100644 index 6a6093064..000000000 --- a/arch/arm64/boot/dts/amd/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive.dtb \ - amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb \ - husky.dtb diff --git a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts deleted file mode 100644 index 8e341be9a..000000000 --- a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DTS file for AMD Seattle Overdrive Development Board - * Note: For Seattle Rev.B0 - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - */ - -/dts-v1/; - -/include/ "amd-seattle-soc.dtsi" - -/ { - model = "AMD Seattle (Rev.B0) Development Board (Overdrive)"; - compatible = "amd,seattle-overdrive", "amd,seattle"; - - chosen { - stdout-path = &serial0; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; -}; - -&ccp0 { - status = "ok"; - amd,zlib-support = <1>; -}; - -/** - * NOTE: In Rev.B, gpio0 is reserved. - */ -&gpio1 { - status = "ok"; -}; - -&gpio2 { - status = "ok"; -}; - -&gpio3 { - status = "ok"; -}; - -&gpio4 { - status = "ok"; -}; - -&i2c0 { - status = "ok"; -}; - -&i2c1 { - status = "ok"; -}; - -&pcie0 { - status = "ok"; -}; - -&spi0 { - status = "ok"; -}; - -&spi1 { - status = "ok"; - sdcard0: sdcard@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3200 3400>; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,com-mode = <0x0>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - }; -}; - -&ipmi_kcs { - status = "ok"; -}; - -&smb0 { - /include/ "amd-seattle-xgbe-b.dtsi" -}; diff --git a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts deleted file mode 100644 index 92cef05c6..000000000 --- a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DTS file for AMD Seattle Overdrive Development Board - * Note: For Seattle Rev.B1 - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - */ - -/dts-v1/; - -/include/ "amd-seattle-soc.dtsi" - -/ { - model = "AMD Seattle (Rev.B1) Development Board (Overdrive)"; - compatible = "amd,seattle-overdrive", "amd,seattle"; - - chosen { - stdout-path = &serial0; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; -}; - -&ccp0 { - status = "ok"; - amd,zlib-support = <1>; -}; - -/** - * NOTE: In Rev.B, gpio0 is reserved. - */ -&gpio1 { - status = "ok"; -}; - -&gpio2 { - status = "ok"; -}; - -&gpio3 { - status = "ok"; -}; - -&gpio4 { - status = "ok"; -}; - -&i2c0 { - status = "ok"; -}; - -&i2c1 { - status = "ok"; -}; - -&pcie0 { - status = "ok"; -}; - -&sata1 { - status = "ok"; -}; - -&spi0 { - status = "ok"; -}; - -&spi1 { - status = "ok"; - sdcard0: sdcard@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3200 3400>; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,com-mode = <0x0>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - }; -}; - -&ipmi_kcs { - status = "ok"; -}; - -&smb0 { - /include/ "amd-seattle-xgbe-b.dtsi" -}; diff --git a/arch/arm64/boot/dts/amd/amd-overdrive.dts b/arch/arm64/boot/dts/amd/amd-overdrive.dts deleted file mode 100644 index 41b3a6c09..000000000 --- a/arch/arm64/boot/dts/amd/amd-overdrive.dts +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DTS file for AMD Seattle Overdrive Development Board - * - * Copyright (C) 2014 Advanced Micro Devices, Inc. - */ - -/dts-v1/; - -/include/ "amd-seattle-soc.dtsi" - -/ { - model = "AMD Seattle Development Board (Overdrive)"; - compatible = "amd,seattle-overdrive", "amd,seattle"; - - chosen { - stdout-path = &serial0; - }; -}; - -&ccp0 { - status = "ok"; -}; - -&gpio0 { - status = "ok"; -}; - -&gpio1 { - status = "ok"; -}; - -&i2c0 { - status = "ok"; -}; - -&pcie0 { - status = "ok"; -}; - -&spi0 { - status = "ok"; -}; - -&spi1 { - status = "ok"; - sdcard0: sdcard@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3200 3400>; - gpios = <&gpio0 7 0>; - interrupt-parent = <&gpio0>; - interrupts = <7 3>; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,com-mode = <0x0>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - }; -}; - -&v2m0 { - arm,msi-base-spi = <64>; - arm,msi-num-spis = <256>; -}; diff --git a/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi deleted file mode 100644 index 2dd2c2817..000000000 --- a/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DTS file for AMD Seattle Clocks - * - * Copyright (C) 2014 Advanced Micro Devices, Inc. - */ - - adl3clk_100mhz: clk100mhz_0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "adl3clk_100mhz"; - }; - - ccpclk_375mhz: clk375mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <375000000>; - clock-output-names = "ccpclk_375mhz"; - }; - - sataclk_333mhz: clk333mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <333000000>; - clock-output-names = "sataclk_333mhz"; - }; - - pcieclk_500mhz: clk500mhz_0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <500000000>; - clock-output-names = "pcieclk_500mhz"; - }; - - dmaclk_500mhz: clk500mhz_1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <500000000>; - clock-output-names = "dmaclk_500mhz"; - }; - - miscclk_250mhz: clk250mhz_4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - clock-output-names = "miscclk_250mhz"; - }; - - uartspiclk_100mhz: clk100mhz_1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "uartspiclk_100mhz"; - }; diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi deleted file mode 100644 index b664e7af7..000000000 --- a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi +++ /dev/null @@ -1,251 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DTS file for AMD Seattle SoC - * - * Copyright (C) 2014 Advanced Micro Devices, Inc. - */ - -/ { - compatible = "amd,seattle"; - interrupt-parent = <&gic0>; - #address-cells = <2>; - #size-cells = <2>; - - gic0: interrupt-controller@e1101000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0xe1110000 0 0x1000>, - <0x0 0xe112f000 0 0x2000>, - <0x0 0xe1140000 0 0x2000>, - <0x0 0xe1160000 0 0x2000>; - interrupts = <1 9 0xf04>; - ranges = <0 0 0 0xe1100000 0 0x100000>; - v2m0: v2m@e0080000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x00080000 0 0x1000>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 0xff04>, - <1 14 0xff04>, - <1 11 0xff04>, - <1 10 0xff04>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <0 7 4>, - <0 8 4>, - <0 9 4>, - <0 10 4>, - <0 11 4>, - <0 12 4>, - <0 13 4>, - <0 14 4>; - }; - - smb0: smb { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* - * dma-ranges is 40-bit address space containing: - * - GICv2m MSI register is at 0xe0080000 - * - DRAM range [0x8000000000 to 0xffffffffff] - */ - dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; - - /include/ "amd-seattle-clks.dtsi" - - sata0: sata@e0300000 { - compatible = "snps,dwc-ahci"; - reg = <0 0xe0300000 0 0xf0000>; - interrupts = <0 355 4>; - clocks = <&sataclk_333mhz>; - dma-coherent; - }; - - /* This is for Rev B only */ - sata1: sata@e0d00000 { - status = "disabled"; - compatible = "snps,dwc-ahci"; - reg = <0 0xe0d00000 0 0xf0000>; - interrupts = <0 354 4>; - clocks = <&sataclk_333mhz>; - dma-coherent; - }; - - i2c0: i2c@e1000000 { - status = "disabled"; - compatible = "snps,designware-i2c"; - reg = <0 0xe1000000 0 0x1000>; - interrupts = <0 357 4>; - clocks = <&miscclk_250mhz>; - }; - - i2c1: i2c@e0050000 { - status = "disabled"; - compatible = "snps,designware-i2c"; - reg = <0 0xe0050000 0 0x1000>; - interrupts = <0 340 4>; - clocks = <&miscclk_250mhz>; - }; - - serial0: serial@e1010000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0 0xe1010000 0 0x1000>; - interrupts = <0 328 4>; - clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - spi0: spi@e1020000 { - status = "disabled"; - compatible = "arm,pl022", "arm,primecell"; - reg = <0 0xe1020000 0 0x1000>; - spi-controller; - interrupts = <0 330 4>; - clocks = <&uartspiclk_100mhz>; - clock-names = "apb_pclk"; - }; - - spi1: spi@e1030000 { - status = "disabled"; - compatible = "arm,pl022", "arm,primecell"; - reg = <0 0xe1030000 0 0x1000>; - spi-controller; - interrupts = <0 329 4>; - clocks = <&uartspiclk_100mhz>; - clock-names = "apb_pclk"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - gpio0: gpio@e1040000 { /* Not available to OS for B0 */ - status = "disabled"; - compatible = "arm,pl061", "arm,primecell"; - #gpio-cells = <2>; - reg = <0 0xe1040000 0 0x1000>; - gpio-controller; - interrupts = <0 359 4>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&miscclk_250mhz>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@e1050000 { /* [0:7] */ - status = "disabled"; - compatible = "arm,pl061", "arm,primecell"; - #gpio-cells = <2>; - reg = <0 0xe1050000 0 0x1000>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 358 4>; - clocks = <&miscclk_250mhz>; - clock-names = "apb_pclk"; - }; - - gpio2: gpio@e0020000 { /* [8:15] */ - status = "disabled"; - compatible = "arm,pl061", "arm,primecell"; - #gpio-cells = <2>; - reg = <0 0xe0020000 0 0x1000>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 366 4>; - clocks = <&miscclk_250mhz>; - clock-names = "apb_pclk"; - }; - - gpio3: gpio@e0030000 { /* [16:23] */ - status = "disabled"; - compatible = "arm,pl061", "arm,primecell"; - #gpio-cells = <2>; - reg = <0 0xe0030000 0 0x1000>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 365 4>; - clocks = <&miscclk_250mhz>; - clock-names = "apb_pclk"; - }; - - gpio4: gpio@e0080000 { /* [24] */ - status = "disabled"; - compatible = "arm,pl061", "arm,primecell"; - #gpio-cells = <2>; - reg = <0 0xe0080000 0 0x1000>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 361 4>; - clocks = <&miscclk_250mhz>; - clock-names = "apb_pclk"; - }; - - ccp0: ccp@e0100000 { - status = "disabled"; - compatible = "amd,ccp-seattle-v1a"; - reg = <0 0xe0100000 0 0x10000>; - interrupts = <0 3 4>; - dma-coherent; - }; - - pcie0: pcie@f0000000 { - compatible = "pci-host-ecam-generic"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - device_type = "pci"; - bus-range = <0 0x7f>; - msi-parent = <&v2m0>; - reg = <0 0xf0000000 0 0x10000000>; - - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; - interrupt-map = - <0x1000 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>, - <0x1000 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>, - <0x1000 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>, - <0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>; - - dma-coherent; - dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>; - ranges = - /* I/O Memory (size=64K) */ - <0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>, - /* 32-bit MMIO (size=2G) */ - <0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>, - /* 64-bit MMIO (size= 124G) */ - <0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>; - }; - - /* Perf CCN504 PMU */ - ccn: ccn@e8000000 { - compatible = "arm,ccn-504"; - reg = <0x0 0xe8000000 0 0x1000000>; - interrupts = <0 380 4>; - }; - - ipmi_kcs: kcs@e0010000 { - status = "disabled"; - compatible = "ipmi-kcs"; - device_type = "ipmi"; - reg = <0x0 0xe0010000 0 0x8>; - interrupts = <0 389 4>; - reg-size = <1>; - reg-spacing = <4>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi deleted file mode 100644 index d97498361..000000000 --- a/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DTS file for AMD Seattle XGBE (RevB) - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - */ - - xgmacclk0_dma_250mhz: clk250mhz_0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk0_dma_250mhz"; - }; - - xgmacclk0_ptp_250mhz: clk250mhz_1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk0_ptp_250mhz"; - }; - - xgmacclk1_dma_250mhz: clk250mhz_2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk1_dma_250mhz"; - }; - - xgmacclk1_ptp_250mhz: clk250mhz_3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk1_ptp_250mhz"; - }; - - xgmac0: xgmac@e0700000 { - compatible = "amd,xgbe-seattle-v1a"; - reg = <0 0xe0700000 0 0x80000>, - <0 0xe0780000 0 0x80000>, - <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */ - <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */ - <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */ - interrupts = <0 325 4>, - <0 346 1>, <0 347 1>, <0 348 1>, <0 349 1>, - <0 323 4>; - amd,per-channel-interrupt; - amd,speed-set = <0>; - amd,serdes-blwc = <1>, <1>, <0>; - amd,serdes-cdr-rate = <2>, <2>, <7>; - amd,serdes-pq-skew = <10>, <10>, <18>; - amd,serdes-tx-amp = <0>, <0>, <0>; - amd,serdes-dfe-tap-config = <3>, <3>, <3>; - amd,serdes-dfe-tap-enable = <0>, <0>, <7>; - mac-address = [ 02 A1 A2 A3 A4 A5 ]; - clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>; - clock-names = "dma_clk", "ptp_clk"; - phy-mode = "xgmii"; - #stream-id-cells = <16>; - dma-coherent; - }; - - xgmac1: xgmac@e0900000 { - compatible = "amd,xgbe-seattle-v1a"; - reg = <0 0xe0900000 0 0x80000>, - <0 0xe0980000 0 0x80000>, - <0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */ - <0 0xe1250080 0 0x00060>, /* SERDES IR 1/2 */ - <0 0xe12500fc 0 0x00004>; /* SERDES IR 2/2 */ - interrupts = <0 324 4>, - <0 341 1>, <0 342 1>, <0 343 1>, <0 344 1>, - <0 322 4>; - amd,per-channel-interrupt; - amd,speed-set = <0>; - amd,serdes-blwc = <1>, <1>, <0>; - amd,serdes-cdr-rate = <2>, <2>, <7>; - amd,serdes-pq-skew = <10>, <10>, <18>; - amd,serdes-tx-amp = <0>, <0>, <0>; - amd,serdes-dfe-tap-config = <3>, <3>, <3>; - amd,serdes-dfe-tap-enable = <0>, <0>, <7>; - mac-address = [ 02 B1 B2 B3 B4 B5 ]; - clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>; - clock-names = "dma_clk", "ptp_clk"; - phy-mode = "xgmii"; - #stream-id-cells = <16>; - dma-coherent; - }; - - xgmac0_smmu: smmu@e0600000 { - compatible = "arm,mmu-401"; - reg = <0 0xe0600000 0 0x10000>; - #global-interrupts = <1>; - interrupts = /* Uses combined intr for both - * global and context - */ - <0 336 4>, - <0 336 4>; - - mmu-masters = <&xgmac0 - 0 1 2 3 4 5 6 7 - 16 17 18 19 20 21 22 23 - >; - }; - - xgmac1_smmu: smmu@e0800000 { - compatible = "arm,mmu-401"; - reg = <0 0xe0800000 0 0x10000>; - #global-interrupts = <1>; - interrupts = /* Uses combined intr for both - * global and context - */ - <0 335 4>, - <0 335 4>; - - mmu-masters = <&xgmac1 - 0 1 2 3 4 5 6 7 - 16 17 18 19 20 21 22 23 - >; - }; diff --git a/arch/arm64/boot/dts/amd/husky.dts b/arch/arm64/boot/dts/amd/husky.dts deleted file mode 100644 index 7acde3477..000000000 --- a/arch/arm64/boot/dts/amd/husky.dts +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DTS file for AMD/Linaro 96Boards Enterprise Edition Server (Husky) Board - * Note: Based-on AMD Seattle Rev.B0 - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - */ - -/dts-v1/; - -/include/ "amd-seattle-soc.dtsi" - -/ { - model = "Linaro 96Boards Enterprise Edition Server (Husky) Board"; - compatible = "amd,seattle-overdrive", "amd,seattle"; - - chosen { - stdout-path = &serial0; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; -}; - -&ccp0 { - status = "ok"; - amd,zlib-support = <1>; -}; - -/** - * NOTE: In Rev.B, gpio0 is reserved. - */ -&gpio1 { - status = "ok"; -}; - -&gpio2 { - status = "ok"; -}; - -&gpio3 { - status = "ok"; -}; - -&gpio4 { - status = "ok"; -}; - -&i2c0 { - status = "ok"; -}; - -&i2c1 { - status = "ok"; -}; - -&pcie0 { - status = "ok"; -}; - -&spi0 { - status = "ok"; -}; - -&spi1 { - status = "ok"; - sdcard0: sdcard@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3200 3400>; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,com-mode = <0x0>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - }; -}; - -&smb0 { - /include/ "amd-seattle-xgbe-b.dtsi" -}; diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile deleted file mode 100644 index ced039463..000000000 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12a-sei510.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12a-x96-max.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking-pro.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2-plus.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12b-ugoos-am6.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-kii-pro.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p200.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p201.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-hub.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-play2.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-libretech-ac.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-hwacom-amazetv.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-khadas-vim.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc-v2.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-phicomm-n1.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-sml5442tw.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-p281.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-tx3-mini.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-libretech-pc.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-libretech-pc.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxm-wetek-core2.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-c4.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts b/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts deleted file mode 100644 index 69c25c68c..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-a1-ad401.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - */ - -/dts-v1/; - -#include "meson-a1.dtsi" - -/ { - compatible = "amlogic,ad401", "amlogic,a1"; - model = "Amlogic Meson A1 AD401 Development Board"; - - aliases { - serial0 = &uart_AO_B; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x8000000>; - }; -}; - -&uart_AO_B { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi deleted file mode 100644 index 755b4ad15..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ /dev/null @@ -1,161 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - */ - -#include -#include -#include - -/ { - compatible = "amlogic,a1"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - - l2: l2-cache0 { - compatible = "cache"; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x0 0x800000>; - alignment = <0x0 0x400000>; - linux,cma-default; - }; - }; - - sm: secure-monitor { - compatible = "amlogic,meson-gxbb-sm"; - - pwrc: power-controller { - compatible = "amlogic,meson-a1-pwrc"; - #power-domain-cells = <1>; - status = "okay"; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - apb: bus@fe000000 { - compatible = "simple-bus"; - reg = <0x0 0xfe000000 0x0 0x1000000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>; - - - reset: reset-controller@0 { - compatible = "amlogic,meson-a1-reset"; - reg = <0x0 0x0 0x0 0x8c>; - #reset-cells = <1>; - }; - - periphs_pinctrl: pinctrl@0400 { - compatible = "amlogic,meson-a1-periphs-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio: bank@0400 { - reg = <0x0 0x0400 0x0 0x003c>, - <0x0 0x0480 0x0 0x0118>; - reg-names = "mux", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&periphs_pinctrl 0 0 62>; - }; - - }; - - uart_AO: serial@1c00 { - compatible = "amlogic,meson-gx-uart", - "amlogic,meson-ao-uart"; - reg = <0x0 0x1c00 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&xtal>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - uart_AO_B: serial@2000 { - compatible = "amlogic,meson-gx-uart", - "amlogic,meson-ao-uart"; - reg = <0x0 0x2000 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&xtal>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - }; - - gic: interrupt-controller@ff901000 { - compatible = "arm,gic-400"; - reg = <0x0 0xff901000 0x0 0x1000>, - <0x0 0xff902000 0x0 0x2000>, - <0x0 0xff904000 0x0 0x2000>, - <0x0 0xff906000 0x0 0x2000>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <3>; - #address-cells = <0>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts deleted file mode 100644 index 7740f97c2..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ /dev/null @@ -1,592 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Amlogic, Inc. All rights reserved. - */ - -/dts-v1/; - -#include "meson-axg.dtsi" -#include - -/ { - compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg"; - model = "Amlogic Meson AXG S400 Development Board"; - - adc_keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-next { - label = "Next"; - linux,code = ; - press-threshold-microvolt = <1116000>; /* 62% */ - }; - - button-prev { - label = "Previous"; - linux,code = ; - press-threshold-microvolt = <900000>; /* 50% */ - }; - - button-wifi { - label = "Wifi"; - linux,code = ; - press-threshold-microvolt = <684000>; /* 38% */ - }; - - button-up { - label = "Volume Up"; - linux,code = ; - press-threshold-microvolt = <468000>; /* 26% */ - }; - - button-down { - label = "Volume Down"; - linux,code = ; - press-threshold-microvolt = <252000>; /* 14% */ - }; - - button-voice { - label = "Voice"; - linux,code = ; - press-threshold-microvolt = <0>; /* 0% */ - }; - }; - - aliases { - serial0 = &uart_AO; - serial1 = &uart_A; - }; - - linein: audio-codec-0 { - #sound-dai-cells = <0>; - compatible = "everest,es7241"; - VDDA-supply = <&vcc_3v3>; - VDDP-supply = <&vcc_3v3>; - VDDD-supply = <&vcc_3v3>; - status = "okay"; - sound-name-prefix = "Linein"; - }; - - lineout: audio-codec-1 { - #sound-dai-cells = <0>; - compatible = "everest,es7154"; - VDD-supply = <&vcc_3v3>; - PVDD-supply = <&vcc_5v>; - status = "okay"; - sound-name-prefix = "Lineout"; - }; - - spdif_dit: audio-codec-2 { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - status = "okay"; - sound-name-prefix = "DIT"; - }; - - dmics: audio-codec-3 { - #sound-dai-cells = <0>; - compatible = "dmic-codec"; - num-channels = <7>; - wakeup-delay-ms = <50>; - status = "okay"; - sound-name-prefix = "MIC"; - }; - - spdif_dir: audio-codec-4 { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dir"; - status = "okay"; - sound-name-prefix = "DIR"; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - main_12v: regulator-main_12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "VCC5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&main_12v>; - - gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&main_12v>; - regulator-always-on; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - usb_pwr: regulator-usb_pwr { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - speaker-leds { - compatible = "gpio-leds"; - - aled1 { - label = "speaker:aled1"; - gpios = <&gpio_speaker 7 0>; - }; - - aled2 { - label = "speaker:aled2"; - gpios = <&gpio_speaker 6 0>; - }; - - aled3 { - label = "speaker:aled3"; - gpios = <&gpio_speaker 5 0>; - }; - - aled4 { - label = "speaker:aled4"; - gpios = <&gpio_speaker 4 0>; - }; - - aled5 { - label = "speaker:aled5"; - gpios = <&gpio_speaker 3 0>; - }; - - aled6 { - label = "speaker:aled6"; - gpios = <&gpio_speaker 2 0>; - }; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "AXG-S400"; - audio-aux-devs = <&tdmin_a>, <&tdmin_b>, <&tdmin_c>, - <&tdmin_lb>, <&tdmout_c>; - audio-widgets = "Line", "Lineout", - "Line", "Linein", - "Speaker", "Speaker1 Left", - "Speaker", "Speaker1 Right"; - audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2", - "SPDIFOUT IN 0", "FRDDR_A OUT 3", - "TDMOUT_C IN 1", "FRDDR_B OUT 2", - "SPDIFOUT IN 1", "FRDDR_B OUT 3", - "TDMOUT_C IN 2", "FRDDR_C OUT 2", - "SPDIFOUT IN 2", "FRDDR_C OUT 3", - "TDM_C Playback", "TDMOUT_C OUT", - "TDMIN_A IN 2", "TDM_C Capture", - "TDMIN_A IN 5", "TDM_C Loopback", - "TDMIN_B IN 2", "TDM_C Capture", - "TDMIN_B IN 5", "TDM_C Loopback", - "TDMIN_C IN 2", "TDM_C Capture", - "TDMIN_C IN 5", "TDM_C Loopback", - "TDMIN_LB IN 2", "TDM_C Loopback", - "TDMIN_LB IN 5", "TDM_C Capture", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT", - "TODDR_A IN 1", "TDMIN_B OUT", - "TODDR_B IN 1", "TDMIN_B OUT", - "TODDR_C IN 1", "TDMIN_B OUT", - "TODDR_A IN 2", "TDMIN_C OUT", - "TODDR_B IN 2", "TDMIN_C OUT", - "TODDR_C IN 2", "TDMIN_C OUT", - "TODDR_A IN 3", "SPDIFIN Capture", - "TODDR_B IN 3", "SPDIFIN Capture", - "TODDR_C IN 3", "SPDIFIN Capture", - "TODDR_A IN 4", "PDM Capture", - "TODDR_B IN 4", "PDM Capture", - "TODDR_C IN 4", "PDM Capture", - "TODDR_A IN 6", "TDMIN_LB OUT", - "TODDR_B IN 6", "TDMIN_LB OUT", - "TODDR_C IN 6", "TDMIN_LB OUT", - "Lineout", "Lineout AOUTL", - "Lineout", "Lineout AOUTR", - "Speaker1 Left", "SPK1 OUT_A", - "Speaker1 Left", "SPK1 OUT_B", - "Speaker1 Right", "SPK1 OUT_C", - "Speaker1 Right", "SPK1 OUT_D", - "Linein AINL", "Linein", - "Linein AINR", "Linein"; - assigned-clocks = <&clkc CLKID_HIFI_PLL>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <589824000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - dai-link-3 { - sound-dai = <&toddr_a>; - }; - - dai-link-4 { - sound-dai = <&toddr_b>; - }; - - dai-link-5 { - sound-dai = <&toddr_c>; - }; - - dai-link-6 { - sound-dai = <&tdmif_c>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-rx-mask-1 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&lineout>; - }; - - codec-1 { - sound-dai = <&speaker_amp1>; - }; - - codec-2 { - sound-dai = <&linein>; - }; - - }; - - dai-link-7 { - sound-dai = <&spdifout>; - - codec { - sound-dai = <&spdif_dit>; - }; - }; - - dai-link-8 { - sound-dai = <&spdifin>; - - codec { - sound-dai = <&spdif_dir>; - }; - }; - - dai-link-9 { - sound-dai = <&pdm>; - - codec { - sound-dai = <&dmics>; - }; - }; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */ - }; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rgmii_y_pins>; - pinctrl-names = "default"; - phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - interrupt-parent = <&gpio_intc>; - interrupts = <98 IRQ_TYPE_LEVEL_LOW>; - eee-broken-1000t; - }; - }; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&i2c1 { - status = "okay"; - pinctrl-0 = <&i2c1_z_pins>; - pinctrl-names = "default"; - - speaker_amp1: audio-codec@1b { - compatible = "ti,tas5707"; - reg = <0x1b>; - reset-gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - AVDD-supply = <&vcc_3v3>; - DVDD-supply = <&vcc_3v3>; - PVDD_A-supply = <&main_12v>; - PVDD_B-supply = <&main_12v>; - PVDD_C-supply = <&main_12v>; - PVDD_D-supply = <&main_12v>; - sound-name-prefix = "SPK1"; - }; -}; - -&i2c_AO { - status = "okay"; - pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>; - pinctrl-names = "default"; - - gpio_speaker: gpio-controller@1f { - compatible = "nxp,pca9557"; - reg = <0x1f>; - gpio-controller; - #gpio-cells = <2>; - vcc-supply = <&vddao_3v3>; - }; -}; - -&pdm { - pinctrl-0 = <&pdm_dclk_a14_pins>, <&pdm_din0_pins>, - <&pdm_din1_pins>, <&pdm_din2_pins>, <&pdm_din3_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pwm_ab { - status = "okay"; - pinctrl-0 = <&pwm_a_x20_pins>; - pinctrl-names = "default"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* wifi module */ -&sd_emmc_b { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr104; - max-frequency = <200000000>; - non-removable; - disable-wp; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* emmc storage */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&spdifin { - pinctrl-0 = <&spdif_in_a19_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&spdifout { - pinctrl-0 = <&spdif_out_a20_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&tdmif_a { - pinctrl-0 = <&tdma_sclk_pins>, <&tdma_fs_pins>, - <&tdma_din0_pins>, <&tdma_dout0_x15_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&tdmif_b { - pinctrl-0 = <&tdmb_sclk_pins>, <&tdmb_fs_pins>, - <&tdmb_din3_pins>, <&mclk_b_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&tdmif_c { - pinctrl-0 = <&tdmc_sclk_pins>, <&tdmc_fs_pins>, - <&tdmc_din1_pins>, <&tdmc_dout2_pins>, - <&mclk_c_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&tdmin_a { - status = "okay"; -}; - -&tdmin_b { - status = "okay"; -}; - -&tdmin_c { - status = "okay"; -}; - -&tdmin_lb { - status = "okay"; -}; - -&tdmout_c { - status = "okay"; -}; - -&toddr_a { - status = "okay"; -}; - -&toddr_b { - status = "okay"; -}; - -&toddr_c { - status = "okay"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "otg"; - vbus-supply = <&usb_pwr>; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi deleted file mode 100644 index fae48efae..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ /dev/null @@ -1,1826 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Amlogic, Inc. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "amlogic,meson-axg"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - tdmif_a: audio-controller-0 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_A"; - clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, - <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_b: audio-controller-1 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_B"; - clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, - <&clkc_audio AUD_CLKID_MST_B_SCLK>, - <&clkc_audio AUD_CLKID_MST_B_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_c: audio-controller-2 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_C"; - clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, - <&clkc_audio AUD_CLKID_MST_C_SCLK>, - <&clkc_audio AUD_CLKID_MST_C_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - }; - - l2: l2-cache0 { - compatible = "cache"; - }; - }; - - sm: secure-monitor { - compatible = "amlogic,meson-gxbb-sm"; - }; - - efuse: efuse { - compatible = "amlogic,meson-gxbb-efuse"; - clocks = <&clkc CLKID_EFUSE>; - #address-cells = <1>; - #size-cells = <1>; - read-only; - secure-monitor = <&sm>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 16 MiB reserved for Hardware ROM Firmware */ - hwrom_reserved: hwrom@0 { - reg = <0x0 0x0 0x0 0x1000000>; - no-map; - }; - - /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@5000000 { - reg = <0x0 0x05000000 0x0 0x300000>; - no-map; - }; - }; - - scpi { - compatible = "arm,scpi-pre-1.0"; - mboxes = <&mailbox 1 &mailbox 2>; - shmem = <&cpu_scp_lpri &cpu_scp_hpri>; - - scpi_clocks: clocks { - compatible = "arm,scpi-clocks"; - - scpi_dvfs: clock-controller { - compatible = "arm,scpi-dvfs-clocks"; - #clock-cells = <1>; - clock-indices = <0>; - clock-output-names = "vcpu"; - }; - }; - - scpi_sensors: sensors { - compatible = "amlogic,meson-gxbb-scpi-sensors"; - #thermal-sensor-cells = <1>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - usb: usb@ffe09080 { - compatible = "amlogic,meson-axg-usb-ctrl"; - reg = <0x0 0xffe09080 0x0 0x20>; - interrupts = ; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>; - clock-names = "usb_ctrl", "ddr"; - resets = <&reset RESET_USB_OTG>; - - dr_mode = "otg"; - - phys = <&usb2_phy1>; - phy-names = "usb2-phy1"; - - dwc2: usb@ff400000 { - compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; - reg = <0x0 0xff400000 0x0 0x40000>; - interrupts = ; - clocks = <&clkc CLKID_USB1>; - clock-names = "otg"; - phys = <&usb2_phy1>; - dr_mode = "peripheral"; - g-rx-fifo-size = <192>; - g-np-tx-fifo-size = <128>; - g-tx-fifo-size = <128 128 16 16 16>; - }; - - dwc3: usb@ff500000 { - compatible = "snps,dwc3"; - reg = <0x0 0xff500000 0x0 0x100000>; - interrupts = ; - dr_mode = "host"; - maximum-speed = "high-speed"; - snps,dis_u2_susphy_quirk; - }; - }; - - ethmac: ethernet@ff3f0000 { - compatible = "amlogic,meson-axg-dwmac", - "snps,dwmac-3.70a", - "snps,dwmac"; - reg = <0x0 0xff3f0000 0x0 0x10000>, - <0x0 0xff634540 0x0 0x8>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "stmmaceth", "clkin0", "clkin1", - "timing-adjustment"; - rx-fifo-depth = <4096>; - tx-fifo-depth = <2048>; - status = "disabled"; - }; - - pdm: audio-controller@ff632000 { - compatible = "amlogic,axg-pdm"; - reg = <0x0 0xff632000 0x0 0x34>; - #sound-dai-cells = <0>; - sound-name-prefix = "PDM"; - clocks = <&clkc_audio AUD_CLKID_PDM>, - <&clkc_audio AUD_CLKID_PDM_DCLK>, - <&clkc_audio AUD_CLKID_PDM_SYSCLK>; - clock-names = "pclk", "dclk", "sysclk"; - status = "disabled"; - }; - - periphs: bus@ff634000 { - compatible = "simple-bus"; - reg = <0x0 0xff634000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; - - hwrng: rng@18 { - compatible = "amlogic,meson-rng"; - reg = <0x0 0x18 0x0 0x4>; - clocks = <&clkc CLKID_RNG0>; - clock-names = "core"; - }; - - pinctrl_periphs: pinctrl@480 { - compatible = "amlogic,meson-axg-periphs-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio: bank@480 { - reg = <0x0 0x00480 0x0 0x40>, - <0x0 0x004e8 0x0 0x14>, - <0x0 0x00520 0x0 0x14>, - <0x0 0x00430 0x0 0x3c>; - reg-names = "mux", "pull", "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_periphs 0 0 86>; - }; - - i2c0_pins: i2c0 { - mux { - groups = "i2c0_sck", - "i2c0_sda"; - function = "i2c0"; - bias-disable; - }; - }; - - i2c1_x_pins: i2c1_x { - mux { - groups = "i2c1_sck_x", - "i2c1_sda_x"; - function = "i2c1"; - bias-disable; - }; - }; - - i2c1_z_pins: i2c1_z { - mux { - groups = "i2c1_sck_z", - "i2c1_sda_z"; - function = "i2c1"; - bias-disable; - }; - }; - - i2c2_a_pins: i2c2_a { - mux { - groups = "i2c2_sck_a", - "i2c2_sda_a"; - function = "i2c2"; - bias-disable; - }; - }; - - i2c2_x_pins: i2c2_x { - mux { - groups = "i2c2_sck_x", - "i2c2_sda_x"; - function = "i2c2"; - bias-disable; - }; - }; - - i2c3_a6_pins: i2c3_a6 { - mux { - groups = "i2c3_sda_a6", - "i2c3_sck_a7"; - function = "i2c3"; - bias-disable; - }; - }; - - i2c3_a12_pins: i2c3_a12 { - mux { - groups = "i2c3_sda_a12", - "i2c3_sck_a13"; - function = "i2c3"; - bias-disable; - }; - }; - - i2c3_a19_pins: i2c3_a19 { - mux { - groups = "i2c3_sda_a19", - "i2c3_sck_a20"; - function = "i2c3"; - bias-disable; - }; - }; - - emmc_pins: emmc { - mux-0 { - groups = "emmc_nand_d0", - "emmc_nand_d1", - "emmc_nand_d2", - "emmc_nand_d3", - "emmc_nand_d4", - "emmc_nand_d5", - "emmc_nand_d6", - "emmc_nand_d7", - "emmc_cmd"; - function = "emmc"; - bias-pull-up; - }; - - mux-1 { - groups = "emmc_clk"; - function = "emmc"; - bias-disable; - }; - }; - - emmc_ds_pins: emmc_ds { - mux { - groups = "emmc_ds"; - function = "emmc"; - bias-pull-down; - }; - }; - - emmc_clk_gate_pins: emmc_clk_gate { - mux { - groups = "BOOT_8"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - eth_rgmii_x_pins: eth-x-rgmii { - mux { - groups = "eth_mdio_x", - "eth_mdc_x", - "eth_rgmii_rx_clk_x", - "eth_rx_dv_x", - "eth_rxd0_x", - "eth_rxd1_x", - "eth_rxd2_rgmii", - "eth_rxd3_rgmii", - "eth_rgmii_tx_clk", - "eth_txen_x", - "eth_txd0_x", - "eth_txd1_x", - "eth_txd2_rgmii", - "eth_txd3_rgmii"; - function = "eth"; - bias-disable; - }; - }; - - eth_rgmii_y_pins: eth-y-rgmii { - mux { - groups = "eth_mdio_y", - "eth_mdc_y", - "eth_rgmii_rx_clk_y", - "eth_rx_dv_y", - "eth_rxd0_y", - "eth_rxd1_y", - "eth_rxd2_rgmii", - "eth_rxd3_rgmii", - "eth_rgmii_tx_clk", - "eth_txen_y", - "eth_txd0_y", - "eth_txd1_y", - "eth_txd2_rgmii", - "eth_txd3_rgmii"; - function = "eth"; - bias-disable; - }; - }; - - eth_rmii_x_pins: eth-x-rmii { - mux { - groups = "eth_mdio_x", - "eth_mdc_x", - "eth_rgmii_rx_clk_x", - "eth_rx_dv_x", - "eth_rxd0_x", - "eth_rxd1_x", - "eth_txen_x", - "eth_txd0_x", - "eth_txd1_x"; - function = "eth"; - bias-disable; - }; - }; - - eth_rmii_y_pins: eth-y-rmii { - mux { - groups = "eth_mdio_y", - "eth_mdc_y", - "eth_rgmii_rx_clk_y", - "eth_rx_dv_y", - "eth_rxd0_y", - "eth_rxd1_y", - "eth_txen_y", - "eth_txd0_y", - "eth_txd1_y"; - function = "eth"; - bias-disable; - }; - }; - - mclk_b_pins: mclk_b { - mux { - groups = "mclk_b"; - function = "mclk_b"; - bias-disable; - }; - }; - - mclk_c_pins: mclk_c { - mux { - groups = "mclk_c"; - function = "mclk_c"; - bias-disable; - }; - }; - - pdm_dclk_a14_pins: pdm_dclk_a14 { - mux { - groups = "pdm_dclk_a14"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_dclk_a19_pins: pdm_dclk_a19 { - mux { - groups = "pdm_dclk_a19"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din0_pins: pdm_din0 { - mux { - groups = "pdm_din0"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_pins: pdm_din1 { - mux { - groups = "pdm_din1"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_pins: pdm_din2 { - mux { - groups = "pdm_din2"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_pins: pdm_din3 { - mux { - groups = "pdm_din3"; - function = "pdm"; - bias-disable; - }; - }; - - pwm_a_a_pins: pwm_a_a { - mux { - groups = "pwm_a_a"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_a_x18_pins: pwm_a_x18 { - mux { - groups = "pwm_a_x18"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_a_x20_pins: pwm_a_x20 { - mux { - groups = "pwm_a_x20"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_a_z_pins: pwm_a_z { - mux { - groups = "pwm_a_z"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_b_a_pins: pwm_b_a { - mux { - groups = "pwm_b_a"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_b_x_pins: pwm_b_x { - mux { - groups = "pwm_b_x"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_b_z_pins: pwm_b_z { - mux { - groups = "pwm_b_z"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_c_a_pins: pwm_c_a { - mux { - groups = "pwm_c_a"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_c_x10_pins: pwm_c_x10 { - mux { - groups = "pwm_c_x10"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_c_x17_pins: pwm_c_x17 { - mux { - groups = "pwm_c_x17"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_d_x11_pins: pwm_d_x11 { - mux { - groups = "pwm_d_x11"; - function = "pwm_d"; - bias-disable; - }; - }; - - pwm_d_x16_pins: pwm_d_x16 { - mux { - groups = "pwm_d_x16"; - function = "pwm_d"; - bias-disable; - }; - }; - - sdio_pins: sdio { - mux-0 { - groups = "sdio_d0", - "sdio_d1", - "sdio_d2", - "sdio_d3", - "sdio_cmd"; - function = "sdio"; - bias-pull-up; - }; - - mux-1 { - groups = "sdio_clk"; - function = "sdio"; - bias-disable; - }; - }; - - sdio_clk_gate_pins: sdio_clk_gate { - mux { - groups = "GPIOX_4"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - spdif_in_z_pins: spdif_in_z { - mux { - groups = "spdif_in_z"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_a1_pins: spdif_in_a1 { - mux { - groups = "spdif_in_a1"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_a7_pins: spdif_in_a7 { - mux { - groups = "spdif_in_a7"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_a19_pins: spdif_in_a19 { - mux { - groups = "spdif_in_a19"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_a20_pins: spdif_in_a20 { - mux { - groups = "spdif_in_a20"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_out_a1_pins: spdif_out_a1 { - mux { - groups = "spdif_out_a1"; - function = "spdif_out"; - bias-disable; - }; - }; - - spdif_out_a11_pins: spdif_out_a11 { - mux { - groups = "spdif_out_a11"; - function = "spdif_out"; - bias-disable; - }; - }; - - spdif_out_a19_pins: spdif_out_a19 { - mux { - groups = "spdif_out_a19"; - function = "spdif_out"; - bias-disable; - }; - }; - - spdif_out_a20_pins: spdif_out_a20 { - mux { - groups = "spdif_out_a20"; - function = "spdif_out"; - bias-disable; - }; - }; - - spdif_out_z_pins: spdif_out_z { - mux { - groups = "spdif_out_z"; - function = "spdif_out"; - bias-disable; - }; - }; - - spi0_pins: spi0 { - mux { - groups = "spi0_miso", - "spi0_mosi", - "spi0_clk"; - function = "spi0"; - bias-disable; - }; - }; - - spi0_ss0_pins: spi0_ss0 { - mux { - groups = "spi0_ss0"; - function = "spi0"; - bias-disable; - }; - }; - - spi0_ss1_pins: spi0_ss1 { - mux { - groups = "spi0_ss1"; - function = "spi0"; - bias-disable; - }; - }; - - spi0_ss2_pins: spi0_ss2 { - mux { - groups = "spi0_ss2"; - function = "spi0"; - bias-disable; - }; - }; - - spi1_a_pins: spi1_a { - mux { - groups = "spi1_miso_a", - "spi1_mosi_a", - "spi1_clk_a"; - function = "spi1"; - bias-disable; - }; - }; - - spi1_ss0_a_pins: spi1_ss0_a { - mux { - groups = "spi1_ss0_a"; - function = "spi1"; - bias-disable; - }; - }; - - spi1_ss1_pins: spi1_ss1 { - mux { - groups = "spi1_ss1"; - function = "spi1"; - bias-disable; - }; - }; - - spi1_x_pins: spi1_x { - mux { - groups = "spi1_miso_x", - "spi1_mosi_x", - "spi1_clk_x"; - function = "spi1"; - bias-disable; - }; - }; - - spi1_ss0_x_pins: spi1_ss0_x { - mux { - groups = "spi1_ss0_x"; - function = "spi1"; - bias-disable; - }; - }; - - tdma_din0_pins: tdma_din0 { - mux { - groups = "tdma_din0"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_dout0_x14_pins: tdma_dout0_x14 { - mux { - groups = "tdma_dout0_x14"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_dout0_x15_pins: tdma_dout0_x15 { - mux { - groups = "tdma_dout0_x15"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_dout1_pins: tdma_dout1 { - mux { - groups = "tdma_dout1"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_din1_pins: tdma_din1 { - mux { - groups = "tdma_din1"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_fs_pins: tdma_fs { - mux { - groups = "tdma_fs"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_fs_slv_pins: tdma_fs_slv { - mux { - groups = "tdma_fs_slv"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_sclk_pins: tdma_sclk { - mux { - groups = "tdma_sclk"; - function = "tdma"; - bias-disable; - }; - }; - - tdma_sclk_slv_pins: tdma_sclk_slv { - mux { - groups = "tdma_sclk_slv"; - function = "tdma"; - bias-disable; - }; - }; - - tdmb_din0_pins: tdmb_din0 { - mux { - groups = "tdmb_din0"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_din1_pins: tdmb_din1 { - mux { - groups = "tdmb_din1"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_din2_pins: tdmb_din2 { - mux { - groups = "tdmb_din2"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_din3_pins: tdmb_din3 { - mux { - groups = "tdmb_din3"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_dout0_pins: tdmb_dout0 { - mux { - groups = "tdmb_dout0"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_dout1_pins: tdmb_dout1 { - mux { - groups = "tdmb_dout1"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_dout2_pins: tdmb_dout2 { - mux { - groups = "tdmb_dout2"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_dout3_pins: tdmb_dout3 { - mux { - groups = "tdmb_dout3"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_fs_pins: tdmb_fs { - mux { - groups = "tdmb_fs"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_fs_slv_pins: tdmb_fs_slv { - mux { - groups = "tdmb_fs_slv"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_sclk_pins: tdmb_sclk { - mux { - groups = "tdmb_sclk"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmb_sclk_slv_pins: tdmb_sclk_slv { - mux { - groups = "tdmb_sclk_slv"; - function = "tdmb"; - bias-disable; - }; - }; - - tdmc_fs_pins: tdmc_fs { - mux { - groups = "tdmc_fs"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_fs_slv_pins: tdmc_fs_slv { - mux { - groups = "tdmc_fs_slv"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_sclk_pins: tdmc_sclk { - mux { - groups = "tdmc_sclk"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_sclk_slv_pins: tdmc_sclk_slv { - mux { - groups = "tdmc_sclk_slv"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_din0_pins: tdmc_din0 { - mux { - groups = "tdmc_din0"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_din1_pins: tdmc_din1 { - mux { - groups = "tdmc_din1"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_din2_pins: tdmc_din2 { - mux { - groups = "tdmc_din2"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_din3_pins: tdmc_din3 { - mux { - groups = "tdmc_din3"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_dout0_pins: tdmc_dout0 { - mux { - groups = "tdmc_dout0"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_dout1_pins: tdmc_dout1 { - mux { - groups = "tdmc_dout1"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_dout2_pins: tdmc_dout2 { - mux { - groups = "tdmc_dout2"; - function = "tdmc"; - bias-disable; - }; - }; - - tdmc_dout3_pins: tdmc_dout3 { - mux { - groups = "tdmc_dout3"; - function = "tdmc"; - bias-disable; - }; - }; - - uart_a_pins: uart_a { - mux { - groups = "uart_tx_a", - "uart_rx_a"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_a_cts_rts_pins: uart_a_cts_rts { - mux { - groups = "uart_cts_a", - "uart_rts_a"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_b_x_pins: uart_b_x { - mux { - groups = "uart_tx_b_x", - "uart_rx_b_x"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_b_x_cts_rts_pins: uart_b_x_cts_rts { - mux { - groups = "uart_cts_b_x", - "uart_rts_b_x"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_b_z_pins: uart_b_z { - mux { - groups = "uart_tx_b_z", - "uart_rx_b_z"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_b_z_cts_rts_pins: uart_b_z_cts_rts { - mux { - groups = "uart_cts_b_z", - "uart_rts_b_z"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_ao_b_z_pins: uart_ao_b_z { - mux { - groups = "uart_ao_tx_b_z", - "uart_ao_rx_b_z"; - function = "uart_ao_b_z"; - bias-disable; - }; - }; - - uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { - mux { - groups = "uart_ao_cts_b_z", - "uart_ao_rts_b_z"; - function = "uart_ao_b_z"; - bias-disable; - }; - }; - }; - }; - - hiubus: bus@ff63c000 { - compatible = "simple-bus"; - reg = <0x0 0xff63c000 0x0 0x1c00>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; - - sysctrl: system-controller@0 { - compatible = "amlogic,meson-axg-hhi-sysctrl", - "simple-mfd", "syscon"; - reg = <0 0 0 0x400>; - - clkc: clock-controller { - compatible = "amlogic,axg-clkc"; - #clock-cells = <1>; - clocks = <&xtal>; - clock-names = "xtal"; - }; - }; - }; - - mailbox: mailbox@ff63c404 { - compatible = "amlogic,meson-gxbb-mhu"; - reg = <0 0xff63c404 0 0x4c>; - interrupts = , - , - ; - #mbox-cells = <1>; - }; - - audio: bus@ff642000 { - compatible = "simple-bus"; - reg = <0x0 0xff642000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; - - clkc_audio: clock-controller@0 { - compatible = "amlogic,axg-audio-clkc"; - reg = <0x0 0x0 0x0 0xb4>; - #clock-cells = <1>; - - clocks = <&clkc CLKID_AUDIO>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL3>, - <&clkc CLKID_HIFI_PLL>, - <&clkc CLKID_FCLK_DIV3>, - <&clkc CLKID_FCLK_DIV4>, - <&clkc CLKID_GP0_PLL>; - clock-names = "pclk", - "mst_in0", - "mst_in1", - "mst_in2", - "mst_in3", - "mst_in4", - "mst_in5", - "mst_in6", - "mst_in7"; - - resets = <&reset RESET_AUDIO>; - }; - - toddr_a: audio-controller@100 { - compatible = "amlogic,axg-toddr"; - reg = <0x0 0x100 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_A"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_A>; - resets = <&arb AXG_ARB_TODDR_A>; - amlogic,fifo-depth = <512>; - status = "disabled"; - }; - - toddr_b: audio-controller@140 { - compatible = "amlogic,axg-toddr"; - reg = <0x0 0x140 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_B"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_B>; - resets = <&arb AXG_ARB_TODDR_B>; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - toddr_c: audio-controller@180 { - compatible = "amlogic,axg-toddr"; - reg = <0x0 0x180 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_C"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_C>; - resets = <&arb AXG_ARB_TODDR_C>; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_a: audio-controller@1c0 { - compatible = "amlogic,axg-frddr"; - reg = <0x0 0x1c0 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_A"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; - resets = <&arb AXG_ARB_FRDDR_A>; - amlogic,fifo-depth = <512>; - status = "disabled"; - }; - - frddr_b: audio-controller@200 { - compatible = "amlogic,axg-frddr"; - reg = <0x0 0x200 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_B"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; - resets = <&arb AXG_ARB_FRDDR_B>; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_c: audio-controller@240 { - compatible = "amlogic,axg-frddr"; - reg = <0x0 0x240 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_C"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; - resets = <&arb AXG_ARB_FRDDR_C>; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - arb: reset-controller@280 { - compatible = "amlogic,meson-axg-audio-arb"; - reg = <0x0 0x280 0x0 0x4>; - #reset-cells = <1>; - clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; - }; - - tdmin_a: audio-controller@300 { - compatible = "amlogic,axg-tdmin"; - reg = <0x0 0x300 0x0 0x40>; - sound-name-prefix = "TDMIN_A"; - clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_b: audio-controller@340 { - compatible = "amlogic,axg-tdmin"; - reg = <0x0 0x340 0x0 0x40>; - sound-name-prefix = "TDMIN_B"; - clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_c: audio-controller@380 { - compatible = "amlogic,axg-tdmin"; - reg = <0x0 0x380 0x0 0x40>; - sound-name-prefix = "TDMIN_C"; - clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_lb: audio-controller@3c0 { - compatible = "amlogic,axg-tdmin"; - reg = <0x0 0x3c0 0x0 0x40>; - sound-name-prefix = "TDMIN_LB"; - clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - spdifin: audio-controller@400 { - compatible = "amlogic,axg-spdifin"; - reg = <0x0 0x400 0x0 0x30>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFIN"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, - <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; - clock-names = "pclk", "refclk"; - status = "disabled"; - }; - - spdifout: audio-controller@480 { - compatible = "amlogic,axg-spdifout"; - reg = <0x0 0x480 0x0 0x50>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFOUT"; - clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, - <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; - clock-names = "pclk", "mclk"; - status = "disabled"; - }; - - tdmout_a: audio-controller@500 { - compatible = "amlogic,axg-tdmout"; - reg = <0x0 0x500 0x0 0x40>; - sound-name-prefix = "TDMOUT_A"; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_b: audio-controller@540 { - compatible = "amlogic,axg-tdmout"; - reg = <0x0 0x540 0x0 0x40>; - sound-name-prefix = "TDMOUT_B"; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_c: audio-controller@580 { - compatible = "amlogic,axg-tdmout"; - reg = <0x0 0x580 0x0 0x40>; - sound-name-prefix = "TDMOUT_C"; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - }; - - aobus: bus@ff800000 { - compatible = "simple-bus"; - reg = <0x0 0xff800000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; - - sysctrl_AO: sys-ctrl@0 { - compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; - reg = <0x0 0x0 0x0 0x100>; - - clkc_AO: clock-controller { - compatible = "amlogic,meson-axg-aoclkc"; - #clock-cells = <1>; - #reset-cells = <1>; - clocks = <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "mpeg-clk"; - }; - }; - - pinctrl_aobus: pinctrl@14 { - compatible = "amlogic,meson-axg-aobus-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio_ao: bank@14 { - reg = <0x0 0x00014 0x0 0x8>, - <0x0 0x0002c 0x0 0x4>, - <0x0 0x00024 0x0 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 0 15>; - }; - - i2c_ao_sck_4_pins: i2c_ao_sck_4 { - mux { - groups = "i2c_ao_sck_4"; - function = "i2c_ao"; - bias-disable; - }; - }; - - i2c_ao_sck_8_pins: i2c_ao_sck_8 { - mux { - groups = "i2c_ao_sck_8"; - function = "i2c_ao"; - bias-disable; - }; - }; - - i2c_ao_sck_10_pins: i2c_ao_sck_10 { - mux { - groups = "i2c_ao_sck_10"; - function = "i2c_ao"; - bias-disable; - }; - }; - - i2c_ao_sda_5_pins: i2c_ao_sda_5 { - mux { - groups = "i2c_ao_sda_5"; - function = "i2c_ao"; - bias-disable; - }; - }; - - i2c_ao_sda_9_pins: i2c_ao_sda_9 { - mux { - groups = "i2c_ao_sda_9"; - function = "i2c_ao"; - bias-disable; - }; - }; - - i2c_ao_sda_11_pins: i2c_ao_sda_11 { - mux { - groups = "i2c_ao_sda_11"; - function = "i2c_ao"; - bias-disable; - }; - }; - - remote_input_ao_pins: remote_input_ao { - mux { - groups = "remote_input_ao"; - function = "remote_input_ao"; - bias-disable; - }; - }; - - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_ao_tx_a", - "uart_ao_rx_a"; - function = "uart_ao_a"; - bias-disable; - }; - }; - - uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { - mux { - groups = "uart_ao_cts_a", - "uart_ao_rts_a"; - function = "uart_ao_a"; - bias-disable; - }; - }; - - uart_ao_b_pins: uart_ao_b { - mux { - groups = "uart_ao_tx_b", - "uart_ao_rx_b"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { - mux { - groups = "uart_ao_cts_b", - "uart_ao_rts_b"; - function = "uart_ao_b"; - bias-disable; - }; - }; - }; - - sec_AO: ao-secure@140 { - compatible = "amlogic,meson-gx-ao-secure", "syscon"; - reg = <0x0 0x140 0x0 0x140>; - amlogic,has-chip-id; - }; - - pwm_AO_cd: pwm@2000 { - compatible = "amlogic,meson-axg-ao-pwm"; - reg = <0x0 0x02000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - uart_AO: serial@3000 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; - reg = <0x0 0x3000 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - uart_AO_B: serial@4000 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; - reg = <0x0 0x4000 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - i2c_AO: i2c@5000 { - compatible = "amlogic,meson-axg-i2c"; - reg = <0x0 0x05000 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_AO_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm_AO_ab: pwm@7000 { - compatible = "amlogic,meson-axg-ao-pwm"; - reg = <0x0 0x07000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - ir: ir@8000 { - compatible = "amlogic,meson-gxbb-ir"; - reg = <0x0 0x8000 0x0 0x20>; - interrupts = ; - status = "disabled"; - }; - - saradc: adc@9000 { - compatible = "amlogic,meson-axg-saradc", - "amlogic,meson-saradc"; - reg = <0x0 0x9000 0x0 0x38>; - #io-channel-cells = <1>; - interrupts = ; - clocks = <&xtal>, - <&clkc_AO CLKID_AO_SAR_ADC>, - <&clkc_AO CLKID_AO_SAR_ADC_CLK>, - <&clkc_AO CLKID_AO_SAR_ADC_SEL>; - clock-names = "clkin", "core", "adc_clk", "adc_sel"; - status = "disabled"; - }; - }; - - gic: interrupt-controller@ffc01000 { - compatible = "arm,gic-400"; - reg = <0x0 0xffc01000 0 0x1000>, - <0x0 0xffc02000 0 0x2000>, - <0x0 0xffc04000 0 0x2000>, - <0x0 0xffc06000 0 0x2000>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <3>; - #address-cells = <0>; - }; - - cbus: bus@ffd00000 { - compatible = "simple-bus"; - reg = <0x0 0xffd00000 0x0 0x25000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; - - reset: reset-controller@1004 { - compatible = "amlogic,meson-axg-reset"; - reg = <0x0 0x01004 0x0 0x9c>; - #reset-cells = <1>; - }; - - gpio_intc: interrupt-controller@f080 { - compatible = "amlogic,meson-axg-gpio-intc", - "amlogic,meson-gpio-intc"; - reg = <0x0 0xf080 0x0 0x10>; - interrupt-controller; - #interrupt-cells = <2>; - amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; - }; - - watchdog@f0d0 { - compatible = "amlogic,meson-gxbb-wdt"; - reg = <0x0 0xf0d0 0x0 0x10>; - clocks = <&xtal>; - }; - - pwm_ab: pwm@1b000 { - compatible = "amlogic,meson-axg-ee-pwm"; - reg = <0x0 0x1b000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_cd: pwm@1a000 { - compatible = "amlogic,meson-axg-ee-pwm"; - reg = <0x0 0x1a000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - spicc0: spi@13000 { - compatible = "amlogic,meson-axg-spicc"; - reg = <0x0 0x13000 0x0 0x3c>; - interrupts = ; - clocks = <&clkc CLKID_SPICC0>; - clock-names = "core"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spicc1: spi@15000 { - compatible = "amlogic,meson-axg-spicc"; - reg = <0x0 0x15000 0x0 0x3c>; - interrupts = ; - clocks = <&clkc CLKID_SPICC1>; - clock-names = "core"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - clk_msr: clock-measure@18000 { - compatible = "amlogic,meson-axg-clk-measure"; - reg = <0x0 0x18000 0x0 0x10>; - }; - - i2c3: i2c@1c000 { - compatible = "amlogic,meson-axg-i2c"; - reg = <0x0 0x1c000 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@1d000 { - compatible = "amlogic,meson-axg-i2c"; - reg = <0x0 0x1d000 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@1e000 { - compatible = "amlogic,meson-axg-i2c"; - reg = <0x0 0x1e000 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c0: i2c@1f000 { - compatible = "amlogic,meson-axg-i2c"; - reg = <0x0 0x1f000 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_I2C>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart_B: serial@23000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x23000 0x0 0x18>; - interrupts = ; - status = "disabled"; - clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - }; - - uart_A: serial@24000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x24000 0x0 0x18>; - interrupts = ; - status = "disabled"; - clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - }; - }; - - apb: bus@ffe00000 { - compatible = "simple-bus"; - reg = <0x0 0xffe00000 0x0 0x200000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; - - sd_emmc_b: sd@5000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0x5000 0x0 0x800>; - interrupts = ; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_B>, - <&clkc CLKID_SD_EMMC_B_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_B>; - }; - - sd_emmc_c: mmc@7000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0x7000 0x0 0x800>; - interrupts = ; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_C>, - <&clkc CLKID_SD_EMMC_C_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_C>; - }; - - usb2_phy1: phy@9020 { - compatible = "amlogic,meson-gxl-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0x9020 0x0 0x20>; - clocks = <&clkc CLKID_USB>; - clock-names = "phy"; - resets = <&reset RESET_USB_OTG>; - reset-names = "phy"; - }; - }; - - sram: sram@fffc0000 { - compatible = "mmio-sram"; - reg = <0x0 0xfffc0000 0x0 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0xfffc0000 0x20000>; - - cpu_scp_lpri: scp-sram@13000 { - compatible = "amlogic,meson-axg-scp-shmem"; - reg = <0x13000 0x400>; - }; - - cpu_scp_hpri: scp-sram@13400 { - compatible = "amlogic,meson-axg-scp-shmem"; - reg = <0x13400 0x400>; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi deleted file mode 100644 index 075153a4d..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ /dev/null @@ -1,2431 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Amlogic, Inc. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - simplefb_cvbs: framebuffer-cvbs { - compatible = "amlogic,simple-framebuffer", - "simple-framebuffer"; - amlogic,pipeline = "vpu-cvbs"; - clocks = <&clkc CLKID_HDMI>, - <&clkc CLKID_HTX_PCLK>, - <&clkc CLKID_VPU_INTR>; - status = "disabled"; - }; - - simplefb_hdmi: framebuffer-hdmi { - compatible = "amlogic,simple-framebuffer", - "simple-framebuffer"; - amlogic,pipeline = "vpu-hdmi"; - clocks = <&clkc CLKID_HDMI>, - <&clkc CLKID_HTX_PCLK>, - <&clkc CLKID_VPU_INTR>; - status = "disabled"; - }; - }; - - efuse: efuse { - compatible = "amlogic,meson-gxbb-efuse"; - clocks = <&clkc CLKID_EFUSE>; - #address-cells = <1>; - #size-cells = <1>; - read-only; - secure-monitor = <&sm>; - }; - - gpu_opp_table: opp-table-gpu { - compatible = "operating-points-v2"; - - opp-124999998 { - opp-hz = /bits/ 64 <124999998>; - opp-microvolt = <800000>; - }; - opp-249999996 { - opp-hz = /bits/ 64 <249999996>; - opp-microvolt = <800000>; - }; - opp-285714281 { - opp-hz = /bits/ 64 <285714281>; - opp-microvolt = <800000>; - }; - opp-399999994 { - opp-hz = /bits/ 64 <399999994>; - opp-microvolt = <800000>; - }; - opp-499999992 { - opp-hz = /bits/ 64 <499999992>; - opp-microvolt = <800000>; - }; - opp-666666656 { - opp-hz = /bits/ 64 <666666656>; - opp-microvolt = <800000>; - }; - opp-799999987 { - opp-hz = /bits/ 64 <799999987>; - opp-microvolt = <800000>; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@5000000 { - reg = <0x0 0x05000000 0x0 0x300000>; - no-map; - }; - - /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ - secmon_reserved_bl32: secmon@5300000 { - reg = <0x0 0x05300000 0x0 0x2000000>; - no-map; - }; - - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x0 0x10000000>; - alignment = <0x0 0x400000>; - linux,cma-default; - }; - }; - - sm: secure-monitor { - compatible = "amlogic,meson-gxbb-sm"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - pcie: pcie@fc000000 { - compatible = "amlogic,g12a-pcie", "snps,dw-pcie"; - reg = <0x0 0xfc000000 0x0 0x400000 - 0x0 0xff648000 0x0 0x2000 - 0x0 0xfc400000 0x0 0x200000>; - reg-names = "elbi", "cfg", "config"; - interrupts = ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; - bus-range = <0x0 0xff>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000 - 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; - - clocks = <&clkc CLKID_PCIE_PHY - &clkc CLKID_PCIE_COMB - &clkc CLKID_PCIE_PLL>; - clock-names = "general", - "pclk", - "port"; - resets = <&reset RESET_PCIE_CTRL_A>, - <&reset RESET_PCIE_APB>; - reset-names = "port", - "apb"; - num-lanes = <1>; - phys = <&usb3_pcie_phy PHY_TYPE_PCIE>; - phy-names = "pcie"; - status = "disabled"; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&cpu_temp>; - - trips { - cpu_passive: cpu-passive { - temperature = <85000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - cpu_hot: cpu-hot { - temperature = <95000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "hot"; - }; - - cpu_critical: cpu-critical { - temperature = <110000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - }; - - ddr_thermal: ddr-thermal { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&ddr_temp>; - - trips { - ddr_passive: ddr-passive { - temperature = <85000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - ddr_critical: ddr-critical { - temperature = <110000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map { - trip = <&ddr_passive>; - cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - ethmac: ethernet@ff3f0000 { - compatible = "amlogic,meson-g12a-dwmac", - "snps,dwmac-3.70a", - "snps,dwmac"; - reg = <0x0 0xff3f0000 0x0 0x10000>, - <0x0 0xff634540 0x0 0x8>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "stmmaceth", "clkin0", "clkin1", - "timing-adjustment"; - rx-fifo-depth = <4096>; - tx-fifo-depth = <2048>; - status = "disabled"; - - mdio0: mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - }; - }; - - apb: bus@ff600000 { - compatible = "simple-bus"; - reg = <0x0 0xff600000 0x0 0x200000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; - - hdmi_tx: hdmi-tx@0 { - compatible = "amlogic,meson-g12a-dw-hdmi"; - reg = <0x0 0x0 0x0 0x10000>; - interrupts = ; - resets = <&reset RESET_HDMITX_CAPB3>, - <&reset RESET_HDMITX_PHY>, - <&reset RESET_HDMITX>; - reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; - clocks = <&clkc CLKID_HDMI>, - <&clkc CLKID_HTX_PCLK>, - <&clkc CLKID_VPU_INTR>; - clock-names = "isfr", "iahb", "venci"; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <0>; - status = "disabled"; - - /* VPU VENC Input */ - hdmi_tx_venc_port: port@0 { - reg = <0>; - - hdmi_tx_in: endpoint { - remote-endpoint = <&hdmi_tx_out>; - }; - }; - - /* TMDS Output */ - hdmi_tx_tmds_port: port@1 { - reg = <1>; - }; - }; - - apb_efuse: bus@30000 { - compatible = "simple-bus"; - reg = <0x0 0x30000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; - - hwrng: rng@218 { - compatible = "amlogic,meson-rng"; - reg = <0x0 0x218 0x0 0x4>; - clocks = <&clkc CLKID_RNG0>; - clock-names = "core"; - }; - }; - - acodec: audio-controller@32000 { - compatible = "amlogic,t9015"; - reg = <0x0 0x32000 0x0 0x14>; - #sound-dai-cells = <0>; - sound-name-prefix = "ACODEC"; - clocks = <&clkc CLKID_AUDIO_CODEC>; - clock-names = "pclk"; - resets = <&reset RESET_AUDIO_CODEC>; - status = "disabled"; - }; - - periphs: bus@34400 { - compatible = "simple-bus"; - reg = <0x0 0x34400 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; - - periphs_pinctrl: pinctrl@40 { - compatible = "amlogic,meson-g12a-periphs-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio: bank@40 { - reg = <0x0 0x40 0x0 0x4c>, - <0x0 0xe8 0x0 0x18>, - <0x0 0x120 0x0 0x18>, - <0x0 0x2c0 0x0 0x40>, - <0x0 0x340 0x0 0x1c>; - reg-names = "gpio", - "pull", - "pull-enable", - "mux", - "ds"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&periphs_pinctrl 0 0 86>; - }; - - cec_ao_a_h_pins: cec_ao_a_h { - mux { - groups = "cec_ao_a_h"; - function = "cec_ao_a_h"; - bias-disable; - }; - }; - - cec_ao_b_h_pins: cec_ao_b_h { - mux { - groups = "cec_ao_b_h"; - function = "cec_ao_b_h"; - bias-disable; - }; - }; - - emmc_ctrl_pins: emmc-ctrl { - mux-0 { - groups = "emmc_cmd"; - function = "emmc"; - bias-pull-up; - drive-strength-microamp = <4000>; - }; - - mux-1 { - groups = "emmc_clk"; - function = "emmc"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - emmc_data_4b_pins: emmc-data-4b { - mux-0 { - groups = "emmc_nand_d0", - "emmc_nand_d1", - "emmc_nand_d2", - "emmc_nand_d3"; - function = "emmc"; - bias-pull-up; - drive-strength-microamp = <4000>; - }; - }; - - emmc_data_8b_pins: emmc-data-8b { - mux-0 { - groups = "emmc_nand_d0", - "emmc_nand_d1", - "emmc_nand_d2", - "emmc_nand_d3", - "emmc_nand_d4", - "emmc_nand_d5", - "emmc_nand_d6", - "emmc_nand_d7"; - function = "emmc"; - bias-pull-up; - drive-strength-microamp = <4000>; - }; - }; - - emmc_ds_pins: emmc-ds { - mux { - groups = "emmc_nand_ds"; - function = "emmc"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - emmc_clk_gate_pins: emmc_clk_gate { - mux { - groups = "BOOT_8"; - function = "gpio_periphs"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - hdmitx_ddc_pins: hdmitx_ddc { - mux { - groups = "hdmitx_sda", - "hdmitx_sck"; - function = "hdmitx"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - hdmitx_hpd_pins: hdmitx_hpd { - mux { - groups = "hdmitx_hpd_in"; - function = "hdmitx"; - bias-disable; - }; - }; - - - i2c0_sda_c_pins: i2c0-sda-c { - mux { - groups = "i2c0_sda_c"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - - }; - }; - - i2c0_sck_c_pins: i2c0-sck-c { - mux { - groups = "i2c0_sck_c"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c0_sda_z0_pins: i2c0-sda-z0 { - mux { - groups = "i2c0_sda_z0"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c0_sck_z1_pins: i2c0-sck-z1 { - mux { - groups = "i2c0_sck_z1"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c0_sda_z7_pins: i2c0-sda-z7 { - mux { - groups = "i2c0_sda_z7"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c0_sda_z8_pins: i2c0-sda-z8 { - mux { - groups = "i2c0_sda_z8"; - function = "i2c0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sda_x_pins: i2c1-sda-x { - mux { - groups = "i2c1_sda_x"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sck_x_pins: i2c1-sck-x { - mux { - groups = "i2c1_sck_x"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sda_h2_pins: i2c1-sda-h2 { - mux { - groups = "i2c1_sda_h2"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sck_h3_pins: i2c1-sck-h3 { - mux { - groups = "i2c1_sck_h3"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sda_h6_pins: i2c1-sda-h6 { - mux { - groups = "i2c1_sda_h6"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c1_sck_h7_pins: i2c1-sck-h7 { - mux { - groups = "i2c1_sck_h7"; - function = "i2c1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_sda_x_pins: i2c2-sda-x { - mux { - groups = "i2c2_sda_x"; - function = "i2c2"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_sck_x_pins: i2c2-sck-x { - mux { - groups = "i2c2_sck_x"; - function = "i2c2"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_sda_z_pins: i2c2-sda-z { - mux { - groups = "i2c2_sda_z"; - function = "i2c2"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c2_sck_z_pins: i2c2-sck-z { - mux { - groups = "i2c2_sck_z"; - function = "i2c2"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c3_sda_h_pins: i2c3-sda-h { - mux { - groups = "i2c3_sda_h"; - function = "i2c3"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c3_sck_h_pins: i2c3-sck-h { - mux { - groups = "i2c3_sck_h"; - function = "i2c3"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c3_sda_a_pins: i2c3-sda-a { - mux { - groups = "i2c3_sda_a"; - function = "i2c3"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c3_sck_a_pins: i2c3-sck-a { - mux { - groups = "i2c3_sck_a"; - function = "i2c3"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk0_a_pins: mclk0-a { - mux { - groups = "mclk0_a"; - function = "mclk0"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk1_a_pins: mclk1-a { - mux { - groups = "mclk1_a"; - function = "mclk1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk1_x_pins: mclk1-x { - mux { - groups = "mclk1_x"; - function = "mclk1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk1_z_pins: mclk1-z { - mux { - groups = "mclk1_z"; - function = "mclk1"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - nor_pins: nor { - mux { - groups = "nor_d", - "nor_q", - "nor_c", - "nor_cs"; - function = "nor"; - bias-disable; - }; - }; - - pdm_din0_a_pins: pdm-din0-a { - mux { - groups = "pdm_din0_a"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din0_c_pins: pdm-din0-c { - mux { - groups = "pdm_din0_c"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din0_x_pins: pdm-din0-x { - mux { - groups = "pdm_din0_x"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din0_z_pins: pdm-din0-z { - mux { - groups = "pdm_din0_z"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_a_pins: pdm-din1-a { - mux { - groups = "pdm_din1_a"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_c_pins: pdm-din1-c { - mux { - groups = "pdm_din1_c"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_x_pins: pdm-din1-x { - mux { - groups = "pdm_din1_x"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din1_z_pins: pdm-din1-z { - mux { - groups = "pdm_din1_z"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_a_pins: pdm-din2-a { - mux { - groups = "pdm_din2_a"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_c_pins: pdm-din2-c { - mux { - groups = "pdm_din2_c"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_x_pins: pdm-din2-x { - mux { - groups = "pdm_din2_x"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din2_z_pins: pdm-din2-z { - mux { - groups = "pdm_din2_z"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_a_pins: pdm-din3-a { - mux { - groups = "pdm_din3_a"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_c_pins: pdm-din3-c { - mux { - groups = "pdm_din3_c"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_x_pins: pdm-din3-x { - mux { - groups = "pdm_din3_x"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_din3_z_pins: pdm-din3-z { - mux { - groups = "pdm_din3_z"; - function = "pdm"; - bias-disable; - }; - }; - - pdm_dclk_a_pins: pdm-dclk-a { - mux { - groups = "pdm_dclk_a"; - function = "pdm"; - bias-disable; - drive-strength-microamp = <500>; - }; - }; - - pdm_dclk_c_pins: pdm-dclk-c { - mux { - groups = "pdm_dclk_c"; - function = "pdm"; - bias-disable; - drive-strength-microamp = <500>; - }; - }; - - pdm_dclk_x_pins: pdm-dclk-x { - mux { - groups = "pdm_dclk_x"; - function = "pdm"; - bias-disable; - drive-strength-microamp = <500>; - }; - }; - - pdm_dclk_z_pins: pdm-dclk-z { - mux { - groups = "pdm_dclk_z"; - function = "pdm"; - bias-disable; - drive-strength-microamp = <500>; - }; - }; - - pwm_a_pins: pwm-a { - mux { - groups = "pwm_a"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_b_x7_pins: pwm-b-x7 { - mux { - groups = "pwm_b_x7"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_b_x19_pins: pwm-b-x19 { - mux { - groups = "pwm_b_x19"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_c_c_pins: pwm-c-c { - mux { - groups = "pwm_c_c"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_c_x5_pins: pwm-c-x5 { - mux { - groups = "pwm_c_x5"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_c_x8_pins: pwm-c-x8 { - mux { - groups = "pwm_c_x8"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_d_x3_pins: pwm-d-x3 { - mux { - groups = "pwm_d_x3"; - function = "pwm_d"; - bias-disable; - }; - }; - - pwm_d_x6_pins: pwm-d-x6 { - mux { - groups = "pwm_d_x6"; - function = "pwm_d"; - bias-disable; - }; - }; - - pwm_e_pins: pwm-e { - mux { - groups = "pwm_e"; - function = "pwm_e"; - bias-disable; - }; - }; - - pwm_f_x_pins: pwm-f-x { - mux { - groups = "pwm_f_x"; - function = "pwm_f"; - bias-disable; - }; - }; - - pwm_f_h_pins: pwm-f-h { - mux { - groups = "pwm_f_h"; - function = "pwm_f"; - bias-disable; - }; - }; - - sdcard_c_pins: sdcard_c { - mux-0 { - groups = "sdcard_d0_c", - "sdcard_d1_c", - "sdcard_d2_c", - "sdcard_d3_c", - "sdcard_cmd_c"; - function = "sdcard"; - bias-pull-up; - drive-strength-microamp = <4000>; - }; - - mux-1 { - groups = "sdcard_clk_c"; - function = "sdcard"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - sdcard_clk_gate_c_pins: sdcard_clk_gate_c { - mux { - groups = "GPIOC_4"; - function = "gpio_periphs"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - sdcard_z_pins: sdcard_z { - mux-0 { - groups = "sdcard_d0_z", - "sdcard_d1_z", - "sdcard_d2_z", - "sdcard_d3_z", - "sdcard_cmd_z"; - function = "sdcard"; - bias-pull-up; - drive-strength-microamp = <4000>; - }; - - mux-1 { - groups = "sdcard_clk_z"; - function = "sdcard"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - sdcard_clk_gate_z_pins: sdcard_clk_gate_z { - mux { - groups = "GPIOZ_6"; - function = "gpio_periphs"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - sdio_pins: sdio { - mux { - groups = "sdio_d0", - "sdio_d1", - "sdio_d2", - "sdio_d3", - "sdio_clk", - "sdio_cmd"; - function = "sdio"; - bias-disable; - drive-strength-microamp = <4000>; - }; - }; - - sdio_clk_gate_pins: sdio_clk_gate { - mux { - groups = "GPIOX_4"; - function = "gpio_periphs"; - bias-pull-down; - drive-strength-microamp = <4000>; - }; - }; - - spdif_in_a10_pins: spdif-in-a10 { - mux { - groups = "spdif_in_a10"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_a12_pins: spdif-in-a12 { - mux { - groups = "spdif_in_a12"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_in_h_pins: spdif-in-h { - mux { - groups = "spdif_in_h"; - function = "spdif_in"; - bias-disable; - }; - }; - - spdif_out_h_pins: spdif-out-h { - mux { - groups = "spdif_out_h"; - function = "spdif_out"; - drive-strength-microamp = <500>; - bias-disable; - }; - }; - - spdif_out_a11_pins: spdif-out-a11 { - mux { - groups = "spdif_out_a11"; - function = "spdif_out"; - drive-strength-microamp = <500>; - bias-disable; - }; - }; - - spdif_out_a13_pins: spdif-out-a13 { - mux { - groups = "spdif_out_a13"; - function = "spdif_out"; - drive-strength-microamp = <500>; - bias-disable; - }; - }; - - spicc0_x_pins: spicc0-x { - mux { - groups = "spi0_mosi_x", - "spi0_miso_x", - "spi0_clk_x"; - function = "spi0"; - drive-strength-microamp = <4000>; - bias-disable; - }; - }; - - spicc0_ss0_x_pins: spicc0-ss0-x { - mux { - groups = "spi0_ss0_x"; - function = "spi0"; - drive-strength-microamp = <4000>; - bias-disable; - }; - }; - - spicc0_c_pins: spicc0-c { - mux { - groups = "spi0_mosi_c", - "spi0_miso_c", - "spi0_ss0_c", - "spi0_clk_c"; - function = "spi0"; - drive-strength-microamp = <4000>; - bias-disable; - }; - }; - - spicc1_pins: spicc1 { - mux { - groups = "spi1_mosi", - "spi1_miso", - "spi1_clk"; - function = "spi1"; - drive-strength-microamp = <4000>; - }; - }; - - spicc1_ss0_pins: spicc1-ss0 { - mux { - groups = "spi1_ss0"; - function = "spi1"; - drive-strength-microamp = <4000>; - bias-disable; - }; - }; - - tdm_a_din0_pins: tdm-a-din0 { - mux { - groups = "tdm_a_din0"; - function = "tdm_a"; - bias-disable; - }; - }; - - - tdm_a_din1_pins: tdm-a-din1 { - mux { - groups = "tdm_a_din1"; - function = "tdm_a"; - bias-disable; - }; - }; - - tdm_a_dout0_pins: tdm-a-dout0 { - mux { - groups = "tdm_a_dout0"; - function = "tdm_a"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_a_dout1_pins: tdm-a-dout1 { - mux { - groups = "tdm_a_dout1"; - function = "tdm_a"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_a_fs_pins: tdm-a-fs { - mux { - groups = "tdm_a_fs"; - function = "tdm_a"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_a_sclk_pins: tdm-a-sclk { - mux { - groups = "tdm_a_sclk"; - function = "tdm_a"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_a_slv_fs_pins: tdm-a-slv-fs { - mux { - groups = "tdm_a_slv_fs"; - function = "tdm_a"; - bias-disable; - }; - }; - - - tdm_a_slv_sclk_pins: tdm-a-slv-sclk { - mux { - groups = "tdm_a_slv_sclk"; - function = "tdm_a"; - bias-disable; - }; - }; - - tdm_b_din0_pins: tdm-b-din0 { - mux { - groups = "tdm_b_din0"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_din1_pins: tdm-b-din1 { - mux { - groups = "tdm_b_din1"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_din2_pins: tdm-b-din2 { - mux { - groups = "tdm_b_din2"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_din3_a_pins: tdm-b-din3-a { - mux { - groups = "tdm_b_din3_a"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_din3_h_pins: tdm-b-din3-h { - mux { - groups = "tdm_b_din3_h"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_dout0_pins: tdm-b-dout0 { - mux { - groups = "tdm_b_dout0"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_dout1_pins: tdm-b-dout1 { - mux { - groups = "tdm_b_dout1"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_dout2_pins: tdm-b-dout2 { - mux { - groups = "tdm_b_dout2"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_dout3_a_pins: tdm-b-dout3-a { - mux { - groups = "tdm_b_dout3_a"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_dout3_h_pins: tdm-b-dout3-h { - mux { - groups = "tdm_b_dout3_h"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_fs_pins: tdm-b-fs { - mux { - groups = "tdm_b_fs"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_sclk_pins: tdm-b-sclk { - mux { - groups = "tdm_b_sclk"; - function = "tdm_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_b_slv_fs_pins: tdm-b-slv-fs { - mux { - groups = "tdm_b_slv_fs"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_b_slv_sclk_pins: tdm-b-slv-sclk { - mux { - groups = "tdm_b_slv_sclk"; - function = "tdm_b"; - bias-disable; - }; - }; - - tdm_c_din0_a_pins: tdm-c-din0-a { - mux { - groups = "tdm_c_din0_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din0_z_pins: tdm-c-din0-z { - mux { - groups = "tdm_c_din0_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din1_a_pins: tdm-c-din1-a { - mux { - groups = "tdm_c_din1_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din1_z_pins: tdm-c-din1-z { - mux { - groups = "tdm_c_din1_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din2_a_pins: tdm-c-din2-a { - mux { - groups = "tdm_c_din2_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - eth_leds_pins: eth-leds { - mux { - groups = "eth_link_led", - "eth_act_led"; - function = "eth"; - bias-disable; - }; - }; - - eth_pins: eth { - mux { - groups = "eth_mdio", - "eth_mdc", - "eth_rgmii_rx_clk", - "eth_rx_dv", - "eth_rxd0", - "eth_rxd1", - "eth_txen", - "eth_txd0", - "eth_txd1"; - function = "eth"; - drive-strength-microamp = <4000>; - bias-disable; - }; - }; - - eth_rgmii_pins: eth-rgmii { - mux { - groups = "eth_rxd2_rgmii", - "eth_rxd3_rgmii", - "eth_rgmii_tx_clk", - "eth_txd2_rgmii", - "eth_txd3_rgmii"; - function = "eth"; - drive-strength-microamp = <4000>; - bias-disable; - }; - }; - - tdm_c_din2_z_pins: tdm-c-din2-z { - mux { - groups = "tdm_c_din2_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din3_a_pins: tdm-c-din3-a { - mux { - groups = "tdm_c_din3_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_din3_z_pins: tdm-c-din3-z { - mux { - groups = "tdm_c_din3_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_dout0_a_pins: tdm-c-dout0-a { - mux { - groups = "tdm_c_dout0_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout0_z_pins: tdm-c-dout0-z { - mux { - groups = "tdm_c_dout0_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout1_a_pins: tdm-c-dout1-a { - mux { - groups = "tdm_c_dout1_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout1_z_pins: tdm-c-dout1-z { - mux { - groups = "tdm_c_dout1_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout2_a_pins: tdm-c-dout2-a { - mux { - groups = "tdm_c_dout2_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout2_z_pins: tdm-c-dout2-z { - mux { - groups = "tdm_c_dout2_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout3_a_pins: tdm-c-dout3-a { - mux { - groups = "tdm_c_dout3_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_dout3_z_pins: tdm-c-dout3-z { - mux { - groups = "tdm_c_dout3_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_fs_a_pins: tdm-c-fs-a { - mux { - groups = "tdm_c_fs_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_fs_z_pins: tdm-c-fs-z { - mux { - groups = "tdm_c_fs_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_sclk_a_pins: tdm-c-sclk-a { - mux { - groups = "tdm_c_sclk_a"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_sclk_z_pins: tdm-c-sclk-z { - mux { - groups = "tdm_c_sclk_z"; - function = "tdm_c"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { - mux { - groups = "tdm_c_slv_fs_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { - mux { - groups = "tdm_c_slv_fs_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { - mux { - groups = "tdm_c_slv_sclk_a"; - function = "tdm_c"; - bias-disable; - }; - }; - - tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { - mux { - groups = "tdm_c_slv_sclk_z"; - function = "tdm_c"; - bias-disable; - }; - }; - - uart_a_pins: uart-a { - mux { - groups = "uart_a_tx", - "uart_a_rx"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_a_cts_rts_pins: uart-a-cts-rts { - mux { - groups = "uart_a_cts", - "uart_a_rts"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_b_pins: uart-b { - mux { - groups = "uart_b_tx", - "uart_b_rx"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_c_pins: uart-c { - mux { - groups = "uart_c_tx", - "uart_c_rx"; - function = "uart_c"; - bias-disable; - }; - }; - - uart_c_cts_rts_pins: uart-c-cts-rts { - mux { - groups = "uart_c_cts", - "uart_c_rts"; - function = "uart_c"; - bias-disable; - }; - }; - }; - }; - - cpu_temp: temperature-sensor@34800 { - compatible = "amlogic,g12a-cpu-thermal", - "amlogic,g12a-thermal"; - reg = <0x0 0x34800 0x0 0x50>; - interrupts = ; - clocks = <&clkc CLKID_TS>; - #thermal-sensor-cells = <0>; - amlogic,ao-secure = <&sec_AO>; - }; - - ddr_temp: temperature-sensor@34c00 { - compatible = "amlogic,g12a-ddr-thermal", - "amlogic,g12a-thermal"; - reg = <0x0 0x34c00 0x0 0x50>; - interrupts = ; - clocks = <&clkc CLKID_TS>; - #thermal-sensor-cells = <0>; - amlogic,ao-secure = <&sec_AO>; - }; - - usb2_phy0: phy@36000 { - compatible = "amlogic,g12a-usb2-phy"; - reg = <0x0 0x36000 0x0 0x2000>; - clocks = <&xtal>; - clock-names = "xtal"; - resets = <&reset RESET_USB_PHY20>; - reset-names = "phy"; - #phy-cells = <0>; - }; - - dmc: bus@38000 { - compatible = "simple-bus"; - reg = <0x0 0x38000 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; - - canvas: video-lut@48 { - compatible = "amlogic,canvas"; - reg = <0x0 0x48 0x0 0x14>; - }; - }; - - usb2_phy1: phy@3a000 { - compatible = "amlogic,g12a-usb2-phy"; - reg = <0x0 0x3a000 0x0 0x2000>; - clocks = <&xtal>; - clock-names = "xtal"; - resets = <&reset RESET_USB_PHY21>; - reset-names = "phy"; - #phy-cells = <0>; - }; - - hiu: bus@3c000 { - compatible = "simple-bus"; - reg = <0x0 0x3c000 0x0 0x1400>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; - - hhi: system-controller@0 { - compatible = "amlogic,meson-gx-hhi-sysctrl", - "simple-mfd", "syscon"; - reg = <0 0 0 0x400>; - - clkc: clock-controller { - compatible = "amlogic,g12a-clkc"; - #clock-cells = <1>; - clocks = <&xtal>; - clock-names = "xtal"; - }; - - pwrc: power-controller { - compatible = "amlogic,meson-g12a-pwrc"; - #power-domain-cells = <1>; - amlogic,ao-sysctrl = <&rti>; - resets = <&reset RESET_VIU>, - <&reset RESET_VENC>, - <&reset RESET_VCBUS>, - <&reset RESET_BT656>, - <&reset RESET_RDMA>, - <&reset RESET_VENCI>, - <&reset RESET_VENCP>, - <&reset RESET_VDAC>, - <&reset RESET_VDI6>, - <&reset RESET_VENCL>, - <&reset RESET_VID_LOCK>; - reset-names = "viu", "venc", "vcbus", "bt656", - "rdma", "venci", "vencp", "vdac", - "vdi6", "vencl", "vid_lock"; - clocks = <&clkc CLKID_VPU>, - <&clkc CLKID_VAPB>; - clock-names = "vpu", "vapb"; - /* - * VPU clocking is provided by two identical clock paths - * VPU_0 and VPU_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - * Same for VAPB but with a final gate after the glitch free mux. - */ - assigned-clocks = <&clkc CLKID_VPU_0_SEL>, - <&clkc CLKID_VPU_0>, - <&clkc CLKID_VPU>, /* Glitch free mux */ - <&clkc CLKID_VAPB_0_SEL>, - <&clkc CLKID_VAPB_0>, - <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, - <0>, /* Do Nothing */ - <&clkc CLKID_VPU_0>, - <&clkc CLKID_FCLK_DIV4>, - <0>, /* Do Nothing */ - <&clkc CLKID_VAPB_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <666666666>, - <0>, /* Do Nothing */ - <0>, /* Do Nothing */ - <250000000>, - <0>; /* Do Nothing */ - }; - }; - }; - - usb3_pcie_phy: phy@46000 { - compatible = "amlogic,g12a-usb3-pcie-phy"; - reg = <0x0 0x46000 0x0 0x2000>; - clocks = <&clkc CLKID_PCIE_PLL>; - clock-names = "ref_clk"; - resets = <&reset RESET_PCIE_PHY>; - reset-names = "phy"; - assigned-clocks = <&clkc CLKID_PCIE_PLL>; - assigned-clock-rates = <100000000>; - #phy-cells = <1>; - }; - - eth_phy: mdio-multiplexer@4c000 { - compatible = "amlogic,g12a-mdio-mux"; - reg = <0x0 0x4c000 0x0 0xa4>; - clocks = <&clkc CLKID_ETH_PHY>, - <&xtal>, - <&clkc CLKID_MPLL_50M>; - clock-names = "pclk", "clkin0", "clkin1"; - mdio-parent-bus = <&mdio0>; - #address-cells = <1>; - #size-cells = <0>; - - ext_mdio: mdio@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - int_mdio: mdio@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - internal_ephy: ethernet_phy@8 { - compatible = "ethernet-phy-id0180.3301", - "ethernet-phy-ieee802.3-c22"; - interrupts = ; - reg = <8>; - max-speed = <100>; - }; - }; - }; - }; - - aobus: bus@ff800000 { - compatible = "simple-bus"; - reg = <0x0 0xff800000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; - - rti: sys-ctrl@0 { - compatible = "amlogic,meson-gx-ao-sysctrl", - "simple-mfd", "syscon"; - reg = <0x0 0x0 0x0 0x100>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; - - clkc_AO: clock-controller { - compatible = "amlogic,meson-g12a-aoclkc"; - #clock-cells = <1>; - #reset-cells = <1>; - clocks = <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "mpeg-clk"; - }; - - ao_pinctrl: pinctrl@14 { - compatible = "amlogic,meson-g12a-aobus-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio_ao: bank@14 { - reg = <0x0 0x14 0x0 0x8>, - <0x0 0x1c 0x0 0x8>, - <0x0 0x24 0x0 0x14>; - reg-names = "mux", - "ds", - "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&ao_pinctrl 0 0 15>; - }; - - i2c_ao_sck_pins: i2c_ao_sck_pins { - mux { - groups = "i2c_ao_sck"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c_ao_sda_pins: i2c_ao_sda { - mux { - groups = "i2c_ao_sda"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c_ao_sck_e_pins: i2c_ao_sck_e { - mux { - groups = "i2c_ao_sck_e"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - i2c_ao_sda_e_pins: i2c_ao_sda_e { - mux { - groups = "i2c_ao_sda_e"; - function = "i2c_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - mclk0_ao_pins: mclk0-ao { - mux { - groups = "mclk0_ao"; - function = "mclk0_ao"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_din0_pins: tdm-ao-b-din0 { - mux { - groups = "tdm_ao_b_din0"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - spdif_ao_out_pins: spdif-ao-out { - mux { - groups = "spdif_ao_out"; - function = "spdif_ao_out"; - drive-strength-microamp = <500>; - bias-disable; - }; - }; - - tdm_ao_b_din1_pins: tdm-ao-b-din1 { - mux { - groups = "tdm_ao_b_din1"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - tdm_ao_b_din2_pins: tdm-ao-b-din2 { - mux { - groups = "tdm_ao_b_din2"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { - mux { - groups = "tdm_ao_b_dout0"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { - mux { - groups = "tdm_ao_b_dout1"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { - mux { - groups = "tdm_ao_b_dout2"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_fs_pins: tdm-ao-b-fs { - mux { - groups = "tdm_ao_b_fs"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_sclk_pins: tdm-ao-b-sclk { - mux { - groups = "tdm_ao_b_sclk"; - function = "tdm_ao_b"; - bias-disable; - drive-strength-microamp = <3000>; - }; - }; - - tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { - mux { - groups = "tdm_ao_b_slv_fs"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { - mux { - groups = "tdm_ao_b_slv_sclk"; - function = "tdm_ao_b"; - bias-disable; - }; - }; - - uart_ao_a_pins: uart-a-ao { - mux { - groups = "uart_ao_a_tx", - "uart_ao_a_rx"; - function = "uart_ao_a"; - bias-disable; - }; - }; - - uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { - mux { - groups = "uart_ao_a_cts", - "uart_ao_a_rts"; - function = "uart_ao_a"; - bias-disable; - }; - }; - - pwm_a_e_pins: pwm-a-e { - mux { - groups = "pwm_a_e"; - function = "pwm_a_e"; - bias-disable; - }; - }; - - pwm_ao_a_pins: pwm-ao-a { - mux { - groups = "pwm_ao_a"; - function = "pwm_ao_a"; - bias-disable; - }; - }; - - pwm_ao_b_pins: pwm-ao-b { - mux { - groups = "pwm_ao_b"; - function = "pwm_ao_b"; - bias-disable; - }; - }; - - pwm_ao_c_4_pins: pwm-ao-c-4 { - mux { - groups = "pwm_ao_c_4"; - function = "pwm_ao_c"; - bias-disable; - }; - }; - - pwm_ao_c_6_pins: pwm-ao-c-6 { - mux { - groups = "pwm_ao_c_6"; - function = "pwm_ao_c"; - bias-disable; - }; - }; - - pwm_ao_d_5_pins: pwm-ao-d-5 { - mux { - groups = "pwm_ao_d_5"; - function = "pwm_ao_d"; - bias-disable; - }; - }; - - pwm_ao_d_10_pins: pwm-ao-d-10 { - mux { - groups = "pwm_ao_d_10"; - function = "pwm_ao_d"; - bias-disable; - }; - }; - - pwm_ao_d_e_pins: pwm-ao-d-e { - mux { - groups = "pwm_ao_d_e"; - function = "pwm_ao_d"; - }; - }; - - remote_input_ao_pins: remote-input-ao { - mux { - groups = "remote_ao_input"; - function = "remote_ao_input"; - bias-disable; - }; - }; - }; - }; - - vrtc: rtc@0a8 { - compatible = "amlogic,meson-vrtc"; - reg = <0x0 0x000a8 0x0 0x4>; - }; - - cec_AO: cec@100 { - compatible = "amlogic,meson-gx-ao-cec"; - reg = <0x0 0x00100 0x0 0x14>; - interrupts = ; - clocks = <&clkc_AO CLKID_AO_CEC>; - clock-names = "core"; - status = "disabled"; - }; - - sec_AO: ao-secure@140 { - compatible = "amlogic,meson-gx-ao-secure", "syscon"; - reg = <0x0 0x140 0x0 0x140>; - amlogic,has-chip-id; - }; - - cecb_AO: cec@280 { - compatible = "amlogic,meson-g12a-ao-cec"; - reg = <0x0 0x00280 0x0 0x1c>; - interrupts = ; - clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; - clock-names = "oscin"; - status = "disabled"; - }; - - pwm_AO_cd: pwm@2000 { - compatible = "amlogic,meson-g12a-ao-pwm-cd"; - reg = <0x0 0x2000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - uart_AO: serial@3000 { - compatible = "amlogic,meson-gx-uart", - "amlogic,meson-ao-uart"; - reg = <0x0 0x3000 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - uart_AO_B: serial@4000 { - compatible = "amlogic,meson-gx-uart", - "amlogic,meson-ao-uart"; - reg = <0x0 0x4000 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - i2c_AO: i2c@5000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x05000 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - pwm_AO_ab: pwm@7000 { - compatible = "amlogic,meson-g12a-ao-pwm-ab"; - reg = <0x0 0x7000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - ir: ir@8000 { - compatible = "amlogic,meson-gxbb-ir"; - reg = <0x0 0x8000 0x0 0x20>; - interrupts = ; - status = "disabled"; - }; - - saradc: adc@9000 { - compatible = "amlogic,meson-g12a-saradc", - "amlogic,meson-saradc"; - reg = <0x0 0x9000 0x0 0x48>; - #io-channel-cells = <1>; - interrupts = ; - clocks = <&xtal>, - <&clkc_AO CLKID_AO_SAR_ADC>, - <&clkc_AO CLKID_AO_SAR_ADC_CLK>, - <&clkc_AO CLKID_AO_SAR_ADC_SEL>; - clock-names = "clkin", "core", "adc_clk", "adc_sel"; - status = "disabled"; - }; - }; - - vdec: video-decoder@ff620000 { - compatible = "amlogic,g12a-vdec"; - reg = <0x0 0xff620000 0x0 0x10000>, - <0x0 0xffd0e180 0x0 0xe4>; - reg-names = "dos", "esparser"; - interrupts = , - ; - interrupt-names = "vdec", "esparser"; - - amlogic,ao-sysctrl = <&rti>; - amlogic,canvas = <&canvas>; - - clocks = <&clkc CLKID_PARSER>, - <&clkc CLKID_DOS>, - <&clkc CLKID_VDEC_1>, - <&clkc CLKID_VDEC_HEVC>, - <&clkc CLKID_VDEC_HEVCF>; - clock-names = "dos_parser", "dos", "vdec_1", - "vdec_hevc", "vdec_hevcf"; - resets = <&reset RESET_PARSER>; - reset-names = "esparser"; - }; - - vpu: vpu@ff900000 { - compatible = "amlogic,meson-g12a-vpu"; - reg = <0x0 0xff900000 0x0 0x100000>, - <0x0 0xff63c000 0x0 0x1000>; - reg-names = "vpu", "hhi"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - amlogic,canvas = <&canvas>; - - /* CVBS VDAC output port */ - cvbs_vdac_port: port@0 { - reg = <0>; - }; - - /* HDMI-TX output port */ - hdmi_tx_port: port@1 { - reg = <1>; - - hdmi_tx_out: endpoint { - remote-endpoint = <&hdmi_tx_in>; - }; - }; - }; - - gic: interrupt-controller@ffc01000 { - compatible = "arm,gic-400"; - reg = <0x0 0xffc01000 0 0x1000>, - <0x0 0xffc02000 0 0x2000>, - <0x0 0xffc04000 0 0x2000>, - <0x0 0xffc06000 0 0x2000>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <3>; - #address-cells = <0>; - }; - - cbus: bus@ffd00000 { - compatible = "simple-bus"; - reg = <0x0 0xffd00000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; - - reset: reset-controller@1004 { - compatible = "amlogic,meson-axg-reset"; - reg = <0x0 0x1004 0x0 0x9c>; - #reset-cells = <1>; - }; - - gpio_intc: interrupt-controller@f080 { - compatible = "amlogic,meson-g12a-gpio-intc", - "amlogic,meson-gpio-intc"; - reg = <0x0 0xf080 0x0 0x10>; - interrupt-controller; - #interrupt-cells = <2>; - amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; - }; - - spicc0: spi@13000 { - compatible = "amlogic,meson-g12a-spicc"; - reg = <0x0 0x13000 0x0 0x44>; - interrupts = ; - clocks = <&clkc CLKID_SPICC0>, - <&clkc CLKID_SPICC0_SCLK>; - clock-names = "core", "pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spicc1: spi@15000 { - compatible = "amlogic,meson-g12a-spicc"; - reg = <0x0 0x15000 0x0 0x44>; - interrupts = ; - clocks = <&clkc CLKID_SPICC1>, - <&clkc CLKID_SPICC1_SCLK>; - clock-names = "core", "pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spifc: spi@14000 { - compatible = "amlogic,meson-gxbb-spifc"; - status = "disabled"; - reg = <0x0 0x14000 0x0 0x80>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_CLK81>; - }; - - pwm_ef: pwm@19000 { - compatible = "amlogic,meson-g12a-ee-pwm"; - reg = <0x0 0x19000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_cd: pwm@1a000 { - compatible = "amlogic,meson-g12a-ee-pwm"; - reg = <0x0 0x1a000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_ab: pwm@1b000 { - compatible = "amlogic,meson-g12a-ee-pwm"; - reg = <0x0 0x1b000 0x0 0x20>; - #pwm-cells = <3>; - status = "disabled"; - }; - - i2c3: i2c@1c000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x1c000 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - i2c2: i2c@1d000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x1d000 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - i2c1: i2c@1e000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x1e000 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - i2c0: i2c@1f000 { - compatible = "amlogic,meson-axg-i2c"; - status = "disabled"; - reg = <0x0 0x1f000 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_I2C>; - }; - - clk_msr: clock-measure@18000 { - compatible = "amlogic,meson-g12a-clk-measure"; - reg = <0x0 0x18000 0x0 0x10>; - }; - - uart_C: serial@22000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x22000 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - uart_B: serial@23000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x23000 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - - uart_A: serial@24000 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x24000 0x0 0x18>; - interrupts = ; - clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; - status = "disabled"; - }; - }; - - sd_emmc_a: sd@ffe03000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0xffe03000 0x0 0x800>; - interrupts = ; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_A>, - <&clkc CLKID_SD_EMMC_A_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_A>; - }; - - sd_emmc_b: sd@ffe05000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0xffe05000 0x0 0x800>; - interrupts = ; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_B>, - <&clkc CLKID_SD_EMMC_B_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_B>; - }; - - sd_emmc_c: mmc@ffe07000 { - compatible = "amlogic,meson-axg-mmc"; - reg = <0x0 0xffe07000 0x0 0x800>; - interrupts = ; - status = "disabled"; - clocks = <&clkc CLKID_SD_EMMC_C>, - <&clkc CLKID_SD_EMMC_C_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_C>; - }; - - usb: usb@ffe09000 { - status = "disabled"; - compatible = "amlogic,meson-g12a-usb-ctrl"; - reg = <0x0 0xffe09000 0x0 0xa0>; - interrupts = ; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&clkc CLKID_USB>; - resets = <&reset RESET_USB>; - - dr_mode = "otg"; - - phys = <&usb2_phy0>, <&usb2_phy1>, - <&usb3_pcie_phy PHY_TYPE_USB3>; - phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; - - dwc2: usb@ff400000 { - compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; - reg = <0x0 0xff400000 0x0 0x40000>; - interrupts = ; - clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; - clock-names = "otg"; - phys = <&usb2_phy1>; - phy-names = "usb2-phy"; - dr_mode = "peripheral"; - g-rx-fifo-size = <192>; - g-np-tx-fifo-size = <128>; - g-tx-fifo-size = <128 128 16 16 16>; - }; - - dwc3: usb@ff500000 { - compatible = "snps,dwc3"; - reg = <0x0 0xff500000 0x0 0x100000>; - interrupts = ; - dr_mode = "host"; - snps,dis_u2_susphy_quirk; - snps,quirk-frame-length-adjustment = <0x20>; - snps,parkmode-disable-ss-quirk; - }; - }; - - mali: gpu@ffe40000 { - compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; - reg = <0x0 0xffe40000 0x0 0x40000>; - interrupt-parent = <&gic>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&clkc CLKID_MALI>; - resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; - operating-points-v2 = <&gpu_opp_table>; - #cooling-cells = <2>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - arm,no-tick-in-suspend; - }; - - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; - -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12.dtsi deleted file mode 100644 index 6a1f4dcf6..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-g12.dtsi +++ /dev/null @@ -1,385 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Jerome Brunet - */ - -#include "meson-g12-common.dtsi" -#include -#include -#include -#include - -/ { - tdmif_a: audio-controller-0 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_A"; - clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, - <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_b: audio-controller-1 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_B"; - clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, - <&clkc_audio AUD_CLKID_MST_B_SCLK>, - <&clkc_audio AUD_CLKID_MST_B_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_c: audio-controller-2 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_C"; - clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, - <&clkc_audio AUD_CLKID_MST_C_SCLK>, - <&clkc_audio AUD_CLKID_MST_C_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; -}; - -&apb { - pdm: audio-controller@40000 { - compatible = "amlogic,g12a-pdm", - "amlogic,axg-pdm"; - reg = <0x0 0x40000 0x0 0x34>; - #sound-dai-cells = <0>; - sound-name-prefix = "PDM"; - clocks = <&clkc_audio AUD_CLKID_PDM>, - <&clkc_audio AUD_CLKID_PDM_DCLK>, - <&clkc_audio AUD_CLKID_PDM_SYSCLK>; - clock-names = "pclk", "dclk", "sysclk"; - resets = <&clkc_audio AUD_RESET_PDM>; - status = "disabled"; - }; - - audio: bus@42000 { - compatible = "simple-bus"; - reg = <0x0 0x42000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; - - clkc_audio: clock-controller@0 { - status = "disabled"; - compatible = "amlogic,g12a-audio-clkc"; - reg = <0x0 0x0 0x0 0xb4>; - #clock-cells = <1>; - #reset-cells = <1>; - - clocks = <&clkc CLKID_AUDIO>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL3>, - <&clkc CLKID_HIFI_PLL>, - <&clkc CLKID_FCLK_DIV3>, - <&clkc CLKID_FCLK_DIV4>, - <&clkc CLKID_GP0_PLL>; - clock-names = "pclk", - "mst_in0", - "mst_in1", - "mst_in2", - "mst_in3", - "mst_in4", - "mst_in5", - "mst_in6", - "mst_in7"; - - resets = <&reset RESET_AUDIO>; - }; - - toddr_a: audio-controller@100 { - compatible = "amlogic,g12a-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x100 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_A"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_A>; - resets = <&arb AXG_ARB_TODDR_A>, - <&clkc_audio AUD_RESET_TODDR_A>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <512>; - status = "disabled"; - }; - - toddr_b: audio-controller@140 { - compatible = "amlogic,g12a-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x140 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_B"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_B>; - resets = <&arb AXG_ARB_TODDR_B>, - <&clkc_audio AUD_RESET_TODDR_B>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - toddr_c: audio-controller@180 { - compatible = "amlogic,g12a-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x180 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_C"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_C>; - resets = <&arb AXG_ARB_TODDR_C>, - <&clkc_audio AUD_RESET_TODDR_C>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_a: audio-controller@1c0 { - compatible = "amlogic,g12a-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x1c0 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_A"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; - resets = <&arb AXG_ARB_FRDDR_A>, - <&clkc_audio AUD_RESET_FRDDR_A>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <512>; - status = "disabled"; - }; - - frddr_b: audio-controller@200 { - compatible = "amlogic,g12a-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x200 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_B"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; - resets = <&arb AXG_ARB_FRDDR_B>, - <&clkc_audio AUD_RESET_FRDDR_B>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_c: audio-controller@240 { - compatible = "amlogic,g12a-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x240 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_C"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; - resets = <&arb AXG_ARB_FRDDR_C>, - <&clkc_audio AUD_RESET_FRDDR_C>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - arb: reset-controller@280 { - status = "disabled"; - compatible = "amlogic,meson-axg-audio-arb"; - reg = <0x0 0x280 0x0 0x4>; - #reset-cells = <1>; - clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; - }; - - tdmin_a: audio-controller@300 { - compatible = "amlogic,g12a-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x300 0x0 0x40>; - sound-name-prefix = "TDMIN_A"; - resets = <&clkc_audio AUD_RESET_TDMIN_A>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_b: audio-controller@340 { - compatible = "amlogic,g12a-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x340 0x0 0x40>; - sound-name-prefix = "TDMIN_B"; - resets = <&clkc_audio AUD_RESET_TDMIN_B>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_c: audio-controller@380 { - compatible = "amlogic,g12a-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x380 0x0 0x40>; - sound-name-prefix = "TDMIN_C"; - resets = <&clkc_audio AUD_RESET_TDMIN_C>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_lb: audio-controller@3c0 { - compatible = "amlogic,g12a-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x3c0 0x0 0x40>; - sound-name-prefix = "TDMIN_LB"; - resets = <&clkc_audio AUD_RESET_TDMIN_LB>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - spdifin: audio-controller@400 { - compatible = "amlogic,g12a-spdifin", - "amlogic,axg-spdifin"; - reg = <0x0 0x400 0x0 0x30>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFIN"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, - <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; - clock-names = "pclk", "refclk"; - resets = <&clkc_audio AUD_RESET_SPDIFIN>; - status = "disabled"; - }; - - spdifout: audio-controller@480 { - compatible = "amlogic,g12a-spdifout", - "amlogic,axg-spdifout"; - reg = <0x0 0x480 0x0 0x50>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFOUT"; - clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, - <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; - clock-names = "pclk", "mclk"; - resets = <&clkc_audio AUD_RESET_SPDIFOUT>; - status = "disabled"; - }; - - tdmout_a: audio-controller@500 { - compatible = "amlogic,g12a-tdmout"; - reg = <0x0 0x500 0x0 0x40>; - sound-name-prefix = "TDMOUT_A"; - resets = <&clkc_audio AUD_RESET_TDMOUT_A>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_b: audio-controller@540 { - compatible = "amlogic,g12a-tdmout"; - reg = <0x0 0x540 0x0 0x40>; - sound-name-prefix = "TDMOUT_B"; - resets = <&clkc_audio AUD_RESET_TDMOUT_B>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_c: audio-controller@580 { - compatible = "amlogic,g12a-tdmout"; - reg = <0x0 0x580 0x0 0x40>; - sound-name-prefix = "TDMOUT_C"; - resets = <&clkc_audio AUD_RESET_TDMOUT_C>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - spdifout_b: audio-controller@680 { - compatible = "amlogic,g12a-spdifout", - "amlogic,axg-spdifout"; - reg = <0x0 0x680 0x0 0x50>; - #sound-dai-cells = <0>; - sound-name-prefix = "SPDIFOUT_B"; - clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>, - <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>; - clock-names = "pclk", "mclk"; - resets = <&clkc_audio AUD_RESET_SPDIFOUT_B>; - status = "disabled"; - }; - - toacodec: audio-controller@740 { - compatible = "amlogic,g12a-toacodec"; - reg = <0x0 0x740 0x0 0x4>; - #sound-dai-cells = <1>; - sound-name-prefix = "TOACODEC"; - resets = <&clkc_audio AUD_RESET_TOACODEC>; - status = "disabled"; - }; - - tohdmitx: audio-controller@744 { - compatible = "amlogic,g12a-tohdmitx"; - reg = <0x0 0x744 0x0 0x4>; - #sound-dai-cells = <1>; - sound-name-prefix = "TOHDMITX"; - resets = <&clkc_audio AUD_RESET_TOHDMITX>; - status = "disabled"; - }; - }; -}; - -ðmac { - power-domains = <&pwrc PWRC_G12A_ETH_ID>; -}; - -&vpu { - power-domains = <&pwrc PWRC_G12A_VPU_ID>; -}; - -&sd_emmc_a { - amlogic,dram-access-quirk; -}; - -&simplefb_cvbs { - power-domains = <&pwrc PWRC_G12A_VPU_ID>; -}; - -&simplefb_hdmi { - power-domains = <&pwrc PWRC_G12A_VPU_ID>; -}; - diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts deleted file mode 100644 index 71f91e31c..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts +++ /dev/null @@ -1,558 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre SAS. All rights reserved. - */ - -/dts-v1/; - -#include "meson-g12a.dtsi" -#include -#include -#include -#include - -/ { - compatible = "seirobotics,sei510", "amlogic,g12a"; - model = "SEI Robotics SEI510"; - - adc_keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-onoff { - label = "On/Off"; - linux,code = ; - press-threshold-microvolt = <1700000>; - }; - }; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - mono_dac: audio-codec-0 { - compatible = "maxim,max98357a"; - #sound-dai-cells = <0>; - sound-name-prefix = "U16"; - sdmode-gpios = <&gpio GPIOX_8 GPIO_ACTIVE_HIGH>; - }; - - dmics: audio-codec-1 { - #sound-dai-cells = <0>; - compatible = "dmic-codec"; - num-channels = <2>; - wakeup-delay-ms = <50>; - status = "okay"; - sound-name-prefix = "MIC"; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - ao_5v: regulator-ao_5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - emmc_1v8: regulator-emmc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - vddao_3v3_t: regultor-vddao_3v3_t { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3_T"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vddcpu: regulator-vddcpu { - /* - * SY8120B1ABC DC/DC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - pwm-supply = <&dc_in>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddio_ao1v8: regulator-vddio_ao1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "G12A-SEI510"; - audio-aux-devs = <&tdmout_a>, <&tdmout_b>, - <&tdmin_a>, <&tdmin_b>; - audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", - "TDMOUT_A IN 1", "FRDDR_B OUT 0", - "TDMOUT_A IN 2", "FRDDR_C OUT 0", - "TDM_A Playback", "TDMOUT_A OUT", - "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "TODDR_A IN 4", "PDM Capture", - "TODDR_B IN 4", "PDM Capture", - "TODDR_C IN 4", "PDM Capture", - "TDMIN_A IN 0", "TDM_A Capture", - "TDMIN_A IN 3", "TDM_A Loopback", - "TDMIN_B IN 0", "TDM_A Capture", - "TDMIN_B IN 3", "TDM_A Loopback", - "TDMIN_A IN 1", "TDM_B Capture", - "TDMIN_A IN 4", "TDM_B Loopback", - "TDMIN_B IN 1", "TDM_B Capture", - "TDMIN_B IN 4", "TDM_B Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT", - "TODDR_A IN 1", "TDMIN_B OUT", - "TODDR_B IN 1", "TDMIN_B OUT", - "TODDR_C IN 1", "TDMIN_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - dai-link-3 { - sound-dai = <&toddr_a>; - }; - - dai-link-4 { - sound-dai = <&toddr_b>; - }; - - dai-link-5 { - sound-dai = <&toddr_c>; - }; - - /* internal speaker interface */ - dai-link-6 { - sound-dai = <&tdmif_a>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&mono_dac>; - }; - - codec-1 { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; - }; - }; - - /* 8ch hdmi interface */ - dai-link-7 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* internal digital mics */ - dai-link-8 { - sound-dai = <&pdm>; - - codec { - sound-dai = <&dmics>; - }; - }; - - /* hdmi glue */ - dai-link-9 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; - phy-handle = <&internal_ephy>; - phy-mode = "rmii"; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; -}; - -&pdm { - pinctrl-0 = <&pdm_din0_z_pins>, <&pdm_din1_z_pins>, - <&pdm_din2_z_pins>, <&pdm_din3_z_pins>, - <&pdm_dclk_z_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao1v8>; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr50; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_ao1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - non-removable; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&emmc_1v8>; -}; - -&tdmif_a { - pinctrl-0 = <&tdm_a_dout0_pins>, <&tdm_a_fs_pins>, <&tdm_a_sclk_pins>; - pinctrl-names = "default"; - status = "okay"; - - assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD0>, - <&clkc_audio AUD_CLKID_TDM_LRCLK_PAD0>; - assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - assigned-clock-rates = <0>, <0>; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmin_a { - status = "okay"; -}; - -&tdmin_b { - status = "okay"; -}; - -&tdmout_a { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&toddr_a { - status = "okay"; -}; - -&toddr_b { - status = "okay"; -}; - -&toddr_c { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - vbat-supply = <&vddao_3v3>; - vddio-supply = <&vddio_ao1v8>; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts deleted file mode 100644 index 4b5d11e56..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts +++ /dev/null @@ -1,308 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Amlogic, Inc. All rights reserved. - */ - -/dts-v1/; - -#include "meson-g12a.dtsi" -#include -#include - -/ { - compatible = "amlogic,u200", "amlogic,g12a"; - model = "Amlogic Meson G12A U200 Development Board"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - flash_1v8: regulator-flash_1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - main_12v: regulator-main_12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - usb_pwr_en: regulator-usb_pwr_en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "VCC_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&main_12v>; - - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&main_12v>; - regulator-always-on; - }; - - vddcpu: regulator-vddcpu { - /* - * MP8756GD Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - pwm-supply = <&main_12v>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; - phy-handle = <&internal_ephy>; - phy-mode = "rmii"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -/* i2c Touch */ -&i2c0 { - status = "okay"; - pinctrl-0 = <&i2c0_sda_z0_pins>, <&i2c0_sck_z1_pins>; - pinctrl-names = "default"; -}; - -/* i2c CM */ -&i2c2 { - status = "okay"; - pinctrl-0 = <&i2c2_sda_z_pins>, <&i2c2_sck_z_pins>; - pinctrl-names = "default"; -}; - -/* i2c Audio */ -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - non-removable; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&flash_1v8>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - vbus-supply = <&usb_pwr_en>; -}; - -&usb2_phy0 { - phy-supply = <&vcc_5v>; -}; - -&usb2_phy1 { - phy-supply = <&vcc_5v>; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts deleted file mode 100644 index 26b5d9327..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts +++ /dev/null @@ -1,481 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 BayLibre SAS. All rights reserved. - */ - -/dts-v1/; - -#include "meson-g12a.dtsi" -#include -#include -#include - -/ { - compatible = "amediatech,x96-max", "amlogic,g12a"; - model = "Shenzhen Amediatech Technology Co., Ltd X96 Max"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - spdif_dit: audio-codec-1 { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - status = "okay"; - sound-name-prefix = "DIT"; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - flash_1v8: regulator-flash_1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "VCC_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-low; - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - vddcpu: regulator-vddcpu { - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - pwm-supply = <&dc_in>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "G12A-X96-MAX"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "SPDIFOUT IN 0", "FRDDR_A OUT 3", - "SPDIFOUT IN 1", "FRDDR_B OUT 3", - "SPDIFOUT IN 2", "FRDDR_C OUT 3"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* spdif hdmi or toslink interface */ - dai-link-4 { - sound-dai = <&spdifout>; - - codec-0 { - sound-dai = <&spdif_dit>; - }; - - codec-1 { - sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>; - }; - }; - - /* spdif hdmi interface */ - dai-link-5 { - sound-dai = <&spdifout_b>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-6 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; -}; - -&arb { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - linux,rc-map-name = "rc-x96max"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - eee-broken-1000t; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr50; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <100000000>; - non-removable; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&flash_1v8>; -}; - -&spdifout { - pinctrl-0 = <&spdif_out_h_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&spdifout_b { - status = "okay"; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi deleted file mode 100644 index fb0ab27d1..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ /dev/null @@ -1,135 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Amlogic, Inc. All rights reserved. - */ - -#include "meson-g12.dtsi" - -/ { - compatible = "amlogic,g12a"; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - l2: l2-cache0 { - compatible = "cache"; - }; - }; - - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <731000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <731000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <731000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <666666666>; - opp-microvolt = <731000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <731000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <731000>; - }; - - opp-1398000000 { - opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <761000>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <791000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <831000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <861000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <981000>; - }; - }; -}; - -&cpu_thermal { - cooling-maps { - map0 { - trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts deleted file mode 100644 index 124a80901..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - * Copyright (c) 2019 Christian Hewitt - */ - -/dts-v1/; - -#include "meson-g12b-a311d.dtsi" -#include "meson-khadas-vim3.dtsi" -#include "meson-g12b-khadas-vim3.dtsi" - -/ { - compatible = "khadas,vim3", "amlogic,a311d", "amlogic,g12b"; -}; - -/* - * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential - * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between - * an USB3.0 Type A connector and a M.2 Key M slot. - * The PHY driving these differential lines is shared between - * the USB3.0 controller and the PCIe Controller, thus only - * a single controller can use it. - * If the MCU is configured to mux the PCIe/USB3.0 differential lines - * to the M.2 Key M slot, uncomment the following block to disable - * USB3.0 from the USB Complex and enable the PCIe controller. - * The End User is not expected to uncomment the following except for - * testing purposes, but instead rely on the firmware/bootloader to - * update these nodes accordingly if PCIe mode is selected by the MCU. - */ -/* -&pcie { - status = "okay"; -}; - -&usb { - phys = <&usb2_phy0>, <&usb2_phy1>; - phy-names = "usb2-phy0", "usb2-phy1"; -}; - */ diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi deleted file mode 100644 index 8e9ad1e51..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi +++ /dev/null @@ -1,109 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - */ - -#include "meson-g12b.dtsi" - -/ { - cpu_opp_table_0: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <761000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <781000>; - }; - - opp-1398000000 { - opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <811000>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <861000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <901000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <951000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1001000>; - }; - }; - - cpub_opp_table_1: opp-table-1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <731000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <751000>; - }; - - opp-1398000000 { - opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <771000>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <771000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <781000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <791000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <831000>; - }; - - opp-1908000000 { - opp-hz = /bits/ 64 <1908000000>; - opp-microvolt = <861000>; - }; - - opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-microvolt = <911000>; - }; - - opp-2108000000 { - opp-hz = /bits/ 64 <2108000000>; - opp-microvolt = <951000>; - }; - - opp-2208000000 { - opp-hz = /bits/ 64 <2208000000>; - opp-microvolt = <1011000>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts deleted file mode 100644 index f0c56a16a..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - * Copyright (c) 2019 Christian Hewitt - */ - -/dts-v1/; - -#include "meson-g12b-w400.dtsi" -#include - -/ { - compatible = "azw,gtking", "amlogic,g12b"; - model = "Beelink GT-King Pro"; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - power-button { - label = "power"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; - }; - }; - - leds { - compatible = "gpio-leds"; - - white { - label = "power:white"; - gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "G12B-GTKING-PRO"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts deleted file mode 100644 index eeb7bc553..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts +++ /dev/null @@ -1,145 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - * Copyright (c) 2019 Christian Hewitt - */ - -/dts-v1/; - -#include "meson-g12b-w400.dtsi" -#include - -/ { - compatible = "azw,gtking", "amlogic,g12b"; - model = "Beelink GT-King"; - - spdif_dit: audio-codec-1 { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - status = "okay"; - sound-name-prefix = "DIT"; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "G12B-GTKING"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "SPDIFOUT IN 0", "FRDDR_A OUT 3", - "SPDIFOUT IN 1", "FRDDR_B OUT 3", - "SPDIFOUT IN 2", "FRDDR_C OUT 3"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* spdif hdmi or toslink interface */ - dai-link-4 { - sound-dai = <&spdifout>; - - codec-0 { - sound-dai = <&spdif_dit>; - }; - - codec-1 { - sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>; - }; - }; - - /* spdif hdmi interface */ - dai-link-5 { - sound-dai = <&spdifout_b>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-6 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&spdifout { - pinctrl-0 = <&spdif_out_h_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&spdifout_b { - status = "okay"; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi deleted file mode 100644 index 16dd40905..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - * Copyright (c) 2019 Christian Hewitt - */ - -/ { - model = "Khadas VIM3"; - - vddcpu_a: regulator-vddcpu-a { - /* - * MP8756GD Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_A"; - regulator-min-microvolt = <690000>; - regulator-max-microvolt = <1050000>; - - pwm-supply = <&dc_in>; - - pwms = <&pwm_ab 0 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddcpu_b: regulator-vddcpu-b { - /* - * Silergy SY8030DEC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_B"; - regulator-min-microvolt = <690000>; - regulator-max-microvolt = <1050000>; - - pwm-supply = <&vsys_3v3>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; -}; - -&cpu0 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu100 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu101 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu102 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu103 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&pwm_ab { - pinctrl-0 = <&pwm_a_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts deleted file mode 100644 index ce1198ad3..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2-plus.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - */ - -/dts-v1/; - -/* The Amlogic S922X Rev. C supports the same OPPs as the A311D variant */ -#include "meson-g12b-a311d.dtsi" -#include "meson-g12b-odroid-n2.dtsi" - -/ { - compatible = "hardkernel,odroid-n2-plus", "amlogic,s922x", "amlogic,g12b"; - model = "Hardkernel ODROID-N2Plus"; -}; - -&vddcpu_a { - regulator-min-microvolt = <680000>; - regulator-max-microvolt = <1040000>; - - pwms = <&pwm_ab 0 1500 0>; -}; - -&vddcpu_b { - regulator-min-microvolt = <680000>; - regulator-max-microvolt = <1040000>; - - pwms = <&pwm_AO_cd 1 1500 0>; -}; - diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts deleted file mode 100644 index a198a9125..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - */ - -/dts-v1/; - -#include "meson-g12b-s922x.dtsi" -#include "meson-g12b-odroid-n2.dtsi" - -/ { - compatible = "hardkernel,odroid-n2", "amlogic,s922x", "amlogic,g12b"; - model = "Hardkernel ODROID-N2"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi deleted file mode 100644 index 87e8e64ad..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi +++ /dev/null @@ -1,625 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - */ - -#include -#include -#include -#include - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - dio2133: audio-amplifier-0 { - compatible = "simple-audio-amplifier"; - enable-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; - VCC-supply = <&vcc_5v>; - sound-name-prefix = "U19"; - status = "okay"; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "n2:blue"; - gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - tflash_vdd: regulator-tflash_vdd { - compatible = "regulator-fixed"; - - regulator-name = "TFLASH_VDD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - tf_io: gpio-regulator-tf_io { - compatible = "regulator-gpio"; - - regulator-name = "TF_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - }; - - flash_1v8: regulator-flash_1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - main_12v: regulator-main_12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&main_12v>; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vddcpu_a: regulator-vddcpu-a { - /* - * MP8756GD Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_A"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - pwm-supply = <&main_12v>; - - pwms = <&pwm_ab 0 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddcpu_b: regulator-vddcpu-b { - /* - * Silergy SY8120B1ABC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_B"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - pwm-supply = <&main_12v>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - hub_5v: regulator-hub_5v { - compatible = "regulator-fixed"; - regulator-name = "HUB_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to the Hub CHIPENABLE, LOW sets low power state */ - gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usb_pwr_en: regulator-usb_pwr_en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to the microUSB port power enable */ - gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&main_12v>; - regulator-always-on; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "G12B-ODROID-N2"; - audio-widgets = "Line", "Lineout"; - audio-aux-devs = <&tdmout_b>, <&tdmout_c>, <&tdmin_a>, - <&tdmin_b>, <&tdmin_c>, <&tdmin_lb>, - <&dio2133>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "TDMOUT_C IN 0", "FRDDR_A OUT 2", - "TDMOUT_C IN 1", "FRDDR_B OUT 2", - "TDMOUT_C IN 2", "FRDDR_C OUT 2", - "TDM_C Playback", "TDMOUT_C OUT", - "TDMIN_A IN 4", "TDM_B Loopback", - "TDMIN_B IN 4", "TDM_B Loopback", - "TDMIN_C IN 4", "TDM_B Loopback", - "TDMIN_LB IN 1", "TDM_B Loopback", - "TDMIN_A IN 5", "TDM_C Loopback", - "TDMIN_B IN 5", "TDM_C Loopback", - "TDMIN_C IN 5", "TDM_C Loopback", - "TDMIN_LB IN 2", "TDM_C Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT", - "TODDR_A IN 1", "TDMIN_B OUT", - "TODDR_B IN 1", "TDMIN_B OUT", - "TODDR_C IN 1", "TDMIN_B OUT", - "TODDR_A IN 2", "TDMIN_C OUT", - "TODDR_B IN 2", "TDMIN_C OUT", - "TODDR_C IN 2", "TDMIN_C OUT", - "TODDR_A IN 6", "TDMIN_LB OUT", - "TODDR_B IN 6", "TDMIN_LB OUT", - "TODDR_C IN 6", "TDMIN_LB OUT", - "U19 INL", "ACODEC LOLP", - "U19 INR", "ACODEC LORP", - "Lineout", "U19 OUTL", - "Lineout", "U19 OUTR"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - dai-link-3 { - sound-dai = <&toddr_a>; - }; - - dai-link-4 { - sound-dai = <&toddr_b>; - }; - - dai-link-5 { - sound-dai = <&toddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-6 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - - codec-1 { - sound-dai = <&toacodec TOACODEC_IN_B>; - }; - }; - - /* i2s jack output interface */ - dai-link-7 { - sound-dai = <&tdmif_c>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>; - }; - - codec-1 { - sound-dai = <&toacodec TOACODEC_IN_C>; - }; - }; - - /* hdmi glue */ - dai-link-8 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - - /* acodec glue */ - dai-link-9 { - sound-dai = <&toacodec TOACODEC_OUT>; - - codec { - sound-dai = <&acodec>; - }; - }; - }; -}; - -&acodec { - AVDD-supply = <&vddao_1v8>; - status = "okay"; -}; - -&arb { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu100 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu101 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu102 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu103 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&gpio { - /* - * WARNING: The USB Hub on the Odroid-N2 needs a reset signal - * to be turned high in order to be detected by the USB Controller - * This signal should be handled by a USB specific power sequence - * in order to reset the Hub when USB bus is powered down. - */ - usb-hub { - gpio-hog; - gpios = ; - output-high; - line-name = "usb-hub-reset"; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - linux,rc-map-name = "rc-odroid"; -}; - -&pwm_ab { - pinctrl-0 = <&pwm_a_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&tflash_vdd>; - vqmmc-supply = <&tf_io>; - -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&flash_1v8>; -}; - -/* - * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins - * and eMMC Data 4 to 7 pins. - * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0, - * and change bus-width to 4 then spifc can be enabled. - * The SW1 slide should also be set to the correct position. - */ -&spifc { - status = "disabled"; - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - - mx25u64: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mxicy,mx25u6435f", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - }; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmif_c { - status = "okay"; -}; - -&tdmin_a { - status = "okay"; -}; - -&tdmin_b { - status = "okay"; -}; - -&tdmin_c { - status = "okay"; -}; - -&tdmin_lb { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tdmout_c { - status = "okay"; -}; - -&toacodec { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&toddr_a { - status = "okay"; -}; - -&toddr_b { - status = "okay"; -}; - -&toddr_c { - status = "okay"; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - vbus-supply = <&usb_pwr_en>; -}; - -&usb2_phy0 { - phy-supply = <&vcc_5v>; -}; - -&usb2_phy1 { - /* Enable the hub which is connected to this port */ - phy-supply = <&hub_5v>; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-khadas-vim3.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-khadas-vim3.dts deleted file mode 100644 index bba98f982..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-khadas-vim3.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - * Copyright (c) 2019 Christian Hewitt - */ - -/dts-v1/; - -#include "meson-g12b-s922x.dtsi" -#include "meson-khadas-vim3.dtsi" -#include "meson-g12b-khadas-vim3.dtsi" - -/ { - compatible = "khadas,vim3", "amlogic,s922x", "amlogic,g12b"; -}; - -/* - * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential - * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between - * an USB3.0 Type A connector and a M.2 Key M slot. - * The PHY driving these differential lines is shared between - * the USB3.0 controller and the PCIe Controller, thus only - * a single controller can use it. - * If the MCU is configured to mux the PCIe/USB3.0 differential lines - * to the M.2 Key M slot, uncomment the following block to disable - * USB3.0 from the USB Complex and enable the PCIe controller. - * The End User is not expected to uncomment the following except for - * testing purposes, but instead rely on the firmware/bootloader to - * update these nodes accordingly if PCIe mode is selected by the MCU. - */ -/* -&pcie { - status = "okay"; -}; - -&usb { - phys = <&usb2_phy0>, <&usb2_phy1>; - phy-names = "usb2-phy0", "usb2-phy1"; -}; - */ diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi deleted file mode 100644 index 44c23c984..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - */ - -#include "meson-g12b.dtsi" - -/ { - cpu_opp_table_0: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <731000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <731000>; - }; - - opp-1398000000 { - opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <761000>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <791000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <831000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <861000>; - }; - - opp-1896000000 { - opp-hz = /bits/ 64 <1896000000>; - opp-microvolt = <981000>; - }; - - opp-1992000000 { - opp-hz = /bits/ 64 <1992000000>; - opp-microvolt = <1001000>; - }; - }; - - cpub_opp_table_1: opp-table-1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <771000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <771000>; - }; - - opp-1398000000 { - opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <791000>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <821000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <861000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <891000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <981000>; - }; - - opp-1908000000 { - opp-hz = /bits/ 64 <1908000000>; - opp-microvolt = <1022000>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts deleted file mode 100644 index b57bb0bef..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts +++ /dev/null @@ -1,184 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - * Copyright (c) 2019 Christian Hewitt - */ - -/dts-v1/; - -#include "meson-g12b-w400.dtsi" -#include - -/ { - compatible = "ugoos,am6", "amlogic,s922x", "amlogic,g12b"; - model = "Ugoos AM6"; - - spdif_dit: audio-codec-1 { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - status = "okay"; - sound-name-prefix = "DIT"; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "G12B-UGOOS-AM6"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "SPDIFOUT IN 0", "FRDDR_A OUT 3", - "SPDIFOUT IN 1", "FRDDR_B OUT 3", - "SPDIFOUT IN 2", "FRDDR_C OUT 3"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* spdif hdmi or toslink interface */ - dai-link-4 { - sound-dai = <&spdifout>; - - codec-0 { - sound-dai = <&spdif_dit>; - }; - - codec-1 { - sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>; - }; - }; - - /* spdif hdmi interface */ - dai-link-5 { - sound-dai = <&spdifout_b>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-6 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&ir { - linux,rc-map-name = "rc-khadas"; -}; - -&spdifout { - pinctrl-0 = <&spdif_out_h_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&spdifout_b { - status = "okay"; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; - vbus-supply = <&usb_pwr_en>; -}; - -&usb2_phy0 { - phy-supply = <&usb1_pow>; -}; - -&usb2_phy1 { - phy-supply = <&usb1_pow>; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi deleted file mode 100644 index b40d2c100..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi +++ /dev/null @@ -1,425 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - * Copyright (c) 2019 Christian Hewitt - */ - -/dts-v1/; - -#include "meson-g12b.dtsi" -#include "meson-g12b-s922x.dtsi" -#include -#include - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - flash_1v8: regulator-flash_1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - main_12v: regulator-main_12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "VCC_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&main_12v>; - - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vddcpu_a: regulator-vddcpu-a { - /* - * MP1653 Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_A"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - pwm-supply = <&main_12v>; - - pwms = <&pwm_ab 0 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddcpu_b: regulator-vddcpu-b { - /* - * MP1652 Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_B"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - pwm-supply = <&main_12v>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - usb1_pow: regulator-usb1-pow { - compatible = "regulator-fixed"; - regulator-name = "USB1_POW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* connected to SY6280A Power Switch */ - gpio = <&gpio GPIOA_8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usb_pwr_en: regulator-usb-pwr-en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to USB3 Type-A Port power enable */ - gpio = <&gpio GPIOAO_7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddao_1v8: regulator-vddao-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&main_12v>; - regulator-always-on; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cpu0 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu100 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu101 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu102 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu103 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ab { - pinctrl-0 = <&pwm_a_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&pwm_ef { - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - non-removable; - disable-wp; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <100000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&flash_1v8>; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; - vbus-supply = <&usb_pwr_en>; -}; - -&usb2_phy0 { - phy-supply = <&usb1_pow>; -}; - -&usb2_phy1 { - phy-supply = <&usb1_pow>; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi deleted file mode 100644 index ee8fcae9f..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - */ - -#include "meson-g12.dtsi" - -/ { - compatible = "amlogic,g12b"; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu100>; - }; - - core1 { - cpu = <&cpu101>; - }; - - core2 { - cpu = <&cpu102>; - }; - - core3 { - cpu = <&cpu103>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - capacity-dmips-mhz = <592>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - capacity-dmips-mhz = <592>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu100: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x0 0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu101: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x0 0x101>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu102: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x0 0x102>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu103: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x0 0x103>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - l2: l2-cache0 { - compatible = "cache"; - }; - }; -}; - -&clkc { - compatible = "amlogic,g12b-clkc"; -}; - -&cpu_thermal { - cooling-maps { - map0 { - trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -&mali { - dma-coherent; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi deleted file mode 100644 index c2480bab8..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi +++ /dev/null @@ -1,447 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 BayLibre SAS. - * Author: Jerome Brunet - */ - -/* Libretech Amlogic GX PC form factor - AKA: Tartiflette */ - -#include -#include -#include - -/ { - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - update-button { - label = "update"; - linux,code = ; - press-threshold-microvolt = <1300000>; - }; - }; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - spi0 = &spifc; - }; - - dio2133: analog-amplifier { - compatible = "simple-audio-amplifier"; - sound-name-prefix = "AU2"; - VCC-supply = <&vcc5v>; - enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - status = "disabled"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - power-button { - label = "power"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ao_5v: regulator-ao_5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - leds { - compatible = "gpio-leds"; - - led-green { - color = ; - function = LED_FUNCTION_DISK_ACTIVITY; - gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - }; - - led-blue { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio GPIODV_28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - panic-indicator; - }; - }; - - vcc_card: regulator-vcc_card { - compatible = "regulator-fixed"; - regulator-name = "VCC_CARD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddio_ao3v3>; - - gpio = <&gpio GPIODV_4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc5v: regulator-vcc5v { - compatible = "regulator-fixed"; - regulator-name = "VCC5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&ao_5v>; - - gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&ao_5v>; - regulator-always-on; - }; - - vddio_ao3v3: regulator-vddio_ao3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&ao_5v>; - regulator-always-on; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddio_ao3v3>; - regulator-always-on; - }; - - vddio_card: regulator-vddio-card { - compatible = "regulator-gpio"; - regulator-name = "VDDIO_CARD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio GPIODV_5 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - - regulator-settling-time-up-us = <200>; - regulator-settling-time-down-us = <50000>; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "GXL-LIBRETECH-S9XX-PC"; - audio-aux-devs = <&dio2133>; - audio-widgets = "Speaker", "7J4-14 LEFT", - "Speaker", "7J4-11 RIGHT"; - audio-routing = "AU2 INL", "ACODEC LOLN", - "AU2 INR", "ACODEC LORN", - "7J4-14 LEFT", "AU2 OUTL", - "7J4-11 RIGHT", "AU2 OUTR"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - - codec-1 { - sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; - }; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - - dai-link-3 { - sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; - - codec-0 { - sound-dai = <&acodec>; - }; - }; - }; -}; - -&acodec { - AVDD-supply = <&vddio_ao18>; - status = "okay"; -}; - -&aiu { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; - status = "okay"; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_phy_irq_pins>; - pinctrl-names = "default"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; - phy-mode = "rgmii"; - status = "okay"; -}; - -&external_mdio { - external_phy: ethernet-phy@0 { - reg = <0>; - max-speed = <1000>; - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <25 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&pinctrl_periphs { - /* - * Make sure the reset pin of the usb HUB is driven high to take - * it out of reset. - */ - usb1_rst_pins: usb1_rst_irq { - mux { - groups = "GPIODV_3"; - function = "gpio_periphs"; - bias-disable; - output-high; - }; - }; - - /* Make sure the phy irq pin is properly configured as input */ - eth_phy_irq_pins: eth_phy_irq { - mux { - groups = "GPIOZ_15"; - function = "gpio_periphs"; - bias-disable; - output-disable; - }; - }; -}; - -&hdmi_tx { - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc5v>; - status = "okay"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c_C { - pinctrl-0 = <&i2c_c_dv18_pins>; - pinctrl-names = "default"; - status = "okay"; - - rtc: rtc@51 { - reg = <0x51>; - compatible = "nxp,pcf8563"; - #clock-cells = <0>; - clock-output-names = "rtc_clkout"; - }; -}; - -&pwm_AO_ab { - pinctrl-0 = <&pwm_ao_a_3_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_ab { - pinctrl-0 = <&pwm_b_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_ef { - pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; - status = "okay"; -}; - -&saradc { - vref-supply = <&vddio_ao18>; - status = "okay"; -}; - -/* SD card */ -&sd_emmc_b { - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - max-frequency = <200000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vcc_card>; - vqmmc-supply = <&vddio_card>; - - status = "okay"; -}; - -/* eMMC */ -&sd_emmc_c { - pinctrl-0 = <&emmc_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vddio_ao3v3>; - vqmmc-supply = <&vddio_boot>; - - status = "okay"; -}; - -&spifc { - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - status = "okay"; - - gd25lq128: spi-flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <12000000>; - }; -}; - -&uart_AO { - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; - -&usb2_phy0 { - pinctrl-0 = <&usb1_rst_pins>; - pinctrl-names = "default"; - phy-supply = <&vcc5v>; -}; - -&usb2_phy1 { - phy-supply = <&vcc5v>; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi deleted file mode 100644 index f9771b51c..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 BayLibre SAS - * Author: Neil Armstrong - */ - -/ { - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-125000000 { - opp-hz = /bits/ 64 <125000000>; - opp-microvolt = <950000>; - }; - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <950000>; - }; - opp-285714285 { - opp-hz = /bits/ 64 <285714285>; - opp-microvolt = <950000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <950000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <950000>; - }; - opp-666666666 { - opp-hz = /bits/ 64 <666666666>; - opp-microvolt = <950000>; - }; - opp-744000000 { - opp-hz = /bits/ 64 <744000000>; - opp-microvolt = <950000>; - }; - }; -}; - -&apb { - mali: gpu@c0000 { - compatible = "arm,mali-450"; - reg = <0x0 0xc0000 0x0 0x40000>; - interrupts = , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", "gpmmu", "pp", "pmu", - "pp0", "ppmmu0", "pp1", "ppmmu1", - "pp2", "ppmmu2"; - operating-points-v2 = <&gpu_opp_table>; - }; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi deleted file mode 100644 index 6b57e15aa..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi +++ /dev/null @@ -1,324 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -/* Common DTSI for same Amlogic Q200/Q201 and P230/P231 boards using either - * the pin-compatible S912 (GXM) or S905D (GXL) SoCs. - */ - -#include - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - dio2133: analog-amplifier { - compatible = "simple-audio-amplifier"; - sound-name-prefix = "AU2"; - VCC-supply = <&hdmi_5v>; - enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; - }; - - spdif_dit: audio-codec-0 { - #sound-dai-cells = <0>; - compatible = "linux,spdif-dit"; - status = "okay"; - sound-name-prefix = "DIT"; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - hdmi_5v: regulator-hdmi-5v { - compatible = "regulator-fixed"; - - regulator-name = "HDMI_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "GX-P230-Q200"; - audio-aux-devs = <&dio2133>; - audio-widgets = "Line", "Lineout"; - audio-routing = "AU2 INL", "ACODEC LOLP", - "AU2 INR", "ACODEC LORP", - "AU2 INL", "ACODEC LOLN", - "AU2 INR", "ACODEC LORN", - "Lineout", "AU2 OUTL", - "Lineout", "AU2 OUTR"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - - codec-1 { - sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; - }; - }; - - dai-link-3 { - sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>; - - codec-0 { - sound-dai = <&spdif_dit>; - }; - }; - - dai-link-4 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - - dai-link-5 { - sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; - - codec-0 { - sound-dai = <&acodec>; - }; - }; - }; -}; - -&acodec { - AVDD-supply = <&vddio_ao18>; - status = "okay"; -}; - -&aiu { - status = "okay"; - pinctrl-0 = <&spdif_out_h_pins>; - pinctrl-names = "default"; - -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "otg"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi deleted file mode 100644 index 47cbb0a1e..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ /dev/null @@ -1,667 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong - * - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 16 MiB reserved for Hardware ROM Firmware */ - hwrom_reserved: hwrom@0 { - reg = <0x0 0x0 0x0 0x1000000>; - no-map; - }; - - /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@10000000 { - reg = <0x0 0x10000000 0x0 0x200000>; - no-map; - }; - - /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved_alt: secmon@5000000 { - reg = <0x0 0x05000000 0x0 0x300000>; - no-map; - }; - - /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ - secmon_reserved_bl32: secmon@5300000 { - reg = <0x0 0x05300000 0x0 0x2000000>; - no-map; - }; - - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x0 0x10000000>; - alignment = <0x0 0x400000>; - linux,cma-default; - }; - }; - - chosen { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - simplefb_cvbs: framebuffer-cvbs { - compatible = "amlogic,simple-framebuffer", - "simple-framebuffer"; - amlogic,pipeline = "vpu-cvbs"; - power-domains = <&pwrc PWRC_GXBB_VPU_ID>; - status = "disabled"; - }; - - simplefb_hdmi: framebuffer-hdmi { - compatible = "amlogic,simple-framebuffer", - "simple-framebuffer"; - amlogic,pipeline = "vpu-hdmi"; - power-domains = <&pwrc PWRC_GXBB_VPU_ID>; - status = "disabled"; - }; - }; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 0>; - #cooling-cells = <2>; - }; - - l2: l2-cache0 { - compatible = "cache"; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - - thermal-sensors = <&scpi_sensors 0>; - - trips { - cpu_passive: cpu-passive { - temperature = <80000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - - cpu_hot: cpu-hot { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "hot"; - }; - - cpu_critical: cpu-critical { - temperature = <110000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cpu_cooling_maps: cooling-maps { - map0 { - trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - xtal: xtal-clk { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; - - firmware { - sm: secure-monitor { - compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm"; - }; - }; - - efuse: efuse { - compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse"; - #address-cells = <1>; - #size-cells = <1>; - read-only; - secure-monitor = <&sm>; - - sn: sn@14 { - reg = <0x14 0x10>; - }; - - eth_mac: eth_mac@34 { - reg = <0x34 0x10>; - }; - - bid: bid@46 { - reg = <0x46 0x30>; - }; - }; - - scpi { - compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; - mboxes = <&mailbox 1 &mailbox 2>; - shmem = <&cpu_scp_lpri &cpu_scp_hpri>; - - scpi_clocks: clocks { - compatible = "arm,scpi-clocks"; - - scpi_dvfs: scpi_clocks@0 { - compatible = "arm,scpi-dvfs-clocks"; - #clock-cells = <1>; - clock-indices = <0>; - clock-output-names = "vcpu"; - }; - }; - - scpi_sensors: sensors { - compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; - #thermal-sensor-cells = <1>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - cbus: bus@c1100000 { - compatible = "simple-bus"; - reg = <0x0 0xc1100000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; - - gpio_intc: interrupt-controller@9880 { - compatible = "amlogic,meson-gpio-intc"; - reg = <0x0 0x9880 0x0 0x10>; - interrupt-controller; - #interrupt-cells = <2>; - amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; - status = "disabled"; - }; - - reset: reset-controller@4404 { - compatible = "amlogic,meson-gxbb-reset"; - reg = <0x0 0x04404 0x0 0x9c>; - #reset-cells = <1>; - }; - - aiu: audio-controller@5400 { - compatible = "amlogic,aiu"; - #sound-dai-cells = <2>; - sound-name-prefix = "AIU"; - reg = <0x0 0x5400 0x0 0x2ac>; - interrupts = , - ; - interrupt-names = "i2s", "spdif"; - status = "disabled"; - }; - - uart_A: serial@84c0 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x84c0 0x0 0x18>; - interrupts = ; - status = "disabled"; - }; - - uart_B: serial@84dc { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x84dc 0x0 0x18>; - interrupts = ; - status = "disabled"; - }; - - i2c_A: i2c@8500 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x08500 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm_ab: pwm@8550 { - compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; - reg = <0x0 0x08550 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm_cd: pwm@8650 { - compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; - reg = <0x0 0x08650 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - saradc: adc@8680 { - compatible = "amlogic,meson-saradc"; - reg = <0x0 0x8680 0x0 0x34>; - #io-channel-cells = <1>; - interrupts = ; - status = "disabled"; - }; - - pwm_ef: pwm@86c0 { - compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; - reg = <0x0 0x086c0 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - uart_C: serial@8700 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x0 0x8700 0x0 0x18>; - interrupts = ; - status = "disabled"; - }; - - clock-measure@8758 { - compatible = "amlogic,meson-gx-clk-measure"; - reg = <0x0 0x8758 0x0 0x10>; - }; - - i2c_B: i2c@87c0 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x087c0 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c_C: i2c@87e0 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x087e0 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spicc: spi@8d80 { - compatible = "amlogic,meson-gx-spicc"; - reg = <0x0 0x08d80 0x0 0x80>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spifc: spi@8c80 { - compatible = "amlogic,meson-gxbb-spifc"; - reg = <0x0 0x08c80 0x0 0x80>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - watchdog@98d0 { - compatible = "amlogic,meson-gxbb-wdt"; - reg = <0x0 0x098d0 0x0 0x10>; - clocks = <&xtal>; - }; - }; - - gic: interrupt-controller@c4301000 { - compatible = "arm,gic-400"; - reg = <0x0 0xc4301000 0 0x1000>, - <0x0 0xc4302000 0 0x2000>, - <0x0 0xc4304000 0 0x2000>, - <0x0 0xc4306000 0 0x2000>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <3>; - #address-cells = <0>; - }; - - sram: sram@c8000000 { - compatible = "mmio-sram"; - reg = <0x0 0xc8000000 0x0 0x14000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0xc8000000 0x14000>; - - cpu_scp_lpri: scp-sram@0 { - compatible = "amlogic,meson-gxbb-scp-shmem"; - reg = <0x13000 0x400>; - }; - - cpu_scp_hpri: scp-sram@200 { - compatible = "amlogic,meson-gxbb-scp-shmem"; - reg = <0x13400 0x400>; - }; - }; - - aobus: bus@c8100000 { - compatible = "simple-bus"; - reg = <0x0 0xc8100000 0x0 0x100000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; - - sysctrl_AO: sys-ctrl@0 { - compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon"; - reg = <0x0 0x0 0x0 0x100>; - - clkc_AO: clock-controller { - compatible = "amlogic,meson-gx-aoclkc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - }; - - cec_AO: cec@100 { - compatible = "amlogic,meson-gx-ao-cec"; - reg = <0x0 0x00100 0x0 0x14>; - interrupts = ; - status = "disabled"; - }; - - sec_AO: ao-secure@140 { - compatible = "amlogic,meson-gx-ao-secure", "syscon"; - reg = <0x0 0x140 0x0 0x140>; - amlogic,has-chip-id; - }; - - uart_AO: serial@4c0 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; - reg = <0x0 0x004c0 0x0 0x18>; - interrupts = ; - status = "disabled"; - }; - - uart_AO_B: serial@4e0 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; - reg = <0x0 0x004e0 0x0 0x18>; - interrupts = ; - status = "disabled"; - }; - - i2c_AO: i2c@500 { - compatible = "amlogic,meson-gxbb-i2c"; - reg = <0x0 0x500 0x0 0x20>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm_AO_ab: pwm@550 { - compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm"; - reg = <0x0 0x00550 0x0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; - - ir: ir@580 { - compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir"; - reg = <0x0 0x00580 0x0 0x40>; - interrupts = ; - status = "disabled"; - }; - }; - - vdec: video-codec@c8820000 { - compatible = "amlogic,gx-vdec"; - reg = <0x0 0xc8820000 0x0 0x10000>, - <0x0 0xc110a580 0x0 0xe4>; - reg-names = "dos", "esparser"; - - interrupts = , - ; - interrupt-names = "vdec", "esparser"; - - amlogic,ao-sysctrl = <&sysctrl_AO>; - amlogic,canvas = <&canvas>; - }; - - periphs: bus@c8834000 { - compatible = "simple-bus"; - reg = <0x0 0xc8834000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; - - hwrng: rng { - compatible = "amlogic,meson-rng"; - reg = <0x0 0x0 0x0 0x4>; - }; - }; - - dmcbus: bus@c8838000 { - compatible = "simple-bus"; - reg = <0x0 0xc8838000 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>; - - canvas: video-lut@48 { - compatible = "amlogic,canvas"; - reg = <0x0 0x48 0x0 0x14>; - }; - }; - - hiubus: bus@c883c000 { - compatible = "simple-bus"; - reg = <0x0 0xc883c000 0x0 0x2000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; - - sysctrl: system-controller@0 { - compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"; - reg = <0 0 0 0x400>; - - pwrc: power-controller { - compatible = "amlogic,meson-gxbb-pwrc"; - #power-domain-cells = <1>; - amlogic,ao-sysctrl = <&sysctrl_AO>; - }; - }; - - mailbox: mailbox@404 { - compatible = "amlogic,meson-gxbb-mhu"; - reg = <0 0x404 0 0x4c>; - interrupts = , - , - ; - #mbox-cells = <1>; - }; - }; - - ethmac: ethernet@c9410000 { - compatible = "amlogic,meson-gxbb-dwmac", - "snps,dwmac-3.70a", - "snps,dwmac"; - reg = <0x0 0xc9410000 0x0 0x10000>, - <0x0 0xc8834540 0x0 0x4>; - interrupts = ; - interrupt-names = "macirq"; - rx-fifo-depth = <4096>; - tx-fifo-depth = <2048>; - power-domains = <&pwrc PWRC_GXBB_ETHERNET_MEM_ID>; - status = "disabled"; - }; - - apb: apb@d0000000 { - compatible = "simple-bus"; - reg = <0x0 0xd0000000 0x0 0x200000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; - - sd_emmc_a: mmc@70000 { - compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x70000 0x0 0x800>; - interrupts = ; - status = "disabled"; - }; - - sd_emmc_b: mmc@72000 { - compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x72000 0x0 0x800>; - interrupts = ; - status = "disabled"; - }; - - sd_emmc_c: mmc@74000 { - compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; - reg = <0x0 0x74000 0x0 0x800>; - interrupts = ; - status = "disabled"; - }; - }; - - vpu: vpu@d0100000 { - compatible = "amlogic,meson-gx-vpu"; - reg = <0x0 0xd0100000 0x0 0x100000>, - <0x0 0xc883c000 0x0 0x1000>; - reg-names = "vpu", "hhi"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - amlogic,canvas = <&canvas>; - - /* CVBS VDAC output port */ - cvbs_vdac_port: port@0 { - reg = <0>; - }; - - /* HDMI-TX output port */ - hdmi_tx_port: port@1 { - reg = <1>; - - hdmi_tx_out: endpoint { - remote-endpoint = <&hdmi_tx_in>; - }; - }; - }; - - hdmi_tx: hdmi-tx@c883a000 { - compatible = "amlogic,meson-gx-dw-hdmi"; - reg = <0x0 0xc883a000 0x0 0x1c>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <0>; - sound-name-prefix = "HDMITX"; - status = "disabled"; - - /* VPU VENC Input */ - hdmi_tx_venc_port: port@0 { - reg = <0>; - - hdmi_tx_in: endpoint { - remote-endpoint = <&hdmi_tx_out>; - }; - }; - - /* TMDS Output */ - hdmi_tx_tmds_port: port@1 { - reg = <1>; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts deleted file mode 100644 index e8394a826..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts +++ /dev/null @@ -1,82 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Mohammad Rasim - */ - -/dts-v1/; - -#include "meson-gxbb-p20x.dtsi" - -#include -#include -#include -/ { - compatible = "videostrong,kii-pro", "amlogic,meson-gxbb"; - model = "Videostrong KII Pro"; - - leds { - compatible = "gpio-leds"; - status { - gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; - default-state = "off"; - color = ; - function = LED_FUNCTION_STATUS; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <20>; - - button-reset { - label = "reset"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; - }; - }; - -}; - - - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm4335a0"; - }; -}; - - - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rmii_pins>; - pinctrl-names = "default"; - - phy-handle = <ð_phy0>; - phy-mode = "rmii"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* IC Plus IP101GR (0x02430c54) */ - reg = <0>; - reset-assert-us = <10000>; - reset-deassert-us = <10000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&ir { - linux,rc-map-name = "rc-videostrong-kii-pro"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts deleted file mode 100644 index de27beafe..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts +++ /dev/null @@ -1,375 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Andreas Färber - */ - -/dts-v1/; - -#include "meson-gxbb.dtsi" -#include - -/ { - compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb"; - model = "FriendlyARM NanoPi K2"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - - led-stat { - label = "nanopi-k2:blue:stat"; - gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; - default-state = "on"; - panic-indicator; - }; - }; - - vdd_5v: regulator-vdd-5v { - compatible = "regulator-fixed"; - regulator-name = "VDD_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vddio_ao18: regulator-vddio-ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddio_ao3v3: regulator-vddio-ao3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_tf: regulator-vddio-tf { - compatible = "regulator-gpio"; - - regulator-name = "VDDIO_TF"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - - regulator-settling-time-up-us = <100>; - regulator-settling-time-down-us = <5000>; - }; - - wifi_32k: wifi-32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi_32k>; - clock-names = "ext_clock"; - }; - - vcc1v8: regulator-vcc1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - /* CVBS is available on CON1 pin 36, disabled by default */ - cvbs-connector { - compatible = "composite-video-connector"; - status = "disabled"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; - - phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - amlogic,tx-delay-ns = <2>; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_15 */ - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&gpio_ao { - gpio-line-names = "UART TX", "UART RX", "Power Control", "Power Key In", - "VCCK En", "CON1 Header Pin31", - "I2S Header Pin6", "IR In", "I2S Header Pin7", - "I2S Header Pin3", "I2S Header Pin4", - "I2S Header Pin5", "HDMI CEC", "SYS LED", - /* GPIO_TEST_N */ - ""; -}; - -&gpio { - gpio-line-names = /* Bank GPIOZ */ - "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk", - "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2", - "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En", - "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3", - "Eth PHY nRESET", "Eth PHY Intc", - /* Bank GPIOH */ - "HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL", - "CON1 Header Pin33", - /* Bank BOOT */ - "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4", - "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk", - "eMMC Reset", "eMMC CMD", - "", "", "", "", "eMMC DS", - "", "", - /* Bank CARD */ - "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", - "SDCard D3", "SDCard D2", "SDCard Det", - /* Bank GPIODV */ - "", "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", - "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK", - "VDDEE Regulator", "VCCK Regulator", - /* Bank GPIOY */ - "CON1 Header Pin7", "CON1 Header Pin11", - "CON1 Header Pin13", "CON1 Header Pin15", - "CON1 Header Pin18", "CON1 Header Pin19", - "CON1 Header Pin22", "CON1 Header Pin21", - "CON1 Header Pin24", "CON1 Header Pin23", - "CON1 Header Pin26", "CON1 Header Pin29", - "CON1 Header Pin32", "CON1 Header Pin8", - "CON1 Header Pin10", "CON1 Header Pin16", - "CON1 Header Pin12", - /* Bank GPIOX */ - "WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2", - "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD", - "WIFI Power Enable", "WIFI WAKE HOST", - "Bluetooth PCM DOUT", "Bluetooth PCM DIN", - "Bluetooth PCM SYNC", "Bluetooth PCM CLK", - "Bluetooth UART TX", "Bluetooth UART RX", - "Bluetooth UART CTS", "Bluetooth UART RTS", - "", "", "", "WIFI 32K", "Bluetooth Enable", - "Bluetooth WAKE HOST", "", - /* Bank GPIOCLK */ - "", "CON1 Header Pin35", "", ""; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>, <&sdio_irq_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddio_ao3v3>; - vqmmc-supply = <&vddio_ao18>; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - }; -}; - -/* SD */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - max-frequency = <100000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddio_ao3v3>; - vqmmc-supply = <&vddio_tf>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "disabled"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - max-frequency = <200000000>; - non-removable; - disable-wp; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc3v3>; - vqmmc-supply = <&vcc1v8>; -}; - -/* DBG_UART */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -/* Bluetooth on AP6212 */ -&uart_A { - status = "disabled"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; -}; - -/* 40-pin CON1 */ -&uart_C { - status = "disabled"; - pinctrl-0 = <&uart_c_pins>; - pinctrl-names = "default"; -}; - -&usb0_phy { - status = "okay"; - phy-supply = <&vdd_5v>; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts deleted file mode 100644 index 67d901ed2..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts +++ /dev/null @@ -1,291 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * Copyright (c) 2016 BayLibre, Inc. - * Author: Neil Armstrong - */ - -/dts-v1/; - -#include "meson-gxbb.dtsi" -#include -#include - -/ { - compatible = "nexbox,a95x", "amlogic,meson-gxbb"; - model = "NEXBOX A95X"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - leds { - compatible = "gpio-leds"; - led-blue { - label = "a95x:system-status"; - gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - button@0 { - label = "reset"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; - }; - }; - - usb_pwr: regulator-usb-pwrs { - compatible = "regulator-fixed"; - - regulator-name = "USB_PWR"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddio_card: gpio-regulator { - compatible = "regulator-gpio"; - - regulator-name = "VDDIO_CARD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - - /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ - states = <1800000 0>, - <3300000 1>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rmii_pins>; - pinctrl-names = "default"; - - phy-handle = <ð_phy0>; - phy-mode = "rmii"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* IC Plus IP101GR (0x02430c54) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <10000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_card>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0_phy { - status = "okay"; - phy-supply = <&usb_pwr>; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts deleted file mode 100644 index 50de1d01e..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ /dev/null @@ -1,378 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * Copyright (c) 2016 BayLibre, Inc. - * Author: Kevin Hilman - */ - -/dts-v1/; - -#include "meson-gxbb.dtsi" -#include - -/ { - compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb"; - model = "Hardkernel ODROID-C2"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - usb_otg_pwr: regulator-usb-pwrs { - compatible = "regulator-fixed"; - - regulator-name = "USB_OTG_PWR"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - /* - * signal name from schematics: PWREN - */ - gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* - * signal name from schematics: USB_POWER - */ - vin-supply = <&p5v0>; - }; - - leds { - compatible = "gpio-leds"; - led-blue { - label = "c2:blue:alive"; - gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - p5v0: regulator-p5v0 { - compatible = "regulator-fixed"; - - regulator-name = "P5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - hdmi_p5v0: regulator-hdmi_p5v0 { - compatible = "regulator-fixed"; - regulator-name = "HDMI_P5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - /* AP2331SA-7 */ - vin-supply = <&p5v0>; - }; - - tflash_vdd: regulator-tflash_vdd { - compatible = "regulator-fixed"; - - regulator-name = "TFLASH_VDD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - /* - * signal name from schematics: TFLASH_VDD_EN - */ - gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* U16 RT9179GB */ - vin-supply = <&vddio_ao3v3>; - }; - - tf_io: gpio-regulator-tf_io { - compatible = "regulator-gpio"; - - regulator-name = "TF_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - /* - * signal name from schematics: TF_3V3N_1V8_EN - */ - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - /* U12/U13 RT9179GB */ - vin-supply = <&vddio_ao3v3>; - }; - - vcc1v8: regulator-vcc1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - /* U18 RT9179GB */ - vin-supply = <&vddio_ao3v3>; - }; - - vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_ao1v8: regulator-vddio-ao1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - /* U17 RT9179GB */ - vin-supply = <&p5v0>; - }; - - vddio_ao3v3: regulator-vddio-ao3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - /* U11 MP2161GJ-C499 */ - vin-supply = <&p5v0>; - }; - - ddr3_1v5: regulator-ddr3_1v5 { - compatible = "regulator-fixed"; - regulator-name = "DDR3_1V5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - /* U15 MP2161GJ-C499 */ - vin-supply = <&p5v0>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; - phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - amlogic,tx-delay-ns = <2>; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_15 */ - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&gpio_ao { - /* - * WARNING: The USB Hub on the Odroid-C2 needs a reset signal - * to be turned high in order to be detected by the USB Controller - * This signal should be handled by a USB specific power sequence - * in order to reset the Hub when USB bus is powered down. - */ - usb-hub { - gpio-hog; - gpios = ; - output-high; - line-name = "usb-hub-reset"; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_p5v0>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c_A { - status = "okay"; - pinctrl-0 = <&i2c_a_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - linux,rc-map-name = "rc-odroid"; -}; - -&gpio_ao { - gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En", - "USB HUB nRESET", "USB OTG Power En", - "J7 Header Pin2", "IR In", "J7 Header Pin4", - "J7 Header Pin6", "J7 Header Pin5", "J7 Header Pin7", - "HDMI CEC", "SYS LED", - /* GPIO_TEST_N */ - ""; -}; - -&gpio { - gpio-line-names = /* Bank GPIOZ */ - "Eth MDIO", "Eth MDC", "Eth RGMII RX Clk", - "Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2", - "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En", - "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3", - "Eth PHY nRESET", "Eth PHY Intc", - /* Bank GPIOH */ - "HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL", "", - /* Bank BOOT */ - "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4", - "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk", - "eMMC Reset", "eMMC CMD", - "", "", "", "", "", "", "", - /* Bank CARD */ - "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", - "SDCard D3", "SDCard D2", "SDCard Det", - /* Bank GPIODV */ - "", "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", - "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK", - "PWM D", "PWM B", - /* Bank GPIOY */ - "Revision Bit0", "Revision Bit1", "", - "J2 Header Pin35", "", "", "", "J2 Header Pin36", - "J2 Header Pin31", "", "", "", "TF VDD En", - "J2 Header Pin32", "J2 Header Pin26", "", "", - /* Bank GPIOX */ - "J2 Header Pin29", "J2 Header Pin24", - "J2 Header Pin23", "J2 Header Pin22", - "J2 Header Pin21", "J2 Header Pin18", - "J2 Header Pin33", "J2 Header Pin19", - "J2 Header Pin16", "J2 Header Pin15", - "J2 Header Pin12", "J2 Header Pin13", - "J2 Header Pin8", "J2 Header Pin10", - "", "", "", "", "", - "J2 Header Pin11", "", "J2 Header Pin7", "", - /* Bank GPIOCLK */ - "", "", "", ""; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc1v8>; -}; - -&scpi_clocks { - status = "disabled"; -}; - -/* SD */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - max-frequency = <100000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&tflash_vdd>; - vqmmc-supply = <&tf_io>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - max-frequency = <200000000>; - non-removable; - disable-wp; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc3v3>; - vqmmc-supply = <&vcc1v8>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0_phy { - status = "disabled"; - phy-supply = <&usb_otg_pwr>; -}; - -&usb1_phy { - status = "okay"; - phy-supply = <&usb_otg_pwr>; -}; - -&usb0 { - status = "disabled"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts deleted file mode 100644 index 3c93d1898..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * Copyright (c) 2016 BayLibre, Inc. - * Author: Kevin Hilman - */ - -/dts-v1/; - -#include "meson-gxbb-p20x.dtsi" -#include - -/ { - compatible = "amlogic,p200", "amlogic,meson-gxbb"; - model = "Amlogic Meson GXBB P200 Development Board"; - - avdd18_usb_adc: regulator-avdd18_usb_adc { - compatible = "regulator-fixed"; - regulator-name = "AVDD18_USB_ADC"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - adc_keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - - button-home { - label = "Home"; - linux,code = ; - press-threshold-microvolt = <900000>; /* 50% */ - }; - - button-esc { - label = "Esc"; - linux,code = ; - press-threshold-microvolt = <684000>; /* 38% */ - }; - - button-up { - label = "Volume Up"; - linux,code = ; - press-threshold-microvolt = <468000>; /* 26% */ - }; - - button-down { - label = "Volume Down"; - linux,code = ; - press-threshold-microvolt = <252000>; /* 14% */ - }; - - button-menu { - label = "Menu"; - linux,code = ; - press-threshold-microvolt = <0>; /* 0% */ - }; - }; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; - phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - amlogic,tx-delay-ns = <2>; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@3 { - /* Micrel KSZ9031 (0x00221620) */ - reg = <3>; - - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_15 */ - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&i2c_B { - status = "okay"; - pinctrl-0 = <&i2c_b_pins>; - pinctrl-names = "default"; -}; - -&saradc { - status = "okay"; - vref-supply = <&avdd18_usb_adc>; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts deleted file mode 100644 index 150a82f3b..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * Copyright (c) 2016 BayLibre, Inc. - * Author: Kevin Hilman - */ - -/dts-v1/; - -#include "meson-gxbb-p20x.dtsi" - -/ { - compatible = "amlogic,p201", "amlogic,meson-gxbb"; - model = "Amlogic Meson GXBB P201 Development Board"; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rmii_pins>; - pinctrl-names = "default"; - phy-mode = "rmii"; - - snps,reset-gpio = <&gpio GPIOZ_14 0>; - snps,reset-delays-us = <0>, <10000>, <1000000>; - snps,reset-active-low; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi deleted file mode 100644 index e803a466f..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +++ /dev/null @@ -1,250 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * Copyright (c) 2016 BayLibre, Inc. - * Author: Kevin Hilman - */ - -#include "meson-gxbb.dtsi" - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - usb_pwr: regulator-usb-pwrs { - compatible = "regulator-fixed"; - - regulator-name = "USB_PWR"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - /* signal name in schematic: USB_PWR_EN */ - gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddio_card: gpio-regulator { - compatible = "regulator-gpio"; - - regulator-name = "VDDIO_CARD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - - /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ - states = <1800000 0>, - <3300000 1>; - - regulator-settling-time-up-us = <10000>; - regulator-settling-time-down-us = <150000>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - cvbs_connector: cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - max-frequency = <100000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_card>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0_phy { - status = "okay"; - phy-supply = <&usb_pwr>; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-meta.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-meta.dts deleted file mode 100644 index c928adf85..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-meta.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -/dts-v1/; - -#include "meson-gxbb-vega-s95.dtsi" - -/ { - compatible = "tronsmart,vega-s95-meta", "tronsmart,vega-s95", "amlogic,meson-gxbb"; - model = "Tronsmart Vega S95 Meta"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-pro.dts deleted file mode 100644 index e81e1d68b..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-pro.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -/dts-v1/; - -#include "meson-gxbb-vega-s95.dtsi" - -/ { - compatible = "tronsmart,vega-s95-pro", "tronsmart,vega-s95", "amlogic,meson-gxbb"; - model = "Tronsmart Vega S95 Pro"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-telos.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-telos.dts deleted file mode 100644 index a8fca0c69..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-telos.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -/dts-v1/; - -#include "meson-gxbb-vega-s95.dtsi" - -/ { - compatible = "tronsmart,vega-s95-telos", "tronsmart,vega-s95", "amlogic,meson-gxbb"; - model = "Tronsmart Vega S95 Telos"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi deleted file mode 100644 index 9b0b81f19..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +++ /dev/null @@ -1,276 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -#include "meson-gxbb.dtsi" - -/ { - compatible = "tronsmart,vega-s95", "amlogic,meson-gxbb"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-blue { - label = "vega-s95:blue:on"; - gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; - default-state = "on"; - panic-indicator; - }; - }; - - usb_pwr: regulator-usb-pwrs { - compatible = "regulator-fixed"; - - regulator-name = "USB_PWR"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; - - phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - amlogic,tx-delay-ns = <2>; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_15 */ - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - linux,rc-map-name = "rc-vega-s9x"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vcc_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* This is connected to the Bluetooth module: */ -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0_phy { - status = "okay"; - phy-supply = <&usb_pwr>; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts deleted file mode 100644 index 83b985bb0..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 BayLibre, Inc. - * Author: Neil Armstrong - */ - -/dts-v1/; - -#include "meson-gxbb-wetek.dtsi" - -/ { - compatible = "wetek,hub", "amlogic,meson-gxbb"; - model = "WeTek Hub"; -}; - -&ir { - linux,rc-map-name = "rc-wetek-hub"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts deleted file mode 100644 index 2ab8a3d10..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 BayLibre, Inc. - * Author: Neil Armstrong - */ - -/dts-v1/; - -#include "meson-gxbb-wetek.dtsi" -#include - -/ { - compatible = "wetek,play2", "amlogic,meson-gxbb"; - model = "WeTek Play 2"; - - leds { - led-wifi { - label = "wetek-play:wifi-status"; - gpios = <&gpio GPIODV_26 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-ethernet { - label = "wetek-play:ethernet-status"; - gpios = <&gpio GPIODV_27 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - button@0 { - label = "reset"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&i2c_A { - status = "okay"; - pinctrl-0 = <&i2c_a_pins>; - pinctrl-names = "default"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&ir { - linux,rc-map-name = "rc-wetek-play2"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi deleted file mode 100644 index a4d34398d..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi +++ /dev/null @@ -1,289 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * Copyright (c) 2016 BayLibre, Inc. - * Author: Kevin Hilman - */ - -#include "meson-gxbb.dtsi" -#include - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - leds { - compatible = "gpio-leds"; - - led-system { - label = "wetek-play:system-status"; - gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; - default-state = "on"; - panic-indicator; - }; - }; - - usb_pwr: regulator-usb-pwrs { - compatible = "regulator-fixed"; - - regulator-name = "USB_PWR"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; - - phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - amlogic,tx-delay-ns = <2>; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - eth_phy0: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_15 */ - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vddio_ao18>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vcc_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* This is connected to the Bluetooth module: */ -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>; - }; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb0_phy { - status = "okay"; - phy-supply = <&usb_pwr>; -}; - -&usb0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi deleted file mode 100644 index 7c029f552..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ /dev/null @@ -1,856 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - */ - -#include "meson-gx.dtsi" -#include "meson-gx-mali450.dtsi" -#include -#include -#include -#include -#include - -/ { - compatible = "amlogic,meson-gxbb"; - - soc { - usb0_phy: phy@c0000000 { - compatible = "amlogic,meson-gxbb-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0xc0000000 0x0 0x20>; - resets = <&reset RESET_USB_OTG>; - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; - clock-names = "usb_general", "usb"; - status = "disabled"; - }; - - usb1_phy: phy@c0000020 { - compatible = "amlogic,meson-gxbb-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0xc0000020 0x0 0x20>; - resets = <&reset RESET_USB_OTG>; - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; - clock-names = "usb_general", "usb"; - status = "disabled"; - }; - - usb0: usb@c9000000 { - compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; - reg = <0x0 0xc9000000 0x0 0x40000>; - interrupts = ; - clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; - clock-names = "otg"; - phys = <&usb0_phy>; - phy-names = "usb2-phy"; - dr_mode = "host"; - status = "disabled"; - }; - - usb1: usb@c9100000 { - compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; - reg = <0x0 0xc9100000 0x0 0x40000>; - interrupts = ; - clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; - clock-names = "otg"; - phys = <&usb1_phy>; - phy-names = "usb2-phy"; - dr_mode = "host"; - status = "disabled"; - }; - }; -}; - -&aiu { - compatible = "amlogic,aiu-gxbb", "amlogic,aiu"; - clocks = <&clkc CLKID_AIU_GLUE>, - <&clkc CLKID_I2S_OUT>, - <&clkc CLKID_AOCLK_GATE>, - <&clkc CLKID_CTS_AMCLK>, - <&clkc CLKID_MIXER_IFACE>, - <&clkc CLKID_IEC958>, - <&clkc CLKID_IEC958_GATE>, - <&clkc CLKID_CTS_MCLK_I958>, - <&clkc CLKID_CTS_I958>; - clock-names = "pclk", - "i2s_pclk", - "i2s_aoclk", - "i2s_mclk", - "i2s_mixer", - "spdif_pclk", - "spdif_aoclk", - "spdif_mclk", - "spdif_mclk_sel"; - resets = <&reset RESET_AIU>; -}; - -&aobus { - pinctrl_aobus: pinctrl@14 { - compatible = "amlogic,meson-gxbb-aobus-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio_ao: bank@14 { - reg = <0x0 0x00014 0x0 0x8>, - <0x0 0x0002c 0x0 0x4>, - <0x0 0x00024 0x0 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 0 14>; - }; - - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_tx_ao_a", "uart_rx_ao_a"; - function = "uart_ao"; - bias-disable; - }; - }; - - uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { - mux { - groups = "uart_cts_ao_a", - "uart_rts_ao_a"; - function = "uart_ao"; - bias-disable; - }; - }; - - uart_ao_b_pins: uart_ao_b { - mux { - groups = "uart_tx_ao_b", "uart_rx_ao_b"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { - mux { - groups = "uart_cts_ao_b", - "uart_rts_ao_b"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - remote_input_ao_pins: remote_input_ao { - mux { - groups = "remote_input_ao"; - function = "remote_input_ao"; - bias-disable; - }; - }; - - i2c_ao_pins: i2c_ao { - mux { - groups = "i2c_sck_ao", - "i2c_sda_ao"; - function = "i2c_ao"; - bias-disable; - }; - }; - - pwm_ao_a_3_pins: pwm_ao_a_3 { - mux { - groups = "pwm_ao_a_3"; - function = "pwm_ao_a_3"; - bias-disable; - }; - }; - - pwm_ao_a_6_pins: pwm_ao_a_6 { - mux { - groups = "pwm_ao_a_6"; - function = "pwm_ao_a_6"; - bias-disable; - }; - }; - - pwm_ao_a_12_pins: pwm_ao_a_12 { - mux { - groups = "pwm_ao_a_12"; - function = "pwm_ao_a_12"; - bias-disable; - }; - }; - - pwm_ao_b_pins: pwm_ao_b { - mux { - groups = "pwm_ao_b"; - function = "pwm_ao_b"; - bias-disable; - }; - }; - - i2s_am_clk_pins: i2s_am_clk { - mux { - groups = "i2s_am_clk"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - i2s_out_ao_clk_pins: i2s_out_ao_clk { - mux { - groups = "i2s_out_ao_clk"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - i2s_out_lr_clk_pins: i2s_out_lr_clk { - mux { - groups = "i2s_out_lr_clk"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - i2s_out_ch01_ao_pins: i2s_out_ch01_ao { - mux { - groups = "i2s_out_ch01_ao"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - i2s_out_ch23_ao_pins: i2s_out_ch23_ao { - mux { - groups = "i2s_out_ch23_ao"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - i2s_out_ch45_ao_pins: i2s_out_ch45_ao { - mux { - groups = "i2s_out_ch45_ao"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - spdif_out_ao_6_pins: spdif_out_ao_6 { - mux { - groups = "spdif_out_ao_6"; - function = "spdif_out_ao"; - }; - }; - - spdif_out_ao_13_pins: spdif_out_ao_13 { - mux { - groups = "spdif_out_ao_13"; - function = "spdif_out_ao"; - bias-disable; - }; - }; - - ao_cec_pins: ao_cec { - mux { - groups = "ao_cec"; - function = "cec_ao"; - bias-disable; - }; - }; - - ee_cec_pins: ee_cec { - mux { - groups = "ee_cec"; - function = "cec_ao"; - bias-disable; - }; - }; - }; -}; - -&cbus { - spifc: spi@8c80 { - compatible = "amlogic,meson-gxbb-spifc"; - reg = <0x0 0x08c80 0x0 0x80>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkc CLKID_SPI>; - status = "disabled"; - }; -}; - -&cec_AO { - clocks = <&clkc_AO CLKID_AO_CEC_32K>; - clock-names = "core"; -}; - -&clkc_AO { - compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; - clocks = <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "mpeg-clk"; -}; - -&efuse { - clocks = <&clkc CLKID_EFUSE>; -}; - -ðmac { - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; -}; - -&gpio_intc { - compatible = "amlogic,meson-gpio-intc", - "amlogic,meson-gxbb-gpio-intc"; - status = "okay"; -}; - -&hdmi_tx { - compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; - resets = <&reset RESET_HDMITX_CAPB3>, - <&reset RESET_HDMI_SYSTEM_RESET>, - <&reset RESET_HDMI_TX>; - reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; - clocks = <&clkc CLKID_HDMI_PCLK>, - <&clkc CLKID_CLK81>, - <&clkc CLKID_GCLK_VENCI_INT0>; - clock-names = "isfr", "iahb", "venci"; -}; - -&sysctrl { - clkc: clock-controller { - compatible = "amlogic,gxbb-clkc"; - #clock-cells = <1>; - clocks = <&xtal>; - clock-names = "xtal"; - }; -}; - -&hwrng { - clocks = <&clkc CLKID_RNG0>; - clock-names = "core"; -}; - -&i2c_A { - clocks = <&clkc CLKID_I2C>; -}; - -&i2c_AO { - clocks = <&clkc CLKID_AO_I2C>; -}; - -&i2c_B { - clocks = <&clkc CLKID_I2C>; -}; - -&i2c_C { - clocks = <&clkc CLKID_I2C>; -}; - -&mali { - compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; - - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; - clock-names = "bus", "core"; - - assigned-clocks = <&clkc CLKID_GP0_PLL>; - assigned-clock-rates = <744000000>; -}; - -&periphs { - pinctrl_periphs: pinctrl@4b0 { - compatible = "amlogic,meson-gxbb-periphs-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio: bank@4b0 { - reg = <0x0 0x004b0 0x0 0x28>, - <0x0 0x004e8 0x0 0x14>, - <0x0 0x00520 0x0 0x14>, - <0x0 0x00430 0x0 0x40>; - reg-names = "mux", "pull", "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_periphs 0 0 119>; - }; - - emmc_pins: emmc { - mux-0 { - groups = "emmc_nand_d07", - "emmc_cmd"; - function = "emmc"; - bias-pull-up; - }; - - mux-1 { - groups = "emmc_clk"; - function = "emmc"; - bias-disable; - }; - }; - - emmc_ds_pins: emmc-ds { - mux { - groups = "emmc_ds"; - function = "emmc"; - bias-pull-down; - }; - }; - - emmc_clk_gate_pins: emmc_clk_gate { - mux { - groups = "BOOT_8"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - nor_pins: nor { - mux { - groups = "nor_d", - "nor_q", - "nor_c", - "nor_cs"; - function = "nor"; - bias-disable; - }; - }; - - spi_pins: spi-pins { - mux { - groups = "spi_miso", - "spi_mosi", - "spi_sclk"; - function = "spi"; - bias-disable; - }; - }; - - spi_ss0_pins: spi-ss0 { - mux { - groups = "spi_ss0"; - function = "spi"; - bias-disable; - }; - }; - - sdcard_pins: sdcard { - mux-0 { - groups = "sdcard_d0", - "sdcard_d1", - "sdcard_d2", - "sdcard_d3", - "sdcard_cmd"; - function = "sdcard"; - bias-pull-up; - }; - - mux-1 { - groups = "sdcard_clk"; - function = "sdcard"; - bias-disable; - }; - }; - - sdcard_clk_gate_pins: sdcard_clk_gate { - mux { - groups = "CARD_2"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - sdio_pins: sdio { - mux-0 { - groups = "sdio_d0", - "sdio_d1", - "sdio_d2", - "sdio_d3", - "sdio_cmd"; - function = "sdio"; - bias-pull-up; - }; - - mux-1 { - groups = "sdio_clk"; - function = "sdio"; - bias-disable; - }; - }; - - sdio_clk_gate_pins: sdio_clk_gate { - mux { - groups = "GPIOX_4"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - sdio_irq_pins: sdio_irq { - mux { - groups = "sdio_irq"; - function = "sdio"; - bias-disable; - }; - }; - - uart_a_pins: uart_a { - mux { - groups = "uart_tx_a", - "uart_rx_a"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_a_cts_rts_pins: uart_a_cts_rts { - mux { - groups = "uart_cts_a", - "uart_rts_a"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_b_pins: uart_b { - mux { - groups = "uart_tx_b", - "uart_rx_b"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_b_cts_rts_pins: uart_b_cts_rts { - mux { - groups = "uart_cts_b", - "uart_rts_b"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_c_pins: uart_c { - mux { - groups = "uart_tx_c", - "uart_rx_c"; - function = "uart_c"; - bias-disable; - }; - }; - - uart_c_cts_rts_pins: uart_c_cts_rts { - mux { - groups = "uart_cts_c", - "uart_rts_c"; - function = "uart_c"; - bias-disable; - }; - }; - - i2c_a_pins: i2c_a { - mux { - groups = "i2c_sck_a", - "i2c_sda_a"; - function = "i2c_a"; - bias-disable; - }; - }; - - i2c_b_pins: i2c_b { - mux { - groups = "i2c_sck_b", - "i2c_sda_b"; - function = "i2c_b"; - bias-disable; - }; - }; - - i2c_c_pins: i2c_c { - mux { - groups = "i2c_sck_c", - "i2c_sda_c"; - function = "i2c_c"; - bias-disable; - }; - }; - - eth_rgmii_pins: eth-rgmii { - mux { - groups = "eth_mdio", - "eth_mdc", - "eth_clk_rx_clk", - "eth_rx_dv", - "eth_rxd0", - "eth_rxd1", - "eth_rxd2", - "eth_rxd3", - "eth_rgmii_tx_clk", - "eth_tx_en", - "eth_txd0", - "eth_txd1", - "eth_txd2", - "eth_txd3"; - function = "eth"; - bias-disable; - }; - }; - - eth_rmii_pins: eth-rmii { - mux { - groups = "eth_mdio", - "eth_mdc", - "eth_clk_rx_clk", - "eth_rx_dv", - "eth_rxd0", - "eth_rxd1", - "eth_tx_en", - "eth_txd0", - "eth_txd1"; - function = "eth"; - bias-disable; - }; - }; - - pwm_a_x_pins: pwm_a_x { - mux { - groups = "pwm_a_x"; - function = "pwm_a_x"; - bias-disable; - }; - }; - - pwm_a_y_pins: pwm_a_y { - mux { - groups = "pwm_a_y"; - function = "pwm_a_y"; - bias-disable; - }; - }; - - pwm_b_pins: pwm_b { - mux { - groups = "pwm_b"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_d_pins: pwm_d { - mux { - groups = "pwm_d"; - function = "pwm_d"; - bias-disable; - }; - }; - - pwm_e_pins: pwm_e { - mux { - groups = "pwm_e"; - function = "pwm_e"; - bias-disable; - }; - }; - - pwm_f_x_pins: pwm_f_x { - mux { - groups = "pwm_f_x"; - function = "pwm_f_x"; - bias-disable; - }; - }; - - pwm_f_y_pins: pwm_f_y { - mux { - groups = "pwm_f_y"; - function = "pwm_f_y"; - bias-disable; - }; - }; - - hdmi_hpd_pins: hdmi_hpd { - mux { - groups = "hdmi_hpd"; - function = "hdmi_hpd"; - bias-disable; - }; - }; - - hdmi_i2c_pins: hdmi_i2c { - mux { - groups = "hdmi_sda", "hdmi_scl"; - function = "hdmi_i2c"; - bias-disable; - }; - }; - - i2sout_ch23_y_pins: i2sout_ch23_y { - mux { - groups = "i2sout_ch23_y"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2sout_ch45_y_pins: i2sout_ch45_y { - mux { - groups = "i2sout_ch45_y"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2sout_ch67_y_pins: i2sout_ch67_y { - mux { - groups = "i2sout_ch67_y"; - function = "i2s_out"; - bias-disable; - }; - }; - - spdif_out_y_pins: spdif_out_y { - mux { - groups = "spdif_out_y"; - function = "spdif_out"; - bias-disable; - }; - }; - }; -}; - -&pwrc { - resets = <&reset RESET_VIU>, - <&reset RESET_VENC>, - <&reset RESET_VCBUS>, - <&reset RESET_BT656>, - <&reset RESET_DVIN_RESET>, - <&reset RESET_RDMA>, - <&reset RESET_VENCI>, - <&reset RESET_VENCP>, - <&reset RESET_VDAC>, - <&reset RESET_VDI6>, - <&reset RESET_VENCL>, - <&reset RESET_VID_LOCK>; - reset-names = "viu", "venc", "vcbus", "bt656", - "dvin", "rdma", "venci", "vencp", - "vdac", "vdi6", "vencl", "vid_lock"; - clocks = <&clkc CLKID_VPU>, - <&clkc CLKID_VAPB>; - clock-names = "vpu", "vapb"; - /* - * VPU clocking is provided by two identical clock paths - * VPU_0 and VPU_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - * Same for VAPB but with a final gate after the glitch free mux. - */ - assigned-clocks = <&clkc CLKID_VPU_0_SEL>, - <&clkc CLKID_VPU_0>, - <&clkc CLKID_VPU>, /* Glitch free mux */ - <&clkc CLKID_VAPB_0_SEL>, - <&clkc CLKID_VAPB_0>, - <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, - <0>, /* Do Nothing */ - <&clkc CLKID_VPU_0>, - <&clkc CLKID_FCLK_DIV4>, - <0>, /* Do Nothing */ - <&clkc CLKID_VAPB_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <666666666>, - <0>, /* Do Nothing */ - <0>, /* Do Nothing */ - <250000000>, - <0>; /* Do Nothing */ -}; - -&saradc { - compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc"; - clocks = <&xtal>, - <&clkc CLKID_SAR_ADC>, - <&clkc CLKID_SAR_ADC_CLK>, - <&clkc CLKID_SAR_ADC_SEL>; - clock-names = "clkin", "core", "adc_clk", "adc_sel"; -}; - -&sd_emmc_a { - clocks = <&clkc CLKID_SD_EMMC_A>, - <&clkc CLKID_SD_EMMC_A_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_A>; -}; - -&sd_emmc_b { - clocks = <&clkc CLKID_SD_EMMC_B>, - <&clkc CLKID_SD_EMMC_B_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_B>; -}; - -&sd_emmc_c { - clocks = <&clkc CLKID_SD_EMMC_C>, - <&clkc CLKID_SD_EMMC_C_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_C>; -}; - -&simplefb_hdmi { - clocks = <&clkc CLKID_HDMI_PCLK>, - <&clkc CLKID_CLK81>, - <&clkc CLKID_GCLK_VENCI_INT0>; -}; - -&spicc { - clocks = <&clkc CLKID_SPICC>; - clock-names = "core"; - resets = <&reset RESET_PERIPHS_SPICC>; - num-cs = <1>; -}; - -&spifc { - clocks = <&clkc CLKID_SPI>; -}; - -&uart_A { - clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_AO { - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_AO_B { - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_B { - clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_C { - clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&vpu { - compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu"; - power-domains = <&pwrc PWRC_GXBB_VPU_ID>; -}; - -&vdec { - compatible = "amlogic,gxbb-vdec", "amlogic,gx-vdec"; - clocks = <&clkc CLKID_DOS_PARSER>, - <&clkc CLKID_DOS>, - <&clkc CLKID_VDEC_1>, - <&clkc CLKID_VDEC_HEVC>; - clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc"; - resets = <&reset RESET_PARSER>; - reset-names = "esparser"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi deleted file mode 100644 index 478e755cc..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 BayLibre SAS - * Author: Neil Armstrong - */ - -#include "meson-gx-mali450.dtsi" - -&mali { - compatible = "amlogic,meson-gxl-mali", "arm,mali-450"; - - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; - clock-names = "bus", "core"; - - assigned-clocks = <&clkc CLKID_GP0_PLL>; - assigned-clock-rates = <744000000>; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts deleted file mode 100644 index 9e43f4dca..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts +++ /dev/null @@ -1,319 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 BayLibre, SAS. - * Author: Neil Armstrong - * Author: Jerome Brunet - */ - -/dts-v1/; - -#include -#include - -#include "meson-gxl-s805x.dtsi" - -/ { - compatible = "libretech,aml-s805x-ac", "amlogic,s805x", - "amlogic,meson-gxl"; - model = "Libre Computer AML-S805X-AC"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - spi0 = &spifc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cvbs-connector { - /* - * The pads are present but no connector is soldered on - * 2J2, so keep this off by default. - */ - status = "disabled"; - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - dc_5v: regulator-dc_5v { - compatible = "regulator-fixed"; - regulator-name = "DC_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x20000000>; - }; - - vcck: regulator-vcck { - compatible = "regulator-fixed"; - regulator-name = "VCCK"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_5v>; - - /* - * This is controlled by GPIOAO_9 we reserve this but - * claiming it as done below reset the board anyway - * Need to investigate this - * - * gpio = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; - * enable-active-high; - */ - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_5v>; - regulator-always-on; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "GXL-LIBRETECH-S805X-AC"; - audio-widgets = "Speaker", "9J5-3 LEFT", - "Speaker", "9J5-2 RIGHT"; - audio-routing = "9J5-3 LEFT", "ACODEC LOLN", - "9J5-2 RIGHT", "ACODEC LORN"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - - codec-1 { - sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; - }; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - - dai-link-3 { - sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; - - codec-0 { - sound-dai = <&acodec>; - }; - }; - }; -}; - -&acodec { - AVDD-supply = <&vddio_ao18>; - status = "okay"; -}; - -&aiu { - status = "okay"; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; -}; - -&internal_phy { - pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&gpio_ao { - gpio-line-names = "UART TX", - "UART RX", - "7J1 Header Pin31", - "", "", "", "", - "IR In", - "HDMI CEC", - "5V VCCK Regulator", - /* GPIO_TEST_N */ - ""; -}; - -&gpio { - gpio-line-names = /* Bank GPIOZ */ - "", "", "", "", "", "", "", - "", "", "", "", "", "", "", - "Eth Link LED", "Eth Activity LED", - /* Bank GPIOH */ - "HDMI HPD", "HDMI SDA", "HDMI SCL", - "", "7J1 Header Pin13", - "7J1 Header Pin15", - "7J1 Header Pin7", - "7J1 Header Pin12", - "7J1 Header Pin16", - "7J1 Header Pin18", - /* Bank BOOT */ - "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", - "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7", - "eMMC Clk", "eMMC Reset", "eMMC CMD", - "SPI NOR MOSI", "SPI NOR MISO", "SPI NOR Clk", - "", "SPI NOR Chip Select", - /* Bank CARD */ - "", "", "", "", "", "", "", - /* Bank GPIODV */ - "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", "", - "7J1 Header Pin27", "7J1 Header Pin28", "", - "7J1 Header Pin29", - "VCCK Regulator", "VDDEE Regulator", - /* Bank GPIOX */ - "7J1 Header Pin22", "7J1 Header Pin26", - "7J1 Header Pin36", "7J1 Header Pin38", - "7J1 Header Pin40", "7J1 Header Pin37", - "7J1 Header Pin33", "7J1 Header Pin35", - "7J1 Header Pin19", "7J1 Header Pin21", - "7J1 Header Pin24", "7J1 Header Pin23", - "7J1 Header Pin8", "7J1 Header Pin10", - "", "", "7J1 Header Pin32", "", "", - /* Bank GPIOCLK */ - "", ""; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&spifc { - status = "okay"; - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - - w25q32: spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <3000000>; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts deleted file mode 100644 index eb7f5a3fe..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts +++ /dev/null @@ -1,222 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 BayLibre, SAS. - * Author: Neil Armstrong - * Author: Jerome Brunet - */ - -/dts-v1/; - -#include - -#include "meson-gxl-s805x.dtsi" - -/ { - compatible = "amlogic,p241", "amlogic,s805x", "amlogic,meson-gxl"; - model = "Amlogic Meson GXL (S805X) P241 Development Board"; - - aliases { - serial0 = &uart_AO; - serial1 = &uart_A; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x20000000>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; -}; - -&internal_phy { - pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -/* This is connected to the Bluetooth module: */ -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi deleted file mode 100644 index 299758498..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x.dtsi +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 BayLibre SAS - * Author: Neil Armstrong - */ - -#include "meson-gxl-s905x.dtsi" - -/ { - compatible = "amlogic,s805x", "amlogic,meson-gxl"; -}; - -/* The S805X Package doesn't seem to handle the 744MHz OPP correctly */ -&gpu_opp_table { - opp-744000000 { - status = "disabled"; - }; -}; - -&mali { - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-rates; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-libretech-pc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-libretech-pc.dts deleted file mode 100644 index 100a1cfee..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-libretech-pc.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 BayLibre SAS. All rights reserved. - * Author: Jerome Brunet - */ - -/dts-v1/; - -#include "meson-gxl-s905d.dtsi" -#include "meson-gx-libretech-pc.dtsi" - -/ { - compatible = "libretech,aml-s905d-pc", "amlogic,s905d", - "amlogic,meson-gxl"; - model = "Libre Computer AML-S905D-PC"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts deleted file mode 100644 index b2ab05c22..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -/dts-v1/; - -#include - -#include "meson-gxl-s905d.dtsi" -#include "meson-gx-p23x-q20x.dtsi" - -/ { - compatible = "amlogic,p230", "amlogic,s905d", "amlogic,meson-gxl"; - model = "Amlogic Meson GXL (S905D) P230 Development Board"; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "Update"; - linux,code = ; - press-threshold-microvolt = <10000>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - button@0 { - label = "power"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -/* P230 has exclusive choice between internal or external PHY */ -ðmac { - pinctrl-0 = <ð_pins>; - pinctrl-names = "default"; - - /* Select external PHY by default */ - phy-handle = <&external_phy>; - - amlogic,tx-delay-ns = <2>; - - /* External PHY is in RGMII */ - phy-mode = "rgmii"; -}; - -&external_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - /* External PHY reset is shared with internal PHY Led signal */ - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - eee-broken-1000t; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&sd_emmc_a { - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts deleted file mode 100644 index 92c425d02..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -/dts-v1/; - -#include "meson-gxl-s905d.dtsi" -#include "meson-gx-p23x-q20x.dtsi" - -/ { - compatible = "amlogic,p231", "amlogic,s905d", "amlogic,meson-gxl"; - model = "Amlogic Meson GXL (S905D) P231 Development Board"; -}; - -/* P231 has only internal PHY port */ -ðmac { - phy-mode = "rmii"; - phy-handle = <&internal_phy>; -}; - -&sd_emmc_a { - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts deleted file mode 100644 index 9ef210f17..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 He Yangxuan - */ - -/dts-v1/; - -#include "meson-gxl-s905d-p230.dts" - -/ { - compatible = "phicomm,n1", "amlogic,s905d", "amlogic,meson-gxl"; - model = "Phicomm N1"; - - cvbs-connector { - status = "disabled"; - }; - - leds { - compatible = "gpio-leds"; - - status { - label = "n1:white:status"; - gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; -}; - -&cvbs_vdac_port { - status = "disabled"; -}; - -&usb { - dr_mode = "host"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts deleted file mode 100644 index 0b95e9ecb..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) Christian Hewitt - */ - -/dts-v1/; - -#include "meson-gxl-s905d.dtsi" -#include "meson-gx-p23x-q20x.dtsi" -#include - -/ { - compatible = "smartlabs,sml5442tw", "amlogic,s905d", "amlogic,meson-gxl"; - model = "SmartLabs SML-5442TW"; - - leds { - compatible = "gpio-leds"; - - yellow { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_ao GPIOAO_6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - blue { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio GPIODV_28 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - green { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - red { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio GPIODV_27 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; -}; - -ðmac { - status = "okay"; - phy-mode = "rmii"; - phy-handle = <&internal_phy>; -}; - -&i2c_A { - status = "okay"; - pinctrl-0 = <&i2c_a_pins>; - pinctrl-names = "default"; -}; - -&internal_phy { - pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; - pinctrl-names = "default"; -}; - -/* This is connected to the Bluetooth module: */ -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "qcom,qca9377-bt"; - enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi deleted file mode 100644 index 433219195..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -#include "meson-gxl.dtsi" -#include "meson-gxl-mali.dtsi" - -/ { - compatible = "amlogic,s905d", "amlogic,meson-gxl"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts deleted file mode 100644 index ecc9df7ca..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Martin Blumenstingl . - * Based on meson-gxl-s905d-p231.dts: - * - Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -/dts-v1/; - -#include "meson-gxl-s905x.dtsi" -#include "meson-gx-p23x-q20x.dtsi" - -/ { - compatible = "amlogic,p281", "amlogic,s905w", "amlogic,meson-gxl"; - model = "Amlogic Meson GXL (S905W) P281 Development Board"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; -}; - -&usb { - dr_mode = "host"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts deleted file mode 100644 index 6705c2082..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Martin Blumenstingl . - * Based on meson-gxl-s905d-p231.dts: - * - Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -/dts-v1/; - -#include "meson-gxl-s905x.dtsi" -#include "meson-gx-p23x-q20x.dtsi" - -/ { - compatible = "oranth,tx3-mini", "amlogic,s905w", "amlogic,meson-gxl"; - model = "Oranth Tanix TX3 Mini"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; /* 1 GiB or 2 GiB */ - }; -}; - -&ir { - linux,rc-map-name = "rc-tanix-tx3mini"; -}; - -&usb { - dr_mode = "host"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts deleted file mode 100644 index c8d74e61d..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts +++ /dev/null @@ -1,164 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Carlo Caione - * Copyright (c) 2016 BayLibre, Inc. - * Author: Neil Armstrong - */ - -/dts-v1/; - -#include "meson-gxl-s905x.dtsi" - -/ { - compatible = "hwacom,amazetv", "amlogic,s905x", "amlogic,meson-gxl"; - model = "Hwacom AmazeTV (S905X)"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - vddio_card: gpio-regulator { - compatible = "regulator-gpio"; - - regulator-name = "VDDIO_CARD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - - /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ - states = <1800000 0>, - <3300000 1>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; - phy-mode = "rmii"; - phy-handle = <&internal_phy>; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_card>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <100000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts deleted file mode 100644 index 8bcdffdf5..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +++ /dev/null @@ -1,213 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Martin Blumenstingl . - */ - -/dts-v1/; - -#include - -#include "meson-gxl-s905x-p212.dtsi" - -/ { - compatible = "khadas,vim", "amlogic,s905x", "amlogic,meson-gxl"; - model = "Khadas VIM"; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "Function"; - linux,code = ; - press-threshold-microvolt = <10000>; - }; - }; - - aliases { - serial2 = &uart_AO_B; - ethernet0 = ðmac; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - power-button { - label = "power"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - - power { - label = "vim:red:power"; - pwms = <&pwm_AO_ab 1 7812500 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c_A { - status = "okay"; - pinctrl-0 = <&i2c_a_pins>; - pinctrl-names = "default"; -}; - -&i2c_B { - status = "okay"; - pinctrl-0 = <&i2c_b_pins>; - pinctrl-names = "default"; - - rtc: rtc@51 { - /* has to be enabled manually when a battery is connected: */ - status = "disabled"; - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - }; -}; - -&ir { - linux,rc-map-name = "rc-khadas"; -}; - -&gpio_ao { - gpio-line-names = "UART TX", - "UART RX", - "Power Key In", - "J9 Header Pin35", - "J9 Header Pin16", - "J9 Header Pin15", - "J9 Header Pin33", - "IR In", - "HDMI CEC", - "SYS LED", - /* GPIO_TEST_N */ - ""; -}; - -&gpio { - gpio-line-names = /* Bank GPIOZ */ - "", "", "", "", "", "", "", - "", "", "", "", "", "", "", - "Power OFF", - "VCCK Enable", - /* Bank GPIOH */ - "HDMI HPD", "HDMI SDA", "HDMI SCL", - "HDMI_5V_EN", "SPDIF", - "J9 Header Pin37", - "J9 Header Pin30", - "J9 Header Pin29", - "J9 Header Pin32", - "J9 Header Pin31", - /* Bank BOOT */ - "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", - "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7", - "eMMC Clk", "eMMC Reset", "eMMC CMD", - "", "BOOT_MODE", "", "", "eMMC Data Strobe", - /* Bank CARD */ - "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", - "SDCard D3", "SDCard D2", "SDCard Det", - /* Bank GPIODV */ - "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", "", - "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK", - "VCCK Regulator", "VDDEE Regulator", - /* Bank GPIOX */ - "WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2", - "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD", - "WIFI Power Enable", "WIFI WAKE HOST", - "Bluetooth PCM DOUT", "Bluetooth PCM DIN", - "Bluetooth PCM SYNC", "Bluetooth PCM CLK", - "Bluetooth UART TX", "Bluetooth UART RX", - "Bluetooth UART CTS", "Bluetooth UART RTS", - "WIFI 32K", "Bluetooth Enable", - "Bluetooth WAKE HOST", - /* Bank GPIOCLK */ - "", "J9 Header Pin39"; -}; - -&pwm_AO_ab { - status = "okay"; - pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; - pinctrl-names = "default"; - clocks = <&xtal> , <&xtal>; - clock-names = "clkin0", "clkin1" ; -}; - -&pwm_ef { - pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; -}; - -&sd_emmc_a { - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -&uart_A { - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */ -&uart_AO { - status = "okay"; -}; - -/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */ -&uart_AO_B { - status = "okay"; - pinctrl-0 = <&uart_ao_b_pins>; - pinctrl-names = "default"; -}; - -&usb { - dr_mode = "peripheral"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts deleted file mode 100644 index 675eaa879..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts +++ /dev/null @@ -1,318 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 BayLibre, SAS. - * Author: Jerome Brunet - */ - -/dts-v1/; - -#include -#include -#include - -#include "meson-gxl-s905x.dtsi" - -/ { - compatible = "libretech,aml-s905x-cc-v2", "amlogic,s905x", - "amlogic,meson-gxl"; - model = "Libre Computer AML-S905X-CC V2"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - spi0 = &spifc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-blue { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - panic-indicator; - }; - - led-green { - color = ; - function = LED_FUNCTION_DISK_ACTIVITY; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ao_5v: regulator-ao_5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - - vcck: regulator-vcck { - compatible = "regulator-fixed"; - regulator-name = "VCCK"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&ao_5v>; - regulator-always-on; - }; - - vcc_card: regulator-vcc_card { - compatible = "regulator-fixed"; - regulator-name = "VCC_CARD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddio_ao3v3>; - - gpio = <&gpio GPIOCLK_1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc5v: regulator-vcc5v { - compatible = "regulator-fixed"; - regulator-name = "VCC5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&ao_5v>; - - gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>; - }; - - vddio_ao3v3: regulator-vddio_ao3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&ao_5v>; - regulator-always-on; - }; - - - vddio_card: regulator-vddio-card { - compatible = "regulator-gpio"; - regulator-name = "VDDIO_CARD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - - regulator-settling-time-up-us = <200>; - regulator-settling-time-down-us = <50000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddio_ao3v3>; - regulator-always-on; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC 1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddio_ao3v3>; - regulator-always-on; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "GXL-LIBRETECH-S905X-CC-V2"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - - -&aiu { - status = "okay"; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - - -ðmac { - status = "okay"; -}; - -&internal_phy { - pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - hdmi-supply = <&vcc5v>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* SD card */ -&sd_emmc_b { - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - max-frequency = <100000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vcc_card>; - vqmmc-supply = <&vddio_card>; - - status = "okay"; -}; - -/* eMMC */ -&sd_emmc_c { - pinctrl-0 = <&emmc_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vddio_ao3v3>; - vqmmc-supply = <&vcc_1v8>; - - status = "okay"; -}; - -&spifc { - status = "okay"; - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - - nor_4u1: spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <3000000>; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; - -&usb2_phy0 { - pinctrl-names = "default"; - phy-supply = <&vcc5v>; -}; - -&usb2_phy1 { - phy-supply = <&vcc5v>; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts deleted file mode 100644 index 5ae7bb620..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts +++ /dev/null @@ -1,356 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 BayLibre, SAS. - * Author: Neil Armstrong - * Author: Jerome Brunet - */ - -/dts-v1/; - -#include -#include - -#include "meson-gxl-s905x.dtsi" - -/ { - compatible = "libretech,aml-s905x-cc", "amlogic,s905x", - "amlogic,meson-gxl"; - model = "Libre Computer AML-S905X-CC"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - dio2133: analog-amplifier { - compatible = "simple-audio-amplifier"; - sound-name-prefix = "AU2"; - VCC-supply = <&hdmi_5v>; - enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-system { - label = "librecomputer:system-status"; - gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; - default-state = "on"; - panic-indicator; - }; - - led-blue { - label = "librecomputer:blue"; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - hdmi_5v: regulator-hdmi-5v { - compatible = "regulator-fixed"; - - regulator-name = "HDMI_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_card: regulator-vcc-card { - compatible = "regulator-gpio"; - - regulator-name = "VCC_CARD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - - regulator-settling-time-up-us = <200>; - regulator-settling-time-down-us = <50000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - /* This is provided by LDOs on the eMMC daugther card */ - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - }; - - sound { - compatible = "amlogic,gx-sound-card"; - model = "GXL-LIBRETECH-S905X-CC"; - audio-aux-devs = <&dio2133>; - audio-widgets = "Line", "Lineout"; - audio-routing = "AU2 INL", "ACODEC LOLN", - "AU2 INR", "ACODEC LORN", - "Lineout", "AU2 OUTL", - "Lineout", "AU2 OUTR"; - assigned-clocks = <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; - }; - - dai-link-1 { - sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; - dai-format = "i2s"; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&aiu AIU_HDMI CTRL_I2S>; - }; - - codec-1 { - sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; - }; - }; - - dai-link-2 { - sound-dai = <&aiu AIU_HDMI CTRL_OUT>; - - codec-0 { - sound-dai = <&hdmi_tx>; - }; - }; - - dai-link-3 { - sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; - - codec-0 { - sound-dai = <&acodec>; - }; - }; - }; -}; - -&acodec { - AVDD-supply = <&vddio_ao18>; - status = "okay"; -}; - -&aiu { - status = "okay"; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; -}; - -&internal_phy { - pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&gpio_ao { - gpio-line-names = "UART TX", - "UART RX", - "Blue LED", - "SDCard Voltage Switch", - "7J1 Header Pin5", - "7J1 Header Pin3", - "7J1 Header Pin12", - "IR In", - "9J3 Switch HDMI CEC/7J1 Header Pin11", - "7J1 Header Pin13", - /* GPIO_TEST_N */ - "7J1 Header Pin15"; -}; - -&gpio { - gpio-line-names = /* Bank GPIOZ */ - "", "", "", "", "", "", "", - "", "", "", "", "", "", "", - "Eth Link LED", "Eth Activity LED", - /* Bank GPIOH */ - "HDMI HPD", "HDMI SDA", "HDMI SCL", - "HDMI_5V_EN", "9J1 Header Pin2", - "Analog Audio Mute", - "2J3 Header Pin6", - "2J3 Header Pin5", - "2J3 Header Pin4", - "2J3 Header Pin3", - /* Bank BOOT */ - "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", - "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7", - "eMMC Clk", "eMMC Reset", "eMMC CMD", - "ALT BOOT MODE", "", "", "", "eMMC Data Strobe", - /* Bank CARD */ - "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD", - "SDCard D3", "SDCard D2", "SDCard Det", - /* Bank GPIODV */ - "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", "", - "Green LED", "VCCK Enable", - "7J1 Header Pin27", "7J1 Header Pin28", - "VCCK Regulator", "VDDEE Regulator", - /* Bank GPIOX */ - "7J1 Header Pin22", "7J1 Header Pin26", - "7J1 Header Pin36", "7J1 Header Pin38", - "7J1 Header Pin40", "7J1 Header Pin37", - "7J1 Header Pin33", "7J1 Header Pin35", - "7J1 Header Pin19", "7J1 Header Pin21", - "7J1 Header Pin24", "7J1 Header Pin23", - "7J1 Header Pin8", "7J1 Header Pin10", - "7J1 Header Pin16", "7J1 Header Pin18", - "7J1 Header Pin32", "7J1 Header Pin29", - "7J1 Header Pin31", - /* Bank GPIOCLK */ - "7J1 Header Pin7", ""; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_card>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; - -&usb2_phy0 { - /* - * even though the schematics don't show it: - * HDMI_5V is also used as supply for the USB VBUS. - */ - phy-supply = <&hdmi_5v>; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts deleted file mode 100644 index f1acca5c4..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts +++ /dev/null @@ -1,224 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Andreas Färber - * Copyright (c) 2016 BayLibre, Inc. - * Author: Neil Armstrong - */ - -/dts-v1/; - -#include "meson-gxl-s905x.dtsi" - -/ { - compatible = "nexbox,a95x", "amlogic,s905x", "amlogic,meson-gxl"; - model = "NEXBOX A95X (S905X)"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - vddio_card: gpio-regulator { - compatible = "regulator-gpio"; - - regulator-name = "VDDIO_CARD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - - /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ - states = <1800000 0>, - <3300000 1>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; - phy-mode = "rmii"; - phy-handle = <&internal_phy>; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_card>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts deleted file mode 100644 index 2602940c2..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -/dts-v1/; - -#include "meson-gxl-s905x-p212.dtsi" - -/ { - compatible = "amlogic,p212", "amlogic,s905x", "amlogic,meson-gxl"; - model = "Amlogic Meson GXL (S905X) P212 Development Board"; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -/* This UART is brought out to the DB9 connector */ -&uart_AO { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi deleted file mode 100644 index 05cb2f5e5..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi +++ /dev/null @@ -1,208 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Martin Blumenstingl . - * Based on meson-gx-p23x-q20x.dtsi: - * - Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - * - Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong - */ - -/* Common DTSI for devices which are based on the P212 reference board. */ - -#include "meson-gxl-s905x.dtsi" - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - hdmi_5v: regulator-hdmi-5v { - compatible = "regulator-fixed"; - - regulator-name = "HDMI_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; -}; - -ðmac { - status = "okay"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -/* This is connected to the Bluetooth module: */ -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; - -&usb2_phy0 { - /* - * HDMI_5V is also used as supply for the USB VBUS. - */ - phy-supply = <&hdmi_5v>; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi deleted file mode 100644 index 40c19f69e..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -#include "meson-gxl.dtsi" -#include "meson-gxl-mali.dtsi" - -/ { - compatible = "amlogic,s905x", "amlogic,meson-gxl"; -}; - -/* S905X only has access to its internal PHY */ -ðmac { - phy-mode = "rmii"; - phy-handle = <&internal_phy>; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi deleted file mode 100644 index c3ac531c4..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ /dev/null @@ -1,925 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -#include "meson-gx.dtsi" -#include -#include -#include -#include - -/ { - compatible = "amlogic,meson-gxl"; - - soc { - usb: usb@d0078080 { - compatible = "amlogic,meson-gxl-usb-ctrl"; - reg = <0x0 0xd0078080 0x0 0x20>; - interrupts = ; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>; - clock-names = "usb_ctrl", "ddr"; - resets = <&reset RESET_USB_OTG>; - - dr_mode = "otg"; - - phys = <&usb2_phy0>, <&usb2_phy1>; - phy-names = "usb2-phy0", "usb2-phy1"; - - dwc2: usb@c9100000 { - compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; - reg = <0x0 0xc9100000 0x0 0x40000>; - interrupts = ; - clocks = <&clkc CLKID_USB1>; - clock-names = "otg"; - phys = <&usb2_phy1>; - dr_mode = "peripheral"; - g-rx-fifo-size = <192>; - g-np-tx-fifo-size = <128>; - g-tx-fifo-size = <128 128 16 16 16>; - }; - - dwc3: usb@c9000000 { - compatible = "snps,dwc3"; - reg = <0x0 0xc9000000 0x0 0x100000>; - interrupts = ; - dr_mode = "host"; - maximum-speed = "high-speed"; - snps,dis_u2_susphy_quirk; - }; - }; - - acodec: audio-controller@c8832000 { - compatible = "amlogic,t9015"; - reg = <0x0 0xc8832000 0x0 0x14>; - #sound-dai-cells = <0>; - sound-name-prefix = "ACODEC"; - clocks = <&clkc CLKID_ACODEC>; - clock-names = "pclk"; - resets = <&reset RESET_ACODEC>; - status = "disabled"; - }; - - crypto: crypto@c883e000 { - compatible = "amlogic,gxl-crypto"; - reg = <0x0 0xc883e000 0x0 0x36>; - interrupts = , - ; - clocks = <&clkc CLKID_BLKMV>; - clock-names = "blkmv"; - status = "okay"; - }; - }; -}; - -&aiu { - compatible = "amlogic,aiu-gxl", "amlogic,aiu"; - clocks = <&clkc CLKID_AIU_GLUE>, - <&clkc CLKID_I2S_OUT>, - <&clkc CLKID_AOCLK_GATE>, - <&clkc CLKID_CTS_AMCLK>, - <&clkc CLKID_MIXER_IFACE>, - <&clkc CLKID_IEC958>, - <&clkc CLKID_IEC958_GATE>, - <&clkc CLKID_CTS_MCLK_I958>, - <&clkc CLKID_CTS_I958>; - clock-names = "pclk", - "i2s_pclk", - "i2s_aoclk", - "i2s_mclk", - "i2s_mixer", - "spdif_pclk", - "spdif_aoclk", - "spdif_mclk", - "spdif_mclk_sel"; - resets = <&reset RESET_AIU>; -}; - -&apb { - usb2_phy0: phy@78000 { - compatible = "amlogic,meson-gxl-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0x78000 0x0 0x20>; - clocks = <&clkc CLKID_USB>; - clock-names = "phy"; - resets = <&reset RESET_USB_OTG>; - reset-names = "phy"; - status = "okay"; - }; - - usb2_phy1: phy@78020 { - compatible = "amlogic,meson-gxl-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0x78020 0x0 0x20>; - clocks = <&clkc CLKID_USB>; - clock-names = "phy"; - resets = <&reset RESET_USB_OTG>; - reset-names = "phy"; - status = "okay"; - }; -}; - -&efuse { - clocks = <&clkc CLKID_EFUSE>; -}; - -ðmac { - clocks = <&clkc CLKID_ETH>, - <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; - - mdio0: mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - }; -}; - -&aobus { - pinctrl_aobus: pinctrl@14 { - compatible = "amlogic,meson-gxl-aobus-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio_ao: bank@14 { - reg = <0x0 0x00014 0x0 0x8>, - <0x0 0x0002c 0x0 0x4>, - <0x0 0x00024 0x0 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 0 14>; - }; - - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_tx_ao_a", "uart_rx_ao_a"; - function = "uart_ao"; - bias-disable; - }; - }; - - uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { - mux { - groups = "uart_cts_ao_a", - "uart_rts_ao_a"; - function = "uart_ao"; - bias-disable; - }; - }; - - uart_ao_b_pins: uart_ao_b { - mux { - groups = "uart_tx_ao_b", "uart_rx_ao_b"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - uart_ao_b_0_1_pins: uart_ao_b_0_1 { - mux { - groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { - mux { - groups = "uart_cts_ao_b", - "uart_rts_ao_b"; - function = "uart_ao_b"; - bias-disable; - }; - }; - - remote_input_ao_pins: remote_input_ao { - mux { - groups = "remote_input_ao"; - function = "remote_input_ao"; - bias-disable; - }; - }; - - i2c_ao_pins: i2c_ao { - mux { - groups = "i2c_sck_ao", - "i2c_sda_ao"; - function = "i2c_ao"; - bias-disable; - }; - }; - - pwm_ao_a_3_pins: pwm_ao_a_3 { - mux { - groups = "pwm_ao_a_3"; - function = "pwm_ao_a"; - bias-disable; - }; - }; - - pwm_ao_a_8_pins: pwm_ao_a_8 { - mux { - groups = "pwm_ao_a_8"; - function = "pwm_ao_a"; - bias-disable; - }; - }; - - pwm_ao_b_pins: pwm_ao_b { - mux { - groups = "pwm_ao_b"; - function = "pwm_ao_b"; - bias-disable; - }; - }; - - pwm_ao_b_6_pins: pwm_ao_b_6 { - mux { - groups = "pwm_ao_b_6"; - function = "pwm_ao_b"; - bias-disable; - }; - }; - - i2s_out_ch23_ao_pins: i2s_out_ch23_ao { - mux { - groups = "i2s_out_ch23_ao"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - i2s_out_ch45_ao_pins: i2s_out_ch45_ao { - mux { - groups = "i2s_out_ch45_ao"; - function = "i2s_out_ao"; - bias-disable; - }; - }; - - spdif_out_ao_6_pins: spdif_out_ao_6 { - mux { - groups = "spdif_out_ao_6"; - function = "spdif_out_ao"; - bias-disable; - }; - }; - - spdif_out_ao_9_pins: spdif_out_ao_9 { - mux { - groups = "spdif_out_ao_9"; - function = "spdif_out_ao"; - bias-disable; - }; - }; - - ao_cec_pins: ao_cec { - mux { - groups = "ao_cec"; - function = "cec_ao"; - bias-disable; - }; - }; - - ee_cec_pins: ee_cec { - mux { - groups = "ee_cec"; - function = "cec_ao"; - bias-disable; - }; - }; - }; -}; - -&cec_AO { - clocks = <&clkc_AO CLKID_AO_CEC_32K>; - clock-names = "core"; -}; - -&clkc_AO { - compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc"; - clocks = <&xtal>, <&clkc CLKID_CLK81>; - clock-names = "xtal", "mpeg-clk"; -}; - -&gpio_intc { - compatible = "amlogic,meson-gpio-intc", - "amlogic,meson-gxl-gpio-intc"; - status = "okay"; -}; - -&hdmi_tx { - compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; - resets = <&reset RESET_HDMITX_CAPB3>, - <&reset RESET_HDMI_SYSTEM_RESET>, - <&reset RESET_HDMI_TX>; - reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; - clocks = <&clkc CLKID_HDMI_PCLK>, - <&clkc CLKID_CLK81>, - <&clkc CLKID_GCLK_VENCI_INT0>; - clock-names = "isfr", "iahb", "venci"; -}; - -&sysctrl { - clkc: clock-controller { - compatible = "amlogic,gxl-clkc"; - #clock-cells = <1>; - clocks = <&xtal>; - clock-names = "xtal"; - }; -}; - -&hwrng { - clocks = <&clkc CLKID_RNG0>; - clock-names = "core"; -}; - -&i2c_A { - clocks = <&clkc CLKID_I2C>; -}; - -&i2c_AO { - clocks = <&clkc CLKID_AO_I2C>; -}; - -&i2c_B { - clocks = <&clkc CLKID_I2C>; -}; - -&i2c_C { - clocks = <&clkc CLKID_I2C>; -}; - -&periphs { - pinctrl_periphs: pinctrl@4b0 { - compatible = "amlogic,meson-gxl-periphs-pinctrl"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio: bank@4b0 { - reg = <0x0 0x004b0 0x0 0x28>, - <0x0 0x004e8 0x0 0x14>, - <0x0 0x00520 0x0 0x14>, - <0x0 0x00430 0x0 0x40>; - reg-names = "mux", "pull", "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_periphs 0 0 100>; - }; - - emmc_pins: emmc { - mux-0 { - groups = "emmc_nand_d07", - "emmc_cmd"; - function = "emmc"; - bias-pull-up; - }; - - mux-1 { - groups = "emmc_clk"; - function = "emmc"; - bias-disable; - }; - }; - - emmc_ds_pins: emmc-ds { - mux { - groups = "emmc_ds"; - function = "emmc"; - bias-pull-down; - }; - }; - - emmc_clk_gate_pins: emmc_clk_gate { - mux { - groups = "BOOT_8"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - nor_pins: nor { - mux { - groups = "nor_d", - "nor_q", - "nor_c", - "nor_cs"; - function = "nor"; - bias-disable; - }; - }; - - spi_pins: spi-pins { - mux { - groups = "spi_miso", - "spi_mosi", - "spi_sclk"; - function = "spi"; - bias-disable; - }; - }; - - spi_ss0_pins: spi-ss0 { - mux { - groups = "spi_ss0"; - function = "spi"; - bias-disable; - }; - }; - - sdcard_pins: sdcard { - mux-0 { - groups = "sdcard_d0", - "sdcard_d1", - "sdcard_d2", - "sdcard_d3", - "sdcard_cmd"; - function = "sdcard"; - bias-pull-up; - }; - - mux-1 { - groups = "sdcard_clk"; - function = "sdcard"; - bias-disable; - }; - }; - - sdcard_clk_gate_pins: sdcard_clk_gate { - mux { - groups = "CARD_2"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - sdio_pins: sdio { - mux-0 { - groups = "sdio_d0", - "sdio_d1", - "sdio_d2", - "sdio_d3", - "sdio_cmd"; - function = "sdio"; - bias-pull-up; - }; - - mux-1 { - groups = "sdio_clk"; - function = "sdio"; - bias-disable; - }; - }; - - sdio_clk_gate_pins: sdio_clk_gate { - mux { - groups = "GPIOX_4"; - function = "gpio_periphs"; - bias-pull-down; - }; - }; - - sdio_irq_pins: sdio_irq { - mux { - groups = "sdio_irq"; - function = "sdio"; - bias-disable; - }; - }; - - uart_a_pins: uart_a { - mux { - groups = "uart_tx_a", - "uart_rx_a"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_a_cts_rts_pins: uart_a_cts_rts { - mux { - groups = "uart_cts_a", - "uart_rts_a"; - function = "uart_a"; - bias-disable; - }; - }; - - uart_b_pins: uart_b { - mux { - groups = "uart_tx_b", - "uart_rx_b"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_b_cts_rts_pins: uart_b_cts_rts { - mux { - groups = "uart_cts_b", - "uart_rts_b"; - function = "uart_b"; - bias-disable; - }; - }; - - uart_c_pins: uart_c { - mux { - groups = "uart_tx_c", - "uart_rx_c"; - function = "uart_c"; - bias-disable; - }; - }; - - uart_c_cts_rts_pins: uart_c_cts_rts { - mux { - groups = "uart_cts_c", - "uart_rts_c"; - function = "uart_c"; - bias-disable; - }; - }; - - i2c_a_pins: i2c_a { - mux { - groups = "i2c_sck_a", - "i2c_sda_a"; - function = "i2c_a"; - bias-disable; - }; - }; - - i2c_b_pins: i2c_b { - mux { - groups = "i2c_sck_b", - "i2c_sda_b"; - function = "i2c_b"; - bias-disable; - }; - }; - - i2c_c_pins: i2c_c { - mux { - groups = "i2c_sck_c", - "i2c_sda_c"; - function = "i2c_c"; - bias-disable; - }; - }; - - i2c_c_dv18_pins: i2c_c_dv18 { - mux { - groups = "i2c_sck_c_dv19", - "i2c_sda_c_dv18"; - function = "i2c_c"; - bias-disable; - }; - }; - - eth_pins: eth_c { - mux { - groups = "eth_mdio", - "eth_mdc", - "eth_clk_rx_clk", - "eth_rx_dv", - "eth_rxd0", - "eth_rxd1", - "eth_rxd2", - "eth_rxd3", - "eth_rgmii_tx_clk", - "eth_tx_en", - "eth_txd0", - "eth_txd1", - "eth_txd2", - "eth_txd3"; - function = "eth"; - bias-disable; - }; - }; - - eth_link_led_pins: eth_link_led { - mux { - groups = "eth_link_led"; - function = "eth_led"; - bias-disable; - }; - }; - - eth_act_led_pins: eth_act_led { - mux { - groups = "eth_act_led"; - function = "eth_led"; - }; - }; - - pwm_a_pins: pwm_a { - mux { - groups = "pwm_a"; - function = "pwm_a"; - bias-disable; - }; - }; - - pwm_b_pins: pwm_b { - mux { - groups = "pwm_b"; - function = "pwm_b"; - bias-disable; - }; - }; - - pwm_c_pins: pwm_c { - mux { - groups = "pwm_c"; - function = "pwm_c"; - bias-disable; - }; - }; - - pwm_d_pins: pwm_d { - mux { - groups = "pwm_d"; - function = "pwm_d"; - bias-disable; - }; - }; - - pwm_e_pins: pwm_e { - mux { - groups = "pwm_e"; - function = "pwm_e"; - bias-disable; - }; - }; - - pwm_f_clk_pins: pwm_f_clk { - mux { - groups = "pwm_f_clk"; - function = "pwm_f"; - bias-disable; - }; - }; - - pwm_f_x_pins: pwm_f_x { - mux { - groups = "pwm_f_x"; - function = "pwm_f"; - bias-disable; - }; - }; - - hdmi_hpd_pins: hdmi_hpd { - mux { - groups = "hdmi_hpd"; - function = "hdmi_hpd"; - bias-disable; - }; - }; - - hdmi_i2c_pins: hdmi_i2c { - mux { - groups = "hdmi_sda", "hdmi_scl"; - function = "hdmi_i2c"; - bias-disable; - }; - }; - - i2s_am_clk_pins: i2s_am_clk { - mux { - groups = "i2s_am_clk"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2s_out_ao_clk_pins: i2s_out_ao_clk { - mux { - groups = "i2s_out_ao_clk"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2s_out_lr_clk_pins: i2s_out_lr_clk { - mux { - groups = "i2s_out_lr_clk"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2s_out_ch01_pins: i2s_out_ch01 { - mux { - groups = "i2s_out_ch01"; - function = "i2s_out"; - bias-disable; - }; - }; - i2sout_ch23_z_pins: i2sout_ch23_z { - mux { - groups = "i2sout_ch23_z"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2sout_ch45_z_pins: i2sout_ch45_z { - mux { - groups = "i2sout_ch45_z"; - function = "i2s_out"; - bias-disable; - }; - }; - - i2sout_ch67_z_pins: i2sout_ch67_z { - mux { - groups = "i2sout_ch67_z"; - function = "i2s_out"; - bias-disable; - }; - }; - - spdif_out_h_pins: spdif_out_ao_h { - mux { - groups = "spdif_out_h"; - function = "spdif_out"; - bias-disable; - }; - }; - }; - - eth-phy-mux { - compatible = "mdio-mux-mmioreg", "mdio-mux"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x55c 0x0 0x4>; - mux-mask = <0xffffffff>; - mdio-parent-bus = <&mdio0>; - - internal_mdio: mdio@e40908ff { - reg = <0xe40908ff>; - #address-cells = <1>; - #size-cells = <0>; - - internal_phy: ethernet-phy@8 { - compatible = "ethernet-phy-id0181.4400"; - interrupts = ; - reg = <8>; - max-speed = <100>; - }; - }; - - external_mdio: mdio@2009087f { - reg = <0x2009087f>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -&pwrc { - resets = <&reset RESET_VIU>, - <&reset RESET_VENC>, - <&reset RESET_VCBUS>, - <&reset RESET_BT656>, - <&reset RESET_DVIN_RESET>, - <&reset RESET_RDMA>, - <&reset RESET_VENCI>, - <&reset RESET_VENCP>, - <&reset RESET_VDAC>, - <&reset RESET_VDI6>, - <&reset RESET_VENCL>, - <&reset RESET_VID_LOCK>; - reset-names = "viu", "venc", "vcbus", "bt656", - "dvin", "rdma", "venci", "vencp", - "vdac", "vdi6", "vencl", "vid_lock"; - clocks = <&clkc CLKID_VPU>, - <&clkc CLKID_VAPB>; - clock-names = "vpu", "vapb"; - /* - * VPU clocking is provided by two identical clock paths - * VPU_0 and VPU_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - * Same for VAPB but with a final gate after the glitch free mux. - */ - assigned-clocks = <&clkc CLKID_VPU_0_SEL>, - <&clkc CLKID_VPU_0>, - <&clkc CLKID_VPU>, /* Glitch free mux */ - <&clkc CLKID_VAPB_0_SEL>, - <&clkc CLKID_VAPB_0>, - <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, - <0>, /* Do Nothing */ - <&clkc CLKID_VPU_0>, - <&clkc CLKID_FCLK_DIV4>, - <0>, /* Do Nothing */ - <&clkc CLKID_VAPB_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <666666666>, - <0>, /* Do Nothing */ - <0>, /* Do Nothing */ - <250000000>, - <0>; /* Do Nothing */ -}; - -&saradc { - compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc"; - clocks = <&xtal>, - <&clkc CLKID_SAR_ADC>, - <&clkc CLKID_SAR_ADC_CLK>, - <&clkc CLKID_SAR_ADC_SEL>; - clock-names = "clkin", "core", "adc_clk", "adc_sel"; -}; - -&sd_emmc_a { - clocks = <&clkc CLKID_SD_EMMC_A>, - <&clkc CLKID_SD_EMMC_A_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_A>; -}; - -&sd_emmc_b { - clocks = <&clkc CLKID_SD_EMMC_B>, - <&clkc CLKID_SD_EMMC_B_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_B>; -}; - -&sd_emmc_c { - clocks = <&clkc CLKID_SD_EMMC_C>, - <&clkc CLKID_SD_EMMC_C_CLK0>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - resets = <&reset RESET_SD_EMMC_C>; -}; - -&simplefb_hdmi { - clocks = <&clkc CLKID_HDMI_PCLK>, - <&clkc CLKID_CLK81>, - <&clkc CLKID_GCLK_VENCI_INT0>; -}; - -&spicc { - clocks = <&clkc CLKID_SPICC>; - clock-names = "core"; - resets = <&reset RESET_PERIPHS_SPICC>; - num-cs = <1>; -}; - -&spifc { - clocks = <&clkc CLKID_SPI>; -}; - -&uart_A { - clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_AO { - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_AO_B { - clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_B { - clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&uart_C { - clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; -}; - -&vpu { - compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu"; - power-domains = <&pwrc PWRC_GXBB_VPU_ID>; -}; - -&vdec { - compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec"; - clocks = <&clkc CLKID_DOS_PARSER>, - <&clkc CLKID_DOS>, - <&clkc CLKID_VDEC_1>, - <&clkc CLKID_VDEC_HEVC>; - clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc"; - resets = <&reset RESET_PARSER>; - reset-names = "esparser"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts deleted file mode 100644 index 62d3e0429..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ /dev/null @@ -1,386 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Martin Blumenstingl . - * Copyright (c) 2017 BayLibre, SAS - * Author: Neil Armstrong - */ - -/dts-v1/; - -#include - -#include "meson-gxm.dtsi" - -/ { - compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm"; - model = "Khadas VIM2"; - - aliases { - serial0 = &uart_AO; - serial2 = &uart_AO_B; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "Function"; - linux,code = ; - press-threshold-microvolt = <10000>; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - gpio_fan: gpio-fan { - compatible = "gpio-fan"; - gpios = <&gpio GPIODV_14 GPIO_ACTIVE_HIGH - &gpio GPIODV_15 GPIO_ACTIVE_HIGH>; - /* Dummy RPM values since fan is optional */ - gpio-fan,speed-map = <0 0 - 1 1 - 2 2 - 3 3>; - #cooling-cells = <2>; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - power-button { - label = "power"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - - power { - label = "vim:red:power"; - pwms = <&pwm_AO_ab 1 7812500 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - hdmi_5v: regulator-hdmi-5v { - compatible = "regulator-fixed"; - - regulator-name = "HDMI_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vddio_ao18: regulator-vddio_ao18 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddio_boot: regulator-vddio_boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - - -&cpu_cooling_maps { - map0 { - cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>; - }; - - map1 { - cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>, - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>; - pinctrl-names = "default"; - - /* Select external PHY by default */ - phy-handle = <&external_phy>; - - amlogic,tx-delay-ns = <2>; - - /* External PHY is in RGMII */ - phy-mode = "rgmii"; - - status = "okay"; -}; - -&external_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_15 */ - interrupts = <25 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; - hdmi-supply = <&hdmi_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c_A { - status = "okay"; - pinctrl-0 = <&i2c_a_pins>; - pinctrl-names = "default"; -}; - -&i2c_B { - status = "okay"; - pinctrl-0 = <&i2c_b_pins>; - pinctrl-names = "default"; - - rtc: rtc@51 { - /* has to be enabled manually when a battery is connected: */ - status = "disabled"; - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - linux,rc-map-name = "rc-khadas"; -}; - -&pwm_AO_ab { - status = "okay"; - pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - max-frequency = <60000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* - * EMMC_DS pin is shared between SPI NOR CS and eMMC Data Strobe - * Remove emmc_ds_pins from sd_emmc_c pinctrl-0 then spifc can be enabled - */ -&spifc { - status = "disabled"; - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - - w25q32: spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q16", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - }; -}; - -/* This one is connected to the Bluetooth module */ -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */ -&uart_AO_B { - status = "okay"; - pinctrl-0 = <&uart_ao_b_pins>; - pinctrl-names = "default"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao18>; -}; - -&usb { - status = "okay"; - dr_mode = "peripheral"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts deleted file mode 100644 index dfa7a37a1..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts +++ /dev/null @@ -1,185 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong - * - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -/dts-v1/; - -#include "meson-gxm.dtsi" - -/ { - compatible = "nexbox,a1", "amlogic,s912", "amlogic,meson-gxm"; - model = "NEXBOX A1"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - vddio_boot: regulator-vddio-boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; -}; - -&cec_AO { - status = "okay"; - pinctrl-0 = <&ao_cec_pins>; - pinctrl-names = "default"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -ðmac { - status = "okay"; - - pinctrl-0 = <ð_pins>; - pinctrl-names = "default"; - - /* Select external PHY by default */ - phy-handle = <&external_phy>; - - amlogic,tx-delay-ns = <2>; - - /* External PHY is in RGMII */ - phy-mode = "rgmii"; -}; - -&external_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - }; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-1 = <&sdcard_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "host"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts deleted file mode 100644 index 8edbfe040..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -/dts-v1/; - -#include - -#include "meson-gxm.dtsi" -#include "meson-gx-p23x-q20x.dtsi" - -/ { - compatible = "amlogic,q200", "amlogic,s912", "amlogic,meson-gxm"; - model = "Amlogic Meson GXM (S912) Q200 Development Board"; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "Update"; - linux,code = ; - press-threshold-microvolt = <10000>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - button@0 { - label = "power"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - }; -}; - -/* Q200 has exclusive choice between internal or external PHY */ -ðmac { - pinctrl-0 = <ð_pins>; - pinctrl-names = "default"; - - /* Select external PHY by default */ - phy-handle = <&external_phy>; - - amlogic,tx-delay-ns = <2>; - - /* External PHY is in RGMII */ - phy-mode = "rgmii"; -}; - -&external_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - /* External PHY reset is shared with internal PHY Led signal */ - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_15 */ - interrupts = <25 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&sd_emmc_a { - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts deleted file mode 100644 index d02b80d77..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -/dts-v1/; - -#include "meson-gxm.dtsi" -#include "meson-gx-p23x-q20x.dtsi" - -/ { - compatible = "amlogic,q201", "amlogic,s912", "amlogic,meson-gxm"; - model = "Amlogic Meson GXM (S912) Q201 Development Board"; -}; - -/* Q201 has only internal PHY port */ -ðmac { - phy-mode = "rmii"; - phy-handle = <&internal_phy>; -}; - -&sd_emmc_a { - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts deleted file mode 100644 index dde7cfe12..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts +++ /dev/null @@ -1,205 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016-2017 Andreas Färber - * - * Based on nexbox-a1: - * - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong - * - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -/dts-v1/; - -#include "meson-gxm.dtsi" - -/ { - compatible = "kingnovel,r-box-pro", "amlogic,s912", "amlogic,meson-gxm"; - model = "R-Box Pro"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB or 3 GiB */ - }; - - leds { - compatible = "gpio-leds"; - - led-blue { - label = "rbox-pro:blue:on"; - gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - led-red { - label = "rbox-pro:red:standby"; - gpios = <&gpio GPIODV_28 GPIO_ACTIVE_HIGH>; - default-state = "off"; - retain-state-suspended; - panic-indicator; - }; - }; - - vddio_boot: regulator-vddio-boot { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_BOOT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; -}; - -ðmac { - status = "okay"; - - pinctrl-0 = <ð_pins>; - pinctrl-names = "default"; - - /* Select external PHY by default */ - phy-handle = <&external_phy>; - - amlogic,tx-delay-ns = <2>; - - /* External PHY is in RGMII */ - phy-mode = "rgmii"; -}; - -&external_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; -}; - -/* Wireless SDIO Module */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; - - brcmf: brcmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_pins>; - pinctrl-names = "default"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; - pinctrl-names = "default"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - non-removable; - disable-wp; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-s912-libretech-pc.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-s912-libretech-pc.dts deleted file mode 100644 index 444c24986..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-s912-libretech-pc.dts +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 BayLibre SAS. All rights reserved. - * Author: Jerome Brunet - */ - -/dts-v1/; - -#include "meson-gxm.dtsi" -#include "meson-gx-libretech-pc.dtsi" - -/ { - compatible = "libretech,aml-s912-pc", "amlogic,s912", - "amlogic,meson-gxm"; - model = "Libre Computer AML-S912-PC"; - - typec2_vbus: regulator-typec2_vbus { - compatible = "regulator-fixed"; - regulator-name = "TYPEC2_VBUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v>; - - gpio = <&gpio GPIODV_1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&pinctrl_periphs { - /* - * Make sure the irq pin of the TYPE C controller is not driven - * by the SoC. - */ - fusb302_irq_pins: fusb302_irq { - mux { - groups = "GPIODV_0"; - function = "gpio_periphs"; - bias-pull-up; - output-disable; - }; - }; -}; - -&i2c_C { - fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - - pinctrl-0 = <&fusb302_irq_pins>; - pinctrl-names = "default"; - interrupt-parent = <&gpio_intc>; - interrupts = <59 IRQ_TYPE_LEVEL_LOW>; - - vbus-supply = <&typec2_vbus>; - - status = "okay"; - }; -}; - -&usb2_phy2 { - phy-supply = <&typec2_vbus>; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts deleted file mode 100644 index d3fdba4da..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 BayLibre, SAS. - * Author: Neil Armstrong - * Copyright (c) 2017 Oleg - */ - -/dts-v1/; - -#include "meson-gxm.dtsi" -#include "meson-gx-p23x-q20x.dtsi" - -/ { - compatible = "tronsmart,vega-s96", "amlogic,s912", "amlogic,meson-gxm"; - model = "Tronsmart Vega S96"; - -}; - -ðmac { - pinctrl-0 = <ð_pins>; - pinctrl-names = "default"; - - /* Select external PHY by default */ - phy-handle = <&external_phy>; - - amlogic,tx-delay-ns = <2>; - - /* External PHY is in RGMII */ - phy-mode = "rgmii"; -}; - -&external_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - }; -}; - -&ir { - linux,rc-map-name = "rc-vega-s9x"; -}; - -&usb { - dr_mode = "host"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-wetek-core2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-wetek-core2.dts deleted file mode 100644 index ec794c134..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-wetek-core2.dts +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Christian Hewitt - */ - -/dts-v1/; - -#include "meson-gxm.dtsi" -#include "meson-gx-p23x-q20x.dtsi" -#include -#include - -/ { - compatible = "wetek,core2", "amlogic,s912", "amlogic,meson-gxm"; - model = "WeTek Core 2"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB or 3 GiB */ - }; - - leds { - compatible = "gpio-leds"; - - blue { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-update { - label = "update"; - linux,code = ; - press-threshold-microvolt = <10000>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - button-power { - label = "power"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - }; - }; -}; - -/* Disabled as Realtek RTL8152 USB provides Ethernet */ -ðmac { - status = "disabled"; -}; - -&internal_phy { - status = "disabled"; -}; - -&ir { - linux,rc-map-name = "rc-wetek-play2"; -}; - -/* This is connected to the Bluetooth module: */ -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi deleted file mode 100644 index fe4145112..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi +++ /dev/null @@ -1,196 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2016 Endless Computers, Inc. - * Author: Carlo Caione - */ - -#include "meson-gxl.dtsi" - -/ { - compatible = "amlogic,meson-gxm"; - - cpus { - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - }; - - cpu4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 1>; - #cooling-cells = <2>; - }; - - cpu5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x101>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 1>; - #cooling-cells = <2>; - }; - - cpu6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x102>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 1>; - #cooling-cells = <2>; - }; - - cpu7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x103>; - enable-method = "psci"; - next-level-cache = <&l2>; - clocks = <&scpi_dvfs 1>; - #cooling-cells = <2>; - }; - }; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-125000000 { - opp-hz = /bits/ 64 <125000000>; - opp-microvolt = <950000>; - }; - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <950000>; - }; - opp-285714285 { - opp-hz = /bits/ 64 <285714285>; - opp-microvolt = <950000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <950000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <950000>; - }; - opp-666666666 { - opp-hz = /bits/ 64 <666666666>; - opp-microvolt = <950000>; - }; - }; -}; - -&apb { - usb2_phy2: phy@78040 { - compatible = "amlogic,meson-gxl-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0x78040 0x0 0x20>; - clocks = <&clkc CLKID_USB>; - clock-names = "phy"; - resets = <&reset RESET_USB_OTG>; - reset-names = "phy"; - status = "okay"; - }; - - mali: gpu@c0000 { - compatible = "amlogic,meson-gxm-mali", "arm,mali-t820"; - reg = <0x0 0xc0000 0x0 0x40000>; - interrupt-parent = <&gic>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&clkc CLKID_MALI>; - resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>; - operating-points-v2 = <&gpu_opp_table>; - }; -}; - -&clkc_AO { - compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc"; -}; - -&cpu_cooling_maps { - map0 { - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; -}; - -&saradc { - compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc"; -}; - -&scpi_dvfs { - clock-indices = <0 1>; - clock-output-names = "vbig", "vlittle"; -}; - -&vpu { - compatible = "amlogic,meson-gxm-vpu", "amlogic,meson-gx-vpu"; -}; - -&hdmi_tx { - compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; -}; - -&usb { - compatible = "amlogic,meson-gxm-usb-ctrl"; - - phy-names = "usb2-phy0", "usb2-phy1", "usb2-phy2"; - phys = <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>; -}; - -&vdec { - compatible = "amlogic,gxm-vdec", "amlogic,gx-vdec"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi deleted file mode 100644 index 7b46555ac..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi +++ /dev/null @@ -1,497 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - * Copyright (c) 2019 Christian Hewitt - */ - -#include -#include -#include - -/ { - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 2>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1710000>; - - button-function { - label = "Function"; - linux,code = ; - press-threshold-microvolt = <10000>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-white { - label = "vim3:white:sys"; - gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-red { - label = "vim3:red"; - gpios = <&gpio_expander 5 GPIO_ACTIVE_HIGH>; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - - power-button { - label = "power"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "VCC_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vsys_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vsys_3v3>; - regulator-always-on; - }; - - emmc_1v8: regulator-emmc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vsys_3v3: regulator-vsys_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VSYS_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - usb_pwr: regulator-usb_pwr { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - gpio = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - - sound { - compatible = "amlogic,axg-sound-card"; - model = "G12B-KHADAS-VIM3"; - audio-aux-devs = <&tdmout_a>; - audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", - "TDMOUT_A IN 1", "FRDDR_B OUT 0", - "TDMOUT_A IN 2", "FRDDR_C OUT 0", - "TDM_A Playback", "TDMOUT_A OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_a>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; - }; - }; - - /* hdmi glue */ - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; -}; - -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cpu_thermal { - trips { - cpu_active: cpu-active { - temperature = <80000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "active"; - }; - }; - - cooling-maps { - map { - trip = <&cpu_active>; - cooling-device = <&khadas_mcu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c_AO { - status = "okay"; - pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>; - pinctrl-names = "default"; - - khadas_mcu: system-controller@18 { - compatible = "khadas,mcu"; - reg = <0x18>; - #cooling-cells = <2>; - }; - - gpio_expander: gpio-controller@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - vcc-supply = <&vcc_3v3>; - gpio-controller; - #gpio-cells = <2>; - }; - - rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - linux,rc-map-name = "rc-khadas"; -}; - -&pcie { - reset-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddao_1v8>; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vsys_3v3>; - vqmmc-supply = <&vddao_1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vsys_3v3>; - vqmmc-supply = <&vsys_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&emmc_1v8>; -}; - -/* - * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR CS - * and eMMC Data 4 to 7 pins. - * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0, - * and change bus-width to 4 then spifc can be enabled. - */ -&spifc { - status = "disabled"; - pinctrl-0 = <&nor_pins>; - pinctrl-names = "default"; - - w25q128: spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q128fw", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - }; -}; - - -&tdmif_a { - status = "okay"; -}; - -&tdmout_a { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - }; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb2_phy0 { - phy-supply = <&dc_in>; -}; - -&usb2_phy1 { - phy-supply = <&usb_pwr>; -}; - -&usb3_pcie_phy { - phy-supply = <&usb_pwr>; -}; - -&usb { - status = "okay"; - dr_mode = "peripheral"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts deleted file mode 100644 index 06de0b1ce..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - */ - -/dts-v1/; - -#include "meson-sm1.dtsi" -#include "meson-khadas-vim3.dtsi" -#include - -/ { - compatible = "khadas,vim3l", "amlogic,sm1"; - model = "Khadas VIM3L"; - - vddcpu: regulator-vddcpu { - /* - * Silergy SY8030DEC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <690000>; - regulator-max-microvolt = <1050000>; - - vin-supply = <&vsys_3v3>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -/* - * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential - * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between - * an USB3.0 Type A connector and a M.2 Key M slot. - * The PHY driving these differential lines is shared between - * the USB3.0 controller and the PCIe Controller, thus only - * a single controller can use it. - * If the MCU is configured to mux the PCIe/USB3.0 differential lines - * to the M.2 Key M slot, uncomment the following block to disable - * USB3.0 from the USB Complex and enable the PCIe controller. - * The End User is not expected to uncomment the following except for - * testing purposes, but instead rely on the firmware/bootloader to - * update these nodes accordingly if PCIe mode is selected by the MCU. - */ -/* -&pcie { - status = "okay"; -}; - -&usb { - phys = <&usb2_phy0>, <&usb2_phy1>; - phy-names = "usb2-phy0", "usb2-phy1"; -}; - */ - -&sd_emmc_a { - sd-uhs-sdr50; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts deleted file mode 100644 index a712273c9..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-c4.dts +++ /dev/null @@ -1,490 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Dongjin Kim - */ - -/dts-v1/; - -#include "meson-sm1.dtsi" -#include -#include -#include - -/ { - compatible = "hardkernel,odroid-c4", "amlogic,sm1"; - model = "Hardkernel ODROID-C4"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - leds { - compatible = "gpio-leds"; - - led-blue { - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - panic-indicator; - }; - }; - - tflash_vdd: regulator-tflash_vdd { - compatible = "regulator-fixed"; - - regulator-name = "TFLASH_VDD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>; - enable-active-high; - regulator-always-on; - }; - - tf_io: gpio-regulator-tf_io { - compatible = "regulator-gpio"; - - regulator-name = "TF_IO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio_ao GPIOAO_6 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - - states = <3300000 0>, - <1800000 1>; - }; - - flash_1v8: regulator-flash_1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - main_12v: regulator-main_12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&main_12v>; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vddcpu: regulator-vddcpu { - /* - * MP8756GD Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&main_12v>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - hub_5v: regulator-hub_5v { - compatible = "regulator-fixed"; - regulator-name = "HUB_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to the Hub CHIPENABLE, LOW sets low power state */ - gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usb_pwr_en: regulator-usb_pwr_en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to the microUSB port power enable */ - gpio = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddao_1v8: regulator-vddao_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&main_12v>; - regulator-always-on; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "SM1-ODROID-C4"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - /* 8ch hdmi interface */ - dai-link-3 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* hdmi glue */ - dai-link-4 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; -}; - -&arb { - status = "okay"; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&gpio { - gpio-line-names = - /* GPIOZ */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* GPIOH */ - "", "", "", "", "", - "PIN_36", /* GPIOH_5 */ - "PIN_26", /* GPIOH_6 */ - "PIN_32", /* GPIOH_7 */ - "", - /* BOOT */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - /* GPIOC */ - "", "", "", "", "", "", "", "", - /* GPIOA */ - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", - "PIN_27", /* GPIOA_14 */ - "PIN_28", /* GPIOA_15 */ - /* GPIOX */ - "PIN_16", /* GPIOX_0 */ - "PIN_18", /* GPIOX_1 */ - "PIN_22", /* GPIOX_2 */ - "PIN_11", /* GPIOX_3 */ - "PIN_13", /* GPIOX_4 */ - "PIN_7", /* GPIOX_5 */ - "PIN_33", /* GPIOX_6 */ - "PIN_15", /* GPIOX_7 */ - "PIN_19", /* GPIOX_8 */ - "PIN_21", /* GPIOX_9 */ - "PIN_24", /* GPIOX_10 */ - "PIN_23", /* GPIOX_11 */ - "PIN_8", /* GPIOX_12 */ - "PIN_10", /* GPIOX_13 */ - "PIN_29", /* GPIOX_14 */ - "PIN_31", /* GPIOX_15 */ - "PIN_12", /* GPIOX_16 */ - "PIN_3", /* GPIOX_17 */ - "PIN_5", /* GPIOX_18 */ - "PIN_35"; /* GPIOX_19 */ - - /* - * WARNING: The USB Hub on the Odroid-C4 needs a reset signal - * to be turned high in order to be detected by the USB Controller - * This signal should be handled by a USB specific power sequence - * in order to reset the Hub when USB bus is powered down. - */ - usb-hub { - gpio-hog; - gpios = ; - output-high; - line-name = "usb-hub-reset"; - }; -}; - -&gpio_ao { - gpio-line-names = - /* GPIOAO */ - "", "", "", "", - "PIN_47", /* GPIOAO_4 */ - "", "", - "PIN_45", /* GPIOAO_7 */ - "PIN_46", /* GPIOAO_8 */ - "PIN_44", /* GPIOAO_9 */ - "PIN_42", /* GPIOAO_10 */ - "", - /* GPIOE */ - "", "", ""; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; - linux,rc-map-name = "rc-odroid"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&saradc { - status = "okay"; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <200000000>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&tflash_vdd>; - vqmmc-supply = <&tf_io>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&flash_1v8>; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - vbus-supply = <&usb_pwr_en>; -}; - -&usb2_phy0 { - phy-supply = <&vcc_5v>; -}; - -&usb2_phy1 { - /* Enable the hub which is connected to this port */ - phy-supply = <&hub_5v>; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts deleted file mode 100644 index c21178e9c..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts +++ /dev/null @@ -1,608 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre SAS. All rights reserved. - */ - -/dts-v1/; - -#include "meson-sm1.dtsi" -#include -#include -#include -#include - -/ { - compatible = "seirobotics,sei610", "amlogic,sm1"; - model = "SEI Robotics SEI610"; - - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - mono_dac: audio-codec-0 { - compatible = "maxim,max98357a"; - #sound-dai-cells = <0>; - sound-name-prefix = "U16"; - sdmode-gpios = <&gpio GPIOX_8 GPIO_ACTIVE_HIGH>; - }; - - dmics: audio-codec-1 { - #sound-dai-cells = <0>; - compatible = "dmic-codec"; - num-channels = <2>; - wakeup-delay-ms = <50>; - status = "okay"; - sound-name-prefix = "MIC"; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key1 { - label = "A"; - linux,code = ; - gpios = <&gpio GPIOH_6 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <34 IRQ_TYPE_EDGE_BOTH>; - }; - - key2 { - label = "B"; - linux,code = ; - gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <35 IRQ_TYPE_EDGE_BOTH>; - }; - - key3 { - label = "C"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <2 IRQ_TYPE_EDGE_BOTH>; - }; - - mic_mute { - label = "MicMute"; - linux,code = ; - linux,input-type = ; - gpios = <&gpio_ao GPIOE_2 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <99 IRQ_TYPE_EDGE_BOTH>; - }; - - power_key { - label = "PowerKey"; - linux,code = ; - gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio_intc>; - interrupts = <3 IRQ_TYPE_EDGE_BOTH>; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-bluetooth { - label = "sei610:blue:bt"; - gpios = <&gpio GPIOC_7 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; - default-state = "off"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - - power { - label = "sei610:red:power"; - pwms = <&pwm_AO_ab 0 30518 0>; - max-brightness = <255>; - linux,default-trigger = "default-on"; - active-low; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - ao_5v: regulator-ao_5v { - compatible = "regulator-fixed"; - regulator-name = "AO_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - dc_in: regulator-dc_in { - compatible = "regulator-fixed"; - regulator-name = "DC_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - emmc_1v8: regulator-emmc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "EMMC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&dc_in>; - regulator-always-on; - }; - - /* Used by Tuner, RGB Led & IR Emitter LED array */ - vddao_3v3_t: regulator-vddao_3v3_t { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3_T"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-low; - regulator-always-on; - }; - - vddcpu: regulator-vddcpu { - /* - * SY8120B1ABC DC/DC Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU"; - regulator-min-microvolt = <690000>; - regulator-max-microvolt = <1050000>; - - vin-supply = <&dc_in>; - - pwms = <&pwm_AO_cd 1 1500 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddio_ao1v8: regulator-vddio_ao1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDIO_AO1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - - sound { - compatible = "amlogic,axg-sound-card"; - model = "SM1-SEI610"; - audio-aux-devs = <&tdmout_a>, <&tdmout_b>, - <&tdmin_a>, <&tdmin_b>; - audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", - "TDMOUT_A IN 1", "FRDDR_B OUT 0", - "TDMOUT_A IN 2", "FRDDR_C OUT 0", - "TDM_A Playback", "TDMOUT_A OUT", - "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT", - "TODDR_A IN 4", "PDM Capture", - "TODDR_B IN 4", "PDM Capture", - "TODDR_C IN 4", "PDM Capture", - "TDMIN_A IN 0", "TDM_A Capture", - "TDMIN_A IN 3", "TDM_A Loopback", - "TDMIN_B IN 0", "TDM_A Capture", - "TDMIN_B IN 3", "TDM_A Loopback", - "TDMIN_A IN 1", "TDM_B Capture", - "TDMIN_A IN 4", "TDM_B Loopback", - "TDMIN_B IN 1", "TDM_B Capture", - "TDMIN_B IN 4", "TDM_B Loopback", - "TODDR_A IN 0", "TDMIN_A OUT", - "TODDR_B IN 0", "TDMIN_A OUT", - "TODDR_C IN 0", "TDMIN_A OUT", - "TODDR_A IN 1", "TDMIN_B OUT", - "TODDR_B IN 1", "TDMIN_B OUT", - "TODDR_C IN 1", "TDMIN_B OUT"; - - assigned-clocks = <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; - assigned-clock-rates = <294912000>, - <270950400>, - <393216000>; - status = "okay"; - - dai-link-0 { - sound-dai = <&frddr_a>; - }; - - dai-link-1 { - sound-dai = <&frddr_b>; - }; - - dai-link-2 { - sound-dai = <&frddr_c>; - }; - - dai-link-3 { - sound-dai = <&toddr_a>; - }; - - dai-link-4 { - sound-dai = <&toddr_b>; - }; - - dai-link-5 { - sound-dai = <&toddr_c>; - }; - - /* internal speaker interface */ - dai-link-6 { - sound-dai = <&tdmif_a>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - mclk-fs = <256>; - - codec-0 { - sound-dai = <&mono_dac>; - }; - - codec-1 { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; - }; - }; - - /* 8ch hdmi interface */ - dai-link-7 { - sound-dai = <&tdmif_b>; - dai-format = "i2s"; - dai-tdm-slot-tx-mask-0 = <1 1>; - dai-tdm-slot-tx-mask-1 = <1 1>; - dai-tdm-slot-tx-mask-2 = <1 1>; - dai-tdm-slot-tx-mask-3 = <1 1>; - mclk-fs = <256>; - - codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; - }; - }; - - /* internal digital mics */ - dai-link-8 { - sound-dai = <&pdm>; - - codec { - sound-dai = <&dmics>; - }; - }; - - /* hdmi glue */ - dai-link-9 { - sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; - - codec { - sound-dai = <&hdmi_tx>; - }; - }; - }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; -}; - -&arb { - status = "okay"; -}; - -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - -&clkc_audio { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; - clock-latency = <50000>; -}; - -&cpu2 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; - clock-latency = <50000>; -}; - -&cpu3 { - cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; - clock-latency = <50000>; -}; - -ðmac { - status = "okay"; - phy-handle = <&internal_ephy>; - phy-mode = "rmii"; -}; - -&frddr_a { - status = "okay"; -}; - -&frddr_b { - status = "okay"; -}; - -&frddr_c { - status = "okay"; -}; - -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; - pinctrl-names = "default"; -}; - -&ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; -}; - -&pdm { - pinctrl-0 = <&pdm_din0_z_pins>, <&pdm_dclk_z_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pwm_AO_ab { - status = "okay"; - pinctrl-0 = <&pwm_ao_a_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&pwm_ef { - status = "okay"; - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vddio_ao1v8>; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr50; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - /* WiFi firmware requires power to be kept while in suspend */ - keep-power-in-suspend; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddio_ao1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - max-frequency = <200000000>; - non-removable; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&emmc_1v8>; -}; - -&tdmif_a { - pinctrl-0 = <&tdm_a_dout0_pins>, <&tdm_a_fs_pins>, <&tdm_a_sclk_pins>; - pinctrl-names = "default"; - status = "okay"; - - assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD0>, - <&clkc_audio AUD_CLKID_TDM_LRCLK_PAD0>; - assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - assigned-clock-rates = <0>, <0>; -}; - -&tdmif_b { - status = "okay"; -}; - -&tdmin_a { - status = "okay"; -}; - -&tdmin_b { - status = "okay"; -}; - -&tdmout_a { - status = "okay"; -}; - -&tdmout_b { - status = "okay"; -}; - -&toddr_a { - status = "okay"; -}; - -&toddr_b { - status = "okay"; -}; - -&toddr_c { - status = "okay"; -}; - -&tohdmitx { - status = "okay"; -}; - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - interrupt-parent = <&gpio_intc>; - interrupts = <95 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wakeup"; - shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; - max-speed = <2000000>; - clocks = <&wifi32k>; - clock-names = "lpo"; - vbat-supply = <&vddao_3v3>; - vddio-supply = <&vddio_ao1v8>; - }; -}; - -/* Exposed via the on-board USB to Serial FT232RL IC */ -&uart_AO { - status = "okay"; - pinctrl-0 = <&uart_ao_a_pins>; - pinctrl-names = "default"; -}; - -&usb { - status = "okay"; - dr_mode = "otg"; -}; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi deleted file mode 100644 index defe0b8d4..000000000 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ /dev/null @@ -1,508 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 BayLibre, SAS - * Author: Neil Armstrong - */ - -#include "meson-g12-common.dtsi" -#include -#include -#include -#include - -/ { - compatible = "amlogic,sm1"; - - tdmif_a: audio-controller-0 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_A"; - clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, - <&clkc_audio AUD_CLKID_MST_A_SCLK>, - <&clkc_audio AUD_CLKID_MST_A_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_b: audio-controller-1 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_B"; - clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, - <&clkc_audio AUD_CLKID_MST_B_SCLK>, - <&clkc_audio AUD_CLKID_MST_B_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - tdmif_c: audio-controller-2 { - compatible = "amlogic,axg-tdm-iface"; - #sound-dai-cells = <0>; - sound-name-prefix = "TDM_C"; - clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, - <&clkc_audio AUD_CLKID_MST_C_SCLK>, - <&clkc_audio AUD_CLKID_MST_C_LRCLK>; - clock-names = "mclk", "sclk", "lrclk"; - status = "disabled"; - }; - - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - #cooling-cells = <2>; - }; - - l2: l2-cache0 { - compatible = "cache"; - }; - }; - - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <770000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <780000>; - }; - - opp-1404000000 { - opp-hz = /bits/ 64 <1404000000>; - opp-microvolt = <790000>; - }; - - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <800000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <810000>; - }; - - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <850000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <900000>; - }; - - opp-1908000000 { - opp-hz = /bits/ 64 <1908000000>; - opp-microvolt = <950000>; - }; - }; -}; - -&apb { - audio: bus@60000 { - compatible = "simple-bus"; - reg = <0x0 0x60000 0x0 0x1000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x60000 0x0 0x1000>; - - clkc_audio: clock-controller@0 { - status = "disabled"; - compatible = "amlogic,sm1-audio-clkc"; - reg = <0x0 0x0 0x0 0xb4>; - #clock-cells = <1>; - #reset-cells = <1>; - - clocks = <&clkc CLKID_AUDIO>, - <&clkc CLKID_MPLL0>, - <&clkc CLKID_MPLL1>, - <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL3>, - <&clkc CLKID_HIFI_PLL>, - <&clkc CLKID_FCLK_DIV3>, - <&clkc CLKID_FCLK_DIV4>, - <&clkc CLKID_FCLK_DIV5>; - clock-names = "pclk", - "mst_in0", - "mst_in1", - "mst_in2", - "mst_in3", - "mst_in4", - "mst_in5", - "mst_in6", - "mst_in7"; - - resets = <&reset RESET_AUDIO>; - }; - - toddr_a: audio-controller@100 { - compatible = "amlogic,sm1-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x100 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_A"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_A>; - resets = <&arb AXG_ARB_TODDR_A>, - <&clkc_audio AUD_RESET_TODDR_A>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <8192>; - status = "disabled"; - }; - - toddr_b: audio-controller@140 { - compatible = "amlogic,sm1-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x140 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_B"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_B>; - resets = <&arb AXG_ARB_TODDR_B>, - <&clkc_audio AUD_RESET_TODDR_B>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - toddr_c: audio-controller@180 { - compatible = "amlogic,sm1-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x180 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_C"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_C>; - resets = <&arb AXG_ARB_TODDR_C>, - <&clkc_audio AUD_RESET_TODDR_C>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_a: audio-controller@1c0 { - compatible = "amlogic,sm1-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x1c0 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_A"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; - resets = <&arb AXG_ARB_FRDDR_A>, - <&clkc_audio AUD_RESET_FRDDR_A>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <512>; - status = "disabled"; - }; - - frddr_b: audio-controller@200 { - compatible = "amlogic,sm1-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x200 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_B"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; - resets = <&arb AXG_ARB_FRDDR_B>, - <&clkc_audio AUD_RESET_FRDDR_B>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_c: audio-controller@240 { - compatible = "amlogic,sm1-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x240 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_C"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; - resets = <&arb AXG_ARB_FRDDR_C>, - <&clkc_audio AUD_RESET_FRDDR_C>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - arb: reset-controller@280 { - status = "disabled"; - compatible = "amlogic,meson-sm1-audio-arb"; - reg = <0x0 0x280 0x0 0x4>; - #reset-cells = <1>; - clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; - }; - - tdmin_a: audio-controller@300 { - compatible = "amlogic,sm1-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x300 0x0 0x40>; - sound-name-prefix = "TDMIN_A"; - resets = <&clkc_audio AUD_RESET_TDMIN_A>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_b: audio-controller@340 { - compatible = "amlogic,sm1-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x340 0x0 0x40>; - sound-name-prefix = "TDMIN_B"; - resets = <&clkc_audio AUD_RESET_TDMIN_B>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_c: audio-controller@380 { - compatible = "amlogic,sm1-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x380 0x0 0x40>; - sound-name-prefix = "TDMIN_C"; - resets = <&clkc_audio AUD_RESET_TDMIN_C>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmin_lb: audio-controller@3c0 { - compatible = "amlogic,sm1-tdmin", - "amlogic,axg-tdmin"; - reg = <0x0 0x3c0 0x0 0x40>; - sound-name-prefix = "TDMIN_LB"; - resets = <&clkc_audio AUD_RESET_TDMIN_LB>; - clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, - <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_a: audio-controller@500 { - compatible = "amlogic,sm1-tdmout"; - reg = <0x0 0x500 0x0 0x40>; - sound-name-prefix = "TDMOUT_A"; - resets = <&clkc_audio AUD_RESET_TDMOUT_A>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_b: audio-controller@540 { - compatible = "amlogic,sm1-tdmout"; - reg = <0x0 0x540 0x0 0x40>; - sound-name-prefix = "TDMOUT_B"; - resets = <&clkc_audio AUD_RESET_TDMOUT_B>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tdmout_c: audio-controller@580 { - compatible = "amlogic,sm1-tdmout"; - reg = <0x0 0x580 0x0 0x40>; - sound-name-prefix = "TDMOUT_C"; - resets = <&clkc_audio AUD_RESET_TDMOUT_C>; - clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, - <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; - clock-names = "pclk", "sclk", "sclk_sel", - "lrclk", "lrclk_sel"; - status = "disabled"; - }; - - tohdmitx: audio-controller@744 { - compatible = "amlogic,sm1-tohdmitx", - "amlogic,g12a-tohdmitx"; - reg = <0x0 0x744 0x0 0x4>; - #sound-dai-cells = <1>; - sound-name-prefix = "TOHDMITX"; - resets = <&clkc_audio AUD_RESET_TOHDMITX>; - status = "disabled"; - }; - - toddr_d: audio-controller@840 { - compatible = "amlogic,sm1-toddr", - "amlogic,axg-toddr"; - reg = <0x0 0x840 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "TODDR_D"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_TODDR_D>; - resets = <&arb AXG_ARB_TODDR_D>, - <&clkc_audio AUD_RESET_TODDR_D>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - - frddr_d: audio-controller@880 { - compatible = "amlogic,sm1-frddr", - "amlogic,axg-frddr"; - reg = <0x0 0x880 0x0 0x2c>; - #sound-dai-cells = <0>; - sound-name-prefix = "FRDDR_D"; - interrupts = ; - clocks = <&clkc_audio AUD_CLKID_FRDDR_D>; - resets = <&arb AXG_ARB_FRDDR_D>, - <&clkc_audio AUD_RESET_FRDDR_D>; - reset-names = "arb", "rst"; - amlogic,fifo-depth = <256>; - status = "disabled"; - }; - }; - - pdm: audio-controller@61000 { - compatible = "amlogic,sm1-pdm", - "amlogic,axg-pdm"; - reg = <0x0 0x61000 0x0 0x34>; - #sound-dai-cells = <0>; - sound-name-prefix = "PDM"; - clocks = <&clkc_audio AUD_CLKID_PDM>, - <&clkc_audio AUD_CLKID_PDM_DCLK>, - <&clkc_audio AUD_CLKID_PDM_SYSCLK>; - clock-names = "pclk", "dclk", "sysclk"; - resets = <&clkc_audio AUD_RESET_PDM>; - status = "disabled"; - }; -}; - -&cecb_AO { - compatible = "amlogic,meson-sm1-ao-cec"; -}; - -&clk_msr { - compatible = "amlogic,meson-sm1-clk-measure"; -}; - - -&clkc { - compatible = "amlogic,sm1-clkc"; -}; - -&cpu_thermal { - cooling-maps { - map0 { - trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -ðmac { - power-domains = <&pwrc PWRC_SM1_ETH_ID>; -}; - -&gpio_intc { - compatible = "amlogic,meson-sm1-gpio-intc", - "amlogic,meson-gpio-intc"; -}; - -&pcie { - power-domains = <&pwrc PWRC_SM1_PCIE_ID>; -}; - -&pwrc { - compatible = "amlogic,meson-sm1-pwrc"; -}; - -&simplefb_cvbs { - power-domains = <&pwrc PWRC_SM1_VPU_ID>; -}; - -&simplefb_hdmi { - power-domains = <&pwrc PWRC_SM1_VPU_ID>; -}; - -&vdec { - compatible = "amlogic,sm1-vdec"; -}; - -&vpu { - power-domains = <&pwrc PWRC_SM1_VPU_ID>; -}; - -&usb { - power-domains = <&pwrc PWRC_SM1_USB_ID>; -}; diff --git a/arch/arm64/boot/dts/apm/Makefile b/arch/arm64/boot/dts/apm/Makefile deleted file mode 100644 index 55b5cdca1..000000000 --- a/arch/arm64/boot/dts/apm/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb -dtb-$(CONFIG_ARCH_XGENE) += apm-merlin.dtb diff --git a/arch/arm64/boot/dts/apm/apm-merlin.dts b/arch/arm64/boot/dts/apm/apm-merlin.dts deleted file mode 100644 index 217d7728b..000000000 --- a/arch/arm64/boot/dts/apm/apm-merlin.dts +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * dts file for AppliedMicro (APM) Merlin Board - * - * Copyright (C) 2015, Applied Micro Circuits Corporation - */ - -/dts-v1/; - -/include/ "apm-shadowcat.dtsi" - -/ { - model = "APM X-Gene Merlin board"; - compatible = "apm,merlin", "apm,xgene-shadowcat"; - - chosen { }; - - memory { - device_type = "memory"; - reg = < 0x1 0x00000000 0x0 0x80000000 >; - }; - - gpio-keys { - compatible = "gpio-keys"; - button@1 { - label = "POWER"; - linux,code = <116>; - linux,input-type = <0x1>; - interrupt-parent = <&sbgpio>; - interrupts = <0x0 0x1>; - }; - }; - - poweroff_mbox: poweroff_mbox@10548000 { - compatible = "syscon"; - reg = <0x0 0x10548000 0x0 0x30>; - }; - - poweroff: poweroff@10548010 { - compatible = "syscon-poweroff"; - regmap = <&poweroff_mbox>; - offset = <0x10>; - mask = <0x1>; - }; -}; - -&serial0 { - status = "ok"; -}; - -&sata1 { - status = "ok"; -}; - -&sata2 { - status = "ok"; -}; - -&sata3 { - status = "ok"; -}; - -&sgenet0 { - status = "ok"; -}; - -&xgenet1 { - status = "ok"; -}; - -&mmc0 { - status = "ok"; -}; - -&i2c4 { - rtc68: rtc@68 { - compatible = "dallas,ds1337"; - reg = <0x68>; - status = "ok"; - }; -}; - -&mdio { - sgenet0phy: phy@0 { - reg = <0x0>; - }; -}; diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts b/arch/arm64/boot/dts/apm/apm-mustang.dts deleted file mode 100644 index e927811ad..000000000 --- a/arch/arm64/boot/dts/apm/apm-mustang.dts +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * dts file for AppliedMicro (APM) Mustang Board - * - * Copyright (C) 2013, Applied Micro Circuits Corporation - */ - -/dts-v1/; - -/include/ "apm-storm.dtsi" - -/ { - model = "APM X-Gene Mustang board"; - compatible = "apm,mustang", "apm,xgene-storm"; - - chosen { }; - - memory { - device_type = "memory"; - reg = < 0x1 0x00000000 0x0 0x80000000 >; /* Updated by bootloader */ - }; - - gpio-keys { - compatible = "gpio-keys"; - button@1 { - label = "POWER"; - linux,code = <116>; - linux,input-type = <0x1>; - interrupt-parent = <&sbgpio>; - interrupts = <0x5 0x1>; - }; - }; - - poweroff_mbox: poweroff_mbox@10548000 { - compatible = "syscon"; - reg = <0x0 0x10548000 0x0 0x30>; - }; - - poweroff: poweroff@10548010 { - compatible = "syscon-poweroff"; - regmap = <&poweroff_mbox>; - offset = <0x10>; - mask = <0x1>; - }; -}; - -&pcie0clk { - status = "ok"; -}; - -&pcie0 { - status = "ok"; -}; - -&serial0 { - status = "ok"; -}; - -&menet { - status = "ok"; -}; - -&sgenet0 { - status = "ok"; -}; - -&sgenet1 { - status = "ok"; -}; - -&xgenet { - status = "ok"; - rxlos-gpios = <&sbgpio 12 1>; -}; - -&mmc0 { - status = "ok"; -}; - -&mdio { - menet0phy: phy@3 { - reg = <0x3>; - }; - sgenet0phy: phy@4 { - reg = <0x4>; - }; - sgenet1phy: phy@5 { - reg = <0x5>; - }; -}; diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi deleted file mode 100644 index a83c82c50..000000000 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ /dev/null @@ -1,818 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC - * - * Copyright (C) 2015, Applied Micro Circuits Corporation - */ - -/ { - compatible = "apm,xgene-shadowcat"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "apm,strega"; - reg = <0x0 0x000>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_0>; - #clock-cells = <1>; - clocks = <&pmd0clk 0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "apm,strega"; - reg = <0x0 0x001>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_0>; - #clock-cells = <1>; - clocks = <&pmd0clk 0>; - }; - cpu@100 { - device_type = "cpu"; - compatible = "apm,strega"; - reg = <0x0 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_1>; - #clock-cells = <1>; - clocks = <&pmd1clk 0>; - }; - cpu@101 { - device_type = "cpu"; - compatible = "apm,strega"; - reg = <0x0 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_1>; - #clock-cells = <1>; - clocks = <&pmd1clk 0>; - }; - cpu@200 { - device_type = "cpu"; - compatible = "apm,strega"; - reg = <0x0 0x200>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_2>; - #clock-cells = <1>; - clocks = <&pmd2clk 0>; - }; - cpu@201 { - device_type = "cpu"; - compatible = "apm,strega"; - reg = <0x0 0x201>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_2>; - #clock-cells = <1>; - clocks = <&pmd2clk 0>; - }; - cpu@300 { - device_type = "cpu"; - compatible = "apm,strega"; - reg = <0x0 0x300>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_3>; - #clock-cells = <1>; - clocks = <&pmd3clk 0>; - }; - cpu@301 { - device_type = "cpu"; - compatible = "apm,strega"; - reg = <0x0 0x301>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_3>; - #clock-cells = <1>; - clocks = <&pmd3clk 0>; - }; - xgene_L2_0: l2-cache-0 { - compatible = "cache"; - }; - xgene_L2_1: l2-cache-1 { - compatible = "cache"; - }; - xgene_L2_2: l2-cache-2 { - compatible = "cache"; - }; - xgene_L2_3: l2-cache-3 { - compatible = "cache"; - }; - }; - - gic: interrupt-controller@78090000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - interrupt-controller; - interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ - ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */ - reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */ - <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */ - <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */ - <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */ - v2m0: v2m@0 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x0 0x0 0x1000>; - }; - v2m1: v2m@10000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x10000 0x0 0x1000>; - }; - v2m2: v2m@20000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x20000 0x0 0x1000>; - }; - v2m3: v2m@30000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x30000 0x0 0x1000>; - }; - v2m4: v2m@40000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x40000 0x0 0x1000>; - }; - v2m5: v2m@50000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x50000 0x0 0x1000>; - }; - v2m6: v2m@60000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x60000 0x0 0x1000>; - }; - v2m7: v2m@70000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x70000 0x0 0x1000>; - }; - v2m8: v2m@80000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x80000 0x0 0x1000>; - }; - v2m9: v2m@90000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0x90000 0x0 0x1000>; - }; - v2m10: v2m@a0000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0xa0000 0x0 0x1000>; - }; - v2m11: v2m@b0000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0xb0000 0x0 0x1000>; - }; - v2m12: v2m@c0000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0xc0000 0x0 0x1000>; - }; - v2m13: v2m@d0000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0xd0000 0x0 0x1000>; - }; - v2m14: v2m@e0000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0xe0000 0x0 0x1000>; - }; - v2m15: v2m@f0000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x0 0xf0000 0x0 0x1000>; - }; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <1 12 0xff04>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 0 0xff08>, /* Secure Phys IRQ */ - <1 13 0xff08>, /* Non-secure Phys IRQ */ - <1 14 0xff08>, /* Virt IRQ */ - <1 15 0xff08>; /* Hyp IRQ */ - clock-frequency = <50000000>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - refclk: refclk { - compatible = "fixed-clock"; - #clock-cells = <1>; - clock-frequency = <100000000>; - clock-output-names = "refclk"; - }; - - pmdpll: pmdpll@170000f0 { - compatible = "apm,xgene-pcppll-v2-clock"; - #clock-cells = <1>; - clocks = <&refclk 0>; - reg = <0x0 0x170000f0 0x0 0x10>; - clock-output-names = "pmdpll"; - }; - - pmd0clk: pmd0clk@7e200200 { - compatible = "apm,xgene-pmd-clock"; - #clock-cells = <1>; - clocks = <&pmdpll 0>; - reg = <0x0 0x7e200200 0x0 0x10>; - clock-output-names = "pmd0clk"; - }; - - pmd1clk: pmd1clk@7e200210 { - compatible = "apm,xgene-pmd-clock"; - #clock-cells = <1>; - clocks = <&pmdpll 0>; - reg = <0x0 0x7e200210 0x0 0x10>; - clock-output-names = "pmd1clk"; - }; - - pmd2clk: pmd2clk@7e200220 { - compatible = "apm,xgene-pmd-clock"; - #clock-cells = <1>; - clocks = <&pmdpll 0>; - reg = <0x0 0x7e200220 0x0 0x10>; - clock-output-names = "pmd2clk"; - }; - - pmd3clk: pmd3clk@7e200230 { - compatible = "apm,xgene-pmd-clock"; - #clock-cells = <1>; - clocks = <&pmdpll 0>; - reg = <0x0 0x7e200230 0x0 0x10>; - clock-output-names = "pmd3clk"; - }; - - socpll: socpll@17000120 { - compatible = "apm,xgene-socpll-v2-clock"; - #clock-cells = <1>; - clocks = <&refclk 0>; - reg = <0x0 0x17000120 0x0 0x1000>; - clock-output-names = "socpll"; - }; - - socplldiv2: socplldiv2 { - compatible = "fixed-factor-clock"; - #clock-cells = <1>; - clocks = <&socpll 0>; - clock-mult = <1>; - clock-div = <2>; - clock-output-names = "socplldiv2"; - }; - - ahbclk: ahbclk@17000000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x17000000 0x0 0x2000>; - reg-names = "div-reg"; - divider-offset = <0x164>; - divider-width = <0x5>; - divider-shift = <0x0>; - clock-output-names = "ahbclk"; - }; - - sbapbclk: sbapbclk@1704c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&ahbclk 0>; - reg = <0x0 0x1704c000 0x0 0x2000>; - reg-names = "div-reg"; - divider-offset = <0x10>; - divider-width = <0x2>; - divider-shift = <0x0>; - clock-output-names = "sbapbclk"; - }; - - sdioclk: sdioclk@1f2ac000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f2ac000 0x0 0x1000 - 0x0 0x17000000 0x0 0x2000>; - reg-names = "csr-reg", "div-reg"; - csr-offset = <0x0>; - csr-mask = <0x2>; - enable-offset = <0x8>; - enable-mask = <0x2>; - divider-offset = <0x178>; - divider-width = <0x8>; - divider-shift = <0x0>; - clock-output-names = "sdioclk"; - }; - - pcie0clk: pcie0clk@1f2bc000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f2bc000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "pcie0clk"; - }; - - pcie1clk: pcie1clk@1f2cc000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f2cc000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "pcie1clk"; - }; - - xge0clk: xge0clk@1f61c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f61c000 0x0 0x1000>; - reg-names = "csr-reg"; - enable-mask = <0x3>; - csr-mask = <0x3>; - clock-output-names = "xge0clk"; - }; - - xge1clk: xge1clk@1f62c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f62c000 0x0 0x1000>; - reg-names = "csr-reg"; - enable-mask = <0x3>; - csr-mask = <0x3>; - clock-output-names = "xge1clk"; - }; - - rngpkaclk: rngpkaclk@17000000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x17000000 0x0 0x2000>; - reg-names = "csr-reg"; - csr-offset = <0xc>; - csr-mask = <0x10>; - enable-offset = <0x10>; - enable-mask = <0x10>; - clock-output-names = "rngpkaclk"; - }; - - i2c4clk: i2c4clk@1704c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&sbapbclk 0>; - reg = <0x0 0x1704c000 0x0 0x1000>; - reg-names = "csr-reg"; - csr-offset = <0x0>; - csr-mask = <0x40>; - enable-offset = <0x8>; - enable-mask = <0x40>; - clock-output-names = "i2c4clk"; - }; - }; - - scu: system-clk-controller@17000000 { - compatible = "apm,xgene-scu","syscon"; - reg = <0x0 0x17000000 0x0 0x400>; - }; - - reboot: reboot@17000014 { - compatible = "syscon-reboot"; - regmap = <&scu>; - offset = <0x14>; - mask = <0x1>; - }; - - csw: csw@7e200000 { - compatible = "apm,xgene-csw", "syscon"; - reg = <0x0 0x7e200000 0x0 0x1000>; - }; - - mcba: mcba@7e700000 { - compatible = "apm,xgene-mcb", "syscon"; - reg = <0x0 0x7e700000 0x0 0x1000>; - }; - - mcbb: mcbb@7e720000 { - compatible = "apm,xgene-mcb", "syscon"; - reg = <0x0 0x7e720000 0x0 0x1000>; - }; - - efuse: efuse@1054a000 { - compatible = "apm,xgene-efuse", "syscon"; - reg = <0x0 0x1054a000 0x0 0x20>; - }; - - edac@78800000 { - compatible = "apm,xgene-edac"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - regmap-csw = <&csw>; - regmap-mcba = <&mcba>; - regmap-mcbb = <&mcbb>; - regmap-efuse = <&efuse>; - reg = <0x0 0x78800000 0x0 0x100>; - interrupts = <0x0 0x20 0x4>, - <0x0 0x21 0x4>, - <0x0 0x27 0x4>; - - edacmc@7e800000 { - compatible = "apm,xgene-edac-mc"; - reg = <0x0 0x7e800000 0x0 0x1000>; - memory-controller = <0>; - }; - - edacmc@7e840000 { - compatible = "apm,xgene-edac-mc"; - reg = <0x0 0x7e840000 0x0 0x1000>; - memory-controller = <1>; - }; - - edacmc@7e880000 { - compatible = "apm,xgene-edac-mc"; - reg = <0x0 0x7e880000 0x0 0x1000>; - memory-controller = <2>; - }; - - edacmc@7e8c0000 { - compatible = "apm,xgene-edac-mc"; - reg = <0x0 0x7e8c0000 0x0 0x1000>; - memory-controller = <3>; - }; - - edacpmd@7c000000 { - compatible = "apm,xgene-edac-pmd"; - reg = <0x0 0x7c000000 0x0 0x200000>; - pmd-controller = <0>; - }; - - edacpmd@7c200000 { - compatible = "apm,xgene-edac-pmd"; - reg = <0x0 0x7c200000 0x0 0x200000>; - pmd-controller = <1>; - }; - - edacpmd@7c400000 { - compatible = "apm,xgene-edac-pmd"; - reg = <0x0 0x7c400000 0x0 0x200000>; - pmd-controller = <2>; - }; - - edacpmd@7c600000 { - compatible = "apm,xgene-edac-pmd"; - reg = <0x0 0x7c600000 0x0 0x200000>; - pmd-controller = <3>; - }; - - edacl3@7e600000 { - compatible = "apm,xgene-edac-l3-v2"; - reg = <0x0 0x7e600000 0x0 0x1000>; - }; - - edacsoc@7e930000 { - compatible = "apm,xgene-edac-soc"; - reg = <0x0 0x7e930000 0x0 0x1000>; - }; - }; - - pmu: pmu@78810000 { - compatible = "apm,xgene-pmu-v2"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - regmap-csw = <&csw>; - regmap-mcba = <&mcba>; - regmap-mcbb = <&mcbb>; - reg = <0x0 0x78810000 0x0 0x1000>; - interrupts = <0x0 0x22 0x4>; - - pmul3c@7e610000 { - compatible = "apm,xgene-pmu-l3c"; - reg = <0x0 0x7e610000 0x0 0x1000>; - }; - - pmuiob@7e940000 { - compatible = "apm,xgene-pmu-iob"; - reg = <0x0 0x7e940000 0x0 0x1000>; - }; - - pmucmcb@7e710000 { - compatible = "apm,xgene-pmu-mcb"; - reg = <0x0 0x7e710000 0x0 0x1000>; - enable-bit-index = <0>; - }; - - pmucmcb@7e730000 { - compatible = "apm,xgene-pmu-mcb"; - reg = <0x0 0x7e730000 0x0 0x1000>; - enable-bit-index = <1>; - }; - - pmucmc@7e810000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e810000 0x0 0x1000>; - enable-bit-index = <0>; - }; - - pmucmc@7e850000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e850000 0x0 0x1000>; - enable-bit-index = <1>; - }; - - pmucmc@7e890000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e890000 0x0 0x1000>; - enable-bit-index = <2>; - }; - - pmucmc@7e8d0000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e8d0000 0x0 0x1000>; - enable-bit-index = <3>; - }; - }; - - mailbox: mailbox@10540000 { - compatible = "apm,xgene-slimpro-mbox"; - reg = <0x0 0x10540000 0x0 0x8000>; - #mbox-cells = <1>; - interrupts = <0x0 0x0 0x4 - 0x0 0x1 0x4 - 0x0 0x2 0x4 - 0x0 0x3 0x4 - 0x0 0x4 0x4 - 0x0 0x5 0x4 - 0x0 0x6 0x4 - 0x0 0x7 0x4>; - }; - - i2cslimpro { - compatible = "apm,xgene-slimpro-i2c"; - mboxes = <&mailbox 0>; - }; - - hwmonslimpro { - compatible = "apm,xgene-slimpro-hwmon"; - mboxes = <&mailbox 7>; - }; - - serial0: serial@10600000 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0 0x10600000 0x0 0x1000>; - reg-shift = <2>; - clock-frequency = <10000000>; - interrupt-parent = <&gic>; - interrupts = <0x0 0x4c 0x4>; - }; - - /* Do not change dwusb name, coded for backward compatibility */ - usb0: dwusb@19000000 { - status = "disabled"; - compatible = "snps,dwc3"; - reg = <0x0 0x19000000 0x0 0x100000>; - interrupts = <0x0 0x5d 0x4>; - dma-coherent; - dr_mode = "host"; - }; - - pcie0: pcie@1f2b0000 { - status = "disabled"; - device_type = "pci"; - compatible = "apm,xgene-pcie", "apm,xgene2-pcie"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ - 0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */ - reg-names = "csr", "cfg"; - ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ - 0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000 /* mem */ - 0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */ - dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 - 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4 - 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4 - 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x4 - 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x4>; - dma-coherent; - clocks = <&pcie0clk 0>; - msi-parent = <&v2m0>; - }; - - pcie1: pcie@1f2c0000 { - status = "disabled"; - device_type = "pci"; - compatible = "apm,xgene-pcie", "apm,xgene2-pcie"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ - 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ - reg-names = "csr", "cfg"; - ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ - 0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000 /* mem */ - 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ - dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 - 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4 - 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4 - 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x4 - 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x4>; - dma-coherent; - clocks = <&pcie1clk 0>; - msi-parent = <&v2m0>; - }; - - sata1: sata@1a000000 { - compatible = "apm,xgene-ahci-v2"; - reg = <0x0 0x1a000000 0x0 0x1000>, - <0x0 0x1f200000 0x0 0x1000>, - <0x0 0x1f20d000 0x0 0x1000>, - <0x0 0x1f20e000 0x0 0x1000>; - interrupts = <0x0 0x5a 0x4>; - dma-coherent; - }; - - sata2: sata@1a200000 { - compatible = "apm,xgene-ahci-v2"; - reg = <0x0 0x1a200000 0x0 0x1000>, - <0x0 0x1f210000 0x0 0x1000>, - <0x0 0x1f21d000 0x0 0x1000>, - <0x0 0x1f21e000 0x0 0x1000>; - interrupts = <0x0 0x5b 0x4>; - dma-coherent; - }; - - sata3: sata@1a400000 { - compatible = "apm,xgene-ahci-v2"; - reg = <0x0 0x1a400000 0x0 0x1000>, - <0x0 0x1f220000 0x0 0x1000>, - <0x0 0x1f22d000 0x0 0x1000>, - <0x0 0x1f22e000 0x0 0x1000>; - interrupts = <0x0 0x5c 0x4>; - dma-coherent; - }; - - mmc0: mmc@1c000000 { - compatible = "arasan,sdhci-4.9a"; - reg = <0x0 0x1c000000 0x0 0x100>; - interrupts = <0x0 0x49 0x4>; - dma-coherent; - no-1-8-v; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&sdioclk 0>, <&ahbclk 0>; - }; - - gfcgpio: gpio@1f63c000 { - compatible = "apm,xgene-gpio"; - reg = <0x0 0x1f63c000 0x0 0x40>; - gpio-controller; - #gpio-cells = <2>; - }; - - dwgpio: gpio@1c024000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0 0x1c024000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - }; - }; - - sbgpio: gpio@17001000{ - compatible = "apm,xgene-gpio-sb"; - reg = <0x0 0x17001000 0x0 0x400>; - #gpio-cells = <2>; - gpio-controller; - interrupts = <0x0 0x28 0x1>, - <0x0 0x29 0x1>, - <0x0 0x2a 0x1>, - <0x0 0x2b 0x1>, - <0x0 0x2c 0x1>, - <0x0 0x2d 0x1>, - <0x0 0x2e 0x1>, - <0x0 0x2f 0x1>; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - interrupt-controller; - apm,nr-gpios = <22>; - apm,nr-irqs = <8>; - apm,irq-start = <8>; - }; - - mdio: mdio@1f610000 { - compatible = "apm,xgene-mdio-xfi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x1f610000 0x0 0xd100>; - clocks = <&xge0clk 0>; - }; - - sgenet0: ethernet@1f610000 { - compatible = "apm,xgene2-sgenet"; - status = "disabled"; - reg = <0x0 0x1f610000 0x0 0xd100>, - <0x0 0x1f600000 0x0 0xd100>, - <0x0 0x20000000 0x0 0x20000>; - interrupts = <0 96 4>, - <0 97 4>; - dma-coherent; - clocks = <&xge0clk 0>; - local-mac-address = [00 01 73 00 00 01]; - phy-connection-type = "sgmii"; - phy-handle = <&sgenet0phy>; - }; - - xgenet1: ethernet@1f620000 { - compatible = "apm,xgene2-xgenet"; - status = "disabled"; - reg = <0x0 0x1f620000 0x0 0x10000>, - <0x0 0x1f600000 0x0 0xd100>, - <0x0 0x20000000 0x0 0x220000>; - interrupts = <0 108 4>, - <0 109 4>, - <0 110 4>, - <0 111 4>, - <0 112 4>, - <0 113 4>, - <0 114 4>, - <0 115 4>; - channel = <12>; - port-id = <1>; - dma-coherent; - clocks = <&xge1clk 0>; - local-mac-address = [00 01 73 00 00 02]; - phy-connection-type = "xgmii"; - }; - - rng: rng@10520000 { - compatible = "apm,xgene-rng"; - reg = <0x0 0x10520000 0x0 0x100>; - interrupts = <0x0 0x41 0x4>; - clocks = <&rngpkaclk 0>; - }; - - i2c1: i2c@10511000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x0 0x10511000 0x0 0x1000>; - interrupts = <0 0x45 0x4>; - #clock-cells = <1>; - clocks = <&sbapbclk 0>; - bus_num = <1>; - }; - - i2c4: i2c@10640000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x0 0x10640000 0x0 0x1000>; - interrupts = <0 0x3a 0x4>; - clocks = <&i2c4clk 0>; - bus_num = <4>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi deleted file mode 100644 index 0f37e77f5..000000000 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ /dev/null @@ -1,1098 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * dts file for AppliedMicro (APM) X-Gene Storm SOC - * - * Copyright (C) 2013, Applied Micro Circuits Corporation - */ - -/ { - compatible = "apm,xgene-storm"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "apm,potenza"; - reg = <0x0 0x000>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "apm,potenza"; - reg = <0x0 0x001>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_0>; - }; - cpu@100 { - device_type = "cpu"; - compatible = "apm,potenza"; - reg = <0x0 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_1>; - }; - cpu@101 { - device_type = "cpu"; - compatible = "apm,potenza"; - reg = <0x0 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_1>; - }; - cpu@200 { - device_type = "cpu"; - compatible = "apm,potenza"; - reg = <0x0 0x200>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_2>; - }; - cpu@201 { - device_type = "cpu"; - compatible = "apm,potenza"; - reg = <0x0 0x201>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_2>; - }; - cpu@300 { - device_type = "cpu"; - compatible = "apm,potenza"; - reg = <0x0 0x300>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_3>; - }; - cpu@301 { - device_type = "cpu"; - compatible = "apm,potenza"; - reg = <0x0 0x301>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - next-level-cache = <&xgene_L2_3>; - }; - xgene_L2_0: l2-cache-0 { - compatible = "cache"; - }; - xgene_L2_1: l2-cache-1 { - compatible = "cache"; - }; - xgene_L2_2: l2-cache-2 { - compatible = "cache"; - }; - xgene_L2_3: l2-cache-3 { - compatible = "cache"; - }; - }; - - gic: interrupt-controller@78010000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */ - <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */ - <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */ - <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */ - interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 0 0xff08>, /* Secure Phys IRQ */ - <1 13 0xff08>, /* Non-secure Phys IRQ */ - <1 14 0xff08>, /* Virt IRQ */ - <1 15 0xff08>; /* Hyp IRQ */ - clock-frequency = <50000000>; - }; - - pmu { - compatible = "apm,potenza-pmu", "arm,armv8-pmuv3"; - interrupts = <1 12 0xff04>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>; - - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; - refclk: refclk { - compatible = "fixed-clock"; - #clock-cells = <1>; - clock-frequency = <100000000>; - clock-output-names = "refclk"; - }; - - pcppll: pcppll@17000100 { - compatible = "apm,xgene-pcppll-clock"; - #clock-cells = <1>; - clocks = <&refclk 0>; - clock-names = "pcppll"; - reg = <0x0 0x17000100 0x0 0x1000>; - clock-output-names = "pcppll"; - type = <0>; - }; - - socpll: socpll@17000120 { - compatible = "apm,xgene-socpll-clock"; - #clock-cells = <1>; - clocks = <&refclk 0>; - clock-names = "socpll"; - reg = <0x0 0x17000120 0x0 0x1000>; - clock-output-names = "socpll"; - type = <1>; - }; - - socplldiv2: socplldiv2 { - compatible = "fixed-factor-clock"; - #clock-cells = <1>; - clocks = <&socpll 0>; - clock-names = "socplldiv2"; - clock-mult = <1>; - clock-div = <2>; - clock-output-names = "socplldiv2"; - }; - - ahbclk: ahbclk@17000000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x17000000 0x0 0x2000>; - reg-names = "div-reg"; - divider-offset = <0x164>; - divider-width = <0x5>; - divider-shift = <0x0>; - clock-output-names = "ahbclk"; - }; - - sdioclk: sdioclk@1f2ac000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f2ac000 0x0 0x1000 - 0x0 0x17000000 0x0 0x2000>; - reg-names = "csr-reg", "div-reg"; - csr-offset = <0x0>; - csr-mask = <0x2>; - enable-offset = <0x8>; - enable-mask = <0x2>; - divider-offset = <0x178>; - divider-width = <0x8>; - divider-shift = <0x0>; - clock-output-names = "sdioclk"; - }; - - ethclk: ethclk { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - clock-names = "ethclk"; - reg = <0x0 0x17000000 0x0 0x1000>; - reg-names = "div-reg"; - divider-offset = <0x238>; - divider-width = <0x9>; - divider-shift = <0x0>; - clock-output-names = "ethclk"; - }; - - menetclk: menetclk { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <ðclk 0>; - reg = <0x0 0x1702c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "menetclk"; - }; - - sge0clk: sge0clk@1f21c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f21c000 0x0 0x1000>; - reg-names = "csr-reg"; - csr-mask = <0xa>; - enable-mask = <0xf>; - clock-output-names = "sge0clk"; - }; - - xge0clk: xge0clk@1f61c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f61c000 0x0 0x1000>; - reg-names = "csr-reg"; - csr-mask = <0x3>; - clock-output-names = "xge0clk"; - }; - - xge1clk: xge1clk@1f62c000 { - compatible = "apm,xgene-device-clock"; - status = "disabled"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f62c000 0x0 0x1000>; - reg-names = "csr-reg"; - csr-mask = <0x3>; - clock-output-names = "xge1clk"; - }; - - sataphy1clk: sataphy1clk@1f21c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f21c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "sataphy1clk"; - status = "disabled"; - csr-offset = <0x4>; - csr-mask = <0x00>; - enable-offset = <0x0>; - enable-mask = <0x06>; - }; - - sataphy2clk: sataphy1clk@1f22c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f22c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "sataphy2clk"; - status = "ok"; - csr-offset = <0x4>; - csr-mask = <0x3a>; - enable-offset = <0x0>; - enable-mask = <0x06>; - }; - - sataphy3clk: sataphy1clk@1f23c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f23c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "sataphy3clk"; - status = "ok"; - csr-offset = <0x4>; - csr-mask = <0x3a>; - enable-offset = <0x0>; - enable-mask = <0x06>; - }; - - sata01clk: sata01clk@1f21c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f21c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "sata01clk"; - csr-offset = <0x4>; - csr-mask = <0x05>; - enable-offset = <0x0>; - enable-mask = <0x39>; - }; - - sata23clk: sata23clk@1f22c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f22c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "sata23clk"; - csr-offset = <0x4>; - csr-mask = <0x05>; - enable-offset = <0x0>; - enable-mask = <0x39>; - }; - - sata45clk: sata45clk@1f23c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f23c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "sata45clk"; - csr-offset = <0x4>; - csr-mask = <0x05>; - enable-offset = <0x0>; - enable-mask = <0x39>; - }; - - rtcclk: rtcclk@17000000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x17000000 0x0 0x2000>; - reg-names = "csr-reg"; - csr-offset = <0xc>; - csr-mask = <0x2>; - enable-offset = <0x10>; - enable-mask = <0x2>; - clock-output-names = "rtcclk"; - }; - - rngpkaclk: rngpkaclk@17000000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x17000000 0x0 0x2000>; - reg-names = "csr-reg"; - csr-offset = <0xc>; - csr-mask = <0x10>; - enable-offset = <0x10>; - enable-mask = <0x10>; - clock-output-names = "rngpkaclk"; - }; - - pcie0clk: pcie0clk@1f2bc000 { - status = "disabled"; - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f2bc000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "pcie0clk"; - }; - - pcie1clk: pcie1clk@1f2cc000 { - status = "disabled"; - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f2cc000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "pcie1clk"; - }; - - pcie2clk: pcie2clk@1f2dc000 { - status = "disabled"; - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f2dc000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "pcie2clk"; - }; - - pcie3clk: pcie3clk@1f50c000 { - status = "disabled"; - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f50c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "pcie3clk"; - }; - - pcie4clk: pcie4clk@1f51c000 { - status = "disabled"; - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f51c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "pcie4clk"; - }; - - dmaclk: dmaclk@1f27c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; - reg = <0x0 0x1f27c000 0x0 0x1000>; - reg-names = "csr-reg"; - clock-output-names = "dmaclk"; - }; - }; - - msi: msi@79000000 { - compatible = "apm,xgene1-msi"; - msi-controller; - reg = <0x00 0x79000000 0x0 0x900000>; - interrupts = < 0x0 0x10 0x4 - 0x0 0x11 0x4 - 0x0 0x12 0x4 - 0x0 0x13 0x4 - 0x0 0x14 0x4 - 0x0 0x15 0x4 - 0x0 0x16 0x4 - 0x0 0x17 0x4 - 0x0 0x18 0x4 - 0x0 0x19 0x4 - 0x0 0x1a 0x4 - 0x0 0x1b 0x4 - 0x0 0x1c 0x4 - 0x0 0x1d 0x4 - 0x0 0x1e 0x4 - 0x0 0x1f 0x4>; - }; - - scu: system-clk-controller@17000000 { - compatible = "apm,xgene-scu","syscon"; - reg = <0x0 0x17000000 0x0 0x400>; - }; - - reboot: reboot@17000014 { - compatible = "syscon-reboot"; - regmap = <&scu>; - offset = <0x14>; - mask = <0x1>; - }; - - csw: csw@7e200000 { - compatible = "apm,xgene-csw", "syscon"; - reg = <0x0 0x7e200000 0x0 0x1000>; - }; - - mcba: mcba@7e700000 { - compatible = "apm,xgene-mcb", "syscon"; - reg = <0x0 0x7e700000 0x0 0x1000>; - }; - - mcbb: mcbb@7e720000 { - compatible = "apm,xgene-mcb", "syscon"; - reg = <0x0 0x7e720000 0x0 0x1000>; - }; - - efuse: efuse@1054a000 { - compatible = "apm,xgene-efuse", "syscon"; - reg = <0x0 0x1054a000 0x0 0x20>; - }; - - rb: rb@7e000000 { - compatible = "apm,xgene-rb", "syscon"; - reg = <0x0 0x7e000000 0x0 0x10>; - }; - - edac@78800000 { - compatible = "apm,xgene-edac"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - regmap-csw = <&csw>; - regmap-mcba = <&mcba>; - regmap-mcbb = <&mcbb>; - regmap-efuse = <&efuse>; - regmap-rb = <&rb>; - reg = <0x0 0x78800000 0x0 0x100>; - interrupts = <0x0 0x20 0x4>, - <0x0 0x21 0x4>, - <0x0 0x27 0x4>; - - edacmc@7e800000 { - compatible = "apm,xgene-edac-mc"; - reg = <0x0 0x7e800000 0x0 0x1000>; - memory-controller = <0>; - }; - - edacmc@7e840000 { - compatible = "apm,xgene-edac-mc"; - reg = <0x0 0x7e840000 0x0 0x1000>; - memory-controller = <1>; - }; - - edacmc@7e880000 { - compatible = "apm,xgene-edac-mc"; - reg = <0x0 0x7e880000 0x0 0x1000>; - memory-controller = <2>; - }; - - edacmc@7e8c0000 { - compatible = "apm,xgene-edac-mc"; - reg = <0x0 0x7e8c0000 0x0 0x1000>; - memory-controller = <3>; - }; - - edacpmd@7c000000 { - compatible = "apm,xgene-edac-pmd"; - reg = <0x0 0x7c000000 0x0 0x200000>; - pmd-controller = <0>; - }; - - edacpmd@7c200000 { - compatible = "apm,xgene-edac-pmd"; - reg = <0x0 0x7c200000 0x0 0x200000>; - pmd-controller = <1>; - }; - - edacpmd@7c400000 { - compatible = "apm,xgene-edac-pmd"; - reg = <0x0 0x7c400000 0x0 0x200000>; - pmd-controller = <2>; - }; - - edacpmd@7c600000 { - compatible = "apm,xgene-edac-pmd"; - reg = <0x0 0x7c600000 0x0 0x200000>; - pmd-controller = <3>; - }; - - edacl3@7e600000 { - compatible = "apm,xgene-edac-l3"; - reg = <0x0 0x7e600000 0x0 0x1000>; - }; - - edacsoc@7e930000 { - compatible = "apm,xgene-edac-soc-v1"; - reg = <0x0 0x7e930000 0x0 0x1000>; - }; - }; - - pmu: pmu@78810000 { - compatible = "apm,xgene-pmu-v2"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - regmap-csw = <&csw>; - regmap-mcba = <&mcba>; - regmap-mcbb = <&mcbb>; - reg = <0x0 0x78810000 0x0 0x1000>; - interrupts = <0x0 0x22 0x4>; - - pmul3c@7e610000 { - compatible = "apm,xgene-pmu-l3c"; - reg = <0x0 0x7e610000 0x0 0x1000>; - }; - - pmuiob@7e940000 { - compatible = "apm,xgene-pmu-iob"; - reg = <0x0 0x7e940000 0x0 0x1000>; - }; - - pmucmcb@7e710000 { - compatible = "apm,xgene-pmu-mcb"; - reg = <0x0 0x7e710000 0x0 0x1000>; - enable-bit-index = <0>; - }; - - pmucmcb@7e730000 { - compatible = "apm,xgene-pmu-mcb"; - reg = <0x0 0x7e730000 0x0 0x1000>; - enable-bit-index = <1>; - }; - - pmucmc@7e810000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e810000 0x0 0x1000>; - enable-bit-index = <0>; - }; - - pmucmc@7e850000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e850000 0x0 0x1000>; - enable-bit-index = <1>; - }; - - pmucmc@7e890000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e890000 0x0 0x1000>; - enable-bit-index = <2>; - }; - - pmucmc@7e8d0000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e8d0000 0x0 0x1000>; - enable-bit-index = <3>; - }; - }; - - pcie0: pcie@1f2b0000 { - status = "disabled"; - device_type = "pci"; - compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ - 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ - reg-names = "csr", "cfg"; - ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ - 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */ - 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */ - dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 - 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4 - 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4 - 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4 - 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>; - dma-coherent; - clocks = <&pcie0clk 0>; - msi-parent = <&msi>; - }; - - pcie1: pcie@1f2c0000 { - status = "disabled"; - device_type = "pci"; - compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ - 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */ - reg-names = "csr", "cfg"; - ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */ - 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */ - 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */ - dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 - 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4 - 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4 - 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4 - 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>; - dma-coherent; - clocks = <&pcie1clk 0>; - msi-parent = <&msi>; - }; - - pcie2: pcie@1f2d0000 { - status = "disabled"; - device_type = "pci"; - compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */ - 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */ - reg-names = "csr", "cfg"; - ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */ - 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */ - 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */ - dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 - 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4 - 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4 - 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4 - 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>; - dma-coherent; - clocks = <&pcie2clk 0>; - msi-parent = <&msi>; - }; - - pcie3: pcie@1f500000 { - status = "disabled"; - device_type = "pci"; - compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */ - 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ - reg-names = "csr", "cfg"; - ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ - 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */ - 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ - dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 - 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4 - 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4 - 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4 - 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>; - dma-coherent; - clocks = <&pcie3clk 0>; - msi-parent = <&msi>; - }; - - pcie4: pcie@1f510000 { - status = "disabled"; - device_type = "pci"; - compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */ - 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */ - reg-names = "csr", "cfg"; - ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ - 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */ - 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */ - dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 - 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4 - 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4 - 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4 - 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>; - dma-coherent; - clocks = <&pcie4clk 0>; - msi-parent = <&msi>; - }; - - mailbox: mailbox@10540000 { - compatible = "apm,xgene-slimpro-mbox"; - reg = <0x0 0x10540000 0x0 0xa000>; - #mbox-cells = <1>; - interrupts = <0x0 0x0 0x4>, - <0x0 0x1 0x4>, - <0x0 0x2 0x4>, - <0x0 0x3 0x4>, - <0x0 0x4 0x4>, - <0x0 0x5 0x4>, - <0x0 0x6 0x4>, - <0x0 0x7 0x4>; - }; - - i2cslimpro { - compatible = "apm,xgene-slimpro-i2c"; - mboxes = <&mailbox 0>; - }; - - hwmonslimpro { - compatible = "apm,xgene-slimpro-hwmon"; - mboxes = <&mailbox 7>; - }; - - serial0: serial@1c020000 { - status = "disabled"; - device_type = "serial"; - compatible = "ns16550a"; - reg = <0 0x1c020000 0x0 0x1000>; - reg-shift = <2>; - clock-frequency = <10000000>; /* Updated by bootloader */ - interrupt-parent = <&gic>; - interrupts = <0x0 0x4c 0x4>; - }; - - serial1: serial@1c021000 { - status = "disabled"; - device_type = "serial"; - compatible = "ns16550a"; - reg = <0 0x1c021000 0x0 0x1000>; - reg-shift = <2>; - clock-frequency = <10000000>; /* Updated by bootloader */ - interrupt-parent = <&gic>; - interrupts = <0x0 0x4d 0x4>; - }; - - serial2: serial@1c022000 { - status = "disabled"; - device_type = "serial"; - compatible = "ns16550a"; - reg = <0 0x1c022000 0x0 0x1000>; - reg-shift = <2>; - clock-frequency = <10000000>; /* Updated by bootloader */ - interrupt-parent = <&gic>; - interrupts = <0x0 0x4e 0x4>; - }; - - serial3: serial@1c023000 { - status = "disabled"; - device_type = "serial"; - compatible = "ns16550a"; - reg = <0 0x1c023000 0x0 0x1000>; - reg-shift = <2>; - clock-frequency = <10000000>; /* Updated by bootloader */ - interrupt-parent = <&gic>; - interrupts = <0x0 0x4f 0x4>; - }; - - mmc0: mmc@1c000000 { - compatible = "arasan,sdhci-4.9a"; - reg = <0x0 0x1c000000 0x0 0x100>; - interrupts = <0x0 0x49 0x4>; - dma-coherent; - no-1-8-v; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&sdioclk 0>, <&ahbclk 0>; - }; - - gfcgpio: gpio0@1701c000 { - compatible = "apm,xgene-gpio"; - reg = <0x0 0x1701c000 0x0 0x40>; - gpio-controller; - #gpio-cells = <2>; - }; - - dwgpio: gpio@1c024000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0 0x1c024000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - }; - }; - - i2c0: i2c@10512000 { - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x0 0x10512000 0x0 0x1000>; - interrupts = <0 0x44 0x4>; - #clock-cells = <1>; - clocks = <&ahbclk 0>; - bus_num = <0>; - }; - - phy1: phy@1f21a000 { - compatible = "apm,xgene-phy"; - reg = <0x0 0x1f21a000 0x0 0x100>; - #phy-cells = <1>; - clocks = <&sataphy1clk 0>; - status = "disabled"; - apm,tx-boost-gain = <30 30 30 30 30 30>; - apm,tx-eye-tuning = <2 10 10 2 10 10>; - }; - - phy2: phy@1f22a000 { - compatible = "apm,xgene-phy"; - reg = <0x0 0x1f22a000 0x0 0x100>; - #phy-cells = <1>; - clocks = <&sataphy2clk 0>; - status = "ok"; - apm,tx-boost-gain = <30 30 30 30 30 30>; - apm,tx-eye-tuning = <1 10 10 2 10 10>; - }; - - phy3: phy@1f23a000 { - compatible = "apm,xgene-phy"; - reg = <0x0 0x1f23a000 0x0 0x100>; - #phy-cells = <1>; - clocks = <&sataphy3clk 0>; - status = "ok"; - apm,tx-boost-gain = <31 31 31 31 31 31>; - apm,tx-eye-tuning = <2 10 10 2 10 10>; - }; - - sata1: sata@1a000000 { - compatible = "apm,xgene-ahci"; - reg = <0x0 0x1a000000 0x0 0x1000>, - <0x0 0x1f210000 0x0 0x1000>, - <0x0 0x1f21d000 0x0 0x1000>, - <0x0 0x1f21e000 0x0 0x1000>, - <0x0 0x1f217000 0x0 0x1000>; - interrupts = <0x0 0x86 0x4>; - dma-coherent; - status = "disabled"; - clocks = <&sata01clk 0>; - phys = <&phy1 0>; - phy-names = "sata-phy"; - }; - - sata2: sata@1a400000 { - compatible = "apm,xgene-ahci"; - reg = <0x0 0x1a400000 0x0 0x1000>, - <0x0 0x1f220000 0x0 0x1000>, - <0x0 0x1f22d000 0x0 0x1000>, - <0x0 0x1f22e000 0x0 0x1000>, - <0x0 0x1f227000 0x0 0x1000>; - interrupts = <0x0 0x87 0x4>; - dma-coherent; - status = "ok"; - clocks = <&sata23clk 0>; - phys = <&phy2 0>; - phy-names = "sata-phy"; - }; - - sata3: sata@1a800000 { - compatible = "apm,xgene-ahci"; - reg = <0x0 0x1a800000 0x0 0x1000>, - <0x0 0x1f230000 0x0 0x1000>, - <0x0 0x1f23d000 0x0 0x1000>, - <0x0 0x1f23e000 0x0 0x1000>; - interrupts = <0x0 0x88 0x4>; - dma-coherent; - status = "ok"; - clocks = <&sata45clk 0>; - phys = <&phy3 0>; - phy-names = "sata-phy"; - }; - - /* Do not change dwusb name, coded for backward compatibility */ - usb0: dwusb@19000000 { - status = "disabled"; - compatible = "snps,dwc3"; - reg = <0x0 0x19000000 0x0 0x100000>; - interrupts = <0x0 0x89 0x4>; - dma-coherent; - dr_mode = "host"; - }; - - usb1: dwusb@19800000 { - status = "disabled"; - compatible = "snps,dwc3"; - reg = <0x0 0x19800000 0x0 0x100000>; - interrupts = <0x0 0x8a 0x4>; - dma-coherent; - dr_mode = "host"; - }; - - sbgpio: gpio@17001000{ - compatible = "apm,xgene-gpio-sb"; - reg = <0x0 0x17001000 0x0 0x400>; - #gpio-cells = <2>; - gpio-controller; - interrupts = <0x0 0x28 0x1>, - <0x0 0x29 0x1>, - <0x0 0x2a 0x1>, - <0x0 0x2b 0x1>, - <0x0 0x2c 0x1>, - <0x0 0x2d 0x1>; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - interrupt-controller; - }; - - rtc: rtc@10510000 { - compatible = "apm,xgene-rtc"; - reg = <0x0 0x10510000 0x0 0x400>; - interrupts = <0x0 0x46 0x4>; - #clock-cells = <1>; - clocks = <&rtcclk 0>; - }; - - mdio: mdio@17020000 { - compatible = "apm,xgene-mdio-rgmii"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x17020000 0x0 0xd100>; - clocks = <&menetclk 0>; - }; - - menet: ethernet@17020000 { - compatible = "apm,xgene-enet"; - status = "disabled"; - reg = <0x0 0x17020000 0x0 0xd100>, - <0x0 0x17030000 0x0 0xc300>, - <0x0 0x10000000 0x0 0x200>; - reg-names = "enet_csr", "ring_csr", "ring_cmd"; - interrupts = <0x0 0x3c 0x4>; - dma-coherent; - clocks = <&menetclk 0>; - /* mac address will be overwritten by the bootloader */ - local-mac-address = [00 00 00 00 00 00]; - phy-connection-type = "rgmii"; - phy-handle = <&menetphy>,<&menet0phy>; - mdio { - compatible = "apm,xgene-mdio"; - #address-cells = <1>; - #size-cells = <0>; - menetphy: menetphy@3 { - compatible = "ethernet-phy-id001c.c915"; - reg = <0x3>; - }; - - }; - }; - - sgenet0: ethernet@1f210000 { - compatible = "apm,xgene1-sgenet"; - status = "disabled"; - reg = <0x0 0x1f210000 0x0 0xd100>, - <0x0 0x1f200000 0x0 0xc300>, - <0x0 0x1b000000 0x0 0x200>; - reg-names = "enet_csr", "ring_csr", "ring_cmd"; - interrupts = <0x0 0xa0 0x4>, - <0x0 0xa1 0x4>; - dma-coherent; - clocks = <&sge0clk 0>; - local-mac-address = [00 00 00 00 00 00]; - phy-connection-type = "sgmii"; - phy-handle = <&sgenet0phy>; - }; - - sgenet1: ethernet@1f210030 { - compatible = "apm,xgene1-sgenet"; - status = "disabled"; - reg = <0x0 0x1f210030 0x0 0xd100>, - <0x0 0x1f200000 0x0 0xc300>, - <0x0 0x1b000000 0x0 0x8000>; - reg-names = "enet_csr", "ring_csr", "ring_cmd"; - interrupts = <0x0 0xac 0x4>, - <0x0 0xad 0x4>; - port-id = <1>; - dma-coherent; - local-mac-address = [00 00 00 00 00 00]; - phy-connection-type = "sgmii"; - phy-handle = <&sgenet1phy>; - }; - - xgenet: ethernet@1f610000 { - compatible = "apm,xgene1-xgenet"; - status = "disabled"; - reg = <0x0 0x1f610000 0x0 0xd100>, - <0x0 0x1f600000 0x0 0xc300>, - <0x0 0x18000000 0x0 0x200>; - reg-names = "enet_csr", "ring_csr", "ring_cmd"; - interrupts = <0x0 0x60 0x4>, - <0x0 0x61 0x4>, - <0x0 0x62 0x4>, - <0x0 0x63 0x4>, - <0x0 0x64 0x4>, - <0x0 0x65 0x4>, - <0x0 0x66 0x4>, - <0x0 0x67 0x4>; - channel = <0>; - dma-coherent; - clocks = <&xge0clk 0>; - /* mac address will be overwritten by the bootloader */ - local-mac-address = [00 00 00 00 00 00]; - phy-connection-type = "xgmii"; - }; - - xgenet1: ethernet@1f620000 { - compatible = "apm,xgene1-xgenet"; - status = "disabled"; - reg = <0x0 0x1f620000 0x0 0xd100>, - <0x0 0x1f600000 0x0 0xc300>, - <0x0 0x18000000 0x0 0x8000>; - reg-names = "enet_csr", "ring_csr", "ring_cmd"; - interrupts = <0x0 0x6c 0x4>, - <0x0 0x6d 0x4>; - port-id = <1>; - dma-coherent; - clocks = <&xge1clk 0>; - /* mac address will be overwritten by the bootloader */ - local-mac-address = [00 00 00 00 00 00]; - phy-connection-type = "xgmii"; - }; - - rng: rng@10520000 { - compatible = "apm,xgene-rng"; - reg = <0x0 0x10520000 0x0 0x100>; - interrupts = <0x0 0x41 0x4>; - clocks = <&rngpkaclk 0>; - }; - - dma: dma@1f270000 { - compatible = "apm,xgene-storm-dma"; - device_type = "dma"; - reg = <0x0 0x1f270000 0x0 0x10000>, - <0x0 0x1f200000 0x0 0x10000>, - <0x0 0x1b000000 0x0 0x400000>, - <0x0 0x1054a000 0x0 0x100>; - interrupts = <0x0 0x82 0x4>, - <0x0 0xb8 0x4>, - <0x0 0xb9 0x4>, - <0x0 0xba 0x4>, - <0x0 0xbb 0x4>; - dma-coherent; - clocks = <&dmaclk 0>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile deleted file mode 100644 index 800da2e84..000000000 --- a/arch/arm64/boot/dts/arm/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_VEXPRESS) += \ - foundation-v8.dtb foundation-v8-psci.dtb \ - foundation-v8-gicv3.dtb foundation-v8-gicv3-psci.dtb -dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb -dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb -dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb -dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi b/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi deleted file mode 100644 index 655fdcce1..000000000 --- a/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -/* - * ARM Ltd. - * - * ARMv8 Foundation model DTS (GICv2 configuration) - */ - -/ { - gic: interrupt-controller@2c001000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - #address-cells = <1>; - interrupt-controller; - reg = <0x0 0x2c001000 0 0x1000>, - <0x0 0x2c002000 0 0x2000>, - <0x0 0x2c004000 0 0x2000>, - <0x0 0x2c006000 0 0x2000>; - interrupts = ; - }; -}; diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv3-psci.dts b/arch/arm64/boot/dts/arm/foundation-v8-gicv3-psci.dts deleted file mode 100644 index e096e670b..000000000 --- a/arch/arm64/boot/dts/arm/foundation-v8-gicv3-psci.dts +++ /dev/null @@ -1,9 +0,0 @@ -/* - * ARM Ltd. - * - * ARMv8 Foundation model DTS (GICv3+PSCI configuration) - */ - -#include "foundation-v8.dtsi" -#include "foundation-v8-gicv3.dtsi" -#include "foundation-v8-psci.dtsi" diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dts b/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dts deleted file mode 100644 index c87380e87..000000000 --- a/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dts +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. - * - * ARMv8 Foundation model DTS (GICv3 configuration) - */ - -#include "foundation-v8.dtsi" -#include "foundation-v8-gicv3.dtsi" -#include "foundation-v8-spin-table.dtsi" diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi b/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi deleted file mode 100644 index e4a3c7dbc..000000000 --- a/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi +++ /dev/null @@ -1,29 +0,0 @@ -/* - * ARM Ltd. - * - * ARMv8 Foundation model DTS (GICv3 configuration) - */ - -/ { - gic: interrupt-controller@2f000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x2f000000 0x100000>; - interrupt-controller; - reg = <0x0 0x2f000000 0x0 0x10000>, - <0x0 0x2f100000 0x0 0x200000>, - <0x0 0x2c000000 0x0 0x2000>, - <0x0 0x2c010000 0x0 0x2000>, - <0x0 0x2c02f000 0x0 0x2000>; - interrupts = ; - - its: msi-controller@2f020000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x20000 0x20000>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/arm/foundation-v8-psci.dts b/arch/arm64/boot/dts/arm/foundation-v8-psci.dts deleted file mode 100644 index 723f23c7c..000000000 --- a/arch/arm64/boot/dts/arm/foundation-v8-psci.dts +++ /dev/null @@ -1,9 +0,0 @@ -/* - * ARM Ltd. - * - * ARMv8 Foundation model DTS (GICv2+PSCI configuration) - */ - -#include "foundation-v8.dtsi" -#include "foundation-v8-gicv2.dtsi" -#include "foundation-v8-psci.dtsi" diff --git a/arch/arm64/boot/dts/arm/foundation-v8-psci.dtsi b/arch/arm64/boot/dts/arm/foundation-v8-psci.dtsi deleted file mode 100644 index 16cdf3957..000000000 --- a/arch/arm64/boot/dts/arm/foundation-v8-psci.dtsi +++ /dev/null @@ -1,28 +0,0 @@ -/* - * ARM Ltd. - * - * ARMv8 Foundation model DTS (PSCI configuration) - */ - -/ { - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; -}; - -&cpu0 { - enable-method = "psci"; -}; - -&cpu1 { - enable-method = "psci"; -}; - -&cpu2 { - enable-method = "psci"; -}; - -&cpu3 { - enable-method = "psci"; -}; diff --git a/arch/arm64/boot/dts/arm/foundation-v8-spin-table.dtsi b/arch/arm64/boot/dts/arm/foundation-v8-spin-table.dtsi deleted file mode 100644 index 4d4186ba0..000000000 --- a/arch/arm64/boot/dts/arm/foundation-v8-spin-table.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -/* - * ARM Ltd. - * - * ARMv8 Foundation model DTS (spin table configuration) - */ - -&cpu0 { - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; -}; - -&cpu1 { - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; -}; - -&cpu2 { - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; -}; - -&cpu3 { - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; -}; diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dts b/arch/arm64/boot/dts/arm/foundation-v8.dts deleted file mode 100644 index b17347d75..000000000 --- a/arch/arm64/boot/dts/arm/foundation-v8.dts +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. - * - * ARMv8 Foundation model DTS (GICv2 configuration) - */ - -#include "foundation-v8.dtsi" -#include "foundation-v8-gicv2.dtsi" -#include "foundation-v8-spin-table.dtsi" diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi deleted file mode 100644 index 05ae893d1..000000000 --- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi +++ /dev/null @@ -1,231 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. - * - * ARMv8 Foundation model DTS - */ - -/dts-v1/; - -#include - -/memreserve/ 0x80000000 0x00010000; - -/ { - model = "Foundation-v8A"; - compatible = "arm,foundation-aarch64", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x0>; - next-level-cache = <&L2_0>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x1>; - next-level-cache = <&L2_0>; - }; - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x2>; - next-level-cache = <&L2_0>; - }; - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x3>; - next-level-cache = <&L2_0>; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x80000000>, - <0x00000008 0x80000000 0 0x80000000>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - clock-frequency = <100000000>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - }; - - watchdog@2a440000 { - compatible = "arm,sbsa-gwdt"; - reg = <0x0 0x2a440000 0 0x1000>, - <0x0 0x2a450000 0 0x1000>; - interrupts = ; - timeout-sec = <30>; - }; - - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - bus@8000000 { - compatible = "arm,vexpress,v2m-p1", "simple-bus"; - arm,v2m-memory-map = "rs1"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <0 0 8 &gic 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <0 0 9 &gic 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <0 0 10 &gic 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <0 0 11 &gic 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <0 0 12 &gic 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <0 0 13 &gic 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <0 0 14 &gic 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <0 0 15 &gic 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <0 0 16 &gic 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <0 0 17 &gic 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <0 0 18 &gic 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <0 0 19 &gic 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <0 0 20 &gic 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <0 0 21 &gic 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <0 0 22 &gic 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <0 0 23 &gic 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, - <0 0 24 &gic 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <0 0 25 &gic 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <0 0 26 &gic 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <0 0 27 &gic 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <0 0 28 &gic 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, - <0 0 29 &gic 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, - <0 0 30 &gic 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <0 0 31 &gic 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <0 0 32 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, - <0 0 33 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <0 0 34 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, - <0 0 35 &gic 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, - <0 0 36 &gic 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, - <0 0 37 &gic 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, - <0 0 38 &gic 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, - <0 0 39 &gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, - <0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, - <0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - - ethernet@202000000 { - compatible = "smsc,lan91c111"; - reg = <2 0x02000000 0x10000>; - interrupts = <15>; - }; - - iofpga-bus@300000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 3 0 0x200000>; - - v2m_sysreg: sysreg@10000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x010000 0x1000>; - }; - - v2m_serial0: serial@90000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x090000 0x1000>; - interrupts = <5>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial1: serial@a0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a0000 0x1000>; - interrupts = <6>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial2: serial@b0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b0000 0x1000>; - interrupts = <7>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial3: serial@c0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c0000 0x1000>; - interrupts = <8>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - virtio-block@130000 { - compatible = "virtio,mmio"; - reg = <0x130000 0x200>; - interrupts = <42>; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts deleted file mode 100644 index ca1bda14d..000000000 --- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts +++ /dev/null @@ -1,270 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Fast Models - * - * Architecture Envelope Model (AEM) ARMv8-A - * ARMAEMv8AMPCT - * - * FVP Base RevC - */ - -/dts-v1/; - -#include - -/memreserve/ 0x80000000 0x00010000; - -#include "rtsm_ve-motherboard.dtsi" -#include "rtsm_ve-motherboard-rs2.dtsi" - -/ { - model = "FVP Base RevC"; - compatible = "arm,fvp-base-revc", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x000>; - enable-method = "psci"; - }; - cpu1: cpu@100 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x100>; - enable-method = "psci"; - }; - cpu2: cpu@200 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x200>; - enable-method = "psci"; - }; - cpu3: cpu@300 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x300>; - enable-method = "psci"; - }; - cpu4: cpu@10000 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x10000>; - enable-method = "psci"; - }; - cpu5: cpu@10100 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x10100>; - enable-method = "psci"; - }; - cpu6: cpu@10200 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x10200>; - enable-method = "psci"; - }; - cpu7: cpu@10300 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x10300>; - enable-method = "psci"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x80000000>, - <0x00000008 0x80000000 0 0x80000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* Chipselect 2,00000000 is physically at 0x18000000 */ - vram: vram@18000000 { - /* 8 MB of designated video RAM */ - compatible = "shared-dma-pool"; - reg = <0x00000000 0x18000000 0 0x00800000>; - no-map; - }; - }; - - gic: interrupt-controller@2f000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - reg = <0x0 0x2f000000 0 0x10000>, // GICD - <0x0 0x2f100000 0 0x200000>, // GICR - <0x0 0x2c000000 0 0x2000>, // GICC - <0x0 0x2c010000 0 0x2000>, // GICH - <0x0 0x2c02f000 0 0x2000>; // GICV - interrupts = ; - - its: msi-controller@2f020000 { - #msi-cells = <1>; - compatible = "arm,gic-v3-its"; - reg = <0x0 0x2f020000 0x0 0x20000>; // GITS - msi-controller; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - spe-pmu { - compatible = "arm,statistical-profiling-extension-v1"; - interrupts = ; - }; - - pci: pci@40000000 { - #address-cells = <0x3>; - #size-cells = <0x2>; - #interrupt-cells = <0x1>; - compatible = "pci-host-ecam-generic"; - device_type = "pci"; - bus-range = <0x0 0x1>; - reg = <0x0 0x40000000 0x0 0x10000000>; - ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>; - interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - msi-map = <0x0 &its 0x0 0x10000>; - iommu-map = <0x0 &smmu 0x0 0x10000>; - - dma-coherent; - ats-supported; - }; - - smmu: iommu@2b400000 { - compatible = "arm,smmu-v3"; - reg = <0x0 0x2b400000 0x0 0x100000>; - interrupts = , - , - , - ; - interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; - dma-coherent; - #iommu-cells = <1>; - msi-parent = <&its 0x10000>; - }; - - panel { - compatible = "arm,rtsm-display", "panel-dpi"; - port { - panel_in: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - - panel-timing { - clock-frequency = <63500127>; - hactive = <1024>; - hback-porch = <152>; - hfront-porch = <48>; - hsync-len = <104>; - vactive = <768>; - vback-porch = <23>; - vfront-porch = <3>; - vsync-len = <4>; - }; - }; - - bus@8000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, - <0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, - <0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, - <0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, - <0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, - <0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, - <0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, - <0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, - <0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, - <0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, - <0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, - <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, - <0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, - <0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; - }; -}; diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi deleted file mode 100644 index 2c0161125..000000000 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ /dev/null @@ -1,840 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "juno-clocks.dtsi" -#include "juno-motherboard.dtsi" - -/ { - /* - * Devices shared by all Juno boards - */ - - memtimer: timer@2a810000 { - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x2a810000 0x0 0x10000>; - clock-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x2a820000 0x20000>; - status = "disabled"; - frame@2a830000 { - frame-number = <1>; - interrupts = ; - reg = <0x10000 0x10000>; - }; - }; - - mailbox: mhu@2b1f0000 { - compatible = "arm,mhu", "arm,primecell"; - reg = <0x0 0x2b1f0000 0x0 0x1000>; - interrupts = , - ; - interrupt-names = "mhu_lpri_rx", - "mhu_hpri_rx"; - #mbox-cells = <1>; - clocks = <&soc_refclk100mhz>; - clock-names = "apb_pclk"; - }; - - smmu_gpu: iommu@2b400000 { - compatible = "arm,mmu-400", "arm,smmu-v1"; - reg = <0x0 0x2b400000 0x0 0x10000>; - interrupts = , - ; - #iommu-cells = <1>; - #global-interrupts = <1>; - power-domains = <&scpi_devpd 1>; - dma-coherent; - status = "disabled"; - }; - - smmu_pcie: iommu@2b500000 { - compatible = "arm,mmu-401", "arm,smmu-v1"; - reg = <0x0 0x2b500000 0x0 0x10000>; - interrupts = , - ; - #iommu-cells = <1>; - #global-interrupts = <1>; - dma-coherent; - status = "disabled"; - }; - - smmu_etr: iommu@2b600000 { - compatible = "arm,mmu-401", "arm,smmu-v1"; - reg = <0x0 0x2b600000 0x0 0x10000>; - interrupts = , - ; - #iommu-cells = <1>; - #global-interrupts = <1>; - dma-coherent; - power-domains = <&scpi_devpd 0>; - }; - - gic: interrupt-controller@2c010000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - reg = <0x0 0x2c010000 0 0x1000>, - <0x0 0x2c02f000 0 0x2000>, - <0x0 0x2c04f000 0 0x2000>, - <0x0 0x2c06f000 0 0x2000>; - #address-cells = <1>; - #interrupt-cells = <3>; - #size-cells = <1>; - interrupt-controller; - interrupts = ; - ranges = <0 0 0x2c1c0000 0x40000>; - - v2m_0: v2m@0 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0 0x10000>; - }; - - v2m@10000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x10000 0x10000>; - }; - - v2m@20000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x20000 0x10000>; - }; - - v2m@30000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x30000 0x10000>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - /* - * Juno TRMs specify the size for these coresight components as 64K. - * The actual size is just 4K though 64K is reserved. Access to the - * unmapped reserved region results in a DECERR response. - */ - etf@20010000 { /* etf0 */ - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x20010000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - - in-ports { - port { - etf0_in_port: endpoint { - remote-endpoint = <&main_funnel_out_port>; - }; - }; - }; - - out-ports { - port { - etf0_out_port: endpoint { - }; - }; - }; - }; - - tpiu@20030000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0 0x20030000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - in-ports { - port { - tpiu_in_port: endpoint { - remote-endpoint = <&replicator_out_port0>; - }; - }; - }; - }; - - /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/ - main_funnel: funnel@20040000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x20040000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - - out-ports { - port { - main_funnel_out_port: endpoint { - remote-endpoint = <&etf0_in_port>; - }; - }; - }; - - main_funnel_in_ports: in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - main_funnel_in_port0: endpoint { - remote-endpoint = <&cluster0_funnel_out_port>; - }; - }; - - port@1 { - reg = <1>; - main_funnel_in_port1: endpoint { - remote-endpoint = <&cluster1_funnel_out_port>; - }; - }; - }; - }; - - etr@20070000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x20070000 0 0x1000>; - iommus = <&smmu_etr 0>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - arm,scatter-gather; - in-ports { - port { - etr_in_port: endpoint { - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - }; - - stm@20100000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0 0x20100000 0 0x1000>, - <0 0x28000000 0 0x1000000>; - reg-names = "stm-base", "stm-stimulus-base"; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - out-ports { - port { - stm_out_port: endpoint { - }; - }; - }; - }; - - replicator@20120000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x20120000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&etr_in_port>; - }; - }; - }; - in-ports { - port { - replicator_in_port0: endpoint { - }; - }; - }; - }; - - cpu_debug0: cpu-debug@22010000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x0 0x22010000 0x0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - }; - - etm0: etm@22040000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x22040000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - out-ports { - port { - cluster0_etm0_out_port: endpoint { - remote-endpoint = <&cluster0_funnel_in_port0>; - }; - }; - }; - }; - - funnel@220c0000 { /* cluster0 funnel */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x220c0000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - out-ports { - port { - cluster0_funnel_out_port: endpoint { - remote-endpoint = <&main_funnel_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - cluster0_funnel_in_port0: endpoint { - remote-endpoint = <&cluster0_etm0_out_port>; - }; - }; - - port@1 { - reg = <1>; - cluster0_funnel_in_port1: endpoint { - remote-endpoint = <&cluster0_etm1_out_port>; - }; - }; - }; - }; - - cpu_debug1: cpu-debug@22110000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x0 0x22110000 0x0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - }; - - etm1: etm@22140000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x22140000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - out-ports { - port { - cluster0_etm1_out_port: endpoint { - remote-endpoint = <&cluster0_funnel_in_port1>; - }; - }; - }; - }; - - cpu_debug2: cpu-debug@23010000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x0 0x23010000 0x0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - }; - - etm2: etm@23040000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x23040000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - out-ports { - port { - cluster1_etm0_out_port: endpoint { - remote-endpoint = <&cluster1_funnel_in_port0>; - }; - }; - }; - }; - - funnel@230c0000 { /* cluster1 funnel */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x230c0000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - out-ports { - port { - cluster1_funnel_out_port: endpoint { - remote-endpoint = <&main_funnel_in_port1>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - cluster1_funnel_in_port0: endpoint { - remote-endpoint = <&cluster1_etm0_out_port>; - }; - }; - - port@1 { - reg = <1>; - cluster1_funnel_in_port1: endpoint { - remote-endpoint = <&cluster1_etm1_out_port>; - }; - }; - port@2 { - reg = <2>; - cluster1_funnel_in_port2: endpoint { - remote-endpoint = <&cluster1_etm2_out_port>; - }; - }; - port@3 { - reg = <3>; - cluster1_funnel_in_port3: endpoint { - remote-endpoint = <&cluster1_etm3_out_port>; - }; - }; - }; - }; - - cpu_debug3: cpu-debug@23110000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x0 0x23110000 0x0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - }; - - etm3: etm@23140000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x23140000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - out-ports { - port { - cluster1_etm1_out_port: endpoint { - remote-endpoint = <&cluster1_funnel_in_port1>; - }; - }; - }; - }; - - cpu_debug4: cpu-debug@23210000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x0 0x23210000 0x0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - }; - - etm4: etm@23240000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x23240000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - out-ports { - port { - cluster1_etm2_out_port: endpoint { - remote-endpoint = <&cluster1_funnel_in_port2>; - }; - }; - }; - }; - - cpu_debug5: cpu-debug@23310000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x0 0x23310000 0x0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - }; - - etm5: etm@23340000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x23340000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - out-ports { - port { - cluster1_etm3_out_port: endpoint { - remote-endpoint = <&cluster1_funnel_in_port3>; - }; - }; - }; - }; - - gpu: gpu@2d000000 { - compatible = "arm,juno-mali", "arm,mali-t624"; - reg = <0 0x2d000000 0 0x10000>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&scpi_dvfs 2>; - power-domains = <&scpi_devpd 1>; - dma-coherent; - /* The SMMU is only really of interest to bare-metal hypervisors */ - /* iommus = <&smmu_gpu 0>; */ - status = "disabled"; - }; - - sram: sram@2e000000 { - compatible = "arm,juno-sram-ns", "mmio-sram"; - reg = <0x0 0x2e000000 0x0 0x8000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x2e000000 0x8000>; - - cpu_scp_lpri: scp-sram@0 { - compatible = "arm,juno-scp-shmem"; - reg = <0x0 0x200>; - }; - - cpu_scp_hpri: scp-sram@200 { - compatible = "arm,juno-scp-shmem"; - reg = <0x200 0x200>; - }; - }; - - pcie_ctlr: pcie@40000000 { - compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic"; - device_type = "pci"; - reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */ - bus-range = <0 255>; - linux,pci-domain = <0>; - #address-cells = <3>; - #size-cells = <2>; - dma-coherent; - ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>, - <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>, - <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; - msi-parent = <&v2m_0>; - status = "disabled"; - iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */ - iommu-map = <0x0 &smmu_pcie 0x0 0x1>; - }; - - scpi { - compatible = "arm,scpi"; - mboxes = <&mailbox 1>; - shmem = <&cpu_scp_hpri>; - - clocks { - compatible = "arm,scpi-clocks"; - - scpi_dvfs: clocks-0 { - compatible = "arm,scpi-dvfs-clocks"; - #clock-cells = <1>; - clock-indices = <0>, <1>, <2>; - clock-output-names = "atlclk", "aplclk","gpuclk"; - }; - scpi_clk: clocks-1 { - compatible = "arm,scpi-variable-clocks"; - #clock-cells = <1>; - clock-indices = <3>; - clock-output-names = "pxlclk"; - }; - }; - - scpi_devpd: power-controller { - compatible = "arm,scpi-power-domains"; - num-domains = <2>; - #power-domain-cells = <1>; - }; - - scpi_sensors0: sensors { - compatible = "arm,scpi-sensors"; - #thermal-sensor-cells = <1>; - }; - }; - - thermal-zones { - pmic { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&scpi_sensors0 0>; - }; - - soc { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&scpi_sensors0 3>; - }; - - big_cluster_thermal_zone: big-cluster { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&scpi_sensors0 21>; - status = "disabled"; - }; - - little_cluster_thermal_zone: little-cluster { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&scpi_sensors0 22>; - status = "disabled"; - }; - - gpu0_thermal_zone: gpu0 { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&scpi_sensors0 23>; - status = "disabled"; - }; - - gpu1_thermal_zone: gpu1 { - polling-delay = <1000>; - polling-delay-passive = <100>; - thermal-sensors = <&scpi_sensors0 24>; - status = "disabled"; - }; - }; - - smmu_dma: iommu@7fb00000 { - compatible = "arm,mmu-401", "arm,smmu-v1"; - reg = <0x0 0x7fb00000 0x0 0x10000>; - interrupts = , - ; - #iommu-cells = <1>; - #global-interrupts = <1>; - dma-coherent; - status = "disabled"; - }; - - smmu_hdlcd1: iommu@7fb10000 { - compatible = "arm,mmu-401", "arm,smmu-v1"; - reg = <0x0 0x7fb10000 0x0 0x10000>; - interrupts = , - ; - #iommu-cells = <1>; - #global-interrupts = <1>; - }; - - smmu_hdlcd0: iommu@7fb20000 { - compatible = "arm,mmu-401", "arm,smmu-v1"; - reg = <0x0 0x7fb20000 0x0 0x10000>; - interrupts = , - ; - #iommu-cells = <1>; - #global-interrupts = <1>; - }; - - smmu_usb: iommu@7fb30000 { - compatible = "arm,mmu-401", "arm,smmu-v1"; - reg = <0x0 0x7fb30000 0x0 0x10000>; - interrupts = , - ; - #iommu-cells = <1>; - #global-interrupts = <1>; - dma-coherent; - }; - - dma@7ff00000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0x7ff00000 0 0x1000>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - interrupts = , - , - , - , - , - , - , - , - ; - iommus = <&smmu_dma 0>, - <&smmu_dma 1>, - <&smmu_dma 2>, - <&smmu_dma 3>, - <&smmu_dma 4>, - <&smmu_dma 5>, - <&smmu_dma 6>, - <&smmu_dma 7>, - <&smmu_dma 8>; - clocks = <&soc_faxiclk>; - clock-names = "apb_pclk"; - }; - - hdlcd@7ff50000 { - compatible = "arm,hdlcd"; - reg = <0 0x7ff50000 0 0x1000>; - interrupts = ; - iommus = <&smmu_hdlcd1 0>; - clocks = <&scpi_clk 3>; - clock-names = "pxlclk"; - - port { - hdlcd1_output: endpoint { - remote-endpoint = <&tda998x_1_input>; - }; - }; - }; - - hdlcd@7ff60000 { - compatible = "arm,hdlcd"; - reg = <0 0x7ff60000 0 0x1000>; - interrupts = ; - iommus = <&smmu_hdlcd0 0>; - clocks = <&scpi_clk 3>; - clock-names = "pxlclk"; - - port { - hdlcd0_output: endpoint { - remote-endpoint = <&tda998x_0_input>; - }; - }; - }; - - soc_uart0: serial@7ff80000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0x7ff80000 0x0 0x1000>; - interrupts = ; - clocks = <&soc_uartclk>, <&soc_refclk100mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - i2c@7ffa0000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x7ffa0000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <400000>; - i2c-sda-hold-time-ns = <500>; - clocks = <&soc_smc50mhz>; - - hdmi-transmitter@70 { - compatible = "nxp,tda998x"; - reg = <0x70>; - port { - tda998x_0_input: endpoint { - remote-endpoint = <&hdlcd0_output>; - }; - }; - }; - - hdmi-transmitter@71 { - compatible = "nxp,tda998x"; - reg = <0x71>; - port { - tda998x_1_input: endpoint { - remote-endpoint = <&hdlcd1_output>; - }; - }; - }; - }; - - usb@7ffb0000 { - compatible = "generic-ohci"; - reg = <0x0 0x7ffb0000 0x0 0x10000>; - interrupts = ; - iommus = <&smmu_usb 0>; - clocks = <&soc_usb48mhz>; - }; - - usb@7ffc0000 { - compatible = "generic-ehci"; - reg = <0x0 0x7ffc0000 0x0 0x10000>; - interrupts = ; - iommus = <&smmu_usb 0>; - clocks = <&soc_usb48mhz>; - }; - - memory-controller@7ffd0000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0 0x7ffd0000 0 0x1000>; - interrupts = , - ; - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - }; - - memory@80000000 { - device_type = "memory"; - /* last 16MB of the first memory area is reserved for secure world use by firmware */ - reg = <0x00000000 0x80000000 0x0 0x7f000000>, - <0x00000008 0x80000000 0x1 0x80000000>; - }; - - bus@8000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 15>; - interrupt-map = <0 0 0 &gic 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, - <0 0 1 &gic 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <0 0 2 &gic 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <0 0 3 &gic 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, - <0 0 4 &gic 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, - <0 0 5 &gic 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, - <0 0 6 &gic 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, - <0 0 7 &gic 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, - <0 0 8 &gic 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, - <0 0 9 &gic 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, - <0 0 10 &gic 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, - <0 0 11 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, - <0 0 12 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - }; - - site2: tlx-bus@60000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x60000000 0x10000000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0>; - interrupt-map = <0 0 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; - }; -}; diff --git a/arch/arm64/boot/dts/arm/juno-clocks.dtsi b/arch/arm64/boot/dts/arm/juno-clocks.dtsi deleted file mode 100644 index 2870b5eeb..000000000 --- a/arch/arm64/boot/dts/arm/juno-clocks.dtsi +++ /dev/null @@ -1,45 +0,0 @@ -/* - * ARM Juno Platform clocks - * - * Copyright (c) 2013-2014 ARM Ltd - * - * This file is licensed under a dual GPLv2 or BSD license. - * - */ -/ { - /* SoC fixed clocks */ - soc_uartclk: refclk7372800hz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <7372800>; - clock-output-names = "juno:uartclk"; - }; - - soc_usb48mhz: clk48mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - clock-output-names = "clk48mhz"; - }; - - soc_smc50mhz: clk50mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "smc_clk"; - }; - - soc_refclk100mhz: refclk100mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "apb_pclk"; - }; - - soc_faxiclk: refclk400mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <400000000>; - clock-output-names = "faxi_clk"; - }; -}; diff --git a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi deleted file mode 100644 index eda3d9e18..000000000 --- a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - funnel@20130000 { /* cssys1 */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x20130000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - out-ports { - port { - csys1_funnel_out_port: endpoint { - remote-endpoint = <&etf1_in_port>; - }; - }; - }; - in-ports { - port { - csys1_funnel_in_port0: endpoint { - }; - }; - - }; - }; - - etf@20140000 { /* etf1 */ - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x20140000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - in-ports { - port { - etf1_in_port: endpoint { - remote-endpoint = <&csys1_funnel_out_port>; - }; - }; - }; - out-ports { - port { - etf1_out_port: endpoint { - remote-endpoint = <&csys2_funnel_in_port1>; - }; - }; - }; - }; - - funnel@20150000 { /* cssys2 */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x20150000 0 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - power-domains = <&scpi_devpd 0>; - out-ports { - port { - csys2_funnel_out_port: endpoint { - remote-endpoint = <&replicator_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - csys2_funnel_in_port0: endpoint { - slave-mode; - remote-endpoint = <&etf0_out_port>; - }; - }; - - port@1 { - reg = <1>; - csys2_funnel_in_port1: endpoint { - slave-mode; - remote-endpoint = <&etf1_out_port>; - }; - }; - - }; - }; -}; diff --git a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi deleted file mode 100644 index 40d95c58b..000000000 --- a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi +++ /dev/null @@ -1,295 +0,0 @@ -/* - * ARM Juno Platform motherboard peripherals - * - * Copyright (c) 2013-2014 ARM Ltd - * - * This file is licensed under a dual GPLv2 or BSD license. - * - */ - -/ { - mb_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "juno_mb:clk24mhz"; - }; - - mb_clk25mhz: clk25mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "juno_mb:clk25mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "juno_mb:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "juno_mb:refclk32khz"; - }; - - mb_fixed_3v3: mcc-sb-3v3 { - compatible = "regulator-fixed"; - regulator-name = "MCC_SB_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power-button { - debounce-interval = <50>; - wakeup-source; - linux,code = <116>; - label = "POWER"; - gpios = <&iofpga_gpio0 0 0x4>; - }; - home-button { - debounce-interval = <50>; - wakeup-source; - linux,code = <102>; - label = "HOME"; - gpios = <&iofpga_gpio0 1 0x4>; - }; - rlock-button { - debounce-interval = <50>; - wakeup-source; - linux,code = <152>; - label = "RLOCK"; - gpios = <&iofpga_gpio0 2 0x4>; - }; - vol-up-button { - debounce-interval = <50>; - wakeup-source; - linux,code = <115>; - label = "VOL+"; - gpios = <&iofpga_gpio0 3 0x4>; - }; - vol-down-button { - debounce-interval = <50>; - wakeup-source; - linux,code = <114>; - label = "VOL-"; - gpios = <&iofpga_gpio0 4 0x4>; - }; - nmi-button { - debounce-interval = <50>; - wakeup-source; - linux,code = <99>; - label = "NMI"; - gpios = <&iofpga_gpio0 5 0x4>; - }; - }; - - bus@8000000 { - motherboard-bus { - compatible = "arm,vexpress,v2p-p1", "simple-bus"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - #interrupt-cells = <1>; - ranges; - model = "V2M-Juno"; - arm,hbi = <0x252>; - arm,vexpress,site = <0>; - arm,v2m-memory-map = "rs1"; - - flash@0 { - /* 2 * 32MiB NOR Flash memory mounted on CS0 */ - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>; - bank-width = <4>; - /* - * Unfortunately, accessing the flash disturbs - * the CPU idle states (suspend) and CPU - * hotplug of the platform. For this reason, - * flash hardware access is disabled by default. - */ - status = "disabled"; - partitions { - compatible = "arm,arm-firmware-suite"; - }; - }; - - ethernet@200000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <2 0x00000000 0x10000>; - interrupts = <3>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - clocks = <&mb_clk25mhz>; - vdd33a-supply = <&mb_fixed_3v3>; - vddvario-supply = <&mb_fixed_3v3>; - }; - - iofpga-bus@300000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 3 0 0x200000>; - - v2m_sysctl: sysctl@20000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x020000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; - assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; - assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; - }; - - apbregs@10000 { - compatible = "syscon", "simple-mfd"; - reg = <0x010000 0x1000>; - - led0 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x01>; - label = "vexpress:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led1 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x02>; - label = "vexpress:1"; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - led2 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x04>; - label = "vexpress:2"; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - led3 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x08>; - label = "vexpress:3"; - linux,default-trigger = "cpu1"; - default-state = "off"; - }; - led4 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x10>; - label = "vexpress:4"; - linux,default-trigger = "cpu2"; - default-state = "off"; - }; - led5 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x20>; - label = "vexpress:5"; - linux,default-trigger = "cpu3"; - default-state = "off"; - }; - led6 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x40>; - label = "vexpress:6"; - default-state = "off"; - }; - led7 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x80>; - label = "vexpress:7"; - default-state = "off"; - }; - }; - - mmci@50000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x050000 0x1000>; - interrupts = <5>; - /* cd-gpios = <&v2m_mmc_gpios 0 0>; - wp-gpios = <&v2m_mmc_gpios 1 0>; */ - max-frequency = <12000000>; - vmmc-supply = <&mb_fixed_3v3>; - clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; - clock-names = "mclk", "apb_pclk"; - }; - - kmi@60000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x060000 0x1000>; - interrupts = <8>; - clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi@70000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x070000 0x1000>; - interrupts = <8>; - clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - wdt@f0000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f0000 0x10000>; - interrupts = <7>; - clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - v2m_timer01: timer@110000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x110000 0x10000>; - interrupts = <9>; - clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - v2m_timer23: timer@120000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x120000 0x10000>; - interrupts = <9>; - clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - rtc@170000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x170000 0x10000>; - interrupts = <0>; - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - }; - - iofpga_gpio0: gpio@1d0000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x1d0000 0x1000>; - interrupts = <6>; - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts deleted file mode 100644 index 5f290090b..000000000 --- a/arch/arm64/boot/dts/arm/juno-r1.dts +++ /dev/null @@ -1,311 +0,0 @@ -/* - * ARM Ltd. Juno Platform - * - * Copyright (c) 2015 ARM Ltd. - * - * This file is licensed under a dual GPLv2 or BSD license. - */ - -/dts-v1/; - -#include -#include "juno-base.dtsi" -#include "juno-cs-r1r2.dtsi" - -/ { - model = "ARM Juno development board (r1)"; - compatible = "arm,juno-r1", "arm,juno", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &soc_uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&A57_0>; - }; - core1 { - cpu = <&A57_1>; - }; - }; - - cluster1 { - core0 { - cpu = <&A53_0>; - }; - core1 { - cpu = <&A53_1>; - }; - core2 { - cpu = <&A53_2>; - }; - core3 { - cpu = <&A53_3>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <300>; - exit-latency-us = <1200>; - min-residency-us = <2000>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x1010000>; - local-timer-stop; - entry-latency-us = <400>; - exit-latency-us = <1200>; - min-residency-us = <2500>; - }; - }; - - A57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0 0x0>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&A57_L2>; - clocks = <&scpi_dvfs 0>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - }; - - A57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x0 0x1>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&A57_L2>; - clocks = <&scpi_dvfs 0>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - }; - - A53_0: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x100>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <578>; - }; - - A53_1: cpu@101 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x101>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <578>; - }; - - A53_2: cpu@102 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x102>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <578>; - }; - - A53_3: cpu@103 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x103>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <578>; - }; - - A57_L2: l2-cache0 { - compatible = "cache"; - cache-size = <0x200000>; - cache-line-size = <64>; - cache-sets = <2048>; - }; - - A53_L2: l2-cache1 { - compatible = "cache"; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - }; - }; - - pmu-a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts = , - ; - interrupt-affinity = <&A57_0>, - <&A57_1>; - }; - - pmu-a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&A53_0>, - <&A53_1>, - <&A53_2>, - <&A53_3>; - }; -}; - -&memtimer { - status = "okay"; -}; - -&pcie_ctlr { - status = "okay"; -}; - -&etm0 { - cpu = <&A57_0>; -}; - -&etm1 { - cpu = <&A57_1>; -}; - -&etm2 { - cpu = <&A53_0>; -}; - -&etm3 { - cpu = <&A53_1>; -}; - -&etm4 { - cpu = <&A53_2>; -}; - -&etm5 { - cpu = <&A53_3>; -}; - -&big_cluster_thermal_zone { - status = "okay"; -}; - -&little_cluster_thermal_zone { - status = "okay"; -}; - -&gpu0_thermal_zone { - status = "okay"; -}; - -&gpu1_thermal_zone { - status = "okay"; -}; - -&etf0_out_port { - remote-endpoint = <&csys2_funnel_in_port0>; -}; - -&replicator_in_port0 { - remote-endpoint = <&csys2_funnel_out_port>; -}; - -&csys1_funnel_in_port0 { - remote-endpoint = <&stm_out_port>; -}; - -&stm_out_port { - remote-endpoint = <&csys1_funnel_in_port0>; -}; - -&cpu_debug0 { - cpu = <&A57_0>; -}; - -&cpu_debug1 { - cpu = <&A57_1>; -}; - -&cpu_debug2 { - cpu = <&A53_0>; -}; - -&cpu_debug3 { - cpu = <&A53_1>; -}; - -&cpu_debug4 { - cpu = <&A53_2>; -}; - -&cpu_debug5 { - cpu = <&A53_3>; -}; diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts deleted file mode 100644 index 305300dd5..000000000 --- a/arch/arm64/boot/dts/arm/juno-r2.dts +++ /dev/null @@ -1,317 +0,0 @@ -/* - * ARM Ltd. Juno Platform - * - * Copyright (c) 2015 ARM Ltd. - * - * This file is licensed under a dual GPLv2 or BSD license. - */ - -/dts-v1/; - -#include -#include "juno-base.dtsi" -#include "juno-cs-r1r2.dtsi" - -/ { - model = "ARM Juno development board (r2)"; - compatible = "arm,juno-r2", "arm,juno", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &soc_uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&A72_0>; - }; - core1 { - cpu = <&A72_1>; - }; - }; - - cluster1 { - core0 { - cpu = <&A53_0>; - }; - core1 { - cpu = <&A53_1>; - }; - core2 { - cpu = <&A53_2>; - }; - core3 { - cpu = <&A53_3>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <300>; - exit-latency-us = <1200>; - min-residency-us = <2000>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x1010000>; - local-timer-stop; - entry-latency-us = <400>; - exit-latency-us = <1200>; - min-residency-us = <2500>; - }; - }; - - A72_0: cpu@0 { - compatible = "arm,cortex-a72"; - reg = <0x0 0x0>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&A72_L2>; - clocks = <&scpi_dvfs 0>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <450>; - }; - - A72_1: cpu@1 { - compatible = "arm,cortex-a72"; - reg = <0x0 0x1>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&A72_L2>; - clocks = <&scpi_dvfs 0>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <450>; - }; - - A53_0: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x100>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <485>; - dynamic-power-coefficient = <140>; - }; - - A53_1: cpu@101 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x101>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <485>; - dynamic-power-coefficient = <140>; - }; - - A53_2: cpu@102 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x102>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <485>; - dynamic-power-coefficient = <140>; - }; - - A53_3: cpu@103 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x103>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <485>; - dynamic-power-coefficient = <140>; - }; - - A72_L2: l2-cache0 { - compatible = "cache"; - cache-size = <0x200000>; - cache-line-size = <64>; - cache-sets = <2048>; - }; - - A53_L2: l2-cache1 { - compatible = "cache"; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - }; - }; - - pmu-a72 { - compatible = "arm,cortex-a72-pmu"; - interrupts = , - ; - interrupt-affinity = <&A72_0>, - <&A72_1>; - }; - - pmu-a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&A53_0>, - <&A53_1>, - <&A53_2>, - <&A53_3>; - }; -}; - -&memtimer { - status = "okay"; -}; - -&pcie_ctlr { - status = "okay"; -}; - -&etm0 { - cpu = <&A72_0>; -}; - -&etm1 { - cpu = <&A72_1>; -}; - -&etm2 { - cpu = <&A53_0>; -}; - -&etm3 { - cpu = <&A53_1>; -}; - -&etm4 { - cpu = <&A53_2>; -}; - -&etm5 { - cpu = <&A53_3>; -}; - -&big_cluster_thermal_zone { - status = "okay"; -}; - -&little_cluster_thermal_zone { - status = "okay"; -}; - -&gpu0_thermal_zone { - status = "okay"; -}; - -&gpu1_thermal_zone { - status = "okay"; -}; - -&etf0_out_port { - remote-endpoint = <&csys2_funnel_in_port0>; -}; - -&replicator_in_port0 { - remote-endpoint = <&csys2_funnel_out_port>; -}; - -&csys1_funnel_in_port0 { - remote-endpoint = <&stm_out_port>; -}; - -&stm_out_port { - remote-endpoint = <&csys1_funnel_in_port0>; -}; - -&cpu_debug0 { - cpu = <&A72_0>; -}; - -&cpu_debug1 { - cpu = <&A72_1>; -}; - -&cpu_debug2 { - cpu = <&A53_0>; -}; - -&cpu_debug3 { - cpu = <&A53_1>; -}; - -&cpu_debug4 { - cpu = <&A53_2>; -}; - -&cpu_debug5 { - cpu = <&A53_3>; -}; diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts deleted file mode 100644 index f00cffbd0..000000000 --- a/arch/arm64/boot/dts/arm/juno.dts +++ /dev/null @@ -1,297 +0,0 @@ -/* - * ARM Ltd. Juno Platform - * - * Copyright (c) 2013-2014 ARM Ltd. - * - * This file is licensed under a dual GPLv2 or BSD license. - */ - -/dts-v1/; - -#include -#include "juno-base.dtsi" - -/ { - model = "ARM Juno development board (r0)"; - compatible = "arm,juno", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &soc_uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&A57_0>; - }; - core1 { - cpu = <&A57_1>; - }; - }; - - cluster1 { - core0 { - cpu = <&A53_0>; - }; - core1 { - cpu = <&A53_1>; - }; - core2 { - cpu = <&A53_2>; - }; - core3 { - cpu = <&A53_3>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <300>; - exit-latency-us = <1200>; - min-residency-us = <2000>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x1010000>; - local-timer-stop; - entry-latency-us = <400>; - exit-latency-us = <1200>; - min-residency-us = <2500>; - }; - }; - - A57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0 0x0>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&A57_L2>; - clocks = <&scpi_dvfs 0>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <530>; - }; - - A57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x0 0x1>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&A57_L2>; - clocks = <&scpi_dvfs 0>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <530>; - }; - - A53_0: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x100>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <578>; - dynamic-power-coefficient = <140>; - }; - - A53_1: cpu@101 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x101>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <578>; - dynamic-power-coefficient = <140>; - }; - - A53_2: cpu@102 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x102>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <578>; - dynamic-power-coefficient = <140>; - }; - - A53_3: cpu@103 { - compatible = "arm,cortex-a53"; - reg = <0x0 0x103>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - clocks = <&scpi_dvfs 1>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <578>; - dynamic-power-coefficient = <140>; - }; - - A57_L2: l2-cache0 { - compatible = "cache"; - cache-size = <0x200000>; - cache-line-size = <64>; - cache-sets = <2048>; - }; - - A53_L2: l2-cache1 { - compatible = "cache"; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - }; - }; - - pmu-a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts = , - ; - interrupt-affinity = <&A57_0>, - <&A57_1>; - }; - - pmu-a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&A53_0>, - <&A53_1>, - <&A53_2>, - <&A53_3>; - }; -}; - -&etm0 { - cpu = <&A57_0>; -}; - -&etm1 { - cpu = <&A57_1>; -}; - -&etm2 { - cpu = <&A53_0>; -}; - -&etm3 { - cpu = <&A53_1>; -}; - -&etm4 { - cpu = <&A53_2>; -}; - -&etm5 { - cpu = <&A53_3>; -}; - -&etf0_out_port { - remote-endpoint = <&replicator_in_port0>; -}; - -&replicator_in_port0 { - remote-endpoint = <&etf0_out_port>; -}; - -&stm_out_port { - remote-endpoint = <&main_funnel_in_port2>; -}; - -&main_funnel_in_ports { - port@2 { - reg = <2>; - main_funnel_in_port2: endpoint { - remote-endpoint = <&stm_out_port>; - }; - }; -}; - -&cpu_debug0 { - cpu = <&A57_0>; -}; - -&cpu_debug1 { - cpu = <&A57_1>; -}; - -&cpu_debug2 { - cpu = <&A53_0>; -}; - -&cpu_debug3 { - cpu = <&A53_1>; -}; - -&cpu_debug4 { - cpu = <&A53_2>; -}; - -&cpu_debug5 { - cpu = <&A53_3>; -}; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts deleted file mode 100644 index 3050f45ba..000000000 --- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts +++ /dev/null @@ -1,193 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Fast Models - * - * Architecture Envelope Model (AEM) ARMv8-A - * ARMAEMv8AMPCT - * - * RTSM_VE_AEMv8A.lisa - */ - -/dts-v1/; - -#include - -/memreserve/ 0x80000000 0x00010000; - -#include "rtsm_ve-motherboard.dtsi" - -/ { - model = "RTSM_VE_AEMv8A"; - compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; - next-level-cache = <&L2_0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; - next-level-cache = <&L2_0>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x2>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; - next-level-cache = <&L2_0>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x3>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; - next-level-cache = <&L2_0>; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x80000000>, - <0x00000008 0x80000000 0 0x80000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* Chipselect 2,00000000 is physically at 0x18000000 */ - vram: vram@18000000 { - /* 8 MB of designated video RAM */ - compatible = "shared-dma-pool"; - reg = <0x00000000 0x18000000 0 0x00800000>; - no-map; - }; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0x2c001000 0 0x1000>, - <0x0 0x2c002000 0 0x2000>, - <0x0 0x2c004000 0 0x2000>, - <0x0 0x2c006000 0 0x2000>; - interrupts = ; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - clock-frequency = <100000000>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - }; - - panel { - compatible = "arm,rtsm-display"; - port { - panel_in: endpoint { - remote-endpoint = <&clcd_pads>; - }; - }; - }; - - bus@8000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, - <0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, - <0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, - <0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, - <0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, - <0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, - <0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, - <0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, - <0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, - <0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, - <0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, - <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - }; -}; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi deleted file mode 100644 index b917d9d3f..000000000 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Fast Models - * - * "rs2" extension for the v2m motherboard - */ -/ { - bus@8000000 { - motherboard-bus { - arm,v2m-memory-map = "rs2"; - - iofpga-bus@300000000 { - virtio-p9@140000 { - compatible = "virtio,mmio"; - reg = <0x140000 0x200>; - interrupts = <43>; - }; - - virtio-net@150000 { - compatible = "virtio,mmio"; - reg = <0x150000 0x200>; - interrupts = <44>; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi deleted file mode 100644 index 4c4a381d2..000000000 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +++ /dev/null @@ -1,250 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Fast Models - * - * Versatile Express (VE) system model - * Motherboard component - * - * VEMotherBoard.lisa - */ -/ { - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - v2m_fixed_3v3: v2m-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - v2m_oscclk1: oscclk1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 63500000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; - - reset { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; - }; - }; - - bus@8000000 { - motherboard-bus { - arm,v2m-memory-map = "rs1"; - compatible = "arm,vexpress,v2m-p1", "simple-bus"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - #interrupt-cells = <1>; - ranges; - - flash@0 { - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>, - <4 0x00000000 0x04000000>; - bank-width = <4>; - }; - - ethernet@202000000 { - compatible = "smsc,lan91c111"; - reg = <2 0x02000000 0x10000>; - interrupts = <15>; - }; - - iofpga-bus@300000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 3 0 0x200000>; - - v2m_sysreg: sysreg@10000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x010000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - }; - - v2m_sysctl: sysctl@20000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x020000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; - clock-names = "refclk", "timclk", "apb_pclk"; - #clock-cells = <1>; - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; - assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; - assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; - }; - - aaci@40000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x040000 0x1000>; - interrupts = <11>; - clocks = <&v2m_clk24mhz>; - clock-names = "apb_pclk"; - }; - - mmci@50000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x050000 0x1000>; - interrupts = <9>, <10>; - cd-gpios = <&v2m_sysreg 0 0>; - wp-gpios = <&v2m_sysreg 1 0>; - max-frequency = <12000000>; - vmmc-supply = <&v2m_fixed_3v3>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "mclk", "apb_pclk"; - }; - - kmi@60000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x060000 0x1000>; - interrupts = <12>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - kmi@70000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x070000 0x1000>; - interrupts = <13>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "KMIREFCLK", "apb_pclk"; - }; - - v2m_serial0: serial@90000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x090000 0x1000>; - interrupts = <5>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial1: serial@a0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a0000 0x1000>; - interrupts = <6>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial2: serial@b0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b0000 0x1000>; - interrupts = <7>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - v2m_serial3: serial@c0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c0000 0x1000>; - interrupts = <8>; - clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - - wdt@f0000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f0000 0x1000>; - interrupts = <0>; - clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - v2m_timer01: timer@110000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x110000 0x1000>; - interrupts = <2>; - clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - v2m_timer23: timer@120000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x120000 0x1000>; - interrupts = <3>; - clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - - virtio-block@130000 { - compatible = "virtio,mmio"; - reg = <0x130000 0x200>; - interrupts = <42>; - }; - - rtc@170000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x170000 0x1000>; - interrupts = <4>; - clocks = <&v2m_clk24mhz>; - clock-names = "apb_pclk"; - }; - - clcd@1f0000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x1f0000 0x1000>; - interrupt-names = "combined"; - interrupts = <14>; - clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; - clock-names = "clcdclk", "apb_pclk"; - memory-region = <&vram>; - - port { - clcd_pads: endpoint { - remote-endpoint = <&panel_in>; - arm,pl11x,tft-r0g0b0-pads = <0 8 16>; - }; - }; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts deleted file mode 100644 index d85991450..000000000 --- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts +++ /dev/null @@ -1,205 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARM Ltd. Versatile Express - * - * LogicTile Express 20MG - * V2F-1XV7 - * - * Cortex-A53 (2 cores) Soft Macrocell Model - * - * HBI-0247C - */ - -/dts-v1/; - -#include -#include "vexpress-v2m-rs1.dtsi" - -/ { - model = "V2F-1XV7 Cortex-A53x2 SMM"; - arm,hbi = <0x247>; - arm,vexpress,site = <0xf>; - compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - chosen { - stdout-path = "serial0:38400n8"; - }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 0>; - next-level-cache = <&L2_0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 1>; - next-level-cache = <&L2_0>; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */ - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* Chipselect 2 is physically at 0x18000000 */ - vram: vram@18000000 { - /* 8 MB of designated video RAM */ - compatible = "shared-dma-pool"; - reg = <0 0x18000000 0 0x00800000>; - no-map; - }; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0x2c001000 0 0x1000>, - <0 0x2c002000 0 0x2000>, - <0 0x2c004000 0 0x2000>, - <0 0x2c006000 0 0x2000>; - interrupts = ; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = , - ; - }; - - dcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - smbclk: smclk { - /* SMC clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 4>; - freq-range = <40000000 40000000>; - #clock-cells = <0>; - clock-output-names = "smclk"; - }; - - volt-vio { - /* VIO to expansion board above */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VIO_UP"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - volt-12v { - /* 12V from power connector J6 */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 1>; - regulator-name = "12"; - regulator-always-on; - }; - - temp-fpga { - /* FPGA temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "FPGA"; - }; - }; - - smb: bus@8000000 { - compatible = "simple-bus"; - - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0x08000000 0x04000000>, - <1 0 0 0x14000000 0x04000000>, - <2 0 0 0x18000000 0x04000000>, - <3 0 0 0x1c000000 0x04000000>, - <4 0 0 0x0c000000 0x04000000>, - <5 0 0 0x10000000 0x04000000>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, - <0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, - <0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, - <0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, - <0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, - <0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, - <0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, - <0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, - <0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, - <0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, - <0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, - <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - }; -}; diff --git a/arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi b/arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi deleted file mode 120000 index 68fd0f8f1..000000000 --- a/arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi +++ /dev/null @@ -1 +0,0 @@ -../../../../arm/boot/dts/vexpress-v2m-rs1.dtsi \ No newline at end of file diff --git a/arch/arm64/boot/dts/bitmain/Makefile b/arch/arm64/boot/dts/bitmain/Makefile deleted file mode 100644 index be90a6071..000000000 --- a/arch/arm64/boot/dts/bitmain/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ - -dtb-$(CONFIG_ARCH_BITMAIN) += bm1880-sophon-edge.dtb diff --git a/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts b/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts deleted file mode 100644 index 7a2c7f9c2..000000000 --- a/arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts +++ /dev/null @@ -1,184 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Linaro Ltd. - * Author: Manivannan Sadhasivam - */ - -/dts-v1/; - -#include "bm1880.dtsi" - -/* - * GPIO name legend: proper name = the GPIO line is used as GPIO - * NC = not connected (pin out but not routed from the chip to - * anything the board) - * "[PER]" = pin is muxed for [peripheral] (not GPIO) - * LSEC = Low Speed External Connector - * HSEC = High Speed External Connector - * - * Line names are taken from the schematic "sophon-edge-schematics" - * version, 1.0210. - * - * For the lines routed to the external connectors the - * lines are named after the 96Boards CE Specification 1.0, - * Appendix "Expansion Connector Signal Description". - * - * When the 96Board naming of a line and the schematic name of - * the same line are in conflict, the 96Board specification - * takes precedence. This is only for the informational - * lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L" - * are the only ones actually used for GPIO. - */ - -/ { - compatible = "bitmain,sophon-edge", "bitmain,bm1880"; - model = "Sophon Edge"; - - aliases { - serial0 = &uart0; - serial1 = &uart2; - serial2 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x1 0x00000000 0x0 0x40000000>; // 1GB - }; - - soc { - gpio0: gpio@50027000 { - porta: gpio-controller@0 { - gpio-line-names = - "GPIO-A", /* GPIO0, LSEC pin 23 */ - "GPIO-C", /* GPIO1, LSEC pin 25 */ - "[GPIO2_PHY0_RST]", /* GPIO2 */ - "GPIO-E", /* GPIO3, LSEC pin 27 */ - "[USB_DET]", /* GPIO4 */ - "[EN_P5V]", /* GPIO5 */ - "[VDDIO_MS1_SEL]", /* GPIO6 */ - "GPIO-G", /* GPIO7, LSEC pin 29 */ - "[BM_TUSB_RST_L]", /* GPIO8 */ - "[EN_P5V_USBHUB]", /* GPIO9 */ - "NC", - "LED_WIFI", /* GPIO11 */ - "LED_BT", /* GPIO12 */ - "[BM_BLM8221_EN_L]", /* GPIO13 */ - "NC", /* GPIO14 */ - "NC", /* GPIO15 */ - "NC", /* GPIO16 */ - "NC", /* GPIO17 */ - "NC", /* GPIO18 */ - "NC", /* GPIO19 */ - "NC", /* GPIO20 */ - "NC", /* GPIO21 */ - "NC", /* GPIO22 */ - "NC", /* GPIO23 */ - "NC", /* GPIO24 */ - "NC", /* GPIO25 */ - "NC", /* GPIO26 */ - "NC", /* GPIO27 */ - "NC", /* GPIO28 */ - "NC", /* GPIO29 */ - "NC", /* GPIO30 */ - "NC"; /* GPIO31 */ - }; - }; - - gpio1: gpio@50027400 { - portb: gpio-controller@0 { - gpio-line-names = - "NC", /* GPIO32 */ - "NC", /* GPIO33 */ - "[I2C0_SDA]", /* GPIO34, LSEC pin 17 */ - "[I2C0_SCL]", /* GPIO35, LSEC pin 15 */ - "[JTAG0_TDO]", /* GPIO36 */ - "[JTAG0_TCK]", /* GPIO37 */ - "[JTAG0_TDI]", /* GPIO38 */ - "[JTAG0_TMS]", /* GPIO39 */ - "[JTAG0_TRST_X]", /* GPIO40 */ - "[JTAG1_TDO]", /* GPIO41 */ - "[JTAG1_TCK]", /* GPIO42 */ - "[JTAG1_TDI]", /* GPIO43 */ - "[CPU_TX]", /* GPIO44 */ - "[CPU_RX]", /* GPIO45 */ - "[UART1_TXD]", /* GPIO46 */ - "[UART1_RXD]", /* GPIO47 */ - "[UART0_TXD]", /* GPIO48 */ - "[UART0_RXD]", /* GPIO49 */ - "GPIO-I", /* GPIO50, LSEC pin 31 */ - "GPIO-K", /* GPIO51, LSEC pin 33 */ - "USER_LED2", /* GPIO52 */ - "USER_LED1", /* GPIO53 */ - "[UART0_RTS]", /* GPIO54 */ - "[UART0_CTS]", /* GPIO55 */ - "USER_LED4", /* GPIO56, JTAG1_TRST_X */ - "USER_LED3", /* GPIO57, JTAG1_TMS */ - "[I2S0_SCLK]", /* GPIO58 */ - "[I2S0_FS]", /* GPIO59 */ - "[I2S0_SDI]", /* GPIO60 */ - "[I2S0_SDO]", /* GPIO61 */ - "GPIO-B", /* GPIO62, LSEC pin 24 */ - "GPIO-F"; /* GPIO63, I2S1_SCLK, LSEC pin 28 */ - }; - }; - - gpio2: gpio@50027800 { - portc: gpio-controller@0 { - gpio-line-names = - "GPIO-D", /* GPIO64, I2S1_FS, LSEC pin 26 */ - "GPIO-J", /* GPIO65, I2S1_SDI, LSEC pin 32 */ - "GPIO-H", /* GPIO66, I2S1_SDO, LSEC pin 30 */ - "GPIO-L", /* GPIO67, LSEC pin 34 */ - "[SPI0_CS]", /* GPIO68, SPI1_CS, LSEC pin 12 */ - "[SPI0_DIN]", /* GPIO69, SPI1_SDI, LSEC pin 10 */ - "[SPI0_DOUT]", /* GPIO70, SPI1_SDO, LSEC pin 14 */ - "[SPI0_SCLK]"; /* GPIO71, SPI1_SCK, LSEC pin 8 */ - }; - }; - }; -}; - -&pinctrl { - pinctrl_uart0_default: pinctrl-uart0-default { - pinmux { - groups = "uart0_grp"; - function = "uart0"; - }; - }; - - pinctrl_uart1_default: pinctrl-uart1-default { - pinmux { - groups = "uart1_grp"; - function = "uart1"; - }; - }; - - pinctrl_uart2_default: pinctrl-uart2-default { - pinmux { - groups = "uart2_grp"; - function = "uart2"; - }; - }; -}; - -&uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0_default>; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; -}; - -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_default>; -}; diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi deleted file mode 100644 index fa6e6905f..000000000 --- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi +++ /dev/null @@ -1,226 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Linaro Ltd. - * Author: Manivannan Sadhasivam - */ - -#include -#include -#include - -/ { - compatible = "bitmain,bm1880"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - enable-method = "psci"; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - enable-method = "psci"; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secmon@100000000 { - reg = <0x1 0x00000000 0x0 0x20000>; - no-map; - }; - - jpu@130000000 { - reg = <0x1 0x30000000 0x0 0x08000000>; // 128M - no-map; - }; - - vpu@138000000 { - reg = <0x1 0x38000000 0x0 0x08000000>; // 128M - no-map; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - osc: osc { - compatible = "fixed-clock"; - clock-frequency = <25000000>; - #clock-cells = <0>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gic: interrupt-controller@50001000 { - compatible = "arm,gic-400"; - reg = <0x0 0x50001000 0x0 0x1000>, - <0x0 0x50002000 0x0 0x2000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - - sctrl: system-controller@50010000 { - compatible = "bitmain,bm1880-sctrl", "syscon", - "simple-mfd"; - reg = <0x0 0x50010000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x50010000 0x1000>; - - pinctrl: pinctrl@400 { - compatible = "bitmain,bm1880-pinctrl"; - reg = <0x400 0x120>; - }; - - clk: clock-controller@e8 { - compatible = "bitmain,bm1880-clk"; - reg = <0xe8 0x0c>, <0x800 0xb0>; - reg-names = "pll", "sys"; - clocks = <&osc>; - clock-names = "osc"; - #clock-cells = <1>; - }; - - rst: reset-controller@c00 { - compatible = "bitmain,bm1880-reset"; - reg = <0xc00 0x8>; - #reset-cells = <1>; - }; - }; - - gpio0: gpio@50027000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0x0 0x50027000 0x0 0x400>; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - }; - - gpio1: gpio@50027400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0x0 0x50027400 0x0 0x400>; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - }; - - gpio2: gpio@50027800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0x0 0x50027800 0x0 0x400>; - - portc: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - }; - - uart0: serial@58018000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x58018000 0x0 0x2000>; - clocks = <&clk BM1880_CLK_UART_500M>, - <&clk BM1880_CLK_APB_UART>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - resets = <&rst BM1880_RST_UART0_1_CLK>; - status = "disabled"; - }; - - uart1: serial@5801A000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x5801a000 0x0 0x2000>; - clocks = <&clk BM1880_CLK_UART_500M>, - <&clk BM1880_CLK_APB_UART>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - resets = <&rst BM1880_RST_UART0_1_ACLK>; - status = "disabled"; - }; - - uart2: serial@5801C000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x5801c000 0x0 0x2000>; - clocks = <&clk BM1880_CLK_UART_500M>, - <&clk BM1880_CLK_APB_UART>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - resets = <&rst BM1880_RST_UART2_3_CLK>; - status = "disabled"; - }; - - uart3: serial@5801E000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x5801e000 0x0 0x2000>; - clocks = <&clk BM1880_CLK_UART_500M>, - <&clk BM1880_CLK_APB_UART>; - clock-names = "baudclk", "apb_pclk"; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - resets = <&rst BM1880_RST_UART2_3_ACLK>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile deleted file mode 100644 index cb7de8d99..000000000 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-4-b.dtb \ - bcm2837-rpi-3-a-plus.dtb \ - bcm2837-rpi-3-b.dtb \ - bcm2837-rpi-3-b-plus.dtb \ - bcm2837-rpi-cm3-io3.dtb - -subdir-y += northstar2 -subdir-y += stingray diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts deleted file mode 100644 index d24c53682..000000000 --- a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts +++ /dev/null @@ -1,2 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2711-rpi-4-b.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts deleted file mode 100644 index f0ec56a1c..000000000 --- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts +++ /dev/null @@ -1,2 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-3-a-plus.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts deleted file mode 100644 index 46ad2023c..000000000 --- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts +++ /dev/null @@ -1,2 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-3-b-plus.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts deleted file mode 100644 index 89b78d6c1..000000000 --- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts +++ /dev/null @@ -1,2 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-3-b.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts deleted file mode 100644 index b1c4ab212..000000000 --- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts +++ /dev/null @@ -1,2 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "arm/bcm2837-rpi-cm3-io3.dts" diff --git a/arch/arm64/boot/dts/broadcom/northstar2/Makefile b/arch/arm64/boot/dts/broadcom/northstar2/Makefile deleted file mode 100644 index 601e1e631..000000000 --- a/arch/arm64/boot/dts/broadcom/northstar2/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb -dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-xmc.dtb diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi deleted file mode 100644 index 99009fdf1..000000000 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi +++ /dev/null @@ -1,105 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright (c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - lcpll_ddr: lcpll_ddr@6501d058 { - #clock-cells = <1>; - compatible = "brcm,ns2-lcpll-ddr"; - reg = <0x6501d058 0x20>, - <0x6501c020 0x4>, - <0x6501d04c 0x4>; - clocks = <&osc>; - clock-output-names = "lcpll_ddr", "pcie_sata_usb", - "ddr", "ddr_ch2_unused", - "ddr_ch3_unused", "ddr_ch4_unused", - "ddr_ch5_unused"; - }; - - lcpll_ports: lcpll_ports@6501d078 { - #clock-cells = <1>; - compatible = "brcm,ns2-lcpll-ports"; - reg = <0x6501d078 0x20>, - <0x6501c020 0x4>, - <0x6501d054 0x4>; - clocks = <&osc>; - clock-output-names = "lcpll_ports", "wan", "rgmii", - "ports_ch2_unused", - "ports_ch3_unused", - "ports_ch4_unused", - "ports_ch5_unused"; - }; - - genpll_scr: genpll_scr@6501d098 { - #clock-cells = <1>; - compatible = "brcm,ns2-genpll-scr"; - reg = <0x6501d098 0x32>, - <0x6501c020 0x4>, - <0x6501d044 0x4>; - clocks = <&osc>; - clock-output-names = "genpll_scr", "scr", "fs", - "audio_ref", "scr_ch3_unused", - "scr_ch4_unused", "scr_ch5_unused"; - }; - - iprocmed: iprocmed { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; - clock-div = <2>; - clock-mult = <1>; - }; - - iprocslow: iprocslow { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; - clock-div = <4>; - clock-mult = <1>; - }; - - genpll_sw: genpll_sw@6501d0c4 { - #clock-cells = <1>; - compatible = "brcm,ns2-genpll-sw"; - reg = <0x6501d0c4 0x32>, - <0x6501c020 0x4>, - <0x6501d044 0x4>; - clocks = <&osc>; - clock-output-names = "genpll_sw", "rpe", "250", "nic", - "chimp", "port", "sdio"; - }; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts deleted file mode 100644 index 12a4b1c03..000000000 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts +++ /dev/null @@ -1,236 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "ns2.dtsi" - -/ { - model = "Broadcom NS2 SVK"; - compatible = "brcm,ns2-svk", "brcm,ns2"; - - aliases { - serial0 = &uart3; - serial1 = &uart0; - serial2 = &uart1; - serial3 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - bootargs = "earlycon=uart8250,mmio32,0x66130000"; - }; - - memory { - device_type = "memory"; - reg = <0x000000000 0x80000000 0x00000000 0x40000000>; - }; -}; - -&enet { - status = "okay"; -}; - -&pci_phy0 { - status = "okay"; -}; - -&pci_phy1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie4 { - status = "okay"; -}; - -&pcie8 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&ssp0 { - status = "okay"; - - slic@0 { - compatible = "silabs,si3226x"; - reg = <0>; - spi-max-frequency = <5000000>; - spi-cpha; - spi-cpol; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable = <0>; - pl022,com-mode = <0>; - pl022,rx-level-trig = <1>; - pl022,tx-level-trig = <1>; - pl022,ctrl-len = <11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; -}; - -&ssp1 { - status = "okay"; - - at25@0 { - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <5000000>; - at25,byte-len = <0x8000>; - at25,addr-mode = <2>; - at25,page-size = <64>; - spi-cpha; - spi-cpol; - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable = <0>; - pl022,com-mode = <0>; - pl022,rx-level-trig = <1>; - pl022,tx-level-trig = <1>; - pl022,ctrl-len = <11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; -}; - -&sata_phy0 { - status = "okay"; -}; - -&sata_phy1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&sdio0 { - status = "okay"; -}; - -&sdio1 { - status = "okay"; -}; - -&nand { - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - nand-bus-width = <16>; - brcm,nand-oob-sector-size = <16>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&mdio_mux_iproc { - mdio@10 { - gphy0: eth-phy@10 { - enet-phy-lane-swap; - reg = <0x10>; - }; - }; -}; - -&pinctrl { - pinctrl-names = "default"; - pinctrl-0 = <&nand_sel>; - nand_sel: nand_sel { - function = "nand"; - groups = "nand_grp"; - }; -}; - -&qspi { - bspi-sel = <0>; - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - reg = <0x0>; - spi-max-frequency = <12500000>; - m25p,fast-read; - spi-cpol; - spi-cpha; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x000a0000>; - }; - - partition@a0000 { - label = "env"; - reg = <0x000a0000 0x00060000>; - }; - - partition@100000 { - label = "system"; - reg = <0x00100000 0x00600000>; - }; - - partition@700000 { - label = "rootfs"; - reg = <0x00700000 0x01900000>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts deleted file mode 100644 index f00c21e07..000000000 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts +++ /dev/null @@ -1,191 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "ns2.dtsi" - -/ { - model = "Broadcom NS2 XMC"; - compatible = "brcm,ns2-xmc", "brcm,ns2"; - - aliases { - serial0 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - bootargs = "earlycon=uart8250,mmio32,0x66130000"; - }; - - memory { - device_type = "memory"; - reg = <0x000000000 0x80000000 0x00000001 0x00000000>; - }; -}; - -&enet { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&mdio_mux_iproc { - mdio@10 { - gphy0: eth-phy@10 { - reg = <0x10>; - }; - }; -}; - -&nand { - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - nand-bus-width = <16>; - brcm,nand-oob-sector-size = <16>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "nboot"; - reg = <0x00000000 0x00280000>; /* 2.5MB */ - read-only; - }; - - partition@280000 { - label = "nenv"; - reg = <0x00280000 0x00040000>; /* 0.25MB */ - read-only; - }; - - partition@2c0000 { - label = "ndtb"; - reg = <0x002c0000 0x00040000>; /* 0.25MB */ - read-only; - }; - - partition@300000 { - label = "nsystem"; - reg = <0x00300000 0x03d00000>; /* 61MB */ - read-only; - }; - - partition@4000000 { - label = "nrootfs"; - reg = <0x04000000 0x06400000>; /* 100MB */ - }; - - partition@a400000{ - label = "ncustfs"; - reg = <0x0a400000 0x35c00000>; /* 860MB */ - }; - }; -}; - -&pci_phy0 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie8 { - status = "okay"; -}; - -&sata_phy0 { - status = "okay"; -}; - -&sata_phy1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&qspi { - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80"; - spi-max-frequency = <62500000>; - m25p,default-addr-width = <3>; - reg = <0x0 0x0>; - - partition@0 { - label = "bl0"; - reg = <0x00000000 0x00080000>; /* 512KB */ - }; - - partition@80000 { - label = "fip"; - reg = <0x00080000 0x00150000>; /* 1344KB */ - }; - - partition@1e0000 { - label = "env"; - reg = <0x001e0000 0x00010000>;/* 64KB */ - }; - - partition@1f0000 { - label = "dtb"; - reg = <0x001f0000 0x00010000>; /* 64KB */ - }; - - partition@200000 { - label = "kernel"; - reg = <0x00200000 0x00e00000>; /* 14MB */ - }; - - partition@1000000 { - label = "rootfs"; - reg = <0x01000000 0x01000000>; /* 16MB */ - }; - }; -}; - -&uart3 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi deleted file mode 100644 index 8c218689f..000000000 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ /dev/null @@ -1,765 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright (c) 2015 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/memreserve/ 0x81000000 0x00200000; - -#include -#include - -/ { - compatible = "brcm,ns2"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - A57_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0 0>; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - }; - - A57_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0 1>; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - }; - - A57_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0 2>; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - }; - - A57_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0 3>; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - }; - - CLUSTER0_L2: l2-cache@0 { - compatible = "cache"; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - interrupt-affinity = <&A57_0>, - <&A57_1>, - <&A57_2>, - <&A57_3>; - }; - - pcie0: pcie@20020000 { - compatible = "brcm,iproc-pcie"; - reg = <0 0x20020000 0 0x1000>; - dma-coherent; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>; - - linux,pci-domain = <0>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>; - - brcm,pcie-ob; - brcm,pcie-ob-oarr-size; - brcm,pcie-ob-axi-offset = <0x00000000>; - brcm,pcie-ob-window-size = <256>; - - status = "disabled"; - - phys = <&pci_phy0>; - phy-names = "pcie-phy"; - - msi-parent = <&v2m0>; - }; - - pcie4: pcie@50020000 { - compatible = "brcm,iproc-pcie"; - reg = <0 0x50020000 0 0x1000>; - dma-coherent; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; - - linux,pci-domain = <4>; - - bus-range = <0x00 0xff>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>; - - brcm,pcie-ob; - brcm,pcie-ob-oarr-size; - brcm,pcie-ob-axi-offset = <0x30000000>; - brcm,pcie-ob-window-size = <256>; - - status = "disabled"; - - phys = <&pci_phy1>; - phy-names = "pcie-phy"; - - msi-parent = <&v2m0>; - }; - - pcie8: pcie@60c00000 { - compatible = "brcm,iproc-pcie-paxc"; - reg = <0 0x60c00000 0 0x1000>; - dma-coherent; - linux,pci-domain = <8>; - - bus-range = <0x0 0x1>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x83000000 0 0x00000000 0 0x60000000 0 0x00c00000>; - - status = "disabled"; - - msi-parent = <&v2m0>; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - - #include "ns2-clock.dtsi" - - enet: ethernet@61000000 { - compatible = "brcm,ns2-amac"; - reg = <0x61000000 0x1000>, - <0x61090000 0x1000>, - <0x61030000 0x100>; - reg-names = "amac_base", "idm_base", "nicpm_base"; - interrupts = ; - dma-coherent; - phy-handle = <&gphy0>; - phy-mode = "rgmii"; - status = "disabled"; - }; - - pdc0: iproc-pdc0@612c0000 { - compatible = "brcm,iproc-pdc-mbox"; - reg = <0x612c0000 0x445>; /* PDC FS0 regs */ - interrupts = ; - #mbox-cells = <1>; - dma-coherent; - brcm,rx-status-len = <32>; - brcm,use-bcm-hdr; - }; - - crypto0: crypto@612d0000 { - compatible = "brcm,spum-crypto"; - reg = <0x612d0000 0x900>; - mboxes = <&pdc0 0>; - }; - - pdc1: iproc-pdc1@612e0000 { - compatible = "brcm,iproc-pdc-mbox"; - reg = <0x612e0000 0x445>; /* PDC FS1 regs */ - interrupts = ; - #mbox-cells = <1>; - dma-coherent; - brcm,rx-status-len = <32>; - brcm,use-bcm-hdr; - }; - - crypto1: crypto@612f0000 { - compatible = "brcm,spum-crypto"; - reg = <0x612f0000 0x900>; - mboxes = <&pdc1 0>; - }; - - pdc2: iproc-pdc2@61300000 { - compatible = "brcm,iproc-pdc-mbox"; - reg = <0x61300000 0x445>; /* PDC FS2 regs */ - interrupts = ; - #mbox-cells = <1>; - dma-coherent; - brcm,rx-status-len = <32>; - brcm,use-bcm-hdr; - }; - - crypto2: crypto@61310000 { - compatible = "brcm,spum-crypto"; - reg = <0x61310000 0x900>; - mboxes = <&pdc2 0>; - }; - - pdc3: iproc-pdc3@61320000 { - compatible = "brcm,iproc-pdc-mbox"; - reg = <0x61320000 0x445>; /* PDC FS3 regs */ - interrupts = ; - #mbox-cells = <1>; - dma-coherent; - brcm,rx-status-len = <32>; - brcm,use-bcm-hdr; - }; - - crypto3: crypto@61330000 { - compatible = "brcm,spum-crypto"; - reg = <0x61330000 0x900>; - mboxes = <&pdc3 0>; - }; - - dma0: dma@61360000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x61360000 0x1000>; - interrupts = , - , - , - , - , - , - , - , - ; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - clocks = <&iprocslow>; - clock-names = "apb_pclk"; - }; - - smmu: mmu@64000000 { - compatible = "arm,mmu-500"; - reg = <0x64000000 0x40000>; - #global-interrupts = <2>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - #iommu-cells = <1>; - }; - - pinctrl: pinctrl@6501d130 { - compatible = "brcm,ns2-pinmux"; - reg = <0x6501d130 0x08>, - <0x660a0028 0x04>, - <0x660009b0 0x40>; - }; - - gpio_aon: gpio@65024800 { - compatible = "brcm,iproc-gpio"; - reg = <0x65024800 0x50>, - <0x65024008 0x18>; - ngpios = <6>; - #gpio-cells = <2>; - gpio-controller; - }; - - gic: interrupt-controller@65210000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x65210000 0x1000>, - <0x65220000 0x1000>, - <0x65240000 0x2000>, - <0x65260000 0x1000>; - interrupts = ; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x652e0000 0x80000>; - - v2m0: v2m@0 { - compatible = "arm,gic-v2m-frame"; - interrupt-parent = <&gic>; - msi-controller; - reg = <0x00000 0x1000>; - arm,msi-base-spi = <72>; - arm,msi-num-spis = <16>; - }; - - v2m1: v2m@10000 { - compatible = "arm,gic-v2m-frame"; - interrupt-parent = <&gic>; - msi-controller; - reg = <0x10000 0x1000>; - arm,msi-base-spi = <88>; - arm,msi-num-spis = <16>; - }; - - v2m2: v2m@20000 { - compatible = "arm,gic-v2m-frame"; - interrupt-parent = <&gic>; - msi-controller; - reg = <0x20000 0x1000>; - arm,msi-base-spi = <104>; - arm,msi-num-spis = <16>; - }; - - v2m3: v2m@30000 { - compatible = "arm,gic-v2m-frame"; - interrupt-parent = <&gic>; - msi-controller; - reg = <0x30000 0x1000>; - arm,msi-base-spi = <120>; - arm,msi-num-spis = <16>; - }; - - v2m4: v2m@40000 { - compatible = "arm,gic-v2m-frame"; - interrupt-parent = <&gic>; - msi-controller; - reg = <0x40000 0x1000>; - arm,msi-base-spi = <136>; - arm,msi-num-spis = <16>; - }; - - v2m5: v2m@50000 { - compatible = "arm,gic-v2m-frame"; - interrupt-parent = <&gic>; - msi-controller; - reg = <0x50000 0x1000>; - arm,msi-base-spi = <152>; - arm,msi-num-spis = <16>; - }; - - v2m6: v2m@60000 { - compatible = "arm,gic-v2m-frame"; - interrupt-parent = <&gic>; - msi-controller; - reg = <0x60000 0x1000>; - arm,msi-base-spi = <168>; - arm,msi-num-spis = <16>; - }; - - v2m7: v2m@70000 { - compatible = "arm,gic-v2m-frame"; - interrupt-parent = <&gic>; - msi-controller; - reg = <0x70000 0x1000>; - arm,msi-base-spi = <184>; - arm,msi-num-spis = <16>; - }; - }; - - cci@65590000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x65590000 0x1000>; - ranges = <0 0x65590000 0x10000>; - - pmu@9000 { - compatible = "arm,cci-400-pmu,r1", - "arm,cci-400-pmu"; - reg = <0x9000 0x4000>; - interrupts = , - , - , - , - , - ; - }; - }; - - usbdrd_phy: phy@66000960 { - #phy-cells = <0>; - compatible = "brcm,ns2-drd-phy"; - reg = <0x66000960 0x24>, - <0x67012800 0x4>, - <0x6501d148 0x4>, - <0x664d0700 0x4>; - reg-names = "icfg", "rst-ctrl", - "crmu-ctrl", "usb2-strap"; - id-gpios = <&gpio_g 30 0>; - vbus-gpios = <&gpio_g 31 0>; - status = "disabled"; - }; - - pwm: pwm@66010000 { - compatible = "brcm,iproc-pwm"; - reg = <0x66010000 0x28>; - clocks = <&osc>; - #pwm-cells = <3>; - status = "disabled"; - }; - - mdio_mux_iproc: mdio-mux@66020000 { - compatible = "brcm,mdio-mux-iproc"; - reg = <0x66020000 0x250>; - #address-cells = <1>; - #size-cells = <0>; - - mdio@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - pci_phy0: pci-phy@0 { - compatible = "brcm,ns2-pcie-phy"; - reg = <0x0>; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - mdio@7 { - reg = <0x7>; - #address-cells = <1>; - #size-cells = <0>; - - pci_phy1: pci-phy@0 { - compatible = "brcm,ns2-pcie-phy"; - reg = <0x0>; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - mdio@10 { - reg = <0x10>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - timer0: timer@66030000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x66030000 0x1000>; - interrupts = ; - clocks = <&iprocslow>, - <&iprocslow>, - <&iprocslow>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - timer1: timer@66040000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x66040000 0x1000>; - interrupts = ; - clocks = <&iprocslow>, - <&iprocslow>, - <&iprocslow>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - timer2: timer@66050000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x66050000 0x1000>; - interrupts = ; - clocks = <&iprocslow>, - <&iprocslow>, - <&iprocslow>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - timer3: timer@66060000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x66060000 0x1000>; - interrupts = ; - clocks = <&iprocslow>, - <&iprocslow>, - <&iprocslow>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - i2c0: i2c@66080000 { - compatible = "brcm,iproc-i2c"; - reg = <0x66080000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <100000>; - status = "disabled"; - }; - - wdt0: watchdog@66090000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x66090000 0x1000>; - interrupts = ; - clocks = <&iprocslow>, <&iprocslow>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - gpio_g: gpio@660a0000 { - compatible = "brcm,iproc-gpio"; - reg = <0x660a0000 0x50>; - ngpios = <32>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - interrupts = ; - }; - - i2c1: i2c@660b0000 { - compatible = "brcm,iproc-i2c"; - reg = <0x660b0000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <100000>; - status = "disabled"; - }; - - uart0: serial@66100000 { - compatible = "snps,dw-apb-uart"; - reg = <0x66100000 0x100>; - interrupts = ; - clocks = <&iprocslow>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: serial@66110000 { - compatible = "snps,dw-apb-uart"; - reg = <0x66110000 0x100>; - interrupts = ; - clocks = <&iprocslow>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@66120000 { - compatible = "snps,dw-apb-uart"; - reg = <0x66120000 0x100>; - interrupts = ; - clocks = <&iprocslow>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart3: serial@66130000 { - compatible = "snps,dw-apb-uart"; - reg = <0x66130000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&osc>; - status = "disabled"; - }; - - ssp0: spi@66180000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x66180000 0x1000>; - interrupts = ; - clocks = <&iprocslow>, <&iprocslow>; - clock-names = "spiclk", "apb_pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ssp1: spi@66190000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x66190000 0x1000>; - interrupts = ; - clocks = <&iprocslow>, <&iprocslow>; - clock-names = "spiclk", "apb_pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hwrng: hwrng@66220000 { - compatible = "brcm,iproc-rng200"; - reg = <0x66220000 0x28>; - }; - - sata_phy: sata_phy@663f0100 { - compatible = "brcm,iproc-ns2-sata-phy"; - reg = <0x663f0100 0x1f00>, - <0x663f004c 0x10>; - reg-names = "phy", "phy-ctrl"; - #address-cells = <1>; - #size-cells = <0>; - - sata_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - status = "disabled"; - }; - - sata_phy1: sata-phy@1 { - reg = <1>; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - sata: sata@663f2000 { - compatible = "brcm,iproc-ahci", "generic-ahci"; - reg = <0x663f2000 0x1000>; - dma-coherent; - reg-names = "ahci"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata0: sata-port@0 { - reg = <0>; - phys = <&sata_phy0>; - phy-names = "sata-phy"; - }; - - sata1: sata-port@1 { - reg = <1>; - phys = <&sata_phy1>; - phy-names = "sata-phy"; - }; - }; - - sdio0: sdhci@66420000 { - compatible = "brcm,sdhci-iproc-cygnus"; - reg = <0x66420000 0x100>; - interrupts = ; - dma-coherent; - bus-width = <8>; - clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>; - status = "disabled"; - }; - - sdio1: sdhci@66430000 { - compatible = "brcm,sdhci-iproc-cygnus"; - reg = <0x66430000 0x100>; - interrupts = ; - dma-coherent; - bus-width = <8>; - clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>; - status = "disabled"; - }; - - nand: nand@66460000 { - compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; - reg = <0x66460000 0x600>, - <0x67015408 0x600>, - <0x66460f00 0x20>; - reg-names = "nand", "iproc-idm", "iproc-ext"; - interrupts = ; - - #address-cells = <1>; - #size-cells = <0>; - - brcm,nand-has-wp; - }; - - qspi: spi@66470200 { - compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi"; - reg = <0x66470200 0x184>, - <0x66470000 0x124>, - <0x67017408 0x004>, - <0x664703a0 0x01c>; - reg-names = "mspi", "bspi", "intr_regs", - "intr_status_reg"; - interrupts = ; - interrupt-names = "spi_l1_intr"; - clocks = <&iprocmed>; - clock-names = "iprocmed"; - num-cs = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - }; -}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/Makefile b/arch/arm64/boot/dts/broadcom/stingray/Makefile deleted file mode 100644 index 20c7d0aa6..000000000 --- a/arch/arm64/boot/dts/broadcom/stingray/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958742k.dtb -dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958742t.dtb - -dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958802a802x.dtb diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi deleted file mode 100644 index 43aa5e9c0..000000000 --- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi +++ /dev/null @@ -1,176 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016-2017 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "stingray-board-base.dtsi" - -/ { - sdio0_vddo_ctrl_reg: sdio0_vddo_ctrl { - compatible = "regulator-gpio"; - regulator-name = "sdio0_vddo_ctrl_reg"; - regulator-type = "voltage"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios = <&pca9505 18 0>; - states = <3300000 0x0 - 1800000 0x1>; - }; - - sdio1_vddo_ctrl_reg: sdio1_vddo_ctrl { - compatible = "regulator-gpio"; - regulator-name = "sdio1_vddo_ctrl_reg"; - regulator-type = "voltage"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios = <&pca9505 19 0>; - states = <3300000 0x0 - 1800000 0x1>; - }; -}; - -&sata0 { - status = "okay"; -}; - -&sata_phy0{ - status = "okay"; -}; - -&sata1 { - status = "okay"; -}; - -&sata_phy1{ - status = "okay"; -}; - -&sata2 { - status = "okay"; -}; - -&sata_phy2{ - status = "okay"; -}; - -&sata3 { - status = "okay"; -}; - -&sata_phy3{ - status = "okay"; -}; - -&sata4 { - status = "okay"; -}; - -&sata_phy4{ - status = "okay"; -}; - -&sata5 { - status = "okay"; -}; - -&sata_phy5{ - status = "okay"; -}; - -&sata6 { - status = "okay"; -}; - -&sata_phy6{ - status = "okay"; -}; - -&sata7 { - status = "okay"; -}; - -&sata_phy7{ - status = "okay"; -}; - -&pwm { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - pca9505: pca9505@20 { - compatible = "nxp,pca9505"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - }; -}; - -&i2c1 { - status = "okay"; - - pcf8574: pcf8574@27 { - compatible = "nxp,pcf8574a"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x27>; - }; -}; - -&enet { - status = "okay"; -}; - -&nand { - status = "okay"; - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - nand-bus-width = <16>; - brcm,nand-oob-sector-size = <16>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&sdio0 { - vqmmc-supply = <&sdio0_vddo_ctrl_reg>; - status = "okay"; -}; - -&sdio1 { - vqmmc-supply = <&sdio1_vddo_ctrl_reg>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts deleted file mode 100644 index 77efa28c4..000000000 --- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts +++ /dev/null @@ -1,86 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016-2017 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm958742-base.dtsi" - -/ { - compatible = "brcm,bcm958742k", "brcm,stingray"; - model = "Stingray Combo SVK (BCM958742K)"; -}; - -&gphy0 { - enet-phy-lane-swap; -}; - -&sdio0 { - mmc-ddr-1_8v; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&ssp0 { - pinctrl-0 = <&spi0_pins>; - pinctrl-names = "default"; - cs-gpios = <&gpio_hsls 34 0>; - status = "okay"; - - spi-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&ssp1 { - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; - cs-gpios = <&gpio_hsls 96 0>; - status = "okay"; - - spi-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts deleted file mode 100644 index 55ba495ef..000000000 --- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2017 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/dts-v1/; - -#include "bcm958742-base.dtsi" - -/ { - compatible = "brcm,bcm958742t", "brcm,stingray"; - model = "Stingray SST100 (BCM958742T)"; -}; - -&gphy0 { - enet-phy-lane-swap; -}; - -&sdio0 { - mmc-ddr-1_8v; -}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts deleted file mode 100644 index a41facd7d..000000000 --- a/arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) -/* - *Copyright(c) 2018 Broadcom - */ - -/dts-v1/; - -#include "stingray-board-base.dtsi" - -/ { - compatible = "brcm,bcm958802a802x", "brcm,stingray"; - model = "Stingray PS225xx (BCM958802A802x)"; -}; - -&enet { - status = "disabled"; -}; - -&sdio0 { - no-1-8-v; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi deleted file mode 100644 index 82a24711d..000000000 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) -/* - * Copyright(c) 2016-2018 Broadcom - */ - -#include "stingray.dtsi" -#include - -/ { - aliases { - serial0 = &uart1; - serial1 = &uart0; - serial2 = &uart2; - serial3 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&memory { /* Default DRAM banks */ - reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ - <0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */ -}; - -&enet { - phy-mode = "rgmii-id"; - phy-handle = <&gphy0>; -}; - -&uart1 { - status = "okay"; -}; - -&sdio0 { - non-removable; - full-pwr-cycle; -}; - -&sdio1 { - full-pwr-cycle; -}; - -&mdio_mux_iproc { - mdio@10 { - gphy0: eth-phy@10 { - reg = <0x10>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi deleted file mode 100644 index 10a106aca..000000000 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi +++ /dev/null @@ -1,182 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016-2017 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - crmu_ref25m: crmu_ref25m { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&osc>; - clock-div = <2>; - clock-mult = <1>; - }; - - genpll0: genpll0@1d104 { - #clock-cells = <1>; - compatible = "brcm,sr-genpll0"; - reg = <0x0001d104 0x32>, - <0x0001c854 0x4>; - clocks = <&osc>; - clock-output-names = "genpll0", "clk_125m", "clk_scr", - "clk_250", "clk_pcie_axi", - "clk_paxc_axi_x2", - "clk_paxc_axi"; - }; - - genpll2: genpll2@1d1ac { - #clock-cells = <1>; - compatible = "brcm,sr-genpll2"; - reg = <0x0001d1ac 0x32>, - <0x0001c854 0x4>; - clocks = <&osc>; - clock-output-names = "genpll2", "clk_nic", - "clk_ts_500_ref", "clk_125_nitro", - "clk_chimp", "clk_nic_flash", - "clk_fs"; - }; - - genpll3: genpll3@1d1e0 { - #clock-cells = <1>; - compatible = "brcm,sr-genpll3"; - reg = <0x0001d1e0 0x32>, - <0x0001c854 0x4>; - clocks = <&osc>; - clock-output-names = "genpll3", "clk_hsls", - "clk_sdio"; - }; - - genpll4: genpll4@1d214 { - #clock-cells = <1>; - compatible = "brcm,sr-genpll4"; - reg = <0x0001d214 0x32>, - <0x0001c854 0x4>; - clocks = <&osc>; - clock-output-names = "genpll4", "clk_ccn", - "clk_tpiu_pll", "clk_noc", - "clk_chclk_fs4", - "clk_bridge_fscpu"; - }; - - genpll5: genpll5@1d248 { - #clock-cells = <1>; - compatible = "brcm,sr-genpll5"; - reg = <0x0001d248 0x32>, - <0x0001c870 0x4>; - clocks = <&osc>; - clock-output-names = "genpll5", "clk_fs4_hf", - "clk_crypto_ae", "clk_raid_ae"; - }; - - lcpll0: lcpll0@1d0c4 { - #clock-cells = <1>; - compatible = "brcm,sr-lcpll0"; - reg = <0x0001d0c4 0x3c>, - <0x0001c870 0x4>; - clocks = <&osc>; - clock-output-names = "lcpll0", "clk_sata_refp", - "clk_sata_refn", "clk_sata_350", - "clk_sata_500"; - }; - - lcpll1: lcpll1@1d138 { - #clock-cells = <1>; - compatible = "brcm,sr-lcpll1"; - reg = <0x0001d138 0x3c>, - <0x0001c870 0x4>; - clocks = <&osc>; - clock-output-names = "lcpll1", "clk_wan", - "clk_usb_ref", - "clk_crmu_ts"; - }; - - hsls_clk: hsls_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll3 1>; - clock-div = <1>; - clock-mult = <1>; - }; - - hsls_div2_clk: hsls_div2_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>; - clock-div = <2>; - clock-mult = <1>; - - }; - - hsls_div4_clk: hsls_div4_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>; - clock-div = <4>; - clock-mult = <1>; - }; - - hsls_25m_clk: hsls_25m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&crmu_ref25m>; - clock-div = <1>; - clock-mult = <1>; - }; - - hsls_25m_div2_clk: hsls_25m_div2_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&hsls_25m_clk>; - clock-div = <2>; - clock-mult = <1>; - }; - - sdio0_clk: sdio0_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>; - clock-div = <1>; - clock-mult = <1>; - }; - - sdio1_clk: sdio1_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>; - clock-div = <1>; - clock-mult = <1>; - }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi deleted file mode 100644 index 9666969c8..000000000 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi +++ /dev/null @@ -1,118 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016-2017 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - - fs4: fs4 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x67000000 0x00800000>; - - crypto_mbox: crypto_mbox@0 { - compatible = "brcm,iproc-flexrm-mbox"; - reg = <0x00000000 0x200000>; - msi-parent = <&gic_its 0x4100>; - #mbox-cells = <3>; - dma-coherent; - }; - - raid_mbox: raid_mbox@400000 { - compatible = "brcm,iproc-flexrm-mbox"; - reg = <0x00400000 0x200000>; - dma-coherent; - msi-parent = <&gic_its 0x4300>; - #mbox-cells = <3>; - }; - - raid0: raid@0 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 0 0x1 0xff00>, - <&raid_mbox 1 0x1 0xff00>, - <&raid_mbox 2 0x1 0xff00>, - <&raid_mbox 3 0x1 0xff00>; - }; - - raid1: raid@1 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 4 0x1 0xff00>, - <&raid_mbox 5 0x1 0xff00>, - <&raid_mbox 6 0x1 0xff00>, - <&raid_mbox 7 0x1 0xff00>; - }; - - raid2: raid@2 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 8 0x1 0xff00>, - <&raid_mbox 9 0x1 0xff00>, - <&raid_mbox 10 0x1 0xff00>, - <&raid_mbox 11 0x1 0xff00>; - }; - - raid3: raid@3 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 12 0x1 0xff00>, - <&raid_mbox 13 0x1 0xff00>, - <&raid_mbox 14 0x1 0xff00>, - <&raid_mbox 15 0x1 0xff00>; - }; - - raid4: raid@4 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 16 0x1 0xff00>, - <&raid_mbox 17 0x1 0xff00>, - <&raid_mbox 18 0x1 0xff00>, - <&raid_mbox 19 0x1 0xff00>; - }; - - raid5: raid@5 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 20 0x1 0xff00>, - <&raid_mbox 21 0x1 0xff00>, - <&raid_mbox 22 0x1 0xff00>, - <&raid_mbox 23 0x1 0xff00>; - }; - - raid6: raid@6 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 24 0x1 0xff00>, - <&raid_mbox 25 0x1 0xff00>, - <&raid_mbox 26 0x1 0xff00>, - <&raid_mbox 27 0x1 0xff00>; - }; - - raid7: raid@7 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 28 0x1 0xff00>, - <&raid_mbox 29 0x1 0xff00>, - <&raid_mbox 30 0x1 0xff00>, - <&raid_mbox 31 0x1 0xff00>; - }; - }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi deleted file mode 100644 index 33a472ab1..000000000 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) -/* - *Copyright(c) 2018 Broadcom - */ - -pcie8: pcie@60400000 { - compatible = "brcm,iproc-pcie-paxc-v2"; - reg = <0 0x60400000 0 0x1000>; - linux,pci-domain = <8>; - - bus-range = <0x0 0x1>; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>; - - dma-coherent; - - msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */ - <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */ - <0x101 &gic_its 0x2080 0x1>, /* PF1 */ - <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */ - <0x102 &gic_its 0x2100 0x1>, /* PF2 */ - <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */ - <0x103 &gic_its 0x2180 0x1>, /* PF3 */ - <0x120 &gic_its 0x21d8 0x8>, /* PF3-VF24-31 */ - <0x104 &gic_its 0x2200 0x1>, /* PF4 */ - <0x128 &gic_its 0x2260 0x8>, /* PF4-VF32-39 */ - <0x105 &gic_its 0x2280 0x1>, /* PF5 */ - <0x130 &gic_its 0x22e8 0x8>, /* PF5-VF40-47 */ - <0x106 &gic_its 0x2300 0x1>, /* PF6 */ - <0x138 &gic_its 0x2370 0x8>, /* PF6-VF48-55 */ - <0x107 &gic_its 0x2380 0x1>, /* PF7 */ - <0x140 &gic_its 0x23f8 0x8>; /* PF7-VF56-63 */ - - phys = <&pcie_phy 8>; - phy-names = "pcie-phy"; -}; - -pcie-ss { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x40000000 0x800>; - - pcie_phy: phy@0 { - compatible = "brcm,sr-pcie-phy"; - reg = <0x0 0x200>; - brcm,sr-cdru = <&cdru>; - brcm,sr-mhb = <&mhb>; - #phy-cells = <1>; - }; -}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi deleted file mode 100644 index 56789ccf9..000000000 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi +++ /dev/null @@ -1,346 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016-2017 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - - pinconf: pinconf@140000 { - compatible = "pinconf-single"; - reg = <0x00140000 0x250>; - pinctrl-single,register-width = <32>; - - /* pinconf functions */ - }; - - pinmux: pinmux@14029c { - compatible = "pinctrl-single"; - reg = <0x0014029c 0x26c>; - #address-cells = <1>; - #size-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xf>; - pinctrl-single,gpio-range = < - &range 0 91 MODE_GPIO - &range 95 60 MODE_GPIO - >; - range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; - - /* pinctrl functions */ - tsio_pins: pinmux_gpio_14 { - pinctrl-single,pins = < - 0x038 MODE_NITRO /* tsio_0 */ - 0x03c MODE_NITRO /* tsio_1 */ - >; - }; - - nor_pins: pinmux_pnor_adv_n { - pinctrl-single,pins = < - 0x0ac MODE_PNOR /* nand_ce1_n */ - 0x0b0 MODE_PNOR /* nand_ce0_n */ - 0x0b4 MODE_PNOR /* nand_we_n */ - 0x0b8 MODE_PNOR /* nand_wp_n */ - 0x0bc MODE_PNOR /* nand_re_n */ - 0x0c0 MODE_PNOR /* nand_rdy_bsy_n */ - 0x0c4 MODE_PNOR /* nand_io0_0 */ - 0x0c8 MODE_PNOR /* nand_io1_0 */ - 0x0cc MODE_PNOR /* nand_io2_0 */ - 0x0d0 MODE_PNOR /* nand_io3_0 */ - 0x0d4 MODE_PNOR /* nand_io4_0 */ - 0x0d8 MODE_PNOR /* nand_io5_0 */ - 0x0dc MODE_PNOR /* nand_io6_0 */ - 0x0e0 MODE_PNOR /* nand_io7_0 */ - 0x0e4 MODE_PNOR /* nand_io8_0 */ - 0x0e8 MODE_PNOR /* nand_io9_0 */ - 0x0ec MODE_PNOR /* nand_io10_0 */ - 0x0f0 MODE_PNOR /* nand_io11_0 */ - 0x0f4 MODE_PNOR /* nand_io12_0 */ - 0x0f8 MODE_PNOR /* nand_io13_0 */ - 0x0fc MODE_PNOR /* nand_io14_0 */ - 0x100 MODE_PNOR /* nand_io15_0 */ - 0x104 MODE_PNOR /* nand_ale_0 */ - 0x108 MODE_PNOR /* nand_cle_0 */ - 0x040 MODE_PNOR /* pnor_adv_n */ - 0x044 MODE_PNOR /* pnor_baa_n */ - 0x048 MODE_PNOR /* pnor_bls_0_n */ - 0x04c MODE_PNOR /* pnor_bls_1_n */ - 0x050 MODE_PNOR /* pnor_cre */ - 0x054 MODE_PNOR /* pnor_cs_2_n */ - 0x058 MODE_PNOR /* pnor_cs_1_n */ - 0x05c MODE_PNOR /* pnor_cs_0_n */ - 0x060 MODE_PNOR /* pnor_we_n */ - 0x064 MODE_PNOR /* pnor_oe_n */ - 0x068 MODE_PNOR /* pnor_intr */ - 0x06c MODE_PNOR /* pnor_dat_0 */ - 0x070 MODE_PNOR /* pnor_dat_1 */ - 0x074 MODE_PNOR /* pnor_dat_2 */ - 0x078 MODE_PNOR /* pnor_dat_3 */ - 0x07c MODE_PNOR /* pnor_dat_4 */ - 0x080 MODE_PNOR /* pnor_dat_5 */ - 0x084 MODE_PNOR /* pnor_dat_6 */ - 0x088 MODE_PNOR /* pnor_dat_7 */ - 0x08c MODE_PNOR /* pnor_dat_8 */ - 0x090 MODE_PNOR /* pnor_dat_9 */ - 0x094 MODE_PNOR /* pnor_dat_10 */ - 0x098 MODE_PNOR /* pnor_dat_11 */ - 0x09c MODE_PNOR /* pnor_dat_12 */ - 0x0a0 MODE_PNOR /* pnor_dat_13 */ - 0x0a4 MODE_PNOR /* pnor_dat_14 */ - 0x0a8 MODE_PNOR /* pnor_dat_15 */ - >; - }; - - nand_pins: pinmux_nand_ce1_n { - pinctrl-single,pins = < - 0x0ac MODE_NAND /* nand_ce1_n */ - 0x0b0 MODE_NAND /* nand_ce0_n */ - 0x0b4 MODE_NAND /* nand_we_n */ - 0x0b8 MODE_NAND /* nand_wp_n */ - 0x0bc MODE_NAND /* nand_re_n */ - 0x0c0 MODE_NAND /* nand_rdy_bsy_n */ - 0x0c4 MODE_NAND /* nand_io0_0 */ - 0x0c8 MODE_NAND /* nand_io1_0 */ - 0x0cc MODE_NAND /* nand_io2_0 */ - 0x0d0 MODE_NAND /* nand_io3_0 */ - 0x0d4 MODE_NAND /* nand_io4_0 */ - 0x0d8 MODE_NAND /* nand_io5_0 */ - 0x0dc MODE_NAND /* nand_io6_0 */ - 0x0e0 MODE_NAND /* nand_io7_0 */ - 0x0e4 MODE_NAND /* nand_io8_0 */ - 0x0e8 MODE_NAND /* nand_io9_0 */ - 0x0ec MODE_NAND /* nand_io10_0 */ - 0x0f0 MODE_NAND /* nand_io11_0 */ - 0x0f4 MODE_NAND /* nand_io12_0 */ - 0x0f8 MODE_NAND /* nand_io13_0 */ - 0x0fc MODE_NAND /* nand_io14_0 */ - 0x100 MODE_NAND /* nand_io15_0 */ - 0x104 MODE_NAND /* nand_ale_0 */ - 0x108 MODE_NAND /* nand_cle_0 */ - >; - }; - - pwm0_pins: pinmux_pwm_0 { - pinctrl-single,pins = < - 0x10c MODE_NITRO - >; - }; - - pwm1_pins: pinmux_pwm_1 { - pinctrl-single,pins = < - 0x110 MODE_NITRO - >; - }; - - pwm2_pins: pinmux_pwm_2 { - pinctrl-single,pins = < - 0x114 MODE_NITRO - >; - }; - - pwm3_pins: pinmux_pwm_3 { - pinctrl-single,pins = < - 0x118 MODE_NITRO - >; - }; - - dbu_rxd_pins: pinmux_uart1_sin_nitro { - pinctrl-single,pins = < - 0x11c MODE_NITRO /* dbu_rxd */ - 0x120 MODE_NITRO /* dbu_txd */ - >; - }; - - uart1_pins: pinmux_uart1_sin_nand { - pinctrl-single,pins = < - 0x11c MODE_NAND /* uart1_sin */ - 0x120 MODE_NAND /* uart1_out */ - >; - }; - - uart2_pins: pinmux_uart2_sin { - pinctrl-single,pins = < - 0x124 MODE_NITRO /* uart2_sin */ - 0x128 MODE_NITRO /* uart2_out */ - >; - }; - - uart3_pins: pinmux_uart3_sin { - pinctrl-single,pins = < - 0x12c MODE_NITRO /* uart3_sin */ - 0x130 MODE_NITRO /* uart3_out */ - >; - }; - - i2s_pins: pinmux_i2s_bitclk { - pinctrl-single,pins = < - 0x134 MODE_NITRO /* i2s_bitclk */ - 0x138 MODE_NITRO /* i2s_sdout */ - 0x13c MODE_NITRO /* i2s_sdin */ - 0x140 MODE_NITRO /* i2s_ws */ - 0x144 MODE_NITRO /* i2s_mclk */ - 0x148 MODE_NITRO /* i2s_spdif_out */ - >; - }; - - qspi_pins: pinumx_qspi_hold_n { - pinctrl-single,pins = < - 0x14c MODE_NAND /* qspi_hold_n */ - 0x150 MODE_NAND /* qspi_wp_n */ - 0x154 MODE_NAND /* qspi_sck */ - 0x158 MODE_NAND /* qspi_cs_n */ - 0x15c MODE_NAND /* qspi_mosi */ - 0x160 MODE_NAND /* qspi_miso */ - >; - }; - - mdio_pins: pinumx_ext_mdio { - pinctrl-single,pins = < - 0x164 MODE_NITRO /* ext_mdio */ - 0x168 MODE_NITRO /* ext_mdc */ - >; - }; - - i2c0_pins: pinmux_i2c0_sda { - pinctrl-single,pins = < - 0x16c MODE_NITRO /* i2c0_sda */ - 0x170 MODE_NITRO /* i2c0_scl */ - >; - }; - - i2c1_pins: pinmux_i2c1_sda { - pinctrl-single,pins = < - 0x174 MODE_NITRO /* i2c1_sda */ - 0x178 MODE_NITRO /* i2c1_scl */ - >; - }; - - sdio0_pins: pinmux_sdio0_cd_l { - pinctrl-single,pins = < - 0x17c MODE_NITRO /* sdio0_cd_l */ - 0x180 MODE_NITRO /* sdio0_clk_sdcard */ - 0x184 MODE_NITRO /* sdio0_data0 */ - 0x188 MODE_NITRO /* sdio0_data1 */ - 0x18c MODE_NITRO /* sdio0_data2 */ - 0x190 MODE_NITRO /* sdio0_data3 */ - 0x194 MODE_NITRO /* sdio0_data4 */ - 0x198 MODE_NITRO /* sdio0_data5 */ - 0x19c MODE_NITRO /* sdio0_data6 */ - 0x1a0 MODE_NITRO /* sdio0_data7 */ - 0x1a4 MODE_NITRO /* sdio0_cmd */ - 0x1a8 MODE_NITRO /* sdio0_emmc_rst_n */ - 0x1ac MODE_NITRO /* sdio0_led_on */ - 0x1b0 MODE_NITRO /* sdio0_wp */ - >; - }; - - sdio1_pins: pinmux_sdio1_cd_l { - pinctrl-single,pins = < - 0x1b4 MODE_NITRO /* sdio1_cd_l */ - 0x1b8 MODE_NITRO /* sdio1_clk_sdcard */ - 0x1bc MODE_NITRO /* sdio1_data0 */ - 0x1c0 MODE_NITRO /* sdio1_data1 */ - 0x1c4 MODE_NITRO /* sdio1_data2 */ - 0x1c8 MODE_NITRO /* sdio1_data3 */ - 0x1cc MODE_NITRO /* sdio1_data4 */ - 0x1d0 MODE_NITRO /* sdio1_data5 */ - 0x1d4 MODE_NITRO /* sdio1_data6 */ - 0x1d8 MODE_NITRO /* sdio1_data7 */ - 0x1dc MODE_NITRO /* sdio1_cmd */ - 0x1e0 MODE_NITRO /* sdio1_emmc_rst_n */ - 0x1e4 MODE_NITRO /* sdio1_led_on */ - 0x1e8 MODE_NITRO /* sdio1_wp */ - >; - }; - - spi0_pins: pinmux_spi0_sck_nand { - pinctrl-single,pins = < - 0x1ec MODE_NITRO /* spi0_sck */ - 0x1f0 MODE_NITRO /* spi0_rxd */ - 0x1f4 MODE_NITRO /* spi0_fss */ - 0x1f8 MODE_NITRO /* spi0_txd */ - >; - }; - - spi1_pins: pinmux_spi1_sck_nand { - pinctrl-single,pins = < - 0x1fc MODE_NITRO /* spi1_sck */ - 0x200 MODE_NITRO /* spi1_rxd */ - 0x204 MODE_NITRO /* spi1_fss */ - 0x208 MODE_NITRO /* spi1_txd */ - >; - }; - - nuart_pins: pinmux_uart0_sin_nitro { - pinctrl-single,pins = < - 0x20c MODE_NITRO /* nuart_rxd */ - 0x210 MODE_NITRO /* nuart_txd */ - >; - }; - - uart0_pins: pinumux_uart0_sin_nand { - pinctrl-single,pins = < - 0x20c MODE_NAND /* uart0_sin */ - 0x210 MODE_NAND /* uart0_out */ - 0x214 MODE_NAND /* uart0_rts */ - 0x218 MODE_NAND /* uart0_cts */ - 0x21c MODE_NAND /* uart0_dtr */ - 0x220 MODE_NAND /* uart0_dcd */ - 0x224 MODE_NAND /* uart0_dsr */ - 0x228 MODE_NAND /* uart0_ri */ - >; - }; - - drdu2_pins: pinmux_drdu2_overcurrent { - pinctrl-single,pins = < - 0x22c MODE_NITRO /* drdu2_overcurrent */ - 0x230 MODE_NITRO /* drdu2_vbus_ppc */ - 0x234 MODE_NITRO /* drdu2_vbus_present */ - 0x238 MODE_NITRO /* drdu2_id */ - >; - }; - - drdu3_pins: pinmux_drdu3_overcurrent { - pinctrl-single,pins = < - 0x23c MODE_NITRO /* drdu3_overcurrent */ - 0x240 MODE_NITRO /* drdu3_vbus_ppc */ - 0x244 MODE_NITRO /* drdu3_vbus_present */ - 0x248 MODE_NITRO /* drdu3_id */ - >; - }; - - usb3h_pins: pinmux_usb3h_overcurrent { - pinctrl-single,pins = < - 0x24c MODE_NITRO /* usb3h_overcurrent */ - 0x250 MODE_NITRO /* usb3h_vbus_ppc */ - >; - }; - }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi deleted file mode 100644 index 8c68e0c26..000000000 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi +++ /dev/null @@ -1,278 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016-2017 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - - sata { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x67d00000 0x00800000>; - - sata0: ahci@0 { - compatible = "brcm,iproc-ahci", "generic-ahci"; - reg = <0x00000000 0x1000>; - reg-names = "ahci"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata0_port0: sata-port@0 { - reg = <0>; - phys = <&sata0_phy0>; - phy-names = "sata-phy"; - }; - }; - - sata_phy0: sata_phy@2100 { - compatible = "brcm,iproc-sr-sata-phy"; - reg = <0x00002100 0x1000>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata0_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - }; - - sata1: ahci@10000 { - compatible = "brcm,iproc-ahci", "generic-ahci"; - reg = <0x00010000 0x1000>; - reg-names = "ahci"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata1_port0: sata-port@0 { - reg = <0>; - phys = <&sata1_phy0>; - phy-names = "sata-phy"; - }; - }; - - sata_phy1: sata_phy@12100 { - compatible = "brcm,iproc-sr-sata-phy"; - reg = <0x00012100 0x1000>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata1_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - }; - - sata2: ahci@20000 { - compatible = "brcm,iproc-ahci", "generic-ahci"; - reg = <0x00020000 0x1000>; - reg-names = "ahci"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata2_port0: sata-port@0 { - reg = <0>; - phys = <&sata2_phy0>; - phy-names = "sata-phy"; - }; - }; - - sata_phy2: sata_phy@22100 { - compatible = "brcm,iproc-sr-sata-phy"; - reg = <0x00022100 0x1000>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata2_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - }; - - sata3: ahci@30000 { - compatible = "brcm,iproc-ahci", "generic-ahci"; - reg = <0x00030000 0x1000>; - reg-names = "ahci"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata3_port0: sata-port@0 { - reg = <0>; - phys = <&sata3_phy0>; - phy-names = "sata-phy"; - }; - }; - - sata_phy3: sata_phy@32100 { - compatible = "brcm,iproc-sr-sata-phy"; - reg = <0x00032100 0x1000>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata3_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - }; - - sata4: ahci@100000 { - compatible = "brcm,iproc-ahci", "generic-ahci"; - reg = <0x00100000 0x1000>; - reg-names = "ahci"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata4_port0: sata-port@0 { - reg = <0>; - phys = <&sata4_phy0>; - phy-names = "sata-phy"; - }; - }; - - sata_phy4: sata_phy@102100 { - compatible = "brcm,iproc-sr-sata-phy"; - reg = <0x00102100 0x1000>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata4_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - }; - - sata5: ahci@110000 { - compatible = "brcm,iproc-ahci", "generic-ahci"; - reg = <0x00110000 0x1000>; - reg-names = "ahci"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata5_port0: sata-port@0 { - reg = <0>; - phys = <&sata5_phy0>; - phy-names = "sata-phy"; - }; - }; - - sata_phy5: sata_phy@112100 { - compatible = "brcm,iproc-sr-sata-phy"; - reg = <0x00112100 0x1000>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata5_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - }; - - sata6: ahci@120000 { - compatible = "brcm,iproc-ahci", "generic-ahci"; - reg = <0x00120000 0x1000>; - reg-names = "ahci"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata6_port0: sata-port@0 { - reg = <0>; - phys = <&sata6_phy0>; - phy-names = "sata-phy"; - }; - }; - - sata_phy6: sata_phy@122100 { - compatible = "brcm,iproc-sr-sata-phy"; - reg = <0x00122100 0x1000>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata6_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - }; - - sata7: ahci@130000 { - compatible = "brcm,iproc-ahci", "generic-ahci"; - reg = <0x00130000 0x1000>; - reg-names = "ahci"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata7_port0: sata-port@0 { - reg = <0>; - phys = <&sata7_phy0>; - phy-names = "sata-phy"; - }; - }; - - sata_phy7: sata_phy@132100 { - compatible = "brcm,iproc-sr-sata-phy"; - reg = <0x00132100 0x1000>; - reg-names = "phy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata7_phy0: sata-phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - }; - }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi deleted file mode 100644 index 5401a646c..000000000 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) -/* - *Copyright(c) 2018 Broadcom - */ - usb { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x68500000 0x0 0x00400000>; - - /* - * Internally, USB bus to the interconnect can only address up - * to 40-bit - */ - dma-ranges = <0 0 0 0 0x100 0x0>; - - usbphy0: usb-phy@0 { - compatible = "brcm,sr-usb-combo-phy"; - reg = <0x0 0x00000000 0x0 0x100>; - #phy-cells = <1>; - status = "disabled"; - }; - - xhci0: usb@1000 { - compatible = "generic-xhci"; - reg = <0x0 0x00001000 0x0 0x1000>; - interrupts = ; - phys = <&usbphy0 1>, <&usbphy0 0>; - phy-names = "phy0", "phy1"; - dma-coherent; - status = "disabled"; - }; - - bdc0: usb@2000 { - compatible = "brcm,bdc-v0.16"; - reg = <0x0 0x00002000 0x0 0x1000>; - interrupts = ; - phys = <&usbphy0 0>, <&usbphy0 1>; - phy-names = "phy0", "phy1"; - dma-coherent; - status = "disabled"; - }; - - usbphy1: usb-phy@10000 { - compatible = "brcm,sr-usb-combo-phy"; - reg = <0x0 0x00010000 0x0 0x100>; - #phy-cells = <1>; - status = "disabled"; - }; - - usbphy2: usb-phy@20000 { - compatible = "brcm,sr-usb-hs-phy"; - reg = <0x0 0x00020000 0x0 0x100>; - #phy-cells = <0>; - status = "disabled"; - }; - - xhci1: usb@11000 { - compatible = "generic-xhci"; - reg = <0x0 0x00011000 0x0 0x1000>; - interrupts = ; - phys = <&usbphy1 1>, <&usbphy2>, <&usbphy1 0>; - phy-names = "phy0", "phy1", "phy2"; - dma-coherent; - status = "disabled"; - }; - - bdc1: usb@21000 { - compatible = "brcm,bdc-v0.16"; - reg = <0x0 0x00021000 0x0 0x1000>; - interrupts = ; - phys = <&usbphy2>; - phy-names = "phy0"; - dma-coherent; - status = "disabled"; - }; - }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi deleted file mode 100644 index b425b12c3..000000000 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ /dev/null @@ -1,722 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015-2017 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -/ { - compatible = "brcm,stingray"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - }; - - cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&CLUSTER1_L2>; - }; - - cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x101>; - enable-method = "psci"; - next-level-cache = <&CLUSTER1_L2>; - }; - - cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x200>; - enable-method = "psci"; - next-level-cache = <&CLUSTER2_L2>; - }; - - cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x201>; - enable-method = "psci"; - next-level-cache = <&CLUSTER2_L2>; - }; - - cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x300>; - enable-method = "psci"; - next-level-cache = <&CLUSTER3_L2>; - }; - - cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0 0x301>; - enable-method = "psci"; - next-level-cache = <&CLUSTER3_L2>; - }; - - CLUSTER0_L2: l2-cache@0 { - compatible = "cache"; - }; - - CLUSTER1_L2: l2-cache@100 { - compatible = "cache"; - }; - - CLUSTER2_L2: l2-cache@200 { - compatible = "cache"; - }; - - CLUSTER3_L2: l2-cache@300 { - compatible = "cache"; - }; - }; - - memory: memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x40000000>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - mhb: syscon@60401000 { - compatible = "brcm,sr-mhb", "syscon"; - reg = <0 0x60401000 0 0x38c>; - }; - - scr { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x61000000 0x05000000>; - - ccn: ccn@0 { - compatible = "arm,ccn-502"; - reg = <0x00000000 0x900000>; - interrupts = ; - }; - - gic: interrupt-controller@2c00000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-controller; - reg = <0x02c00000 0x010000>, /* GICD */ - <0x02e00000 0x600000>; /* GICR */ - interrupts = ; - - gic_its: gic-its@63c20000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x02c20000 0x10000>; - }; - }; - - smmu: mmu@3000000 { - compatible = "arm,mmu-500"; - reg = <0x03000000 0x80000>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - #iommu-cells = <2>; - }; - }; - - crmu: crmu { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x66400000 0x100000>; - - #include "stingray-clock.dtsi" - - otp: otp@1c400 { - compatible = "brcm,ocotp-v2"; - reg = <0x0001c400 0x68>; - brcm,ocotp-size = <2048>; - status = "okay"; - }; - - cdru: syscon@1d000 { - compatible = "brcm,sr-cdru", "syscon"; - reg = <0x0001d000 0x400>; - }; - - gpio_crmu: gpio@24800 { - compatible = "brcm,iproc-gpio"; - reg = <0x00024800 0x4c>; - ngpios = <6>; - #gpio-cells = <2>; - gpio-controller; - }; - }; - - #include "stingray-fs4.dtsi" - #include "stingray-sata.dtsi" - #include "stingray-pcie.dtsi" - #include "stingray-usb.dtsi" - - hsls { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x68900000 0x17700000>; - - #include "stingray-pinctrl.dtsi" - - mdio_mux_iproc: mdio-mux@20000 { - compatible = "brcm,mdio-mux-iproc"; - reg = <0x00020000 0x250>; - #address-cells = <1>; - #size-cells = <0>; - - mdio@0 { /* PCIe serdes */ - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - mdio@2 { /* SATA */ - reg = <0x2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - mdio@3 { /* USB */ - reg = <0x3>; - #address-cells = <1>; - #size-cells = <0>; - }; - - mdio@10 { /* RGMII */ - reg = <0x10>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - pwm: pwm@10000 { - compatible = "brcm,iproc-pwm"; - reg = <0x00010000 0x1000>; - clocks = <&crmu_ref25m>; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer0: timer@30000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00030000 0x1000>; - interrupts = ; - clocks = <&hsls_25m_div2_clk>, - <&hsls_25m_div2_clk>, - <&hsls_div4_clk>; - clock-names = "timer1", "timer2", "apb_pclk"; - status = "disabled"; - }; - - timer1: timer@40000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00040000 0x1000>; - interrupts = ; - clocks = <&hsls_25m_div2_clk>, - <&hsls_25m_div2_clk>, - <&hsls_div4_clk>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - timer2: timer@50000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00050000 0x1000>; - interrupts = ; - clocks = <&hsls_25m_div2_clk>, - <&hsls_25m_div2_clk>, - <&hsls_div4_clk>; - clock-names = "timer1", "timer2", "apb_pclk"; - status = "disabled"; - }; - - timer3: timer@60000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00060000 0x1000>; - interrupts = ; - clocks = <&hsls_25m_div2_clk>, - <&hsls_25m_div2_clk>, - <&hsls_div4_clk>; - clock-names = "timer1", "timer2", "apb_pclk"; - status = "disabled"; - }; - - timer4: timer@70000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00070000 0x1000>; - interrupts = ; - clocks = <&hsls_25m_div2_clk>, - <&hsls_25m_div2_clk>, - <&hsls_div4_clk>; - clock-names = "timer1", "timer2", "apb_pclk"; - status = "disabled"; - }; - - timer5: timer@80000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00080000 0x1000>; - interrupts = ; - clocks = <&hsls_25m_div2_clk>, - <&hsls_25m_div2_clk>, - <&hsls_div4_clk>; - clock-names = "timer1", "timer2", "apb_pclk"; - status = "disabled"; - }; - - timer6: timer@90000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x00090000 0x1000>; - interrupts = ; - clocks = <&hsls_25m_div2_clk>, - <&hsls_25m_div2_clk>, - <&hsls_div4_clk>; - clock-names = "timer1", "timer2", "apb_pclk"; - status = "disabled"; - }; - - timer7: timer@a0000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x000a0000 0x1000>; - interrupts = ; - clocks = <&hsls_25m_div2_clk>, - <&hsls_25m_div2_clk>, - <&hsls_div4_clk>; - clock-names = "timer1", "timer2", "apb_pclk"; - status = "disabled"; - }; - - i2c0: i2c@b0000 { - compatible = "brcm,iproc-i2c"; - reg = <0x000b0000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <100000>; - status = "disabled"; - }; - - wdt0: watchdog@c0000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x000c0000 0x1000>; - interrupts = ; - clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>; - clock-names = "wdog_clk", "apb_pclk"; - timeout-sec = <60>; - }; - - gpio_hsls: gpio@d0000 { - compatible = "brcm,iproc-gpio"; - reg = <0x000d0000 0x864>; - ngpios = <151>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - interrupts = ; - gpio-ranges = <&pinmux 0 0 16>, - <&pinmux 16 71 2>, - <&pinmux 18 131 8>, - <&pinmux 26 83 6>, - <&pinmux 32 123 4>, - <&pinmux 36 43 24>, - <&pinmux 60 89 2>, - <&pinmux 62 73 4>, - <&pinmux 66 95 28>, - <&pinmux 94 127 4>, - <&pinmux 98 139 10>, - <&pinmux 108 16 27>, - <&pinmux 135 77 6>, - <&pinmux 141 67 4>, - <&pinmux 145 149 6>; - }; - - i2c1: i2c@e0000 { - compatible = "brcm,iproc-i2c"; - reg = <0x000e0000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <100000>; - status = "disabled"; - }; - - uart0: uart@100000 { - device_type = "serial"; - compatible = "snps,dw-apb-uart"; - reg = <0x00100000 0x1000>; - reg-shift = <2>; - clock-frequency = <25000000>; - interrupt-parent = <&gic>; - interrupts = ; - status = "disabled"; - }; - - uart1: uart@110000 { - device_type = "serial"; - compatible = "snps,dw-apb-uart"; - reg = <0x00110000 0x1000>; - reg-shift = <2>; - clock-frequency = <25000000>; - interrupt-parent = <&gic>; - interrupts = ; - status = "disabled"; - }; - - uart2: uart@120000 { - device_type = "serial"; - compatible = "snps,dw-apb-uart"; - reg = <0x00120000 0x1000>; - reg-shift = <2>; - clock-frequency = <25000000>; - interrupt-parent = <&gic>; - interrupts = ; - status = "disabled"; - }; - - uart3: uart@130000 { - device_type = "serial"; - compatible = "snps,dw-apb-uart"; - reg = <0x00130000 0x1000>; - reg-shift = <2>; - clock-frequency = <25000000>; - interrupt-parent = <&gic>; - interrupts = ; - status = "disabled"; - }; - - ssp0: spi@180000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x00180000 0x1000>; - interrupts = ; - clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; - clock-names = "spiclk", "apb_pclk"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ssp1: spi@190000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x00190000 0x1000>; - interrupts = ; - clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; - clock-names = "spiclk", "apb_pclk"; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hwrng: hwrng@220000 { - compatible = "brcm,iproc-rng200"; - reg = <0x00220000 0x28>; - }; - - dma0: dma@310000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x00310000 0x1000>; - interrupts = , - , - , - , - , - , - , - , - ; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - clocks = <&hsls_div2_clk>; - clock-names = "apb_pclk"; - iommus = <&smmu 0x6000 0x0000>; - }; - - enet: ethernet@340000{ - compatible = "brcm,amac"; - reg = <0x00340000 0x1000>; - reg-names = "amac_base"; - dma-coherent; - interrupts = ; - status= "disabled"; - }; - - nand: nand@360000 { - compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; - reg = <0x00360000 0x600>, - <0x0050a408 0x600>, - <0x00360f00 0x20>; - reg-names = "nand", "iproc-idm", "iproc-ext"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - brcm,nand-has-wp; - status = "disabled"; - }; - - sdio0: sdhci@3f1000 { - compatible = "brcm,sdhci-iproc"; - reg = <0x003f1000 0x100>; - interrupts = ; - bus-width = <8>; - clocks = <&sdio0_clk>; - iommus = <&smmu 0x6002 0x0000>; - status = "disabled"; - }; - - sdio1: sdhci@3f2000 { - compatible = "brcm,sdhci-iproc"; - reg = <0x003f2000 0x100>; - interrupts = ; - bus-width = <8>; - clocks = <&sdio1_clk>; - iommus = <&smmu 0x6003 0x0000>; - status = "disabled"; - }; - }; - - tmons { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x8f100000 0x100>; - - tmon: tmon@0 { - compatible = "brcm,sr-thermal"; - reg = <0x0 0x40>; - brcm,tmon-mask = <0x3f>; - #thermal-sensor-cells = <1>; - }; - }; - - thermal-zones { - ihost0_thermal: ihost0-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - thermal-sensors = <&tmon 0>; - trips { - cpu-crit { - temperature = <105000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - ihost1_thermal: ihost1-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - thermal-sensors = <&tmon 1>; - trips { - cpu-crit { - temperature = <105000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - ihost2_thermal: ihost2-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - thermal-sensors = <&tmon 2>; - trips { - cpu-crit { - temperature = <105000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - ihost3_thermal: ihost3-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - thermal-sensors = <&tmon 3>; - trips { - cpu-crit { - temperature = <105000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - crmu_thermal: crmu-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - thermal-sensors = <&tmon 4>; - trips { - cpu-crit { - temperature = <105000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - nitro_thermal: nitro-thermal { - polling-delay-passive = <0>; - polling-delay = <1000>; - thermal-sensors = <&tmon 5>; - trips { - cpu-crit { - temperature = <105000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - }; - - nic-hsls { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x7fffffff>; - - nic_i2c0: i2c@60826100 { - compatible = "brcm,iproc-nic-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x60826100 0x100>, - <0x60e00408 0x1000>; - brcm,ape-hsls-addr-mask = <0x03400000>; - clock-frequency = <100000>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/cavium/Makefile b/arch/arm64/boot/dts/cavium/Makefile deleted file mode 100644 index c178f7e06..000000000 --- a/arch/arm64/boot/dts/cavium/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb -dtb-$(CONFIG_ARCH_THUNDER2) += thunder2-99xx.dtb diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dts b/arch/arm64/boot/dts/cavium/thunder-88xx.dts deleted file mode 100644 index 5ec2bfa5f..000000000 --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dts +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Cavium Thunder DTS file - Thunder board description - * - * Copyright (C) 2014, Cavium Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -/include/ "thunder-88xx.dtsi" - -/ { - model = "Cavium ThunderX CN88XX board"; - compatible = "cavium,thunder-88xx"; - - aliases { - serial0 = &uaa0; - serial1 = &uaa1; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x00000000 0x0 0x80000000>; - }; -}; diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi deleted file mode 100644 index e0a717952..000000000 --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi +++ /dev/null @@ -1,415 +0,0 @@ -/* - * Cavium Thunder DTS file - Thunder SoC description - * - * Copyright (C) 2014, Cavium Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/ { - compatible = "cavium,thunder-88xx"; - interrupt-parent = <&gic0>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x000>; - enable-method = "psci"; - }; - cpu@1 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x001>; - enable-method = "psci"; - }; - cpu@2 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x002>; - enable-method = "psci"; - }; - cpu@3 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x003>; - enable-method = "psci"; - }; - cpu@4 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x004>; - enable-method = "psci"; - }; - cpu@5 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x005>; - enable-method = "psci"; - }; - cpu@6 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x006>; - enable-method = "psci"; - }; - cpu@7 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x007>; - enable-method = "psci"; - }; - cpu@8 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x008>; - enable-method = "psci"; - }; - cpu@9 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x009>; - enable-method = "psci"; - }; - cpu@a { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x00a>; - enable-method = "psci"; - }; - cpu@b { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x00b>; - enable-method = "psci"; - }; - cpu@c { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x00c>; - enable-method = "psci"; - }; - cpu@d { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x00d>; - enable-method = "psci"; - }; - cpu@e { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x00e>; - enable-method = "psci"; - }; - cpu@f { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x00f>; - enable-method = "psci"; - }; - cpu@100 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x100>; - enable-method = "psci"; - }; - cpu@101 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x101>; - enable-method = "psci"; - }; - cpu@102 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x102>; - enable-method = "psci"; - }; - cpu@103 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x103>; - enable-method = "psci"; - }; - cpu@104 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x104>; - enable-method = "psci"; - }; - cpu@105 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x105>; - enable-method = "psci"; - }; - cpu@106 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x106>; - enable-method = "psci"; - }; - cpu@107 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x107>; - enable-method = "psci"; - }; - cpu@108 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x108>; - enable-method = "psci"; - }; - cpu@109 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x109>; - enable-method = "psci"; - }; - cpu@10a { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x10a>; - enable-method = "psci"; - }; - cpu@10b { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x10b>; - enable-method = "psci"; - }; - cpu@10c { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x10c>; - enable-method = "psci"; - }; - cpu@10d { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x10d>; - enable-method = "psci"; - }; - cpu@10e { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x10e>; - enable-method = "psci"; - }; - cpu@10f { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x10f>; - enable-method = "psci"; - }; - cpu@200 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x200>; - enable-method = "psci"; - }; - cpu@201 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x201>; - enable-method = "psci"; - }; - cpu@202 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x202>; - enable-method = "psci"; - }; - cpu@203 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x203>; - enable-method = "psci"; - }; - cpu@204 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x204>; - enable-method = "psci"; - }; - cpu@205 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x205>; - enable-method = "psci"; - }; - cpu@206 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x206>; - enable-method = "psci"; - }; - cpu@207 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x207>; - enable-method = "psci"; - }; - cpu@208 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x208>; - enable-method = "psci"; - }; - cpu@209 { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x209>; - enable-method = "psci"; - }; - cpu@20a { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x20a>; - enable-method = "psci"; - }; - cpu@20b { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x20b>; - enable-method = "psci"; - }; - cpu@20c { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x20c>; - enable-method = "psci"; - }; - cpu@20d { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x20d>; - enable-method = "psci"; - }; - cpu@20e { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x20e>; - enable-method = "psci"; - }; - cpu@20f { - device_type = "cpu"; - compatible = "cavium,thunder"; - reg = <0x0 0x20f>; - enable-method = "psci"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 4>, - <1 14 4>, - <1 11 4>, - <1 10 4>; - }; - - pmu { - compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3"; - interrupts = <1 7 4>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - refclk50mhz: refclk50mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "refclk50mhz"; - }; - - gic0: interrupt-controller@8010,00000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */ - <0x8010 0x80000000 0x0 0x600000>; /* GICR */ - interrupts = <1 9 0xf04>; - - its: gic-its@8010,00020000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x8010 0x20000 0x0 0x200000>; - }; - }; - - uaa0: serial@87e0,24000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x87e0 0x24000000 0x0 0x1000>; - interrupts = <1 21 4>; - clocks = <&refclk50mhz>; - clock-names = "apb_pclk"; - }; - - uaa1: serial@87e0,25000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x87e0 0x25000000 0x0 0x1000>; - interrupts = <1 22 4>; - clocks = <&refclk50mhz>; - clock-names = "apb_pclk"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts deleted file mode 100644 index d005e1e79..000000000 --- a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * dts file for Cavium ThunderX2 CN99XX Evaluation Platform - * - * Copyright (c) 2017 Cavium Inc. - * Copyright (c) 2013-2016 Broadcom - */ - -/dts-v1/; - -#include "thunder2-99xx.dtsi" - -/ { - model = "Cavium ThunderX2 CN99XX"; - compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ - <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi deleted file mode 100644 index dfb41705a..000000000 --- a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi +++ /dev/null @@ -1,145 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * dtsi file for Cavium ThunderX2 CN99XX processor - * - * Copyright (c) 2017 Cavium Inc. - * Copyright (c) 2013-2016 Broadcom - * Author: Zi Shen Lim - */ - -#include - -/ { - model = "Cavium ThunderX2 CN99XX"; - compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - /* just 4 cpus now, 128 needed in full config */ - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu@0 { - device_type = "cpu"; - compatible = "cavium,thunder2", "brcm,vulcan"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "cavium,thunder2", "brcm,vulcan"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "cavium,thunder2", "brcm,vulcan"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "cavium,thunder2", "brcm,vulcan"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - gic: interrupt-controller@400080000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ - <0x04 0x01000000 0x0 0x1000000>; /* GICR */ - interrupts = ; - - gicits: gic-its@40010000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; - interrupts = ; /* PMU overflow */ - }; - - clk125mhz: uart_clk125mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "clk125mhz"; - }; - - pcie@30000000 { - compatible = "pci-host-ecam-generic"; - device_type = "pci"; - #interrupt-cells = <1>; - #address-cells = <3>; - #size-cells = <2>; - - /* ECAM at 0x3000_0000 - 0x4000_0000 */ - reg = <0x0 0x30000000 0x0 0x10000000>; - reg-names = "PCI ECAM"; - - /* - * PCI ranges: - * IO no supported - * MEM 0x4000_0000 - 0x6000_0000 - * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 - */ - ranges = - <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 - 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; - bus-range = <0 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = - /* addr pin ic icaddr icintr */ - <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH - 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH - 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH - 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - msi-parent = <&gicits>; - dma-coherent; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - uart0: serial@402020000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x04 0x02020000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - clocks = <&clk125mhz>; - clock-names = "apb_pclk"; - }; - }; - -}; diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile deleted file mode 100644 index e0a2facde..000000000 --- a/arch/arm64/boot/dts/exynos/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_EXYNOS) += \ - exynos5433-tm2.dtb \ - exynos5433-tm2e.dtb \ - exynos7-espresso.dtb diff --git a/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi deleted file mode 100644 index d77b88af9..000000000 --- a/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi +++ /dev/null @@ -1,194 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos5433 SoC Memory interface and AMBA bus device tree source - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * Chanwoo Choi - */ - -&soc { - bus_g2d_400: bus0 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_top CLK_ACLK_G2D_400>; - clock-names = "bus"; - operating-points-v2 = <&bus_g2d_400_opp_table>; - status = "disabled"; - }; - - bus_g2d_266: bus1 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_top CLK_ACLK_G2D_266>; - clock-names = "bus"; - operating-points-v2 = <&bus_g2d_266_opp_table>; - status = "disabled"; - }; - - bus_gscl: bus2 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_top CLK_ACLK_GSCL_333>; - clock-names = "bus"; - operating-points-v2 = <&bus_gscl_opp_table>; - status = "disabled"; - }; - - bus_hevc: bus3 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_top CLK_ACLK_HEVC_400>; - clock-names = "bus"; - operating-points-v2 = <&bus_hevc_opp_table>; - status = "disabled"; - }; - - bus_jpeg: bus4 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_top CLK_SCLK_JPEG_MSCL>; - clock-names = "bus"; - operating-points-v2 = <&bus_g2d_400_opp_table>; - status = "disabled"; - }; - - bus_mfc: bus5 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_top CLK_ACLK_MFC_400>; - clock-names = "bus"; - operating-points-v2 = <&bus_g2d_400_opp_table>; - status = "disabled"; - }; - - bus_mscl: bus6 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_top CLK_ACLK_MSCL_400>; - clock-names = "bus"; - operating-points-v2 = <&bus_g2d_400_opp_table>; - status = "disabled"; - }; - - bus_noc0: bus7 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_top CLK_ACLK_BUS0_400>; - clock-names = "bus"; - operating-points-v2 = <&bus_hevc_opp_table>; - status = "disabled"; - }; - - bus_noc1: bus8 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_top CLK_ACLK_BUS1_400>; - clock-names = "bus"; - operating-points-v2 = <&bus_hevc_opp_table>; - status = "disabled"; - }; - - bus_noc2: bus9 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_mif CLK_ACLK_BUS2_400>; - clock-names = "bus"; - operating-points-v2 = <&bus_noc2_opp_table>; - status = "disabled"; - }; - - bus_g2d_400_opp_table: opp_table2 { - compatible = "operating-points-v2"; - opp-shared; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1075000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <1000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <975000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <962500>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <950000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <937500>; - }; - }; - - bus_g2d_266_opp_table: opp_table3 { - compatible = "operating-points-v2"; - - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; - - bus_gscl_opp_table: opp_table4 { - compatible = "operating-points-v2"; - - opp-333000000 { - opp-hz = /bits/ 64 <333000000>; - }; - opp-222000000 { - opp-hz = /bits/ 64 <222000000>; - }; - opp-166500000 { - opp-hz = /bits/ 64 <166500000>; - }; - }; - - bus_hevc_opp_table: opp_table5 { - compatible = "operating-points-v2"; - opp-shared; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; - - bus_noc2_opp_table: opp_table6 { - compatible = "operating-points-v2"; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi deleted file mode 100644 index 9df7c6559..000000000 --- a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi +++ /dev/null @@ -1,790 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * Chanwoo Choi - * - * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device - * tree nodes are listed in this file. - */ - -#include - -#define PIN(_func, _pin, _pull, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = ; \ - samsung,pin-pud = ; \ - samsung,pin-drv = ; \ - } - -&pinctrl_alive { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - #interrupt-cells = <2>; - }; - - gpa2: gpa2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa3: gpa3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf2: gpf2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf3: gpf3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf4: gpf4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf5: gpf5 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&pinctrl_aud { - gpz0: gpz0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpz1: gpz1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3", - "gpz0-4", "gpz0-5", "gpz0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm0_bus: pcm0-bus { - samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart_aud_bus: uart-aud-bus { - samsung,pins = "gpz1-3", "gpz1-2", "gpz1-1", "gpz1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_cpif { - gpv6: gpv6 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&pinctrl_ese { - gpj2: gpj2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&pinctrl_finger { - gpd5: gpd5 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpd5-0", "gpd5-2", "gpd5-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c6_bus: hs-i2c6-bus { - samsung,pins = "gpd5-3", "gpd5-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_fsys { - gph1: gph1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpr4: gpr4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpr0: gpr0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpr1: gpr1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpr2: gpr2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpr3: gpr3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpr0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpr0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_rdqs: sd0-rdqs { - samsung,pins = "gpr0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_qrdy: sd0-qrdy { - samsung,pins = "gpr0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpr1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpr2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpr2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpr3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus8: sd1-bus-width8 { - samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcie_bus: pcie_bus { - samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpr4-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpr4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpr4-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpr4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_clk_output: sd2-clk-output { - samsung,pins = "gpr4-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd_output: sd2-cmd-output { - samsung,pins = "gpr4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_imem { - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&pinctrl_nfc { - gpj0: gpj0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - hs_i2c4_bus: hs-i2c4-bus { - samsung,pins = "gpj0-1", "gpj0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_peric { - gpv7: gpv7 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb0: gpb0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc2: gpc2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc3: gpc3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg0: gpg0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd2: gpd2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd4: gpd4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd8: gpd8 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd6: gpd6 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd7: gpd7 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg1: gpg1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg2: gpg2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg3: gpg3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - hs_i2c8_bus: hs-i2c8-bus { - samsung,pins = "gpb0-1", "gpb0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c9_bus: hs-i2c9-bus { - samsung,pins = "gpb0-3", "gpb0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", - "gpd4-3", "gpd4-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", - "gpd4-3", "gpd4-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spdif_bus: spdif-bus { - samsung,pins = "gpd4-3", "gpd4-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_spi_pin0: fimc-is-spi-pin0 { - samsung,pins = "gpc3-3", "gpc3-2", "gpc3-1", "gpc3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_spi_pin1: fimc-is-spi-pin1 { - samsung,pins = "gpc3-7", "gpc3-6", "gpc3-5", "gpc3-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_bus: uart0-bus { - samsung,pins = "gpd0-3", "gpd0-2", "gpd0-1", "gpd0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - hs_i2c2_bus: hs-i2c2-bus { - samsung,pins = "gpd0-3", "gpd0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_bus: uart2-bus { - samsung,pins = "gpd1-5", "gpd1-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - uart1_bus: uart1-bus { - samsung,pins = "gpd1-3", "gpd1-2", "gpd1-1", "gpd1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - }; - - hs_i2c3_bus: hs-i2c3-bus { - samsung,pins = "gpd1-3", "gpd1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c0_bus: hs-i2c0-bus { - samsung,pins = "gpd2-1", "gpd2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c1_bus: hs-i2c1-bus { - samsung,pins = "gpd2-3", "gpd2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpd2-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpd2-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpd2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpd2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpd6-2", "gpd6-4", "gpd6-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c7_bus: hs-i2c7-bus { - samsung,pins = "gpd2-7", "gpd2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpd8-0", "gpd6-0", "gpd6-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c10_bus: hs-i2c10-bus { - samsung,pins = "gpg3-1", "gpg3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c11_bus: hs-i2c11-bus { - samsung,pins = "gpg3-3", "gpg3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi3_bus: spi3-bus { - samsung,pins = "gpg3-4", "gpg3-6", "gpg3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi4_bus: spi4-bus { - samsung,pins = "gpv7-1", "gpv7-3", "gpv7-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_uart: fimc-is-uart { - samsung,pins = "gpc1-1", "gpc0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_ch0_i2c: fimc-is-ch0_i2c { - samsung,pins = "gpc2-1", "gpc2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_ch0_mclk: fimc-is-ch0_mclk { - samsung,pins = "gpd7-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_ch1_i2c: fimc-is-ch1-i2c { - samsung,pins = "gpc2-3", "gpc2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_ch1_mclk: fimc-is-ch1-mclk { - samsung,pins = "gpd7-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_ch2_i2c: fimc-is-ch2-i2c { - samsung,pins = "gpc2-5", "gpc2-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - fimc_is_ch2_mclk: fimc-is-ch2-mclk { - samsung,pins = "gpd7-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_touch { - gpj1: gpj1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - hs_i2c5_bus: hs-i2c5-bus { - samsung,pins = "gpj1-1", "gpj1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi deleted file mode 100644 index 106397a99..000000000 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ /dev/null @@ -1,1333 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos5433 TM2 board device tree source - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * - * Common device tree source file for Samsung's TM2 and TM2E boards - * which are based on Samsung Exynos5433 SoC. - */ - -/dts-v1/; -#include "exynos5433.dtsi" -#include -#include -#include -#include -#include - -/ { - aliases { - gsc0 = &gsc_0; - gsc1 = &gsc_1; - gsc2 = &gsc_2; - pinctrl0 = &pinctrl_alive; - pinctrl1 = &pinctrl_aud; - pinctrl2 = &pinctrl_cpif; - pinctrl3 = &pinctrl_ese; - pinctrl4 = &pinctrl_finger; - pinctrl5 = &pinctrl_fsys; - pinctrl6 = &pinctrl_imem; - pinctrl7 = &pinctrl_nfc; - pinctrl8 = &pinctrl_peric; - pinctrl9 = &pinctrl_touch; - serial0 = &serial_0; - serial1 = &serial_1; - serial2 = &serial_2; - serial3 = &serial_3; - spi0 = &spi_0; - spi1 = &spi_1; - spi2 = &spi_2; - spi3 = &spi_3; - spi4 = &spi_4; - mshc0 = &mshc_0; - mshc2 = &mshc_2; - }; - - chosen { - stdout-path = &serial_1; - }; - - memory@20000000 { - device_type = "memory"; - reg = <0x0 0x20000000 0x0 0xc0000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power-key { - gpios = <&gpa2 7 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "power key"; - debounce-interval = <10>; - }; - - volume-up-key { - gpios = <&gpa2 0 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "volume-up key"; - debounce-interval = <10>; - }; - - volume-down-key { - gpios = <&gpa2 1 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "volume-down key"; - debounce-interval = <10>; - }; - - homepage-key { - gpios = <&gpa0 3 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "homepage key"; - debounce-interval = <10>; - }; - }; - - i2c_max98504: i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpd0 1 GPIO_ACTIVE_HIGH>; - scl-gpios = <&gpd0 0 GPIO_ACTIVE_HIGH>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - max98504: max98504@31 { - compatible = "maxim,max98504"; - reg = <0x31>; - maxim,rx-path = <1>; - maxim,tx-path = <1>; - maxim,tx-channel-mask = <3>; - maxim,tx-channel-source = <2>; - }; - }; - - irda_regulator: irda-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpr3 3 GPIO_ACTIVE_HIGH>; - regulator-name = "irda_regulator"; - }; - - sound { - compatible = "samsung,tm2-audio"; - audio-codec = <&wm5110>, <&hdmi>; - i2s-controller = <&i2s0 0>, <&i2s1 0>; - audio-amplifier = <&max98504>; - mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>; - model = "wm5110"; - samsung,audio-routing = - /* Headphone */ - "HP", "HPOUT1L", - "HP", "HPOUT1R", - - /* Speaker */ - "SPK", "SPKOUT", - "SPKOUT", "HPOUT2L", - "SPKOUT", "HPOUT2R", - - /* Receiver */ - "RCV", "HPOUT3L", - "RCV", "HPOUT3R"; - status = "okay"; - }; -}; - -&adc { - vdd-supply = <&ldo3_reg>; - status = "okay"; - - thermistor-ap { - compatible = "murata,ncp03wf104"; - pullup-uv = <1800000>; - pullup-ohm = <100000>; - pulldown-ohm = <0>; - io-channels = <&adc 0>; - }; - - thermistor-battery { - compatible = "murata,ncp03wf104"; - pullup-uv = <1800000>; - pullup-ohm = <100000>; - pulldown-ohm = <0>; - io-channels = <&adc 1>; - #thermal-sensor-cells = <0>; - }; - - thermistor-charger { - compatible = "murata,ncp03wf104"; - pullup-uv = <1800000>; - pullup-ohm = <100000>; - pulldown-ohm = <0>; - io-channels = <&adc 2>; - }; -}; - -&bus_g2d_400 { - devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>; - vdd-supply = <&buck4_reg>; - exynos,saturation-ratio = <10>; - status = "okay"; -}; - -&bus_g2d_266 { - devfreq = <&bus_g2d_400>; - status = "okay"; -}; - -&bus_gscl { - devfreq = <&bus_g2d_400>; - status = "okay"; -}; - -&bus_hevc { - devfreq = <&bus_g2d_400>; - status = "okay"; -}; - -&bus_jpeg { - devfreq = <&bus_g2d_400>; - status = "okay"; -}; - -&bus_mfc { - devfreq = <&bus_g2d_400>; - status = "okay"; -}; - -&bus_mscl { - devfreq = <&bus_g2d_400>; - status = "okay"; -}; - -&bus_noc0 { - devfreq = <&bus_g2d_400>; - status = "okay"; -}; - -&bus_noc1 { - devfreq = <&bus_g2d_400>; - status = "okay"; -}; - -&bus_noc2 { - devfreq = <&bus_g2d_400>; - status = "okay"; -}; - -&cmu_aud { - assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>, - <&cmu_aud CLK_MOUT_SCLK_AUD_I2S>, - <&cmu_aud CLK_MOUT_SCLK_AUD_PCM>, - <&cmu_top CLK_MOUT_AUD_PLL>, - <&cmu_top CLK_MOUT_AUD_PLL_USER_T>, - <&cmu_top CLK_MOUT_SCLK_AUDIO0>, - <&cmu_top CLK_MOUT_SCLK_AUDIO1>, - <&cmu_top CLK_MOUT_SCLK_SPDIF>, - - <&cmu_aud CLK_DIV_AUD_CA5>, - <&cmu_aud CLK_DIV_ACLK_AUD>, - <&cmu_aud CLK_DIV_PCLK_DBG_AUD>, - <&cmu_aud CLK_DIV_SCLK_AUD_I2S>, - <&cmu_aud CLK_DIV_SCLK_AUD_PCM>, - <&cmu_aud CLK_DIV_SCLK_AUD_SLIMBUS>, - <&cmu_aud CLK_DIV_SCLK_AUD_UART>, - <&cmu_top CLK_DIV_SCLK_AUDIO0>, - <&cmu_top CLK_DIV_SCLK_AUDIO1>, - <&cmu_top CLK_DIV_SCLK_PCM1>, - <&cmu_top CLK_DIV_SCLK_I2S1>; - - assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>, - <&cmu_aud CLK_MOUT_AUD_PLL_USER>, - <&cmu_aud CLK_MOUT_AUD_PLL_USER>, - <&cmu_top CLK_FOUT_AUD_PLL>, - <&cmu_top CLK_MOUT_AUD_PLL>, - <&cmu_top CLK_MOUT_AUD_PLL_USER_T>, - <&cmu_top CLK_MOUT_AUD_PLL_USER_T>, - <&cmu_top CLK_SCLK_AUDIO0>; - - assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, - <196608001>, <65536001>, <32768001>, <49152001>, - <2048001>, <24576001>, <196608001>, - <24576001>, <98304001>, <2048001>, <49152001>; -}; - -&cmu_fsys { - assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>, - <&cmu_top CLK_MOUT_SCLK_USBHOST30>, - <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>, - <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>, - <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>, - <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>, - <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>, - <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>, - <&cmu_top CLK_DIV_SCLK_USBDRD30>, - <&cmu_top CLK_DIV_SCLK_USBHOST30>; - assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>, - <&cmu_top CLK_MOUT_BUS_PLL_USER>, - <&cmu_top CLK_SCLK_USBDRD30_FSYS>, - <&cmu_top CLK_SCLK_USBHOST30_FSYS>, - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>, - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>, - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>, - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>; - assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, - <66700000>, <66700000>; -}; - -&cmu_gscl { - assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>, - <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>; - assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>, - <&cmu_top CLK_ACLK_GSCL_333>; -}; - -&cmu_mfc { - assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>; - assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>; -}; - -&cmu_mif { - assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DSD_A>, <&cmu_mif CLK_DIV_SCLK_DSD>; - assigned-clock-parents = <&cmu_mif CLK_MOUT_MFC_PLL_DIV2>; - assigned-clock-rates = <0>, <333000000>; -}; - -&cmu_mscl { - assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>, - <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>, - <&cmu_mscl CLK_MOUT_SCLK_JPEG>, - <&cmu_top CLK_MOUT_SCLK_JPEG_A>; - assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>, - <&cmu_top CLK_SCLK_JPEG_MSCL>, - <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>, - <&cmu_top CLK_MOUT_BUS_PLL_USER>; -}; - -&cmu_top { - assigned-clocks = <&cmu_top CLK_FOUT_AUD_PLL>; - assigned-clock-rates = <196608001>; -}; - -&cpu0 { - cpu-supply = <&buck3_reg>; -}; - -&cpu4 { - cpu-supply = <&buck2_reg>; -}; - -&decon { - status = "okay"; -}; - -&decon_tv { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - tv_to_hdmi: endpoint { - remote-endpoint = <&hdmi_to_tv>; - }; - }; - }; -}; - -&dsi { - status = "okay"; - vddcore-supply = <&ldo6_reg>; - vddio-supply = <&ldo7_reg>; - samsung,burst-clock-frequency = <512000000>; - samsung,esc-clock-frequency = <16000000>; - samsung,pll-clock-frequency = <24000000>; - pinctrl-names = "default"; - pinctrl-0 = <&te_irq>; -}; - -&gpu { - mali-supply = <&buck6_reg>; - status = "okay"; -}; - -&hdmi { - hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>; - status = "okay"; - vdd-supply = <&ldo6_reg>; - vdd_osc-supply = <&ldo7_reg>; - vdd_pll-supply = <&ldo6_reg>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - hdmi_to_tv: endpoint { - remote-endpoint = <&tv_to_hdmi>; - }; - }; - - port@1 { - reg = <1>; - hdmi_to_mhl: endpoint { - remote-endpoint = <&mhl_to_hdmi>; - }; - }; - }; -}; - -&hsi2c_0 { - status = "okay"; - clock-frequency = <2500000>; - - s2mps13-pmic@66 { - compatible = "samsung,s2mps13-pmic"; - interrupt-parent = <&gpa0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - reg = <0x66>; - samsung,s2mps11-wrstbi-ground; - - s2mps13_osc: clocks { - compatible = "samsung,s2mps13-clk"; - #clock-cells = <1>; - clock-output-names = "s2mps13_ap", "s2mps13_cp", - "s2mps13_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE_0.9V_AP"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDDQ_MMC2_2.8V_AP"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo3_reg: LDO3 { - regulator-name = "VDD1_E_1.8V_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "VDD10_MIF_PLL_1.0V_AP"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo5_reg: LDO5 { - regulator-name = "VDD10_DPLL_1.0V_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo6_reg: LDO6 { - regulator-name = "VDD10_MIPI2L_1.0V_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD18_MIPI2L_1.8V_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo8_reg: LDO8 { - regulator-name = "VDD18_LLI_1.8V_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo9_reg: LDO9 { - regulator-name = "VDD18_ABB_ETC_1.8V_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo10_reg: LDO10 { - regulator-name = "VDD33_USB30_3.0V_AP"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD_INT_M_1.0V_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo12_reg: LDO12 { - regulator-name = "VDD_KFC_M_1.1V_AP"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - ldo13_reg: LDO13 { - regulator-name = "VDD_G3D_M_0.95V_AP"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <950000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo14_reg: LDO14 { - regulator-name = "VDDQ_M1_LDO_1.2V_AP"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: LDO15 { - regulator-name = "VDDQ_M2_LDO_1.2V_AP"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo16_reg: LDO16 { - regulator-name = "VDDQ_EFUSE"; - regulator-min-microvolt = <1400000>; - regulator-max-microvolt = <3400000>; - regulator-always-on; - }; - - ldo17_reg: LDO17 { - regulator-name = "V_TFLASH_2.8V_AP"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo18_reg: LDO18 { - regulator-name = "V_CODEC_1.8V_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "VDDA_1.8V_COMP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo20_reg: LDO20 { - regulator-name = "VCC_2.8V_AP"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ldo21_reg: LDO21 { - regulator-name = "VT_CAM_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo22_reg: LDO22 { - regulator-name = "CAM_IO_1.8V_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo23_reg: LDO23 { - regulator-name = "CAM_SEN_CORE_1.05V_AP"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo24_reg: LDO24 { - regulator-name = "VT_CAM_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "UNUSED_LDO25"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo26_reg: LDO26 { - regulator-name = "CAM_AF_2.8V_AP"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo27_reg: LDO27 { - regulator-name = "VCC_3.0V_LCD_AP"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo28_reg: LDO28 { - regulator-name = "VCC_1.8V_LCD_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo29_reg: LDO29 { - regulator-name = "VT_CAM_2.8V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo30_reg: LDO30 { - regulator-name = "TSP_AVDD_3.3V_AP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo31_reg: LDO31 { - /* - * LDO31 differs from target to target, - * its definition is in the .dts - */ - }; - - ldo32_reg: LDO32 { - regulator-name = "VTOUCH_1.8V_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo33_reg: LDO33 { - regulator-name = "VTOUCH_LED_3.3V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - }; - - ldo34_reg: LDO34 { - regulator-name = "VCC_1.8V_MHL_AP"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <2100000>; - }; - - ldo35_reg: LDO35 { - regulator-name = "OIS_VM_2.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo36_reg: LDO36 { - regulator-name = "VSIL_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo37_reg: LDO37 { - regulator-name = "VF_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo38_reg: LDO38 { - /* - * LDO38 differs from target to target, - * its definition is in the .dts - */ - }; - - ldo39_reg: LDO39 { - regulator-name = "V_HRM_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo40_reg: LDO40 { - regulator-name = "V_HRM_3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "VDD_MIF_0.9V_AP"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "VDD_EGL_1.0V_AP"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "VDD_KFC_1.0V_AP"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "VDD_INT_0.95V_AP"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "VDD_DISP_CAM0_0.9V_AP"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck6_reg: BUCK6 { - regulator-name = "VDD_G3D_0.9V_AP"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck7_reg: BUCK7 { - regulator-name = "VDD_MEM1_1.2V_AP"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "VDD_LLDO_1.35V_AP"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - buck9_reg: BUCK9 { - regulator-name = "VDD_MLDO_2.0V_AP"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - buck10_reg: BUCK10 { - regulator-name = "vdd_mem2"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - }; - }; -}; - -&hsi2c_4 { - status = "okay"; - - s3fwrn5: nfc@27 { - compatible = "samsung,s3fwrn5-i2c"; - reg = <0x27>; - interrupt-parent = <&gpa1>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; - en-gpios = <&gpf1 4 GPIO_ACTIVE_HIGH>; - wake-gpios = <&gpj0 2 GPIO_ACTIVE_HIGH>; - }; -}; - -&hsi2c_5 { - status = "okay"; - - stmfts: touchscreen@49 { - compatible = "st,stmfts"; - reg = <0x49>; - interrupt-parent = <&gpa1>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - avdd-supply = <&ldo30_reg>; - vdd-supply = <&ldo31_reg>; - }; -}; - -&hsi2c_7 { - status = "okay"; - clock-frequency = <1000000>; - - sii8620@39 { - reg = <0x39>; - compatible = "sil,sii8620"; - cvcc10-supply = <&ldo36_reg>; - iovcc18-supply = <&ldo34_reg>; - interrupt-parent = <&gpf0>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>; - clocks = <&pmu_system_controller 0>; - clock-names = "xtal"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mhl_to_hdmi: endpoint { - remote-endpoint = <&hdmi_to_mhl>; - }; - }; - - port@1 { - reg = <1>; - mhl_to_musb_con: endpoint { - remote-endpoint = <&musb_con_to_mhl>; - }; - }; - }; - }; -}; - -&hsi2c_8 { - status = "okay"; - - max77843@66 { - compatible = "maxim,max77843"; - interrupt-parent = <&gpa1>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - reg = <0x66>; - - muic: max77843-muic { - compatible = "maxim,max77843-muic"; - - musb_con: musb_connector { - compatible = "samsung,usb-connector-11pin", - "usb-b-connector"; - label = "micro-USB"; - type = "micro"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@3 { - reg = <3>; - musb_con_to_mhl: endpoint { - remote-endpoint = <&mhl_to_musb_con>; - }; - }; - }; - }; - - ports { - port { - muic_to_usb: endpoint { - remote-endpoint = <&usb_to_muic>; - }; - }; - }; - }; - - regulators { - compatible = "maxim,max77843-regulator"; - safeout1_reg: SAFEOUT1 { - regulator-name = "SAFEOUT1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <4950000>; - }; - - safeout2_reg: SAFEOUT2 { - regulator-name = "SAFEOUT2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <4950000>; - }; - - charger_reg: CHARGER { - regulator-name = "CHARGER"; - regulator-min-microamp = <100000>; - regulator-max-microamp = <3150000>; - }; - }; - - haptic: max77843-haptic { - compatible = "maxim,max77843-haptic"; - haptic-supply = <&ldo38_reg>; - pwms = <&pwm 0 33670 0>; - pwm-names = "haptic"; - }; - }; -}; - -&hsi2c_11 { - status = "okay"; -}; - -&i2s0 { - status = "okay"; -}; - -&i2s1 { - assigned-clocks = <&i2s1 CLK_I2S_RCLK_SRC>; - assigned-clock-parents = <&cmu_peric CLK_SCLK_I2S1>; - status = "okay"; -}; - -&mshc_0 { - status = "okay"; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - cap-mmc-highspeed; - non-removable; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - samsung,dw-mshc-hs400-timing = <0 3>; - samsung,read-strobe-delay = <90>; - fifo-depth = <0x80>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4 - &sd0_bus8 &sd0_rdqs>; - bus-width = <8>; - assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>; - assigned-clock-rates = <800000000>; -}; - -&mshc_2 { - status = "okay"; - cap-sd-highspeed; - disable-wp; - cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - fifo-depth = <0x80>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; -}; - -&ppmu_d0_general { - status = "okay"; - events { - ppmu_event0_d0_general: ppmu-event0-d0-general { - event-name = "ppmu-event0-d0-general"; - }; - }; -}; - -&ppmu_d1_general { - status = "okay"; - events { - ppmu_event0_d1_general: ppmu-event0-d1-general { - event-name = "ppmu-event0-d1-general"; - }; - }; -}; - -&pinctrl_alive { - pinctrl-names = "default"; - pinctrl-0 = <&initial_alive>; - - initial_alive: initial-state { - PIN(INPUT, gpa0-0, DOWN, FAST_SR1); - PIN(INPUT, gpa0-1, NONE, FAST_SR1); - PIN(INPUT, gpa0-2, DOWN, FAST_SR1); - PIN(INPUT, gpa0-3, NONE, FAST_SR1); - PIN(INPUT, gpa0-4, NONE, FAST_SR1); - PIN(INPUT, gpa0-5, DOWN, FAST_SR1); - PIN(INPUT, gpa0-6, NONE, FAST_SR1); - PIN(INPUT, gpa0-7, NONE, FAST_SR1); - - PIN(INPUT, gpa1-0, UP, FAST_SR1); - PIN(INPUT, gpa1-1, UP, FAST_SR1); - PIN(INPUT, gpa1-2, NONE, FAST_SR1); - PIN(INPUT, gpa1-3, DOWN, FAST_SR1); - PIN(INPUT, gpa1-4, DOWN, FAST_SR1); - PIN(INPUT, gpa1-5, NONE, FAST_SR1); - PIN(INPUT, gpa1-6, NONE, FAST_SR1); - PIN(INPUT, gpa1-7, NONE, FAST_SR1); - - PIN(INPUT, gpa2-0, NONE, FAST_SR1); - PIN(INPUT, gpa2-1, NONE, FAST_SR1); - PIN(INPUT, gpa2-2, NONE, FAST_SR1); - PIN(INPUT, gpa2-3, DOWN, FAST_SR1); - PIN(INPUT, gpa2-4, NONE, FAST_SR1); - PIN(INPUT, gpa2-5, DOWN, FAST_SR1); - PIN(INPUT, gpa2-6, DOWN, FAST_SR1); - PIN(INPUT, gpa2-7, NONE, FAST_SR1); - - PIN(INPUT, gpa3-0, DOWN, FAST_SR1); - PIN(INPUT, gpa3-1, DOWN, FAST_SR1); - PIN(INPUT, gpa3-2, NONE, FAST_SR1); - PIN(INPUT, gpa3-3, DOWN, FAST_SR1); - PIN(INPUT, gpa3-4, NONE, FAST_SR1); - PIN(INPUT, gpa3-5, DOWN, FAST_SR1); - PIN(INPUT, gpa3-6, DOWN, FAST_SR1); - PIN(INPUT, gpa3-7, DOWN, FAST_SR1); - - PIN(INPUT, gpf1-0, NONE, FAST_SR1); - PIN(INPUT, gpf1-1, NONE, FAST_SR1); - PIN(INPUT, gpf1-2, DOWN, FAST_SR1); - PIN(INPUT, gpf1-4, UP, FAST_SR1); - PIN(OUTPUT, gpf1-5, NONE, FAST_SR1); - PIN(INPUT, gpf1-6, DOWN, FAST_SR1); - PIN(INPUT, gpf1-7, DOWN, FAST_SR1); - - PIN(INPUT, gpf2-0, DOWN, FAST_SR1); - PIN(INPUT, gpf2-1, DOWN, FAST_SR1); - PIN(INPUT, gpf2-2, DOWN, FAST_SR1); - PIN(INPUT, gpf2-3, DOWN, FAST_SR1); - - PIN(INPUT, gpf3-0, DOWN, FAST_SR1); - PIN(INPUT, gpf3-1, DOWN, FAST_SR1); - PIN(INPUT, gpf3-2, NONE, FAST_SR1); - PIN(INPUT, gpf3-3, DOWN, FAST_SR1); - - PIN(INPUT, gpf4-0, DOWN, FAST_SR1); - PIN(INPUT, gpf4-1, DOWN, FAST_SR1); - PIN(INPUT, gpf4-2, DOWN, FAST_SR1); - PIN(INPUT, gpf4-3, DOWN, FAST_SR1); - PIN(INPUT, gpf4-4, DOWN, FAST_SR1); - PIN(INPUT, gpf4-5, DOWN, FAST_SR1); - PIN(INPUT, gpf4-6, DOWN, FAST_SR1); - PIN(INPUT, gpf4-7, DOWN, FAST_SR1); - - PIN(INPUT, gpf5-0, DOWN, FAST_SR1); - PIN(INPUT, gpf5-1, DOWN, FAST_SR1); - PIN(INPUT, gpf5-2, DOWN, FAST_SR1); - PIN(INPUT, gpf5-3, DOWN, FAST_SR1); - PIN(OUTPUT, gpf5-4, NONE, FAST_SR1); - PIN(INPUT, gpf5-5, DOWN, FAST_SR1); - PIN(INPUT, gpf5-6, DOWN, FAST_SR1); - PIN(INPUT, gpf5-7, DOWN, FAST_SR1); - }; - - te_irq: te_irq { - samsung,pins = "gpf1-3"; - samsung,pin-function = <0xf>; - }; -}; - -&pinctrl_cpif { - pinctrl-names = "default"; - pinctrl-0 = <&initial_cpif>; - - initial_cpif: initial-state { - PIN(INPUT, gpv6-0, DOWN, FAST_SR1); - PIN(INPUT, gpv6-1, DOWN, FAST_SR1); - }; -}; - -&pinctrl_ese { - pinctrl-names = "default"; - pinctrl-0 = <&initial_ese>; - - initial_ese: initial-state { - PIN(INPUT, gpj2-0, DOWN, FAST_SR1); - PIN(INPUT, gpj2-1, DOWN, FAST_SR1); - PIN(INPUT, gpj2-2, DOWN, FAST_SR1); - }; -}; - -&pinctrl_fsys { - pinctrl-names = "default"; - pinctrl-0 = <&initial_fsys>; - - initial_fsys: initial-state { - PIN(INPUT, gpr3-0, NONE, FAST_SR1); - PIN(INPUT, gpr3-1, DOWN, FAST_SR1); - PIN(INPUT, gpr3-2, DOWN, FAST_SR1); - PIN(INPUT, gpr3-3, DOWN, FAST_SR1); - PIN(INPUT, gpr3-7, NONE, FAST_SR1); - }; -}; - -&pinctrl_imem { - pinctrl-names = "default"; - pinctrl-0 = <&initial_imem>; - - initial_imem: initial-state { - PIN(INPUT, gpf0-0, UP, FAST_SR1); - PIN(INPUT, gpf0-1, UP, FAST_SR1); - PIN(INPUT, gpf0-2, DOWN, FAST_SR1); - PIN(INPUT, gpf0-3, UP, FAST_SR1); - PIN(INPUT, gpf0-4, DOWN, FAST_SR1); - PIN(INPUT, gpf0-5, NONE, FAST_SR1); - PIN(INPUT, gpf0-6, DOWN, FAST_SR1); - PIN(INPUT, gpf0-7, UP, FAST_SR1); - }; -}; - -&pinctrl_nfc { - pinctrl-names = "default"; - pinctrl-0 = <&initial_nfc>; - - initial_nfc: initial-state { - PIN(INPUT, gpj0-2, DOWN, FAST_SR1); - }; -}; - -&pinctrl_peric { - pinctrl-names = "default"; - pinctrl-0 = <&initial_peric>; - - initial_peric: initial-state { - PIN(INPUT, gpv7-0, DOWN, FAST_SR1); - PIN(INPUT, gpv7-1, DOWN, FAST_SR1); - PIN(INPUT, gpv7-2, NONE, FAST_SR1); - PIN(INPUT, gpv7-3, DOWN, FAST_SR1); - PIN(INPUT, gpv7-4, DOWN, FAST_SR1); - PIN(INPUT, gpv7-5, DOWN, FAST_SR1); - - PIN(INPUT, gpb0-4, DOWN, FAST_SR1); - - PIN(INPUT, gpc0-2, DOWN, FAST_SR1); - PIN(INPUT, gpc0-5, DOWN, FAST_SR1); - PIN(INPUT, gpc0-7, DOWN, FAST_SR1); - - PIN(INPUT, gpc1-1, DOWN, FAST_SR1); - - PIN(INPUT, gpc3-4, NONE, FAST_SR1); - PIN(INPUT, gpc3-5, NONE, FAST_SR1); - PIN(INPUT, gpc3-6, NONE, FAST_SR1); - PIN(INPUT, gpc3-7, NONE, FAST_SR1); - - PIN(OUTPUT, gpg0-0, NONE, FAST_SR1); - PIN(2, gpg0-1, DOWN, FAST_SR1); - - PIN(INPUT, gpd2-5, DOWN, FAST_SR1); - - PIN(INPUT, gpd4-0, NONE, FAST_SR1); - PIN(INPUT, gpd4-1, DOWN, FAST_SR1); - PIN(INPUT, gpd4-2, DOWN, FAST_SR1); - PIN(INPUT, gpd4-3, DOWN, FAST_SR1); - PIN(INPUT, gpd4-4, DOWN, FAST_SR1); - - PIN(INPUT, gpd6-3, DOWN, FAST_SR1); - - PIN(INPUT, gpd8-1, UP, FAST_SR1); - - PIN(INPUT, gpg1-0, DOWN, FAST_SR1); - PIN(INPUT, gpg1-1, DOWN, FAST_SR1); - PIN(INPUT, gpg1-2, DOWN, FAST_SR1); - PIN(INPUT, gpg1-3, DOWN, FAST_SR1); - PIN(INPUT, gpg1-4, DOWN, FAST_SR1); - - PIN(INPUT, gpg2-0, DOWN, FAST_SR1); - PIN(INPUT, gpg2-1, DOWN, FAST_SR1); - - PIN(INPUT, gpg3-0, DOWN, FAST_SR1); - PIN(INPUT, gpg3-1, DOWN, FAST_SR1); - PIN(INPUT, gpg3-5, DOWN, FAST_SR1); - }; -}; - -&pinctrl_touch { - pinctrl-names = "default"; - pinctrl-0 = <&initial_touch>; - - initial_touch: initial-state { - PIN(INPUT, gpj1-2, DOWN, FAST_SR1); - }; -}; - -&pwm { - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - status = "okay"; -}; - -&mic { - status = "okay"; -}; - -&pmu_system_controller { - assigned-clocks = <&pmu_system_controller 0>; - assigned-clock-parents = <&xxti>; -}; - -&serial_1 { - status = "okay"; -}; - -&serial_3 { - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <3000000>; - shutdown-gpios = <&gpd4 0 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpr3 7 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpa2 2 GPIO_ACTIVE_HIGH>; - clocks = <&s2mps13_osc S2MPS11_CLK_BT>; - clock-names = "extclk"; - }; -}; - -&spi_1 { - cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>; - status = "okay"; - - wm5110: wm5110-codec@0 { - compatible = "wlf,wm5110"; - reg = <0x0>; - spi-max-frequency = <20000000>; - interrupt-parent = <&gpa0>; - interrupts = <4 IRQ_TYPE_NONE>; - clocks = <&pmu_system_controller 0>, - <&s2mps13_osc S2MPS11_CLK_BT>; - clock-names = "mclk1", "mclk2"; - - gpio-controller; - #gpio-cells = <2>; - - wlf,micd-detect-debounce = <300>; - wlf,micd-bias-start-time = <0x1>; - wlf,micd-rate = <0x7>; - wlf,micd-dbtime = <0x1>; - wlf,micd-force-micbias; - wlf,micd-configs = <0x0 1 0>; - wlf,hpdet-channel = <1>; - wlf,gpsw = <0x1>; - wlf,inmode = <2 0 2 0>; - - wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>; - wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>; - - /* core supplies */ - AVDD-supply = <&ldo18_reg>; - DBVDD1-supply = <&ldo18_reg>; - CPVDD-supply = <&ldo18_reg>; - DBVDD2-supply = <&ldo18_reg>; - DBVDD3-supply = <&ldo18_reg>; - - controller-data { - samsung,spi-feedback-delay = <0>; - }; - }; -}; - -&spi_3 { - status = "okay"; - no-cs-readback; - - irled@0 { - compatible = "ir-spi-led"; - reg = <0x0>; - spi-max-frequency = <5000000>; - power-supply = <&irda_regulator>; - duty-cycle = <60>; - led-active-low; - - controller-data { - samsung,spi-feedback-delay = <0>; - }; - }; -}; - -&timer { - clock-frequency = <24000000>; -}; - -&tmu_atlas0 { - vtmu-supply = <&ldo3_reg>; - status = "okay"; -}; - -&tmu_apollo { - vtmu-supply = <&ldo3_reg>; - status = "okay"; -}; - -&tmu_g3d { - vtmu-supply = <&ldo3_reg>; - status = "okay"; -}; - -&usbdrd30 { - vdd33-supply = <&ldo10_reg>; - vdd10-supply = <&ldo6_reg>; - status = "okay"; -}; - -&usbdrd_dwc3 { - dr_mode = "otg"; -}; - -&usbdrd30_phy { - vbus-supply = <&safeout1_reg>; - status = "okay"; - - port { - usb_to_muic: endpoint { - remote-endpoint = <&muic_to_usb>; - }; - }; -}; - -&xxti { - clock-frequency = <24000000>; -}; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts deleted file mode 100644 index fdd0796b2..000000000 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos5433 TM2 board device tree source - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * - * Device tree source file for Samsung's TM2 board which is based on - * Samsung Exynos5433 SoC. - */ - -#include "exynos5433-tm2-common.dtsi" - -/ { - model = "Samsung TM2 board"; - compatible = "samsung,tm2", "samsung,exynos5433"; -}; - -&cmu_disp { - /* - * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned - * clocks properties for DISP CMU for each board to keep them together - * for easier review and maintenance. - */ - assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>, - <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, - <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>, - <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, - <&cmu_disp CLK_MOUT_SCLK_DSIM0>, - <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, - <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>, - <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>, - <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>, - <&cmu_disp CLK_MOUT_DISP_PLL>, - <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>, - <&cmu_disp CLK_MOUT_SCLK_DSD_USER>; - assigned-clock-parents = <0>, <0>, - <&cmu_mif CLK_ACLK_DISP_333>, - <&cmu_mif CLK_SCLK_DSIM0_DISP>, - <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, - <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, - <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, - <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>, - <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>, - <&cmu_disp CLK_FOUT_DISP_PLL>, - <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, - <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, - <&cmu_mif CLK_SCLK_DSD_DISP>; - assigned-clock-rates = <250000000>, <400000000>; -}; - -&dsi { - panel@0 { - compatible = "samsung,s6e3ha2"; - reg = <0>; - vdd3-supply = <&ldo27_reg>; - vci-supply = <&ldo28_reg>; - reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>; - enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>; - }; -}; - -&hsi2c_9 { - status = "okay"; - - touchkey@20 { - compatible = "cypress,tm2-touchkey"; - reg = <0x20>; - interrupt-parent = <&gpa3>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - vcc-supply = <&ldo32_reg>; - vdd-supply = <&ldo33_reg>; - }; -}; - -&ldo31_reg { - regulator-name = "TSP_VDD_1.85V_AP"; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <1850000>; -}; - -&ldo38_reg { - regulator-name = "VCC_3.0V_MOTOR_AP"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; -}; - -&stmfts { - touchscreen-size-x = <1439>; - touchscreen-size-y = <2559>; -}; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts deleted file mode 100644 index 089fc7a1a..000000000 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos5433 TM2E board device tree source - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * - * Device tree source file for Samsung's TM2E(TM2 EDGE) board which is based on - * Samsung Exynos5433 SoC. - */ - -#include "exynos5433-tm2-common.dtsi" - -/ { - model = "Samsung TM2E board"; - compatible = "samsung,tm2e", "samsung,exynos5433"; -}; - -&cmu_disp { - /* - * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned - * clocks properties for DISP CMU for each board to keep them together - * for easier review and maintenance. - */ - assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>, - <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, - <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>, - <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, - <&cmu_disp CLK_MOUT_SCLK_DSIM0>, - <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, - <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>, - <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>, - <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>, - <&cmu_disp CLK_MOUT_DISP_PLL>, - <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; - assigned-clock-parents = <0>, <0>, - <&cmu_mif CLK_ACLK_DISP_333>, - <&cmu_mif CLK_SCLK_DSIM0_DISP>, - <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, - <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, - <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, - <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>, - <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>, - <&cmu_disp CLK_FOUT_DISP_PLL>, - <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, - <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; - assigned-clock-rates = <278000000>, <400000000>; -}; - -&dsi { - panel@0 { - compatible = "samsung,s6e3hf2"; - reg = <0>; - vdd3-supply = <&ldo27_reg>; - vci-supply = <&ldo28_reg>; - reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>; - enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>; - }; -}; - -&ldo31_reg { - regulator-name = "TSP_VDD_1.8V_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; -}; - -&ldo38_reg { - regulator-name = "VCC_3.3V_MOTOR_AP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; -}; - -&stmfts { - touchscreen-size-x = <1599>; - touchscreen-size-y = <2559>; - touch-key-connected; - ledvdd-supply = <&ldo33_reg>; -}; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi deleted file mode 100644 index 81b72393d..000000000 --- a/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi +++ /dev/null @@ -1,305 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree sources for Exynos5433 thermal zone - * - * Copyright (c) 2016 Chanwoo Choi - */ - -#include - -/ { -thermal-zones { - atlas0_thermal: atlas0-thermal { - thermal-sensors = <&tmu_atlas0>; - polling-delay-passive = <0>; - polling-delay = <0>; - trips { - atlas0_alert_0: atlas0-alert-0 { - temperature = <65000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas0_alert_1: atlas0-alert-1 { - temperature = <70000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas0_alert_2: atlas0-alert-2 { - temperature = <75000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas0_alert_3: atlas0-alert-3 { - temperature = <80000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas0_alert_4: atlas0-alert-4 { - temperature = <85000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas0_alert_5: atlas0-alert-5 { - temperature = <90000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas0_alert_6: atlas0-alert-6 { - temperature = <95000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - }; - - cooling-maps { - map0 { - /* Set maximum frequency as 1800MHz */ - trip = <&atlas0_alert_0>; - cooling-device = <&cpu4 1 2>, <&cpu5 1 2>, - <&cpu6 1 2>, <&cpu7 1 2>; - }; - map1 { - /* Set maximum frequency as 1700MHz */ - trip = <&atlas0_alert_1>; - cooling-device = <&cpu4 2 3>, <&cpu5 2 3>, - <&cpu6 2 3>, <&cpu7 2 3>; - }; - map2 { - /* Set maximum frequency as 1600MHz */ - trip = <&atlas0_alert_2>; - cooling-device = <&cpu4 3 4>, <&cpu5 3 4>, - <&cpu6 3 4>, <&cpu7 3 4>; - }; - map3 { - /* Set maximum frequency as 1500MHz */ - trip = <&atlas0_alert_3>; - cooling-device = <&cpu4 4 5>, <&cpu5 4 5>, - <&cpu6 4 5>, <&cpu7 4 5>; - }; - map4 { - /* Set maximum frequency as 1400MHz */ - trip = <&atlas0_alert_4>; - cooling-device = <&cpu4 5 7>, <&cpu5 5 7>, - <&cpu6 5 7>, <&cpu7 5 7>; - }; - map5 { - /* Set maximum frequencyas 1200MHz */ - trip = <&atlas0_alert_5>; - cooling-device = <&cpu4 7 9>, <&cpu5 7 9>, - <&cpu6 7 9>, <&cpu7 7 9>; - }; - map6 { - /* Set maximum frequency as 1000MHz */ - trip = <&atlas0_alert_6>; - cooling-device = <&cpu4 9 14>, <&cpu5 9 14>, - <&cpu6 9 14>, <&cpu7 9 14>; - }; - }; - }; - - atlas1_thermal: atlas1-thermal { - thermal-sensors = <&tmu_atlas1>; - polling-delay-passive = <0>; - polling-delay = <0>; - trips { - atlas1_alert_0: atlas1-alert-0 { - temperature = <65000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas1_alert_1: atlas1-alert-1 { - temperature = <70000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas1_alert_2: atlas1-alert-2 { - temperature = <75000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas1_alert_3: atlas1-alert-3 { - temperature = <80000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas1_alert_4: atlas1-alert-4 { - temperature = <85000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas1_alert_5: atlas1-alert-5 { - temperature = <90000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - atlas1_alert_6: atlas1-alert-6 { - temperature = <95000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - }; - }; - - g3d_thermal: g3d-thermal { - thermal-sensors = <&tmu_g3d>; - polling-delay-passive = <0>; - polling-delay = <0>; - trips { - g3d_alert_0: g3d-alert-0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - g3d_alert_1: g3d-alert-1 { - temperature = <75000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - g3d_alert_2: g3d-alert-2 { - temperature = <80000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - g3d_alert_3: g3d-alert-3 { - temperature = <85000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - g3d_alert_4: g3d-alert-4 { - temperature = <90000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - g3d_alert_5: g3d-alert-5 { - temperature = <95000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - g3d_alert_6: g3d-alert-6 { - temperature = <100000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - }; - }; - - apollo_thermal: apollo-thermal { - thermal-sensors = <&tmu_apollo>; - polling-delay-passive = <0>; - polling-delay = <0>; - trips { - apollo_alert_0: apollo-alert-0 { - temperature = <65000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - apollo_alert_1: apollo-alert-1 { - temperature = <70000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - apollo_alert_2: apollo-alert-2 { - temperature = <75000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - apollo_alert_3: apollo-alert-3 { - temperature = <80000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - apollo_alert_4: apollo-alert-4 { - temperature = <85000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - apollo_alert_5: apollo-alert-5 { - temperature = <90000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - apollo_alert_6: apollo-alert-6 { - temperature = <95000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - }; - - cooling-maps { - map0 { - /* Set maximum frequency as 1200MHz */ - trip = <&apollo_alert_2>; - cooling-device = <&cpu0 1 2>, <&cpu1 1 2>, - <&cpu2 1 2>, <&cpu3 1 2>; - }; - map1 { - /* Set maximum frequency as 1100MHz */ - trip = <&apollo_alert_3>; - cooling-device = <&cpu0 2 3>, <&cpu1 2 3>, - <&cpu2 2 3>, <&cpu3 2 3>; - }; - map2 { - /* Set maximum frequency as 1000MHz */ - trip = <&apollo_alert_4>; - cooling-device = <&cpu0 3 4>, <&cpu1 3 4>, - <&cpu2 3 4>, <&cpu3 3 4>; - }; - map3 { - /* Set maximum frequency as 900MHz */ - trip = <&apollo_alert_5>; - cooling-device = <&cpu0 4 5>, <&cpu1 4 5>, - <&cpu2 4 5>, <&cpu3 4 5>; - }; - map4 { - /* Set maximum frequency as 800MHz */ - trip = <&apollo_alert_6>; - cooling-device = <&cpu0 5 9>, <&cpu1 5 9>, - <&cpu2 5 9>, <&cpu3 5 9>; - }; - }; - }; - - isp_thermal: isp-thermal { - thermal-sensors = <&tmu_isp>; - polling-delay-passive = <0>; - polling-delay = <0>; - trips { - isp_alert_0: isp-alert-0 { - temperature = <80000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - isp_alert_1: isp-alert-1 { - temperature = <85000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - isp_alert_2: isp-alert-2 { - temperature = <90000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - isp_alert_3: isp-alert-3 { - temperature = <95000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - isp_alert_4: isp-alert-4 { - temperature = <100000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - isp_alert_5: isp-alert-5 { - temperature = <105000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - isp_alert_6: isp-alert-6 { - temperature = <110000>; /* millicelsius */ - hysteresis = <1000>; /* millicelsius */ - type = "active"; - }; - }; - }; -}; -}; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi deleted file mode 100644 index 8eb4576da..000000000 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ /dev/null @@ -1,1850 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos5433 SoC device tree source - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * - * Samsung's Exynos5433 SoC device nodes are listed in this file. - * Exynos5433 based board files can include this file and provide - * values for board specific bindings. - * - * Note: This file does not include device nodes for all the controllers in - * Exynos5433 SoC. As device tree coverage for Exynos5433 increases, - * additional nodes can be added to this file. - */ - -#include -#include - -/ { - compatible = "samsung,exynos5433"; - #address-cells = <2>; - #size-cells = <2>; - - interrupt-parent = <&gic>; - - arm_a53_pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - arm_a57_pmu { - compatible = "arm,cortex-a57-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; - }; - - xxti: clock { - /* XXTI */ - compatible = "fixed-clock"; - clock-output-names = "oscclk"; - #clock-cells = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x100>; - clock-frequency = <1300000000>; - clocks = <&cmu_apollo CLK_SCLK_APOLLO>; - clock-names = "apolloclk"; - operating-points-v2 = <&cluster_a53_opp_table>; - #cooling-cells = <2>; - }; - - cpu1: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x101>; - clock-frequency = <1300000000>; - operating-points-v2 = <&cluster_a53_opp_table>; - #cooling-cells = <2>; - }; - - cpu2: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x102>; - clock-frequency = <1300000000>; - operating-points-v2 = <&cluster_a53_opp_table>; - #cooling-cells = <2>; - }; - - cpu3: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x103>; - clock-frequency = <1300000000>; - operating-points-v2 = <&cluster_a53_opp_table>; - #cooling-cells = <2>; - }; - - cpu4: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - enable-method = "psci"; - reg = <0x0>; - clock-frequency = <1900000000>; - clocks = <&cmu_atlas CLK_SCLK_ATLAS>; - clock-names = "atlasclk"; - operating-points-v2 = <&cluster_a57_opp_table>; - #cooling-cells = <2>; - }; - - cpu5: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - enable-method = "psci"; - reg = <0x1>; - clock-frequency = <1900000000>; - operating-points-v2 = <&cluster_a57_opp_table>; - #cooling-cells = <2>; - }; - - cpu6: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - enable-method = "psci"; - reg = <0x2>; - clock-frequency = <1900000000>; - operating-points-v2 = <&cluster_a57_opp_table>; - #cooling-cells = <2>; - }; - - cpu7: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - enable-method = "psci"; - reg = <0x3>; - clock-frequency = <1900000000>; - operating-points-v2 = <&cluster_a57_opp_table>; - #cooling-cells = <2>; - }; - }; - - cluster_a53_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <900000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <925000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <950000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <975000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1000000>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <1050000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1075000>; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1112500>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1112500>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1150000>; - }; - }; - - cluster_a57_opp_table: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <900000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <900000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <912500>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <912500>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <937500>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <975000>; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1012500>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1037500>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1062500>; - }; - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1087500>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1125000>; - }; - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <1137500>; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <1175000>; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1212500>; - }; - opp-1900000000 { - opp-hz = /bits/ 64 <1900000000>; - opp-microvolt = <1262500>; - }; - }; - - psci { - compatible = "arm,psci"; - method = "smc"; - cpu_off = <0x84000002>; - cpu_on = <0xC4000003>; - }; - - soc: soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x18000000>; - - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; - - cmu_top: clock-controller@10030000 { - compatible = "samsung,exynos5433-cmu-top"; - reg = <0x10030000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_mphy_pll", - "sclk_mfc_pll", - "sclk_bus_pll"; - clocks = <&xxti>, - <&cmu_cpif CLK_SCLK_MPHY_PLL>, - <&cmu_mif CLK_SCLK_MFC_PLL>, - <&cmu_mif CLK_SCLK_BUS_PLL>; - }; - - cmu_cpif: clock-controller@10fc0000 { - compatible = "samsung,exynos5433-cmu-cpif"; - reg = <0x10fc0000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk"; - clocks = <&xxti>; - }; - - cmu_mif: clock-controller@105b0000 { - compatible = "samsung,exynos5433-cmu-mif"; - reg = <0x105b0000 0x2000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_mphy_pll"; - clocks = <&xxti>, - <&cmu_cpif CLK_SCLK_MPHY_PLL>; - }; - - cmu_peric: clock-controller@14c80000 { - compatible = "samsung,exynos5433-cmu-peric"; - reg = <0x14c80000 0x1000>; - #clock-cells = <1>; - }; - - cmu_peris: clock-controller@10040000 { - compatible = "samsung,exynos5433-cmu-peris"; - reg = <0x10040000 0x1000>; - #clock-cells = <1>; - }; - - cmu_fsys: clock-controller@156e0000 { - compatible = "samsung,exynos5433-cmu-fsys"; - reg = <0x156e0000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_ufs_mphy", - "aclk_fsys_200", - "sclk_pcie_100_fsys", - "sclk_ufsunipro_fsys", - "sclk_mmc2_fsys", - "sclk_mmc1_fsys", - "sclk_mmc0_fsys", - "sclk_usbhost30_fsys", - "sclk_usbdrd30_fsys"; - clocks = <&xxti>, - <&cmu_cpif CLK_SCLK_UFS_MPHY>, - <&cmu_top CLK_ACLK_FSYS_200>, - <&cmu_top CLK_SCLK_PCIE_100_FSYS>, - <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, - <&cmu_top CLK_SCLK_MMC2_FSYS>, - <&cmu_top CLK_SCLK_MMC1_FSYS>, - <&cmu_top CLK_SCLK_MMC0_FSYS>, - <&cmu_top CLK_SCLK_USBHOST30_FSYS>, - <&cmu_top CLK_SCLK_USBDRD30_FSYS>; - }; - - cmu_g2d: clock-controller@12460000 { - compatible = "samsung,exynos5433-cmu-g2d"; - reg = <0x12460000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_g2d_266", - "aclk_g2d_400"; - clocks = <&xxti>, - <&cmu_top CLK_ACLK_G2D_266>, - <&cmu_top CLK_ACLK_G2D_400>; - power-domains = <&pd_g2d>; - }; - - cmu_disp: clock-controller@13b90000 { - compatible = "samsung,exynos5433-cmu-disp"; - reg = <0x13b90000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_dsim1_disp", - "sclk_dsim0_disp", - "sclk_dsd_disp", - "sclk_decon_tv_eclk_disp", - "sclk_decon_vclk_disp", - "sclk_decon_eclk_disp", - "sclk_decon_tv_vclk_disp", - "aclk_disp_333"; - clocks = <&xxti>, - <&cmu_mif CLK_SCLK_DSIM1_DISP>, - <&cmu_mif CLK_SCLK_DSIM0_DISP>, - <&cmu_mif CLK_SCLK_DSD_DISP>, - <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, - <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, - <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, - <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, - <&cmu_mif CLK_ACLK_DISP_333>; - power-domains = <&pd_disp>; - }; - - cmu_aud: clock-controller@114c0000 { - compatible = "samsung,exynos5433-cmu-aud"; - reg = <0x114c0000 0x1000>; - #clock-cells = <1>; - clock-names = "oscclk", "fout_aud_pll"; - clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>; - power-domains = <&pd_aud>; - }; - - cmu_bus0: clock-controller@13600000 { - compatible = "samsung,exynos5433-cmu-bus0"; - reg = <0x13600000 0x1000>; - #clock-cells = <1>; - - clock-names = "aclk_bus0_400"; - clocks = <&cmu_top CLK_ACLK_BUS0_400>; - }; - - cmu_bus1: clock-controller@14800000 { - compatible = "samsung,exynos5433-cmu-bus1"; - reg = <0x14800000 0x1000>; - #clock-cells = <1>; - - clock-names = "aclk_bus1_400"; - clocks = <&cmu_top CLK_ACLK_BUS1_400>; - }; - - cmu_bus2: clock-controller@13400000 { - compatible = "samsung,exynos5433-cmu-bus2"; - reg = <0x13400000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", "aclk_bus2_400"; - clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>; - }; - - cmu_g3d: clock-controller@14aa0000 { - compatible = "samsung,exynos5433-cmu-g3d"; - reg = <0x14aa0000 0x2000>; - #clock-cells = <1>; - - clock-names = "oscclk", "aclk_g3d_400"; - clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; - power-domains = <&pd_g3d>; - }; - - cmu_gscl: clock-controller@13cf0000 { - compatible = "samsung,exynos5433-cmu-gscl"; - reg = <0x13cf0000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_gscl_111", - "aclk_gscl_333"; - clocks = <&xxti>, - <&cmu_top CLK_ACLK_GSCL_111>, - <&cmu_top CLK_ACLK_GSCL_333>; - power-domains = <&pd_gscl>; - }; - - cmu_apollo: clock-controller@11900000 { - compatible = "samsung,exynos5433-cmu-apollo"; - reg = <0x11900000 0x2000>; - #clock-cells = <1>; - - clock-names = "oscclk", "sclk_bus_pll_apollo"; - clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>; - }; - - cmu_atlas: clock-controller@11800000 { - compatible = "samsung,exynos5433-cmu-atlas"; - reg = <0x11800000 0x2000>; - #clock-cells = <1>; - - clock-names = "oscclk", "sclk_bus_pll_atlas"; - clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>; - }; - - cmu_mscl: clock-controller@150d0000 { - compatible = "samsung,exynos5433-cmu-mscl"; - reg = <0x150d0000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_jpeg_mscl", - "aclk_mscl_400"; - clocks = <&xxti>, - <&cmu_top CLK_SCLK_JPEG_MSCL>, - <&cmu_top CLK_ACLK_MSCL_400>; - power-domains = <&pd_mscl>; - }; - - cmu_mfc: clock-controller@15280000 { - compatible = "samsung,exynos5433-cmu-mfc"; - reg = <0x15280000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", "aclk_mfc_400"; - clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; - power-domains = <&pd_mfc>; - }; - - cmu_hevc: clock-controller@14f80000 { - compatible = "samsung,exynos5433-cmu-hevc"; - reg = <0x14f80000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", "aclk_hevc_400"; - clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; - power-domains = <&pd_hevc>; - }; - - cmu_isp: clock-controller@146d0000 { - compatible = "samsung,exynos5433-cmu-isp"; - reg = <0x146d0000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_isp_dis_400", - "aclk_isp_400"; - clocks = <&xxti>, - <&cmu_top CLK_ACLK_ISP_DIS_400>, - <&cmu_top CLK_ACLK_ISP_400>; - power-domains = <&pd_isp>; - }; - - cmu_cam0: clock-controller@120d0000 { - compatible = "samsung,exynos5433-cmu-cam0"; - reg = <0x120d0000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_cam0_333", - "aclk_cam0_400", - "aclk_cam0_552"; - clocks = <&xxti>, - <&cmu_top CLK_ACLK_CAM0_333>, - <&cmu_top CLK_ACLK_CAM0_400>, - <&cmu_top CLK_ACLK_CAM0_552>; - power-domains = <&pd_cam0>; - }; - - cmu_cam1: clock-controller@145d0000 { - compatible = "samsung,exynos5433-cmu-cam1"; - reg = <0x145d0000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "sclk_isp_uart_cam1", - "sclk_isp_spi1_cam1", - "sclk_isp_spi0_cam1", - "aclk_cam1_333", - "aclk_cam1_400", - "aclk_cam1_552"; - clocks = <&xxti>, - <&cmu_top CLK_SCLK_ISP_UART_CAM1>, - <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>, - <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>, - <&cmu_top CLK_ACLK_CAM1_333>, - <&cmu_top CLK_ACLK_CAM1_400>, - <&cmu_top CLK_ACLK_CAM1_552>; - power-domains = <&pd_cam1>; - }; - - cmu_imem: clock-controller@11060000 { - compatible = "samsung,exynos5433-cmu-imem"; - reg = <0x11060000 0x1000>; - #clock-cells = <1>; - - clock-names = "oscclk", - "aclk_imem_sssx_266", - "aclk_imem_266", - "aclk_imem_200"; - clocks = <&xxti>, - <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>, - <&cmu_top CLK_DIV_ACLK_IMEM_266>, - <&cmu_top CLK_DIV_ACLK_IMEM_200>; - }; - - slim_sss: slim-sss@11140000 { - compatible = "samsung,exynos5433-slim-sss"; - reg = <0x11140000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_imem CLK_ACLK_SLIMSSS>, - <&cmu_imem CLK_PCLK_SLIMSSS>; - }; - - pd_gscl: power-domain@105c4000 { - compatible = "samsung,exynos5433-pd"; - reg = <0x105c4000 0x20>; - #power-domain-cells = <0>; - label = "GSCL"; - }; - - pd_cam0: power-domain@105c4020 { - compatible = "samsung,exynos5433-pd"; - reg = <0x105c4020 0x20>; - #power-domain-cells = <0>; - power-domains = <&pd_cam1>; - label = "CAM0"; - }; - - pd_mscl: power-domain@105c4040 { - compatible = "samsung,exynos5433-pd"; - reg = <0x105c4040 0x20>; - #power-domain-cells = <0>; - label = "MSCL"; - }; - - pd_g3d: power-domain@105c4060 { - compatible = "samsung,exynos5433-pd"; - reg = <0x105c4060 0x20>; - #power-domain-cells = <0>; - label = "G3D"; - }; - - pd_disp: power-domain@105c4080 { - compatible = "samsung,exynos5433-pd"; - reg = <0x105c4080 0x20>; - #power-domain-cells = <0>; - label = "DISP"; - }; - - pd_cam1: power-domain@105c40a0 { - compatible = "samsung,exynos5433-pd"; - reg = <0x105c40a0 0x20>; - #power-domain-cells = <0>; - label = "CAM1"; - }; - - pd_aud: power-domain@105c40c0 { - compatible = "samsung,exynos5433-pd"; - reg = <0x105c40c0 0x20>; - #power-domain-cells = <0>; - label = "AUD"; - }; - - pd_g2d: power-domain@105c4120 { - compatible = "samsung,exynos5433-pd"; - reg = <0x105c4120 0x20>; - #power-domain-cells = <0>; - label = "G2D"; - }; - - pd_isp: power-domain@105c4140 { - compatible = "samsung,exynos5433-pd"; - reg = <0x105c4140 0x20>; - #power-domain-cells = <0>; - power-domains = <&pd_cam0>; - label = "ISP"; - }; - - pd_mfc: power-domain@105c4180 { - compatible = "samsung,exynos5433-pd"; - reg = <0x105c4180 0x20>; - #power-domain-cells = <0>; - label = "MFC"; - }; - - pd_hevc: power-domain@105c41c0 { - compatible = "samsung,exynos5433-pd"; - reg = <0x105c41c0 0x20>; - #power-domain-cells = <0>; - label = "HEVC"; - }; - - tmu_atlas0: tmu@10060000 { - compatible = "samsung,exynos5433-tmu"; - reg = <0x10060000 0x200>; - interrupts = ; - clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>, - <&cmu_peris CLK_SCLK_TMU0>; - clock-names = "tmu_apbif", "tmu_sclk"; - #thermal-sensor-cells = <0>; - status = "disabled"; - }; - - tmu_atlas1: tmu@10068000 { - compatible = "samsung,exynos5433-tmu"; - reg = <0x10068000 0x200>; - interrupts = ; - clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>, - <&cmu_peris CLK_SCLK_TMU0>; - clock-names = "tmu_apbif", "tmu_sclk"; - #thermal-sensor-cells = <0>; - status = "disabled"; - }; - - tmu_g3d: tmu@10070000 { - compatible = "samsung,exynos5433-tmu"; - reg = <0x10070000 0x200>; - interrupts = ; - clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, - <&cmu_peris CLK_SCLK_TMU1>; - clock-names = "tmu_apbif", "tmu_sclk"; - #thermal-sensor-cells = <0>; - status = "disabled"; - }; - - tmu_apollo: tmu@10078000 { - compatible = "samsung,exynos5433-tmu"; - reg = <0x10078000 0x200>; - interrupts = ; - clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, - <&cmu_peris CLK_SCLK_TMU1>; - clock-names = "tmu_apbif", "tmu_sclk"; - #thermal-sensor-cells = <0>; - status = "disabled"; - }; - - tmu_isp: tmu@1007c000 { - compatible = "samsung,exynos5433-tmu"; - reg = <0x1007c000 0x200>; - interrupts = ; - clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, - <&cmu_peris CLK_SCLK_TMU1>; - clock-names = "tmu_apbif", "tmu_sclk"; - #thermal-sensor-cells = <0>; - status = "disabled"; - }; - - timer@101c0000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x101c0000 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>; - clock-names = "fin_pll", "mct"; - }; - - ppmu_d0_cpu: ppmu@10480000 { - compatible = "samsung,exynos-ppmu-v2"; - reg = <0x10480000 0x2000>; - status = "disabled"; - }; - - ppmu_d0_general: ppmu@10490000 { - compatible = "samsung,exynos-ppmu-v2"; - reg = <0x10490000 0x2000>; - status = "disabled"; - }; - - ppmu_d1_cpu: ppmu@104b0000 { - compatible = "samsung,exynos-ppmu-v2"; - reg = <0x104b0000 0x2000>; - status = "disabled"; - }; - - ppmu_d1_general: ppmu@104c0000 { - compatible = "samsung,exynos-ppmu-v2"; - reg = <0x104c0000 0x2000>; - status = "disabled"; - }; - - pinctrl_alive: pinctrl@10580000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x10580000 0x1a20>, <0x11090000 0x100>; - - wakeup-interrupt-controller { - compatible = "samsung,exynos7-wakeup-eint"; - interrupts = ; - }; - }; - - pinctrl_aud: pinctrl@114b0000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x114b0000 0x1000>; - interrupts = ; - power-domains = <&pd_aud>; - }; - - pinctrl_cpif: pinctrl@10fe0000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x10fe0000 0x1000>; - interrupts = ; - }; - - pinctrl_ese: pinctrl@14ca0000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x14ca0000 0x1000>; - interrupts = ; - }; - - pinctrl_finger: pinctrl@14cb0000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x14cb0000 0x1000>; - interrupts = ; - }; - - pinctrl_fsys: pinctrl@15690000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x15690000 0x1000>; - interrupts = ; - }; - - pinctrl_imem: pinctrl@11090000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x11090000 0x1000>; - interrupts = ; - }; - - pinctrl_nfc: pinctrl@14cd0000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x14cd0000 0x1000>; - interrupts = ; - }; - - pinctrl_peric: pinctrl@14cc0000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x14cc0000 0x1100>; - interrupts = ; - }; - - pinctrl_touch: pinctrl@14ce0000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x14ce0000 0x1100>; - interrupts = ; - }; - - pmu_system_controller: system-controller@105c0000 { - compatible = "samsung,exynos5433-pmu", "syscon"; - reg = <0x105c0000 0x5008>; - #clock-cells = <1>; - clock-names = "clkout16"; - clocks = <&xxti>; - - reboot: syscon-reboot { - compatible = "syscon-reboot"; - regmap = <&pmu_system_controller>; - offset = <0x400>; /* SWRESET */ - mask = <0x1>; - }; - }; - - gic: interrupt-controller@11001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x11001000 0x1000>, - <0x11002000 0x2000>, - <0x11004000 0x2000>, - <0x11006000 0x2000>; - interrupts = ; - }; - - mipi_phy: video-phy { - compatible = "samsung,exynos5433-mipi-video-phy"; - #phy-cells = <1>; - samsung,pmu-syscon = <&pmu_system_controller>; - samsung,cam0-sysreg = <&syscon_cam0>; - samsung,cam1-sysreg = <&syscon_cam1>; - samsung,disp-sysreg = <&syscon_disp>; - }; - - decon: decon@13800000 { - compatible = "samsung,exynos5433-decon"; - reg = <0x13800000 0x2104>; - clocks = <&cmu_disp CLK_PCLK_DECON>, - <&cmu_disp CLK_ACLK_DECON>, - <&cmu_disp CLK_ACLK_SMMU_DECON0X>, - <&cmu_disp CLK_ACLK_XIU_DECON0X>, - <&cmu_disp CLK_PCLK_SMMU_DECON0X>, - <&cmu_disp CLK_ACLK_SMMU_DECON1X>, - <&cmu_disp CLK_ACLK_XIU_DECON1X>, - <&cmu_disp CLK_PCLK_SMMU_DECON1X>, - <&cmu_disp CLK_SCLK_DECON_VCLK>, - <&cmu_disp CLK_SCLK_DECON_ECLK>, - <&cmu_disp CLK_SCLK_DSD>; - clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", - "aclk_xiu_decon0x", "pclk_smmu_decon0x", - "aclk_smmu_decon1x", "aclk_xiu_decon1x", - "pclk_smmu_decon1x", "sclk_decon_vclk", - "sclk_decon_eclk", "dsd"; - power-domains = <&pd_disp>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = , - , - ; - samsung,disp-sysreg = <&syscon_disp>; - status = "disabled"; - iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>; - iommu-names = "m0", "m1"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - decon_to_mic: endpoint { - remote-endpoint = - <&mic_to_decon>; - }; - }; - }; - }; - - decon_tv: decon@13880000 { - compatible = "samsung,exynos5433-decon-tv"; - reg = <0x13880000 0x20b8>; - clocks = <&cmu_disp CLK_PCLK_DECON_TV>, - <&cmu_disp CLK_ACLK_DECON_TV>, - <&cmu_disp CLK_ACLK_SMMU_TV0X>, - <&cmu_disp CLK_ACLK_XIU_TV0X>, - <&cmu_disp CLK_PCLK_SMMU_TV0X>, - <&cmu_disp CLK_ACLK_SMMU_TV1X>, - <&cmu_disp CLK_ACLK_XIU_TV1X>, - <&cmu_disp CLK_PCLK_SMMU_TV1X>, - <&cmu_disp CLK_SCLK_DECON_TV_VCLK>, - <&cmu_disp CLK_SCLK_DECON_TV_ECLK>, - <&cmu_disp CLK_SCLK_DSD>; - clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", - "aclk_xiu_decon0x", "pclk_smmu_decon0x", - "aclk_smmu_decon1x", "aclk_xiu_decon1x", - "pclk_smmu_decon1x", "sclk_decon_vclk", - "sclk_decon_eclk", "dsd"; - samsung,disp-sysreg = <&syscon_disp>; - power-domains = <&pd_disp>; - interrupt-names = "fifo", "vsync", "lcd_sys"; - interrupts = , - , - ; - status = "disabled"; - iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>; - iommu-names = "m0", "m1"; - }; - - dsi: dsi@13900000 { - compatible = "samsung,exynos5433-mipi-dsi"; - reg = <0x13900000 0xC0>; - interrupts = ; - phys = <&mipi_phy 1>; - phy-names = "dsim"; - clocks = <&cmu_disp CLK_PCLK_DSIM0>, - <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>, - <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>, - <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>, - <&cmu_disp CLK_SCLK_DSIM0>; - clock-names = "bus_clk", - "phyclk_mipidphy0_bitclkdiv8", - "phyclk_mipidphy0_rxclkesc0", - "sclk_rgb_vclk_to_dsim0", - "sclk_mipi"; - power-domains = <&pd_disp>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi_to_mic: endpoint { - remote-endpoint = <&mic_to_dsi>; - }; - }; - }; - }; - - mic: mic@13930000 { - compatible = "samsung,exynos5433-mic"; - reg = <0x13930000 0x48>; - clocks = <&cmu_disp CLK_PCLK_MIC0>, - <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>; - clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0"; - power-domains = <&pd_disp>; - samsung,disp-syscon = <&syscon_disp>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mic_to_decon: endpoint { - remote-endpoint = - <&decon_to_mic>; - }; - }; - - port@1 { - reg = <1>; - mic_to_dsi: endpoint { - remote-endpoint = <&dsi_to_mic>; - }; - }; - }; - }; - - hdmi: hdmi@13970000 { - compatible = "samsung,exynos5433-hdmi"; - reg = <0x13970000 0x70000>; - interrupts = ; - clocks = <&cmu_disp CLK_PCLK_HDMI>, - <&cmu_disp CLK_PCLK_HDMIPHY>, - <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>, - <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>, - <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>, - <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>, - <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>, - <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>, - <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>; - clock-names = "hdmi_pclk", "hdmi_i_pclk", - "i_tmds_clk", "i_pixel_clk", - "tmds_clko", "tmds_clko_user", - "pixel_clko", "pixel_clko_user", - "oscclk", "i_spdif_clk"; - phy = <&hdmiphy>; - ddc = <&hsi2c_11>; - samsung,syscon-phandle = <&pmu_system_controller>; - samsung,sysreg-phandle = <&syscon_disp>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - hdmiphy: hdmiphy@13af0000 { - reg = <0x13af0000 0x80>; - }; - - syscon_disp: syscon@13b80000 { - compatible = "samsung,exynos5433-sysreg", "syscon"; - reg = <0x13b80000 0x1010>; - }; - - syscon_cam0: syscon@120f0000 { - compatible = "samsung,exynos5433-sysreg", "syscon"; - reg = <0x120f0000 0x1020>; - }; - - syscon_cam1: syscon@145f0000 { - compatible = "samsung,exynos5433-sysreg", "syscon"; - reg = <0x145f0000 0x1038>; - }; - - gsc_0: video-scaler@13c00000 { - compatible = "samsung,exynos5433-gsc"; - reg = <0x13c00000 0x1000>; - interrupts = ; - clock-names = "pclk", "aclk", "aclk_xiu", - "aclk_gsclbend", "gsd"; - clocks = <&cmu_gscl CLK_PCLK_GSCL0>, - <&cmu_gscl CLK_ACLK_GSCL0>, - <&cmu_gscl CLK_ACLK_XIU_GSCLX>, - <&cmu_gscl CLK_ACLK_GSCLBEND_333>, - <&cmu_gscl CLK_ACLK_GSD>; - iommus = <&sysmmu_gscl0>; - power-domains = <&pd_gscl>; - }; - - gsc_1: video-scaler@13c10000 { - compatible = "samsung,exynos5433-gsc"; - reg = <0x13c10000 0x1000>; - interrupts = ; - clock-names = "pclk", "aclk", "aclk_xiu", - "aclk_gsclbend", "gsd"; - clocks = <&cmu_gscl CLK_PCLK_GSCL1>, - <&cmu_gscl CLK_ACLK_GSCL1>, - <&cmu_gscl CLK_ACLK_XIU_GSCLX>, - <&cmu_gscl CLK_ACLK_GSCLBEND_333>, - <&cmu_gscl CLK_ACLK_GSD>; - iommus = <&sysmmu_gscl1>; - power-domains = <&pd_gscl>; - }; - - gsc_2: video-scaler@13c20000 { - compatible = "samsung,exynos5433-gsc"; - reg = <0x13c20000 0x1000>; - interrupts = ; - clock-names = "pclk", "aclk", "aclk_xiu", - "aclk_gsclbend", "gsd"; - clocks = <&cmu_gscl CLK_PCLK_GSCL2>, - <&cmu_gscl CLK_ACLK_GSCL2>, - <&cmu_gscl CLK_ACLK_XIU_GSCLX>, - <&cmu_gscl CLK_ACLK_GSCLBEND_333>, - <&cmu_gscl CLK_ACLK_GSD>; - iommus = <&sysmmu_gscl2>; - power-domains = <&pd_gscl>; - }; - - gpu: gpu@14ac0000 { - compatible = "samsung,exynos5433-mali", "arm,mali-t760"; - reg = <0x14ac0000 0x5000>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&cmu_g3d CLK_ACLK_G3D>; - clock-names = "core"; - power-domains = <&pd_g3d>; - operating-points-v2 = <&gpu_opp_table>; - status = "disabled"; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <1000000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <1000000>; - }; - opp-350000000 { - opp-hz = /bits/ 64 <350000000>; - opp-microvolt = <1025000>; - }; - opp-420000000 { - opp-hz = /bits/ 64 <420000000>; - opp-microvolt = <1025000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <1075000>; - }; - opp-550000000 { - opp-hz = /bits/ 64 <550000000>; - opp-microvolt = <1125000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1150000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <1150000>; - }; - }; - }; - - scaler_0: scaler@15000000 { - compatible = "samsung,exynos5433-scaler"; - reg = <0x15000000 0x1294>; - interrupts = <0 402 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "pclk", "aclk", "aclk_xiu"; - clocks = <&cmu_mscl CLK_PCLK_M2MSCALER0>, - <&cmu_mscl CLK_ACLK_M2MSCALER0>, - <&cmu_mscl CLK_ACLK_XIU_MSCLX>; - iommus = <&sysmmu_scaler_0>; - power-domains = <&pd_mscl>; - }; - - scaler_1: scaler@15010000 { - compatible = "samsung,exynos5433-scaler"; - reg = <0x15010000 0x1294>; - interrupts = <0 403 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "pclk", "aclk", "aclk_xiu"; - clocks = <&cmu_mscl CLK_PCLK_M2MSCALER1>, - <&cmu_mscl CLK_ACLK_M2MSCALER1>, - <&cmu_mscl CLK_ACLK_XIU_MSCLX>; - iommus = <&sysmmu_scaler_1>; - power-domains = <&pd_mscl>; - }; - - jpeg: codec@15020000 { - compatible = "samsung,exynos5433-jpeg"; - reg = <0x15020000 0x10000>; - interrupts = ; - clock-names = "pclk", "aclk", "aclk_xiu", "sclk"; - clocks = <&cmu_mscl CLK_PCLK_JPEG>, - <&cmu_mscl CLK_ACLK_JPEG>, - <&cmu_mscl CLK_ACLK_XIU_MSCLX>, - <&cmu_mscl CLK_SCLK_JPEG>; - iommus = <&sysmmu_jpeg>; - power-domains = <&pd_mscl>; - }; - - mfc: codec@152e0000 { - compatible = "samsung,exynos5433-mfc"; - reg = <0x152E0000 0x10000>; - interrupts = ; - clock-names = "pclk", "aclk", "aclk_xiu"; - clocks = <&cmu_mfc CLK_PCLK_MFC>, - <&cmu_mfc CLK_ACLK_MFC>, - <&cmu_mfc CLK_ACLK_XIU_MFCX>; - iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>; - iommu-names = "left", "right"; - power-domains = <&pd_mfc>; - }; - - sysmmu_decon0x: sysmmu@13a00000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13a00000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_disp CLK_ACLK_SMMU_DECON0X>, - <&cmu_disp CLK_PCLK_SMMU_DECON0X>; - power-domains = <&pd_disp>; - #iommu-cells = <0>; - }; - - sysmmu_decon1x: sysmmu@13a10000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13a10000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_disp CLK_ACLK_SMMU_DECON1X>, - <&cmu_disp CLK_PCLK_SMMU_DECON1X>; - #iommu-cells = <0>; - power-domains = <&pd_disp>; - }; - - sysmmu_tv0x: sysmmu@13a20000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13a20000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_disp CLK_ACLK_SMMU_TV0X>, - <&cmu_disp CLK_PCLK_SMMU_TV0X>; - #iommu-cells = <0>; - power-domains = <&pd_disp>; - }; - - sysmmu_tv1x: sysmmu@13a30000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13a30000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_disp CLK_ACLK_SMMU_TV1X>, - <&cmu_disp CLK_PCLK_SMMU_TV1X>; - #iommu-cells = <0>; - power-domains = <&pd_disp>; - }; - - sysmmu_gscl0: sysmmu@13c80000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13C80000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>, - <&cmu_gscl CLK_PCLK_SMMU_GSCL0>; - #iommu-cells = <0>; - power-domains = <&pd_gscl>; - }; - - sysmmu_gscl1: sysmmu@13c90000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13C90000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>, - <&cmu_gscl CLK_PCLK_SMMU_GSCL1>; - #iommu-cells = <0>; - power-domains = <&pd_gscl>; - }; - - sysmmu_gscl2: sysmmu@13ca0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x13CA0000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>, - <&cmu_gscl CLK_PCLK_SMMU_GSCL2>; - #iommu-cells = <0>; - power-domains = <&pd_gscl>; - }; - - sysmmu_scaler_0: sysmmu@15040000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x15040000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER0>, - <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>; - #iommu-cells = <0>; - power-domains = <&pd_mscl>; - }; - - sysmmu_scaler_1: sysmmu@15050000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x15050000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER1>, - <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>; - #iommu-cells = <0>; - power-domains = <&pd_mscl>; - }; - - sysmmu_jpeg: sysmmu@15060000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x15060000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_mscl CLK_ACLK_SMMU_JPEG>, - <&cmu_mscl CLK_PCLK_SMMU_JPEG>; - #iommu-cells = <0>; - power-domains = <&pd_mscl>; - }; - - sysmmu_mfc_0: sysmmu@15200000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x15200000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_0>, - <&cmu_mfc CLK_PCLK_SMMU_MFC_0>; - #iommu-cells = <0>; - power-domains = <&pd_mfc>; - }; - - sysmmu_mfc_1: sysmmu@15210000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x15210000 0x1000>; - interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_1>, - <&cmu_mfc CLK_PCLK_SMMU_MFC_1>; - #iommu-cells = <0>; - power-domains = <&pd_mfc>; - }; - - serial_0: serial@14c10000 { - compatible = "samsung,exynos5433-uart"; - reg = <0x14c10000 0x100>; - interrupts = ; - clocks = <&cmu_peric CLK_PCLK_UART0>, - <&cmu_peric CLK_SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_bus>; - status = "disabled"; - }; - - serial_1: serial@14c20000 { - compatible = "samsung,exynos5433-uart"; - reg = <0x14c20000 0x100>; - interrupts = ; - clocks = <&cmu_peric CLK_PCLK_UART1>, - <&cmu_peric CLK_SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_bus>; - status = "disabled"; - }; - - serial_2: serial@14c30000 { - compatible = "samsung,exynos5433-uart"; - reg = <0x14c30000 0x100>; - interrupts = ; - clocks = <&cmu_peric CLK_PCLK_UART2>, - <&cmu_peric CLK_SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_bus>; - status = "disabled"; - }; - - spi_0: spi@14d20000 { - compatible = "samsung,exynos5433-spi"; - reg = <0x14d20000 0x100>; - interrupts = ; - dmas = <&pdma0 9>, <&pdma0 8>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu_peric CLK_PCLK_SPI0>, - <&cmu_peric CLK_SCLK_SPI0>, - <&cmu_peric CLK_SCLK_IOCLK_SPI0>; - clock-names = "spi", "spi_busclk0", "spi_ioclk"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_bus>; - num-cs = <1>; - status = "disabled"; - }; - - spi_1: spi@14d30000 { - compatible = "samsung,exynos5433-spi"; - reg = <0x14d30000 0x100>; - interrupts = ; - dmas = <&pdma0 11>, <&pdma0 10>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu_peric CLK_PCLK_SPI1>, - <&cmu_peric CLK_SCLK_SPI1>, - <&cmu_peric CLK_SCLK_IOCLK_SPI1>; - clock-names = "spi", "spi_busclk0", "spi_ioclk"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_bus>; - num-cs = <1>; - status = "disabled"; - }; - - spi_2: spi@14d40000 { - compatible = "samsung,exynos5433-spi"; - reg = <0x14d40000 0x100>; - interrupts = ; - dmas = <&pdma0 13>, <&pdma0 12>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu_peric CLK_PCLK_SPI2>, - <&cmu_peric CLK_SCLK_SPI2>, - <&cmu_peric CLK_SCLK_IOCLK_SPI2>; - clock-names = "spi", "spi_busclk0", "spi_ioclk"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_bus>; - num-cs = <1>; - status = "disabled"; - }; - - spi_3: spi@14d50000 { - compatible = "samsung,exynos5433-spi"; - reg = <0x14d50000 0x100>; - interrupts = ; - dmas = <&pdma0 23>, <&pdma0 22>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu_peric CLK_PCLK_SPI3>, - <&cmu_peric CLK_SCLK_SPI3>, - <&cmu_peric CLK_SCLK_IOCLK_SPI3>; - clock-names = "spi", "spi_busclk0", "spi_ioclk"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi3_bus>; - num-cs = <1>; - status = "disabled"; - }; - - spi_4: spi@14d00000 { - compatible = "samsung,exynos5433-spi"; - reg = <0x14d00000 0x100>; - interrupts = ; - dmas = <&pdma0 25>, <&pdma0 24>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu_peric CLK_PCLK_SPI4>, - <&cmu_peric CLK_SCLK_SPI4>, - <&cmu_peric CLK_SCLK_IOCLK_SPI4>; - clock-names = "spi", "spi_busclk0", "spi_ioclk"; - samsung,spi-src-clk = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi4_bus>; - num-cs = <1>; - status = "disabled"; - }; - - adc: adc@14d10000 { - compatible = "samsung,exynos7-adc"; - reg = <0x14d10000 0x100>; - interrupts = ; - clock-names = "adc"; - clocks = <&cmu_peric CLK_PCLK_ADCIF>; - #io-channel-cells = <1>; - io-channel-ranges; - status = "disabled"; - }; - - i2s1: i2s@14d60000 { - compatible = "samsung,exynos7-i2s"; - reg = <0x14d60000 0x100>; - dmas = <&pdma0 31>, <&pdma0 30>; - dma-names = "tx", "rx"; - interrupts = ; - clocks = <&cmu_peric CLK_PCLK_I2S1>, - <&cmu_peric CLK_PCLK_I2S1>, - <&cmu_peric CLK_SCLK_I2S1>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - #clock-cells = <1>; - #sound-dai-cells = <1>; - status = "disabled"; - }; - - pwm: pwm@14dd0000 { - compatible = "samsung,exynos4210-pwm"; - reg = <0x14dd0000 0x100>; - interrupts = , - , - , - , - ; - samsung,pwm-outputs = <0>, <1>, <2>, <3>; - clocks = <&cmu_peric CLK_PCLK_PWM>; - clock-names = "timers"; - #pwm-cells = <3>; - status = "disabled"; - }; - - hsi2c_0: hsi2c@14e40000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14e40000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c0_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C0>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_1: hsi2c@14e50000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14e50000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c1_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C1>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_2: hsi2c@14e60000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14e60000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c2_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C2>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_3: hsi2c@14e70000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14e70000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c3_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C3>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_4: hsi2c@14ec0000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14ec0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c4_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C4>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_5: hsi2c@14ed0000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14ed0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c5_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C5>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_6: hsi2c@14ee0000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14ee0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c6_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C6>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_7: hsi2c@14ef0000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14ef0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c7_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C7>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_8: hsi2c@14d90000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14d90000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c8_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C8>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_9: hsi2c@14da0000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14da0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c9_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C9>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_10: hsi2c@14de0000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14de0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c10_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C10>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_11: hsi2c@14df0000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14df0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c11_bus>; - clocks = <&cmu_peric CLK_PCLK_HSI2C11>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - usbdrd30: usbdrd { - compatible = "samsung,exynos5433-dwusb3"; - clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, - <&cmu_fsys CLK_SCLK_USBDRD30>, - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>, - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>; - clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - usbdrd_dwc3: dwc3@15400000 { - compatible = "snps,dwc3"; - clocks = <&cmu_fsys CLK_SCLK_USBDRD30>, - <&cmu_fsys CLK_ACLK_USBDRD30>, - <&cmu_fsys CLK_SCLK_USBDRD30>; - clock-names = "ref", "bus_early", "suspend"; - reg = <0x15400000 0x10000>; - interrupts = ; - phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - usbdrd30_phy: phy@15500000 { - compatible = "samsung,exynos5433-usbdrd-phy"; - reg = <0x15500000 0x100>; - clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>, - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>, - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>, - <&cmu_fsys CLK_SCLK_USBDRD30>; - clock-names = "phy", "ref", "phy_utmi", "phy_pipe", - "itp"; - #phy-cells = <1>; - samsung,pmu-syscon = <&pmu_system_controller>; - status = "disabled"; - }; - - usbhost30_phy: phy@15580000 { - compatible = "samsung,exynos5433-usbdrd-phy"; - reg = <0x15580000 0x100>; - clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>, - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>, - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>, - <&cmu_fsys CLK_SCLK_USBHOST30>; - clock-names = "phy", "ref", "phy_utmi", "phy_pipe", - "itp"; - #phy-cells = <1>; - samsung,pmu-syscon = <&pmu_system_controller>; - status = "disabled"; - }; - - usbhost30: usbhost { - compatible = "samsung,exynos5433-dwusb3"; - clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, - <&cmu_fsys CLK_SCLK_USBHOST30>, - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>, - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>; - clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - usbhost_dwc3: dwc3@15a00000 { - compatible = "snps,dwc3"; - clocks = <&cmu_fsys CLK_SCLK_USBHOST30>, - <&cmu_fsys CLK_ACLK_USBHOST30>, - <&cmu_fsys CLK_SCLK_USBHOST30>; - clock-names = "ref", "bus_early", "suspend"; - reg = <0x15a00000 0x10000>; - interrupts = ; - phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - mshc_0: mshc@15540000 { - compatible = "samsung,exynos7-dw-mshc-smu"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x15540000 0x2000>; - clocks = <&cmu_fsys CLK_ACLK_MMC0>, - <&cmu_fsys CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - mshc_1: mshc@15550000 { - compatible = "samsung,exynos7-dw-mshc-smu"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x15550000 0x2000>; - clocks = <&cmu_fsys CLK_ACLK_MMC1>, - <&cmu_fsys CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - mshc_2: mshc@15560000 { - compatible = "samsung,exynos7-dw-mshc-smu"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x15560000 0x2000>; - clocks = <&cmu_fsys CLK_ACLK_MMC2>, - <&cmu_fsys CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - pdma0: pdma@15610000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x15610000 0x1000>; - interrupts = ; - clocks = <&cmu_fsys CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@15600000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x15600000 0x1000>; - interrupts = ; - clocks = <&cmu_fsys CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - audio-subsystem@11400000 { - compatible = "samsung,exynos5433-lpass"; - reg = <0x11400000 0x100>, <0x11500000 0x08>; - clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>; - clock-names = "sfr0_ctrl"; - samsung,pmu-syscon = <&pmu_system_controller>; - power-domains = <&pd_aud>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - adma: adma@11420000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x11420000 0x1000>; - interrupts = ; - clocks = <&cmu_aud CLK_ACLK_DMAC>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - power-domains = <&pd_aud>; - }; - - i2s0: i2s@11440000 { - compatible = "samsung,exynos7-i2s"; - reg = <0x11440000 0x100>; - dmas = <&adma 0>, <&adma 2>; - dma-names = "tx", "rx"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cmu_aud CLK_PCLK_AUD_I2S>, - <&cmu_aud CLK_SCLK_AUD_I2S>, - <&cmu_aud CLK_SCLK_I2S_BCLK>; - clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - #clock-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - power-domains = <&pd_aud>; - #sound-dai-cells = <1>; - status = "disabled"; - }; - - serial_3: serial@11460000 { - compatible = "samsung,exynos5433-uart"; - reg = <0x11460000 0x100>; - interrupts = ; - clocks = <&cmu_aud CLK_PCLK_AUD_UART>, - <&cmu_aud CLK_SCLK_AUD_UART>; - clock-names = "uart", "clk_uart_baud0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart_aud_bus>; - power-domains = <&pd_aud>; - status = "disabled"; - }; - }; - }; - - timer: timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; - -#include "exynos5433-bus.dtsi" -#include "exynos5433-pinctrl.dtsi" -#include "exynos5433-tmu.dtsi" diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts deleted file mode 100644 index 358b7b6ea..000000000 --- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts +++ /dev/null @@ -1,418 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos7 Espresso board device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos7.dtsi" -#include -#include -#include - -/ { - model = "Samsung Exynos7 Espresso board based on Exynos7"; - compatible = "samsung,exynos7-espresso", "samsung,exynos7"; - - aliases { - serial0 = &serial_2; - mshc0 = &mmc_0; - mshc2 = &mmc_2; - }; - - chosen { - stdout-path = &serial_2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0x0 0xC0000000>; - }; - - usb30_vbus_reg: regulator-usb30 { - compatible = "regulator-fixed"; - regulator-name = "VBUS_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gph1 1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb30_vbus_en>; - enable-active-high; - }; - - usb3drd_boost_5v: regulator-usb3drd-boost { - compatible = "regulator-fixed"; - regulator-name = "VUSB_VBUS_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpf4 1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb3drd_boost_en>; - enable-active-high; - }; - -}; - -&fin_pll { - clock-frequency = <24000000>; -}; - -&gpu { - mali-supply = <&buck6_reg>; - status = "okay"; -}; - -&serial_2 { - status = "okay"; -}; - -&rtc { - status = "okay"; - clocks = <&clock_ccore PCLK_RTC>, <&s2mps15_osc S2MPS11_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&watchdog { - status = "okay"; -}; - -&adc { - status = "okay"; -}; - -&hsi2c_4 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <200000>; - status = "okay"; - - s2mps15_pmic@66 { - compatible = "samsung,s2mps15-pmic"; - reg = <0x66>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpa0>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_irq>; - wakeup-source; - - s2mps15_osc: clocks { - compatible = "samsung,s2mps13-clk"; - #clock-cells = <1>; - clock-output-names = "s2mps13_ap", "s2mps13_cp", - "s2mps13_bt"; - }; - - regulators { - ldo1_reg: LDO1 { - regulator-name = "vdd_ldo1"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - regulator-enable-ramp-delay = <125>; - }; - - ldo2_reg: LDO2 { - regulator-name = "vqmmc-sdcard"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-enable-ramp-delay = <125>; - }; - - ldo3_reg: LDO3 { - regulator-name = "vdd_ldo3"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <1980000>; - regulator-always-on; - regulator-boot-on; - regulator-enable-ramp-delay = <125>; - }; - - ldo4_reg: LDO4 { - regulator-name = "vdd_ldo4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1110000>; - regulator-always-on; - regulator-enable-ramp-delay = <125>; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd_ldo5"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <1980000>; - regulator-always-on; - regulator-enable-ramp-delay = <125>; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_ldo6"; - regulator-min-microvolt = <2250000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo7_reg: LDO7 { - regulator-name = "vdd_ldo7"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1150000>; - regulator-enable-ramp-delay = <125>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd_ldo8"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1000000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo9_reg: LDO9 { - regulator-name = "vdd_ldo9"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1000000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd_ldo10"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1000000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo11_reg: LDO11 { - regulator-name = "vdd_ldo11"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-enable-ramp-delay = <125>; - }; - - ldo12_reg: LDO12 { - regulator-name = "vdd_ldo12"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-enable-ramp-delay = <125>; - regulator-always-on; - }; - - ldo13_reg: LDO13 { - regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-enable-ramp-delay = <125>; - }; - - ldo14_reg: LDO14 { - regulator-name = "vdd_ldo14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3375000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo17_reg: LDO17 { - regulator-name = "vmmc-sdcard"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3375000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo18_reg: LDO18 { - regulator-name = "vdd_ldo18"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2275000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo19_reg: LDO19 { - regulator-name = "vdd_ldo19"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3375000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo21_reg: LDO21 { - regulator-name = "vdd_ldo21"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3375000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo23_reg: LDO23 { - regulator-name = "vdd_ldo23"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2275000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo25_reg: LDO25 { - regulator-name = "vdd_ldo25"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3375000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo26_reg: LDO26 { - regulator-name = "vdd_ldo26"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1470000>; - regulator-enable-ramp-delay = <125>; - }; - - ldo27_reg: LDO27 { - regulator-name = "vdd_ldo27"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2275000>; - regulator-enable-ramp-delay = <125>; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <25000>; - regulator-enable-ramp-delay = <250>; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_atlas"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <250>; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <250>; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_buck5"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1300000>; - regulator-ramp-delay = <25000>; - regulator-enable-ramp-delay = <250>; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1400000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <250>; - }; - - buck7_reg: BUCK7 { - regulator-name = "vdd_buck7"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-ramp-delay = <25000>; - regulator-enable-ramp-delay = <250>; - }; - - buck8_reg: BUCK8 { - regulator-name = "vdd_buck8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-ramp-delay = <25000>; - regulator-enable-ramp-delay = <250>; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_buck9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - regulator-always-on; - regulator-ramp-delay = <25000>; - regulator-enable-ramp-delay = <250>; - }; - - buck10_reg: BUCK10 { - regulator-name = "vdd_buck10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-ramp-delay = <25000>; - regulator-enable-ramp-delay = <250>; - }; - }; - }; -}; - -&pinctrl_alive { - pmic_irq: pmic-irq { - samsung,pins = "gpa0-2"; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&mmc_0 { - status = "okay"; - cap-mmc-highspeed; - mmc-hs200-1_8v; - non-removable; - card-detect-delay = <200>; - clock-frequency = <800000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4 &sd0_bus8>; - bus-width = <8>; -}; - -&mmc_2 { - status = "okay"; - cap-sd-highspeed; - card-detect-delay = <200>; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - bus-width = <4>; - vmmc-supply = <&ldo17_reg>; - vqmmc-supply = <&ldo2_reg>; - disable-wp; -}; - -&pinctrl_bus1 { - usb30_vbus_en: usb30-vbus-en { - samsung,pins = "gph1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - usb3drd_boost_en: usb3drd-boost-en { - samsung,pins = "gpf4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&ufs { - status = "okay"; -}; - -&usbdrd_phy { - vbus-supply = <&usb30_vbus_reg>; - vbus-boost-supply = <&usb3drd_boost_5v>; -}; diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi deleted file mode 100644 index 472dd649a..000000000 --- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi +++ /dev/null @@ -1,702 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's Exynos7 SoC pin-mux and pin-config device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as - * device tree nodes in this file. - */ - -#include - -&pinctrl_alive { - gpa0: gpa0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - interrupts = , - , - , - , - , - , - , - ; - }; - - gpa1: gpa1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - interrupts = , - , - , - , - , - , - , - ; - }; - - gpa2: gpa2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpa3: gpa3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&pinctrl_bus0 { - gpb0: gpb0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc0: gpc0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc1: gpc1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc2: gpc2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc3: gpc3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd0: gpd0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd1: gpd1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd2: gpd2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd4: gpd4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd5: gpd5 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd6: gpd6 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd7: gpd7 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd8: gpd8 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg0: gpg0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg3: gpg3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - hs_i2c10_bus: hs-i2c10-bus { - samsung,pins = "gpb0-1", "gpb0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c11_bus: hs-i2c11-bus { - samsung,pins = "gpb0-3", "gpb0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c2_bus: hs-i2c2-bus { - samsung,pins = "gpd0-3", "gpd0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_data: uart0-data { - samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpd1-4", "gpd1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c3_bus: hs-i2c3-bus { - samsung,pins = "gpd1-3", "gpd1-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c0_bus: hs-i2c0-bus { - samsung,pins = "gpd2-1", "gpd2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c1_bus: hs-i2c1-bus { - samsung,pins = "gpd2-3", "gpd2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c9_bus: hs-i2c9-bus { - samsung,pins = "gpd2-7", "gpd2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpd2-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpd2-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm2_out: pwm2-out { - samsung,pins = "gpd2-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pwm3_out: pwm3-out { - samsung,pins = "gpd2-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c8_bus: hs-i2c8-bus { - samsung,pins = "gpd5-3", "gpd5-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gpd5-0", "gpd5-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi2_bus: spi2-bus { - samsung,pins = "gpd5-0", "gpd5-1", "gpd5-2", "gpd5-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpd6-2", "gpd6-3", "gpd6-4", "gpd6-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpd8-0", "gpd8-1", "gpd6-0", "gpd6-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c4_bus: hs-i2c4-bus { - samsung,pins = "gpg3-1", "gpg3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - hs_i2c5_bus: hs-i2c5-bus { - samsung,pins = "gpg3-3", "gpg3-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_nfc { - gpj0: gpj0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - hs_i2c6_bus: hs-i2c6-bus { - samsung,pins = "gpj0-1", "gpj0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_touch { - gpj1: gpj1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - hs_i2c7_bus: hs-i2c7-bus { - samsung,pins = "gpj1-1", "gpj1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_ff { - gpg4: gpg4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - spi3_bus: spi3-bus { - samsung,pins = "gpg4-0", "gpg4-1", "gpg4-2", "gpg4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_ese { - gpv7: gpv7 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - spi4_bus: spi4-bus { - samsung,pins = "gpv7-0", "gpv7-1", "gpv7-2", "gpv7-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_fsys0 { - gpr4: gpr4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpr4-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpr4-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_cd: sd2-cd { - samsung,pins = "gpr4-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus1: sd2-bus-width1 { - samsung,pins = "gpr4-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd2_bus4: sd2-bus-width4 { - samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_fsys1 { - gpr0: gpr0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpr1: gpr1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpr2: gpr2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpr3: gpr3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpr0-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpr0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_ds: sd0-ds { - samsung,pins = "gpr0-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_qrdy: sd0-qrdy { - samsung,pins = "gpr0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus1: sd0-bus-width1 { - samsung,pins = "gpr1-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus4: sd0-bus-width4 { - samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd0_bus8: sd0-bus-width8 { - samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gpr2-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gpr2-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_ds: sd1-ds { - samsung,pins = "gpr2-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_qrdy: sd1-qrdy { - samsung,pins = "gpr2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_int: sd1-int { - samsung,pins = "gpr2-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus1: sd1-bus-width1 { - samsung,pins = "gpr3-0"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus4: sd1-bus-width4 { - samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd1_bus8: sd1-bus-width8 { - samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_bus1 { - gpf0: gpf0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf1: gpf1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf2: gpf2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf3: gpf3 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf4: gpf4 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpf5: gpf5 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg1: gpg1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg2: gpg2 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph1: gph1 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpv6: gpv6 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - spi5_bus: spi5-bus { - samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ufs_refclk_out: ufs-refclk-out { - samsung,pins = "gpg2-4"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - ufs_rst_n: ufs-rst-n { - samsung,pins = "gph1-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; diff --git a/arch/arm64/boot/dts/exynos/exynos7-trip-points.dtsi b/arch/arm64/boot/dts/exynos/exynos7-trip-points.dtsi deleted file mode 100644 index d3301b8bd..000000000 --- a/arch/arm64/boot/dts/exynos/exynos7-trip-points.dtsi +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree sources for default Exynos7 thermal zone definition - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -trips { - cpu-alert-0 { - temperature = <75000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu-alert-1 { - temperature = <80000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu-alert-2 { - temperature = <85000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu-alert-3 { - temperature = <90000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu-alert-4 { - temperature = <95000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu-alert-5 { - temperature = <100000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu-alert-6 { - temperature = <110000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu-crit-0 { - temperature = <115000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; -}; diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi deleted file mode 100644 index 48952a556..000000000 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ /dev/null @@ -1,685 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung Exynos7 SoC device tree source - * - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -#include -#include - -/ { - compatible = "samsung,exynos7"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - pinctrl0 = &pinctrl_alive; - pinctrl1 = &pinctrl_bus0; - pinctrl2 = &pinctrl_nfc; - pinctrl3 = &pinctrl_touch; - pinctrl4 = &pinctrl_ff; - pinctrl5 = &pinctrl_ese; - pinctrl6 = &pinctrl_fsys0; - pinctrl7 = &pinctrl_fsys1; - pinctrl8 = &pinctrl_bus1; - tmuctrl0 = &tmuctrl_0; - }; - - arm-pmu { - compatible = "arm,cortex-a57-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>, - <&cpu_atlas2>, <&cpu_atlas3>; - }; - - fin_pll: clock { - /* XXTI */ - compatible = "fixed-clock"; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu_atlas0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0>; - enable-method = "psci"; - }; - - cpu_atlas1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1>; - enable-method = "psci"; - }; - - cpu_atlas2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x2>; - enable-method = "psci"; - }; - - cpu_atlas3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x3>; - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci"; - method = "smc"; - cpu_off = <0x84000002>; - cpu_on = <0xC4000003>; - }; - - soc: soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0x18000000>; - - chipid@10000000 { - compatible = "samsung,exynos4210-chipid"; - reg = <0x10000000 0x100>; - }; - - gic: interrupt-controller@11001000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x11001000 0x1000>, - <0x11002000 0x2000>, - <0x11004000 0x2000>, - <0x11006000 0x2000>; - }; - - pdma0: pdma@10e10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x10E10000 0x1000>; - interrupts = ; - clocks = <&clock_fsys0 ACLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - pdma1: pdma@10eb0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x10EB0000 0x1000>; - interrupts = ; - clocks = <&clock_fsys0 ACLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - clock_topc: clock-controller@10570000 { - compatible = "samsung,exynos7-clock-topc"; - reg = <0x10570000 0x10000>; - #clock-cells = <1>; - }; - - clock_top0: clock-controller@105d0000 { - compatible = "samsung,exynos7-clock-top0"; - reg = <0x105d0000 0xb000>; - #clock-cells = <1>; - clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, - <&clock_topc DOUT_SCLK_BUS1_PLL>, - <&clock_topc DOUT_SCLK_CC_PLL>, - <&clock_topc DOUT_SCLK_MFC_PLL>; - clock-names = "fin_pll", "dout_sclk_bus0_pll", - "dout_sclk_bus1_pll", "dout_sclk_cc_pll", - "dout_sclk_mfc_pll"; - }; - - clock_top1: clock-controller@105e0000 { - compatible = "samsung,exynos7-clock-top1"; - reg = <0x105e0000 0xb000>; - #clock-cells = <1>; - clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, - <&clock_topc DOUT_SCLK_BUS1_PLL>, - <&clock_topc DOUT_SCLK_CC_PLL>, - <&clock_topc DOUT_SCLK_MFC_PLL>; - clock-names = "fin_pll", "dout_sclk_bus0_pll", - "dout_sclk_bus1_pll", "dout_sclk_cc_pll", - "dout_sclk_mfc_pll"; - }; - - clock_ccore: clock-controller@105b0000 { - compatible = "samsung,exynos7-clock-ccore"; - reg = <0x105b0000 0xd00>; - #clock-cells = <1>; - clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>; - clock-names = "fin_pll", "dout_aclk_ccore_133"; - }; - - clock_peric0: clock-controller@13610000 { - compatible = "samsung,exynos7-clock-peric0"; - reg = <0x13610000 0xd00>; - #clock-cells = <1>; - clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>, - <&clock_top0 CLK_SCLK_UART0>; - clock-names = "fin_pll", "dout_aclk_peric0_66", - "sclk_uart0"; - }; - - clock_peric1: clock-controller@14c80000 { - compatible = "samsung,exynos7-clock-peric1"; - reg = <0x14c80000 0xd00>; - #clock-cells = <1>; - clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>, - <&clock_top0 CLK_SCLK_UART1>, - <&clock_top0 CLK_SCLK_UART2>, - <&clock_top0 CLK_SCLK_UART3>; - clock-names = "fin_pll", "dout_aclk_peric1_66", - "sclk_uart1", "sclk_uart2", "sclk_uart3"; - }; - - clock_peris: clock-controller@10040000 { - compatible = "samsung,exynos7-clock-peris"; - reg = <0x10040000 0xd00>; - #clock-cells = <1>; - clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>; - clock-names = "fin_pll", "dout_aclk_peris_66"; - }; - - clock_fsys0: clock-controller@10e90000 { - compatible = "samsung,exynos7-clock-fsys0"; - reg = <0x10e90000 0xd00>; - #clock-cells = <1>; - clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>, - <&clock_top1 DOUT_SCLK_MMC2>; - clock-names = "fin_pll", "dout_aclk_fsys0_200", - "dout_sclk_mmc2"; - }; - - clock_fsys1: clock-controller@156e0000 { - compatible = "samsung,exynos7-clock-fsys1"; - reg = <0x156e0000 0xd00>; - #clock-cells = <1>; - clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>, - <&clock_top1 DOUT_SCLK_MMC0>, - <&clock_top1 DOUT_SCLK_MMC1>, - <&clock_top1 DOUT_SCLK_UFSUNIPRO20>, - <&clock_top1 DOUT_SCLK_PHY_FSYS1>, - <&clock_top1 DOUT_SCLK_PHY_FSYS1_26M>; - clock-names = "fin_pll", "dout_aclk_fsys1_200", - "dout_sclk_mmc0", "dout_sclk_mmc1", - "dout_sclk_ufsunipro20", "dout_sclk_phy_fsys1", - "dout_sclk_phy_fsys1_26m"; - }; - - serial_0: serial@13630000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13630000 0x100>; - interrupts = ; - clocks = <&clock_peric0 PCLK_UART0>, - <&clock_peric0 SCLK_UART0>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - serial_1: serial@14c20000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x14c20000 0x100>; - interrupts = ; - clocks = <&clock_peric1 PCLK_UART1>, - <&clock_peric1 SCLK_UART1>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - serial_2: serial@14c30000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x14c30000 0x100>; - interrupts = ; - clocks = <&clock_peric1 PCLK_UART2>, - <&clock_peric1 SCLK_UART2>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - serial_3: serial@14c40000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x14c40000 0x100>; - interrupts = ; - clocks = <&clock_peric1 PCLK_UART3>, - <&clock_peric1 SCLK_UART3>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; - }; - - pinctrl_alive: pinctrl@10580000 { - compatible = "samsung,exynos7-pinctrl"; - reg = <0x10580000 0x1000>; - - wakeup-interrupt-controller { - compatible = "samsung,exynos7-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pinctrl_bus0: pinctrl@13470000 { - compatible = "samsung,exynos7-pinctrl"; - reg = <0x13470000 0x1000>; - interrupts = ; - }; - - pinctrl_nfc: pinctrl@14cd0000 { - compatible = "samsung,exynos7-pinctrl"; - reg = <0x14cd0000 0x1000>; - interrupts = ; - }; - - pinctrl_touch: pinctrl@14ce0000 { - compatible = "samsung,exynos7-pinctrl"; - reg = <0x14ce0000 0x1000>; - interrupts = ; - }; - - pinctrl_ff: pinctrl@14c90000 { - compatible = "samsung,exynos7-pinctrl"; - reg = <0x14c90000 0x1000>; - interrupts = ; - }; - - pinctrl_ese: pinctrl@14ca0000 { - compatible = "samsung,exynos7-pinctrl"; - reg = <0x14ca0000 0x1000>; - interrupts = ; - }; - - pinctrl_fsys0: pinctrl@10e60000 { - compatible = "samsung,exynos7-pinctrl"; - reg = <0x10e60000 0x1000>; - interrupts = ; - }; - - pinctrl_fsys1: pinctrl@15690000 { - compatible = "samsung,exynos7-pinctrl"; - reg = <0x15690000 0x1000>; - interrupts = ; - }; - - pinctrl_bus1: pinctrl@14870000 { - compatible = "samsung,exynos7-pinctrl"; - reg = <0x14870000 0x1000>; - interrupts = ; - }; - - hsi2c_0: hsi2c@13640000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x13640000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c0_bus>; - clocks = <&clock_peric0 PCLK_HSI2C0>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_1: hsi2c@13650000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x13650000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c1_bus>; - clocks = <&clock_peric0 PCLK_HSI2C1>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_2: hsi2c@14e60000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14e60000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c2_bus>; - clocks = <&clock_peric1 PCLK_HSI2C2>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_3: hsi2c@14e70000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14e70000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c3_bus>; - clocks = <&clock_peric1 PCLK_HSI2C3>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_4: hsi2c@13660000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x13660000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c4_bus>; - clocks = <&clock_peric0 PCLK_HSI2C4>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_5: hsi2c@13670000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x13670000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c5_bus>; - clocks = <&clock_peric0 PCLK_HSI2C5>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_6: hsi2c@14e00000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14e00000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c6_bus>; - clocks = <&clock_peric1 PCLK_HSI2C6>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_7: hsi2c@13e10000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x13e10000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c7_bus>; - clocks = <&clock_peric1 PCLK_HSI2C7>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_8: hsi2c@14e20000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x14e20000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c8_bus>; - clocks = <&clock_peric1 PCLK_HSI2C8>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_9: hsi2c@13680000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x13680000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c9_bus>; - clocks = <&clock_peric0 PCLK_HSI2C9>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_10: hsi2c@13690000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x13690000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c10_bus>; - clocks = <&clock_peric0 PCLK_HSI2C10>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - hsi2c_11: hsi2c@136a0000 { - compatible = "samsung,exynos7-hsi2c"; - reg = <0x136a0000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hs_i2c11_bus>; - clocks = <&clock_peric0 PCLK_HSI2C11>; - clock-names = "hsi2c"; - status = "disabled"; - }; - - pmu_system_controller: system-controller@105c0000 { - compatible = "samsung,exynos7-pmu", "syscon"; - reg = <0x105c0000 0x5000>; - }; - - rtc: rtc@10590000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x10590000 0x100>; - interrupts = , - ; - clocks = <&clock_ccore PCLK_RTC>; - clock-names = "rtc"; - status = "disabled"; - }; - - watchdog: watchdog@101d0000 { - compatible = "samsung,exynos7-wdt"; - reg = <0x101d0000 0x100>; - interrupts = ; - clocks = <&clock_peris PCLK_WDT>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - - gpu: gpu@14ac0000 { - compatible = "samsung,exynos5433-mali", "arm,mali-t760"; - reg = <0x14ac0000 0x5000>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - status = "disabled"; - /* TODO: operating points for DVFS, cooling device */ - }; - - mmc_0: mmc@15740000 { - compatible = "samsung,exynos7-dw-mshc-smu"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x15740000 0x2000>; - clocks = <&clock_fsys1 ACLK_MMC0>, - <&clock_top1 CLK_SCLK_MMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - mmc_1: mmc@15750000 { - compatible = "samsung,exynos7-dw-mshc"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x15750000 0x2000>; - clocks = <&clock_fsys1 ACLK_MMC1>, - <&clock_top1 CLK_SCLK_MMC1>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - mmc_2: mmc@15560000 { - compatible = "samsung,exynos7-dw-mshc-smu"; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x15560000 0x2000>; - clocks = <&clock_fsys0 ACLK_MMC2>, - <&clock_top1 CLK_SCLK_MMC2>; - clock-names = "biu", "ciu"; - fifo-depth = <0x40>; - status = "disabled"; - }; - - adc: adc@13620000 { - compatible = "samsung,exynos7-adc"; - reg = <0x13620000 0x100>; - interrupts = ; - clocks = <&clock_peric0 PCLK_ADCIF>; - clock-names = "adc"; - #io-channel-cells = <1>; - io-channel-ranges; - status = "disabled"; - }; - - pwm: pwm@136c0000 { - compatible = "samsung,exynos4210-pwm"; - reg = <0x136c0000 0x100>; - interrupts = , - , - , - , - ; - samsung,pwm-outputs = <0>, <1>, <2>, <3>; - #pwm-cells = <3>; - clocks = <&clock_peric0 PCLK_PWM>; - clock-names = "timers"; - }; - - tmuctrl_0: tmu@10060000 { - compatible = "samsung,exynos7-tmu"; - reg = <0x10060000 0x200>; - interrupts = ; - clocks = <&clock_peris PCLK_TMU>, - <&clock_peris SCLK_TMU>; - clock-names = "tmu_apbif", "tmu_sclk"; - #thermal-sensor-cells = <0>; - }; - - ufs: ufs@15570000 { - compatible = "samsung,exynos7-ufs"; - reg = <0x15570000 0x100>, /* 0: HCI standard */ - <0x15570100 0x100>, /* 1: Vendor specificed */ - <0x15571000 0x200>, /* 2: UNIPRO */ - <0x15572000 0x300>; /* 3: UFS protector */ - reg-names = "hci", "vs_hci", "unipro", "ufsp"; - interrupts = ; - clocks = <&clock_fsys1 ACLK_UFS20_LINK>, - <&clock_fsys1 SCLK_UFSUNIPRO20_USER>; - clock-names = "core_clk", "sclk_unipro_main"; - freq-table-hz = <0 0>, <0 0>; - pinctrl-names = "default"; - pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; - phys = <&ufs_phy>; - phy-names = "ufs-phy"; - status = "disabled"; - }; - - ufs_phy: ufs-phy@15571800 { - compatible = "samsung,exynos7-ufs-phy"; - reg = <0x15571800 0x240>; - reg-names = "phy-pma"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <0>; - clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>, - <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>, - <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>, - <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>; - clock-names = "ref_clk", "rx1_symbol_clk", - "rx0_symbol_clk", - "tx0_symbol_clk"; - }; - - usbdrd_phy: phy@15500000 { - compatible = "samsung,exynos7-usbdrd-phy"; - reg = <0x15500000 0x100>; - clocks = <&clock_fsys0 ACLK_USBDRD300>, - <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>, - <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>, - <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>, - <&clock_fsys0 SCLK_USBDRD300_REFCLK>; - clock-names = "phy", "ref", "phy_pipe", - "phy_utmi", "itp"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <1>; - }; - - usbdrd3 { - compatible = "samsung,exynos7-dwusb3"; - clocks = <&clock_fsys0 ACLK_USBDRD300>, - <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>, - <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>; - clock-names = "usbdrd30", "usbdrd30_susp_clk", - "usbdrd30_axius_clk"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dwc3@15400000 { - compatible = "snps,dwc3"; - reg = <0x15400000 0x10000>; - interrupts = ; - phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - }; - - thermal-zones { - atlas_thermal: cluster0-thermal { - polling-delay-passive = <0>; /* milliseconds */ - polling-delay = <0>; /* milliseconds */ - thermal-sensors = <&tmuctrl_0>; - #include "exynos7-trip-points.dtsi" - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; - -#include "exynos7-pinctrl.dtsi" -#include "arm/exynos-syscon-restart.dtsi" diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile deleted file mode 100644 index f8d59433a..000000000 --- a/arch/arm64/boot/dts/freescale/Makefile +++ /dev/null @@ -1,54 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-kbox-a-230-ls.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var2.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-clearfog-cx.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb - -dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r2.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r3.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mq-phanbell.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mq-thor96.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb - -dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts deleted file mode 100644 index 67702667e..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Freescale LS1012A Freedom Board. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * - */ -/dts-v1/; - -#include "fsl-ls1012a.dtsi" - -/ { - model = "LS1012A Freedom Board"; - compatible = "fsl,ls1012a-frdm", "fsl,ls1012a"; - - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker Ext", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Microphone Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Speaker Ext", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - frame-master; - bitclock-master; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - frame-master; - bitclock-master; - system-clock-frequency = <25000000>; - }; - }; -}; - -&duart0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - codec: sgtl5000@a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0xa>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_1p8v>; - clocks = <&sys_mclk>; - }; -}; - -&qspi { - status = "okay"; - - s25fs512s0: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - m25p,fast-read; - reg = <0>; - spi-rx-bus-width = <2>; - spi-tx-bus-width = <2>; - }; -}; - -&sai2 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts deleted file mode 100644 index 6290e2f9d..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Freescale LS1012A FRWY Board. - * - * Copyright 2018 NXP - * - * Pramod Kumar - * - */ -/dts-v1/; - -#include "fsl-ls1012a.dtsi" - -/ { - model = "LS1012A FRWY Board"; - compatible = "fsl,ls1012a-frwy", "fsl,ls1012a"; -}; - -&duart0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&qspi { - status = "okay"; - - w25q16dw0: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - m25p,fast-read; - spi-max-frequency = <50000000>; - reg = <0>; - spi-rx-bus-width = <2>; - spi-tx-bus-width = <2>; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts deleted file mode 100644 index 242f4b0cb..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Oxalis - * - * Copyright (c) 2019 Manivannan Sadhasivam - * - */ - -/dts-v1/; - -#include "fsl-ls1012a.dtsi" - -/ { - model = "Oxalis"; - compatible = "ebs-systart,oxalis", "fsl,ls1012a"; - - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker Ext", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Microphone Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Speaker Ext", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - frame-master; - bitclock-master; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - frame-master; - bitclock-master; - system-clock-frequency = <25000000>; - }; - }; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&esdhc1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - codec: audio-codec@a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0xa>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_1p8v>; - clocks = <&sys_mclk>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&sai2 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts deleted file mode 100644 index 449475a97..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Freescale LS1012A QDS Board. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * - */ -/dts-v1/; - -#include "fsl-ls1012a.dtsi" - -/ { - model = "LS1012A QDS Board"; - compatible = "fsl,ls1012a-qds", "fsl,ls1012a"; - - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker Ext", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Microphone Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Speaker Ext", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - frame-master; - bitclock-master; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - frame-master; - bitclock-master; - system-clock-frequency = <24576000>; - }; - }; -}; - -&dspi { - bus-num = <0>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a11", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - }; - - flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "sst25wf040b", "jedec,spi-nor"; - spi-cpol; - spi-cpha; - reg = <1>; - spi-max-frequency = <10000000>; - }; - - flash@2 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "en25s64", "jedec,spi-nor"; - spi-cpol; - spi-cpha; - reg = <2>; - spi-max-frequency = <10000000>; - }; -}; - -&duart0 { - status = "okay"; -}; - -&esdhc0 { - status = "okay"; -}; - -&esdhc1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - pca9547@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4>; - - codec: sgtl5000@a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0xa>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&sys_mclk>; - }; - }; - }; -}; - -&qspi { - status = "okay"; - - s25fs512s0: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - m25p,fast-read; - reg = <0>; - spi-rx-bus-width = <2>; - spi-tx-bus-width = <2>; - }; -}; - -&sai2 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts deleted file mode 100644 index d45c17620..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Freescale LS1012A RDB Board. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * - */ -/dts-v1/; - -#include "fsl-ls1012a.dtsi" - -/ { - model = "LS1012A RDB Board"; - compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; -}; - -&duart0 { - status = "okay"; -}; - -&esdhc0 { - sd-uhs-sdr104; - sd-uhs-sdr50; - sd-uhs-sdr25; - sd-uhs-sdr12; - status = "okay"; -}; - -&esdhc1 { - mmc-hs200-1_8v; - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&qspi { - status = "okay"; - - s25fs512s0: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - m25p,fast-read; - reg = <0>; - spi-rx-bus-width = <2>; - spi-tx-bus-width = <2>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi deleted file mode 100644 index 5fd3ea202..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ /dev/null @@ -1,540 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for NXP Layerscape-1012A family SoC. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2019-2020 NXP - * - */ - -#include -#include - -/ { - compatible = "fsl,ls1012a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - crypto = &crypto; - rtc1 = &ftm_alarm0; - rtic-a = &rtic_a; - rtic-b = &rtic_b; - rtic-c = &rtic_c; - rtic-d = &rtic_d; - sec-mon = &sec_mon; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - clocks = <&clockgen 1 0>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_PH20>; - }; - }; - - idle-states { - /* - * PSCI node is not added default, U-boot will add missing - * parts if it determines to use PSCI. - */ - entry-method = "psci"; - - CPU_PH20: cpu-ph20 { - compatible = "arm,idle-state"; - idle-state-name = "PH20"; - arm,psci-suspend-param = <0x0>; - entry-latency-us = <1000>; - exit-latency-us = <1000>; - min-residency-us = <3000>; - }; - }; - - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "sysclk"; - }; - - coreclk: coreclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "coreclk"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ - <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ - <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ - <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; - }; - - gic: interrupt-controller@1400000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x1401000 0 0x1000>, /* GICD */ - <0x0 0x1402000 0 0x2000>, /* GICC */ - <0x0 0x1404000 0 0x2000>, /* GICH */ - <0x0 0x1406000 0 0x2000>; /* GICV */ - interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>; - }; - - reboot { - compatible = "syscon-reboot"; - regmap = <&dcfg>; - offset = <0xb0>; - mask = <0x02>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 0>; - - trips { - cpu_alert: cpu-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - qspi: spi@1550000 { - compatible = "fsl,ls1021a-qspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x1550000 0x0 0x10000>, - <0x0 0x40000000 0x0 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = ; - clock-names = "qspi_en", "qspi"; - clocks = <&clockgen 4 0>, <&clockgen 4 0>; - status = "disabled"; - }; - - esdhc0: esdhc@1560000 { - compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; - reg = <0x0 0x1560000 0x0 0x10000>; - interrupts = <0 62 0x4>; - clocks = <&clockgen 4 0>; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - big-endian; - bus-width = <4>; - status = "disabled"; - }; - - scfg: scfg@1570000 { - compatible = "fsl,ls1012a-scfg", "syscon"; - reg = <0x0 0x1570000 0x0 0x10000>; - big-endian; - }; - - esdhc1: esdhc@1580000 { - compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; - reg = <0x0 0x1580000 0x0 0x10000>; - interrupts = <0 65 0x4>; - clocks = <&clockgen 4 0>; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - big-endian; - broken-cd; - bus-width = <4>; - status = "disabled"; - }; - - crypto: crypto@1700000 { - compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", - "fsl,sec-v4.0"; - fsl,sec-era = <8>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x1700000 0x100000>; - reg = <0x00 0x1700000 0x0 0x100000>; - interrupts = ; - dma-coherent; - - sec_jr0: jr@10000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; - interrupts = ; - }; - - sec_jr1: jr@20000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; - interrupts = ; - }; - - sec_jr2: jr@30000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; - interrupts = ; - }; - - sec_jr3: jr@40000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; - interrupts = ; - }; - - rtic@60000 { - compatible = "fsl,sec-v5.4-rtic", - "fsl,sec-v5.0-rtic", - "fsl,sec-v4.0-rtic"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x60000 0x100 0x60e00 0x18>; - ranges = <0x0 0x60100 0x500>; - - rtic_a: rtic-a@0 { - compatible = "fsl,sec-v5.4-rtic-memory", - "fsl,sec-v5.0-rtic-memory", - "fsl,sec-v4.0-rtic-memory"; - reg = <0x00 0x20 0x100 0x100>; - }; - - rtic_b: rtic-b@20 { - compatible = "fsl,sec-v5.4-rtic-memory", - "fsl,sec-v5.0-rtic-memory", - "fsl,sec-v4.0-rtic-memory"; - reg = <0x20 0x20 0x200 0x100>; - }; - - rtic_c: rtic-c@40 { - compatible = "fsl,sec-v5.4-rtic-memory", - "fsl,sec-v5.0-rtic-memory", - "fsl,sec-v4.0-rtic-memory"; - reg = <0x40 0x20 0x300 0x100>; - }; - - rtic_d: rtic-d@60 { - compatible = "fsl,sec-v5.4-rtic-memory", - "fsl,sec-v5.0-rtic-memory", - "fsl,sec-v4.0-rtic-memory"; - reg = <0x60 0x20 0x400 0x100>; - }; - }; - }; - - sec_mon: sec_mon@1e90000 { - compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon", - "fsl,sec-v4.0-mon"; - reg = <0x0 0x1e90000 0x0 0x10000>; - interrupts = , - ; - }; - - dcfg: dcfg@1ee0000 { - compatible = "fsl,ls1012a-dcfg", - "syscon"; - reg = <0x0 0x1ee0000 0x0 0x10000>; - big-endian; - }; - - clockgen: clocking@1ee1000 { - compatible = "fsl,ls1012a-clockgen"; - reg = <0x0 0x1ee1000 0x0 0x1000>; - #clock-cells = <2>; - clocks = <&sysclk &coreclk>; - clock-names = "sysclk", "coreclk"; - }; - - tmu: tmu@1f00000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x0 0x1f00000 0x0 0x10000>; - interrupts = <0 33 0x4>; - fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; - fsl,tmu-calibration = <0x00000000 0x00000026 - 0x00000001 0x0000002d - 0x00000002 0x00000032 - 0x00000003 0x00000039 - 0x00000004 0x0000003f - 0x00000005 0x00000046 - 0x00000006 0x0000004d - 0x00000007 0x00000054 - 0x00000008 0x0000005a - 0x00000009 0x00000061 - 0x0000000a 0x0000006a - 0x0000000b 0x00000071 - - 0x00010000 0x00000025 - 0x00010001 0x0000002c - 0x00010002 0x00000035 - 0x00010003 0x0000003d - 0x00010004 0x00000045 - 0x00010005 0x0000004e - 0x00010006 0x00000057 - 0x00010007 0x00000061 - 0x00010008 0x0000006b - 0x00010009 0x00000076 - - 0x00020000 0x00000029 - 0x00020001 0x00000033 - 0x00020002 0x0000003d - 0x00020003 0x00000049 - 0x00020004 0x00000056 - 0x00020005 0x00000061 - 0x00020006 0x0000006d - - 0x00030000 0x00000021 - 0x00030001 0x0000002a - 0x00030002 0x0000003c - 0x00030003 0x0000004e>; - big-endian; - #thermal-sensor-cells = <1>; - }; - - i2c0: i2c@2180000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2180000 0x0 0x10000>; - interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 3>; - status = "disabled"; - }; - - i2c1: i2c@2190000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2190000 0x0 0x10000>; - interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 3>; - status = "disabled"; - }; - - dspi: spi@2100000 { - compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "dspi"; - clocks = <&clockgen 4 0>; - spi-num-chipselects = <5>; - big-endian; - status = "disabled"; - }; - - duart0: serial@21c0500 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x00 0x21c0500 0x0 0x100>; - interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - - duart1: serial@21c0600 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x00 0x21c0600 0x0 0x100>; - interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - - gpio0: gpio@2300000 { - compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2310000 { - compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - wdog0: wdog@2ad0000 { - compatible = "fsl,ls1012a-wdt", - "fsl,imx21-wdt"; - reg = <0x0 0x2ad0000 0x0 0x10000>; - interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 0>; - big-endian; - }; - - sai1: sai@2b50000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; - reg = <0x0 0x2b50000 0x0 0x10000>; - interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>, - <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 47>, - <&edma0 1 46>; - status = "disabled"; - }; - - sai2: sai@2b60000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; - reg = <0x0 0x2b60000 0x0 0x10000>; - interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>, - <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 45>, - <&edma0 1 44>; - status = "disabled"; - }; - - edma0: edma@2c00000 { - #dma-cells = <2>; - compatible = "fsl,vf610-edma"; - reg = <0x0 0x2c00000 0x0 0x10000>, - <0x0 0x2c10000 0x0 0x10000>, - <0x0 0x2c20000 0x0 0x10000>; - interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>, - <0 103 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma-tx", "edma-err"; - dma-channels = <32>; - big-endian; - clock-names = "dmamux0", "dmamux1"; - clocks = <&clockgen 4 3>, - <&clockgen 4 3>; - }; - - usb0: usb3@2f00000 { - compatible = "snps,dwc3"; - reg = <0x0 0x2f00000 0x0 0x10000>; - interrupts = <0 60 0x4>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - sata: sata@3200000 { - compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>, - <0x0 0x20140520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 0>; - dma-coherent; - status = "disabled"; - }; - - usb1: usb2@8600000 { - compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; - reg = <0x0 0x8600000 0x0 0x1000>; - interrupts = <0 139 0x4>; - dr_mode = "host"; - phy_type = "ulpi"; - }; - - msi: msi-controller1@1572000 { - compatible = "fsl,ls1012a-msi"; - reg = <0x0 0x1572000 0x0 0x8>; - msi-controller; - interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; - }; - - pcie1: pcie@3400000 { - compatible = "fsl,ls1012a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = <0 118 0x4>, /* controller interrupt */ - <0 117 0x4>; /* PME interrupt */ - interrupt-names = "aer", "pme"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-viewport = <2>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - rcpm: power-controller@1ee2140 { - compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+"; - reg = <0x0 0x1ee2140 0x0 0x4>; - #fsl,rcpm-wakeup-cells = <1>; - }; - - ftm_alarm0: timer@29d0000 { - compatible = "fsl,ls1012a-ftm-alarm"; - reg = <0x0 0x29d0000 0x0 0x10000>; - fsl,rcpm-wakeup = <&rcpm 0x20000>; - interrupts = ; - big-endian; - }; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts deleted file mode 100644 index d66d8b2c3..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts +++ /dev/null @@ -1,109 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree File for the Kontron KBox A-230-LS. - * - * This consists of a Kontron SMARC-sAL28 (Dual PHY) and a special - * carrier (s1914). - * - * Copyright (C) 2019 Michael Walle - * - */ - -/dts-v1/; -#include "fsl-ls1028a-kontron-sl28-var4.dts" -#include - -/ { - model = "Kontron KBox A-230-LS"; - compatible = "kontron,kbox-a-230-ls", "kontron,sl28-var4", - "kontron,sl28", "fsl,ls1028a"; - - leds { - compatible = "gpio-leds"; - - alarm-led { - function = LED_FUNCTION_ALARM; - color = ; - gpios = <&sl28cpld_gpio0 0 GPIO_ACTIVE_HIGH>; - }; - - power-led { - linux,default-trigger = "default-on"; - function = LED_FUNCTION_POWER; - color = ; - gpios = <&sl28cpld_gpio1 3 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&enetc_mdio_pf3 { - /* BCM54140 QSGMII quad PHY */ - qsgmii_phy0: ethernet-phy@7 { - reg = <7>; - }; - - qsgmii_phy1: ethernet-phy@8 { - reg = <8>; - }; - - qsgmii_phy2: ethernet-phy@9 { - reg = <9>; - }; - - qsgmii_phy3: ethernet-phy@10 { - reg = <10>; - }; -}; - -&enetc_port2 { - status = "okay"; -}; - -&i2c3 { - eeprom@57 { - compatible = "atmel,24c32"; - reg = <0x57>; - pagesize = <32>; - }; -}; - -&mscc_felix { - status = "okay"; -}; - -&mscc_felix_port0 { - label = "swp0"; - managed = "in-band-status"; - phy-handle = <&qsgmii_phy0>; - phy-mode = "qsgmii"; - status = "okay"; -}; - -&mscc_felix_port1 { - label = "swp1"; - managed = "in-band-status"; - phy-handle = <&qsgmii_phy1>; - phy-mode = "qsgmii"; - status = "okay"; -}; - -&mscc_felix_port2 { - label = "swp2"; - managed = "in-band-status"; - phy-handle = <&qsgmii_phy2>; - phy-mode = "qsgmii"; - status = "okay"; -}; - -&mscc_felix_port3 { - label = "swp3"; - managed = "in-band-status"; - phy-handle = <&qsgmii_phy3>; - phy-mode = "qsgmii"; - status = "okay"; -}; - -&mscc_felix_port4 { - ethernet = <&enetc_port2>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts deleted file mode 100644 index f6a79c808..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for the Kontron SMARC-sAL28 board. - * - * This is for the network variant 2 which has two ethernet ports. These - * ports are connected to the internal switch. - * - * Copyright (C) 2020 Michael Walle - * - */ - -/dts-v1/; -#include "fsl-ls1028a-kontron-sl28.dts" - -/ { - model = "Kontron SMARC-sAL28 (TSN-on-module)"; - compatible = "kontron,sl28-var2", "kontron,sl28", "fsl,ls1028a"; -}; - -&enetc_mdio_pf3 { - phy0: ethernet-phy@5 { - reg = <0x5>; - eee-broken-1000t; - eee-broken-100tx; - }; - - phy1: ethernet-phy@4 { - reg = <0x4>; - eee-broken-1000t; - eee-broken-100tx; - }; -}; - -&enetc_port0 { - status = "disabled"; - /* - * In the base device tree the PHY was registered in the mdio - * subnode as it is PHY for this port. On this module this PHY - * is connected to a switch port instead and registered above. - * Therefore, delete the mdio subnode as well as the phy-handle - * property here. - */ - /delete-property/ phy-handle; - /delete-node/ mdio; -}; - -&enetc_port2 { - status = "okay"; -}; - -&mscc_felix { - status = "okay"; -}; - -&mscc_felix_port0 { - label = "swp0"; - managed = "in-band-status"; - phy-handle = <&phy0>; - phy-mode = "sgmii"; - status = "okay"; -}; - -&mscc_felix_port1 { - label = "swp1"; - managed = "in-band-status"; - phy-handle = <&phy1>; - phy-mode = "sgmii"; - status = "okay"; -}; - -&mscc_felix_port4 { - ethernet = <&enetc_port2>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts deleted file mode 100644 index c45d7b40e..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts +++ /dev/null @@ -1,126 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for the Kontron SMARC-sAL28 board on a SMARC Eval 2.0 - * carrier (ADS2). - * - * Copyright (C) 2019 Michael Walle - * - */ - -/dts-v1/; -#include "fsl-ls1028a-kontron-sl28.dts" - -/ { - model = "Kontron SMARC-sAL28 (Single PHY) on SMARC Eval 2.0 carrier"; - compatible = "kontron,sl28-var3-ads2", "kontron,sl28-var3", - "kontron,sl28", "fsl,ls1028a"; - - pwm-fan { - compatible = "pwm-fan"; - cooling-min-state = <0>; - cooling-max-state = <3>; - #cooling-cells = <2>; - pwms = <&sl28cpld_pwm0 0 4000000>; - cooling-levels = <1 128 192 255>; - }; - - sound { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-audio-card"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line Out Jack", - "Microphone", "Microphone Jack", - "Line", "Line In Jack"; - simple-audio-card,routing = - "Line Out Jack", "LINEOUTR", - "Line Out Jack", "LINEOUTL", - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "IN1L", "Line In Jack", - "IN1R", "Line In Jack", - "Microphone Jack", "MICBIAS", - "IN2L", "Microphone Jack", - "IN2R", "Microphone Jack"; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,dai-link@0 { - reg = <0>; - bitclock-master = <&dailink0_master>; - frame-master = <&dailink0_master>; - format = "i2s"; - - cpu { - sound-dai = <&sai6>; - }; - - dailink0_master: codec { - sound-dai = <&wm8904>; - }; - }; - - simple-audio-card,dai-link@1 { - reg = <1>; - bitclock-master = <&dailink1_master>; - frame-master = <&dailink1_master>; - format = "i2s"; - - cpu { - sound-dai = <&sai5>; - }; - - dailink1_master: codec { - sound-dai = <&wm8904>; - }; - }; - }; -}; - -&dspi2 { - flash@0 { - compatible = "jedec,spi-nor"; - m25p,fast-read; - spi-max-frequency = <100000000>; - reg = <0>; - }; -}; - -&i2c3 { - eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - pagesize = <32>; - }; -}; - -&i2c4 { - status = "okay"; - - wm8904: audio-codec@1a { - #sound-dai-cells = <0>; - compatible = "wlf,wm8904"; - reg = <0x1a>; - clocks = <&mclk>; - clock-names = "mclk"; - assigned-clocks = <&mclk>; - assigned-clock-rates = <1250000>; - }; -}; - -&sai5 { - status = "okay"; -}; - -&sai6 { - status = "okay"; -}; - -&soc { - mclk: clock-mclk@f130080 { - compatible = "fsl,vf610-sai-clock"; - reg = <0x0 0xf130080 0x0 0x80>; - clocks = <&clockgen 4 1>; - #clock-cells = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts deleted file mode 100644 index e65d1c477..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for the Kontron SMARC-sAL28 board. - * - * This is for the network variant 4 which has two ethernet ports. It - * extends the base and provides one more port connected via RGMII. - * - * Copyright (C) 2019 Michael Walle - * - */ - -/dts-v1/; -#include "fsl-ls1028a-kontron-sl28.dts" -#include - -/ { - model = "Kontron SMARC-sAL28 (Dual PHY)"; - compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a"; -}; - -&enetc_port1 { - phy-handle = <&phy1>; - phy-connection-type = "rgmii-id"; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy1: ethernet-phy@4 { - reg = <0x4>; - eee-broken-1000t; - eee-broken-100tx; - qca,clk-out-frequency = <125000000>; - qca,clk-out-strength = ; - qca,keep-pll-enabled; - vddio-supply = <&vddio>; - - vddio: vddio-regulator { - regulator-name = "VDDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddh: vddh-regulator { - regulator-name = "VDDH"; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts deleted file mode 100644 index b3fa4dbee..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts +++ /dev/null @@ -1,317 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree file for the Kontron SMARC-sAL28 board. - * - * Copyright (C) 2019 Michael Walle - * - */ - -/dts-v1/; -#include "fsl-ls1028a.dtsi" -#include -#include -#include - -/ { - model = "Kontron SMARC-sAL28"; - compatible = "kontron,sl28", "fsl,ls1028a"; - - aliases { - crypto = &crypto; - serial0 = &duart0; - serial1 = &duart1; - serial2 = &lpuart1; - spi0 = &fspi; - spi1 = &dspi2; - }; - - buttons0 { - compatible = "gpio-keys"; - - power-button { - interrupts-extended = <&sl28cpld_intc - 4 IRQ_TYPE_EDGE_BOTH>; - linux,code = ; - label = "Power"; - }; - - sleep-button { - interrupts-extended = <&sl28cpld_intc - 5 IRQ_TYPE_EDGE_BOTH>; - linux,code = ; - label = "Sleep"; - }; - }; - - buttons1 { - compatible = "gpio-keys-polled"; - poll-interval = <200>; - - lid-switch { - linux,input-type = ; - linux,code = ; - gpios = <&sl28cpld_gpio3 4 GPIO_ACTIVE_LOW>; - label = "Lid"; - }; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&dspi2 { - status = "okay"; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&enetc_port0 { - phy-handle = <&phy0>; - phy-connection-type = "sgmii"; - managed = "in-band-status"; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@5 { - reg = <0x5>; - eee-broken-1000t; - eee-broken-100tx; - }; - }; -}; - -&esdhc { - sd-uhs-sdr104; - sd-uhs-sdr50; - sd-uhs-sdr25; - sd-uhs-sdr12; - status = "okay"; -}; - -&esdhc1 { - mmc-hs200-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - status = "okay"; -}; - -&fspi { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - m25p,fast-read; - spi-max-frequency = <133000000>; - reg = <0>; - /* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */ - spi-rx-bus-width = <2>; /* 2 SPI Rx lines */ - spi-tx-bus-width = <1>; /* 1 SPI Tx line */ - - partition@0 { - reg = <0x000000 0x010000>; - label = "rcw"; - read-only; - }; - - partition@10000 { - reg = <0x010000 0x0f0000>; - label = "failsafe bootloader"; - read-only; - }; - - partition@100000 { - reg = <0x100000 0x040000>; - label = "failsafe DP firmware"; - read-only; - }; - - partition@140000 { - reg = <0x140000 0x0a0000>; - label = "failsafe trusted firmware"; - read-only; - }; - - partition@1e0000 { - reg = <0x1e0000 0x020000>; - label = "reserved"; - read-only; - }; - - partition@200000 { - reg = <0x200000 0x010000>; - label = "configuration store"; - }; - - partition@210000 { - reg = <0x210000 0x1d0000>; - label = "bootloader"; - }; - - partition@3e0000 { - reg = <0x3e0000 0x020000>; - label = "bootloader environment"; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "TDO", "TCK", - "", "", "", "", "", "", "", ""; -}; - -&gpio2 { - gpio-line-names = - "", "", "", "", "", "", "TMS", "TDI", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c0 { - status = "okay"; - - rtc@32 { - compatible = "microcrystal,rv8803"; - reg = <0x32>; - }; - - sl28cpld@4a { - compatible = "kontron,sl28cpld"; - reg = <0x4a>; - #address-cells = <1>; - #size-cells = <0>; - - watchdog@4 { - compatible = "kontron,sl28cpld-wdt"; - reg = <0x4>; - kontron,assert-wdt-timeout-pin; - }; - - hwmon@b { - compatible = "kontron,sl28cpld-fan"; - reg = <0xb>; - }; - - sl28cpld_pwm0: pwm@c { - compatible = "kontron,sl28cpld-pwm"; - reg = <0xc>; - #pwm-cells = <2>; - }; - - sl28cpld_pwm1: pwm@e { - compatible = "kontron,sl28cpld-pwm"; - reg = <0xe>; - #pwm-cells = <2>; - }; - - sl28cpld_gpio0: gpio@10 { - compatible = "kontron,sl28cpld-gpio"; - reg = <0x10>; - interrupts-extended = <&gpio2 6 - IRQ_TYPE_EDGE_FALLING>; - - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - "GPIO0_CAM0_PWR_N", "GPIO1_CAM1_PWR_N", - "GPIO2_CAM0_RST_N", "GPIO3_CAM1_RST_N", - "GPIO4_HDA_RST_N", "GPIO5_PWM_OUT", - "GPIO6_TACHIN", "GPIO7"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sl28cpld_gpio1: gpio@15 { - compatible = "kontron,sl28cpld-gpio"; - reg = <0x15>; - interrupts-extended = <&gpio2 6 - IRQ_TYPE_EDGE_FALLING>; - - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - "GPIO8", "GPIO9", "GPIO10", "GPIO11", - "", "", "", ""; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - sl28cpld_gpio2: gpio@1a { - compatible = "kontron,sl28cpld-gpo"; - reg = <0x1a>; - - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - "LCD0 voltage enable", - "LCD0 backlight enable", - "eMMC reset", "LVDS bridge reset", - "LVDS bridge power-down", - "SDIO power enable", - "", ""; - }; - - sl28cpld_gpio3: gpio@1b { - compatible = "kontron,sl28cpld-gpi"; - reg = <0x1b>; - - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - "Power button", "Force recovery", "Sleep", - "Battery low", "Lid state", "Charging", - "Charger present", ""; - }; - - sl28cpld_intc: interrupt-controller@1c { - compatible = "kontron,sl28cpld-intc"; - reg = <0x1c>; - interrupts-extended = <&gpio2 6 - IRQ_TYPE_EDGE_FALLING>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&lpuart1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts deleted file mode 100644 index 71858c937..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ /dev/null @@ -1,330 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for NXP LS1028A QDS Board. - * - * Copyright 2018 NXP - * - * Harninder Rai - * - */ - -/dts-v1/; - -#include "fsl-ls1028a.dtsi" - -/ { - model = "LS1028A QDS Board"; - compatible = "fsl,ls1028a-qds", "fsl,ls1028a"; - - aliases { - crypto = &crypto; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - serial0 = &duart0; - serial1 = &duart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x1 0x00000000>; - }; - - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - sb_3v3: regulator-sb3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker Ext", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Microphone Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Speaker Ext", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai1>; - frame-master; - bitclock-master; - }; - - simple-audio-card,codec { - sound-dai = <&sgtl5000>; - frame-master; - bitclock-master; - system-clock-frequency = <25000000>; - }; - }; - - mdio-mux { - compatible = "mdio-mux-multiplexer"; - mux-controls = <&mux 0>; - mdio-parent-bus = <&enetc_mdio_pf3>; - #address-cells=<1>; - #size-cells = <0>; - - /* on-board RGMII PHY */ - mdio@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - qds_phy1: ethernet-phy@5 { - /* Atheros 8035 */ - reg = <5>; - }; - }; - }; -}; - -&dspi0 { - bus-num = <0>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-cpol; - spi-cpha; - reg = <0>; - spi-max-frequency = <10000000>; - }; - - flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-cpol; - spi-cpha; - reg = <1>; - spi-max-frequency = <10000000>; - }; - - flash@2 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-cpol; - spi-cpha; - reg = <2>; - spi-max-frequency = <10000000>; - }; -}; - -&dspi1 { - bus-num = <1>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-cpol; - spi-cpha; - reg = <0>; - spi-max-frequency = <10000000>; - }; - - flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-cpol; - spi-cpha; - reg = <1>; - spi-max-frequency = <10000000>; - }; - - flash@2 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-cpol; - spi-cpha; - reg = <2>; - spi-max-frequency = <10000000>; - }; -}; - -&dspi2 { - bus-num = <2>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-cpol; - spi-cpha; - reg = <0>; - spi-max-frequency = <10000000>; - }; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&esdhc { - status = "okay"; -}; - -&esdhc1 { - status = "okay"; -}; - -&fspi { - status = "okay"; - - mt35xu02g0: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */ - spi-rx-bus-width = <8>; /* 8 SPI Rx lines */ - spi-tx-bus-width = <1>; /* 1 SPI Tx line */ - reg = <0>; - }; -}; - -&i2c0 { - status = "okay"; - - i2c-mux@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - - current-monitor@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - - current-monitor@41 { - compatible = "ti,ina220"; - reg = <0x41>; - shunt-resistor = <1000>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - temperature-sensor@4c { - compatible = "nxp,sa56004"; - reg = <0x4c>; - vcc-supply = <&sb_3v3>; - }; - - eeprom@56 { - compatible = "atmel,24c512"; - reg = <0x56>; - }; - - eeprom@57 { - compatible = "atmel,24c512"; - reg = <0x57>; - }; - }; - - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x5>; - - sgtl5000: audio-codec@a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0xa>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_1p8v>; - clocks = <&sys_mclk>; - }; - }; - }; - - fpga@66 { - compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c", - "simple-mfd"; - reg = <0x66>; - - mux: mux-controller { - compatible = "reg-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x54 0xf0>; /* 0: reg 0x54, bits 7:4 */ - }; - }; - -}; - -&i2c1 { - status = "okay"; - - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - }; -}; - -&enetc_port1 { - phy-handle = <&qds_phy1>; - phy-connection-type = "rgmii-id"; - status = "okay"; -}; - -&lpuart0 { - status = "okay"; -}; - -&sai1 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts deleted file mode 100644 index 1efb61cff..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ /dev/null @@ -1,269 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for NXP LS1028A RDB Board. - * - * Copyright 2018 NXP - * - * Harninder Rai - * - */ - -/dts-v1/; -#include "fsl-ls1028a.dtsi" - -/ { - model = "LS1028A RDB Board"; - compatible = "fsl,ls1028a-rdb", "fsl,ls1028a"; - - aliases { - crypto = &crypto; - serial0 = &duart0; - serial1 = &duart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x1 0x0000000>; - }; - - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - sb_3v3: regulator-sb3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker Ext", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Microphone Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Speaker Ext", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai4>; - frame-master; - bitclock-master; - }; - - simple-audio-card,codec { - sound-dai = <&sgtl5000>; - frame-master; - bitclock-master; - system-clock-frequency = <25000000>; - }; - }; -}; - -&esdhc { - sd-uhs-sdr104; - sd-uhs-sdr50; - sd-uhs-sdr25; - sd-uhs-sdr12; - status = "okay"; -}; - -&esdhc1 { - mmc-hs200-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - status = "okay"; -}; - -&fspi { - status = "okay"; - - mt35xu02g0: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */ - spi-rx-bus-width = <8>; /* 8 SPI Rx lines */ - spi-tx-bus-width = <1>; /* 1 SPI Tx line */ - reg = <0>; - }; -}; - -&i2c0 { - status = "okay"; - - i2c-mux@77 { - compatible = "nxp,pca9847"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1>; - - sgtl5000: audio-codec@a { - #sound-dai-cells = <0>; - compatible = "fsl,sgtl5000"; - reg = <0xa>; - VDDA-supply = <®_1p8v>; - VDDIO-supply = <®_1p8v>; - clocks = <&sys_mclk>; - sclk-strength = <3>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x02>; - - current-monitor@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <500>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - temperature-sensor@4c { - compatible = "nxp,sa56004"; - reg = <0x4c>; - vcc-supply = <&sb_3v3>; - }; - - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - }; - }; - }; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&enetc_mdio_pf3 { - /* VSC8514 QSGMII quad PHY */ - qsgmii_phy0: ethernet-phy@10 { - reg = <0x10>; - }; - - qsgmii_phy1: ethernet-phy@11 { - reg = <0x11>; - }; - - qsgmii_phy2: ethernet-phy@12 { - reg = <0x12>; - }; - - qsgmii_phy3: ethernet-phy@13 { - reg = <0x13>; - }; -}; - -&enetc_port0 { - phy-handle = <&sgmii_phy0>; - phy-connection-type = "sgmii"; - managed = "in-band-status"; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - sgmii_phy0: ethernet-phy@2 { - reg = <0x2>; - }; - }; -}; - -&enetc_port2 { - status = "okay"; -}; - -&mscc_felix { - status = "okay"; -}; - -&mscc_felix_port0 { - label = "swp0"; - managed = "in-band-status"; - phy-handle = <&qsgmii_phy0>; - phy-mode = "qsgmii"; - status = "okay"; -}; - -&mscc_felix_port1 { - label = "swp1"; - managed = "in-band-status"; - phy-handle = <&qsgmii_phy1>; - phy-mode = "qsgmii"; - status = "okay"; -}; - -&mscc_felix_port2 { - label = "swp2"; - managed = "in-band-status"; - phy-handle = <&qsgmii_phy2>; - phy-mode = "qsgmii"; - status = "okay"; -}; - -&mscc_felix_port3 { - label = "swp3"; - managed = "in-band-status"; - phy-handle = <&qsgmii_phy3>; - phy-mode = "qsgmii"; - status = "okay"; -}; - -&mscc_felix_port4 { - ethernet = <&enetc_port2>; - status = "okay"; -}; - -&sai4 { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&usb1 { - dr_mode = "otg"; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi deleted file mode 100644 index 580690057..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ /dev/null @@ -1,1062 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for NXP Layerscape-1028A family SoC. - * - * Copyright 2018-2020 NXP - * - * Harninder Rai - * - */ - -#include -#include - -/ { - compatible = "fsl,ls1028a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - rtc1 = &ftm_alarm0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0>; - enable-method = "psci"; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_PW20>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x1>; - enable-method = "psci"; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_PW20>; - #cooling-cells = <2>; - }; - - l2: l2-cache { - compatible = "cache"; - }; - }; - - idle-states { - /* - * PSCI node is not added default, U-boot will add missing - * parts if it determines to use PSCI. - */ - entry-method = "psci"; - - CPU_PW20: cpu-pw20 { - compatible = "arm,idle-state"; - idle-state-name = "PW20"; - arm,psci-suspend-param = <0x0>; - entry-latency-us = <2000>; - exit-latency-us = <2000>; - min-residency-us = <6000>; - }; - }; - - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "sysclk"; - }; - - osc_27m: clock-osc-27m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - clock-output-names = "phy_27m"; - }; - - dpclk: clock-controller@f1f0000 { - compatible = "fsl,ls1028a-plldig"; - reg = <0x0 0xf1f0000 0x0 0xffff>; - #clock-cells = <0>; - clocks = <&osc_27m>; - }; - - reboot { - compatible ="syscon-reboot"; - regmap = <&rst>; - offset = <0>; - mask = <0x02>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a72-pmu"; - interrupts = ; - }; - - gic: interrupt-controller@6000000 { - compatible= "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ - <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ - #interrupt-cells= <3>; - interrupt-controller; - interrupts = ; - its: gic-its@6020000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ - }; - }; - - thermal-zones { - ddr-controller { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 0>; - - trips { - ddr-ctrler-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - ddr-ctrler-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - core-cluster { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 1>; - - trips { - core_cluster_alert: core-cluster-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - core_cluster_crit: core-cluster-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&core_cluster_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ddr: memory-controller@1080000 { - compatible = "fsl,qoriq-memory-controller"; - reg = <0x0 0x1080000 0x0 0x1000>; - interrupts = ; - little-endian; - }; - - dcfg: syscon@1e00000 { - compatible = "fsl,ls1028a-dcfg", "syscon"; - reg = <0x0 0x1e00000 0x0 0x10000>; - little-endian; - }; - - rst: syscon@1e60000 { - compatible = "syscon"; - reg = <0x0 0x1e60000 0x0 0x10000>; - little-endian; - }; - - scfg: syscon@1fc0000 { - compatible = "fsl,ls1028a-scfg", "syscon"; - reg = <0x0 0x1fc0000 0x0 0x10000>; - big-endian; - }; - - clockgen: clock-controller@1300000 { - compatible = "fsl,ls1028a-clockgen"; - reg = <0x0 0x1300000 0x0 0xa0000>; - #clock-cells = <2>; - clocks = <&sysclk>; - }; - - i2c0: i2c@2000000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2000000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 3>; - status = "disabled"; - }; - - i2c1: i2c@2010000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2010000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 3>; - status = "disabled"; - }; - - i2c2: i2c@2020000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2020000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 3>; - status = "disabled"; - }; - - i2c3: i2c@2030000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2030000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 3>; - status = "disabled"; - }; - - i2c4: i2c@2040000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2040000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 3>; - status = "disabled"; - }; - - i2c5: i2c@2050000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2050000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 3>; - status = "disabled"; - }; - - i2c6: i2c@2060000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2060000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 3>; - status = "disabled"; - }; - - i2c7: i2c@2070000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2070000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 3>; - status = "disabled"; - }; - - fspi: spi@20c0000 { - compatible = "nxp,lx2160a-fspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x20c0000 0x0 0x10000>, - <0x0 0x20000000 0x0 0x10000000>; - reg-names = "fspi_base", "fspi_mmap"; - interrupts = ; - clocks = <&clockgen 2 0>, <&clockgen 2 0>; - clock-names = "fspi_en", "fspi"; - status = "disabled"; - }; - - dspi0: spi@2100000 { - compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = ; - clock-names = "dspi"; - clocks = <&clockgen 4 1>; - dmas = <&edma0 0 62>, <&edma0 0 60>; - dma-names = "tx", "rx"; - spi-num-chipselects = <4>; - little-endian; - status = "disabled"; - }; - - dspi1: spi@2110000 { - compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2110000 0x0 0x10000>; - interrupts = ; - clock-names = "dspi"; - clocks = <&clockgen 4 1>; - dmas = <&edma0 0 58>, <&edma0 0 56>; - dma-names = "tx", "rx"; - spi-num-chipselects = <4>; - little-endian; - status = "disabled"; - }; - - dspi2: spi@2120000 { - compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2120000 0x0 0x10000>; - interrupts = ; - clock-names = "dspi"; - clocks = <&clockgen 4 1>; - dmas = <&edma0 0 54>, <&edma0 0 2>; - dma-names = "tx", "rx"; - spi-num-chipselects = <3>; - little-endian; - status = "disabled"; - }; - - esdhc: mmc@2140000 { - compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; - reg = <0x0 0x2140000 0x0 0x10000>; - interrupts = ; - clock-frequency = <0>; /* fixed up by bootloader */ - clocks = <&clockgen 2 1>; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - little-endian; - bus-width = <4>; - status = "disabled"; - }; - - esdhc1: mmc@2150000 { - compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; - reg = <0x0 0x2150000 0x0 0x10000>; - interrupts = ; - clock-frequency = <0>; /* fixed up by bootloader */ - clocks = <&clockgen 2 1>; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - broken-cd; - little-endian; - bus-width = <4>; - status = "disabled"; - }; - - can0: can@2180000 { - compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan"; - reg = <0x0 0x2180000 0x0 0x10000>; - interrupts = ; - clocks = <&sysclk>, <&clockgen 4 1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - can1: can@2190000 { - compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan"; - reg = <0x0 0x2190000 0x0 0x10000>; - interrupts = ; - clocks = <&sysclk>, <&clockgen 4 1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - duart0: serial@21c0500 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x00 0x21c0500 0x0 0x100>; - interrupts = ; - clocks = <&clockgen 4 1>; - status = "disabled"; - }; - - duart1: serial@21c0600 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x00 0x21c0600 0x0 0x100>; - interrupts = ; - clocks = <&clockgen 4 1>; - status = "disabled"; - }; - - - lpuart0: serial@2260000 { - compatible = "fsl,ls1028a-lpuart"; - reg = <0x0 0x2260000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - dma-names = "rx","tx"; - dmas = <&edma0 1 32>, - <&edma0 1 33>; - status = "disabled"; - }; - - lpuart1: serial@2270000 { - compatible = "fsl,ls1028a-lpuart"; - reg = <0x0 0x2270000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - dma-names = "rx","tx"; - dmas = <&edma0 1 30>, - <&edma0 1 31>; - status = "disabled"; - }; - - lpuart2: serial@2280000 { - compatible = "fsl,ls1028a-lpuart"; - reg = <0x0 0x2280000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - dma-names = "rx","tx"; - dmas = <&edma0 1 28>, - <&edma0 1 29>; - status = "disabled"; - }; - - lpuart3: serial@2290000 { - compatible = "fsl,ls1028a-lpuart"; - reg = <0x0 0x2290000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - dma-names = "rx","tx"; - dmas = <&edma0 1 26>, - <&edma0 1 27>; - status = "disabled"; - }; - - lpuart4: serial@22a0000 { - compatible = "fsl,ls1028a-lpuart"; - reg = <0x0 0x22a0000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - dma-names = "rx","tx"; - dmas = <&edma0 1 24>, - <&edma0 1 25>; - status = "disabled"; - }; - - lpuart5: serial@22b0000 { - compatible = "fsl,ls1028a-lpuart"; - reg = <0x0 0x22b0000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - dma-names = "rx","tx"; - dmas = <&edma0 1 22>, - <&edma0 1 23>; - status = "disabled"; - }; - - edma0: dma-controller@22c0000 { - #dma-cells = <2>; - compatible = "fsl,ls1028a-edma", "fsl,vf610-edma"; - reg = <0x0 0x22c0000 0x0 0x10000>, - <0x0 0x22d0000 0x0 0x10000>, - <0x0 0x22e0000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "edma-tx", "edma-err"; - dma-channels = <32>; - clock-names = "dmamux0", "dmamux1"; - clocks = <&clockgen 4 1>, - <&clockgen 4 1>; - }; - - gpio1: gpio@2300000 { - compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - little-endian; - }; - - gpio2: gpio@2310000 { - compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - little-endian; - }; - - gpio3: gpio@2320000 { - compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - little-endian; - }; - - usb0: usb@3100000 { - compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - snps,dis_rxdet_inp3_quirk; - snps,quirk-frame-length-adjustment = <0x20>; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - usb1: usb@3110000 { - compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; - reg = <0x0 0x3110000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - snps,dis_rxdet_inp3_quirk; - snps,quirk-frame-length-adjustment = <0x20>; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - sata: sata@3200000 { - compatible = "fsl,ls1028a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>, - <0x7 0x100520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = ; - clocks = <&clockgen 4 1>; - status = "disabled"; - }; - - pcie1: pcie@3400000 { - compatible = "fsl,ls1028a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = , /* PME interrupt */ - ; /* aer interrupt */ - interrupt-names = "pme", "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <8>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - pcie2: pcie@3500000 { - compatible = "fsl,ls1028a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = , - ; - interrupt-names = "pme", "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <8>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - smmu: iommu@5000000 { - compatible = "arm,mmu-500"; - reg = <0 0x5000000 0 0x800000>; - #global-interrupts = <8>; - #iommu-cells = <1>; - stream-match-mask = <0x7c00>; - /* global secure fault */ - interrupts = , - /* combined secure interrupt */ - , - /* global non-secure fault */ - , - /* combined non-secure interrupt */ - , - /* performance counter interrupts 0-7 */ - , , - , , - /* per context interrupt, 64 interrupts */ - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , ; - }; - - crypto: crypto@8000000 { - compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; - fsl,sec-era = <10>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x8000000 0x100000>; - reg = <0x00 0x8000000 0x0 0x100000>; - interrupts = ; - dma-coherent; - - sec_jr0: jr@10000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; - interrupts = ; - }; - - sec_jr1: jr@20000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; - interrupts = ; - }; - - sec_jr2: jr@30000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; - interrupts = ; - }; - - sec_jr3: jr@40000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; - interrupts = ; - }; - }; - - qdma: dma-controller@8380000 { - compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; - reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ - <0x0 0x8390000 0x0 0x10000>, /* Status regs */ - <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ - interrupts = , - , - , - , - ; - interrupt-names = "qdma-error", "qdma-queue0", - "qdma-queue1", "qdma-queue2", "qdma-queue3"; - dma-channels = <8>; - block-number = <1>; - block-offset = <0x10000>; - fsl,dma-queues = <2>; - status-sizes = <64>; - queue-sizes = <64 64>; - }; - - cluster1_core0_watchdog: watchdog@c000000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xc000000 0x0 0x1000>; - clocks = <&clockgen 4 15>, <&clockgen 4 15>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - cluster1_core1_watchdog: watchdog@c010000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xc010000 0x0 0x1000>; - clocks = <&clockgen 4 15>, <&clockgen 4 15>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - sai1: audio-controller@f100000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; - reg = <0x0 0xf100000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 4>, - <&edma0 1 3>; - fsl,sai-asynchronous; - status = "disabled"; - }; - - sai2: audio-controller@f110000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; - reg = <0x0 0xf110000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 6>, - <&edma0 1 5>; - fsl,sai-asynchronous; - status = "disabled"; - }; - - sai3: audio-controller@f120000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; - reg = <0x0 0xf120000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 8>, - <&edma0 1 7>; - fsl,sai-asynchronous; - status = "disabled"; - }; - - sai4: audio-controller@f130000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; - reg = <0x0 0xf130000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 10>, - <&edma0 1 9>; - fsl,sai-asynchronous; - status = "disabled"; - }; - - sai5: audio-controller@f140000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; - reg = <0x0 0xf140000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 12>, - <&edma0 1 11>; - fsl,sai-asynchronous; - status = "disabled"; - }; - - sai6: audio-controller@f150000 { - #sound-dai-cells = <0>; - compatible = "fsl,vf610-sai"; - reg = <0x0 0xf150000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 14>, - <&edma0 1 13>; - fsl,sai-asynchronous; - status = "disabled"; - }; - - tmu: tmu@1f80000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x0 0x1f80000 0x0 0x10000>; - interrupts = <0 23 0x4>; - fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; - fsl,tmu-calibration = <0x00000000 0x00000024 - 0x00000001 0x0000002b - 0x00000002 0x00000031 - 0x00000003 0x00000038 - 0x00000004 0x0000003f - 0x00000005 0x00000045 - 0x00000006 0x0000004c - 0x00000007 0x00000053 - 0x00000008 0x00000059 - 0x00000009 0x00000060 - 0x0000000a 0x00000066 - 0x0000000b 0x0000006d - - 0x00010000 0x0000001c - 0x00010001 0x00000024 - 0x00010002 0x0000002c - 0x00010003 0x00000035 - 0x00010004 0x0000003d - 0x00010005 0x00000045 - 0x00010006 0x0000004d - 0x00010007 0x00000055 - 0x00010008 0x0000005e - 0x00010009 0x00000066 - 0x0001000a 0x0000006e - - 0x00020000 0x00000018 - 0x00020001 0x00000022 - 0x00020002 0x0000002d - 0x00020003 0x00000038 - 0x00020004 0x00000043 - 0x00020005 0x0000004d - 0x00020006 0x00000058 - 0x00020007 0x00000063 - 0x00020008 0x0000006e - - 0x00030000 0x00000010 - 0x00030001 0x0000001c - 0x00030002 0x00000029 - 0x00030003 0x00000036 - 0x00030004 0x00000042 - 0x00030005 0x0000004f - 0x00030006 0x0000005b - 0x00030007 0x00000068>; - little-endian; - #thermal-sensor-cells = <1>; - }; - - pcie@1f0000000 { /* Integrated Endpoint Root Complex */ - compatible = "pci-host-ecam-generic"; - reg = <0x01 0xf0000000 0x0 0x100000>; - #address-cells = <3>; - #size-cells = <2>; - msi-parent = <&its>; - device_type = "pci"; - bus-range = <0x0 0x0>; - dma-coherent; - msi-map = <0 &its 0x17 0xe>; - iommu-map = <0 &smmu 0x17 0xe>; - /* PF0-6 BAR0 - non-prefetchable memory */ - ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 - /* PF0-6 BAR2 - prefetchable memory */ - 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 - /* PF0: VF0-1 BAR0 - non-prefetchable memory */ - 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 - /* PF0: VF0-1 BAR2 - prefetchable memory */ - 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 - /* PF1: VF0-1 BAR0 - non-prefetchable memory */ - 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 - /* PF1: VF0-1 BAR2 - prefetchable memory */ - 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000 - /* BAR4 (PF5) - non-prefetchable memory */ - 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>; - - enetc_port0: ethernet@0,0 { - compatible = "fsl,enetc"; - reg = <0x000000 0 0 0 0>; - status = "disabled"; - }; - - enetc_port1: ethernet@0,1 { - compatible = "fsl,enetc"; - reg = <0x000100 0 0 0 0>; - status = "disabled"; - }; - - enetc_port2: ethernet@0,2 { - compatible = "fsl,enetc"; - reg = <0x000200 0 0 0 0>; - phy-mode = "internal"; - status = "disabled"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - enetc_mdio_pf3: mdio@0,3 { - compatible = "fsl,enetc-mdio"; - reg = <0x000300 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - ethernet@0,4 { - compatible = "fsl,enetc-ptp"; - reg = <0x000400 0 0 0 0>; - clocks = <&clockgen 2 3>; - little-endian; - fsl,extts-fifo; - }; - - mscc_felix: ethernet-switch@0,5 { - reg = <0x000500 0 0 0 0>; - /* IEP INT_B */ - interrupts = ; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* External ports */ - mscc_felix_port0: port@0 { - reg = <0>; - status = "disabled"; - }; - - mscc_felix_port1: port@1 { - reg = <1>; - status = "disabled"; - }; - - mscc_felix_port2: port@2 { - reg = <2>; - status = "disabled"; - }; - - mscc_felix_port3: port@3 { - reg = <3>; - status = "disabled"; - }; - - /* Internal ports */ - mscc_felix_port4: port@4 { - reg = <4>; - phy-mode = "internal"; - status = "disabled"; - - fixed-link { - speed = <2500>; - full-duplex; - }; - }; - - mscc_felix_port5: port@5 { - reg = <5>; - phy-mode = "internal"; - status = "disabled"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - }; - - enetc_port3: ethernet@0,6 { - compatible = "fsl,enetc"; - reg = <0x000600 0 0 0 0>; - phy-mode = "internal"; - status = "disabled"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; - - rcpm: power-controller@1e34040 { - compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; - reg = <0x0 0x1e34040 0x0 0x1c>; - #fsl,rcpm-wakeup-cells = <7>; - little-endian; - }; - - ftm_alarm0: timer@2800000 { - compatible = "fsl,ls1028a-ftm-alarm"; - reg = <0x0 0x2800000 0x0 0x10000>; - fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; - interrupts = ; - }; - }; - - malidp0: display@f080000 { - compatible = "arm,mali-dp500"; - reg = <0x0 0xf080000 0x0 0x10000>; - interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, - <0 223 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "DE", "SE"; - clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>, - <&clockgen 2 2>; - clock-names = "pxlclk", "mclk", "aclk", "pclk"; - arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; - arm,malidp-arqos-value = <0xd000d000>; - - port { - dp0_out: endpoint { - - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi deleted file mode 100644 index d237162a8..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi +++ /dev/null @@ -1,46 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ FMan v3 device tree nodes for ls1043 - * - * Copyright 2015-2016 Freescale Semiconductor Inc. - */ - -&soc { - -/* include used FMan blocks */ -#include "qoriq-fman3-0.dtsi" -#include "qoriq-fman3-0-1g-0.dtsi" -#include "qoriq-fman3-0-1g-1.dtsi" -#include "qoriq-fman3-0-1g-2.dtsi" -#include "qoriq-fman3-0-1g-3.dtsi" -#include "qoriq-fman3-0-1g-4.dtsi" -#include "qoriq-fman3-0-1g-5.dtsi" -#include "qoriq-fman3-0-10g-0.dtsi" - -}; - -&fman0 { - fsl,erratum-a050385; - - /* these aliases provide the FMan ports mapping */ - enet0: ethernet@e0000 { - }; - - enet1: ethernet@e2000 { - }; - - enet2: ethernet@e4000 { - }; - - enet3: ethernet@e6000 { - }; - - enet4: ethernet@e8000 { - }; - - enet5: ethernet@ea000 { - }; - - enet6: ethernet@f0000 { - }; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts deleted file mode 100644 index fea167d22..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts +++ /dev/null @@ -1,155 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Freescale Layerscape-1043A family SoC. - * - * Copyright 2014-2015 Freescale Semiconductor, Inc. - * Copyright 2018 NXP - * - * Mingkai Hu - */ - -/dts-v1/; -#include "fsl-ls1043a.dtsi" - -/ { - model = "LS1043A QDS Board"; - compatible = "fsl,ls1043a-qds", "fsl,ls1043a"; - - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - serial0 = &duart0; - serial1 = &duart1; - serial2 = &duart2; - serial3 = &duart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&ifc { - #address-cells = <2>; - #size-cells = <1>; - /* NOR, NAND Flashes and FPGA on board */ - ranges = <0x0 0x0 0x0 0x60000000 0x08000000 - 0x1 0x0 0x0 0x7e800000 0x00010000 - 0x2 0x0 0x0 0x7fb00000 0x00000100>; - status = "okay"; - - nor@0,0 { - compatible = "cfi-flash"; - reg = <0x0 0x0 0x8000000>; - big-endian; - bank-width = <2>; - device-width = <1>; - }; - - nand@1,0 { - compatible = "fsl,ifc-nand"; - reg = <0x1 0x0 0x10000>; - }; - - fpga: board-control@2,0 { - compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis"; - reg = <0x2 0x0 0x0000100>; - }; -}; - -&i2c0 { - status = "okay"; - - pca9547@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - - rtc@68 { - compatible = "dallas,ds3232"; - reg = <0x68>; - /* IRQ10_B */ - interrupts = <0 150 0x4>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - - ina220@41 { - compatible = "ti,ina220"; - reg = <0x41>; - shunt-resistor = <1000>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - eeprom@56 { - compatible = "atmel,24c512"; - reg = <0x56>; - }; - - eeprom@57 { - compatible = "atmel,24c512"; - reg = <0x57>; - }; - - temp-sensor@4c { - compatible = "adi,adt7461a"; - reg = <0x4c>; - }; - }; - }; -}; - -&lpuart0 { - status = "okay"; -}; - -&qspi { - status = "okay"; - - qflash0: flash@0 { - compatible = "spansion,m25p80"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <20000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - reg = <0>; - }; -}; - -&usb0 { - status = "okay"; -}; - -#include "fsl-ls1043-post.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts deleted file mode 100644 index 3516af472..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts +++ /dev/null @@ -1,219 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Freescale Layerscape-1043A family SoC. - * - * Copyright 2014-2015 Freescale Semiconductor, Inc. - * Copyright 2018 NXP - * - * Mingkai Hu - */ - -/dts-v1/; -#include "fsl-ls1043a.dtsi" - -/ { - model = "LS1043A RDB Board"; - compatible = "fsl,ls1043a-rdb", "fsl,ls1043a"; - - aliases { - serial0 = &duart0; - serial1 = &duart1; - serial2 = &duart2; - serial3 = &duart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&i2c0 { - status = "okay"; - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - adt7461a@4c { - compatible = "adi,adt7461"; - reg = <0x4c>; - }; - eeprom@52 { - compatible = "atmel,24c512"; - reg = <0x52>; - }; - eeprom@53 { - compatible = "atmel,24c512"; - reg = <0x53>; - }; - rtc@68 { - compatible = "pericom,pt7c4338"; - reg = <0x68>; - }; -}; - -&ifc { - status = "okay"; - #address-cells = <2>; - #size-cells = <1>; - /* NOR, NAND Flashes and FPGA on board */ - ranges = <0x0 0x0 0x0 0x60000000 0x08000000 - 0x1 0x0 0x0 0x7e800000 0x00010000 - 0x2 0x0 0x0 0x7fb00000 0x00000100>; - - nor@0,0 { - compatible = "cfi-flash"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x0 0x8000000>; - big-endian; - bank-width = <2>; - device-width = <1>; - }; - - nand@1,0 { - compatible = "fsl,ifc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x1 0x0 0x10000>; - }; - - cpld: board-control@2,0 { - compatible = "fsl,ls1043ardb-cpld"; - reg = <0x2 0x0 0x0000100>; - }; -}; - -&dspi0 { - bus-num = <0>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */ - reg = <0>; - spi-max-frequency = <1000000>; /* input clock */ - }; - - slic@2 { - compatible = "maxim,ds26522"; - reg = <2>; - spi-max-frequency = <2000000>; - fsl,spi-cs-sck-delay = <100>; - fsl,spi-sck-cs-delay = <50>; - }; - - slic@3 { - compatible = "maxim,ds26522"; - reg = <3>; - spi-max-frequency = <2000000>; - fsl,spi-cs-sck-delay = <100>; - fsl,spi-sck-cs-delay = <50>; - }; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -#include "fsl-ls1043-post.dtsi" - -&fman0 { - ethernet@e0000 { - phy-handle = <&qsgmii_phy1>; - phy-connection-type = "qsgmii"; - }; - - ethernet@e2000 { - phy-handle = <&qsgmii_phy2>; - phy-connection-type = "qsgmii"; - }; - - ethernet@e4000 { - phy-handle = <&rgmii_phy1>; - phy-connection-type = "rgmii-id"; - }; - - ethernet@e6000 { - phy-handle = <&rgmii_phy2>; - phy-connection-type = "rgmii-id"; - }; - - ethernet@e8000 { - phy-handle = <&qsgmii_phy3>; - phy-connection-type = "qsgmii"; - }; - - ethernet@ea000 { - phy-handle = <&qsgmii_phy4>; - phy-connection-type = "qsgmii"; - }; - - ethernet@f0000 { /* 10GEC1 */ - phy-handle = <&aqr105_phy>; - phy-connection-type = "xgmii"; - }; - - mdio@fc000 { - rgmii_phy1: ethernet-phy@1 { - reg = <0x1>; - }; - - rgmii_phy2: ethernet-phy@2 { - reg = <0x2>; - }; - - qsgmii_phy1: ethernet-phy@4 { - reg = <0x4>; - }; - - qsgmii_phy2: ethernet-phy@5 { - reg = <0x5>; - }; - - qsgmii_phy3: ethernet-phy@6 { - reg = <0x6>; - }; - - qsgmii_phy4: ethernet-phy@7 { - reg = <0x7>; - }; - }; - - mdio@fd000 { - aqr105_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c45"; - interrupts = <0 132 4>; - reg = <0x1>; - }; - }; -}; - -&uqe { - ucc_hdlc: ucc@2000 { - compatible = "fsl,ucc-hdlc"; - rx-clock-name = "clk8"; - tx-clock-name = "clk9"; - fsl,rx-sync-clock = "rsync_pin"; - fsl,tx-sync-clock = "tsync_pin"; - fsl,tx-timeslot-mask = <0xfffffffe>; - fsl,rx-timeslot-mask = <0xfffffffe>; - fsl,tdm-framer-type = "e1"; - fsl,tdm-id = <0>; - fsl,siram-entry-id = <0>; - fsl,tdm-interface; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi deleted file mode 100644 index b1b9544d8..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ /dev/null @@ -1,942 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for NXP Layerscape-1043A family SoC. - * - * Copyright 2014-2015 Freescale Semiconductor, Inc. - * Copyright 2018, 2020 NXP - * - * Mingkai Hu - */ - -#include -#include - -/ { - compatible = "fsl,ls1043a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - crypto = &crypto; - fman0 = &fman0; - ethernet0 = &enet0; - ethernet1 = &enet1; - ethernet2 = &enet2; - ethernet3 = &enet3; - ethernet4 = &enet4; - ethernet5 = &enet5; - ethernet6 = &enet6; - rtc1 = &ftm_alarm0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - /* - * We expect the enable-method for cpu's to be "psci", but this - * is dependent on the SoC FW, which will fill this in. - * - * Currently supported enable-method is psci v0.2 - */ - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x2>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x3>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - l2: l2-cache { - compatible = "cache"; - }; - }; - - idle-states { - /* - * PSCI node is not added default, U-boot will add missing - * parts if it determines to use PSCI. - */ - entry-method = "psci"; - - CPU_PH20: cpu-ph20 { - compatible = "arm,idle-state"; - idle-state-name = "PH20"; - arm,psci-suspend-param = <0x0>; - entry-latency-us = <1000>; - exit-latency-us = <1000>; - min-residency-us = <3000>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0 0x80000000>; - /* DRAM space 1, size: 2GiB DRAM */ - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - bman_fbpr: bman-fbpr { - compatible = "shared-dma-pool"; - size = <0 0x1000000>; - alignment = <0 0x1000000>; - no-map; - }; - - qman_fqd: qman-fqd { - compatible = "shared-dma-pool"; - size = <0 0x400000>; - alignment = <0 0x400000>; - no-map; - }; - - qman_pfdr: qman-pfdr { - compatible = "shared-dma-pool"; - size = <0 0x2000000>; - alignment = <0 0x2000000>; - no-map; - }; - }; - - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "sysclk"; - }; - - reboot { - compatible ="syscon-reboot"; - regmap = <&dcfg>; - offset = <0xb0>; - mask = <0x02>; - }; - - thermal-zones { - ddr-controller { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 0>; - - trips { - ddr-ctrler-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - ddr-ctrler-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - serdes { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 1>; - - trips { - serdes-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - serdes-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - fman { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 2>; - - trips { - fman-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - fman-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - core-cluster { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 3>; - - trips { - core_cluster_alert: core-cluster-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - core_cluster_crit: core-cluster-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&core_cluster_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - sec { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 4>; - - trips { - sec-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - sec-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf08>, /* Physical Secure PPI */ - <1 14 0xf08>, /* Physical Non-Secure PPI */ - <1 11 0xf08>, /* Virtual PPI */ - <1 10 0xf08>; /* Hypervisor PPI */ - fsl,erratum-a008585; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <0 106 0x4>, - <0 107 0x4>, - <0 95 0x4>, - <0 97 0x4>; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - gic: interrupt-controller@1400000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x1401000 0 0x1000>, /* GICD */ - <0x0 0x1402000 0 0x2000>, /* GICC */ - <0x0 0x1404000 0 0x2000>, /* GICH */ - <0x0 0x1406000 0 0x2000>; /* GICV */ - interrupts = <1 9 0xf08>; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clockgen: clocking@1ee1000 { - compatible = "fsl,ls1043a-clockgen"; - reg = <0x0 0x1ee1000 0x0 0x1000>; - #clock-cells = <2>; - clocks = <&sysclk>; - }; - - scfg: scfg@1570000 { - compatible = "fsl,ls1043a-scfg", "syscon"; - reg = <0x0 0x1570000 0x0 0x10000>; - big-endian; - }; - - crypto: crypto@1700000 { - compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", - "fsl,sec-v4.0"; - fsl,sec-era = <3>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x1700000 0x100000>; - reg = <0x00 0x1700000 0x0 0x100000>; - interrupts = <0 75 0x4>; - dma-coherent; - - sec_jr0: jr@10000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; - interrupts = <0 71 0x4>; - }; - - sec_jr1: jr@20000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; - interrupts = <0 72 0x4>; - }; - - sec_jr2: jr@30000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; - interrupts = <0 73 0x4>; - }; - - sec_jr3: jr@40000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; - interrupts = <0 74 0x4>; - }; - }; - - dcfg: dcfg@1ee0000 { - compatible = "fsl,ls1043a-dcfg", "syscon"; - reg = <0x0 0x1ee0000 0x0 0x10000>; - big-endian; - }; - - ifc: ifc@1530000 { - compatible = "fsl,ifc", "simple-bus"; - reg = <0x0 0x1530000 0x0 0x10000>; - interrupts = <0 43 0x4>; - }; - - qspi: spi@1550000 { - compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x1550000 0x0 0x10000>, - <0x0 0x40000000 0x0 0x4000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = <0 99 0x4>; - clock-names = "qspi_en", "qspi"; - clocks = <&clockgen 4 0>, <&clockgen 4 0>; - status = "disabled"; - }; - - esdhc: esdhc@1560000 { - compatible = "fsl,ls1043a-esdhc", "fsl,esdhc"; - reg = <0x0 0x1560000 0x0 0x10000>; - interrupts = <0 62 0x4>; - clock-frequency = <0>; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - big-endian; - bus-width = <4>; - }; - - ddr: memory-controller@1080000 { - compatible = "fsl,qoriq-memory-controller"; - reg = <0x0 0x1080000 0x0 0x1000>; - interrupts = <0 144 0x4>; - big-endian; - }; - - tmu: tmu@1f00000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x0 0x1f00000 0x0 0x10000>; - interrupts = <0 33 0x4>; - fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; - fsl,tmu-calibration = <0x00000000 0x00000026 - 0x00000001 0x0000002d - 0x00000002 0x00000032 - 0x00000003 0x00000039 - 0x00000004 0x0000003f - 0x00000005 0x00000046 - 0x00000006 0x0000004d - 0x00000007 0x00000054 - 0x00000008 0x0000005a - 0x00000009 0x00000061 - 0x0000000a 0x0000006a - 0x0000000b 0x00000071 - - 0x00010000 0x00000025 - 0x00010001 0x0000002c - 0x00010002 0x00000035 - 0x00010003 0x0000003d - 0x00010004 0x00000045 - 0x00010005 0x0000004e - 0x00010006 0x00000057 - 0x00010007 0x00000061 - 0x00010008 0x0000006b - 0x00010009 0x00000076 - - 0x00020000 0x00000029 - 0x00020001 0x00000033 - 0x00020002 0x0000003d - 0x00020003 0x00000049 - 0x00020004 0x00000056 - 0x00020005 0x00000061 - 0x00020006 0x0000006d - - 0x00030000 0x00000021 - 0x00030001 0x0000002a - 0x00030002 0x0000003c - 0x00030003 0x0000004e>; - #thermal-sensor-cells = <1>; - }; - - qman: qman@1880000 { - compatible = "fsl,qman"; - reg = <0x0 0x1880000 0x0 0x10000>; - interrupts = ; - memory-region = <&qman_fqd &qman_pfdr>; - }; - - bman: bman@1890000 { - compatible = "fsl,bman"; - reg = <0x0 0x1890000 0x0 0x10000>; - interrupts = ; - memory-region = <&bman_fbpr>; - }; - - bportals: bman-portals@508000000 { - ranges = <0x0 0x5 0x08000000 0x8000000>; - }; - - qportals: qman-portals@500000000 { - ranges = <0x0 0x5 0x00000000 0x8000000>; - }; - - dspi0: spi@2100000 { - compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = <0 64 0x4>; - clock-names = "dspi"; - clocks = <&clockgen 4 0>; - spi-num-chipselects = <5>; - big-endian; - status = "disabled"; - }; - - dspi1: spi@2110000 { - compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2110000 0x0 0x10000>; - interrupts = <0 65 0x4>; - clock-names = "dspi"; - clocks = <&clockgen 4 0>; - spi-num-chipselects = <5>; - big-endian; - status = "disabled"; - }; - - i2c0: i2c@2180000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2180000 0x0 0x10000>; - interrupts = <0 56 0x4>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - dmas = <&edma0 1 39>, - <&edma0 1 38>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - i2c1: i2c@2190000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2190000 0x0 0x10000>; - interrupts = <0 57 0x4>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - - i2c2: i2c@21a0000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x21a0000 0x0 0x10000>; - interrupts = <0 58 0x4>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - - i2c3: i2c@21b0000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x21b0000 0x0 0x10000>; - interrupts = <0 59 0x4>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - - duart0: serial@21c0500 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x00 0x21c0500 0x0 0x100>; - interrupts = <0 54 0x4>; - clocks = <&clockgen 4 0>; - }; - - duart1: serial@21c0600 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x00 0x21c0600 0x0 0x100>; - interrupts = <0 54 0x4>; - clocks = <&clockgen 4 0>; - }; - - duart2: serial@21d0500 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21d0500 0x0 0x100>; - interrupts = <0 55 0x4>; - clocks = <&clockgen 4 0>; - }; - - duart3: serial@21d0600 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21d0600 0x0 0x100>; - interrupts = <0 55 0x4>; - clocks = <&clockgen 4 0>; - }; - - gpio1: gpio@2300000 { - compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = <0 66 0x4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2310000 { - compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = <0 67 0x4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@2320000 { - compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = <0 68 0x4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@2330000 { - compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2330000 0x0 0x10000>; - interrupts = <0 134 0x4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - uqe: uqe@2400000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,qe", "simple-bus"; - ranges = <0x0 0x0 0x2400000 0x40000>; - reg = <0x0 0x2400000 0x0 0x480>; - brg-frequency = <100000000>; - bus-frequency = <200000000>; - fsl,qe-num-riscs = <1>; - fsl,qe-num-snums = <28>; - - qeic: qeic@80 { - compatible = "fsl,qe-ic"; - reg = <0x80 0x80>; - #address-cells = <0>; - interrupt-controller; - #interrupt-cells = <1>; - interrupts = , - ; - }; - - si1: si@700 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,ls1043-qe-si", - "fsl,t1040-qe-si"; - reg = <0x700 0x80>; - }; - - siram1: siram@1000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,ls1043-qe-siram", - "fsl,t1040-qe-siram"; - reg = <0x1000 0x800>; - }; - - ucc@2000 { - cell-index = <1>; - reg = <0x2000 0x200>; - interrupts = <32>; - interrupt-parent = <&qeic>; - }; - - ucc@2200 { - cell-index = <3>; - reg = <0x2200 0x200>; - interrupts = <34>; - interrupt-parent = <&qeic>; - }; - - muram@10000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,qe-muram", "fsl,cpm-muram"; - ranges = <0x0 0x10000 0x6000>; - - data-only@0 { - compatible = "fsl,qe-muram-data", - "fsl,cpm-muram-data"; - reg = <0x0 0x6000>; - }; - }; - }; - - lpuart0: serial@2950000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2950000 0x0 0x1000>; - interrupts = <0 48 0x4>; - clocks = <&clockgen 0 0>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart1: serial@2960000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2960000 0x0 0x1000>; - interrupts = <0 49 0x4>; - clocks = <&clockgen 4 0>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart2: serial@2970000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2970000 0x0 0x1000>; - interrupts = <0 50 0x4>; - clocks = <&clockgen 4 0>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart3: serial@2980000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2980000 0x0 0x1000>; - interrupts = <0 51 0x4>; - clocks = <&clockgen 4 0>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart4: serial@2990000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2990000 0x0 0x1000>; - interrupts = <0 52 0x4>; - clocks = <&clockgen 4 0>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart5: serial@29a0000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x29a0000 0x0 0x1000>; - interrupts = <0 53 0x4>; - clocks = <&clockgen 4 0>; - clock-names = "ipg"; - status = "disabled"; - }; - - wdog0: wdog@2ad0000 { - compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; - reg = <0x0 0x2ad0000 0x0 0x10000>; - interrupts = <0 83 0x4>; - clocks = <&clockgen 4 0>; - clock-names = "wdog"; - big-endian; - }; - - edma0: edma@2c00000 { - #dma-cells = <2>; - compatible = "fsl,vf610-edma"; - reg = <0x0 0x2c00000 0x0 0x10000>, - <0x0 0x2c10000 0x0 0x10000>, - <0x0 0x2c20000 0x0 0x10000>; - interrupts = <0 103 0x4>, - <0 103 0x4>; - interrupt-names = "edma-tx", "edma-err"; - dma-channels = <32>; - big-endian; - clock-names = "dmamux0", "dmamux1"; - clocks = <&clockgen 4 0>, - <&clockgen 4 0>; - }; - - usb0: usb3@2f00000 { - compatible = "snps,dwc3"; - reg = <0x0 0x2f00000 0x0 0x10000>; - interrupts = <0 60 0x4>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - status = "disabled"; - }; - - usb1: usb3@3000000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3000000 0x0 0x10000>; - interrupts = <0 61 0x4>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - status = "disabled"; - }; - - usb2: usb3@3100000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <0 63 0x4>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - status = "disabled"; - }; - - sata: sata@3200000 { - compatible = "fsl,ls1043a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>, - <0x0 0x20140520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = <0 69 0x4>; - clocks = <&clockgen 4 0>; - dma-coherent; - }; - - msi1: msi-controller1@1571000 { - compatible = "fsl,ls1043a-msi"; - reg = <0x0 0x1571000 0x0 0x8>; - msi-controller; - interrupts = <0 116 0x4>; - }; - - msi2: msi-controller2@1572000 { - compatible = "fsl,ls1043a-msi"; - reg = <0x0 0x1572000 0x0 0x8>; - msi-controller; - interrupts = <0 126 0x4>; - }; - - msi3: msi-controller3@1573000 { - compatible = "fsl,ls1043a-msi"; - reg = <0x0 0x1573000 0x0 0x8>; - msi-controller; - interrupts = <0 160 0x4>; - }; - - pcie1: pcie@3400000 { - compatible = "fsl,ls1043a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = <0 118 0x4>, /* controller interrupt */ - <0 117 0x4>; /* PME interrupt */ - interrupt-names = "intr", "pme"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <6>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi1>, <&msi2>, <&msi3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, - <0000 0 0 2 &gic 0 111 0x4>, - <0000 0 0 3 &gic 0 112 0x4>, - <0000 0 0 4 &gic 0 113 0x4>; - status = "disabled"; - }; - - pcie2: pcie@3500000 { - compatible = "fsl,ls1043a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = <0 128 0x4>, - <0 127 0x4>; - interrupt-names = "intr", "pme"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <6>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi1>, <&msi2>, <&msi3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, - <0000 0 0 2 &gic 0 121 0x4>, - <0000 0 0 3 &gic 0 122 0x4>, - <0000 0 0 4 &gic 0 123 0x4>; - status = "disabled"; - }; - - pcie3: pcie@3600000 { - compatible = "fsl,ls1043a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = <0 162 0x4>, - <0 161 0x4>; - interrupt-names = "intr", "pme"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <6>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi1>, <&msi2>, <&msi3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, - <0000 0 0 2 &gic 0 155 0x4>, - <0000 0 0 3 &gic 0 156 0x4>, - <0000 0 0 4 &gic 0 157 0x4>; - status = "disabled"; - }; - - qdma: dma-controller@8380000 { - compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma"; - reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ - <0x0 0x8390000 0x0 0x10000>, /* Status regs */ - <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ - interrupts = , - , - , - , - ; - interrupt-names = "qdma-error", "qdma-queue0", - "qdma-queue1", "qdma-queue2", "qdma-queue3"; - dma-channels = <8>; - block-number = <1>; - block-offset = <0x10000>; - fsl,dma-queues = <2>; - status-sizes = <64>; - queue-sizes = <64 64>; - big-endian; - }; - - rcpm: power-controller@1ee2140 { - compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+"; - reg = <0x0 0x1ee2140 0x0 0x4>; - #fsl,rcpm-wakeup-cells = <1>; - }; - - ftm_alarm0: timer@29d0000 { - compatible = "fsl,ls1043a-ftm-alarm"; - reg = <0x0 0x29d0000 0x0 0x10000>; - fsl,rcpm-wakeup = <&rcpm 0x20000>; - interrupts = ; - big-endian; - }; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; - -}; - -#include "qoriq-qman-portals.dtsi" -#include "qoriq-bman-portals.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi deleted file mode 100644 index d6caaea57..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ FMan v3 device tree nodes for ls1046 - * - * Copyright 2015-2016 Freescale Semiconductor Inc. - * - */ - -&soc { - -/* include used FMan blocks */ -#include "qoriq-fman3-0.dtsi" -#include "qoriq-fman3-0-1g-0.dtsi" -#include "qoriq-fman3-0-1g-1.dtsi" -#include "qoriq-fman3-0-1g-2.dtsi" -#include "qoriq-fman3-0-1g-3.dtsi" -#include "qoriq-fman3-0-1g-4.dtsi" -#include "qoriq-fman3-0-1g-5.dtsi" -#include "qoriq-fman3-0-10g-0.dtsi" -#include "qoriq-fman3-0-10g-1.dtsi" -}; - -&fman0 { - /* these aliases provide the FMan ports mapping */ - enet0: ethernet@e0000 { - }; - - enet1: ethernet@e2000 { - }; - - enet2: ethernet@e4000 { - }; - - enet3: ethernet@e6000 { - }; - - enet4: ethernet@e8000 { - }; - - enet5: ethernet@ea000 { - }; - - enet6: ethernet@f0000 { - }; - - enet7: ethernet@f2000 { - }; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts deleted file mode 100644 index 6d22efbd6..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts +++ /dev/null @@ -1,163 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Freescale Layerscape-1046A family SoC. - * - * Copyright 2019 NXP. - * - */ - -/dts-v1/; - -#include "fsl-ls1046a.dtsi" - -/ { - model = "LS1046A FRWY Board"; - compatible = "fsl,ls1046a-frwy", "fsl,ls1046a"; - - aliases { - serial0 = &duart0; - serial1 = &duart1; - serial2 = &duart2; - serial3 = &duart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - sb_3v3: regulator-sb3v3 { - compatible = "regulator-fixed"; - regulator-name = "LT8642SEV-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&duart2 { - status = "okay"; -}; - -&duart3 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - i2c-mux@77 { - compatible = "nxp,pca9546"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - power-monitor@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - - temperature-sensor@4c { - compatible = "nxp,sa56004"; - reg = <0x4c>; - vcc-supply = <&sb_3v3>; - }; - - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - }; - - eeprom@52 { - compatible = "onnn,cat24c04", "atmel,24c04"; - reg = <0x52>; - }; - }; - }; -}; - -&ifc { - #address-cells = <2>; - #size-cells = <1>; - /* NAND Flash */ - ranges = <0x0 0x0 0x0 0x7e800000 0x00010000>; - status = "okay"; - - nand@0,0 { - compatible = "fsl,ifc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x0 0x10000>; - }; - -}; - -&qspi { - status = "okay"; - - mt25qu512a0: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - reg = <0>; - }; -}; - -#include "fsl-ls1046-post.dtsi" - -&fman0 { - ethernet@e0000 { - phy-handle = <&qsgmii_phy4>; - phy-connection-type = "qsgmii"; - }; - - ethernet@e8000 { - phy-handle = <&qsgmii_phy2>; - phy-connection-type = "qsgmii"; - }; - - ethernet@ea000 { - phy-handle = <&qsgmii_phy1>; - phy-connection-type = "qsgmii"; - }; - - ethernet@f2000 { - phy-handle = <&qsgmii_phy3>; - phy-connection-type = "qsgmii"; - }; - - mdio@fd000 { - qsgmii_phy1: ethernet-phy@1c { - reg = <0x1c>; - }; - - qsgmii_phy2: ethernet-phy@1d { - reg = <0x1d>; - }; - - qsgmii_phy3: ethernet-phy@1e { - reg = <0x1e>; - }; - - qsgmii_phy4: ethernet-phy@1f { - reg = <0x1f>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts deleted file mode 100644 index eec62c63d..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts +++ /dev/null @@ -1,179 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Freescale Layerscape-1046A family SoC. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2018 NXP - * - * Shaohui Xie - */ - -/dts-v1/; - -#include "fsl-ls1046a.dtsi" - -/ { - model = "LS1046A QDS Board"; - compatible = "fsl,ls1046a-qds", "fsl,ls1046a"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - serial0 = &duart0; - serial1 = &duart1; - serial2 = &duart2; - serial3 = &duart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&dspi { - bus-num = <0>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a11", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - }; - - flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "sst25wf040b", "jedec,spi-nor"; - spi-cpol; - spi-cpha; - reg = <1>; - spi-max-frequency = <10000000>; - }; - - flash@2 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "en25s64", "jedec,spi-nor"; - spi-cpol; - spi-cpha; - reg = <2>; - spi-max-frequency = <10000000>; - }; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - pca9547@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - - ina220@41 { - compatible = "ti,ina220"; - reg = <0x41>; - shunt-resistor = <1000>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - /* IRQ10_B */ - interrupts = <0 150 0x4>; - }; - - eeprom@56 { - compatible = "atmel,24c512"; - reg = <0x56>; - }; - - eeprom@57 { - compatible = "atmel,24c512"; - reg = <0x57>; - }; - - temp-sensor@4c { - compatible = "adi,adt7461a"; - reg = <0x4c>; - }; - }; - }; -}; - -&ifc { - #address-cells = <2>; - #size-cells = <1>; - /* NOR, NAND Flashes and FPGA on board */ - ranges = <0x0 0x0 0x0 0x60000000 0x08000000 - 0x1 0x0 0x0 0x7e800000 0x00010000 - 0x2 0x0 0x0 0x7fb00000 0x00000100>; - status = "okay"; - - nor@0,0 { - compatible = "cfi-flash"; - reg = <0x0 0x0 0x8000000>; - big-endian; - bank-width = <2>; - device-width = <1>; - }; - - nand@1,0 { - compatible = "fsl,ifc-nand"; - reg = <0x1 0x0 0x10000>; - }; - - fpga: board-control@2,0 { - compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis"; - reg = <0x2 0x0 0x0000100>; - }; -}; - -&lpuart0 { - status = "okay"; -}; - -&qspi { - status = "okay"; - - qflash0: flash@0 { - compatible = "spansion,m25p80"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <20000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - reg = <0>; - }; -}; - -#include "fsl-ls1046-post.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts deleted file mode 100644 index 07139e356..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts +++ /dev/null @@ -1,182 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Freescale Layerscape-1046A family SoC. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * - * Mingkai Hu - */ - -/dts-v1/; - -#include "fsl-ls1046a.dtsi" - -/ { - model = "LS1046A RDB Board"; - compatible = "fsl,ls1046a-rdb", "fsl,ls1046a"; - - aliases { - serial0 = &duart0; - serial1 = &duart1; - serial2 = &duart2; - serial3 = &duart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&esdhc { - mmc-hs200-1_8v; - sd-uhs-sdr104; - sd-uhs-sdr50; - sd-uhs-sdr25; - sd-uhs-sdr12; -}; - -&i2c0 { - status = "okay"; - - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - - temp-sensor@4c { - compatible = "adi,adt7461"; - reg = <0x4c>; - }; - - eeprom@52 { - compatible = "onnn,cat24c05", "atmel,24c04"; - reg = <0x52>; - }; -}; - -&i2c3 { - status = "okay"; - - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - }; -}; - -&ifc { - #address-cells = <2>; - #size-cells = <1>; - /* NAND Flashe and CPLD on board */ - ranges = <0x0 0x0 0x0 0x7e800000 0x00010000 - 0x2 0x0 0x0 0x7fb00000 0x00000100>; - status = "okay"; - - nand@0,0 { - compatible = "fsl,ifc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x0 0x10000>; - }; - - cpld: board-control@2,0 { - compatible = "fsl,ls1046ardb-cpld"; - reg = <0x2 0x0 0x0000100>; - }; -}; - -&qspi { - status = "okay"; - - s25fs512s0: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - reg = <0>; - }; - - s25fs512s1: flash@1 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - reg = <1>; - }; -}; - -&usb1 { - dr_mode = "otg"; -}; - -#include "fsl-ls1046-post.dtsi" - -&fman0 { - ethernet@e4000 { - phy-handle = <&rgmii_phy1>; - phy-connection-type = "rgmii-id"; - }; - - ethernet@e6000 { - phy-handle = <&rgmii_phy2>; - phy-connection-type = "rgmii-id"; - }; - - ethernet@e8000 { - phy-handle = <&sgmii_phy1>; - phy-connection-type = "sgmii"; - }; - - ethernet@ea000 { - phy-handle = <&sgmii_phy2>; - phy-connection-type = "sgmii"; - }; - - ethernet@f0000 { /* 10GEC1 */ - phy-handle = <&aqr106_phy>; - phy-connection-type = "xgmii"; - }; - - ethernet@f2000 { /* 10GEC2 */ - fixed-link = <0 1 1000 0 0>; - phy-connection-type = "xgmii"; - }; - - mdio@fc000 { - rgmii_phy1: ethernet-phy@1 { - reg = <0x1>; - }; - - rgmii_phy2: ethernet-phy@2 { - reg = <0x2>; - }; - - sgmii_phy1: ethernet-phy@3 { - reg = <0x3>; - }; - - sgmii_phy2: ethernet-phy@4 { - reg = <0x4>; - }; - }; - - mdio@fd000 { - aqr106_phy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c45"; - interrupts = <0 131 4>; - reg = <0x0>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi deleted file mode 100644 index acf2ae2e1..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ /dev/null @@ -1,902 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for NXP Layerscape-1046A family SoC. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2018, 2020 NXP - * - * Mingkai Hu - */ - -#include -#include - -/ { - compatible = "fsl,ls1046a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - crypto = &crypto; - fman0 = &fman0; - ethernet0 = &enet0; - ethernet1 = &enet1; - ethernet2 = &enet2; - ethernet3 = &enet3; - ethernet4 = &enet4; - ethernet5 = &enet5; - ethernet6 = &enet6; - ethernet7 = &enet7; - rtc1 = &ftm_alarm0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x1>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x2>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x3>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - l2: l2-cache { - compatible = "cache"; - }; - }; - - idle-states { - /* - * PSCI node is not added default, U-boot will add missing - * parts if it determines to use PSCI. - */ - entry-method = "psci"; - - CPU_PH20: cpu-ph20 { - compatible = "arm,idle-state"; - idle-state-name = "PH20"; - arm,psci-suspend-param = <0x0>; - entry-latency-us = <1000>; - exit-latency-us = <1000>; - min-residency-us = <3000>; - }; - }; - - memory@80000000 { - device_type = "memory"; - /* Real size will be filled by bootloader */ - reg = <0x0 0x80000000 0x0 0x0>; - }; - - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "sysclk"; - }; - - reboot { - compatible ="syscon-reboot"; - regmap = <&dcfg>; - offset = <0xb0>; - mask = <0x02>; - }; - - thermal-zones { - ddr-controller { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 0>; - - trips { - ddr-ctrler-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - ddr-ctrler-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - serdes { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 1>; - - trips { - serdes-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - serdes-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - fman { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 2>; - - trips { - fman-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - fman-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - core-cluster { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 3>; - - trips { - core_cluster_alert: core-cluster-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - core_cluster_crit: core-cluster-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&core_cluster_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - sec { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 4>; - - trips { - sec-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - sec-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a72-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - gic: interrupt-controller@1400000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x1410000 0 0x10000>, /* GICD */ - <0x0 0x1420000 0 0x20000>, /* GICC */ - <0x0 0x1440000 0 0x20000>, /* GICH */ - <0x0 0x1460000 0 0x20000>; /* GICV */ - interrupts = ; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ddr: memory-controller@1080000 { - compatible = "fsl,qoriq-memory-controller"; - reg = <0x0 0x1080000 0x0 0x1000>; - interrupts = ; - big-endian; - }; - - ifc: ifc@1530000 { - compatible = "fsl,ifc", "simple-bus"; - reg = <0x0 0x1530000 0x0 0x10000>; - interrupts = ; - status = "disabled"; - }; - - qspi: spi@1550000 { - compatible = "fsl,ls1021a-qspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x1550000 0x0 0x10000>, - <0x0 0x40000000 0x0 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = ; - clock-names = "qspi_en", "qspi"; - clocks = <&clockgen 4 1>, <&clockgen 4 1>; - status = "disabled"; - }; - - esdhc: esdhc@1560000 { - compatible = "fsl,ls1046a-esdhc", "fsl,esdhc"; - reg = <0x0 0x1560000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 2 1>; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - big-endian; - bus-width = <4>; - }; - - scfg: scfg@1570000 { - compatible = "fsl,ls1046a-scfg", "syscon"; - reg = <0x0 0x1570000 0x0 0x10000>; - big-endian; - }; - - crypto: crypto@1700000 { - compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", - "fsl,sec-v4.0"; - fsl,sec-era = <8>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x1700000 0x100000>; - reg = <0x00 0x1700000 0x0 0x100000>; - interrupts = ; - dma-coherent; - - sec_jr0: jr@10000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; - interrupts = ; - }; - - sec_jr1: jr@20000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; - interrupts = ; - }; - - sec_jr2: jr@30000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; - interrupts = ; - }; - - sec_jr3: jr@40000 { - compatible = "fsl,sec-v5.4-job-ring", - "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; - interrupts = ; - }; - }; - - qman: qman@1880000 { - compatible = "fsl,qman"; - reg = <0x0 0x1880000 0x0 0x10000>; - interrupts = ; - memory-region = <&qman_fqd &qman_pfdr>; - - }; - - bman: bman@1890000 { - compatible = "fsl,bman"; - reg = <0x0 0x1890000 0x0 0x10000>; - interrupts = ; - memory-region = <&bman_fbpr>; - - }; - - qportals: qman-portals@500000000 { - ranges = <0x0 0x5 0x00000000 0x8000000>; - }; - - bportals: bman-portals@508000000 { - ranges = <0x0 0x5 0x08000000 0x8000000>; - }; - - dcfg: dcfg@1ee0000 { - compatible = "fsl,ls1046a-dcfg", "syscon"; - reg = <0x0 0x1ee0000 0x0 0x1000>; - big-endian; - }; - - clockgen: clocking@1ee1000 { - compatible = "fsl,ls1046a-clockgen"; - reg = <0x0 0x1ee1000 0x0 0x1000>; - #clock-cells = <2>; - clocks = <&sysclk>; - }; - - tmu: tmu@1f00000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x0 0x1f00000 0x0 0x10000>; - interrupts = <0 33 0x4>; - fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; - fsl,tmu-calibration = - /* Calibration data group 1 */ - <0x00000000 0x00000026 - 0x00000001 0x0000002d - 0x00000002 0x00000032 - 0x00000003 0x00000039 - 0x00000004 0x0000003f - 0x00000005 0x00000046 - 0x00000006 0x0000004d - 0x00000007 0x00000054 - 0x00000008 0x0000005a - 0x00000009 0x00000061 - 0x0000000a 0x0000006a - 0x0000000b 0x00000071 - /* Calibration data group 2 */ - 0x00010000 0x00000025 - 0x00010001 0x0000002c - 0x00010002 0x00000035 - 0x00010003 0x0000003d - 0x00010004 0x00000045 - 0x00010005 0x0000004e - 0x00010006 0x00000057 - 0x00010007 0x00000061 - 0x00010008 0x0000006b - 0x00010009 0x00000076 - /* Calibration data group 3 */ - 0x00020000 0x00000029 - 0x00020001 0x00000033 - 0x00020002 0x0000003d - 0x00020003 0x00000049 - 0x00020004 0x00000056 - 0x00020005 0x00000061 - 0x00020006 0x0000006d - /* Calibration data group 4 */ - 0x00030000 0x00000021 - 0x00030001 0x0000002a - 0x00030002 0x0000003c - 0x00030003 0x0000004e>; - big-endian; - #thermal-sensor-cells = <1>; - }; - - dspi: spi@2100000 { - compatible = "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = ; - clock-names = "dspi"; - clocks = <&clockgen 4 1>; - spi-num-chipselects = <5>; - big-endian; - status = "disabled"; - }; - - i2c0: i2c@2180000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2180000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>; - dmas = <&edma0 1 39>, - <&edma0 1 38>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - i2c1: i2c@2190000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2190000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>; - status = "disabled"; - }; - - i2c2: i2c@21a0000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x21a0000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>; - status = "disabled"; - }; - - i2c3: i2c@21b0000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x21b0000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>; - status = "disabled"; - }; - - duart0: serial@21c0500 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x00 0x21c0500 0x0 0x100>; - interrupts = ; - clocks = <&clockgen 4 1>; - status = "disabled"; - }; - - duart1: serial@21c0600 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x00 0x21c0600 0x0 0x100>; - interrupts = ; - clocks = <&clockgen 4 1>; - status = "disabled"; - }; - - duart2: serial@21d0500 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21d0500 0x0 0x100>; - interrupts = ; - clocks = <&clockgen 4 1>; - status = "disabled"; - }; - - duart3: serial@21d0600 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21d0600 0x0 0x100>; - interrupts = ; - clocks = <&clockgen 4 1>; - status = "disabled"; - }; - - gpio0: gpio@2300000 { - compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2310000 { - compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2320000 { - compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@2330000 { - compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2330000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - lpuart0: serial@2950000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2950000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 0>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart1: serial@2960000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2960000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart2: serial@2970000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2970000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart3: serial@2980000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2980000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart4: serial@2990000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2990000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart5: serial@29a0000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x29a0000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; - - wdog0: watchdog@2ad0000 { - compatible = "fsl,imx21-wdt"; - reg = <0x0 0x2ad0000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 1>; - big-endian; - }; - - edma0: edma@2c00000 { - #dma-cells = <2>; - compatible = "fsl,vf610-edma"; - reg = <0x0 0x2c00000 0x0 0x10000>, - <0x0 0x2c10000 0x0 0x10000>, - <0x0 0x2c20000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "edma-tx", "edma-err"; - dma-channels = <32>; - big-endian; - clock-names = "dmamux0", "dmamux1"; - clocks = <&clockgen 4 1>, - <&clockgen 4 1>; - }; - - usb0: usb@2f00000 { - compatible = "snps,dwc3"; - reg = <0x0 0x2f00000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - usb1: usb@3000000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3000000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - usb2: usb@3100000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - sata: sata@3200000 { - compatible = "fsl,ls1046a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>, - <0x0 0x20140520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = ; - clocks = <&clockgen 4 1>; - }; - - msi1: msi-controller@1580000 { - compatible = "fsl,ls1046a-msi"; - msi-controller; - reg = <0x0 0x1580000 0x0 0x10000>; - interrupts = , - , - , - ; - }; - - msi2: msi-controller@1590000 { - compatible = "fsl,ls1046a-msi"; - msi-controller; - reg = <0x0 0x1590000 0x0 0x10000>; - interrupts = , - , - , - ; - }; - - msi3: msi-controller@15a0000 { - compatible = "fsl,ls1046a-msi"; - msi-controller; - reg = <0x0 0x15a0000 0x0 0x10000>; - interrupts = , - , - , - ; - }; - - pcie1: pcie@3400000 { - compatible = "fsl,ls1046a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = , /* controller interrupt */ - ; /* PME interrupt */ - interrupt-names = "aer", "pme"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <8>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi1>, <&msi2>, <&msi3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - pcie_ep1: pcie_ep@3400000 { - compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; - reg = <0x00 0x03400000 0x0 0x00100000 - 0x40 0x00000000 0x8 0x00000000>; - reg-names = "regs", "addr_space"; - num-ib-windows = <6>; - num-ob-windows = <8>; - status = "disabled"; - }; - - pcie2: pcie@3500000 { - compatible = "fsl,ls1046a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = , /* controller interrupt */ - ; /* PME interrupt */ - interrupt-names = "aer", "pme"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <8>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi2>, <&msi3>, <&msi1>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - pcie_ep2: pcie_ep@3500000 { - compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; - reg = <0x00 0x03500000 0x0 0x00100000 - 0x48 0x00000000 0x8 0x00000000>; - reg-names = "regs", "addr_space"; - num-ib-windows = <6>; - num-ob-windows = <8>; - status = "disabled"; - }; - - pcie3: pcie@3600000 { - compatible = "fsl,ls1046a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = , /* controller interrupt */ - ; /* PME interrupt */ - interrupt-names = "aer", "pme"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <8>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi3>, <&msi1>, <&msi2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - pcie_ep3: pcie_ep@3600000 { - compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"; - reg = <0x00 0x03600000 0x0 0x00100000 - 0x50 0x00000000 0x8 0x00000000>; - reg-names = "regs", "addr_space"; - num-ib-windows = <6>; - num-ob-windows = <8>; - status = "disabled"; - }; - - qdma: dma-controller@8380000 { - compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma"; - reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ - <0x0 0x8390000 0x0 0x10000>, /* Status regs */ - <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ - interrupts = , - , - , - , - ; - interrupt-names = "qdma-error", "qdma-queue0", - "qdma-queue1", "qdma-queue2", "qdma-queue3"; - dma-channels = <8>; - block-number = <1>; - block-offset = <0x10000>; - fsl,dma-queues = <2>; - status-sizes = <64>; - queue-sizes = <64 64>; - big-endian; - }; - - rcpm: power-controller@1ee2140 { - compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+"; - reg = <0x0 0x1ee2140 0x0 0x4>; - #fsl,rcpm-wakeup-cells = <1>; - }; - - ftm_alarm0: timer@29d0000 { - compatible = "fsl,ls1046a-ftm-alarm"; - reg = <0x0 0x29d0000 0x0 0x10000>; - fsl,rcpm-wakeup = <&rcpm 0x20000>; - interrupts = ; - big-endian; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - bman_fbpr: bman-fbpr { - compatible = "shared-dma-pool"; - size = <0 0x1000000>; - alignment = <0 0x1000000>; - no-map; - }; - - qman_fqd: qman-fqd { - compatible = "shared-dma-pool"; - size = <0 0x800000>; - alignment = <0 0x800000>; - no-map; - }; - - qman_pfdr: qman-pfdr { - compatible = "shared-dma-pool"; - size = <0 0x2000000>; - alignment = <0 0x2000000>; - no-map; - }; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; -}; - -#include "qoriq-qman-portals.dtsi" -#include "qoriq-bman-portals.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts deleted file mode 100644 index 41d8b15f2..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for NXP LS1088A QDS Board. - * - * Copyright 2017 NXP - * - * Harninder Rai - * - */ - -/dts-v1/; - -#include "fsl-ls1088a.dtsi" - -/ { - model = "LS1088A QDS Board"; - compatible = "fsl,ls1088a-qds", "fsl,ls1088a"; -}; - -&dspi { - bus-num = <0>; - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - - flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-cpol; - spi-cpha; - spi-max-frequency = <3500000>; - reg = <1>; - }; - - flash@2 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-cpol; - spi-cpha; - spi-max-frequency = <3500000>; - reg = <2>; - }; -}; - -&i2c0 { - status = "okay"; - - i2c-switch@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - - ina220@41 { - compatible = "ti,ina220"; - reg = <0x41>; - shunt-resistor = <1000>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - temp-sensor@4c { - compatible = "adi,adt7461a"; - reg = <0x4c>; - }; - - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - /* IRQ10_B */ - interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; - }; - - eeprom@56 { - compatible = "atmel,24c512"; - reg = <0x56>; - }; - - eeprom@57 { - compatible = "atmel,24c512"; - reg = <0x57>; - }; - }; - }; -}; - -&ifc { - ranges = <0 0 0x5 0x80000000 0x08000000 - 2 0 0x5 0x30000000 0x00010000 - 3 0 0x5 0x20000000 0x00010000>; - status = "okay"; - - nor@0,0 { - compatible = "cfi-flash"; - reg = <0x0 0x0 0x8000000>; - bank-width = <2>; - device-width = <1>; - }; - - nand@2,0 { - compatible = "fsl,ifc-nand"; - reg = <0x2 0x0 0x10000>; - }; - - fpga: board-control@3,0 { - compatible = "fsl,ls1088aqds-fpga", "fsl,fpga-qixis"; - reg = <0x3 0x0 0x0000100>; - }; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&esdhc { - status = "okay"; -}; - -&qspi { - status = "okay"; - - s25fs512s0: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - reg = <0>; - }; - - s25fs512s1: flash@1 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - reg = <1>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts deleted file mode 100644 index 5633e59fe..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for NXP LS1088A RDB Board. - * - * Copyright 2017 NXP - * - * Harninder Rai - * - */ - -/dts-v1/; - -#include "fsl-ls1088a.dtsi" - -/ { - model = "LS1088A RDB Board"; - compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; -}; - -&i2c0 { - status = "okay"; - - i2c-switch@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - temp-sensor@4c { - compatible = "adi,adt7461a"; - reg = <0x4c>; - }; - - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - /* IRQ10_B */ - interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; -}; - -&ifc { - ranges = <0 0 0x5 0x30000000 0x00010000 - 2 0 0x5 0x20000000 0x00010000>; - status = "okay"; - - nand@0,0 { - compatible = "fsl,ifc-nand"; - reg = <0x0 0x0 0x10000>; - }; - - fpga: board-control@2,0 { - compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis"; - reg = <0x2 0x0 0x0000100>; - }; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&esdhc { - mmc-hs200-1_8v; - status = "okay"; -}; - -&qspi { - status = "okay"; - - s25fs512s0: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - reg = <0>; - }; - - s25fs512s1: flash@1 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - reg = <1>; - }; -}; - -&sata { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - dr_mode = "otg"; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi deleted file mode 100644 index 334af263d..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ /dev/null @@ -1,825 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for NXP Layerscape-1088A family SoC. - * - * Copyright 2017-2020 NXP - * - * Harninder Rai - * - */ -#include -#include - -/ { - compatible = "fsl,ls1088a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - crypto = &crypto; - rtc1 = &ftm_alarm0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - /* We have 2 clusters having 4 Cortex-A53 cores each */ - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - clocks = <&clockgen 1 0>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - clocks = <&clockgen 1 0>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x2>; - clocks = <&clockgen 1 0>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x3>; - clocks = <&clockgen 1 0>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x100>; - clocks = <&clockgen 1 1>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x101>; - clocks = <&clockgen 1 1>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x102>; - clocks = <&clockgen 1 1>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - cpu7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x103>; - clocks = <&clockgen 1 1>; - cpu-idle-states = <&CPU_PH20>; - #cooling-cells = <2>; - }; - - CPU_PH20: cpu-ph20 { - compatible = "arm,idle-state"; - idle-state-name = "PH20"; - arm,psci-suspend-param = <0x0>; - entry-latency-us = <1000>; - exit-latency-us = <1000>; - min-residency-us = <3000>; - }; - }; - - gic: interrupt-controller@6000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ - <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ - <0x0 0x0c0c0000 0 0x2000>, /* GICC */ - <0x0 0x0c0d0000 0 0x1000>, /* GICH */ - <0x0 0x0c0e0000 0 0x20000>; /* GICV */ - interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - its: gic-its@6020000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x0 0x6020000 0 0x20000>; - }; - }; - - thermal-zones { - core-cluster { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 0>; - - trips { - core_cluster_alert: core-cluster-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - core-cluster-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&core_cluster_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - soc { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 1>; - - trips { - soc-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ - <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ - <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ - <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "sysclk"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; - - clockgen: clocking@1300000 { - compatible = "fsl,ls1088a-clockgen"; - reg = <0 0x1300000 0 0xa0000>; - #clock-cells = <2>; - clocks = <&sysclk>; - }; - - dcfg: dcfg@1e00000 { - compatible = "fsl,ls1088a-dcfg", "syscon"; - reg = <0x0 0x1e00000 0x0 0x10000>; - little-endian; - }; - - tmu: tmu@1f80000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x0 0x1f80000 0x0 0x10000>; - interrupts = <0 23 0x4>; - fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; - fsl,tmu-calibration = - /* Calibration data group 1 */ - <0x00000000 0x00000023 - 0x00000001 0x0000002a - 0x00000002 0x00000030 - 0x00000003 0x00000037 - 0x00000004 0x0000003d - 0x00000005 0x00000044 - 0x00000006 0x0000004a - 0x00000007 0x00000051 - 0x00000008 0x00000057 - 0x00000009 0x0000005e - 0x0000000a 0x00000064 - 0x0000000b 0x0000006b - /* Calibration data group 2 */ - 0x00010000 0x00000022 - 0x00010001 0x0000002a - 0x00010002 0x00000032 - 0x00010003 0x0000003a - 0x00010004 0x00000042 - 0x00010005 0x0000004a - 0x00010006 0x00000052 - 0x00010007 0x0000005a - 0x00010008 0x00000062 - 0x00010009 0x0000006a - /* Calibration data group 3 */ - 0x00020000 0x00000021 - 0x00020001 0x0000002b - 0x00020002 0x00000035 - 0x00020003 0x00000040 - 0x00020004 0x0000004a - 0x00020005 0x00000054 - 0x00020006 0x0000005e - /* Calibration data group 4 */ - 0x00030000 0x00000010 - 0x00030001 0x0000001c - 0x00030002 0x00000027 - 0x00030003 0x00000032 - 0x00030004 0x0000003e - 0x00030005 0x00000049 - 0x00030006 0x00000054 - 0x00030007 0x00000060>; - little-endian; - #thermal-sensor-cells = <1>; - }; - - dspi: spi@2100000 { - compatible = "fsl,ls1088a-dspi", - "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = ; - clock-names = "dspi"; - clocks = <&clockgen 4 1>; - spi-num-chipselects = <6>; - status = "disabled"; - }; - - duart0: serial@21c0500 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0500 0x0 0x100>; - clocks = <&clockgen 4 3>; - interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - duart1: serial@21c0600 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0600 0x0 0x100>; - clocks = <&clockgen 4 3>; - interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - gpio0: gpio@2300000 { - compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2310000 { - compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2320000 { - compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@2330000 { - compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2330000 0x0 0x10000>; - interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - ifc: ifc@2240000 { - compatible = "fsl,ifc", "simple-bus"; - reg = <0x0 0x2240000 0x0 0x20000>; - interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - #address-cells = <2>; - #size-cells = <1>; - status = "disabled"; - }; - - i2c0: i2c@2000000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2000000 0x0 0x10000>; - interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 7>; - status = "disabled"; - }; - - i2c1: i2c@2010000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2010000 0x0 0x10000>; - interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 7>; - status = "disabled"; - }; - - i2c2: i2c@2020000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2020000 0x0 0x10000>; - interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 7>; - status = "disabled"; - }; - - i2c3: i2c@2030000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2030000 0x0 0x10000>; - interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 7>; - status = "disabled"; - }; - - qspi: spi@20c0000 { - compatible = "fsl,ls2080a-qspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x20c0000 0x0 0x10000>, - <0x0 0x20000000 0x0 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = ; - clock-names = "qspi_en", "qspi"; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - status = "disabled"; - }; - - esdhc: esdhc@2140000 { - compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; - reg = <0x0 0x2140000 0x0 0x10000>; - interrupts = <0 28 0x4>; /* Level high type */ - clock-frequency = <0>; - clocks = <&clockgen 2 1>; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - little-endian; - bus-width = <4>; - status = "disabled"; - }; - - usb0: usb3@3100000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - status = "disabled"; - }; - - usb1: usb3@3110000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3110000 0x0 0x10000>; - interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - status = "disabled"; - }; - - sata: sata@3200000 { - compatible = "fsl,ls1088a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>, - <0x7 0x100520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 3>; - dma-coherent; - status = "disabled"; - }; - - crypto: crypto@8000000 { - compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; - fsl,sec-era = <8>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x8000000 0x100000>; - reg = <0x00 0x8000000 0x0 0x100000>; - interrupts = ; - dma-coherent; - - sec_jr0: jr@10000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; - interrupts = ; - }; - - sec_jr1: jr@20000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; - interrupts = ; - }; - - sec_jr2: jr@30000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; - interrupts = ; - }; - - sec_jr3: jr@40000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; - interrupts = ; - }; - }; - - pcie1: pcie@3400000 { - compatible = "fsl,ls1088a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ - interrupt-names = "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <256>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - pcie2: pcie@3500000 { - compatible = "fsl,ls1088a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ - interrupt-names = "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <6>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - pcie3: pcie@3600000 { - compatible = "fsl,ls1088a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ - interrupt-names = "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <6>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - smmu: iommu@5000000 { - compatible = "arm,mmu-500"; - reg = <0 0x5000000 0 0x800000>; - #iommu-cells = <1>; - stream-match-mask = <0x7C00>; - #global-interrupts = <12>; - // global secure fault - interrupts = , - // combined secure - , - // global non-secure fault - , - // combined non-secure - , - // performance counter interrupts 0-7 - , - , - , - , - , - , - , - , - // per context interrupt, 64 interrupts - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - console@8340020 { - compatible = "fsl,dpaa2-console"; - reg = <0x00000000 0x08340020 0 0x2>; - }; - - ptp-timer@8b95000 { - compatible = "fsl,dpaa2-ptp"; - reg = <0x0 0x8b95000 0x0 0x100>; - clocks = <&clockgen 4 0>; - little-endian; - fsl,extts-fifo; - }; - - cluster1_core0_watchdog: wdt@c000000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xc000000 0x0 0x1000>; - clocks = <&clockgen 4 15>, <&clockgen 4 15>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - cluster1_core1_watchdog: wdt@c010000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xc010000 0x0 0x1000>; - clocks = <&clockgen 4 15>, <&clockgen 4 15>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - cluster1_core2_watchdog: wdt@c020000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xc020000 0x0 0x1000>; - clocks = <&clockgen 4 15>, <&clockgen 4 15>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - cluster1_core3_watchdog: wdt@c030000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xc030000 0x0 0x1000>; - clocks = <&clockgen 4 15>, <&clockgen 4 15>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - cluster2_core0_watchdog: wdt@c100000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xc100000 0x0 0x1000>; - clocks = <&clockgen 4 15>, <&clockgen 4 15>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - cluster2_core1_watchdog: wdt@c110000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xc110000 0x0 0x1000>; - clocks = <&clockgen 4 15>, <&clockgen 4 15>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - cluster2_core2_watchdog: wdt@c120000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xc120000 0x0 0x1000>; - clocks = <&clockgen 4 15>, <&clockgen 4 15>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - cluster2_core3_watchdog: wdt@c130000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xc130000 0x0 0x1000>; - clocks = <&clockgen 4 15>, <&clockgen 4 15>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - fsl_mc: fsl-mc@80c000000 { - compatible = "fsl,qoriq-mc"; - reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ - <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ - msi-parent = <&its>; - iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ - dma-coherent; - #address-cells = <3>; - #size-cells = <1>; - - /* - * Region type 0x0 - MC portals - * Region type 0x1 - QBMAN portals - */ - ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 - 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; - - dpmacs { - #address-cells = <1>; - #size-cells = <0>; - - dpmac1: dpmac@1 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <1>; - }; - - dpmac2: dpmac@2 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <2>; - }; - - dpmac3: dpmac@3 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <3>; - }; - - dpmac4: dpmac@4 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <4>; - }; - - dpmac5: dpmac@5 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <5>; - }; - - dpmac6: dpmac@6 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <6>; - }; - - dpmac7: dpmac@7 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <7>; - }; - - dpmac8: dpmac@8 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <8>; - }; - - dpmac9: dpmac@9 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <9>; - }; - - dpmac10: dpmac@a { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xa>; - }; - }; - }; - - rcpm: power-controller@1e34040 { - compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+"; - reg = <0x0 0x1e34040 0x0 0x18>; - #fsl,rcpm-wakeup-cells = <6>; - little-endian; - }; - - ftm_alarm0: timer@2800000 { - compatible = "fsl,ls1088a-ftm-alarm"; - reg = <0x0 0x2800000 0x0 0x10000>; - fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; - interrupts = ; - }; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts deleted file mode 100644 index f6c3ee78a..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Freescale LS2080a QDS Board. - * - * Copyright 2015-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - * - * Abhimanyu Saini - * Bhupesh Sharma - * - */ - -/dts-v1/; - -#include "fsl-ls2080a.dtsi" -#include "fsl-ls208xa-qds.dtsi" - -/ { - model = "Freescale Layerscape 2080a QDS Board"; - compatible = "fsl,ls2080a-qds", "fsl,ls2080a"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts deleted file mode 100644 index 448943560..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Freescale LS2080a RDB Board. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - * - * Abhimanyu Saini - * Bhupesh Sharma - * - */ - -/dts-v1/; - -#include "fsl-ls2080a.dtsi" -#include "fsl-ls208xa-rdb.dtsi" - -/ { - model = "Freescale Layerscape 2080a RDB Board"; - compatible = "fsl,ls2080a-rdb", "fsl,ls2080a"; - - chosen { - stdout-path = "serial1:115200n8"; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts deleted file mode 100644 index 551730503..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Freescale LS2080a software Simulator model - * - * Copyright 2014-2015 Freescale Semiconductor, Inc. - * - * Bhupesh Sharma - * - */ - -/dts-v1/; - -#include "fsl-ls2080a.dtsi" - -/ { - model = "Freescale Layerscape 2080a software Simulator model"; - compatible = "fsl,ls2080a-simu", "fsl,ls2080a"; - - ethernet@2210000 { - compatible = "smsc,lan91c111"; - reg = <0x0 0x2210000 0x0 0x100>; - interrupts = <0 58 0x1>; - }; -}; - -&ifc { - status = "okay"; -}; - diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi deleted file mode 100644 index f9c1d30cf..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Freescale Layerscape-2080A family SoC. - * - * Copyright 2014-2016 Freescale Semiconductor, Inc. - * - * Abhimanyu Saini - * Bhupesh Sharma - * - */ - -#include "fsl-ls208xa.dtsi" - -&cpu { - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0>; - clocks = <&clockgen 1 0>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster0_l2>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x1>; - clocks = <&clockgen 1 0>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster0_l2>; - #cooling-cells = <2>; - }; - - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x100>; - clocks = <&clockgen 1 1>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster1_l2>; - #cooling-cells = <2>; - }; - - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x101>; - clocks = <&clockgen 1 1>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster1_l2>; - #cooling-cells = <2>; - }; - - cpu4: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x200>; - clocks = <&clockgen 1 2>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster2_l2>; - #cooling-cells = <2>; - }; - - cpu5: cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x201>; - clocks = <&clockgen 1 2>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster2_l2>; - #cooling-cells = <2>; - }; - - cpu6: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x300>; - clocks = <&clockgen 1 3>; - next-level-cache = <&cluster3_l2>; - cpu-idle-states = <&CPU_PW20>; - #cooling-cells = <2>; - }; - - cpu7: cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x301>; - clocks = <&clockgen 1 3>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster3_l2>; - #cooling-cells = <2>; - }; - - cluster0_l2: l2-cache0 { - compatible = "cache"; - }; - - cluster1_l2: l2-cache1 { - compatible = "cache"; - }; - - cluster2_l2: l2-cache2 { - compatible = "cache"; - }; - - cluster3_l2: l2-cache3 { - compatible = "cache"; - }; - - CPU_PW20: cpu-pw20 { - compatible = "arm,idle-state"; - idle-state-name = "PW20"; - arm,psci-suspend-param = <0x00010000>; - entry-latency-us = <2000>; - exit-latency-us = <2000>; - min-residency-us = <6000>; - }; -}; - -&pcie1 { - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x10 0x00000000 0x0 0x00002000>; /* configuration space */ - - ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -}; - -&pcie2 { - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x12 0x00000000 0x0 0x00002000>; /* configuration space */ - - ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -}; - -&pcie3 { - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x14 0x00000000 0x0 0x00002000>; /* configuration space */ - - ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -}; - -&pcie4 { - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ - 0x16 0x00000000 0x0 0x00002000>; /* configuration space */ - - ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts deleted file mode 100644 index 7c17b1bd4..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Freescale LS2088A QDS Board. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - * - * Abhimanyu Saini - * - */ - -/dts-v1/; - -#include "fsl-ls2088a.dtsi" -#include "fsl-ls208xa-qds.dtsi" - -/ { - model = "Freescale Layerscape 2088A QDS Board"; - compatible = "fsl,ls2088a-qds", "fsl,ls2088a"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts deleted file mode 100644 index f6b4d75a2..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Freescale LS2088A RDB Board. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - * - * Abhimanyu Saini - * - */ - -/dts-v1/; - -#include "fsl-ls2088a.dtsi" -#include "fsl-ls208xa-rdb.dtsi" - -/ { - model = "Freescale Layerscape 2088A RDB Board"; - compatible = "fsl,ls2088a-rdb", "fsl,ls2088a"; - - chosen { - stdout-path = "serial1:115200n8"; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi deleted file mode 100644 index a5f668d78..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ /dev/null @@ -1,155 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Freescale Layerscape-2088A family SoC. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - * - * Abhimanyu Saini - * - */ - -#include "fsl-ls208xa.dtsi" - -&cpu { - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x0>; - clocks = <&clockgen 1 0>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster0_l2>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x1>; - clocks = <&clockgen 1 0>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster0_l2>; - #cooling-cells = <2>; - }; - - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x100>; - clocks = <&clockgen 1 1>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster1_l2>; - #cooling-cells = <2>; - }; - - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x101>; - clocks = <&clockgen 1 1>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster1_l2>; - #cooling-cells = <2>; - }; - - cpu4: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x200>; - clocks = <&clockgen 1 2>; - next-level-cache = <&cluster2_l2>; - cpu-idle-states = <&CPU_PW20>; - #cooling-cells = <2>; - }; - - cpu5: cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x201>; - clocks = <&clockgen 1 2>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster2_l2>; - #cooling-cells = <2>; - }; - - cpu6: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x300>; - clocks = <&clockgen 1 3>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster3_l2>; - #cooling-cells = <2>; - }; - - cpu7: cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x301>; - clocks = <&clockgen 1 3>; - cpu-idle-states = <&CPU_PW20>; - next-level-cache = <&cluster3_l2>; - #cooling-cells = <2>; - }; - - cluster0_l2: l2-cache0 { - compatible = "cache"; - }; - - cluster1_l2: l2-cache1 { - compatible = "cache"; - }; - - cluster2_l2: l2-cache2 { - compatible = "cache"; - }; - - cluster3_l2: l2-cache3 { - compatible = "cache"; - }; - - CPU_PW20: cpu-pw20 { - compatible = "arm,idle-state"; - idle-state-name = "PW20"; - arm,psci-suspend-param = <0x0>; - entry-latency-us = <2000>; - exit-latency-us = <2000>; - min-residency-us = <6000>; - }; -}; - -&pcie1 { - compatible = "fsl,ls2088a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ - - ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 - 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; -}; - -&pcie2 { - compatible = "fsl,ls2088a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ - - ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 - 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; -}; - -&pcie3 { - compatible = "fsl,ls2088a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ - - ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 - 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; -}; - -&pcie4 { - compatible = "fsl,ls2088a-pcie"; - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ - 0x38 0x00000000 0x0 0x00002000>; /* configuration space */ - - ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000 - 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi deleted file mode 100644 index 10d2fe091..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Freescale LS2080A QDS Board. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - * - * Abhimanyu Saini - * - */ - -&esdhc { - mmc-hs200-1_8v; - status = "okay"; -}; - -&ifc { - status = "okay"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0x0 0x0 0x5 0x80000000 0x08000000 - 0x2 0x0 0x5 0x30000000 0x00010000 - 0x3 0x0 0x5 0x20000000 0x00010000>; - - nor@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0x0 0x0 0x8000000>; - bank-width = <2>; - device-width = <1>; - }; - - nand@2,0 { - compatible = "fsl,ifc-nand"; - reg = <0x2 0x0 0x10000>; - }; - - cpld@3,0 { - reg = <0x3 0x0 0x10000>; - compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis"; - }; -}; - -&i2c0 { - status = "okay"; - pca9547@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x00>; - rtc@68 { - compatible = "dallas,ds3232"; - reg = <0x68>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x02>; - - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <500>; - }; - - ina220@41 { - compatible = "ti,ina220"; - reg = <0x41>; - shunt-resistor = <1000>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - adt7481@4c { - compatible = "adi,adt7461"; - reg = <0x4c>; - }; - }; - }; -}; - -&i2c1 { - status = "disabled"; -}; - -&i2c2 { - status = "disabled"; -}; - -&i2c3 { - status = "disabled"; -}; - -&dspi { - status = "okay"; - dflash0: n25q128a@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80"; - spi-max-frequency = <3000000>; - reg = <0>; - }; - dflash1: sst25wf040b@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80"; - spi-max-frequency = <3000000>; - reg = <1>; - }; - dflash2: en25s64@2 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80"; - spi-max-frequency = <3000000>; - reg = <2>; - }; -}; - -&qspi { - status = "okay"; - flash0: s25fl256s1@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80"; - spi-max-frequency = <20000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - reg = <0>; - }; - flash2: s25fl256s1@2 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80"; - spi-max-frequency = <20000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - reg = <2>; - }; -}; - -&sata0 { - status = "okay"; -}; - -&sata1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi deleted file mode 100644 index d0d670227..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi +++ /dev/null @@ -1,136 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Freescale LS2080A RDB Board. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - * - * Abhimanyu Saini - * - */ - -&esdhc { - status = "okay"; -}; - -&ifc { - status = "okay"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0x0 0x0 0x5 0x80000000 0x08000000 - 0x2 0x0 0x5 0x30000000 0x00010000 - 0x3 0x0 0x5 0x20000000 0x00010000>; - - nor@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0x0 0x0 0x8000000>; - bank-width = <2>; - device-width = <1>; - }; - - nand@2,0 { - compatible = "fsl,ifc-nand"; - reg = <0x2 0x0 0x10000>; - }; - - cpld@3,0 { - reg = <0x3 0x0 0x10000>; - compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis"; - }; - -}; - -&i2c0 { - status = "okay"; - pca9547@75 { - compatible = "nxp,pca9547"; - reg = <0x75>; - #address-cells = <1>; - #size-cells = <0>; - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x01>; - rtc@68 { - compatible = "dallas,ds3232"; - reg = <0x68>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x02>; - - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <500>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - adt7481@4c { - compatible = "adi,adt7461"; - reg = <0x4c>; - }; - }; - }; -}; - -&i2c1 { - status = "disabled"; -}; - -&i2c2 { - status = "disabled"; -}; - -&i2c3 { - status = "disabled"; -}; - -&dspi { - status = "okay"; - dflash0: n25q512a@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80"; - spi-max-frequency = <3000000>; - reg = <0>; - }; -}; - -&qspi { - status = "okay"; - - s25fs512s0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; -}; - -&sata0 { - status = "okay"; -}; - -&sata1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi deleted file mode 100644 index eb6641a35..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ /dev/null @@ -1,925 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Freescale Layerscape-2080A family SoC. - * - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - * - * Abhimanyu Saini - * - */ - -#include -#include - -/ { - compatible = "fsl,ls2080a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - crypto = &crypto; - rtc1 = &ftm_alarm0; - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - }; - - cpu: cpus { - #address-cells = <1>; - #size-cells = <0>; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x80000000>; - /* DRAM space - 1, size : 2 GB DRAM */ - }; - - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "sysclk"; - }; - - gic: interrupt-controller@6000000 { - compatible = "arm,gic-v3"; - reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ - <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ - <0x0 0x0c0c0000 0 0x2000>, /* GICC */ - <0x0 0x0c0d0000 0 0x1000>, /* GICH */ - <0x0 0x0c0e0000 0 0x20000>; /* GICV */ - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - interrupts = <1 9 0x4>; - - its: gic-its@6020000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x0 0x6020000 0 0x20000>; - }; - }; - - rstcr: syscon@1e60000 { - compatible = "fsl,ls2080a-rstcr", "syscon"; - reg = <0x0 0x1e60000 0x0 0x4>; - }; - - reboot { - compatible ="syscon-reboot"; - regmap = <&rstcr>; - offset = <0x0>; - mask = <0x2>; - }; - - thermal-zones { - ddr-controller1 { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 1>; - - trips { - ddr-ctrler1-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - ddr-controller2 { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 2>; - - trips { - ddr-ctrler2-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - ddr-controller3 { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 3>; - - trips { - ddr-ctrler3-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - core-cluster1 { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 4>; - - trips { - core_cluster1_alert: core-cluster1-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - core-cluster1-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&core_cluster1_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - core-cluster2 { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 5>; - - trips { - core_cluster2_alert: core-cluster2-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - core-cluster2-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&core_cluster2_alert>; - cooling-device = - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - core-cluster3 { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 6>; - - trips { - core_cluster3_alert: core-cluster3-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - core-cluster3-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&core_cluster3_alert>; - cooling-device = - <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - core-cluster4 { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 7>; - - trips { - core_cluster4_alert: core-cluster4-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - core-cluster4-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&core_cluster4_alert>; - cooling-device = - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 4>, /* Physical Secure PPI, active-low */ - <1 14 4>, /* Physical Non-Secure PPI, active-low */ - <1 11 4>, /* Virtual PPI, active-low */ - <1 10 4>; /* Hypervisor PPI, active-low */ - fsl,erratum-a008585; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; - - clockgen: clocking@1300000 { - compatible = "fsl,ls2080a-clockgen"; - reg = <0 0x1300000 0 0xa0000>; - #clock-cells = <2>; - clocks = <&sysclk>; - }; - - dcfg: dcfg@1e00000 { - compatible = "fsl,ls2080a-dcfg", "syscon"; - reg = <0x0 0x1e00000 0x0 0x10000>; - little-endian; - }; - - tmu: tmu@1f80000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x0 0x1f80000 0x0 0x10000>; - interrupts = <0 23 0x4>; - fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; - fsl,tmu-calibration = <0x00000000 0x00000026 - 0x00000001 0x0000002d - 0x00000002 0x00000032 - 0x00000003 0x00000039 - 0x00000004 0x0000003f - 0x00000005 0x00000046 - 0x00000006 0x0000004d - 0x00000007 0x00000054 - 0x00000008 0x0000005a - 0x00000009 0x00000061 - 0x0000000a 0x0000006a - 0x0000000b 0x00000071 - - 0x00010000 0x00000025 - 0x00010001 0x0000002c - 0x00010002 0x00000035 - 0x00010003 0x0000003d - 0x00010004 0x00000045 - 0x00010005 0x0000004e - 0x00010006 0x00000057 - 0x00010007 0x00000061 - 0x00010008 0x0000006b - 0x00010009 0x00000076 - - 0x00020000 0x00000029 - 0x00020001 0x00000033 - 0x00020002 0x0000003d - 0x00020003 0x00000049 - 0x00020004 0x00000056 - 0x00020005 0x00000061 - 0x00020006 0x0000006d - - 0x00030000 0x00000021 - 0x00030001 0x0000002a - 0x00030002 0x0000003c - 0x00030003 0x0000004e>; - little-endian; - #thermal-sensor-cells = <1>; - }; - - serial0: serial@21c0500 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0500 0x0 0x100>; - clocks = <&clockgen 4 3>; - interrupts = <0 32 0x4>; /* Level high type */ - }; - - serial1: serial@21c0600 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0600 0x0 0x100>; - clocks = <&clockgen 4 3>; - interrupts = <0 32 0x4>; /* Level high type */ - }; - - serial2: serial@21d0500 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21d0500 0x0 0x100>; - clocks = <&clockgen 4 3>; - interrupts = <0 33 0x4>; /* Level high type */ - }; - - serial3: serial@21d0600 { - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21d0600 0x0 0x100>; - clocks = <&clockgen 4 3>; - interrupts = <0 33 0x4>; /* Level high type */ - }; - - cluster1_core0_watchdog: wdt@c000000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xc000000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - cluster1_core1_watchdog: wdt@c010000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xc010000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - cluster2_core0_watchdog: wdt@c100000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xc100000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - cluster2_core1_watchdog: wdt@c110000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xc110000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - cluster3_core0_watchdog: wdt@c200000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xc200000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - cluster3_core1_watchdog: wdt@c210000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xc210000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - cluster4_core0_watchdog: wdt@c300000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xc300000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - cluster4_core1_watchdog: wdt@c310000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xc310000 0x0 0x1000>; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - crypto: crypto@8000000 { - compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; - fsl,sec-era = <8>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x8000000 0x100000>; - reg = <0x00 0x8000000 0x0 0x100000>; - interrupts = ; - dma-coherent; - - sec_jr0: jr@10000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; - interrupts = ; - }; - - sec_jr1: jr@20000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; - interrupts = ; - }; - - sec_jr2: jr@30000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; - interrupts = ; - }; - - sec_jr3: jr@40000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; - interrupts = ; - }; - }; - - console@8340020 { - compatible = "fsl,dpaa2-console"; - reg = <0x00000000 0x08340020 0 0x2>; - }; - - ptp-timer@8b95000 { - compatible = "fsl,dpaa2-ptp"; - reg = <0x0 0x8b95000 0x0 0x100>; - clocks = <&clockgen 4 1>; - little-endian; - fsl,extts-fifo; - }; - - fsl_mc: fsl-mc@80c000000 { - compatible = "fsl,qoriq-mc"; - reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ - <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ - msi-parent = <&its>; - iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ - dma-coherent; - #address-cells = <3>; - #size-cells = <1>; - - /* - * Region type 0x0 - MC portals - * Region type 0x1 - QBMAN portals - */ - ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 - 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; - - /* - * Define the maximum number of MACs present on the SoC. - */ - dpmacs { - #address-cells = <1>; - #size-cells = <0>; - - dpmac1: dpmac@1 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x1>; - }; - - dpmac2: dpmac@2 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x2>; - }; - - dpmac3: dpmac@3 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x3>; - }; - - dpmac4: dpmac@4 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x4>; - }; - - dpmac5: dpmac@5 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x5>; - }; - - dpmac6: dpmac@6 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x6>; - }; - - dpmac7: dpmac@7 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x7>; - }; - - dpmac8: dpmac@8 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x8>; - }; - - dpmac9: dpmac@9 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x9>; - }; - - dpmac10: dpmac@a { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xa>; - }; - - dpmac11: dpmac@b { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xb>; - }; - - dpmac12: dpmac@c { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xc>; - }; - - dpmac13: dpmac@d { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xd>; - }; - - dpmac14: dpmac@e { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xe>; - }; - - dpmac15: dpmac@f { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xf>; - }; - - dpmac16: dpmac@10 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x10>; - }; - }; - }; - - smmu: iommu@5000000 { - compatible = "arm,mmu-500"; - reg = <0 0x5000000 0 0x800000>; - #global-interrupts = <12>; - #iommu-cells = <1>; - stream-match-mask = <0x7C00>; - dma-coherent; - interrupts = <0 13 4>, /* global secure fault */ - <0 14 4>, /* combined secure interrupt */ - <0 15 4>, /* global non-secure fault */ - <0 16 4>, /* combined non-secure interrupt */ - /* performance counter interrupts 0-7 */ - <0 211 4>, <0 212 4>, - <0 213 4>, <0 214 4>, - <0 215 4>, <0 216 4>, - <0 217 4>, <0 218 4>, - /* per context interrupt, 64 interrupts */ - <0 146 4>, <0 147 4>, - <0 148 4>, <0 149 4>, - <0 150 4>, <0 151 4>, - <0 152 4>, <0 153 4>, - <0 154 4>, <0 155 4>, - <0 156 4>, <0 157 4>, - <0 158 4>, <0 159 4>, - <0 160 4>, <0 161 4>, - <0 162 4>, <0 163 4>, - <0 164 4>, <0 165 4>, - <0 166 4>, <0 167 4>, - <0 168 4>, <0 169 4>, - <0 170 4>, <0 171 4>, - <0 172 4>, <0 173 4>, - <0 174 4>, <0 175 4>, - <0 176 4>, <0 177 4>, - <0 178 4>, <0 179 4>, - <0 180 4>, <0 181 4>, - <0 182 4>, <0 183 4>, - <0 184 4>, <0 185 4>, - <0 186 4>, <0 187 4>, - <0 188 4>, <0 189 4>, - <0 190 4>, <0 191 4>, - <0 192 4>, <0 193 4>, - <0 194 4>, <0 195 4>, - <0 196 4>, <0 197 4>, - <0 198 4>, <0 199 4>, - <0 200 4>, <0 201 4>, - <0 202 4>, <0 203 4>, - <0 204 4>, <0 205 4>, - <0 206 4>, <0 207 4>, - <0 208 4>, <0 209 4>; - }; - - dspi: spi@2100000 { - status = "disabled"; - compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = <0 26 0x4>; /* Level high type */ - clocks = <&clockgen 4 3>; - clock-names = "dspi"; - spi-num-chipselects = <5>; - }; - - esdhc: esdhc@2140000 { - status = "disabled"; - compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; - reg = <0x0 0x2140000 0x0 0x10000>; - interrupts = <0 28 0x4>; /* Level high type */ - clocks = <&clockgen 4 1>; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - little-endian; - bus-width = <4>; - }; - - gpio0: gpio@2300000 { - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = <0 36 0x4>; /* Level high type */ - gpio-controller; - little-endian; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2310000 { - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = <0 36 0x4>; /* Level high type */ - gpio-controller; - little-endian; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2320000 { - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = <0 37 0x4>; /* Level high type */ - gpio-controller; - little-endian; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@2330000 { - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2330000 0x0 0x10000>; - interrupts = <0 37 0x4>; /* Level high type */ - gpio-controller; - little-endian; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - i2c0: i2c@2000000 { - status = "disabled"; - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2000000 0x0 0x10000>; - interrupts = <0 34 0x4>; /* Level high type */ - clock-names = "i2c"; - clocks = <&clockgen 4 3>; - }; - - i2c1: i2c@2010000 { - status = "disabled"; - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2010000 0x0 0x10000>; - interrupts = <0 34 0x4>; /* Level high type */ - clock-names = "i2c"; - clocks = <&clockgen 4 3>; - }; - - i2c2: i2c@2020000 { - status = "disabled"; - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2020000 0x0 0x10000>; - interrupts = <0 35 0x4>; /* Level high type */ - clock-names = "i2c"; - clocks = <&clockgen 4 3>; - }; - - i2c3: i2c@2030000 { - status = "disabled"; - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2030000 0x0 0x10000>; - interrupts = <0 35 0x4>; /* Level high type */ - clock-names = "i2c"; - clocks = <&clockgen 4 3>; - }; - - ifc: ifc@2240000 { - compatible = "fsl,ifc", "simple-bus"; - reg = <0x0 0x2240000 0x0 0x20000>; - interrupts = <0 21 0x4>; /* Level high type */ - little-endian; - #address-cells = <2>; - #size-cells = <1>; - - ranges = <0 0 0x5 0x80000000 0x08000000 - 2 0 0x5 0x30000000 0x00010000 - 3 0 0x5 0x20000000 0x00010000>; - }; - - qspi: spi@20c0000 { - compatible = "fsl,ls2080a-qspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x20c0000 0x0 0x10000>, - <0x0 0x20000000 0x0 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = ; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - pcie1: pcie@3400000 { - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; - reg-names = "regs", "config"; - interrupts = <0 108 0x4>; /* Level high type */ - interrupt-names = "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <6>; - bus-range = <0x0 0xff>; - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, - <0000 0 0 2 &gic 0 0 0 110 4>, - <0000 0 0 3 &gic 0 0 0 111 4>, - <0000 0 0 4 &gic 0 0 0 112 4>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - pcie2: pcie@3500000 { - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; - reg-names = "regs", "config"; - interrupts = <0 113 0x4>; /* Level high type */ - interrupt-names = "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <6>; - bus-range = <0x0 0xff>; - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, - <0000 0 0 2 &gic 0 0 0 115 4>, - <0000 0 0 3 &gic 0 0 0 116 4>, - <0000 0 0 4 &gic 0 0 0 117 4>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - pcie3: pcie@3600000 { - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; - reg-names = "regs", "config"; - interrupts = <0 118 0x4>; /* Level high type */ - interrupt-names = "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <256>; - bus-range = <0x0 0xff>; - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, - <0000 0 0 2 &gic 0 0 0 120 4>, - <0000 0 0 3 &gic 0 0 0 121 4>, - <0000 0 0 4 &gic 0 0 0 122 4>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - pcie4: pcie@3700000 { - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; - reg-names = "regs", "config"; - interrupts = <0 123 0x4>; /* Level high type */ - interrupt-names = "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <6>; - bus-range = <0x0 0xff>; - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, - <0000 0 0 2 &gic 0 0 0 125 4>, - <0000 0 0 3 &gic 0 0 0 126 4>, - <0000 0 0 4 &gic 0 0 0 127 4>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - sata0: sata@3200000 { - status = "disabled"; - compatible = "fsl,ls2080a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>; - interrupts = <0 133 0x4>; /* Level high type */ - clocks = <&clockgen 4 3>; - dma-coherent; - }; - - sata1: sata@3210000 { - status = "disabled"; - compatible = "fsl,ls2080a-ahci"; - reg = <0x0 0x3210000 0x0 0x10000>; - interrupts = <0 136 0x4>; /* Level high type */ - clocks = <&clockgen 4 3>; - dma-coherent; - }; - - usb0: usb3@3100000 { - status = "disabled"; - compatible = "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <0 80 0x4>; /* Level high type */ - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - usb1: usb3@3110000 { - status = "disabled"; - compatible = "snps,dwc3"; - reg = <0x0 0x3110000 0x0 0x10000>; - interrupts = <0 81 0x4>; /* Level high type */ - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; - - ccn@4000000 { - compatible = "arm,ccn-504"; - reg = <0x0 0x04000000 0x0 0x01000000>; - interrupts = <0 12 4>; - }; - - rcpm: power-controller@1e34040 { - compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+"; - reg = <0x0 0x1e34040 0x0 0x18>; - #fsl,rcpm-wakeup-cells = <6>; - little-endian; - }; - - ftm_alarm0: timer@2800000 { - compatible = "fsl,ls208xa-ftm-alarm"; - reg = <0x0 0x2800000 0x0 0x10000>; - fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; - interrupts = ; - }; - }; - - ddr1: memory-controller@1080000 { - compatible = "fsl,qoriq-memory-controller"; - reg = <0x0 0x1080000 0x0 0x1000>; - interrupts = <0 17 0x4>; - little-endian; - }; - - ddr2: memory-controller@1090000 { - compatible = "fsl,qoriq-memory-controller"; - reg = <0x0 0x1090000 0x0 0x1000>; - interrupts = <0 18 0x4>; - little-endian; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi deleted file mode 100644 index d87d16460..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi +++ /dev/null @@ -1,164 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Device Tree file for LX2160A-CEx7 -// -// Copyright 2019 SolidRun Ltd. - -/dts-v1/; - -#include "fsl-lx2160a.dtsi" - -/ { - model = "SolidRun LX2160A COM Express Type 7 module"; - compatible = "solidrun,lx2160a-cex7", "fsl,lx2160a"; - - aliases { - crypto = &crypto; - }; - - sb_3v3: regulator-sb3v3 { - compatible = "regulator-fixed"; - regulator-name = "RT7290"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&crypto { - status = "okay"; -}; - -&dpmac17 { - phy-handle = <&rgmii_phy1>; - phy-connection-type = "rgmii-id"; -}; - -&emdio1 { - status = "okay"; - - rgmii_phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&esdhc1 { - mmc-hs200-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - i2c-switch@77 { - compatible = "nxp,pca9547"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x77>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - eeprom@50 { - compatible = "atmel,24c512"; - reg = <0x50>; - }; - - eeprom@51 { - compatible = "atmel,spd"; - reg = <0x51>; - }; - - eeprom@53 { - compatible = "atmel,spd"; - reg = <0x53>; - }; - - eeprom@57 { - compatible = "atmel,24c02"; - reg = <0x57>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - fan-temperature-ctrlr@18 { - compatible = "ti,amc6821"; - reg = <0x18>; - cooling-min-state = <0>; - cooling-max-state = <9>; - #cooling-cells = <2>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - regulator@5c { - compatible = "lltc,ltc3882"; - reg = <0x5c>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - temperature-sensor@48 { - compatible = "nxp,sa56004"; - reg = <0x48>; - vcc-supply = <&sb_3v3>; - }; - }; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; - - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - // IRQ10_B - interrupts = ; - }; -}; - -&fspi { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,m25p80"; - m25p,fast-read; - spi-max-frequency = <50000000>; - reg = <0>; - /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */ - spi-rx-bus-width = <8>; - spi-tx-bus-width = <1>; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts deleted file mode 100644 index 86a9b7714..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Device Tree file for LX2160A Clearfog CX board -// -// Copyright 2019 SolidRun Ltd. - -/dts-v1/; - -#include "fsl-lx2160a-clearfog-itx.dtsi" - -/ { - model = "SolidRun LX2160A Clearfog CX"; - compatible = "solidrun,clearfog-cx", - "solidrun,lx2160a-cex7", "fsl,lx2160a"; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi deleted file mode 100644 index f3741a32e..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Device Tree file for LX2160A Clearfog ITX board; this contains the -// common parts shared between the Clearfog CX and Honeycomb builds. -// -// Copyright 2019 SolidRun Ltd. - -/dts-v1/; - -#include "fsl-lx2160a-cex7.dtsi" - -/ { - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&emdio2 { - status = "okay"; -}; - -&esdhc0 { - sd-uhs-sdr104; - sd-uhs-sdr50; - sd-uhs-sdr25; - sd-uhs-sdr12; - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -&sata1 { - status = "okay"; -}; - -&sata2 { - status = "okay"; -}; - -&sata3 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts deleted file mode 100644 index fe19f3009..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Device Tree file for LX2160A Honeycomb board -// -// Copyright 2019 SolidRun Ltd. - -/dts-v1/; - -#include "fsl-lx2160a-clearfog-itx.dtsi" - -/ { - model = "SolidRun LX2160A Honeycomb"; - compatible = "solidrun,honeycomb", - "solidrun,lx2160a-cex7", "fsl,lx2160a"; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts deleted file mode 100644 index 2d1fe6c37..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts +++ /dev/null @@ -1,179 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Device Tree file for LX2160AQDS -// -// Copyright 2018 NXP - -/dts-v1/; - -#include "fsl-lx2160a.dtsi" - -/ { - model = "NXP Layerscape LX2160AQDS"; - compatible = "fsl,lx2160a-qds", "fsl,lx2160a"; - - aliases { - crypto = &crypto; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - sb_3v3: regulator-sb3v3 { - compatible = "regulator-fixed"; - regulator-name = "MC34717-3.3VSB"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&crypto { - status = "okay"; -}; - -&dspi0 { - status = "okay"; - - dflash0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <1000000>; - }; -}; - -&dspi1 { - status = "okay"; - - dflash1: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <1000000>; - }; -}; - -&dspi2 { - status = "okay"; - - dflash2: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <1000000>; - }; -}; - -&esdhc0 { - status = "okay"; -}; - -&esdhc1 { - status = "okay"; -}; - -&fspi { - status = "okay"; - - mt35xu512aba0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - m25p,fast-read; - spi-max-frequency = <50000000>; - reg = <0>; - spi-rx-bus-width = <8>; - spi-tx-bus-width = <8>; - }; -}; - -&i2c0 { - status = "okay"; - - i2c-mux@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - - power-monitor@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <500>; - }; - - power-monitor@41 { - compatible = "ti,ina220"; - reg = <0x41>; - shunt-resistor = <1000>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - temperature-sensor@4c { - compatible = "nxp,sa56004"; - reg = <0x4c>; - vcc-supply = <&sb_3v3>; - }; - - temperature-sensor@4d { - compatible = "nxp,sa56004"; - reg = <0x4d>; - vcc-supply = <&sb_3v3>; - }; - - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - }; - }; - }; -}; - -&sata0 { - status = "okay"; -}; - -&sata1 { - status = "okay"; -}; - -&sata2 { - status = "okay"; -}; - -&sata3 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts deleted file mode 100644 index 54fe8cd3a..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts +++ /dev/null @@ -1,189 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Device Tree file for LX2160ARDB -// -// Copyright 2018 NXP - -/dts-v1/; - -#include "fsl-lx2160a.dtsi" - -/ { - model = "NXP Layerscape LX2160ARDB"; - compatible = "fsl,lx2160a-rdb", "fsl,lx2160a"; - - aliases { - crypto = &crypto; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - sb_3v3: regulator-sb3v3 { - compatible = "regulator-fixed"; - regulator-name = "MC34717-3.3VSB"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&crypto { - status = "okay"; -}; - -&dpmac17 { - phy-handle = <&rgmii_phy1>; - phy-connection-type = "rgmii-id"; -}; - -&dpmac18 { - phy-handle = <&rgmii_phy2>; - phy-connection-type = "rgmii-id"; -}; - -&emdio1 { - status = "okay"; - - rgmii_phy1: ethernet-phy@1 { - /* AR8035 PHY */ - compatible = "ethernet-phy-id004d.d072"; - reg = <0x1>; - eee-broken-1000t; - }; - - rgmii_phy2: ethernet-phy@2 { - /* AR8035 PHY */ - compatible = "ethernet-phy-id004d.d072"; - reg = <0x2>; - eee-broken-1000t; - }; -}; - -&esdhc0 { - sd-uhs-sdr104; - sd-uhs-sdr50; - sd-uhs-sdr25; - sd-uhs-sdr12; - status = "okay"; -}; - -&esdhc1 { - mmc-hs200-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - status = "okay"; -}; - -&fspi { - status = "okay"; - - mt35xu512aba0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - m25p,fast-read; - spi-max-frequency = <50000000>; - reg = <0>; - spi-rx-bus-width = <8>; - spi-tx-bus-width = <8>; - }; - - mt35xu512aba1: flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - m25p,fast-read; - spi-max-frequency = <50000000>; - reg = <1>; - spi-rx-bus-width = <8>; - spi-tx-bus-width = <8>; - }; -}; - -&i2c0 { - status = "okay"; - - i2c-mux@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - - power-monitor@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <500>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - temperature-sensor@4c { - compatible = "nxp,sa56004"; - reg = <0x4c>; - vcc-supply = <&sb_3v3>; - }; - - temperature-sensor@4d { - compatible = "nxp,sa56004"; - reg = <0x4d>; - vcc-supply = <&sb_3v3>; - }; - }; - }; -}; - -&i2c4 { - status = "okay"; - - rtc@51 { - compatible = "nxp,pcf2129"; - reg = <0x51>; - // IRQ10_B - interrupts = <0 150 0x4>; - }; -}; - -&sata0 { - status = "okay"; -}; - -&sata1 { - status = "okay"; -}; - -&sata2 { - status = "okay"; -}; - -&sata3 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi deleted file mode 100644 index 83072da6f..000000000 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ /dev/null @@ -1,1425 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -// -// Device Tree Include file for Layerscape-LX2160A family SoC. -// -// Copyright 2018-2020 NXP - -#include -#include -#include - -/memreserve/ 0x80000000 0x00010000; - -/ { - compatible = "fsl,lx2160a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - rtc1 = &ftm_alarm0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - // 8 clusters having 2 Cortex-A72 cores each - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x0>; - clocks = <&clockgen 1 0>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster0_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x1>; - clocks = <&clockgen 1 0>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster0_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu100: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x100>; - clocks = <&clockgen 1 1>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster1_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu101: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x101>; - clocks = <&clockgen 1 1>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster1_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu200: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x200>; - clocks = <&clockgen 1 2>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster2_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu201: cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x201>; - clocks = <&clockgen 1 2>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster2_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu300: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x300>; - clocks = <&clockgen 1 3>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster3_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu301: cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x301>; - clocks = <&clockgen 1 3>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster3_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu400: cpu@400 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x400>; - clocks = <&clockgen 1 4>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster4_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu401: cpu@401 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x401>; - clocks = <&clockgen 1 4>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster4_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu500: cpu@500 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x500>; - clocks = <&clockgen 1 5>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster5_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu501: cpu@501 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x501>; - clocks = <&clockgen 1 5>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster5_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu600: cpu@600 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x600>; - clocks = <&clockgen 1 6>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster6_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu601: cpu@601 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x601>; - clocks = <&clockgen 1 6>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster6_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu700: cpu@700 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x700>; - clocks = <&clockgen 1 7>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster7_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cpu701: cpu@701 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x701>; - clocks = <&clockgen 1 7>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <192>; - next-level-cache = <&cluster7_l2>; - cpu-idle-states = <&cpu_pw15>; - #cooling-cells = <2>; - }; - - cluster0_l2: l2-cache0 { - compatible = "cache"; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - }; - - cluster1_l2: l2-cache1 { - compatible = "cache"; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - }; - - cluster2_l2: l2-cache2 { - compatible = "cache"; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - }; - - cluster3_l2: l2-cache3 { - compatible = "cache"; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - }; - - cluster4_l2: l2-cache4 { - compatible = "cache"; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - }; - - cluster5_l2: l2-cache5 { - compatible = "cache"; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - }; - - cluster6_l2: l2-cache6 { - compatible = "cache"; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - }; - - cluster7_l2: l2-cache7 { - compatible = "cache"; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - }; - - cpu_pw15: cpu-pw15 { - compatible = "arm,idle-state"; - idle-state-name = "PW15"; - arm,psci-suspend-param = <0x0>; - entry-latency-us = <2000>; - exit-latency-us = <2000>; - min-residency-us = <6000>; - }; - }; - - gic: interrupt-controller@6000000 { - compatible = "arm,gic-v3"; - reg = <0x0 0x06000000 0 0x10000>, // GIC Dist - <0x0 0x06200000 0 0x200000>, // GICR (RD_base + - // SGI_base) - <0x0 0x0c0c0000 0 0x2000>, // GICC - <0x0 0x0c0d0000 0 0x1000>, // GICH - <0x0 0x0c0e0000 0 0x20000>; // GICV - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - interrupts = ; - - its: gic-its@6020000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x0 0x6020000 0 0x20000>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a72-pmu"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - memory@80000000 { - // DRAM space - 1, size : 2 GB DRAM - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x80000000>; - }; - - ddr1: memory-controller@1080000 { - compatible = "fsl,qoriq-memory-controller"; - reg = <0x0 0x1080000 0x0 0x1000>; - interrupts = ; - little-endian; - }; - - ddr2: memory-controller@1090000 { - compatible = "fsl,qoriq-memory-controller"; - reg = <0x0 0x1090000 0x0 0x1000>; - interrupts = ; - little-endian; - }; - - // One clock unit-sysclk node which bootloader require during DT fix-up - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; // fixed up by bootloader - clock-output-names = "sysclk"; - }; - - thermal-zones { - cluster6-7 { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 0>; - - trips { - cluster6_7_alert: cluster6-7-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cluster6_7_crit: cluster6-7-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cluster6_7_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - ddr-cluster5 { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 1>; - - trips { - ddr-cluster5-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - ddr-cluster5-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - wriop { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 2>; - - trips { - wriop-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - wriop-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - dce-qbman-hsio2 { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 3>; - - trips { - dce-qbman-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - dce-qbman-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - ccn-dpaa-tbu { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 4>; - - trips { - ccn-dpaa-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - ccn-dpaa-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cluster4-hsio3 { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 5>; - - trips { - clust4-hsio3-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - clust4-hsio3-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cluster2-3 { - polling-delay-passive = <1000>; - polling-delay = <5000>; - thermal-sensors = <&tmu 6>; - - trips { - cluster2-3-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cluster2-3-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; - - crypto: crypto@8000000 { - compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; - fsl,sec-era = <10>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x00 0x8000000 0x100000>; - reg = <0x00 0x8000000 0x0 0x100000>; - interrupts = ; - dma-coherent; - status = "disabled"; - - sec_jr0: jr@10000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x10000 0x10000>; - interrupts = ; - }; - - sec_jr1: jr@20000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x20000 0x10000>; - interrupts = ; - }; - - sec_jr2: jr@30000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x30000 0x10000>; - interrupts = ; - }; - - sec_jr3: jr@40000 { - compatible = "fsl,sec-v5.0-job-ring", - "fsl,sec-v4.0-job-ring"; - reg = <0x40000 0x10000>; - interrupts = ; - }; - }; - - clockgen: clock-controller@1300000 { - compatible = "fsl,lx2160a-clockgen"; - reg = <0 0x1300000 0 0xa0000>; - #clock-cells = <2>; - clocks = <&sysclk>; - }; - - dcfg: syscon@1e00000 { - compatible = "fsl,lx2160a-dcfg", "syscon"; - reg = <0x0 0x1e00000 0x0 0x10000>; - little-endian; - }; - - tmu: tmu@1f80000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x0 0x1f80000 0x0 0x10000>; - interrupts = ; - fsl,tmu-range = <0x800000e6 0x8001017d>; - fsl,tmu-calibration = - /* Calibration data group 1 */ - <0x00000000 0x00000035 - /* Calibration data group 2 */ - 0x00000001 0x00000154>; - little-endian; - #thermal-sensor-cells = <1>; - }; - - i2c0: i2c@2000000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2000000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 15>; - scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - i2c1: i2c@2010000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2010000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 15>; - status = "disabled"; - }; - - i2c2: i2c@2020000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2020000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 15>; - status = "disabled"; - }; - - i2c3: i2c@2030000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2030000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 15>; - status = "disabled"; - }; - - i2c4: i2c@2040000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2040000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 15>; - scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - i2c5: i2c@2050000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2050000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 15>; - status = "disabled"; - }; - - i2c6: i2c@2060000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2060000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 15>; - status = "disabled"; - }; - - i2c7: i2c@2070000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2070000 0x0 0x10000>; - interrupts = ; - clock-names = "i2c"; - clocks = <&clockgen 4 15>; - status = "disabled"; - }; - - fspi: spi@20c0000 { - compatible = "nxp,lx2160a-fspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x20c0000 0x0 0x10000>, - <0x0 0x20000000 0x0 0x10000000>; - reg-names = "fspi_base", "fspi_mmap"; - interrupts = ; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "fspi_en", "fspi"; - status = "disabled"; - }; - - dspi0: spi@2100000 { - compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 7>; - clock-names = "dspi"; - spi-num-chipselects = <5>; - bus-num = <0>; - status = "disabled"; - }; - - dspi1: spi@2110000 { - compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2110000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 7>; - clock-names = "dspi"; - spi-num-chipselects = <5>; - bus-num = <1>; - status = "disabled"; - }; - - dspi2: spi@2120000 { - compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2120000 0x0 0x10000>; - interrupts = ; - clocks = <&clockgen 4 7>; - clock-names = "dspi"; - spi-num-chipselects = <5>; - bus-num = <2>; - status = "disabled"; - }; - - esdhc0: esdhc@2140000 { - compatible = "fsl,esdhc"; - reg = <0x0 0x2140000 0x0 0x10000>; - interrupts = <0 28 0x4>; /* Level high type */ - clocks = <&clockgen 4 1>; - dma-coherent; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - little-endian; - bus-width = <4>; - status = "disabled"; - }; - - esdhc1: esdhc@2150000 { - compatible = "fsl,esdhc"; - reg = <0x0 0x2150000 0x0 0x10000>; - interrupts = <0 63 0x4>; /* Level high type */ - clocks = <&clockgen 4 1>; - dma-coherent; - voltage-ranges = <1800 1800 3300 3300>; - sdhci,auto-cmd12; - broken-cd; - little-endian; - bus-width = <4>; - status = "disabled"; - }; - - uart0: serial@21c0000 { - compatible = "arm,sbsa-uart","arm,pl011"; - reg = <0x0 0x21c0000 0x0 0x1000>; - interrupts = ; - current-speed = <115200>; - status = "disabled"; - }; - - uart1: serial@21d0000 { - compatible = "arm,sbsa-uart","arm,pl011"; - reg = <0x0 0x21d0000 0x0 0x1000>; - interrupts = ; - current-speed = <115200>; - status = "disabled"; - }; - - uart2: serial@21e0000 { - compatible = "arm,sbsa-uart","arm,pl011"; - reg = <0x0 0x21e0000 0x0 0x1000>; - interrupts = ; - current-speed = <115200>; - status = "disabled"; - }; - - uart3: serial@21f0000 { - compatible = "arm,sbsa-uart","arm,pl011"; - reg = <0x0 0x21f0000 0x0 0x1000>; - interrupts = ; - current-speed = <115200>; - status = "disabled"; - }; - - gpio0: gpio@2300000 { - compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = ; - gpio-controller; - little-endian; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2310000 { - compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = ; - gpio-controller; - little-endian; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2320000 { - compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = ; - gpio-controller; - little-endian; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@2330000 { - compatible = "fsl,qoriq-gpio"; - reg = <0x0 0x2330000 0x0 0x10000>; - interrupts = ; - gpio-controller; - little-endian; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - watchdog@23a0000 { - compatible = "arm,sbsa-gwdt"; - reg = <0x0 0x23a0000 0 0x1000>, - <0x0 0x2390000 0 0x1000>; - interrupts = ; - timeout-sec = <30>; - }; - - rcpm: power-controller@1e34040 { - compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+"; - reg = <0x0 0x1e34040 0x0 0x1c>; - #fsl,rcpm-wakeup-cells = <7>; - little-endian; - }; - - ftm_alarm0: timer@2800000 { - compatible = "fsl,lx2160a-ftm-alarm"; - reg = <0x0 0x2800000 0x0 0x10000>; - fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; - interrupts = ; - }; - - usb0: usb@3100000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - status = "disabled"; - }; - - usb1: usb@3110000 { - compatible = "snps,dwc3"; - reg = <0x0 0x3110000 0x0 0x10000>; - interrupts = ; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - status = "disabled"; - }; - - sata0: sata@3200000 { - compatible = "fsl,lx2160a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000>, - <0x7 0x100520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = ; - clocks = <&clockgen 4 3>; - dma-coherent; - status = "disabled"; - }; - - sata1: sata@3210000 { - compatible = "fsl,lx2160a-ahci"; - reg = <0x0 0x3210000 0x0 0x10000>, - <0x7 0x100520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = ; - clocks = <&clockgen 4 3>; - dma-coherent; - status = "disabled"; - }; - - sata2: sata@3220000 { - compatible = "fsl,lx2160a-ahci"; - reg = <0x0 0x3220000 0x0 0x10000>, - <0x7 0x100520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = ; - clocks = <&clockgen 4 3>; - dma-coherent; - status = "disabled"; - }; - - sata3: sata@3230000 { - compatible = "fsl,lx2160a-ahci"; - reg = <0x0 0x3230000 0x0 0x10000>, - <0x7 0x100520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = ; - clocks = <&clockgen 4 3>; - dma-coherent; - status = "disabled"; - }; - - pcie1: pcie@3400000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "csr_axi_slave", "config_axi_slave"; - interrupts = , /* AER interrupt */ - , /* PME interrupt */ - ; /* controller interrupt */ - interrupt-names = "aer", "pme", "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - apio-wins = <8>; - ppio-wins = <8>; - bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - pcie2: pcie@3500000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "csr_axi_slave", "config_axi_slave"; - interrupts = , /* AER interrupt */ - , /* PME interrupt */ - ; /* controller interrupt */ - interrupt-names = "aer", "pme", "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - apio-wins = <8>; - ppio-wins = <8>; - bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - pcie3: pcie@3600000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x90 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "csr_axi_slave", "config_axi_slave"; - interrupts = , /* AER interrupt */ - , /* PME interrupt */ - ; /* controller interrupt */ - interrupt-names = "aer", "pme", "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - apio-wins = <256>; - ppio-wins = <24>; - bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - pcie4: pcie@3700000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ - 0x98 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "csr_axi_slave", "config_axi_slave"; - interrupts = , /* AER interrupt */ - , /* PME interrupt */ - ; /* controller interrupt */ - interrupt-names = "aer", "pme", "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - apio-wins = <8>; - ppio-wins = <8>; - bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - pcie5: pcie@3800000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ - 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "csr_axi_slave", "config_axi_slave"; - interrupts = , /* AER interrupt */ - , /* PME interrupt */ - ; /* controller interrupt */ - interrupt-names = "aer", "pme", "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - apio-wins = <256>; - ppio-wins = <24>; - bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - pcie6: pcie@3900000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ - 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "csr_axi_slave", "config_axi_slave"; - interrupts = , /* AER interrupt */ - , /* PME interrupt */ - ; /* controller interrupt */ - interrupt-names = "aer", "pme", "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - apio-wins = <8>; - ppio-wins = <8>; - bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - smmu: iommu@5000000 { - compatible = "arm,mmu-500"; - reg = <0 0x5000000 0 0x800000>; - #iommu-cells = <1>; - #global-interrupts = <14>; - // global secure fault - interrupts = , - // combined secure - , - // global non-secure fault - , - // combined non-secure - , - // performance counter interrupts 0-9 - , - , - , - , - , - , - , - , - , - , - // per context interrupt, 64 interrupts - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - dma-coherent; - }; - - console@8340020 { - compatible = "fsl,dpaa2-console"; - reg = <0x00000000 0x08340020 0 0x2>; - }; - - ptp-timer@8b95000 { - compatible = "fsl,dpaa2-ptp"; - reg = <0x0 0x8b95000 0x0 0x100>; - clocks = <&clockgen 4 1>; - little-endian; - fsl,extts-fifo; - }; - - /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ - emdio1: mdio@8b96000 { - compatible = "fsl,fman-memac-mdio"; - reg = <0x0 0x8b96000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - little-endian; - status = "disabled"; - }; - - emdio2: mdio@8b97000 { - compatible = "fsl,fman-memac-mdio"; - reg = <0x0 0x8b97000 0x0 0x1000>; - interrupts = ; - little-endian; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - fsl_mc: fsl-mc@80c000000 { - compatible = "fsl,qoriq-mc"; - reg = <0x00000008 0x0c000000 0 0x40>, - <0x00000000 0x08340000 0 0x40000>; - msi-parent = <&its>; - /* iommu-map property is fixed up by u-boot */ - iommu-map = <0 &smmu 0 0>; - dma-coherent; - #address-cells = <3>; - #size-cells = <1>; - - /* - * Region type 0x0 - MC portals - * Region type 0x1 - QBMAN portals - */ - ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 - 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; - - /* - * Define the maximum number of MACs present on the SoC. - */ - dpmacs { - #address-cells = <1>; - #size-cells = <0>; - - dpmac1: dpmac@1 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x1>; - }; - - dpmac2: dpmac@2 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x2>; - }; - - dpmac3: dpmac@3 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x3>; - }; - - dpmac4: dpmac@4 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x4>; - }; - - dpmac5: dpmac@5 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x5>; - }; - - dpmac6: dpmac@6 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x6>; - }; - - dpmac7: dpmac@7 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x7>; - }; - - dpmac8: dpmac@8 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x8>; - }; - - dpmac9: dpmac@9 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x9>; - }; - - dpmac10: dpmac@a { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xa>; - }; - - dpmac11: dpmac@b { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xb>; - }; - - dpmac12: dpmac@c { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xc>; - }; - - dpmac13: dpmac@d { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xd>; - }; - - dpmac14: dpmac@e { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xe>; - }; - - dpmac15: dpmac@f { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0xf>; - }; - - dpmac16: dpmac@10 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x10>; - }; - - dpmac17: dpmac@11 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x11>; - }; - - dpmac18: dpmac@12 { - compatible = "fsl,qoriq-mc-dpmac"; - reg = <0x12>; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi deleted file mode 100644 index d6b9dedd1..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi +++ /dev/null @@ -1,285 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2020 Compass Electronics Group, LLC - */ - -/ { - leds { - compatible = "gpio-leds"; - - led0 { - label = "gen_led0"; - gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led1 { - label = "gen_led1"; - gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led2 { - label = "gen_led2"; - gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led3>; - label = "heartbeat"; - gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_audio: regulator-audio { - compatible = "regulator-fixed"; - regulator-name = "3v3_aud"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx-audio-wm8962"; - model = "wm8962-audio"; - audio-cpu = <&sai3>; - audio-codec = <&wm8962>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC"; - }; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_espi2>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - status = "okay"; - - eeprom@0 { - compatible = "microchip,at25160bn", "atmel,at25"; - reg = <0>; - spi-max-frequency = <5000000>; - spi-cpha; - spi-cpol; - pagesize = <32>; - size = <2048>; - address-width = <16>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - wm8962: audio-codec@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; - clock-names = "xclk"; - DCVDD-supply = <®_audio>; - DBVDD-supply = <®_audio>; - AVDD-supply = <®_audio>; - CPVDD-supply = <®_audio>; - MICVDD-supply = <®_audio>; - PLLVDD-supply = <®_audio>; - SPKVDD1-supply = <®_audio>; - SPKVDD2-supply = <®_audio>; - gpio-cfg = < - 0x0000 /* 0:Default */ - 0x0000 /* 1:Default */ - 0x0000 /* 2:FN_DMICCLK */ - 0x0000 /* 3:Default */ - 0x0000 /* 4:FN_DMICCDAT */ - 0x0000 /* 5:Default */ - >; - }; - - pca6416_0: gpio@20 { - compatible = "nxp,pcal6416"; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcal6414>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - }; - - pca6416_1: gpio@21 { - compatible = "nxp,pcal6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MM_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart2 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clk IMX8MM_CLK_UART3>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&iomuxc { - pinctrl_espi2: espi2grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 - >; - }; - - pinctrl_led3: led3grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41 - >; - }; - - pinctrl_pcal6414: pcal6414-gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40 - MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41 - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts deleted file mode 100644 index 74a7b0cc1..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2020 Compass Electronics Group, LLC - */ - -/dts-v1/; - -#include "imx8mm.dtsi" -#include "imx8mm-beacon-som.dtsi" -#include "imx8mm-beacon-baseboard.dtsi" - -/ { - model = "Beacon EmbeddedWorks i.MX8M Mini Development Kit"; - compatible = "beacon,imx8mm-beacon-kit", "fsl,imx8mm"; - - chosen { - stdout-path = &uart2; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi deleted file mode 100644 index b88c3c99b..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ /dev/null @@ -1,412 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2020 Compass Electronics Group, LLC - */ - -/ { - usdhc1_pwrseq: usdhc1_pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1_gpio>; - reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; - clocks = <&osc_32k>; - clock-names = "ext_clock"; - post-power-on-delay-ms = <80>; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - // BUCK6 in datasheet - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - // BUCK7 in datasheet - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - // BUCK8 in datasheet - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - eeprom@50 { - compatible = "microchip,24c64", "atmel,24c64"; - pagesize = <32>; - read-only; /* Manufacturing EEPROM programmed at factory */ - reg = <0x50>; - }; - - rtc@51 { - compatible = "nxp,pcf85263"; - reg = <0x51>; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clk IMX8MM_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; - clocks = <&osc_32k>; - max-speed = <4000000>; - clock-names = "extclk"; - }; -}; - -&usdhc1 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - non-removable; - cap-power-off-card; - pm-ignore-notify; - keep-power-in-suspend; - mmc-pwrseq = <&usdhc1_pwrseq>; - status = "okay"; - - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan>; - interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - }; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 - MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 - MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 - MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 - MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 - >; - }; - - pinctrl_usdhc1_gpio: usdhc1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; - - pinctrl_wlan: wlangrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts deleted file mode 100644 index 6c079c0a3..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2020 NXP - */ - -/dts-v1/; - -#include "imx8mm-evk.dtsi" - -/ { - model = "FSL i.MX8MM DDR4 EVK with CYW43455 WIFI/BT board"; - compatible = "fsl,imx8mm-ddr4-evk", "fsl,imx8mm"; - - leds { - pinctrl-0 = <&pinctrl_gpio_led_2>; - - status { - gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "okay"; -}; - -&iomuxc { - pinctrl_gpmi_nand: gpmi-nand { - fsl,pins = < - MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 - MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 - MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x00000096 - MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 - MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 - MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 - MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 - MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 - MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 - MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 - MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 - MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 - MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 - MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 - MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 - MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 - >; - }; - - pinctrl_gpio_led_2: gpioled2grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts deleted file mode 100644 index 4e2820d19..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019-2020 NXP - */ - -/dts-v1/; - -#include -#include "imx8mm-evk.dtsi" - -/ { - model = "FSL i.MX8MM EVK board"; - compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; - - aliases { - spi0 = &flexspi; - }; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi>; - status = "okay"; - - flash@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <80000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -}; - -&usdhc3 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&iomuxc { - pinctrl_flexspi: flexspigrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 - MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi deleted file mode 100644 index 521eb3a5a..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ /dev/null @@ -1,475 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2020 NXP - */ - -/dts-v1/; - -#include -#include "imx8mm.dtsi" - -/ { - chosen { - stdout-path = &uart2; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; - - status { - label = "status"; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - wm8524: audio-codec { - #sound-dai-cells = <0>; - compatible = "wlf,wm8524"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_wlf>; - wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; - }; - - sound-wm8524 { - compatible = "simple-audio-card"; - simple-audio-card,name = "wm8524-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&cpudai>; - simple-audio-card,bitclock-master = <&cpudai>; - simple-audio-card,widgets = - "Line", "Left Line Out Jack", - "Line", "Right Line Out Jack"; - simple-audio-card,routing = - "Left Line Out Jack", "LINEVOUTL", - "Right Line Out Jack", "LINEVOUTR"; - - cpudai: simple-audio-card,cpu { - sound-dai = <&sai3>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <32>; - }; - - simple-audio-card,codec { - sound-dai = <&wm8524>; - clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; - }; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - // BUCK6 in datasheet - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - // BUCK7 in datasheet - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - // BUCK8 in datasheet - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ptn5110: tcpc@50 { - compatible = "nxp,ptn5110"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_typec1>; - reg = <0x50>; - interrupt-parent = <&gpio2>; - interrupts = <11 8>; - status = "okay"; - - port { - typec1_dr_sw: endpoint { - remote-endpoint = <&usb1_drd_sw>; - }; - }; - - typec1_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "dual"; - data-role = "dual"; - try-power-role = "sink"; - source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <15000000>; - self-powered; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - pca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MM_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart2 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - usb-role-switch; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - status = "okay"; - - port { - usb1_drd_sw: endpoint { - remote-endpoint = <&typec1_dr_sw>; - }; - }; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 - >; - }; - - pinctrl_gpio_wlf: gpiowlfgrp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - >; - }; - - pinctrl_typec1: typec1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h deleted file mode 100644 index a003e6af3..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h +++ /dev/null @@ -1,645 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017-2018 NXP - */ - -#ifndef __DTS_IMX8MM_PINFUNC_H -#define __DTS_IMX8MM_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ - -#define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 -#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 -#define MX8MM_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 -#define MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x0FC 0x364 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x100 0x368 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x104 0x36C 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x108 0x370 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x11C 0x384 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x120 0x388 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x124 0x38C 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x128 0x390 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 -#define MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x130 0x398 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x138 0x3A0 0x000 0x12 0x0 -#define MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x13C 0x3A4 0x000 0x2 0x0 -#define MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 -#define MX8MM_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 -#define MX8MM_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0x144 0x3AC 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 -#define MX8MM_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0x148 0x3B0 0x534 0x4 0x0 -#define MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 -#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0 -#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 -#define MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0x14C 0x3B4 0x538 0x4 0x0 -#define MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 -#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1 -#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 -#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0x150 0x3B8 0x53c 0x4 0x0 -#define MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 -#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2 -#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 -#define MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0x154 0x3BC 0x540 0x4 0x0 -#define MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0 -#define MX8MM_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0 -#define MX8MM_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0 -#define MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_RXD0_PDM_DATA0 0x164 0x3CC 0x534 0x3 0x1 -#define MX8MM_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_RXD1_PDM_DATA1 0x168 0x3D0 0x538 0x3 0x1 -#define MX8MM_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_RXD2_PDM_DATA2 0x16C 0x3D4 0x53C 0x3 0x1 -#define MX8MM_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1 -#define MX8MM_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_RXD3_PDM_DATA3 0x170 0x3D8 0x540 0x3 0x1 -#define MX8MM_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0 -#define MX8MM_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0 -#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1 -#define MX8MM_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0 -#define MX8MM_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4 -#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0 -#define MX8MM_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3 -#define MX8MM_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1 -#define MX8MM_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1 -#define MX8MM_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0 -#define MX8MM_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1 -#define MX8MM_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_TXD7_PDM_CLK 0x1A8 0x410 0x000 0x3 0x0 -#define MX8MM_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0 -#define MX8MM_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1 -#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2 -#define MX8MM_IOMUXC_SAI1_MCLK_PDM_CLK 0x1AC 0x414 0x000 0x3 0x0 -#define MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 -#define MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1B0 0x418 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI2_RXFS_UART1_DTE_RX 0x1B0 0x418 0x4F4 0x4 0x2 -#define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 -#define MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1B4 0x41C 0x4F4 0x4 0x3 -#define MX8MM_IOMUXC_SAI2_RXC_UART1_DTE_TX 0x1B4 0x41C 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x1B8 0x420 0x4F0 0x4 0x2 -#define MX8MM_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B 0x1B8 0x420 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x1BC 0x424 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B 0x1BC 0x424 0x4F0 0x4 0x3 -#define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2 -#define MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 -#define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CLK 0x1D0 0x438 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 -#define MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1D0 0x438 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x1D0 0x438 0x4F8 0x4 0x2 -#define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 -#define MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1D4 0x43C 0x4F8 0x4 0x3 -#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x1D4 0x43C 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 -#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4Fc 0x4 0x2 -#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x1D8 0x440 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 -#define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1DC 0x444 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4Fc 0x4 0x3 -#define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2 -#define MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3 -#define MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0 -#define MX8MM_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 -#define MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 -#define MX8MM_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 -#define MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 -#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 -#define MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0 -#define MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0 -#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 -#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 -#define MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 -#define MX8MM_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 -#define MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 -#define MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 -#define MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 -#define MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 -#define MX8MM_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 -#define MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 -#define MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x12 0x0 -#define MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 -#define MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 -#define MX8MM_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 -#define MX8MM_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0 -#define MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 -#define MX8MM_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 -#define MX8MM_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0 -#define MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 -#define MX8MM_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 -#define MX8MM_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 -#define MX8MM_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 -#define MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 -#define MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 -#define MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 -#define MX8MM_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 -#define MX8MM_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1 -#define MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0 -#define MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 -#define MX8MM_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 -#define MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 -#define MX8MM_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 -#define MX8MM_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1 -#define MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 -#define MX8MM_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0 - -#endif /* __DTS_IMX8MM_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts deleted file mode 100644 index ac1fe1530..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ /dev/null @@ -1,255 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2020 Krzysztof Kozlowski - */ - -/dts-v1/; - -#include "imx8mm-var-som.dtsi" - -/ { - model = "Variscite VAR-SOM-MX8MM Symphony evaluation board"; - compatible = "variscite,var-som-mx8mm-symphony", "variscite,var-som-mx8mm", "fsl,imx8mm"; - - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb_otg2_vbus>; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - gpio-keys { - compatible = "gpio-keys"; - - back { - label = "Back"; - gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - home { - label = "Home"; - gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - menu { - label = "Menu"; - gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - led { - label = "Heartbeat"; - gpios = <&pca9534 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -ðphy { - reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pca9534: gpio@20 { - compatible = "nxp,pca9534"; - reg = <0x20>; - gpio-controller; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pca9534>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - #gpio-cells = <2>; - wakeup-source; - - /* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */ - usb3-sata-sel-hog { - gpio-hog; - gpios = <4 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "usb3_sata_sel"; - }; - - som-vselect-hog { - gpio-hog; - gpios = <6 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "som_vselect"; - }; - - enet-sel-hog { - gpio-hog; - gpios = <7 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "enet_sel"; - }; - }; - - extcon_usbotg1: typec@3d { - compatible = "nxp,ptn5150"; - reg = <0x3d>; - interrupt-parent = <&gpio1>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ptn5150>; - status = "okay"; - }; -}; - -&i2c3 { - /* Capacitive touch controller */ - ft5x06_ts: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_captouch>; - interrupt-parent = <&gpio5>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; - - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - touchscreen-inverted-x; - touchscreen-inverted-y; - }; - - rtc@68 { - compatible = "dallas,ds1337"; - reg = <0x68>; - }; -}; - -/* Header */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* Header */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbotg1 { - disable-over-current; - extcon = <&extcon_usbotg1>, <&extcon_usbotg1>; -}; - -&usbotg2 { - dr_mode = "host"; - vbus-supply = <®_usb_otg2_vbus>; - srp-disable; - hnp-disable; - adp-disable; - disable-over-current; - /delete-property/ usb-role-switch; - /* - * FIXME: having USB2 enabled hangs the boot just after: - * [ 1.943365] ci_hdrc ci_hdrc.1: EHCI Host Controller - * [ 1.948287] ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 1 - * [ 1.971006] ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00 - * [ 1.977203] hub 1-0:1.0: USB hub found - * [ 1.980987] hub 1-0:1.0: 1 port detected - */ - status = "disabled"; -}; - -&pinctrl_fec1 { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */ - >; -}; - -&iomuxc { - pinctrl_captouch: captouchgrp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_pca9534: pca9534grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 - >; - }; - - pinctrl_ptn5150: ptn5150grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16 - >; - }; - - pinctrl_reg_usb_otg2_vbus: regusbotg2vbusgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x16 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi deleted file mode 100644 index 0fac1f3f7..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi +++ /dev/null @@ -1,558 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - * Copyright (C) 2020 Krzysztof Kozlowski - */ - -#include "imx8mm.dtsi" - -/ { - model = "Variscite VAR-SOM-MX8MM module"; - compatible = "variscite,var-som-mx8mm", "fsl,imx8mm"; - - chosen { - stdout-path = &uart4; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - reg_eth_phy: regulator-eth-phy { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_eth_phy>; - regulator-name = "eth_phy_pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>, - <&gpio1 0 GPIO_ACTIVE_LOW>; - /delete-property/ dmas; - /delete-property/ dma-names; - status = "okay"; - - /* Resistive touch controller */ - touchscreen@0 { - reg = <0>; - compatible = "ti,ads7846"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_restouch>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - - spi-max-frequency = <1500000>; - pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; - - ti,x-min = /bits/ 16 <125>; - touchscreen-size-x = <4008>; - ti,y-min = /bits/ 16 <282>; - touchscreen-size-y = <3864>; - ti,x-plate-ohms = /bits/ 16 <180>; - touchscreen-max-pressure = <255>; - touchscreen-average-samples = <10>; - ti,debounce-tol = /bits/ 16 <3>; - ti,debounce-rep = /bits/ 16 <1>; - ti,settle-delay-usec = /bits/ 16 <150>; - ti,keep-vref-on; - wakeup-source; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii"; - phy-handle = <ðphy>; - phy-supply = <®_eth_phy>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@4 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <4>; - reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <10000>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio2>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - buck3_reg: BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5_reg: LDO5 { - regulator-compatible = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - /* TODO: configure audio, as of now just put a placeholder */ - wm8904: codec@1a { - compatible = "wlf,wm8904"; - reg = <0x1a>; - status = "disabled"; - }; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -/* Bluetooth */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - assigned-clocks = <&clk IMX8MM_CLK_UART2>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; - uart-has-rtscts; - status = "okay"; -}; - -/* Console */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - usb-role-switch; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "otg"; - usb-role-switch; - status = "okay"; -}; - -/* WIFI */ -&usdhc1 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <4>; - non-removable; - keep-power-in-suspend; - status = "okay"; - - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD */ -&usdhc2 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13 - MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13 - MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13 - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13 - MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141 - >; - }; - - pinctrl_reg_eth_phy: regethphygrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 - >; - }; - - pinctrl_restouch: restouchgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 - MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 - MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xc1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi deleted file mode 100644 index f4d7bb757..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ /dev/null @@ -1,983 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - */ - -#include -#include -#include -#include -#include - -#include "imx8mm-pinfunc.h" - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet0 = &fec1; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - idle-states { - entry-method = "psci"; - - cpu_pd_wait: cpu-pd-wait { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010033>; - local-timer-stop; - entry-latency-us = <1000>; - exit-latency-us = <700>; - min-residency-us = <2700>; - }; - }; - - A53_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MM_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - nvmem-cells = <&cpu_speed_grade>; - nvmem-cell-names = "speed_grade"; - cpu-idle-states = <&cpu_pd_wait>; - #cooling-cells = <2>; - }; - - A53_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MM_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - cpu-idle-states = <&cpu_pd_wait>; - #cooling-cells = <2>; - }; - - A53_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x2>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MM_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - cpu-idle-states = <&cpu_pd_wait>; - #cooling-cells = <2>; - }; - - A53_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x3>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MM_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - cpu-idle-states = <&cpu_pd_wait>; - #cooling-cells = <2>; - }; - - A53_L2: l2-cache0 { - compatible = "cache"; - }; - }; - - a53_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <850000>; - opp-supported-hw = <0xe>, <0x7>; - clock-latency-ns = <150000>; - opp-suspend; - }; - - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <950000>; - opp-supported-hw = <0xc>, <0x7>; - clock-latency-ns = <150000>; - opp-suspend; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1000000>; - opp-supported-hw = <0x8>, <0x3>; - clock-latency-ns = <150000>; - opp-suspend; - }; - }; - - osc_32k: clock-osc-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "osc_32k"; - }; - - osc_24m: clock-osc-24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc_24m"; - }; - - clk_ext1: clock-ext1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext1"; - }; - - clk_ext2: clock-ext2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext2"; - }; - - clk_ext3: clock-ext3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext3"; - }; - - clk_ext4: clock-ext4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency= <133000000>; - clock-output-names = "clk_ext4"; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , /* Physical Secure */ - , /* Physical Non-Secure */ - , /* Virtual */ - ; /* Hypervisor */ - clock-frequency = <8000000>; - arm,no-tick-in-suspend; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu>; - trips { - cpu_alert0: trip0 { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit0: trip1 { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; - assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; - clock-names = "main_clk"; - }; - - usbphynop2: usbphynop2 { - compatible = "usb-nop-xceiv"; - clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; - assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; - clock-names = "main_clk"; - }; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x3e000000>; - - aips1: bus@30000000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x30000000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x30000000 0x30000000 0x400000>; - - sai1: sai@30010000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30010000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI1_IPG>, - <&clk IMX8MM_CLK_SAI1_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai2: sai@30020000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30020000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI2_IPG>, - <&clk IMX8MM_CLK_SAI2_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai3: sai@30030000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30030000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI3_IPG>, - <&clk IMX8MM_CLK_SAI3_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai5: sai@30050000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30050000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI5_IPG>, - <&clk IMX8MM_CLK_SAI5_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai6: sai@30060000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; - reg = <0x30060000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI6_IPG>, - <&clk IMX8MM_CLK_SAI6_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - gpio1: gpio@30200000 { - compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; - reg = <0x30200000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 10 30>; - }; - - gpio2: gpio@30210000 { - compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; - reg = <0x30210000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 40 21>; - }; - - gpio3: gpio@30220000 { - compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; - reg = <0x30220000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 61 26>; - }; - - gpio4: gpio@30230000 { - compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; - reg = <0x30230000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 87 32>; - }; - - gpio5: gpio@30240000 { - compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; - reg = <0x30240000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 119 30>; - }; - - tmu: tmu@30260000 { - compatible = "fsl,imx8mm-tmu"; - reg = <0x30260000 0x10000>; - clocks = <&clk IMX8MM_CLK_TMU_ROOT>; - #thermal-sensor-cells = <0>; - }; - - wdog1: watchdog@30280000 { - compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; - reg = <0x30280000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>; - status = "disabled"; - }; - - wdog2: watchdog@30290000 { - compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; - reg = <0x30290000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>; - status = "disabled"; - }; - - wdog3: watchdog@302a0000 { - compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; - reg = <0x302a0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>; - status = "disabled"; - }; - - sdma2: dma-controller@302c0000 { - compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; - reg = <0x302c0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, - <&clk IMX8MM_CLK_SDMA2_ROOT>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - sdma3: dma-controller@302b0000 { - compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; - reg = <0x302b0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, - <&clk IMX8MM_CLK_SDMA3_ROOT>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - iomuxc: pinctrl@30330000 { - compatible = "fsl,imx8mm-iomuxc"; - reg = <0x30330000 0x10000>; - }; - - gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; - reg = <0x30340000 0x10000>; - }; - - ocotp: efuse@30350000 { - compatible = "fsl,imx8mm-ocotp", "syscon"; - reg = <0x30350000 0x10000>; - clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; - /* For nvmem subnodes */ - #address-cells = <1>; - #size-cells = <1>; - - cpu_speed_grade: speed-grade@10 { - reg = <0x10 4>; - }; - }; - - anatop: anatop@30360000 { - compatible = "fsl,imx8mm-anatop", "syscon"; - reg = <0x30360000 0x10000>; - }; - - snvs: snvs@30370000 { - compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; - reg = <0x30370000 0x10000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = , - ; - clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; - clock-names = "snvs-rtc"; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; - clock-names = "snvs-pwrkey"; - linux,keycode = ; - wakeup-source; - status = "disabled"; - }; - }; - - clk: clock-controller@30380000 { - compatible = "fsl,imx8mm-ccm"; - reg = <0x30380000 0x10000>; - #clock-cells = <1>; - clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; - clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; - assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>, - <&clk IMX8MM_CLK_A53_CORE>, - <&clk IMX8MM_CLK_NOC>, - <&clk IMX8MM_CLK_AUDIO_AHB>, - <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, - <&clk IMX8MM_SYS_PLL3>, - <&clk IMX8MM_VIDEO_PLL1>, - <&clk IMX8MM_AUDIO_PLL1>, - <&clk IMX8MM_AUDIO_PLL2>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, - <&clk IMX8MM_ARM_PLL_OUT>, - <&clk IMX8MM_SYS_PLL3_OUT>, - <&clk IMX8MM_SYS_PLL1_800M>; - assigned-clock-rates = <0>, <0>, <0>, - <400000000>, - <400000000>, - <750000000>, - <594000000>, - <393216000>, - <361267200>; - }; - - src: reset-controller@30390000 { - compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"; - reg = <0x30390000 0x10000>; - interrupts = ; - #reset-cells = <1>; - }; - }; - - aips2: bus@30400000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x30400000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x30400000 0x30400000 0x400000>; - - pwm1: pwm@30660000 { - compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; - reg = <0x30660000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_PWM1_ROOT>, - <&clk IMX8MM_CLK_PWM1_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@30670000 { - compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; - reg = <0x30670000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_PWM2_ROOT>, - <&clk IMX8MM_CLK_PWM2_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@30680000 { - compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; - reg = <0x30680000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_PWM3_ROOT>, - <&clk IMX8MM_CLK_PWM3_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@30690000 { - compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; - reg = <0x30690000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_PWM4_ROOT>, - <&clk IMX8MM_CLK_PWM4_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - system_counter: timer@306a0000 { - compatible = "nxp,sysctr-timer"; - reg = <0x306a0000 0x20000>; - interrupts = ; - clocks = <&osc_24m>; - clock-names = "per"; - }; - }; - - aips3: bus@30800000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x30800000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x30800000 0x30800000 0x400000>, - <0x8000000 0x8000000 0x10000000>; - - ecspi1: spi@30820000 { - compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30820000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, - <&clk IMX8MM_CLK_ECSPI1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi2: spi@30830000 { - compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30830000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, - <&clk IMX8MM_CLK_ECSPI2_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi3: spi@30840000 { - compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30840000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, - <&clk IMX8MM_CLK_ECSPI3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@30860000 { - compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_UART1_ROOT>, - <&clk IMX8MM_CLK_UART1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart3: serial@30880000 { - compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_UART3_ROOT>, - <&clk IMX8MM_CLK_UART3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: serial@30890000 { - compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_UART2_ROOT>, - <&clk IMX8MM_CLK_UART2_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - crypto: crypto@30900000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30900000 0x40000>; - ranges = <0 0x30900000 0x40000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_AHB>, - <&clk IMX8MM_CLK_IPG_ROOT>; - clock-names = "aclk", "ipg"; - - sec_jr0: jr@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - sec_jr1: jr@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = ; - }; - - sec_jr2: jr@3000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x3000 0x1000>; - interrupts = ; - }; - }; - - i2c1: i2c@30a20000 { - compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30a20000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_I2C1_ROOT>; - status = "disabled"; - }; - - i2c2: i2c@30a30000 { - compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30a30000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_I2C2_ROOT>; - status = "disabled"; - }; - - i2c3: i2c@30a40000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; - reg = <0x30a40000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_I2C3_ROOT>; - status = "disabled"; - }; - - i2c4: i2c@30a50000 { - compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30a50000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_I2C4_ROOT>; - status = "disabled"; - }; - - uart4: serial@30a60000 { - compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; - reg = <0x30a60000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_UART4_ROOT>, - <&clk IMX8MM_CLK_UART4_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - mu: mailbox@30aa0000 { - compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu"; - reg = <0x30aa0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_MU_ROOT>; - #mbox-cells = <2>; - }; - - usdhc1: mmc@30b40000 { - compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; - reg = <0x30b40000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_IPG_ROOT>, - <&clk IMX8MM_CLK_NAND_USDHC_BUS>, - <&clk IMX8MM_CLK_USDHC1_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: mmc@30b50000 { - compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; - reg = <0x30b50000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_IPG_ROOT>, - <&clk IMX8MM_CLK_NAND_USDHC_BUS>, - <&clk IMX8MM_CLK_USDHC2_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - bus-width = <4>; - status = "disabled"; - }; - - usdhc3: mmc@30b60000 { - compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; - reg = <0x30b60000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_IPG_ROOT>, - <&clk IMX8MM_CLK_NAND_USDHC_BUS>, - <&clk IMX8MM_CLK_USDHC3_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - bus-width = <4>; - status = "disabled"; - }; - - flexspi: spi@30bb0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nxp,imx8mm-fspi"; - reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; - reg-names = "fspi_base", "fspi_mmap"; - interrupts = ; - clocks = <&clk IMX8MM_CLK_QSPI_ROOT>, - <&clk IMX8MM_CLK_QSPI_ROOT>; - clock-names = "fspi", "fspi_en"; - status = "disabled"; - }; - - sdma1: dma-controller@30bd0000 { - compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; - reg = <0x30bd0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, - <&clk IMX8MM_CLK_AHB>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - fec1: ethernet@30be0000 { - compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec"; - reg = <0x30be0000 0x10000>; - interrupts = , - , - , - ; - clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, - <&clk IMX8MM_CLK_ENET1_ROOT>, - <&clk IMX8MM_CLK_ENET_TIMER>, - <&clk IMX8MM_CLK_ENET_REF>, - <&clk IMX8MM_CLK_ENET_PHY_REF>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, - <&clk IMX8MM_CLK_ENET_TIMER>, - <&clk IMX8MM_CLK_ENET_REF>, - <&clk IMX8MM_CLK_ENET_PHY_REF>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, - <&clk IMX8MM_SYS_PLL2_100M>, - <&clk IMX8MM_SYS_PLL2_125M>, - <&clk IMX8MM_SYS_PLL2_50M>; - assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; - status = "disabled"; - }; - - }; - - aips4: bus@32c00000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x32c00000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x32c00000 0x32c00000 0x400000>; - - usbotg1: usb@32e40000 { - compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; - reg = <0x32e40000 0x200>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; - clock-names = "usb1_ctrl_root_clk"; - assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; - fsl,usbphy = <&usbphynop1>; - fsl,usbmisc = <&usbmisc1 0>; - status = "disabled"; - }; - - usbmisc1: usbmisc@32e40200 { - compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; - #index-cells = <1>; - reg = <0x32e40200 0x200>; - }; - - usbotg2: usb@32e50000 { - compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; - reg = <0x32e50000 0x200>; - interrupts = ; - clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; - clock-names = "usb1_ctrl_root_clk"; - assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; - fsl,usbphy = <&usbphynop2>; - fsl,usbmisc = <&usbmisc2 0>; - status = "disabled"; - }; - - usbmisc2: usbmisc@32e50200 { - compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; - #index-cells = <1>; - reg = <0x32e50200 0x200>; - }; - - }; - - dma_apbh: dma-controller@33000000 { - compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; - reg = <0x33000000 0x2000>; - interrupts = , - , - , - ; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; - #dma-cells = <1>; - dma-channels = <4>; - clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; - }; - - gpmi: nand-controller@33002000{ - compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x33002000 0x2000>, <0x33004000 0x4000>; - reg-names = "gpmi-nand", "bch"; - interrupts = ; - interrupt-names = "bch"; - clocks = <&clk IMX8MM_CLK_NAND_ROOT>, - <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; - clock-names = "gpmi_io", "gpmi_bch_apb"; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - gic: interrupt-controller@38800000 { - compatible = "arm,gic-v3"; - reg = <0x38800000 0x10000>, /* GIC Dist */ - <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - }; - - ddrc: memory-controller@3d400000 { - compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; - reg = <0x3d400000 0x400000>; - clock-names = "core", "pll", "alt", "apb"; - clocks = <&clk IMX8MM_CLK_DRAM_CORE>, - <&clk IMX8MM_DRAM_PLL>, - <&clk IMX8MM_CLK_DRAM_ALT>, - <&clk IMX8MM_CLK_DRAM_APB>; - }; - - ddr-pmu@3d800000 { - compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; - reg = <0x3d800000 0x400000>; - interrupts = ; - }; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts deleted file mode 100644 index d8ce217c6..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts +++ /dev/null @@ -1,160 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - */ - -/dts-v1/; - -#include "imx8mn.dtsi" -#include "imx8mn-evk.dtsi" - -/ { - model = "NXP i.MX8MNano DDR4 EVK board"; - compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn"; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-600M { - opp-hz = /bits/ 64 <600000000>; - }; - }; -}; - -&i2c1 { - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - }; - - buck4_reg: BUCK4 { - // BUCK6 in datasheet - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - // BUCK7 in datasheet - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - // BUCK8 in datasheet - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts deleted file mode 100644 index 8311b95de..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - */ - -/dts-v1/; - -#include "imx8mn.dtsi" -#include "imx8mn-evk.dtsi" -#include - -/ { - model = "NXP i.MX8MNano EVK board"; - compatible = "fsl,imx8mn-evk", "fsl,imx8mn"; -}; - -&i2c1 { - pmic: pmic@25 { - compatible = "nxp,pca9450b"; - reg = <0x25>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - regulators { - buck1: BUCK1{ - regulator-name = "BUCK1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - }; - - buck4: BUCK4{ - regulator-name = "BUCK4"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5: BUCK5{ - regulator-name = "BUCK5"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2: LDO2 { - regulator-name = "LDO2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-name = "LDO4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5: LDO5 { - regulator-name = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&A53_0 { - /delete-property/operating-points-v2; -}; - -&A53_1 { - /delete-property/operating-points-v2; -}; - -&A53_2 { - /delete-property/operating-points-v2; -}; - -&A53_3 { - /delete-property/operating-points-v2; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi deleted file mode 100644 index 4aa0dbd57..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ /dev/null @@ -1,346 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - */ - -#include -#include "imx8mn.dtsi" - -/ { - chosen { - stdout-path = &uart2; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; - - status { - label = "yellow:status"; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ptn5110: tcpc@50 { - compatible = "nxp,ptn5110"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_typec1>; - reg = <0x50>; - interrupt-parent = <&gpio2>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - status = "okay"; - - port { - typec1_dr_sw: endpoint { - remote-endpoint = <&usb1_drd_sw>; - }; - }; - - typec1_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "dual"; - data-role = "dual"; - try-power-role = "sink"; - source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <15000000>; - self-powered; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - pca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart2 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - usb-role-switch; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - status = "okay"; - - port { - usb1_drd_sw: endpoint { - remote-endpoint = <&typec1_dr_sw>; - }; - }; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&usdhc3 { - assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_typec1: typec1grp { - fsl,pins = < - MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h deleted file mode 100644 index faf1e69e7..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h +++ /dev/null @@ -1,646 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018-2019 NXP - */ - -#ifndef __DTS_IMX8MN_PINFUNC_H -#define __DTS_IMX8MN_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ - -#define MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3 -#define MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0 -#define MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3 -#define MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x4BC 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x4C0 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO08_PWM1_OUT 0x048 0x2B0 0x000 0x2 0x0 -#define MX8MN_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_PWM2_OUT 0x04C 0x2B4 0x000 0x2 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x04C 0x2B4 0x000 0x4 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO10_PWM3_OUT 0x050 0x2B8 0x000 0x2 0x0 -#define MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO11_PWM2_OUT 0x054 0x2BC 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x054 0x2BC 0x000 0x4 0x0 -#define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 -#define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x060 0x2C8 0x598 0x4 0x2 -#define MX8MN_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO15_USDHC3_WP 0x064 0x2CC 0x5B8 0x4 0x2 -#define MX8MN_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 -#define MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_MDC_SAI6_TX_DATA0 0x068 0x2D0 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_MDC_PDM_BIT_STREAM3 0x068 0x2D0 0x540 0x3 0x1 -#define MX8MN_IOMUXC_ENET_MDC_SPDIF1_OUT 0x068 0x2D0 0x000 0x4 0x0 -#define MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_MDC_USDHC3_STROBE 0x068 0x2D0 0x59C 0x6 0x1 -#define MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 -#define MX8MN_IOMUXC_ENET_MDIO_SAI6_TX_SYNC 0x06C 0x2D4 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_MDIO_PDM_BIT_STREAM2 0x06C 0x2D4 0x53C 0x3 0x1 -#define MX8MN_IOMUXC_ENET_MDIO_SPDIF1_IN 0x06C 0x2D4 0x5CC 0x4 0x1 -#define MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_MDIO_USDHC3_DATA5 0x06C 0x2D4 0x550 0x6 0x1 -#define MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TD3_SAI6_TX_BCLK 0x070 0x2D8 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TD3_PDM_BIT_STREAM1 0x070 0x2D8 0x538 0x3 0x1 -#define MX8MN_IOMUXC_ENET_TD3_SPDIF1_EXT_CLK 0x070 0x2D8 0x568 0x4 0x1 -#define MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TD3_USDHC3_DATA6 0x070 0x2D8 0x584 0x6 0x1 -#define MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x5A4 0x1 0x0 -#define MX8MN_IOMUXC_ENET_TD2_CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x074 0x2DC 0x5A4 0x1 0x0 -#define MX8MN_IOMUXC_ENET_TD2_SAI6_RX_DATA0 0x074 0x2DC 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TD2_PDM_BIT_STREAM3 0x074 0x2DC 0x540 0x3 0x2 -#define MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TD2_USDHC3_DATA7 0x074 0x2DC 0x54C 0x6 0x1 -#define MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TD1_SAI6_RX_SYNC 0x078 0x2E0 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TD1_PDM_BIT_STREAM2 0x078 0x2E0 0x53C 0x3 0x2 -#define MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TD1_USDHC3_CD_B 0x078 0x2E0 0x598 0x6 0x3 -#define MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TD0_SAI6_RX_BCLK 0x07C 0x2E4 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TD0_PDM_BIT_STREAM1 0x07C 0x2E4 0x538 0x3 0x2 -#define MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TD0_USDHC3_WP 0x07C 0x2E4 0x5B8 0x6 0x3 -#define MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TX_CTL_SAI6_MCLK 0x080 0x2E8 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TX_CTL_USDHC3_DATA0 0x080 0x2E8 0x5B4 0x6 0x1 -#define MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ENET_TXC_SAI7_TX_DATA0 0x084 0x2EC 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TXC_USDHC3_DATA1 0x084 0x2EC 0x5B0 0x6 0x1 -#define MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x574 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RX_CTL_SAI7_TX_SYNC 0x088 0x2F0 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM3 0x088 0x2F0 0x540 0x3 0x3 -#define MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RX_CTL_USDHC3_DATA2 0x088 0x2F0 0x5E4 0x6 0x1 -#define MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x5C8 0x1 0x0 -#define MX8MN_IOMUXC_ENET_RXC_SAI7_TX_BCLK 0x08C 0x2F4 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RXC_PDM_BIT_STREAM2 0x08C 0x2F4 0x53C 0x3 0x3 -#define MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RXC_USDHC3_DATA3 0x08C 0x2F4 0x5E0 0x6 0x1 -#define MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x57C 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RD0_SAI7_RX_DATA0 0x090 0x2F8 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RD0_PDM_BIT_STREAM1 0x090 0x2F8 0x538 0x3 0x3 -#define MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RD0_USDHC3_DATA4 0x090 0x2F8 0x558 0x6 0x1 -#define MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x554 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RD1_SAI7_RX_SYNC 0x094 0x2FC 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RD1_PDM_BIT_STREAM0 0x094 0x2FC 0x534 0x3 0x1 -#define MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RD1_USDHC3_RESET_B 0x094 0x2FC 0x000 0x6 0x0 -#define MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RD2_SAI7_RX_BCLK 0x098 0x300 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RD2_PDM_CLK 0x098 0x300 0x000 0x3 0x0 -#define MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RD2_USDHC3_CLK 0x098 0x300 0x5A0 0x6 0x1 -#define MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RD3_SAI7_MCLK 0x09C 0x304 0x000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RD3_SPDIF1_IN 0x09C 0x304 0x5CC 0x3 0x5 -#define MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RD3_USDHC3_CMD 0x09C 0x304 0x5DC 0x6 0x1 -#define MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_CLK_ENET1_MDC 0x0A0 0x308 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SD1_CLK_UART1_DCE_TX 0x0A0 0x308 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_CLK_UART1_DTE_RX 0x0A0 0x308 0x4F4 0x4 0x4 -#define MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_CMD_ENET1_MDIO 0x0A4 0x30C 0x4C0 0x1 0x3 -#define MX8MN_IOMUXC_SD1_CMD_UART1_DCE_RX 0x0A4 0x30C 0x4F4 0x4 0x5 -#define MX8MN_IOMUXC_SD1_CMD_UART1_DTE_TX 0x0A4 0x30C 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA0_ENET1_RGMII_TD1 0x0A8 0x310 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SD1_DATA0_UART1_DCE_RTS_B 0x0A8 0x310 0x4F0 0x4 0x4 -#define MX8MN_IOMUXC_SD1_DATA0_UART1_DTE_CTS_B 0x0A8 0x310 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA1_ENET1_RGMII_TD0 0x0AC 0x314 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SD1_DATA1_UART1_DCE_CTS_B 0x0AC 0x314 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA1_UART1_DTE_RTS_B 0x0AC 0x314 0x4F0 0x4 0x5 -#define MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA2_ENET1_RGMII_RD0 0x0B0 0x318 0x57C 0x1 0x1 -#define MX8MN_IOMUXC_SD1_DATA2_UART2_DCE_TX 0x0B0 0x318 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA2_UART2_DTE_RX 0x0B0 0x318 0x4FC 0x4 0x4 -#define MX8MN_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA3_ENET1_RGMII_RD1 0x0B4 0x31C 0x554 0x1 0x1 -#define MX8MN_IOMUXC_SD1_DATA3_UART2_DCE_RX 0x0B4 0x31C 0x4FC 0x4 0x5 -#define MX8MN_IOMUXC_SD1_DATA3_UART2_DTE_TX 0x0B4 0x31C 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA4_ENET1_RGMII_TX_CTL 0x0B8 0x320 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SD1_DATA4_I2C1_SCL 0x0B8 0x320 0x55C 0x3 0x1 -#define MX8MN_IOMUXC_SD1_DATA4_UART2_DCE_RTS_B 0x0B8 0x320 0x4F8 0x4 0x4 -#define MX8MN_IOMUXC_SD1_DATA4_UART2_DTE_CTS_B 0x0B8 0x320 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA5_ENET1_TX_ER 0x0BC 0x324 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SD1_DATA5_I2C1_SDA 0x0BC 0x324 0x56C 0x3 0x1 -#define MX8MN_IOMUXC_SD1_DATA5_UART2_DCE_CTS_B 0x0BC 0x324 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA5_UART2_DTE_RTS_B 0x0BC 0x324 0x4F8 0x4 0x5 -#define MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA6_ENET1_RGMII_RX_CTL 0x0C0 0x328 0x574 0x1 0x1 -#define MX8MN_IOMUXC_SD1_DATA6_I2C2_SCL 0x0C0 0x328 0x5D0 0x3 0x1 -#define MX8MN_IOMUXC_SD1_DATA6_UART3_DCE_TX 0x0C0 0x328 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA6_UART3_DTE_RX 0x0C0 0x328 0x504 0x4 0x4 -#define MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA7_ENET1_RX_ER 0x0C4 0x32C 0x5C8 0x1 0x1 -#define MX8MN_IOMUXC_SD1_DATA7_I2C2_SDA 0x0C4 0x32C 0x560 0x3 0x1 -#define MX8MN_IOMUXC_SD1_DATA7_UART3_DCE_RX 0x0C4 0x32C 0x504 0x4 0x5 -#define MX8MN_IOMUXC_SD1_DATA7_UART3_DTE_TX 0x0C4 0x32C 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_RESET_B_ENET1_TX_CLK 0x0C8 0x330 0x5A4 0x1 0x1 -#define MX8MN_IOMUXC_SD1_RESET_B_CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x0C8 0x330 0x5A4 0x1 0x0 -#define MX8MN_IOMUXC_SD1_RESET_B_I2C3_SCL 0x0C8 0x330 0x588 0x3 0x1 -#define MX8MN_IOMUXC_SD1_RESET_B_UART3_DCE_RTS_B 0x0C8 0x330 0x500 0x4 0x2 -#define MX8MN_IOMUXC_SD1_RESET_B_UART3_DTE_CTS_B 0x0C8 0x330 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_STROBE_I2C3_SDA 0x0CC 0x334 0x5BC 0x3 0x1 -#define MX8MN_IOMUXC_SD1_STROBE_UART3_DCE_CTS_B 0x0CC 0x334 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_STROBE_UART3_DTE_RTS_B 0x0CC 0x334 0x500 0x4 0x3 -#define MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_CD_B_CCMSRCGPCMIX_TESTER_ACK 0x0D0 0x338 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_CLK_SAI5_RX_SYNC 0x0D4 0x33C 0x4E4 0x1 0x1 -#define MX8MN_IOMUXC_SD2_CLK_ECSPI2_SCLK 0x0D4 0x33C 0x580 0x2 0x1 -#define MX8MN_IOMUXC_SD2_CLK_UART4_DCE_RX 0x0D4 0x33C 0x50C 0x3 0x4 -#define MX8MN_IOMUXC_SD2_CLK_UART4_DTE_TX 0x0D4 0x33C 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SD2_CLK_SAI5_MCLK 0x0D4 0x33C 0x594 0x4 0x1 -#define MX8MN_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_CMD_SAI5_RX_BCLK 0x0D8 0x340 0x4D0 0x1 0x1 -#define MX8MN_IOMUXC_SD2_CMD_ECSPI2_MOSI 0x0D8 0x340 0x590 0x2 0x1 -#define MX8MN_IOMUXC_SD2_CMD_UART4_DCE_TX 0x0D8 0x340 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SD2_CMD_UART4_DTE_RX 0x0D8 0x340 0x50C 0x3 0x5 -#define MX8MN_IOMUXC_SD2_CMD_PDM_CLK 0x0D8 0x340 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_DATA0_SAI5_RX_DATA0 0x0DC 0x344 0x4D4 0x1 0x1 -#define MX8MN_IOMUXC_SD2_DATA0_I2C4_SDA 0x0DC 0x344 0x58C 0x2 0x1 -#define MX8MN_IOMUXC_SD2_DATA0_UART2_DCE_RX 0x0DC 0x344 0x4FC 0x3 0x6 -#define MX8MN_IOMUXC_SD2_DATA0_UART2_DTE_TX 0x0DC 0x344 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SD2_DATA0_PDM_BIT_STREAM0 0x0DC 0x344 0x534 0x4 0x2 -#define MX8MN_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_DATA1_SAI5_TX_SYNC 0x0E0 0x348 0x4EC 0x1 0x1 -#define MX8MN_IOMUXC_SD2_DATA1_I2C4_SCL 0x0E0 0x348 0x5D4 0x2 0x1 -#define MX8MN_IOMUXC_SD2_DATA1_UART2_DCE_TX 0x0E0 0x348 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SD2_DATA1_UART2_DTE_RX 0x0E0 0x348 0x4FC 0x3 0x7 -#define MX8MN_IOMUXC_SD2_DATA1_PDM_BIT_STREAM1 0x0E0 0x348 0x538 0x4 0x4 -#define MX8MN_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_DATA2_SAI5_TX_BCLK 0x0E4 0x34C 0x4E8 0x1 0x1 -#define MX8MN_IOMUXC_SD2_DATA2_ECSPI2_SS0 0x0E4 0x34C 0x570 0x2 0x2 -#define MX8MN_IOMUXC_SD2_DATA2_SPDIF1_OUT 0x0E4 0x34C 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SD2_DATA2_PDM_BIT_STREAM2 0x0E4 0x34C 0x53C 0x4 0x4 -#define MX8MN_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_DATA3_SAI5_TX_DATA0 0x0E8 0x350 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SD2_DATA3_ECSPI2_MISO 0x0E8 0x350 0x578 0x2 0x1 -#define MX8MN_IOMUXC_SD2_DATA3_SPDIF1_IN 0x0E8 0x350 0x5CC 0x3 0x2 -#define MX8MN_IOMUXC_SD2_DATA3_PDM_BIT_STREAM3 0x0E8 0x350 0x540 0x4 0x4 -#define MX8MN_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_WP_CORESIGHT_EVENTI 0x0F0 0x358 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_ALE_PDM_BIT_STREAM0 0x0F4 0x35C 0x534 0x3 0x3 -#define MX8MN_IOMUXC_NAND_ALE_UART3_DCE_RX 0x0F4 0x35C 0x504 0x4 0x6 -#define MX8MN_IOMUXC_NAND_ALE_UART3_DTE_TX 0x0F4 0x35C 0x000 0x4 0x0 -#define MX8MN_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK 0x0F4 0x35C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_CE0_B_PDM_BIT_STREAM1 0x0F8 0x360 0x538 0x3 0x5 -#define MX8MN_IOMUXC_NAND_CE0_B_UART3_DCE_TX 0x0F8 0x360 0x000 0x4 0x0 -#define MX8MN_IOMUXC_NAND_CE0_B_UART3_DTE_RX 0x0F8 0x360 0x504 0x4 0x7 -#define MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL 0x0F8 0x360 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x0FC 0x364 0x59C 0x2 0x0 -#define MX8MN_IOMUXC_NAND_CE1_B_PDM_BIT_STREAM0 0x0FC 0x364 0x534 0x3 0x4 -#define MX8MN_IOMUXC_NAND_CE1_B_I2C4_SCL 0x0FC 0x364 0x5D4 0x4 0x2 -#define MX8MN_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_CE1_B_CORESIGHT_TRACE0 0x0FC 0x364 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x100 0x368 0x550 0x2 0x0 -#define MX8MN_IOMUXC_NAND_CE2_B_PDM_BIT_STREAM1 0x100 0x368 0x538 0x3 0x6 -#define MX8MN_IOMUXC_NAND_CE2_B_I2C4_SDA 0x100 0x368 0x58C 0x4 0x2 -#define MX8MN_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_CE2_B_CORESIGHT_TRACE1 0x100 0x368 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x104 0x36C 0x584 0x2 0x0 -#define MX8MN_IOMUXC_NAND_CE3_B_PDM_BIT_STREAM2 0x104 0x36C 0x53C 0x3 0x5 -#define MX8MN_IOMUXC_NAND_CE3_B_I2C3_SDA 0x104 0x36C 0x5BC 0x4 0x2 -#define MX8MN_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_CE3_B_CORESIGHT_TRACE2 0x104 0x36C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x108 0x370 0x54C 0x2 0x0 -#define MX8MN_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_CLE_CORESIGHT_TRACE3 0x108 0x370 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA00_PDM_BIT_STREAM2 0x10C 0x374 0x53C 0x3 0x6 -#define MX8MN_IOMUXC_NAND_DATA00_UART4_DCE_RX 0x10C 0x374 0x50C 0x4 0x6 -#define MX8MN_IOMUXC_NAND_DATA00_UART4_DTE_TX 0x10C 0x374 0x000 0x4 0x0 -#define MX8MN_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA00_CORESIGHT_TRACE4 0x10C 0x374 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA01_PDM_BIT_STREAM3 0x110 0x378 0x540 0x3 0x5 -#define MX8MN_IOMUXC_NAND_DATA01_UART4_DCE_TX 0x110 0x378 0x000 0x4 0x0 -#define MX8MN_IOMUXC_NAND_DATA01_UART4_DTE_RX 0x110 0x378 0x50C 0x4 0x7 -#define MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA01_CORESIGHT_TRACE5 0x110 0x378 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA02_USDHC3_CD_B 0x114 0x37C 0x598 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA02_I2C4_SDA 0x114 0x37C 0x58C 0x4 0x3 -#define MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA02_CORESIGHT_TRACE6 0x114 0x37C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA03_USDHC3_WP 0x118 0x380 0x5B8 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA03_CORESIGHT_TRACE7 0x118 0x380 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x11C 0x384 0x5B4 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA04_CORESIGHT_TRACE8 0x11C 0x384 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x120 0x388 0x5B0 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA05_CORESIGHT_TRACE9 0x120 0x388 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x124 0x38C 0x5E4 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA06_CORESIGHT_TRACE10 0x124 0x38C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x128 0x390 0x5E0 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA07_CORESIGHT_TRACE11 0x128 0x390 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DQS_PDM_CLK 0x12C 0x394 0x000 0x3 0x0 -#define MX8MN_IOMUXC_NAND_DQS_I2C3_SCL 0x12C 0x394 0x588 0x4 0x2 -#define MX8MN_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DQS_CORESIGHT_TRACE12 0x12C 0x394 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x130 0x398 0x558 0x2 0x0 -#define MX8MN_IOMUXC_NAND_RE_B_PDM_BIT_STREAM1 0x130 0x398 0x538 0x3 0x7 -#define MX8MN_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_RE_B_CORESIGHT_TRACE13 0x130 0x398 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x134 0x39C 0x000 0x2 0x0 -#define MX8MN_IOMUXC_NAND_READY_B_PDM_BIT_STREAM3 0x134 0x39C 0x540 0x3 0x6 -#define MX8MN_IOMUXC_NAND_READY_B_I2C3_SCL 0x134 0x39C 0x588 0x4 0x3 -#define MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_READY_B_CORESIGHT_TRACE14 0x134 0x39C 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x138 0x3A0 0x5A0 0x2 0x0 -#define MX8MN_IOMUXC_NAND_WE_B_I2C3_SDA 0x138 0x3A0 0x5BC 0x4 0x3 -#define MX8MN_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_WE_B_CORESIGHT_TRACE15 0x138 0x3A0 0x000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x13C 0x3A4 0x5DC 0x2 0x0 -#define MX8MN_IOMUXC_NAND_WP_B_I2C4_SDA 0x13C 0x3A4 0x58C 0x4 0x4 -#define MX8MN_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_WP_B_CORESIGHT_EVENTO 0x13C 0x3A4 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0x144 0x3AC 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x148 0x3B0 0x534 0x4 0x0 -#define MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 -#define MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x14C 0x3B4 0x538 0x4 0x0 -#define MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 -#define MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x150 0x3B8 0x53C 0x4 0x0 -#define MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x154 0x3BC 0x540 0x4 0x0 -#define MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x594 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 -#define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x1B0 0x418 0x000 0x2 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x1B0 0x418 0x5AC 0x3 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1B0 0x418 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_UART1_DTE_RX 0x1B0 0x418 0x4F4 0x4 0x2 -#define MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_PDM_BIT_STREAM2 0x1B0 0x418 0x53C 0x6 0x7 -#define MX8MN_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 -#define MX8MN_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1B4 0x41C 0x4F4 0x4 0x3 -#define MX8MN_IOMUXC_SAI2_RXC_UART1_DTE_TX 0x1B4 0x41C 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_RXC_PDM_BIT_STREAM1 0x1B4 0x41C 0x538 0x6 0x8 -#define MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI2_RXD0_SAI2_TX_DATA1 0x1B8 0x420 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x1B8 0x420 0x4F0 0x4 0x2 -#define MX8MN_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B 0x1B8 0x420 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_RXD0_PDM_BIT_STREAM3 0x1B8 0x420 0x540 0x6 0x7 -#define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x1BC 0x424 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x1BC 0x424 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B 0x1BC 0x424 0x4F0 0x4 0x3 -#define MX8MN_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_TXFS_PDM_BIT_STREAM2 0x1BC 0x424 0x53C 0x6 0x8 -#define MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_TXC_PDM_BIT_STREAM1 0x1C0 0x428 0x538 0x6 0x9 -#define MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_TXD0_CCMSRCGPCMIX_BOOT_MODE4 0x1C4 0x42C 0x540 0x6 0x8 -#define MX8MN_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x594 0x1 0x2 -#define MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_MCLK_SAI3_MCLK 0x1C8 0x430 0x5C0 0x6 0x1 -#define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x5F0 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 -#define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x1CC 0x434 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SAI3_RXFS_SPDIF1_IN 0x1CC 0x434 0x5CC 0x4 0x3 -#define MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_RXFS_PDM_BIT_STREAM0 0x1CC 0x434 0x534 0x6 0x5 -#define MX8MN_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_RXC_GPT1_CLK 0x1D0 0x438 0x5E8 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 -#define MX8MN_IOMUXC_SAI3_RXC_SAI2_RX_DATA1 0x1D0 0x438 0x5AC 0x3 0x2 -#define MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1D0 0x438 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x1D0 0x438 0x4F8 0x4 0x2 -#define MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_RXC_PDM_CLK 0x1D0 0x438 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 -#define MX8MN_IOMUXC_SAI3_RXD_SAI3_TX_DATA1 0x1D4 0x43C 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1D4 0x43C 0x4F8 0x4 0x3 -#define MX8MN_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x1D4 0x43C 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_PDM_BIT_STREAM1 0x1D4 0x43C 0x538 0x6 0x10 -#define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x5EC 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x1 -#define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x1D8 0x440 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4FC 0x4 0x2 -#define MX8MN_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x1D8 0x440 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_TXFS_PDM_BIT_STREAM3 0x1D8 0x440 0x540 0x6 0x9 -#define MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x1 -#define MX8MN_IOMUXC_SAI3_TXC_SAI2_TX_DATA1 0x1DC 0x444 0x000 0x3 0x0 -#define MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1DC 0x444 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4FC 0x4 0x3 -#define MX8MN_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_TXC_PDM_BIT_STREAM2 0x1DC 0x444 0x53C 0x6 0x9 -#define MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x1 -#define MX8MN_IOMUXC_SAI3_TXD_SPDIF1_EXT_CLK 0x1E0 0x448 0x568 0x4 0x2 -#define MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_TXD_CCMSRCGPCMIX_BOOT_MODE5 0x1E0 0x448 0x000 0x6 0x0 -#define MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x5C0 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x594 0x2 0x3 -#define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_OUT 0x1E4 0x44C 0x000 0x4 0x0 -#define MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_IN 0x1E4 0x44C 0x5CC 0x6 0x4 -#define MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 -#define MX8MN_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x5CC 0x0 0x0 -#define MX8MN_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 -#define MX8MN_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x568 0x0 0x0 -#define MX8MN_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 -#define MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x5D8 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_SCLK_I2C1_SCL 0x1F4 0x45C 0x55C 0x2 0x2 -#define MX8MN_IOMUXC_ECSPI1_SCLK_SAI5_RX_SYNC 0x1F4 0x45C 0x4DC 0x3 0x2 -#define MX8MN_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x5A8 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 -#define MX8MN_IOMUXC_ECSPI1_MOSI_I2C1_SDA 0x1F8 0x460 0x56C 0x2 0x2 -#define MX8MN_IOMUXC_ECSPI1_MOSI_SAI5_RX_BCLK 0x1F8 0x460 0x4D0 0x3 0x3 -#define MX8MN_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x5C4 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_MISO_I2C2_SCL 0x1FC 0x464 0x5D0 0x2 0x2 -#define MX8MN_IOMUXC_ECSPI1_MISO_SAI5_RX_DATA0 0x1FC 0x464 0x4D4 0x3 0x3 -#define MX8MN_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x564 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 -#define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_SS0_I2C2_SDA 0x200 0x468 0x560 0x2 0x2 -#define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_RX_DATA1 0x200 0x468 0x4D8 0x3 0x2 -#define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_TX_SYNC 0x200 0x468 0x4EC 0x4 0x3 -#define MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x580 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_SCLK_I2C3_SCL 0x204 0x46C 0x588 0x2 0x4 -#define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_RX_DATA2 0x204 0x46C 0x000 0x3 0x0 -#define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_TX_BCLK 0x204 0x46C 0x4E8 0x4 0x3 -#define MX8MN_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x590 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 -#define MX8MN_IOMUXC_ECSPI2_MOSI_I2C3_SDA 0x208 0x470 0x5BC 0x2 0x4 -#define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_RX_DATA3 0x208 0x470 0x4E0 0x3 0x2 -#define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_TX_DATA0 0x208 0x470 0x000 0x4 0x0 -#define MX8MN_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x578 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_MISO_I2C4_SCL 0x20C 0x474 0x5D4 0x2 0x3 -#define MX8MN_IOMUXC_ECSPI2_MISO_SAI5_MCLK 0x20C 0x474 0x594 0x3 0x4 -#define MX8MN_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x570 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 -#define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_SS0_I2C4_SDA 0x210 0x478 0x58C 0x2 0x5 -#define MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x55C 0x0 0x0 -#define MX8MN_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_I2C1_SCL_ECSPI1_SCLK 0x214 0x47C 0x5D8 0x3 0x1 -#define MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x56C 0x0 0x0 -#define MX8MN_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 -#define MX8MN_IOMUXC_I2C1_SDA_ECSPI1_MOSI 0x218 0x480 0x5A8 0x3 0x1 -#define MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x5D0 0x0 0x0 -#define MX8MN_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 -#define MX8MN_IOMUXC_I2C2_SCL_USDHC3_CD_B 0x21C 0x484 0x598 0x2 0x1 -#define MX8MN_IOMUXC_I2C2_SCL_ECSPI1_MISO 0x21C 0x484 0x5C4 0x3 0x1 -#define MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x560 0x0 0x0 -#define MX8MN_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 -#define MX8MN_IOMUXC_I2C2_SDA_USDHC3_WP 0x220 0x488 0x5B8 0x2 0x1 -#define MX8MN_IOMUXC_I2C2_SDA_ECSPI1_SS0 0x220 0x488 0x564 0x3 0x1 -#define MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x588 0x0 0x0 -#define MX8MN_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 -#define MX8MN_IOMUXC_I2C3_SCL_ECSPI2_SCLK 0x224 0x48C 0x580 0x3 0x2 -#define MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x5BC 0x0 0x0 -#define MX8MN_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 -#define MX8MN_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 -#define MX8MN_IOMUXC_I2C3_SDA_ECSPI2_MOSI 0x228 0x490 0x590 0x3 0x2 -#define MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x5D4 0x0 0x0 -#define MX8MN_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 -#define MX8MN_IOMUXC_I2C4_SCL_ECSPI2_MISO 0x22C 0x494 0x578 0x3 0x2 -#define MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 -#define MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x58C 0x0 0x0 -#define MX8MN_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 -#define MX8MN_IOMUXC_I2C4_SDA_ECSPI2_SS0 0x230 0x498 0x570 0x3 0x1 -#define MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 -#define MX8MN_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x1 -#define MX8MN_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 -#define MX8MN_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART2_RXD_GPT1_COMPARE3 0x23C 0x4A4 0x000 0x3 0x0 -#define MX8MN_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 -#define MX8MN_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART2_TXD_GPT1_COMPARE2 0x240 0x4A8 0x000 0x3 0x0 -#define MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 -#define MX8MN_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 -#define MX8MN_IOMUXC_UART3_RXD_USDHC3_RESET_B 0x244 0x4AC 0x000 0x2 0x0 -#define MX8MN_IOMUXC_UART3_RXD_GPT1_CAPTURE2 0x244 0x4AC 0x5EC 0x3 0x1 -#define MX8MN_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 -#define MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 -#define MX8MN_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART3_TXD_USDHC3_VSELECT 0x248 0x4B0 0x000 0x2 0x0 -#define MX8MN_IOMUXC_UART3_TXD_GPT1_CLK 0x248 0x4B0 0x5E8 0x3 0x1 -#define MX8MN_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 -#define MX8MN_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 -#define MX8MN_IOMUXC_UART4_RXD_GPT1_COMPARE1 0x24C 0x4B4 0x000 0x3 0x0 -#define MX8MN_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 -#define MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 -#define MX8MN_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 -#define MX8MN_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 -#define MX8MN_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 -#define MX8MN_IOMUXC_UART4_TXD_GPT1_CAPTURE1 0x250 0x4B8 0x5F0 0x3 0x1 -#define MX8MN_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 - -#endif /* __DTS_IMX8MN_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts deleted file mode 100644 index f61c48776..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ /dev/null @@ -1,240 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019-2020 Variscite Ltd. - * Copyright (C) 2020 Krzysztof Kozlowski - */ - -/dts-v1/; - -#include "imx8mn-var-som.dtsi" - -/ { - model = "Variscite VAR-SOM-MX8MN Symphony evaluation board"; - compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn"; - - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - gpio-keys { - compatible = "gpio-keys"; - - back { - label = "Back"; - gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - home { - label = "Home"; - gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - menu { - label = "Menu"; - gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - led { - label = "Heartbeat"; - gpios = <&pca9534 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -ðphy { - reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pca9534: gpio@20 { - compatible = "nxp,pca9534"; - reg = <0x20>; - gpio-controller; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pca9534>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - #gpio-cells = <2>; - wakeup-source; - - /* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */ - usb3-sata-sel-hog { - gpio-hog; - gpios = <4 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "usb3_sata_sel"; - }; - - som-vselect-hog { - gpio-hog; - gpios = <6 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "som_vselect"; - }; - - enet-sel-hog { - gpio-hog; - gpios = <7 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "enet_sel"; - }; - }; - - extcon_usbotg1: typec@3d { - compatible = "nxp,ptn5150"; - reg = <0x3d>; - interrupt-parent = <&gpio1>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ptn5150>; - status = "okay"; - }; -}; - -&i2c3 { - /* Capacitive touch controller */ - ft5x06_ts: touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_captouch>; - interrupt-parent = <&gpio5>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; - - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - touchscreen-inverted-x; - touchscreen-inverted-y; - }; - - rtc@68 { - compatible = "dallas,ds1337"; - reg = <0x68>; - }; -}; - -/* Header */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* Header */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbotg1 { - disable-over-current; - extcon = <&extcon_usbotg1>, <&extcon_usbotg1>; -}; - -&pinctrl_fec1 { - fsl,pins = < - MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */ - >; -}; - -&pinctrl_fec1_sleep { - fsl,pins = < - MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120 - MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120 - MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120 - MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120 - MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120 - MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120 - MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120 - MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120 - MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120 - MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120 - MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120 - MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120 - MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120 - MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120 - /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */ - >; -}; - -&iomuxc { - pinctrl_captouch: captouchgrp { - fsl,pins = < - MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_pca9534: pca9534grp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 - >; - }; - - pinctrl_ptn5150: ptn5150grp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi deleted file mode 100644 index f6287f174..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ /dev/null @@ -1,548 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - * Copyright 2019-2020 Variscite Ltd. - * Copyright (C) 2020 Krzysztof Kozlowski - */ - -#include "imx8mn.dtsi" - -/ { - model = "Variscite VAR-SOM-MX8MN module"; - compatible = "variscite,var-som-mx8mn", "fsl,imx8mn"; - - chosen { - stdout-path = &uart4; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x40000000>; - }; - - reg_eth_phy: regulator-eth-phy { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_eth_phy>; - regulator-name = "eth_phy_pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>, - <&gpio1 0 GPIO_ACTIVE_LOW>; - /delete-property/ dmas; - /delete-property/ dma-names; - status = "okay"; - - /* Resistive touch controller */ - touchscreen@0 { - reg = <0>; - compatible = "ti,ads7846"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_restouch>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - - spi-max-frequency = <1500000>; - pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; - - ti,x-min = /bits/ 16 <125>; - touchscreen-size-x = <4008>; - ti,y-min = /bits/ 16 <282>; - touchscreen-size-y = <3864>; - ti,x-plate-ohms = /bits/ 16 <180>; - touchscreen-max-pressure = <255>; - touchscreen-average-samples = <10>; - ti,debounce-tol = /bits/ 16 <3>; - ti,debounce-rep = /bits/ 16 <1>; - ti,settle-delay-usec = /bits/ 16 <150>; - ti,keep-vref-on; - wakeup-source; - }; -}; - -&fec1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_fec1>; - pinctrl-1 = <&pinctrl_fec1_sleep>; - phy-mode = "rgmii"; - phy-handle = <ðphy>; - phy-supply = <®_eth_phy>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@4 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <4>; - reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio2>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - }; - - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - buck3_reg: BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <2600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5_reg: LDO5 { - regulator-compatible = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - /* TODO: configure audio, as of now just put a placeholder */ - wm8904: codec@1a { - compatible = "wlf,wm8904"; - reg = <0x1a>; - status = "disabled"; - }; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -/* Bluetooth */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - assigned-clocks = <&clk IMX8MN_CLK_UART2>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; - uart-has-rtscts; - status = "okay"; -}; - -/* Console */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - usb-role-switch; - status = "okay"; -}; - -/* WIFI */ -&usdhc1 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <4>; - non-removable; - keep-power-in-suspend; - status = "okay"; - - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD */ -&usdhc2 { - assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13 - MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13 - MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13 - MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13 - MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - >; - }; - - pinctrl_fec1_sleep: fec1sleepgrp { - fsl,pins = < - MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120 - MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120 - MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120 - MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120 - MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120 - MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120 - MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120 - MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120 - MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120 - MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120 - MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120 - MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120 - MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120 - MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120 - MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x120 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141 - >; - }; - - pinctrl_reg_eth_phy: regethphygrp { - fsl,pins = < - MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 - >; - }; - - pinctrl_restouch: restouchgrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 - MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 - MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 - MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 - MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi deleted file mode 100644 index aea723eb2..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ /dev/null @@ -1,858 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - */ - -#include -#include -#include -#include -#include - -#include "imx8mn-pinfunc.h" - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet0 = &fec1; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - idle-states { - entry-method = "psci"; - - cpu_pd_wait: cpu-pd-wait { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010033>; - local-timer-stop; - entry-latency-us = <1000>; - exit-latency-us = <700>; - min-residency-us = <2700>; - }; - }; - - A53_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - clock-latency = <61036>; - clocks = <&clk IMX8MN_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - nvmem-cells = <&cpu_speed_grade>; - nvmem-cell-names = "speed_grade"; - cpu-idle-states = <&cpu_pd_wait>; - #cooling-cells = <2>; - }; - - A53_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - clock-latency = <61036>; - clocks = <&clk IMX8MN_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - cpu-idle-states = <&cpu_pd_wait>; - #cooling-cells = <2>; - }; - - A53_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x2>; - clock-latency = <61036>; - clocks = <&clk IMX8MN_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - cpu-idle-states = <&cpu_pd_wait>; - #cooling-cells = <2>; - }; - - A53_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x3>; - clock-latency = <61036>; - clocks = <&clk IMX8MN_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - cpu-idle-states = <&cpu_pd_wait>; - #cooling-cells = <2>; - }; - - A53_L2: l2-cache0 { - compatible = "cache"; - }; - }; - - a53_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <850000>; - opp-supported-hw = <0xb00>, <0x7>; - clock-latency-ns = <150000>; - opp-suspend; - }; - - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <950000>; - opp-supported-hw = <0x300>, <0x7>; - clock-latency-ns = <150000>; - opp-suspend; - }; - - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1000000>; - opp-supported-hw = <0x100>, <0x3>; - clock-latency-ns = <150000>; - opp-suspend; - }; - }; - - osc_32k: clock-osc-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "osc_32k"; - }; - - osc_24m: clock-osc-24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc_24m"; - }; - - clk_ext1: clock-ext1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext1"; - }; - - clk_ext2: clock-ext2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext2"; - }; - - clk_ext3: clock-ext3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext3"; - }; - - clk_ext4: clock-ext4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency= <133000000>; - clock-output-names = "clk_ext4"; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu>; - trips { - cpu_alert0: trip0 { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit0: trip1 { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - clock-frequency = <8000000>; - arm,no-tick-in-suspend; - }; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x3e000000>; - - aips1: bus@30000000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x30000000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio1: gpio@30200000 { - compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; - reg = <0x30200000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 10 30>; - }; - - gpio2: gpio@30210000 { - compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; - reg = <0x30210000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 40 21>; - }; - - gpio3: gpio@30220000 { - compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; - reg = <0x30220000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 61 26>; - }; - - gpio4: gpio@30230000 { - compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; - reg = <0x30230000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 21 108 11>; - }; - - gpio5: gpio@30240000 { - compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; - reg = <0x30240000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 119 30>; - }; - - tmu: tmu@30260000 { - compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; - reg = <0x30260000 0x10000>; - clocks = <&clk IMX8MN_CLK_TMU_ROOT>; - #thermal-sensor-cells = <0>; - }; - - wdog1: watchdog@30280000 { - compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; - reg = <0x30280000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>; - status = "disabled"; - }; - - wdog2: watchdog@30290000 { - compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; - reg = <0x30290000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>; - status = "disabled"; - }; - - wdog3: watchdog@302a0000 { - compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; - reg = <0x302a0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>; - status = "disabled"; - }; - - sdma3: dma-controller@302b0000 { - compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; - reg = <0x302b0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, - <&clk IMX8MN_CLK_SDMA3_ROOT>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - sdma2: dma-controller@302c0000 { - compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; - reg = <0x302c0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, - <&clk IMX8MN_CLK_SDMA2_ROOT>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - iomuxc: pinctrl@30330000 { - compatible = "fsl,imx8mn-iomuxc"; - reg = <0x30330000 0x10000>; - }; - - gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; - reg = <0x30340000 0x10000>; - }; - - ocotp: efuse@30350000 { - compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon"; - reg = <0x30350000 0x10000>; - clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; - #address-cells = <1>; - #size-cells = <1>; - - cpu_speed_grade: speed-grade@10 { - reg = <0x10 4>; - }; - }; - - anatop: anatop@30360000 { - compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop", - "syscon"; - reg = <0x30360000 0x10000>; - }; - - snvs: snvs@30370000 { - compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; - reg = <0x30370000 0x10000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = , - ; - clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; - clock-names = "snvs-rtc"; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; - clock-names = "snvs-pwrkey"; - linux,keycode = ; - wakeup-source; - status = "disabled"; - }; - }; - - clk: clock-controller@30380000 { - compatible = "fsl,imx8mn-ccm"; - reg = <0x30380000 0x10000>; - #clock-cells = <1>; - clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; - clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; - assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>, - <&clk IMX8MN_CLK_A53_CORE>, - <&clk IMX8MN_CLK_NOC>, - <&clk IMX8MN_CLK_AUDIO_AHB>, - <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, - <&clk IMX8MN_SYS_PLL3>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>, - <&clk IMX8MN_ARM_PLL_OUT>, - <&clk IMX8MN_SYS_PLL3_OUT>, - <&clk IMX8MN_SYS_PLL1_800M>; - assigned-clock-rates = <0>, <0>, <0>, - <400000000>, - <400000000>, - <600000000>; - }; - - src: reset-controller@30390000 { - compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"; - reg = <0x30390000 0x10000>; - interrupts = ; - #reset-cells = <1>; - }; - }; - - aips2: bus@30400000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x30400000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pwm1: pwm@30660000 { - compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; - reg = <0x30660000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_PWM1_ROOT>, - <&clk IMX8MN_CLK_PWM1_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@30670000 { - compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; - reg = <0x30670000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_PWM2_ROOT>, - <&clk IMX8MN_CLK_PWM2_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@30680000 { - compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; - reg = <0x30680000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_PWM3_ROOT>, - <&clk IMX8MN_CLK_PWM3_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@30690000 { - compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; - reg = <0x30690000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_PWM4_ROOT>, - <&clk IMX8MN_CLK_PWM4_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - system_counter: timer@306a0000 { - compatible = "nxp,sysctr-timer"; - reg = <0x306a0000 0x20000>; - interrupts = ; - clocks = <&osc_24m>; - clock-names = "per"; - }; - }; - - aips3: bus@30800000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x30800000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - ecspi1: spi@30820000 { - compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30820000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, - <&clk IMX8MN_CLK_ECSPI1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi2: spi@30830000 { - compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30830000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, - <&clk IMX8MN_CLK_ECSPI2_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi3: spi@30840000 { - compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30840000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, - <&clk IMX8MN_CLK_ECSPI3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@30860000 { - compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_UART1_ROOT>, - <&clk IMX8MN_CLK_UART1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart3: serial@30880000 { - compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_UART3_ROOT>, - <&clk IMX8MN_CLK_UART3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: serial@30890000 { - compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_UART2_ROOT>, - <&clk IMX8MN_CLK_UART2_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - crypto: crypto@30900000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30900000 0x40000>; - ranges = <0 0x30900000 0x40000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_AHB>, - <&clk IMX8MN_CLK_IPG_ROOT>; - clock-names = "aclk", "ipg"; - - sec_jr0: jr@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - sec_jr1: jr@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = ; - }; - - sec_jr2: jr@3000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x3000 0x1000>; - interrupts = ; - }; - }; - - i2c1: i2c@30a20000 { - compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30a20000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_I2C1_ROOT>; - status = "disabled"; - }; - - i2c2: i2c@30a30000 { - compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30a30000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_I2C2_ROOT>; - status = "disabled"; - }; - - i2c3: i2c@30a40000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; - reg = <0x30a40000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_I2C3_ROOT>; - status = "disabled"; - }; - - i2c4: i2c@30a50000 { - compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30a50000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_I2C4_ROOT>; - status = "disabled"; - }; - - uart4: serial@30a60000 { - compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; - reg = <0x30a60000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_UART4_ROOT>, - <&clk IMX8MN_CLK_UART4_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - mu: mailbox@30aa0000 { - compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu"; - reg = <0x30aa0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_MU_ROOT>; - #mbox-cells = <2>; - }; - - usdhc1: mmc@30b40000 { - compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; - reg = <0x30b40000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_IPG_ROOT>, - <&clk IMX8MN_CLK_NAND_USDHC_BUS>, - <&clk IMX8MN_CLK_USDHC1_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: mmc@30b50000 { - compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; - reg = <0x30b50000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_IPG_ROOT>, - <&clk IMX8MN_CLK_NAND_USDHC_BUS>, - <&clk IMX8MN_CLK_USDHC2_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - bus-width = <4>; - status = "disabled"; - }; - - usdhc3: mmc@30b60000 { - compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; - reg = <0x30b60000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_IPG_ROOT>, - <&clk IMX8MN_CLK_NAND_USDHC_BUS>, - <&clk IMX8MN_CLK_USDHC3_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - bus-width = <4>; - status = "disabled"; - }; - - sdma1: dma-controller@30bd0000 { - compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; - reg = <0x30bd0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, - <&clk IMX8MN_CLK_AHB>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - fec1: ethernet@30be0000 { - compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec"; - reg = <0x30be0000 0x10000>; - interrupts = , - , - , - ; - clocks = <&clk IMX8MN_CLK_ENET1_ROOT>, - <&clk IMX8MN_CLK_ENET1_ROOT>, - <&clk IMX8MN_CLK_ENET_TIMER>, - <&clk IMX8MN_CLK_ENET_REF>, - <&clk IMX8MN_CLK_ENET_PHY_REF>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>, - <&clk IMX8MN_CLK_ENET_TIMER>, - <&clk IMX8MN_CLK_ENET_REF>, - <&clk IMX8MN_CLK_ENET_PHY_REF>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, - <&clk IMX8MN_SYS_PLL2_100M>, - <&clk IMX8MN_SYS_PLL2_125M>, - <&clk IMX8MN_SYS_PLL2_50M>; - assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; - status = "disabled"; - }; - - }; - - aips4: bus@32c00000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x32c00000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbotg1: usb@32e40000 { - compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; - reg = <0x32e40000 0x200>; - interrupts = ; - clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; - clock-names = "usb1_ctrl_root_clk"; - assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; - fsl,usbphy = <&usbphynop1>; - fsl,usbmisc = <&usbmisc1 0>; - status = "disabled"; - }; - - usbmisc1: usbmisc@32e40200 { - compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; - #index-cells = <1>; - reg = <0x32e40200 0x200>; - }; - }; - - dma_apbh: dma-controller@33000000 { - compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; - reg = <0x33000000 0x2000>; - interrupts = , - , - , - ; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; - #dma-cells = <1>; - dma-channels = <4>; - clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; - }; - - gpmi: nand-controller@33002000 { - compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x33002000 0x2000>, <0x33004000 0x4000>; - reg-names = "gpmi-nand", "bch"; - interrupts = ; - interrupt-names = "bch"; - clocks = <&clk IMX8MN_CLK_NAND_ROOT>, - <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; - clock-names = "gpmi_io", "gpmi_bch_apb"; - dmas = <&dma_apbh 0>; - dma-names = "rx-tx"; - status = "disabled"; - }; - - gic: interrupt-controller@38800000 { - compatible = "arm,gic-v3"; - reg = <0x38800000 0x10000>, - <0x38880000 0xc0000>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - }; - - ddrc: memory-controller@3d400000 { - compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc"; - reg = <0x3d400000 0x400000>; - clock-names = "core", "pll", "alt", "apb"; - clocks = <&clk IMX8MN_CLK_DRAM_CORE>, - <&clk IMX8MN_DRAM_PLL>, - <&clk IMX8MN_CLK_DRAM_ALT>, - <&clk IMX8MN_CLK_DRAM_APB>; - }; - - ddr-pmu@3d800000 { - compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; - reg = <0x3d800000 0x400000>; - interrupts = ; - }; - }; - - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; - assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; - clock-names = "main_clk"; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts deleted file mode 100644 index c13b4a02d..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ /dev/null @@ -1,270 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - */ - -/dts-v1/; - -#include "imx8mp.dtsi" - -/ { - model = "NXP i.MX8MPlus EVK board"; - compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; - - chosen { - stdout-path = &uart2; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; - - status { - label = "yellow:status"; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0xc0000000>, - <0x1 0x00000000 0 0xc0000000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - eee-broken-1000t; - reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - pca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart2 { - /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - bus-width = <4>; - status = "okay"; -}; - -&usdhc3 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec: fecgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 - MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f - MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f - MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f - MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f - MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f - MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h deleted file mode 100644 index 0fef06647..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h +++ /dev/null @@ -1,799 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 NXP - */ - -#ifndef __DTS_IMX8MP_PINFUNC_H -#define __DTS_IMX8MP_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ -#define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO02__ISP_FLASH_TRIG_0 0x01C 0x27C 0x000 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_ANY 0x01C 0x27C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO02__SJC_DE_B 0x01C 0x27C 0x000 0x7 0x0 -#define MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x020 0x280 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0x020 0x280 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO03__ISP_PRELIGHT_TRIG_0 0x020 0x280 0x000 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO03__SDMA1_EXT_EVENT00 0x020 0x280 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x024 0x284 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x024 0x284 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO04__ISP_SHUTTER_OPEN_0 0x024 0x284 0x000 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO04__SDMA1_EXT_EVENT01 0x024 0x284 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x028 0x288 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO05__M7_NMI 0x028 0x288 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO05__ISP_FL_TRIG_1 0x028 0x288 0x5D8 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO05__CCM_PMIC_READY 0x028 0x288 0x554 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x02C 0x28C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO06__ENET_QOS_MDC 0x02C 0x28C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO06__ISP_SHUTTER_TRIG_1 0x02C 0x28C 0x5E0 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO06__USDHC1_CD_B 0x02C 0x28C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO06__CCM_EXT_CLK3 0x02C 0x28C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x030 0x290 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO07__ENET_QOS_MDIO 0x030 0x290 0x590 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO07__ISP_FLASH_TRIG_1 0x030 0x290 0x000 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO07__USDHC1_WP 0x030 0x290 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO07__CCM_EXT_CLK4 0x030 0x290 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x034 0x294 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_IN 0x034 0x294 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO08__PWM1_OUT 0x034 0x294 0x000 0x2 0x0 -#define MX8MP_IOMUXC_GPIO1_IO08__ISP_PRELIGHT_TRIG_1 0x034 0x294 0x000 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_AUX_IN 0x034 0x294 0x000 0x4 0x0 -#define MX8MP_IOMUXC_GPIO1_IO08__USDHC2_RESET_B 0x034 0x294 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x038 0x298 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT 0x038 0x298 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x038 0x298 0x000 0x2 0x0 -#define MX8MP_IOMUXC_GPIO1_IO09__ISP_SHUTTER_OPEN_1 0x038 0x298 0x000 0x3 0x0 -#define MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x038 0x298 0x000 0x4 0x0 -#define MX8MP_IOMUXC_GPIO1_IO09__SDMA2_EXT_EVENT00 0x038 0x298 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x03C 0x29C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x03C 0x29C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x03C 0x29C 0x000 0x2 0x0 -#define MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x040 0x2A0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID 0x040 0x2A0 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x040 0x2A0 0x000 0x2 0x0 -#define MX8MP_IOMUXC_GPIO1_IO11__USDHC3_VSELECT 0x040 0x2A0 0x000 0x4 0x0 -#define MX8MP_IOMUXC_GPIO1_IO11__CCM_PMIC_READY 0x040 0x2A0 0x554 0x5 0x1 -#define MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x044 0x2A4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x044 0x2A4 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO12__SDMA2_EXT_EVENT01 0x044 0x2A4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x048 0x2A8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x048 0x2A8 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO13__PWM2_OUT 0x048 0x2A8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x04C 0x2AC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x04C 0x2AC 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO14__USDHC3_CD_B 0x04C 0x2AC 0x608 0x4 0x0 -#define MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT 0x04C 0x2AC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x04C 0x2AC 0x000 0x6 0x0 -#define MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x050 0x2B0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x050 0x2B0 0x000 0x1 0x0 -#define MX8MP_IOMUXC_GPIO1_IO15__USDHC3_WP 0x050 0x2B0 0x634 0x4 0x0 -#define MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT 0x050 0x2B0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x050 0x2B0 0x000 0x6 0x0 -#define MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x054 0x2B4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_MDC__AUDIOMIX_SAI6_TX_DATA00 0x054 0x2B4 0x000 0x2 0x0 -#define MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16 0x054 0x2B4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_MDC__USDHC3_STROBE 0x054 0x2B4 0x630 0x6 0x0 -#define MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x058 0x2B8 0x590 0x0 0x1 -#define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_SAI6_TX_SYNC 0x058 0x2B8 0x528 0x2 0x0 -#define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_PDM_BIT_STREAM03 0x058 0x2B8 0x4CC 0x3 0x0 -#define MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17 0x058 0x2B8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_MDIO__USDHC3_DATA5 0x058 0x2B8 0x624 0x6 0x0 -#define MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x05C 0x2BC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_SAI6_TX_BCLK 0x05C 0x2BC 0x524 0x2 0x0 -#define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_PDM_BIT_STREAM02 0x05C 0x2BC 0x4C8 0x3 0x0 -#define MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18 0x05C 0x2BC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_TD3__USDHC3_DATA6 0x05C 0x2BC 0x628 0x6 0x0 -#define MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x060 0x2C0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x060 0x2C0 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_SAI6_RX_DATA00 0x060 0x2C0 0x51C 0x2 0x0 -#define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_PDM_BIT_STREAM01 0x060 0x2C0 0x4C4 0x3 0x0 -#define MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19 0x060 0x2C0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_TD2__USDHC3_DATA7 0x060 0x2C0 0x62C 0x6 0x0 -#define MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x064 0x2C4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_SAI6_RX_SYNC 0x064 0x2C4 0x520 0x2 0x0 -#define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_PDM_BIT_STREAM00 0x064 0x2C4 0x4C0 0x3 0x0 -#define MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20 0x064 0x2C4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_TD1__USDHC3_CD_B 0x064 0x2C4 0x608 0x6 0x1 -#define MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x068 0x2C8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_SAI6_RX_BCLK 0x068 0x2C8 0x518 0x2 0x0 -#define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_PDM_CLK 0x068 0x2C8 0x000 0x3 0x0 -#define MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21 0x068 0x2C8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_TD0__USDHC3_WP 0x068 0x2C8 0x634 0x6 0x1 -#define MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x06C 0x2CC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SAI6_MCLK 0x06C 0x2CC 0x514 0x2 0x0 -#define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SPDIF1_OUT 0x06C 0x2CC 0x000 0x3 0x0 -#define MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22 0x06C 0x2CC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_TX_CTL__USDHC3_DATA0 0x06C 0x2CC 0x610 0x6 0x0 -#define MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x070 0x2D0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_TXC__ENET_QOS_TX_ER 0x070 0x2D0 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ENET_TXC__AUDIOMIX_SAI7_TX_DATA00 0x070 0x2D0 0x000 0x2 0x0 -#define MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23 0x070 0x2D0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_TXC__USDHC3_DATA1 0x070 0x2D0 0x614 0x6 0x0 -#define MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x074 0x2D4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_SAI7_TX_SYNC 0x074 0x2D4 0x540 0x2 0x0 -#define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_PDM_BIT_STREAM03 0x074 0x2D4 0x4CC 0x3 0x1 -#define MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 0x074 0x2D4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_RX_CTL__USDHC3_DATA2 0x074 0x2D4 0x618 0x6 0x0 -#define MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x078 0x2D8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x078 0x2D8 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_SAI7_TX_BCLK 0x078 0x2D8 0x53C 0x2 0x0 -#define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_PDM_BIT_STREAM02 0x078 0x2D8 0x4C8 0x3 0x1 -#define MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 0x078 0x2D8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_RXC__USDHC3_DATA3 0x078 0x2D8 0x61C 0x6 0x0 -#define MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x07C 0x2DC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_SAI7_RX_DATA00 0x07C 0x2DC 0x534 0x2 0x0 -#define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_PDM_BIT_STREAM01 0x07C 0x2DC 0x4C4 0x3 0x1 -#define MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 0x07C 0x2DC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_RD0__USDHC3_DATA4 0x07C 0x2DC 0x620 0x6 0x0 -#define MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x080 0x2E0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_SAI7_RX_SYNC 0x080 0x2E0 0x538 0x2 0x0 -#define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_PDM_BIT_STREAM00 0x080 0x2E0 0x4C0 0x3 0x1 -#define MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 0x080 0x2E0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_RD1__USDHC3_RESET_B 0x080 0x2E0 0x000 0x6 0x0 -#define MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x084 0x2E4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_SAI7_RX_BCLK 0x084 0x2E4 0x530 0x2 0x0 -#define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_PDM_CLK 0x084 0x2E4 0x000 0x3 0x0 -#define MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28 0x084 0x2E4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_RD2__USDHC3_CLK 0x084 0x2E4 0x604 0x6 0x0 -#define MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x088 0x2E8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SAI7_MCLK 0x088 0x2E8 0x52C 0x2 0x0 -#define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SPDIF1_IN 0x088 0x2E8 0x544 0x3 0x0 -#define MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 0x088 0x2E8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ENET_RD3__USDHC3_CMD 0x088 0x2E8 0x60C 0x6 0x0 -#define MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x08C 0x2EC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_CLK__ENET1_MDC 0x08C 0x2EC 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SD1_CLK__I2C5_SCL 0x08C 0x2EC 0x5C4 0x3 0x0 -#define MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x08C 0x2EC 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_CLK__UART1_DTE_RX 0x08C 0x2EC 0x5E8 0x4 0x0 -#define MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00 0x08C 0x2EC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x090 0x2F0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_CMD__ENET1_MDIO 0x090 0x2F0 0x57C 0x1 0x0 -#define MX8MP_IOMUXC_SD1_CMD__I2C5_SDA 0x090 0x2F0 0x5C8 0x3 0x0 -#define MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x090 0x2F0 0x5E8 0x4 0x1 -#define MX8MP_IOMUXC_SD1_CMD__UART1_DTE_TX 0x090 0x2F0 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01 0x090 0x2F0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x094 0x2F4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_DATA0__ENET1_RGMII_TD1 0x094 0x2F4 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x094 0x2F4 0x5CC 0x3 0x0 -#define MX8MP_IOMUXC_SD1_DATA0__UART1_DCE_RTS 0x094 0x2F4 0x5E4 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA0__UART1_DTE_CTS 0x094 0x2F4 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x094 0x2F4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x098 0x2F8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_DATA1__ENET1_RGMII_TD0 0x098 0x2F8 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x098 0x2F8 0x5D0 0x3 0x0 -#define MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 0x098 0x2F8 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA1__UART1_DTE_RTS 0x098 0x2F8 0x5E4 0x4 0x1 -#define MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x098 0x2F8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x09C 0x2FC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_DATA2__ENET1_RGMII_RD0 0x09C 0x2FC 0x580 0x1 0x0 -#define MX8MP_IOMUXC_SD1_DATA2__I2C4_SCL 0x09C 0x2FC 0x5BC 0x3 0x0 -#define MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x09C 0x2FC 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA2__UART2_DTE_RX 0x09C 0x2FC 0x5F0 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04 0x09C 0x2FC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x0A0 0x300 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_DATA3__ENET1_RGMII_RD1 0x0A0 0x300 0x584 0x1 0x0 -#define MX8MP_IOMUXC_SD1_DATA3__I2C4_SDA 0x0A0 0x300 0x5C0 0x3 0x0 -#define MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x0A0 0x300 0x5F0 0x4 0x1 -#define MX8MP_IOMUXC_SD1_DATA3__UART2_DTE_TX 0x0A0 0x300 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05 0x0A0 0x300 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x0A4 0x304 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_DATA4__ENET1_RGMII_TX_CTL 0x0A4 0x304 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL 0x0A4 0x304 0x5A4 0x3 0x0 -#define MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x0A4 0x304 0x5EC 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA4__UART2_DTE_CTS 0x0A4 0x304 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x0A4 0x304 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x0A8 0x308 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_DATA5__ENET1_TX_ER 0x0A8 0x308 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA 0x0A8 0x308 0x5A8 0x3 0x0 -#define MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x0A8 0x308 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA5__UART2_DTE_RTS 0x0A8 0x308 0x5EC 0x4 0x1 -#define MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x0A8 0x308 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x0AC 0x30C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_DATA6__ENET1_RGMII_RX_CTL 0x0AC 0x30C 0x588 0x1 0x0 -#define MX8MP_IOMUXC_SD1_DATA6__I2C2_SCL 0x0AC 0x30C 0x5AC 0x3 0x0 -#define MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x0AC 0x30C 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA6__UART3_DTE_RX 0x0AC 0x30C 0x5F8 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x0AC 0x30C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x0B0 0x310 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_DATA7__ENET1_RX_ER 0x0B0 0x310 0x58C 0x1 0x0 -#define MX8MP_IOMUXC_SD1_DATA7__I2C2_SDA 0x0B0 0x310 0x5B0 0x3 0x0 -#define MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x0B0 0x310 0x5F8 0x4 0x1 -#define MX8MP_IOMUXC_SD1_DATA7__UART3_DTE_TX 0x0B0 0x310 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x0B0 0x310 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x0B4 0x314 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_RESET_B__ENET1_TX_CLK 0x0B4 0x314 0x578 0x1 0x0 -#define MX8MP_IOMUXC_SD1_RESET_B__I2C3_SCL 0x0B4 0x314 0x5B4 0x3 0x0 -#define MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x0B4 0x314 0x5F4 0x4 0x0 -#define MX8MP_IOMUXC_SD1_RESET_B__UART3_DTE_CTS 0x0B4 0x314 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x0B4 0x314 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x0B8 0x318 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD1_STROBE__I2C3_SDA 0x0B8 0x318 0x5B8 0x3 0x0 -#define MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x0B8 0x318 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD1_STROBE__UART3_DTE_RTS 0x0B8 0x318 0x5F4 0x4 0x1 -#define MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x0B8 0x318 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x0BC 0x31C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0BC 0x31C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x0C0 0x320 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD2_CLK__ECSPI2_SCLK 0x0C0 0x320 0x568 0x2 0x0 -#define MX8MP_IOMUXC_SD2_CLK__UART4_DCE_RX 0x0C0 0x320 0x600 0x3 0x0 -#define MX8MP_IOMUXC_SD2_CLK__UART4_DTE_TX 0x0C0 0x320 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x0C0 0x320 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x0C4 0x324 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD2_CMD__ECSPI2_MOSI 0x0C4 0x324 0x570 0x2 0x0 -#define MX8MP_IOMUXC_SD2_CMD__UART4_DCE_TX 0x0C4 0x324 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SD2_CMD__UART4_DTE_RX 0x0C4 0x324 0x600 0x3 0x1 -#define MX8MP_IOMUXC_SD2_CMD__AUDIOMIX_PDM_CLK 0x0C4 0x324 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x0C4 0x324 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x0C8 0x328 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD2_DATA0__I2C4_SDA 0x0C8 0x328 0x5C0 0x2 0x1 -#define MX8MP_IOMUXC_SD2_DATA0__UART2_DCE_RX 0x0C8 0x328 0x5F0 0x3 0x2 -#define MX8MP_IOMUXC_SD2_DATA0__UART2_DTE_TX 0x0C8 0x328 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SD2_DATA0__AUDIOMIX_PDM_BIT_STREAM00 0x0C8 0x328 0x4C0 0x4 0x2 -#define MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x0C8 0x328 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x0CC 0x32C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD2_DATA1__I2C4_SCL 0x0CC 0x32C 0x5BC 0x2 0x1 -#define MX8MP_IOMUXC_SD2_DATA1__UART2_DCE_TX 0x0CC 0x32C 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SD2_DATA1__UART2_DTE_RX 0x0CC 0x32C 0x5F0 0x3 0x3 -#define MX8MP_IOMUXC_SD2_DATA1__AUDIOMIX_PDM_BIT_STREAM01 0x0CC 0x32C 0x4C4 0x4 0x2 -#define MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x0CC 0x32C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x0D0 0x330 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD2_DATA2__ECSPI2_SS0 0x0D0 0x330 0x574 0x2 0x0 -#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_SPDIF1_OUT 0x0D0 0x330 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_PDM_BIT_STREAM02 0x0D0 0x330 0x4C8 0x4 0x2 -#define MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x0D0 0x330 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x0D4 0x334 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD2_DATA3__ECSPI2_MISO 0x0D4 0x334 0x56C 0x2 0x0 -#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_SPDIF1_IN 0x0D4 0x334 0x544 0x3 0x1 -#define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_PDM_BIT_STREAM03 0x0D4 0x334 0x4CC 0x4 0x2 -#define MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x0D4 0x334 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_DATA3__SRC_EARLY_RESET 0x0D4 0x334 0x000 0x6 0x0 -#define MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x0D8 0x338 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0D8 0x338 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_RESET_B__SRC_SYSTEM_RESET 0x0D8 0x338 0x000 0x6 0x0 -#define MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x0DC 0x33C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x0DC 0x33C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SD2_WP__CORESIGHT_EVENTI 0x0DC 0x33C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_ALE__NAND_ALE 0x0E0 0x340 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x0E0 0x340 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_ALE__AUDIOMIX_SAI3_TX_BCLK 0x0E0 0x340 0x4E8 0x2 0x0 -#define MX8MP_IOMUXC_NAND_ALE__ISP_FL_TRIG_0 0x0E0 0x340 0x5D4 0x3 0x1 -#define MX8MP_IOMUXC_NAND_ALE__UART3_DCE_RX 0x0E0 0x340 0x5F8 0x4 0x2 -#define MX8MP_IOMUXC_NAND_ALE__UART3_DTE_TX 0x0E0 0x340 0x000 0x4 0x0 -#define MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x0E0 0x340 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_ALE__CORESIGHT_TRACE_CLK 0x0E0 0x340 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_CE0_B__NAND_CE0_B 0x0E4 0x344 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x0E4 0x344 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_CE0_B__AUDIOMIX_SAI3_TX_DATA00 0x0E4 0x344 0x000 0x2 0x0 -#define MX8MP_IOMUXC_NAND_CE0_B__ISP_SHUTTER_TRIG_0 0x0E4 0x344 0x5DC 0x3 0x1 -#define MX8MP_IOMUXC_NAND_CE0_B__UART3_DCE_TX 0x0E4 0x344 0x000 0x4 0x0 -#define MX8MP_IOMUXC_NAND_CE0_B__UART3_DTE_RX 0x0E4 0x344 0x5F8 0x4 0x3 -#define MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x0E4 0x344 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_CE0_B__CORESIGHT_TRACE_CTL 0x0E4 0x344 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_CE1_B__NAND_CE1_B 0x0E8 0x348 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_CE1_B__FLEXSPI_A_SS1_B 0x0E8 0x348 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x0E8 0x348 0x630 0x2 0x1 -#define MX8MP_IOMUXC_NAND_CE1_B__I2C4_SCL 0x0E8 0x348 0x5BC 0x4 0x2 -#define MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x0E8 0x348 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_CE1_B__CORESIGHT_TRACE00 0x0E8 0x348 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_CE2_B__NAND_CE2_B 0x0EC 0x34C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_CE2_B__FLEXSPI_B_SS0_B 0x0EC 0x34C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x0EC 0x34C 0x624 0x2 0x1 -#define MX8MP_IOMUXC_NAND_CE2_B__I2C4_SDA 0x0EC 0x34C 0x5C0 0x4 0x2 -#define MX8MP_IOMUXC_NAND_CE2_B__GPIO3_IO03 0x0EC 0x34C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_CE2_B__CORESIGHT_TRACE01 0x0EC 0x34C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_CE3_B__NAND_CE3_B 0x0F0 0x350 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_CE3_B__FLEXSPI_B_SS1_B 0x0F0 0x350 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x0F0 0x350 0x628 0x2 0x1 -#define MX8MP_IOMUXC_NAND_CE3_B__I2C3_SDA 0x0F0 0x350 0x5B8 0x4 0x1 -#define MX8MP_IOMUXC_NAND_CE3_B__GPIO3_IO04 0x0F0 0x350 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_CE3_B__CORESIGHT_TRACE02 0x0F0 0x350 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_CLE__NAND_CLE 0x0F4 0x354 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_CLE__FLEXSPI_B_SCLK 0x0F4 0x354 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x0F4 0x354 0x62C 0x2 0x1 -#define MX8MP_IOMUXC_NAND_CLE__UART4_DCE_RX 0x0F4 0x354 0x600 0x4 0x2 -#define MX8MP_IOMUXC_NAND_CLE__UART4_DTE_TX 0x0F4 0x354 0x000 0x4 0x0 -#define MX8MP_IOMUXC_NAND_CLE__GPIO3_IO05 0x0F4 0x354 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_CLE__CORESIGHT_TRACE03 0x0F4 0x354 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA00__NAND_DATA00 0x0F8 0x358 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x0F8 0x358 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_DATA00__AUDIOMIX_SAI3_RX_DATA00 0x0F8 0x358 0x4E4 0x2 0x0 -#define MX8MP_IOMUXC_NAND_DATA00__ISP_FLASH_TRIG_0 0x0F8 0x358 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA00__UART4_DCE_RX 0x0F8 0x358 0x600 0x4 0x3 -#define MX8MP_IOMUXC_NAND_DATA00__UART4_DTE_TX 0x0F8 0x358 0x000 0x4 0x0 -#define MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x0F8 0x358 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_DATA00__CORESIGHT_TRACE04 0x0F8 0x358 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA01__NAND_DATA01 0x0FC 0x35C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x0FC 0x35C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC 0x0FC 0x35C 0x4EC 0x2 0x0 -#define MX8MP_IOMUXC_NAND_DATA01__ISP_PRELIGHT_TRIG_0 0x0FC 0x35C 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA01__UART4_DCE_TX 0x0FC 0x35C 0x000 0x4 0x0 -#define MX8MP_IOMUXC_NAND_DATA01__UART4_DTE_RX 0x0FC 0x35C 0x600 0x4 0x4 -#define MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x0FC 0x35C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_DATA01__CORESIGHT_TRACE05 0x0FC 0x35C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA02__NAND_DATA02 0x100 0x360 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x100 0x360 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_DATA02__USDHC3_CD_B 0x100 0x360 0x608 0x2 0x2 -#define MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x100 0x360 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA02__UART4_DTE_RTS 0x100 0x360 0x5FC 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA02__I2C4_SDA 0x100 0x360 0x5C0 0x4 0x3 -#define MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x100 0x360 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_DATA02__CORESIGHT_TRACE06 0x100 0x360 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA03__NAND_DATA03 0x104 0x364 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x104 0x364 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_DATA03__USDHC3_WP 0x104 0x364 0x634 0x2 0x2 -#define MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS 0x104 0x364 0x5FC 0x3 0x1 -#define MX8MP_IOMUXC_NAND_DATA03__UART4_DTE_CTS 0x104 0x364 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA03__ISP_FL_TRIG_1 0x104 0x364 0x5D8 0x4 0x1 -#define MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x104 0x364 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_DATA03__CORESIGHT_TRACE07 0x104 0x364 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA04__NAND_DATA04 0x108 0x368 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_B_DATA00 0x108 0x368 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x108 0x368 0x610 0x2 0x1 -#define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_A_DATA04 0x108 0x368 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA04__ISP_SHUTTER_TRIG_1 0x108 0x368 0x5E0 0x4 0x1 -#define MX8MP_IOMUXC_NAND_DATA04__GPIO3_IO10 0x108 0x368 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_DATA04__CORESIGHT_TRACE08 0x108 0x368 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA05__NAND_DATA05 0x10C 0x36C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_B_DATA01 0x10C 0x36C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x10C 0x36C 0x614 0x2 0x1 -#define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_A_DATA05 0x10C 0x36C 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA05__ISP_FLASH_TRIG_1 0x10C 0x36C 0x000 0x4 0x0 -#define MX8MP_IOMUXC_NAND_DATA05__GPIO3_IO11 0x10C 0x36C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_DATA05__CORESIGHT_TRACE09 0x10C 0x36C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA06__NAND_DATA06 0x110 0x370 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_B_DATA02 0x110 0x370 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x110 0x370 0x618 0x2 0x1 -#define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_A_DATA06 0x110 0x370 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA06__ISP_PRELIGHT_TRIG_1 0x110 0x370 0x000 0x4 0x0 -#define MX8MP_IOMUXC_NAND_DATA06__GPIO3_IO12 0x110 0x370 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_DATA06__CORESIGHT_TRACE10 0x110 0x370 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DATA07__NAND_DATA07 0x114 0x374 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_B_DATA03 0x114 0x374 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x114 0x374 0x61C 0x2 0x1 -#define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_A_DATA07 0x114 0x374 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DATA07__ISP_SHUTTER_OPEN_1 0x114 0x374 0x000 0x4 0x0 -#define MX8MP_IOMUXC_NAND_DATA07__GPIO3_IO13 0x114 0x374 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_DATA07__CORESIGHT_TRACE11 0x114 0x374 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_DQS__NAND_DQS 0x118 0x378 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x118 0x378 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_DQS__AUDIOMIX_SAI3_MCLK 0x118 0x378 0x4E0 0x2 0x0 -#define MX8MP_IOMUXC_NAND_DQS__ISP_SHUTTER_OPEN_0 0x118 0x378 0x000 0x3 0x0 -#define MX8MP_IOMUXC_NAND_DQS__I2C3_SCL 0x118 0x378 0x5B4 0x4 0x1 -#define MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x118 0x378 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_DQS__CORESIGHT_TRACE12 0x118 0x378 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_RE_B__NAND_RE_B 0x11C 0x37C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_RE_B__FLEXSPI_B_DQS 0x11C 0x37C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x11C 0x37C 0x620 0x2 0x1 -#define MX8MP_IOMUXC_NAND_RE_B__UART4_DCE_TX 0x11C 0x37C 0x000 0x4 0x0 -#define MX8MP_IOMUXC_NAND_RE_B__UART4_DTE_RX 0x11C 0x37C 0x600 0x4 0x5 -#define MX8MP_IOMUXC_NAND_RE_B__GPIO3_IO15 0x11C 0x37C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_RE_B__CORESIGHT_TRACE13 0x11C 0x37C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_READY_B__NAND_READY_B 0x120 0x380 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x120 0x380 0x000 0x2 0x0 -#define MX8MP_IOMUXC_NAND_READY_B__I2C3_SCL 0x120 0x380 0x5B4 0x4 0x2 -#define MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x120 0x380 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_READY_B__CORESIGHT_TRACE14 0x120 0x380 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_WE_B__NAND_WE_B 0x124 0x384 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x124 0x384 0x604 0x2 0x1 -#define MX8MP_IOMUXC_NAND_WE_B__I2C3_SDA 0x124 0x384 0x5B8 0x4 0x2 -#define MX8MP_IOMUXC_NAND_WE_B__GPIO3_IO17 0x124 0x384 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_WE_B__CORESIGHT_TRACE15 0x124 0x384 0x000 0x6 0x0 -#define MX8MP_IOMUXC_NAND_WP_B__NAND_WP_B 0x128 0x388 0x000 0x0 0x0 -#define MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x128 0x388 0x60C 0x2 0x1 -#define MX8MP_IOMUXC_NAND_WP_B__I2C4_SCL 0x128 0x388 0x5BC 0x4 0x3 -#define MX8MP_IOMUXC_NAND_WP_B__GPIO3_IO18 0x128 0x388 0x000 0x5 0x0 -#define MX8MP_IOMUXC_NAND_WP_B__CORESIGHT_EVENTO 0x128 0x388 0x000 0x6 0x0 -#define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x12C 0x38C 0x508 0x0 0x0 -#define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x12C 0x38C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x12C 0x38C 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x12C 0x38C 0x5CC 0x3 0x1 -#define MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x12C 0x38C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI5_RX_BCLK 0x130 0x390 0x4F4 0x0 0x0 -#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI1_TX_DATA01 0x130 0x390 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x130 0x390 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x130 0x390 0x5D0 0x3 0x1 -#define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0x130 0x390 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x130 0x390 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x134 0x394 0x4F8 0x0 0x0 -#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI1_TX_DATA02 0x134 0x394 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x134 0x394 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x134 0x394 0x5C4 0x3 0x1 -#define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0x134 0x394 0x4C0 0x4 0x3 -#define MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x134 0x394 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01 0x138 0x398 0x4FC 0x0 0x0 -#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_DATA03 0x138 0x398 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x138 0x398 0x4D8 0x2 0x0 -#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x138 0x398 0x510 0x3 0x0 -#define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0x138 0x398 0x4C4 0x4 0x3 -#define MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x138 0x398 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x138 0x398 0x000 0x6 0x0 -#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_RX_DATA02 0x13C 0x39C 0x500 0x0 0x0 -#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_DATA04 0x13C 0x39C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_SYNC 0x13C 0x39C 0x4D8 0x2 0x1 -#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x13C 0x39C 0x50C 0x3 0x0 -#define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0x13C 0x39C 0x4C8 0x4 0x3 -#define MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x13C 0x39C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x13C 0x39C 0x54C 0x6 0x0 -#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_RX_DATA03 0x140 0x3A0 0x504 0x0 0x0 -#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_DATA05 0x140 0x3A0 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_SYNC 0x140 0x3A0 0x4D8 0x2 0x2 -#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0x140 0x3A0 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0x140 0x3A0 0x4CC 0x4 0x3 -#define MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x140 0x3A0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x140 0x3A0 0x000 0x6 0x0 -#define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x144 0x3A4 0x4F0 0x0 0x0 -#define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x144 0x3A4 0x4D4 0x1 0x0 -#define MX8MP_IOMUXC_SAI5_MCLK__PWM1_OUT 0x144 0x3A4 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 0x144 0x3A4 0x5C8 0x3 0x1 -#define MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x144 0x3A4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x144 0x3A4 0x550 0x6 0x0 -#define MX8MP_IOMUXC_SAI1_RXFS__AUDIOMIX_SAI1_RX_SYNC 0x148 0x3A8 0x4D0 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x148 0x3A8 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x148 0x3A8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_SAI1_RX_BCLK 0x14C 0x3AC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_PDM_CLK 0x14C 0x3AC 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x14C 0x3AC 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x14C 0x3AC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x150 0x3B0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_TX_DATA01 0x150 0x3B0 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0x150 0x3B0 0x4C0 0x3 0x4 -#define MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x150 0x3B0 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x150 0x3B0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01 0x154 0x3B4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0x154 0x3B4 0x4C4 0x3 0x4 -#define MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x154 0x3B4 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x154 0x3B4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02 0x158 0x3B8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0x158 0x3B8 0x4C8 0x3 0x4 -#define MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x158 0x3B8 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x158 0x3B8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI1_RX_DATA03 0x15C 0x3BC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0x15C 0x3BC 0x4CC 0x3 0x4 -#define MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x15C 0x3BC 0x57C 0x4 0x1 -#define MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x15C 0x3BC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI1_RX_DATA04 0x160 0x3C0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_TX_BCLK 0x160 0x3C0 0x524 0x1 0x1 -#define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_RX_BCLK 0x160 0x3C0 0x518 0x2 0x1 -#define MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x160 0x3C0 0x580 0x4 0x1 -#define MX8MP_IOMUXC_SAI1_RXD4__GPIO4_IO06 0x160 0x3C0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_RX_DATA05 0x164 0x3C4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_TX_DATA00 0x164 0x3C4 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_RX_DATA00 0x164 0x3C4 0x51C 0x2 0x1 -#define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_RX_SYNC 0x164 0x3C4 0x4D0 0x3 0x1 -#define MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x164 0x3C4 0x584 0x4 0x1 -#define MX8MP_IOMUXC_SAI1_RXD5__GPIO4_IO07 0x164 0x3C4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI1_RX_DATA06 0x168 0x3C8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_TX_SYNC 0x168 0x3C8 0x528 0x1 0x1 -#define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_RX_SYNC 0x168 0x3C8 0x520 0x2 0x1 -#define MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x168 0x3C8 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x168 0x3C8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_RX_DATA07 0x16C 0x3CC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI6_MCLK 0x16C 0x3CC 0x514 0x1 0x1 -#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_TX_SYNC 0x16C 0x3CC 0x4D8 0x2 0x3 -#define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_TX_DATA04 0x16C 0x3CC 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x16C 0x3CC 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x16C 0x3CC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC 0x170 0x3D0 0x4D8 0x0 0x4 -#define MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x170 0x3D0 0x588 0x4 0x1 -#define MX8MP_IOMUXC_SAI1_TXFS__GPIO4_IO10 0x170 0x3D0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK 0x174 0x3D4 0x4D4 0x0 0x1 -#define MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x174 0x3D4 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x174 0x3D4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 0x178 0x3D8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x178 0x3D8 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x178 0x3D8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 0x17C 0x3DC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x17C 0x3DC 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x17C 0x3DC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 0x180 0x3E0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x180 0x3E0 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x180 0x3E0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 0x184 0x3E4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x184 0x3E4 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x184 0x3E4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 0x188 0x3E8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_RX_BCLK 0x188 0x3E8 0x518 0x1 0x2 -#define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_TX_BCLK 0x188 0x3E8 0x524 0x2 0x2 -#define MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x188 0x3E8 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x188 0x3E8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 0x18C 0x3EC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_RX_DATA00 0x18C 0x3EC 0x51C 0x1 0x2 -#define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_TX_DATA00 0x18C 0x3EC 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x18C 0x3EC 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x18C 0x3EC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 0x190 0x3F0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_RX_SYNC 0x190 0x3F0 0x520 0x1 0x2 -#define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_TX_SYNC 0x190 0x3F0 0x528 0x2 0x2 -#define MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x190 0x3F0 0x58C 0x4 0x1 -#define MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x190 0x3F0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 0x194 0x3F4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI6_MCLK 0x194 0x3F4 0x514 0x1 0x2 -#define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_PDM_CLK 0x194 0x3F4 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SAI1_TXD7__ENET1_TX_ER 0x194 0x3F4 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x194 0x3F4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x198 0x3F8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x198 0x3F8 0x4D4 0x2 0x2 -#define MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x198 0x3F8 0x578 0x4 0x1 -#define MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x198 0x3F8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_SYNC 0x19C 0x3FC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC 0x19C 0x3FC 0x510 0x1 0x2 -#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_DATA01 0x19C 0x3FC 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x19C 0x3FC 0x4DC 0x3 0x0 -#define MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x19C 0x3FC 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI2_RXFS__UART1_DTE_RX 0x19C 0x3FC 0x5E8 0x4 0x2 -#define MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x19C 0x3FC 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_PDM_BIT_STREAM02 0x19C 0x3FC 0x4C8 0x6 0x5 -#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK 0x1A0 0x400 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK 0x1A0 0x400 0x50C 0x1 0x2 -#define MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x1A0 0x400 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x1A0 0x400 0x5E8 0x4 0x3 -#define MX8MP_IOMUXC_SAI2_RXC__UART1_DTE_TX 0x1A0 0x400 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1A0 0x400 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_PDM_BIT_STREAM01 0x1A0 0x400 0x4C4 0x6 0x5 -#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0x1A4 0x404 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x1A4 0x404 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x1A4 0x404 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_TX_DATA01 0x1A4 0x404 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1A4 0x404 0x5E4 0x4 0x2 -#define MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 0x1A4 0x404 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x1A4 0x404 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_PDM_BIT_STREAM03 0x1A4 0x404 0x4CC 0x6 0x5 -#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0x1A8 0x408 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI5_TX_DATA01 0x1A8 0x408 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI2_TXFS__ENET_QOS_1588_EVENT3_OUT 0x1A8 0x408 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1A8 0x408 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1A8 0x408 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 0x1A8 0x408 0x5E4 0x4 0x3 -#define MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x1A8 0x408 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_PDM_BIT_STREAM02 0x1A8 0x408 0x4C8 0x6 0x6 -#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0x1AC 0x40C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI5_TX_DATA02 0x1AC 0x40C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x1AC 0x40C 0x54C 0x3 0x1 -#define MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1AC 0x40C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_PDM_BIT_STREAM01 0x1AC 0x40C 0x4C4 0x6 0x6 -#define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0x1B0 0x410 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI5_TX_DATA03 0x1B0 0x410 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1B0 0x410 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x1B0 0x410 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_AUX_IN 0x1B0 0x410 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x1B0 0x410 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0x1B4 0x414 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI5_MCLK 0x1B4 0x414 0x4F0 0x1 0x2 -#define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_IN 0x1B4 0x414 0x000 0x2 0x0 -#define MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x1B4 0x414 0x550 0x3 0x1 -#define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_AUX_IN 0x1B4 0x414 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x1B4 0x414 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI3_MCLK 0x1B4 0x414 0x4E0 0x6 0x1 -#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0x1B8 0x418 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x1B8 0x418 0x4DC 0x1 0x1 -#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x1B8 0x418 0x508 0x2 0x2 -#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01 0x1B8 0x418 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SPDIF1_IN 0x1B8 0x418 0x544 0x4 0x2 -#define MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1B8 0x418 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00 0x1B8 0x418 0x4C0 0x6 0x5 -#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0x1BC 0x41C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI2_RX_DATA02 0x1BC 0x41C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK 0x1BC 0x41C 0x4F4 0x2 0x2 -#define MX8MP_IOMUXC_SAI3_RXC__GPT1_CLK 0x1BC 0x41C 0x59C 0x3 0x0 -#define MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x1BC 0x41C 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI3_RXC__UART2_DTE_RTS 0x1BC 0x41C 0x5EC 0x4 0x2 -#define MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1BC 0x41C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CLK 0x1BC 0x41C 0x000 0x6 0x0 -#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1C0 0x420 0x4E4 0x0 0x1 -#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI2_RX_DATA03 0x1C0 0x420 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 0x1C0 0x420 0x4F8 0x2 0x2 -#define MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x1C0 0x420 0x5EC 0x4 0x3 -#define MX8MP_IOMUXC_SAI3_RXD__UART2_DTE_CTS 0x1C0 0x420 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x1C0 0x420 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_PDM_BIT_STREAM01 0x1C0 0x420 0x4C4 0x6 0x7 -#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1C4 0x424 0x4EC 0x0 0x1 -#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1C4 0x424 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI5_RX_DATA01 0x1C4 0x424 0x4FC 0x2 0x2 -#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_DATA01 0x1C4 0x424 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX 0x1C4 0x424 0x5F0 0x4 0x4 -#define MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX 0x1C4 0x424 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x1C4 0x424 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_PDM_BIT_STREAM03 0x1C4 0x424 0x4CC 0x6 0x6 -#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1C8 0x428 0x4E8 0x0 0x1 -#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI2_TX_DATA02 0x1C8 0x428 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI5_RX_DATA02 0x1C8 0x428 0x500 0x2 0x2 -#define MX8MP_IOMUXC_SAI3_TXC__GPT1_CAPTURE1 0x1C8 0x428 0x594 0x3 0x0 -#define MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX 0x1C8 0x428 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX 0x1C8 0x428 0x5F0 0x4 0x5 -#define MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x1C8 0x428 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_PDM_BIT_STREAM02 0x1C8 0x428 0x4C8 0x6 0x7 -#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x1CC 0x42C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI2_TX_DATA03 0x1CC 0x42C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI5_RX_DATA03 0x1CC 0x42C 0x504 0x2 0x2 -#define MX8MP_IOMUXC_SAI3_TXD__GPT1_CAPTURE2 0x1CC 0x42C 0x598 0x3 0x0 -#define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SPDIF1_EXT_CLK 0x1CC 0x42C 0x548 0x4 0x0 -#define MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x1CC 0x42C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0x1D0 0x430 0x4E0 0x0 0x2 -#define MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x1D0 0x430 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI5_MCLK 0x1D0 0x430 0x4F0 0x2 0x3 -#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF1_OUT 0x1D0 0x430 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1D0 0x430 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF1_IN 0x1D0 0x430 0x544 0x6 0x3 -#define MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF1_OUT 0x1D4 0x434 0x000 0x0 0x0 -#define MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x1D4 0x434 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x1D4 0x434 0x5C4 0x2 0x2 -#define MX8MP_IOMUXC_SPDIF_TX__GPT1_COMPARE1 0x1D4 0x434 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x1D4 0x434 0x000 0x4 0x0 -#define MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x1D4 0x434 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF1_IN 0x1D8 0x438 0x544 0x0 0x4 -#define MX8MP_IOMUXC_SPDIF_RX__PWM2_OUT 0x1D8 0x438 0x000 0x1 0x0 -#define MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x1D8 0x438 0x5C8 0x2 0x2 -#define MX8MP_IOMUXC_SPDIF_RX__GPT1_COMPARE2 0x1D8 0x438 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x1D8 0x438 0x54C 0x4 0x2 -#define MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1D8 0x438 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPT1_COMPARE3 0x1DC 0x43C 0x000 0x3 0x0 -#define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x1DC 0x43C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF1_EXT_CLK 0x1DC 0x43C 0x548 0x0 0x1 -#define MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x1DC 0x43C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1E0 0x440 0x558 0x0 0x0 -#define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x1E0 0x440 0x5F8 0x1 0x4 -#define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DTE_TX 0x1E0 0x440 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ECSPI1_SCLK__I2C1_SCL 0x1E0 0x440 0x5A4 0x2 0x1 -#define MX8MP_IOMUXC_ECSPI1_SCLK__AUDIOMIX_SAI7_RX_SYNC 0x1E0 0x440 0x538 0x3 0x1 -#define MX8MP_IOMUXC_ECSPI1_SCLK__GPIO5_IO06 0x1E0 0x440 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1E4 0x444 0x560 0x0 0x0 -#define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x1E4 0x444 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DTE_RX 0x1E4 0x444 0x5F8 0x1 0x5 -#define MX8MP_IOMUXC_ECSPI1_MOSI__I2C1_SDA 0x1E4 0x444 0x5A8 0x2 0x1 -#define MX8MP_IOMUXC_ECSPI1_MOSI__AUDIOMIX_SAI7_RX_BCLK 0x1E4 0x444 0x530 0x3 0x1 -#define MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07 0x1E4 0x444 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1E8 0x448 0x55C 0x0 0x0 -#define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x1E8 0x448 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DTE_RTS 0x1E8 0x448 0x5F4 0x1 0x2 -#define MX8MP_IOMUXC_ECSPI1_MISO__I2C2_SCL 0x1E8 0x448 0x5AC 0x2 0x1 -#define MX8MP_IOMUXC_ECSPI1_MISO__AUDIOMIX_SAI7_RX_DATA00 0x1E8 0x448 0x534 0x3 0x1 -#define MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x1E8 0x448 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0 0x1EC 0x44C 0x564 0x0 0x0 -#define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x1EC 0x44C 0x5F4 0x1 0x3 -#define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DTE_CTS 0x1EC 0x44C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ECSPI1_SS0__I2C2_SDA 0x1EC 0x44C 0x5B0 0x2 0x1 -#define MX8MP_IOMUXC_ECSPI1_SS0__AUDIOMIX_SAI7_TX_SYNC 0x1EC 0x44C 0x540 0x3 0x1 -#define MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1EC 0x44C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1F0 0x450 0x568 0x0 0x1 -#define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1F0 0x450 0x600 0x1 0x6 -#define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DTE_TX 0x1F0 0x450 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ECSPI2_SCLK__I2C3_SCL 0x1F0 0x450 0x5B4 0x2 0x3 -#define MX8MP_IOMUXC_ECSPI2_SCLK__AUDIOMIX_SAI7_TX_BCLK 0x1F0 0x450 0x53C 0x3 0x1 -#define MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1F0 0x450 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1F4 0x454 0x570 0x0 0x1 -#define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1F4 0x454 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DTE_RX 0x1F4 0x454 0x600 0x1 0x7 -#define MX8MP_IOMUXC_ECSPI2_MOSI__I2C3_SDA 0x1F4 0x454 0x5B8 0x2 0x3 -#define MX8MP_IOMUXC_ECSPI2_MOSI__AUDIOMIX_SAI7_TX_DATA00 0x1F4 0x454 0x000 0x3 0x0 -#define MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1F4 0x454 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1F8 0x458 0x000 0x5 0x0 -#define MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1F8 0x458 0x56C 0x0 0x1 -#define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1F8 0x458 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DTE_RTS 0x1F8 0x458 0x5FC 0x1 0x2 -#define MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x1F8 0x458 0x5BC 0x2 0x4 -#define MX8MP_IOMUXC_ECSPI2_MISO__AUDIOMIX_SAI7_MCLK 0x1F8 0x458 0x52C 0x3 0x1 -#define MX8MP_IOMUXC_ECSPI2_MISO__CCM_CLKO1 0x1F8 0x458 0x000 0x4 0x0 -#define MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x1FC 0x45C 0x574 0x0 0x1 -#define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1FC 0x45C 0x5FC 0x1 0x3 -#define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DTE_CTS 0x1FC 0x45C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x1FC 0x45C 0x5C0 0x2 0x4 -#define MX8MP_IOMUXC_ECSPI2_SS0__CCM_CLKO2 0x1FC 0x45C 0x000 0x4 0x0 -#define MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1FC 0x45C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x200 0x460 0x5A4 0x0 0x2 -#define MX8MP_IOMUXC_I2C1_SCL__ENET_QOS_MDC 0x200 0x460 0x000 0x1 0x0 -#define MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x200 0x460 0x558 0x3 0x1 -#define MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x200 0x460 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x204 0x464 0x5A8 0x0 0x2 -#define MX8MP_IOMUXC_I2C1_SDA__ENET_QOS_MDIO 0x204 0x464 0x590 0x1 0x2 -#define MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x204 0x464 0x560 0x3 0x1 -#define MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x204 0x464 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x208 0x468 0x5AC 0x0 0x2 -#define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_IN 0x208 0x468 0x000 0x1 0x0 -#define MX8MP_IOMUXC_I2C2_SCL__USDHC3_CD_B 0x208 0x468 0x608 0x2 0x3 -#define MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x208 0x468 0x55C 0x3 0x1 -#define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_AUX_IN 0x208 0x468 0x000 0x4 0x0 -#define MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x208 0x468 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x20C 0x46C 0x5B0 0x0 0x2 -#define MX8MP_IOMUXC_I2C2_SDA__ENET_QOS_1588_EVENT1_OUT 0x20C 0x46C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_I2C2_SDA__USDHC3_WP 0x20C 0x46C 0x634 0x2 0x3 -#define MX8MP_IOMUXC_I2C2_SDA__ECSPI1_SS0 0x20C 0x46C 0x564 0x3 0x1 -#define MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x20C 0x46C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x210 0x470 0x5B4 0x0 0x4 -#define MX8MP_IOMUXC_I2C3_SCL__PWM4_OUT 0x210 0x470 0x000 0x1 0x0 -#define MX8MP_IOMUXC_I2C3_SCL__GPT2_CLK 0x210 0x470 0x000 0x2 0x0 -#define MX8MP_IOMUXC_I2C3_SCL__ECSPI2_SCLK 0x210 0x470 0x568 0x3 0x2 -#define MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x210 0x470 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x214 0x474 0x5B8 0x0 0x4 -#define MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x214 0x474 0x000 0x1 0x0 -#define MX8MP_IOMUXC_I2C3_SDA__GPT3_CLK 0x214 0x474 0x000 0x2 0x0 -#define MX8MP_IOMUXC_I2C3_SDA__ECSPI2_MOSI 0x214 0x474 0x570 0x3 0x2 -#define MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x214 0x474 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x218 0x478 0x5BC 0x0 0x5 -#define MX8MP_IOMUXC_I2C4_SCL__PWM2_OUT 0x218 0x478 0x000 0x1 0x0 -#define MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x218 0x478 0x5A0 0x2 0x0 -#define MX8MP_IOMUXC_I2C4_SCL__ECSPI2_MISO 0x218 0x478 0x56C 0x3 0x2 -#define MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x218 0x478 0x000 0x5 0x0 -#define MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x21C 0x47C 0x5C0 0x0 0x5 -#define MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT 0x21C 0x47C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_I2C4_SDA__ECSPI2_SS0 0x21C 0x47C 0x574 0x3 0x2 -#define MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x21C 0x47C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x220 0x480 0x5E8 0x0 0x4 -#define MX8MP_IOMUXC_UART1_RXD__UART1_DTE_TX 0x220 0x480 0x000 0x0 0x0 -#define MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x220 0x480 0x000 0x1 0x0 -#define MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x220 0x480 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x224 0x484 0x000 0x0 0x0 -#define MX8MP_IOMUXC_UART1_TXD__UART1_DTE_RX 0x224 0x484 0x5E8 0x0 0x5 -#define MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x224 0x484 0x000 0x1 0x0 -#define MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x224 0x484 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x228 0x488 0x5F0 0x0 0x6 -#define MX8MP_IOMUXC_UART2_RXD__UART2_DTE_TX 0x228 0x488 0x000 0x0 0x0 -#define MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x228 0x488 0x000 0x1 0x0 -#define MX8MP_IOMUXC_UART2_RXD__GPT1_COMPARE3 0x228 0x488 0x000 0x3 0x0 -#define MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24 0x228 0x488 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x22C 0x48C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_UART2_TXD__UART2_DTE_RX 0x22C 0x48C 0x5F0 0x0 0x7 -#define MX8MP_IOMUXC_UART2_TXD__ECSPI3_SS0 0x22C 0x48C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_UART2_TXD__GPT1_COMPARE2 0x22C 0x48C 0x000 0x3 0x0 -#define MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x22C 0x48C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x230 0x490 0x5F8 0x0 0x6 -#define MX8MP_IOMUXC_UART3_RXD__UART3_DTE_TX 0x230 0x490 0x000 0x0 0x0 -#define MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x230 0x490 0x000 0x1 0x0 -#define MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS 0x230 0x490 0x5E4 0x1 0x4 -#define MX8MP_IOMUXC_UART3_RXD__USDHC3_RESET_B 0x230 0x490 0x000 0x2 0x0 -#define MX8MP_IOMUXC_UART3_RXD__GPT1_CAPTURE2 0x230 0x490 0x598 0x3 0x1 -#define MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x230 0x490 0x000 0x4 0x0 -#define MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x230 0x490 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x234 0x494 0x000 0x0 0x0 -#define MX8MP_IOMUXC_UART3_TXD__UART3_DTE_RX 0x234 0x494 0x5F8 0x0 0x7 -#define MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x234 0x494 0x5E4 0x1 0x5 -#define MX8MP_IOMUXC_UART3_TXD__UART1_DTE_CTS 0x234 0x494 0x000 0x1 0x0 -#define MX8MP_IOMUXC_UART3_TXD__USDHC3_VSELECT 0x234 0x494 0x000 0x2 0x0 -#define MX8MP_IOMUXC_UART3_TXD__GPT1_CLK 0x234 0x494 0x59C 0x3 0x1 -#define MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x234 0x494 0x550 0x4 0x2 -#define MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x234 0x494 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x238 0x498 0x600 0x0 0x8 -#define MX8MP_IOMUXC_UART4_RXD__UART4_DTE_TX 0x238 0x498 0x000 0x0 0x0 -#define MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS 0x238 0x498 0x000 0x1 0x0 -#define MX8MP_IOMUXC_UART4_RXD__UART2_DTE_RTS 0x238 0x498 0x5EC 0x1 0x4 -#define MX8MP_IOMUXC_UART4_RXD__PCIE_CLKREQ_B 0x238 0x498 0x5A0 0x2 0x1 -#define MX8MP_IOMUXC_UART4_RXD__GPT1_COMPARE1 0x238 0x498 0x000 0x3 0x0 -#define MX8MP_IOMUXC_UART4_RXD__I2C6_SCL 0x238 0x498 0x5CC 0x4 0x2 -#define MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x238 0x498 0x000 0x5 0x0 -#define MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x23C 0x49C 0x000 0x0 0x0 -#define MX8MP_IOMUXC_UART4_TXD__UART4_DTE_RX 0x23C 0x49C 0x600 0x0 0x9 -#define MX8MP_IOMUXC_UART4_TXD__UART2_DCE_RTS 0x23C 0x49C 0x5EC 0x1 0x5 -#define MX8MP_IOMUXC_UART4_TXD__UART2_DTE_CTS 0x23C 0x49C 0x000 0x1 0x0 -#define MX8MP_IOMUXC_UART4_TXD__GPT1_CAPTURE1 0x23C 0x49C 0x594 0x3 0x1 -#define MX8MP_IOMUXC_UART4_TXD__I2C6_SDA 0x23C 0x49C 0x5D0 0x4 0x2 -#define MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x23C 0x49C 0x000 0x5 0x0 -#define MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x240 0x4A0 0x000 0x0 0x0 -#define MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x240 0x4A0 0x5C4 0x3 0x3 -#define MX8MP_IOMUXC_HDMI_DDC_SCL__CAN1_TX 0x240 0x4A0 0x000 0x4 0x0 -#define MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x240 0x4A0 0x000 0x5 0x0 -#define MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x244 0x4A4 0x000 0x0 0x0 -#define MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x244 0x4A4 0x5C8 0x3 0x3 -#define MX8MP_IOMUXC_HDMI_DDC_SDA__CAN1_RX 0x244 0x4A4 0x54C 0x4 0x3 -#define MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x244 0x4A4 0x000 0x5 0x0 -#define MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x248 0x4A8 0x000 0x0 0x0 -#define MX8MP_IOMUXC_HDMI_CEC__I2C6_SCL 0x248 0x4A8 0x5CC 0x3 0x3 -#define MX8MP_IOMUXC_HDMI_CEC__CAN2_TX 0x248 0x4A8 0x000 0x4 0x0 -#define MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28 0x248 0x4A8 0x000 0x5 0x0 -#define MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x24C 0x4AC 0x000 0x0 0x0 -#define MX8MP_IOMUXC_HDMI_HPD__AUDIOMIX_HDMI_HPD_O 0x24C 0x4AC 0x000 0x1 0x0 -#define MX8MP_IOMUXC_HDMI_HPD__I2C6_SDA 0x24C 0x4AC 0x5D0 0x3 0x3 -#define MX8MP_IOMUXC_HDMI_HPD__CAN2_RX 0x24C 0x4AC 0x550 0x4 0x3 -#define MX8MP_IOMUXC_HDMI_HPD__GPIO3_IO29 0x24C 0x4AC 0x000 0x5 0x0 - -#endif /* __DTS_IMX8MP_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi deleted file mode 100644 index acee71ca3..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ /dev/null @@ -1,756 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - */ - -#include -#include -#include -#include -#include - -#include "imx8mp-pinfunc.h" - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet0 = &fec; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - i2c4 = &i2c5; - i2c5 = &i2c6; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - A53_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - clock-latency = <61036>; - clocks = <&clk IMX8MP_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - #cooling-cells = <2>; - }; - - A53_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - clock-latency = <61036>; - clocks = <&clk IMX8MP_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - #cooling-cells = <2>; - }; - - A53_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x2>; - clock-latency = <61036>; - clocks = <&clk IMX8MP_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - #cooling-cells = <2>; - }; - - A53_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x3>; - clock-latency = <61036>; - clocks = <&clk IMX8MP_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - #cooling-cells = <2>; - }; - - A53_L2: l2-cache0 { - compatible = "cache"; - }; - }; - - osc_32k: clock-osc-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "osc_32k"; - }; - - osc_24m: clock-osc-24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc_24m"; - }; - - clk_ext1: clock-ext1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext1"; - }; - - clk_ext2: clock-ext2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext2"; - }; - - clk_ext3: clock-ext3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext3"; - }; - - clk_ext4: clock-ext4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency= <133000000>; - clock-output-names = "clk_ext4"; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu 0>; - trips { - cpu_alert0: trip0 { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit0: trip1 { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - soc-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu 1>; - trips { - soc_alert0: trip0 { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - soc_crit0: trip1 { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&soc_alert0>; - cooling-device = - <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - clock-frequency = <8000000>; - arm,no-tick-in-suspend; - }; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x3e000000>; - - aips1: bus@30000000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x30000000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio1: gpio@30200000 { - compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; - reg = <0x30200000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 5 30>; - }; - - gpio2: gpio@30210000 { - compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; - reg = <0x30210000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 35 21>; - }; - - gpio3: gpio@30220000 { - compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; - reg = <0x30220000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>; - }; - - gpio4: gpio@30230000 { - compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; - reg = <0x30230000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 82 32>; - }; - - gpio5: gpio@30240000 { - compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; - reg = <0x30240000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 114 30>; - }; - - tmu: tmu@30260000 { - compatible = "fsl,imx8mp-tmu"; - reg = <0x30260000 0x10000>; - clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; - #thermal-sensor-cells = <1>; - }; - - wdog1: watchdog@30280000 { - compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; - reg = <0x30280000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; - status = "disabled"; - }; - - iomuxc: pinctrl@30330000 { - compatible = "fsl,imx8mp-iomuxc"; - reg = <0x30330000 0x10000>; - }; - - gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; - reg = <0x30340000 0x10000>; - }; - - ocotp: efuse@30350000 { - compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; - reg = <0x30350000 0x10000>; - clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; - /* For nvmem subnodes */ - #address-cells = <1>; - #size-cells = <1>; - - cpu_speed_grade: speed-grade@10 { - reg = <0x10 4>; - }; - }; - - anatop: anatop@30360000 { - compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop", - "syscon"; - reg = <0x30360000 0x10000>; - }; - - snvs: snvs@30370000 { - compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; - reg = <0x30370000 0x10000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap =<&snvs>; - offset = <0x34>; - interrupts = , - ; - clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; - clock-names = "snvs-rtc"; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; - clock-names = "snvs-pwrkey"; - linux,keycode = ; - wakeup-source; - status = "disabled"; - }; - }; - - clk: clock-controller@30380000 { - compatible = "fsl,imx8mp-ccm"; - reg = <0x30380000 0x10000>; - #clock-cells = <1>; - clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; - clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; - assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, - <&clk IMX8MP_CLK_A53_CORE>, - <&clk IMX8MP_CLK_NOC>, - <&clk IMX8MP_CLK_NOC_IO>, - <&clk IMX8MP_CLK_GIC>, - <&clk IMX8MP_CLK_AUDIO_AHB>, - <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, - <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>, - <&clk IMX8MP_AUDIO_PLL1>, - <&clk IMX8MP_AUDIO_PLL2>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_ARM_PLL_OUT>, - <&clk IMX8MP_SYS_PLL2_1000M>, - <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_SYS_PLL2_500M>, - <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <0>, <0>, - <1000000000>, - <800000000>, - <500000000>, - <400000000>, - <800000000>, - <400000000>, - <393216000>, - <361267200>; - }; - - src: reset-controller@30390000 { - compatible = "fsl,imx8mp-src", "syscon"; - reg = <0x30390000 0x10000>; - interrupts = ; - #reset-cells = <1>; - }; - }; - - aips2: bus@30400000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x30400000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pwm1: pwm@30660000 { - compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; - reg = <0x30660000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, - <&clk IMX8MP_CLK_PWM1_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@30670000 { - compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; - reg = <0x30670000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, - <&clk IMX8MP_CLK_PWM2_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@30680000 { - compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; - reg = <0x30680000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, - <&clk IMX8MP_CLK_PWM3_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@30690000 { - compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; - reg = <0x30690000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, - <&clk IMX8MP_CLK_PWM4_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - system_counter: timer@306a0000 { - compatible = "nxp,sysctr-timer"; - reg = <0x306a0000 0x20000>; - interrupts = ; - clocks = <&osc_24m>; - clock-names = "per"; - }; - }; - - aips3: bus@30800000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x30800000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - ecspi1: spi@30820000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; - reg = <0x30820000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, - <&clk IMX8MP_CLK_ECSPI1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi2: spi@30830000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; - reg = <0x30830000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, - <&clk IMX8MP_CLK_ECSPI2_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi3: spi@30840000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; - reg = <0x30840000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, - <&clk IMX8MP_CLK_ECSPI3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@30860000 { - compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_UART1_ROOT>, - <&clk IMX8MP_CLK_UART1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart3: serial@30880000 { - compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_UART3_ROOT>, - <&clk IMX8MP_CLK_UART3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: serial@30890000 { - compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_UART2_ROOT>, - <&clk IMX8MP_CLK_UART2_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - crypto: crypto@30900000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30900000 0x40000>; - ranges = <0 0x30900000 0x40000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_AHB>, - <&clk IMX8MP_CLK_IPG_ROOT>; - clock-names = "aclk", "ipg"; - - sec_jr0: jr@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - sec_jr1: jr@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = ; - }; - - sec_jr2: jr@3000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x3000 0x1000>; - interrupts = ; - }; - }; - - i2c1: i2c@30a20000 { - compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30a20000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; - status = "disabled"; - }; - - i2c2: i2c@30a30000 { - compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30a30000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; - status = "disabled"; - }; - - i2c3: i2c@30a40000 { - compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30a40000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; - status = "disabled"; - }; - - i2c4: i2c@30a50000 { - compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30a50000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; - status = "disabled"; - }; - - uart4: serial@30a60000 { - compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; - reg = <0x30a60000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_UART4_ROOT>, - <&clk IMX8MP_CLK_UART4_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - mu: mailbox@30aa0000 { - compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; - reg = <0x30aa0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_MU_ROOT>; - #mbox-cells = <2>; - }; - - i2c5: i2c@30ad0000 { - compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30ad0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; - status = "disabled"; - }; - - i2c6: i2c@30ae0000 { - compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30ae0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; - status = "disabled"; - }; - - usdhc1: mmc@30b40000 { - compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; - reg = <0x30b40000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_DUMMY>, - <&clk IMX8MP_CLK_NAND_USDHC_BUS>, - <&clk IMX8MP_CLK_USDHC1_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: mmc@30b50000 { - compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; - reg = <0x30b50000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_DUMMY>, - <&clk IMX8MP_CLK_NAND_USDHC_BUS>, - <&clk IMX8MP_CLK_USDHC2_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - bus-width = <4>; - status = "disabled"; - }; - - usdhc3: mmc@30b60000 { - compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; - reg = <0x30b60000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_DUMMY>, - <&clk IMX8MP_CLK_NAND_USDHC_BUS>, - <&clk IMX8MP_CLK_USDHC3_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - bus-width = <4>; - status = "disabled"; - }; - - sdma1: dma-controller@30bd0000 { - compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; - reg = <0x30bd0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, - <&clk IMX8MP_CLK_AHB>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - fec: ethernet@30be0000 { - compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; - reg = <0x30be0000 0x10000>; - interrupts = , - , - , - ; - clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, - <&clk IMX8MP_CLK_SIM_ENET_ROOT>, - <&clk IMX8MP_CLK_ENET_TIMER>, - <&clk IMX8MP_CLK_ENET_REF>, - <&clk IMX8MP_CLK_ENET_PHY_REF>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, - <&clk IMX8MP_CLK_ENET_TIMER>, - <&clk IMX8MP_CLK_ENET_REF>, - <&clk IMX8MP_CLK_ENET_PHY_REF>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, - <&clk IMX8MP_SYS_PLL2_100M>, - <&clk IMX8MP_SYS_PLL2_125M>, - <&clk IMX8MP_SYS_PLL2_50M>; - assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; - status = "disabled"; - }; - }; - - gic: interrupt-controller@38800000 { - compatible = "arm,gic-v3"; - reg = <0x38800000 0x10000>, - <0x38880000 0xc0000>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - interrupt-parent = <&gic>; - }; - - ddr-pmu@3d800000 { - compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; - reg = <0x3d800000 0x400000>; - interrupts = ; - }; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts deleted file mode 100644 index 2418cca00..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ /dev/null @@ -1,575 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2017 NXP - * Copyright (C) 2017-2018 Pengutronix, Lucas Stach - */ - -/dts-v1/; - -#include "imx8mq.dtsi" - -/ { - model = "NXP i.MX8MQ EVK"; - compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; - - chosen { - stdout-path = &uart1; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x00000000 0x40000000 0 0xc0000000>; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - reg_usdhc2_vmmc: regulator-vsd-3v3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2>; - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - buck2_reg: regulator-buck2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_buck2>; - compatible = "regulator-gpio"; - regulator-name = "vdd_arm"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1000000>; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - states = <1000000 0x0 - 900000 0x1>; - regulator-boot-on; - regulator-always-on; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir>; - }; - - wm8524: audio-codec { - #sound-dai-cells = <0>; - compatible = "wlf,wm8524"; - wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - }; - - sound-wm8524 { - compatible = "simple-audio-card"; - simple-audio-card,name = "wm8524-audio"; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&cpudai>; - simple-audio-card,bitclock-master = <&cpudai>; - simple-audio-card,widgets = - "Line", "Left Line Out Jack", - "Line", "Right Line Out Jack"; - simple-audio-card,routing = - "Left Line Out Jack", "LINEVOUTL", - "Right Line Out Jack", "LINEVOUTR"; - - cpudai: simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - link_codec: simple-audio-card,codec { - sound-dai = <&wm8524>; - clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; - }; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - /* - * On imx8mq B0 PLL can't be bypassed so low bus is 166M - */ - opp-166M { - opp-hz = /bits/ 64 <166935483>; - }; - - opp-800M { - opp-hz = /bits/ 64 <800000000>; - }; - }; -}; - -&dphy { - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - }; - }; -}; - -&gpio5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_reset>; - - wl-reg-on-hog { - gpio-hog; - gpios = <29 GPIO_ACTIVE_HIGH>; - output-high; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x8>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - sw3a_reg: sw3ab { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <975000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1675000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1625000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3625000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; -}; - -&lcdif { - status = "okay"; -}; - -&mipi_dsi { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - panel@0 { - pinctrl-0 = <&pinctrl_mipi_dsi>; - pinctrl-names = "default"; - compatible = "raydium,rm67191"; - reg = <0>; - reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; - dsi-lanes = <4>; - - port { - panel_in: endpoint { - remote-endpoint = <&mipi_dsi_out>; - }; - }; - }; - - ports { - port@1 { - reg = <1>; - mipi_dsi_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, - <&clk IMX8MQ_CLK_PCIE1_AUX>, - <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; - status = "okay"; -}; - -&pgc_gpu { - power-supply = <&sw1a_reg>; -}; - -&qspi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - - n25q256a: flash@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; - }; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <0>, <24576000>; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - vqmmc-supply = <&sw4_reg>; - bus-width = <8>; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_buck2: vddarmgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 - >; - - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f - >; - }; - - pinctrl_ir: irgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f - >; - }; - - pinctrl_mipi_dsi: mipidsigrp { - fsl,pins = < - MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 - MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 - >; - }; - - pinctrl_qspi: qspigrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 - MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - - >; - }; - - pinctrl_reg_usdhc2: regusdhc2gpiogrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 - MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 - MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 - MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 - MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_wdog: wdog1grp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; - - pinctrl_wifi_reset: wifiresetgrp { - fsl,pins = < - MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts b/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts deleted file mode 100644 index 366693f31..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts +++ /dev/null @@ -1,264 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2018 Jon Nettleton - */ - -/dts-v1/; - -#include "dt-bindings/usb/pd.h" -#include "imx8mq-sr-som.dtsi" - -/ { - model = "SolidRun i.MX8MQ HummingBoard Pulse"; - compatible = "solidrun,hummingboard-pulse", "fsl,imx8mq"; - - chosen { - stdout-path = &uart1; - }; - - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; - - reg_v_5v0: regulator-v-5v0 { - compatible = "regulator-fixed"; - regulator-name = "v_5v0"; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "okay"; - - typec_ptn5100: usb-typec@50 { - compatible = "nxp,ptn5110"; - reg = <0x50>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_typec>; - interrupt-parent = <&gpio1>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <9000000>; - - port { - typec1_dr_sw: endpoint { - remote-endpoint = <&usb1_drd_sw>; - }; - }; - }; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <100000>; - status = "okay"; - - eeprom@57 { - compatible = "atmel,24c02"; - reg = <0x57>; - status = "okay"; - }; - - rtc@69 { - compatible = "abracon,ab1805"; - reg = <0x69>; - abracon,tc-diode = "schottky"; - abracon,tc-resistor = <3>; - }; -}; - -&uart2 { /* J35 header */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - assigned-clocks = <&clk IMX8MQ_CLK_UART2>; - assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; - status = "okay"; -}; - -&uart3 { /* Mikrobus */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clk IMX8MQ_CLK_UART3>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; - uart-has-rtscts; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&usb_dwc3_0 { - dr_mode = "otg"; - status = "okay"; - - port { - usb1_drd_sw: endpoint { - remote-endpoint = <&typec1_dr_sw>; - }; - }; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - /* MikroBus Analog */ - MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x41 - /* MikroBus Reset */ - MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x41 - /* - * The following 2 pins need to be commented out and - * reconfigured to enable RTS/CTS on UART3 - */ - /* MikroBus PWM */ - MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x41 - /* MikroBus INT */ - MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f - MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f - MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f - >; - }; - - pinctrl_typec: typecgrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16 - MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x17059 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 - MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 - MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 - /* - * These pins are by default GPIO on the Mikro Bus - * Header. To use RTS/CTS on UART3 comment them out - * of the hoggrp and enable them here - */ - /* MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 */ - /* MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 */ - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 - >; - }; - - pinctrl_usdhc2_vmmc: usdhc2vmmcgpiogrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts deleted file mode 100644 index af139b283..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ /dev/null @@ -1,1000 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018-2019 Purism SPC - */ - -/dts-v1/; - -#include "dt-bindings/input/input.h" -#include -#include "dt-bindings/pwm/pwm.h" -#include "dt-bindings/usb/pd.h" -#include "imx8mq.dtsi" - -/ { - model = "Purism Librem 5 devkit"; - compatible = "purism,librem5-devkit", "fsl,imx8mq"; - - backlight_dsi: backlight-dsi { - compatible = "pwm-backlight"; - /* 200 Hz for the PAM2841 */ - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 100>; - num-interpolated-steps = <100>; - /* Default brightness level (index into the array defined by */ - /* the "brightness-levels" property) */ - default-brightness-level = <0>; - power-supply = <®_22v4_p>; - }; - - chosen { - stdout-path = &uart1; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - btn1 { - label = "VOL_UP"; - gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; - wakeup-source; - linux,code = ; - }; - - btn2 { - label = "VOL_DOWN"; - gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - wakeup-source; - linux,code = ; - }; - - hp-det { - label = "HP_DET"; - gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; - wakeup-source; - linux,code = ; - }; - - wwan-wake { - label = "WWAN_WAKE"; - gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio3>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - wakeup-source; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led1 { - label = "LED 1"; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pmic_osc: clock-pmic { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "pmic_osc"; - }; - - reg_1v8_p: regulator-1v8-p { - compatible = "regulator-fixed"; - regulator-name = "1v8_p"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <®_pwr_en>; - }; - - reg_2v8_p: regulator-2v8-p { - compatible = "regulator-fixed"; - regulator-name = "2v8_p"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - vin-supply = <®_pwr_en>; - }; - - reg_3v3_p: regulator-3v3-p { - compatible = "regulator-fixed"; - regulator-name = "3v3_p"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_pwr_en>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - reg_5v_p: regulator-5v-p { - compatible = "regulator-fixed"; - regulator-name = "5v_p"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_pwr_en>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - reg_22v4_p: regulator-22v4-p { - compatible = "regulator-fixed"; - regulator-name = "22v4_P"; - regulator-min-microvolt = <22400000>; - regulator-max-microvolt = <22400000>; - vin-supply = <®_pwr_en>; - }; - - reg_pwr_en: regulator-pwr-en { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwr_en>; - regulator-name = "PWR_EN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_pwr>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - wwan_codec: sound-wwan-codec { - compatible = "option,gtm601"; - #sound-dai-cells = <0>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "Speaker Ext", - "Line", "Line In Jack"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Microphone Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "Speaker Ext", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - simple-audio-card,codec { - sound-dai = <&sgtl5000>; - clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; - frame-master; - bitclock-master; - }; - }; - - sound-wwan { - compatible = "simple-audio-card"; - simple-audio-card,name = "SIMCom SIM7100"; - simple-audio-card,format = "dsp_a"; - - simple-audio-card,cpu { - sound-dai = <&sai6>; - }; - - telephony_link_master: simple-audio-card,codec { - sound-dai = <&wwan_codec>; - frame-master; - bitclock-master; - }; - }; - - vibrator { - compatible = "gpio-vibrator"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_haptic>; - enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; - vcc-supply = <®_3v3_p>; - }; - - wifi_pwr_en: regulator-wifi-en { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_pwr_en>; - regulator-name = "WIFI_EN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -&clk { - assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>; - assigned-clock-rates = <786432000>, <722534400>; -}; - -&dphy { - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - phy-supply = <®_3v3_p>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pmic@4b { - compatible = "rohm,bd71837"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - clocks = <&pmic_osc>; - clock-names = "osc"; - #clock-cells = <0>; - clock-output-names = "pmic_clk"; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <900000>; - rohm,dvs-idle-voltage = <850000>; - rohm,dvs-suspend-voltage = <800000>; - }; - - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - buck3_reg: BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - rohm,dvs-run-voltage = <900000>; - }; - - buck4_reg: BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - rohm,dvs-run-voltage = <1000000>; - }; - - buck5_reg: BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "buck7"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "buck8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - /* leave on for snvs power button */ - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - /* leave on for snvs power button */ - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - ldo5_reg: LDO5 { - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - }; - }; - - typec_ptn5100: usb-typec@52 { - compatible = "nxp,ptn5110"; - reg = <0x52>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_typec>; - interrupt-parent = <&gpio3>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <10000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb_con_hs: endpoint { - remote-endpoint = <&typec_hs>; - }; - }; - - port@1 { - reg = <1>; - - usb_con_ss: endpoint { - remote-endpoint = <&typec_ss>; - }; - }; - }; - }; - }; - - rtc@68 { - compatible = "microcrystal,rv4162"; - reg = <0x68>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; - interrupt-parent = <&gpio4>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; - }; - - charger@6b { /* bq25896 */ - compatible = "ti,bq25890"; - reg = <0x6b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_charger>; - interrupt-parent = <&gpio3>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - ti,battery-regulation-voltage = <4192000>; /* 4.192V */ - ti,charge-current = <1600000>; /* 1.6A */ - ti,termination-current = <66000>; /* 66mA */ - ti,precharge-current = <130000>; /* 130mA */ - ti,minimum-sys-voltage = <3000000>; /* 3V */ - ti,boost-voltage = <5000000>; /* 5V */ - ti,boost-max-current = <50000>; /* 50mA */ - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - magnetometer@1e { - compatible = "st,lsm9ds1-magn"; - reg = <0x1e>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_imu>; - interrupt-parent = <&gpio3>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; - vdd-supply = <®_3v3_p>; - vddio-supply = <®_3v3_p>; - }; - - sgtl5000: audio-codec@a { - compatible = "fsl,sgtl5000"; - clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; - assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - #sound-dai-cells = <0>; - reg = <0x0a>; - VDDD-supply = <®_1v8_p>; - VDDIO-supply = <®_3v3_p>; - VDDA-supply = <®_3v3_p>; - }; - - touchscreen@5d { - compatible = "goodix,gt5688"; - reg = <0x5d>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts>; - interrupt-parent = <&gpio3>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; - touchscreen-size-x = <720>; - touchscreen-size-y = <1440>; - AVDD28-supply = <®_2v8_p>; - VDDIO-supply = <®_1v8_p>; - }; - - proximity-sensor@60 { - compatible = "vishay,vcnl4040"; - reg = <0x60>; - pinctrl-0 = <&pinctrl_prox>; - }; - - accel-gyro@6a { - compatible = "st,lsm9ds1-imu"; - reg = <0x6a>; - vdd-supply = <®_3v3_p>; - vddio-supply = <®_3v3_p>; - mount-matrix = "1", "0", "0", - "0", "1", "0", - "0", "0", "-1"; - }; -}; - -&iomuxc { - pinctrl_bl: blgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* DSI_BL_PWM */ - >; - }; - - pinctrl_bt: btgrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 /* nBT_DISABLE */ - MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x10 /* BT_HOST_WAKE */ - >; - }; - - pinctrl_charger: chargergrp { - fsl,pins = < - MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x80 /* CHRG_nINT */ - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f - >; - }; - - pinctrl_ts: tsgrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x16 /* TOUCH INT */ - MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* TOUCH RST */ - >; - }; - - pinctrl_gpio_leds: gpioledgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16 - >; - }; - - pinctrl_gpio_keys: gpiokeygrp { - fsl,pins = < - MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16 - MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16 - MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x180 /* HP_DET */ - MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */ - >; - }; - - pinctrl_haptic: hapticgrp { - fsl,pins = < - MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0xc6 /* nHAPTIC */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000001f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000001f - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f - MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f - >; - }; - - pinctrl_imu: imugrp { - fsl,pins = < - MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x8 /* IMU_INT */ - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80 /* PMIC intr */ - >; - }; - - pinctrl_prox: proxgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x80 /* prox intr */ - >; - }; - - pinctrl_pwr_en: pwrengrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06 - >; - }; - - pinctrl_rtc: rtcgrp { - fsl,pins = < - MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x80 /* RTC intr */ - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 - MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 - MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 - MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 - MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 - >; - }; - - pinctrl_sai6: sai6grp { - fsl,pins = < - MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6 - MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6 - MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6 - MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6 - >; - }; - - pinctrl_typec: typecgrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16 - MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x80 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 - MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 - MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 - MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 - MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49 - MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49 - MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49 - MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49 - MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x49 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2_pwr: usdhc2pwrgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80 /* WIFI_WAKE */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; - - pinctrl_wifi_pwr_en: wifipwrengrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x06 - >; - }; - - pinctrl_wwan: wwangrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x09 /* nWWAN_DISABLE */ - MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */ - MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */ - >; - }; -}; - -&lcdif { - status = "okay"; -}; - -&mipi_dsi { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - panel@0 { - compatible = "rocktech,jh057n00900"; - reg = <0>; - backlight = <&backlight_dsi>; - reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; - iovcc-supply = <®_1v8_p>; - vcc-supply = <®_2v8_p>; - port { - panel_in: endpoint { - remote-endpoint = <&mipi_dsi_out>; - }; - }; - }; - - ports { - port@1 { - reg = <1>; - mipi_dsi_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pgc_gpu { - power-supply = <&buck3_reg>; -}; - -&pgc_vpu { - power-supply = <&buck4_reg>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bl>; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -&sai6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai6>; - assigned-clocks = <&clk IMX8MQ_CLK_SAI6>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - fsl,sai-synchronous-rx; - status = "okay"; -}; - -&uart1 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart3 { /* GNSS */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { /* BT */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>; - uart-has-rtscts; - status = "okay"; -}; - -&usb3_phy0 { - vbus-supply = <®_5v_p>; - status = "okay"; -}; - -&usb3_phy1 { - vbus-supply = <®_5v_p>; - status = "okay"; -}; - -&usb_dwc3_0 { - #address-cells = <1>; - #size-cells = <0>; - dr_mode = "otg"; - status = "okay"; - - port@0 { - reg = <0>; - - typec_hs: endpoint { - remote-endpoint = <&usb_con_hs>; - }; - }; - - port@1 { - reg = <1>; - - typec_ss: endpoint { - remote-endpoint = <&usb_con_ss>; - }; - }; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - power-supply = <&wifi_pwr_en>; - broken-cd; - disable-wp; - cap-sdio-irq; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts deleted file mode 100644 index d77fc5df3..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2020 Purism SPC -// -// Librem 5 Chestnut - -/dts-v1/; - -#include "imx8mq-librem5.dtsi" - -/ { - model = "Purism Librem 5r2"; - compatible = "purism,librem5r2", "purism,librem5", "fsl,imx8mq"; -}; - -&bq25895 { - ti,battery-regulation-voltage = <4192000>; /* uV */ - ti,charge-current = <1600000>; /* uA */ - ti,termination-current = <66000>; /* uA */ -}; - -&accel_gyro { - mount-matrix = "1", "0", "0", - "0", "-1", "0", - "0", "0", "1"; -}; - -&proximity { - proximity-near-level = <220>; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts deleted file mode 100644 index cc29223ca..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2020 Purism SPC - -/dts-v1/; - -#include "imx8mq-librem5.dtsi" - -/ { - model = "Purism Librem 5r3"; - compatible = "purism,librem5r3", "purism,librem5", "fsl,imx8mq"; -}; - -&accel_gyro { - mount-matrix = "1", "0", "0", - "0", "1", "0", - "0", "0", "-1"; -}; - -&bq25895 { - ti,battery-regulation-voltage = <4200000>; /* uV */ - ti,charge-current = <1500000>; /* uA */ - ti,termination-current = <144000>; /* uA */ -}; - -&buck3_reg { - regulator-always-on; -}; - -&proximity { - proximity-near-level = <25>; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi deleted file mode 100644 index e3c6d1272..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ /dev/null @@ -1,1106 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018-2020 Purism SPC - */ - -/dts-v1/; - -#include "dt-bindings/input/input.h" -#include -#include "dt-bindings/pwm/pwm.h" -#include "dt-bindings/usb/pd.h" -#include "imx8mq.dtsi" - -/ { - model = "Purism Librem 5"; - compatible = "purism,librem5", "fsl,imx8mq"; - - backlight_dsi: backlight-dsi { - compatible = "led-backlight"; - leds = <&led_backlight>; - }; - - pmic_osc: clock-pmic { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "pmic_osc"; - }; - - chosen { - stdout-path = &uart1; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_keys>; - - vol-down { - label = "VOL_DOWN"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - vol-up { - label = "VOL_UP"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - reg_aud_1v8: regulator-audio-1v8 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopwr>; - regulator-name = "AUDIO_PWR_EN"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_gnss: regulator-gnss { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gnsspwr>; - regulator-name = "GNSS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_hub: regulator-hub { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hub_pwr>; - regulator-name = "HUB"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lcd_3v4: regulator-lcd-3v4 { - compatible = "regulator-fixed"; - regulator-name = "LCD_3V4"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dsibiasen>; - vin-supply = <®_vsys_3v4>; - gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vdd_sen: regulator-vdd-sen { - compatible = "regulator-fixed"; - regulator-name = "VDD_SEN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_vdd_3v3: regulator-vdd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_vdd_1v8: regulator-vdd-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_vsys_3v4: regulator-vsys-3v4 { - compatible = "regulator-fixed"; - regulator-name = "VSYS_3V4"; - regulator-min-microvolt = <3400000>; - regulator-max-microvolt = <3400000>; - regulator-always-on; - }; - - reg_wifi_3v3: regulator-wifi-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3_WIFI"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - sound { - compatible = "simple-audio-card"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hp>; - simple-audio-card,name = "Librem 5"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Headphone", "Headphones", - "Microphone", "Headset Mic", - "Microphone", "Digital Mic", - "Speaker", "Speaker"; - simple-audio-card,routing = - "Headphones", "HPOUTL", - "Headphones", "HPOUTR", - "Speaker", "SPKOUTL", - "Speaker", "SPKOUTR", - "Headset Mic", "MICBIAS", - "IN3R", "Headset Mic", - "DMICDAT", "Digital Mic"; - simple-audio-card,hp-det-gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; - frame-master; - bitclock-master; - }; - }; - - sound-wwan { - compatible = "simple-audio-card"; - simple-audio-card,name = "Modem"; - simple-audio-card,format = "i2s"; - - simple-audio-card,cpu { - sound-dai = <&sai6>; - frame-inversion; - }; - - simple-audio-card,codec { - sound-dai = <&bm818_codec>; - frame-master; - bitclock-master; - }; - }; - - bm818_codec: sound-wwan-codec { - compatible = "broadmobi,bm818", "option,gtm601"; - #sound-dai-cells = <0>; - }; - - vibrator { - compatible = "pwm-vibrator"; - pwms = <&pwm1 0 1000000000 0>; - pwm-names = "enable"; - vcc-supply = <®_vdd_3v3>; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: ddrc-opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-800M { - opp-hz = /bits/ 64 <800000000>; - }; - }; -}; - -&dphy { - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - nor_flash: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <1000000>; - }; -}; - -&gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic_5v>; - - pmic-5v { - gpio-hog; - gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - input; - }; -}; - -&iomuxc { - pinctrl_audiopwr: audiopwrgrp { - fsl,pins = < - /* AUDIO_POWER_EN_3V3 */ - MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x83 - >; - }; - - pinctrl_bl: blgrp { - fsl,pins = < - /* BACKLINGE_EN */ - MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x83 - >; - }; - - pinctrl_charger_in: chargeringrp { - fsl,pins = < - /* CHRG_INT */ - MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x00 - /* CHG_STATUS_B */ - MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x80 - >; - }; - - pinctrl_dsibiasen: dsibiasengrp { - fsl,pins = < - /* DSI_BIAS_EN */ - MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x83 - >; - }; - - pinctrl_dsien: dsiengrp { - fsl,pins = < - /* DSI_EN_3V3 */ - MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x83 - >; - }; - - pinctrl_ecspi1: ecspigrp { - fsl,pins = < - MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x83 - MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x83 - MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 - MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x83 - >; - }; - - pinctrl_gauge: gaugegrp { - fsl,pins = < - /* BAT_LOW */ - MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x80 - >; - }; - - pinctrl_gnsspwr: gnsspwrgrp { - fsl,pins = < - /* GPS3V3_EN */ - MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x83 - >; - }; - - pinctrl_haptic: hapticgrp { - fsl,pins = < - /* MOTO */ - MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x83 - >; - }; - - pinctrl_hp: hpgrp { - fsl,pins = < - /* HEADPHONE_DET_1V8 */ - MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x180 - >; - }; - - pinctrl_hub_pwr: hubpwrgrp { - fsl,pins = < - /* HUB_PWR_3V3_EN */ - MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x83 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000026 - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000026 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000026 - MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000026 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000026 - MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000026 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000026 - MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000026 - >; - }; - - pinctrl_keys: keysgrp { - fsl,pins = < - /* VOL- */ - MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x01C0 - /* VOL+ */ - MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x01C0 - >; - }; - - pinctrl_led_b: ledbgrp { - fsl,pins = < - /* LED_B */ - MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x06 - >; - }; - - pinctrl_led_g: ledggrp { - fsl,pins = < - /* LED_G */ - MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x06 - >; - }; - - pinctrl_led_r: ledrgrp { - fsl,pins = < - /* LED_R */ - MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x06 - >; - }; - - pinctrl_mag: maggrp { - fsl,pins = < - /* INT_MAG */ - MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x80 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - /* PMIC_NINT */ - MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x80 - >; - }; - - pinctrl_pmic_5v: pmic5vgrp { - fsl,pins = < - /* PMIC_5V */ - MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x80 - >; - }; - - pinctrl_prox: proxgrp { - fsl,pins = < - /* INT_LIGHT */ - MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x80 - >; - }; - - pinctrl_rtc: rtcgrp { - fsl,pins = < - /* RTC_INT */ - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x80 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 - MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 - MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 - MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 - MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 - >; - }; - - pinctrl_sai6: sai6grp { - fsl,pins = < - MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6 - MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6 - MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6 - MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6 - >; - }; - - pinctrl_tcpc: tcpcgrp { - fsl,pins = < - /* TCPC_INT */ - MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x01C0 - >; - }; - - pinctrl_typec: typecgrp { - fsl,pins = < - /* TYPEC_MUX_EN */ - MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x83 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 - MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 - MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49 - MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49 - MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49 - MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd - MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf - MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - /* nWDOG */ - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x1f - >; - }; -}; - -&i2c1 { - clock-frequency = <387000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - typec_pd: usb-pd@3f { - compatible = "ti,tps6598x"; - reg = <0x3f>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_typec>, <&pinctrl_tcpc>; - interrupt-parent = <&gpio1>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "irq"; - - connector { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb_con_hs: endpoint { - remote-endpoint = <&typec_hs>; - }; - }; - - port@1 { - reg = <1>; - - usb_con_ss: endpoint { - remote-endpoint = <&typec_ss>; - }; - }; - }; - }; - }; - - pmic: pmic@4b { - compatible = "rohm,bd71837"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - clocks = <&pmic_osc>; - clock-names = "osc"; - clock-output-names = "pmic_clk"; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <900000>; - rohm,dvs-idle-voltage = <850000>; - rohm,dvs-suspend-voltage = <800000>; - regulator-always-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - regulator-always-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - rohm,dvs-run-voltage = <900000>; - regulator-always-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - rohm,dvs-run-voltage = <1000000>; - }; - - buck5_reg: BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "buck7"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "buck8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - /* leave on for snvs power button */ - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - /* leave on for snvs power button */ - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo5_reg: LDO5 { - /* VDD_PHY_0V9 - MIPI and HDMI domains */ - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - /* VDD_PHY_0V9 - MIPI, HDMI and USB domains */ - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - /* VDD_PHY_3V3 - USB domain */ - regulator-name = "ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - rtc@68 { - compatible = "microcrystal,rv4162"; - reg = <0x68>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c2 { - clock-frequency = <387000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - magnetometer@1e { - compatible = "st,lsm9ds1-magn"; - reg = <0x1e>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mag>; - interrupt-parent = <&gpio3>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; - vdd-supply = <®_vdd_sen>; - vddio-supply = <®_vdd_1v8>; - }; - - regulator@3e { - compatible = "tps65132"; - reg = <0x3e>; - - outp { - regulator-name = "LCD_AVDD"; - vin-supply = <®_lcd_3v4>; - }; - - outn { - regulator-name = "LCD_AVEE"; - vin-supply = <®_lcd_3v4>; - }; - }; - - proximity: prox@60 { - compatible = "vishay,vcnl4040"; - reg = <0x60>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_prox>; - interrupt-parent = <&gpio3>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - }; - - accel_gyro: accel-gyro@6a { - compatible = "st,lsm9ds1-imu"; - reg = <0x6a>; - vdd-supply = <®_vdd_sen>; - vddio-supply = <®_vdd_1v8>; - }; -}; - -&i2c3 { - clock-frequency = <387000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - codec: audio-codec@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; - assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - #sound-dai-cells = <0>; - mic-cfg = <0x200>; - DCVDD-supply = <®_aud_1v8>; - DBVDD-supply = <®_aud_1v8>; - AVDD-supply = <®_aud_1v8>; - CPVDD-supply = <®_aud_1v8>; - MICVDD-supply = <®_aud_1v8>; - PLLVDD-supply = <®_aud_1v8>; - SPKVDD1-supply = <®_vsys_3v4>; - SPKVDD2-supply = <®_vsys_3v4>; - gpio-cfg = < - 0x0000 /* n/c */ - 0x0001 /* gpio2, 1: default */ - 0x0013 /* gpio3, 2: dmicclk */ - 0x0000 /* n/c, 3: default */ - 0x8014 /* gpio5, 4: dmic_dat */ - 0x0000 /* gpio6, 5: default */ - >; - }; - - backlight@36 { - compatible = "ti,lm36922"; - reg = <0x36>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bl>; - #address-cells = <1>; - #size-cells = <0>; - enable-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - vled-supply = <®_vsys_3v4>; - ti,ovp-microvolt = <25000000>; - - led_backlight: led@0 { - reg = <0>; - label = ":backlight"; - linux,default-trigger = "backlight"; - led-max-microamp = <20000>; - }; - }; - - touchscreen@38 { - compatible = "edt,edt-ft5506"; - reg = <0x38>; - interrupt-parent = <&gpio1>; - interrupts = <27 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <720>; - touchscreen-size-y = <1440>; - }; -}; - -&i2c4 { - clock-frequency = <387000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - bat: fuel-gauge@36 { - compatible = "maxim,max17055"; - reg = <0x36>; - interrupt-parent = <&gpio3>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gauge>; - maxim,over-heat-temp = <700>; - maxim,over-volt = <4500>; - maxim,rsns-microohm = <5000>; - }; - - bq25895: charger@6a { - compatible = "ti,bq25895", "ti,bq25890"; - reg = <0x6a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_charger_in>; - interrupt-parent = <&gpio3>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - phys = <&usb3_phy0>; - ti,precharge-current = <130000>; /* uA */ - ti,minimum-sys-voltage = <3700000>; /* uV */ - ti,boost-voltage = <5000000>; /* uV */ - ti,boost-max-current = <500000>; /* uA */ - ti,use-vinmin-threshold = <1>; /* enable VINDPM */ - ti,vinmin-threshold = <3900000>; /* uV */ - monitored-battery = <&bat>; - }; -}; - -&pgc_gpu { - power-supply = <&buck3_reg>; -}; - -&pgc_mipi { - power-supply = <&ldo5_reg>; -}; - -&pgc_vpu { - power-supply = <&buck4_reg>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_haptic>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_b>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_g>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_r>; - status = "okay"; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>; - assigned-clock-rates = <786432000>, <722534400>; - status = "okay"; -}; - -&sai6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai6>; - assigned-clocks = <&clk IMX8MQ_CLK_SAI6>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - fsl,sai-synchronous-rx; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&snvs_rtc { - status = "disabled"; -}; - -&uart1 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { /* TPS - GPS - DEBUG */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; - - gnss { - compatible = "globaltop,pa6h"; - vcc-supply = <®_gnss>; - current-speed = <9600>; - }; -}; - -&uart3 { /* SMC */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { /* BT */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - uart-has-rtscts; - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb3_phy1 { - vbus-supply = <®_hub>; - status = "okay"; -}; - -&usb_dwc3_0 { - #address-cells = <1>; - #size-cells = <0>; - dr_mode = "otg"; - snps,dis_u3_susphy_quirk; - status = "okay"; - - port@0 { - reg = <0>; - - typec_hs: endpoint { - remote-endpoint = <&usb_con_hs>; - }; - }; - - port@1 { - reg = <1>; - - typec_ss: endpoint { - remote-endpoint = <&usb_con_ss>; - }; - }; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - /* Microchip USB2642 */ - hub@1 { - compatible = "usb424,2640"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mass-storage@1 { - compatible = "usb424,4041"; - reg = <1>; - }; - }; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - vmmc-supply = <®_vdd_3v3>; - power-supply = <®_vdd_1v8>; - non-removable; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - bus-width = <4>; - vmmc-supply = <®_wifi_3v3>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - disable-wp; - cap-sdio-irq; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts deleted file mode 100644 index 81d269296..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts +++ /dev/null @@ -1,407 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2018 Boundary Devices - */ - -/dts-v1/; - -#include -#include "imx8mq.dtsi" - -/ { - model = "Boundary Devices i.MX8MQ Nitrogen8M"; - compatible = "boundary,imx8mq-nitrogen8m", "fsl,imx8mq"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x00000000 0x40000000 0 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - power { - label = "Power Button"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - reg_vref_0v9: regulator-vref-0v9 { - compatible = "regulator-fixed"; - regulator-name = "vref-0v9"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - }; - - reg_vref_1v8: regulator-vref-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_vref_2v5: regulator-vref-2v5 { - compatible = "regulator-fixed"; - regulator-name = "vref-2v5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - reg_vref_3v3: regulator-vref-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vref-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_vref_5v: regulator-vref-5v { - compatible = "regulator-fixed"; - regulator-name = "vref-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@4 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <4>; - interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - i2cmux@70 { - compatible = "nxp,pca9546"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_pca9546>; - reg = <0x70>; - reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - #address-cells = <1>; - #size-cells = <0>; - - i2c1a: i2c1@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - reg_arm_dram: regulator@60 { - compatible = "fcs,fan53555"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_arm_dram>; - reg = <0x60>; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; - }; - }; - - i2c1b: i2c1@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - reg_dram_1p1v: regulator@60 { - compatible = "fcs,fan53555"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_dram_1p1v>; - reg = <0x60>; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - vsel-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; - }; - }; - - i2c1c: i2c1@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - reg_soc_gpu_vpu: regulator@60 { - compatible = "fcs,fan53555"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>; - reg = <0x60>; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; - }; - }; - - i2c1d: i2c1@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@68 { - compatible = "microcrystal,rv4162"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1d_rv4162>; - reg = <0x68>; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>; - wakeup-source; - }; - }; - }; -}; - -&uart1 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clk IMX8MQ_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - assigned-clocks = <&clk IMX8MQ_CLK_UART2>; - assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; - status = "okay"; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - non-removable; - vmmc-supply = <®_vref_1v8>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - /* J17 connector, odd */ - MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* Pin 19 */ - MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 /* Pin 21 */ - MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x19 /* Pin 23 */ - MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* Pin 25 */ - MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* Pin 27 */ - MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* Pin 29 */ - MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 /* Pin 31 */ - MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 /* Pin 33 */ - MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 /* Pin 35 */ - MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x19 /* Pin 39 */ - MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* Pin 41 */ - MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* Pin 43 */ - MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* Pin 45 */ - MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* Pin 47 */ - MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* Pin 49 */ - MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* Pin 51 */ - - /* J17 connector, even */ - MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* Pin 44 */ - MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 /* Pin 48 */ - MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* Pin 50 */ - MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* Pin 54 */ - MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* Pin 56 */ - - /* J18 connector, odd */ - MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* Pin 41 */ - MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* Pin 43 */ - MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* Pin 45 */ - MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* Pin 47 */ - MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* Pin 49 */ - MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* Pin 53 */ - - /* J18 connector, even */ - MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* Pin 32 */ - MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* Pin 36 */ - MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* Pin 38 */ - MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* Pin 40 */ - MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* Pin 42 */ - MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* Pin 44 */ - MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* Pin 46 */ - - /* J13 Pin 2, WL_WAKE */ - MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0xd6 - /* J13 Pin 4, WL_IRQ, not needed for Silex */ - MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0xd6 - /* J13 pin 9, unused */ - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - /* J13 Pin 41, BT_CLK_REQ */ - MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0xd6 - /* J13 Pin 42, BT_HOST_WAKE */ - MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0xd6 - - /* Clock for both CSI1 and CSI2 */ - MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x07 - /* test points */ - MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 /* TP87 */ - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59 - >; - }; - - pinctrl_gpio_keys: gpio-keysgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 - >; - }; - - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f - >; - }; - - pinctrl_i2c1_pca9546: i2c1-pca9546grp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49 - >; - }; - - pinctrl_i2c1d_rv4162: i2c1d-rv4162grp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x49 - >; - }; - - pinctrl_reg_arm_dram: reg-arm-dramgrp { - fsl,pins = < - MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16 - >; - }; - - pinctrl_reg_dram_1p1v: reg-dram-1p1vgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16 - >; - }; - - pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpugrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45 - MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts deleted file mode 100644 index a3b9d615a..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +++ /dev/null @@ -1,481 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2017-2019 NXP - */ - -/dts-v1/; - -#include "imx8mq.dtsi" -#include - -/ { - model = "Google i.MX8MQ Phanbell"; - compatible = "google,imx8mq-phanbell", "fsl,imx8mq"; - - chosen { - stdout-path = &uart1; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x00000000 0x40000000 0 0x40000000>; - }; - - pmic_osc: clock-pmic { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "pmic_osc"; - }; - - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - fan: gpio-fan { - compatible = "gpio-fan"; - gpio-fan,speed-map = <0 0 8600 1>; - gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; - #cooling-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_fan>; - status = "okay"; - }; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -&cpu_thermal { - trips { - cpu_alert0: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_alert1: trip1 { - temperature = <80000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit0: trip3 { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - - fan_toggle0: trip4 { - temperature = <65000>; - hysteresis = <10000>; - type = "active"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&A53_0 0 1>; /* Exclude highest OPP */ - }; - - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&A53_0 0 2>; /* Exclude two highest OPPs */ - }; - - map4 { - trip = <&fan_toggle0>; - cooling-device = <&fan 0 1>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pmic@4b { - compatible = "rohm,bd71837"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - #clock-cells = <0>; - clocks = <&pmic_osc>; - clock-output-names = "pmic_clk"; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - regulators { - buck1: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <900000>; - rohm,dvs-idle-voltage = <900000>; - rohm,dvs-suspend-voltage = <800000>; - }; - - buck2: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - buck3: BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - rohm,dvs-run-voltage = <900000>; - }; - - buck4: BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - rohm,dvs-run-voltage = <900000>; - }; - - buck5: BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck7: BUCK7 { - regulator-name = "buck7"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck8: BUCK8 { - regulator-name = "buck8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5: LDO5 { - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo6: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo7: LDO7 { - regulator-name = "ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <50000>; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb_dwc3_0 { - dr_mode = "otg"; - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - >; - }; - - pinctrl_gpio_fan: gpiofangrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 - MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts b/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts deleted file mode 100644 index 89cbec5c4..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts +++ /dev/null @@ -1,418 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018 Wandboard, Org. - * Copyright 2017 NXP - * - * Author: Richard Hu - */ - -/dts-v1/; - -#include "imx8mq.dtsi" -#include - -/ { - model = "TechNexion PICO-PI-8M"; - compatible = "technexion,pico-pi-imx8m", "fsl,imx8mq"; - - chosen { - stdout-path = &uart1; - }; - - pmic_osc: clock-pmic { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "pmic_osc"; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_otg_vbus>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 14 GPIO_ACTIVE_LOW>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1 &pinctrl_enet_3v3>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pmic@4b { - reg = <0x4b>; - compatible = "rohm,bd71837"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - clocks = <&pmic_osc>; - clock-names = "osc"; - clock-output-names = "pmic_clk"; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "irq"; - - regulators { - buck1: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <900000>; - rohm,dvs-idle-voltage = <850000>; - rohm,dvs-suspend-voltage = <800000>; - }; - - buck2: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - buck3: BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - rohm,dvs-run-voltage = <1000000>; - }; - - buck4: BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - rohm,dvs-run-voltage = <1000000>; - }; - - buck5: BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - }; - - buck6: BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - buck7: BUCK7 { - regulator-name = "buck7"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - }; - - buck8: BUCK8 { - regulator-name = "buck8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - }; - - ldo1: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - ldo4: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - ldo5: LDO5 { - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - ldo6: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - ldo7: LDO7 { - regulator-name = "ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&uart1 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_enet_3v3: enet3v3grp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f - MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f - >; - }; - - pinctrl_otg_vbus: otgvbusgrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* USB OTG VBUS Enable */ - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 - MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 - MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 - MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h deleted file mode 100644 index 68e8fa172..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h +++ /dev/null @@ -1,623 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - */ - -#ifndef __DTS_IMX8MQ_PINFUNC_H -#define __DTS_IMX8MQ_PINFUNC_H - -/* - * The pin function ID is a tuple of - * - */ - -#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 -#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 -#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1 -#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2 -#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 -#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1 -#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4 -#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3 -#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1 -#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0 -#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1 -#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2 -#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 -#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 -#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2 -#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2 -#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3 -#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 -#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 -#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 -#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 -#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 -#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 -#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 -#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 -#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1 -#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 -#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 -#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 -#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1 -#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 -#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0 -#define MX8MQ_IOMUXC_TEST_MODE 0x000 0x254 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_BOOT_MODE0 0x000 0x258 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_BOOT_MODE1 0x000 0x25C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_MOD 0x000 0x260 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TRST_B 0x000 0x264 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TDI 0x000 0x268 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TMS 0x000 0x26C 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TCK 0x000 0x270 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_JTAG_TDO 0x000 0x274 0x000 0x0 0x0 -#define MX8MQ_IOMUXC_RTC 0x000 0x278 0x000 0x0 0x0 - -#endif /* __DTS_IMX8MQ_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi deleted file mode 100644 index 0187890a9..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi +++ /dev/null @@ -1,317 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2018 Jon Nettleton - */ - -#include "imx8mq.dtsi" - -/ { - reg_vdd_3v3: regulator-vdd-3v3 { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-name = "vdd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@4 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <4>; - reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - reset-assert-us = <2000>; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <400000>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sw3a_reg: sw3ab { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - - eeprom@50 { - compatible = "atmel,24c01"; - reg = <0x50>; - status = "okay"; - }; -}; - -&pgc_gpu{ - power-supply = <&sw1a_reg>; -}; - -&pgc_vpu { - power-supply = <&sw1c_reg>; -}; - -&qspi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - - /* SPI flash; not assembled by default */ - spi_flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - compatible = "micron,n25q256a", "jedec,spi-nor"; - spi-max-frequency = <29000000>; - status = "disabled"; - }; -}; - -&uart1 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clk IMX8MQ_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; - assigned-clock-rates = <25000000>; - status = "okay"; -}; - -&uart4 { /* ublox BT */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - assigned-clocks = <&clk IMX8MQ_CLK_UART4>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; - assigned-clock-rates = <80000000>; - status = "okay"; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x74 - MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x16 - MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16 - >; - }; - - pinctrl_qspi: qspigrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 - MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49 - MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49 - MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-thor96.dts b/arch/arm64/boot/dts/freescale/imx8mq-thor96.dts deleted file mode 100644 index 5d5aa6537..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mq-thor96.dts +++ /dev/null @@ -1,581 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 Einfochips - * Copyright 2019 Linaro Ltd. - */ - -/dts-v1/; - -#include "imx8mq.dtsi" - -/ { - model = "Einfochips i.MX8MQ Thor96"; - compatible = "einfochips,imx8mq-thor96", "fsl,imx8mq"; - - chosen { - stdout-path = &uart1; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x00000000 0x40000000 0 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - user-led1 { - label = "green:user1"; - gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - user-led2 { - label = "green:user2"; - gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - }; - - user-led3 { - label = "green:user3"; - gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - user-led4 { - label = "green:user4"; - gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; - panic-indicator; - linux,default-trigger = "none"; - }; - - wlan-active-led { - label = "yellow:wlan"; - gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - bt-active-led { - label = "blue:bt"; - gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "hci0-power"; - default-state = "off"; - }; - }; - - reg_usdhc1_vmmc: reg-usdhc1-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usdhc1_vqmmc: reg-usdhc1-vqmmc { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8_EXT"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_usdhc2_vmmc: reg-usdhc2-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usdhc2_vqmmc: reg-usdhc2-vqmmc { - compatible = "regulator-fixed"; - regulator-name = "NVCC_SD2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_reg_on>; - gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>; - }; -}; - -/* LS-SPI0 */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@3 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <3>; - reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - }; - }; -}; - -/* LS-I2C0 */ -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x8>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sw3a_reg: sw3ab { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; -}; - -/* LS-I2C1 */ -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - eeprom: eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; - -/* HS-I2C2 */ -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -/* HS-I2C3 */ -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; -}; - -&pgc_gpu { - power-supply = <&sw1a_reg>; -}; - -&pgc_vpu { - power-supply = <&sw1c_reg>; -}; - -&qspi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi0>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <100000000>; - reg = <0>; - }; -}; - -/* Debug UART */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clk IMX8MQ_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; - status = "okay"; -}; - -/* LS-UART0 */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - assigned-clocks = <&clk IMX8MQ_CLK_UART2>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - device-wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt_gpios>; - }; -}; - -/* LS-UART1 */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clk IMX8MQ_CLK_UART3>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -/* SDIO */ -&usdhc1 { - #address-cells = <0x1>; - #size-cells = <0x0>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - vmmc-supply = <®_usdhc1_vmmc>; - vqmmc-supply = <®_usdhc1_vqmmc>; - mmc-pwrseq = <&sdio_pwrseq>; - bus-width = <4>; - non-removable; - no-sd; - no-emmc; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* uSD */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - vmmc-supply = <®_usdhc2_vmmc>; - vqmmc-supply = <®_usdhc2_vqmmc>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - no-sdio; - no-emmc; - disable-wp; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_bt_gpios: btgpiosgrp { - fsl,pins = < - MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 - MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 - MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x16 - MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x16 - MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x16 - MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x16 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x4 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x24 - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1c - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1c - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1c - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1c - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1c - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1c - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f - MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f - MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f - MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x19 - MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 - MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 - MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 - MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 - MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 - >; - }; - - pinctrl_qspi0: qspi0grp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 - MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - - >; - }; - - pinctrl_reg_usdhc2: regusdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 - MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 - MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 - MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 - MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x85 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd - MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x85 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf - MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x85 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8c - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcc - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcc - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcc - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcc - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcc - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9c - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdc - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdc - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdc - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdc - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdc - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xcc - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; - - pinctrl_wifi_reg_on: wifiregongrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts deleted file mode 100644 index bfad4b885..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2019 Zodiac Inflight Innovations - */ - -/dts-v1/; - -#include "imx8mq-zii-ultra.dtsi" - -/ { - model = "ZII Ultra RMB3 Board"; - compatible = "zii,imx8mq-ultra-rmb3", "zii,imx8mq-ultra", "fsl,imx8mq"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - nor_flash: flash@0 { - compatible = "st,n25q128a13", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&i2c2 { - temp-sense@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; -}; - -&i2c4 { - touchscreen@20 { - compatible = "syna,rmi4-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts>; - reg = <0x20>; - interrupt-parent = <&gpio1>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - - #address-cells = <1>; - #size-cells = <0>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <2>; - }; - - rmi4-f11@11 { - reg = <0x11>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - syna,sensor-type = <1>; - }; - - rmi4-f12@12 { - reg = <0x12>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - syna,sensor-type = <1>; - }; - }; - - touchscreen@2a { - compatible = "eeti,exc3000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts>; - reg = <0x2a>; - interrupt-parent = <&gpio1>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - status = "disabled"; - }; -}; - -&usbhub { - swap-dx-lanes = <0>; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 - MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 - MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 - MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts deleted file mode 100644 index 173b9e9b2..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2019 Zodiac Inflight Innovations - */ - -/dts-v1/; - -#include "imx8mq-zii-ultra.dtsi" - -/ { - model = "ZII Ultra Zest Board"; - compatible = "zii,imx8mq-ultra-zest", "zii,imx8mq-ultra", "fsl,imx8mq"; -}; - -&i2c4 { - touchscreen@4a { - compatible = "atmel,maxtouch"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ts>; - reg = <0x4a>; - interrupt-parent = <&gpio1>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi deleted file mode 100644 index 825c83c71..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi +++ /dev/null @@ -1,771 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2019 Zodiac Inflight Innovations - */ - -#include "imx8mq.dtsi" - -/ { - aliases { - mdio-gpio0 = &mdio0; - rtc0 = &ds1341; - }; - - chosen { - stdout-path = &uart1; - }; - - mdio0: bitbang-mdio { - compatible = "virtual,mdio-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mdio_bitbang>, <&pinctrl_fec1_phy_reset>; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>, /* MDC */ - <&gpio1 14 GPIO_ACTIVE_HIGH>; /* MDIO */ - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - reg = <0>; - reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - }; - }; - - pcie0_refclk: clock-pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pcie1_refclk: clock-pcie1-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - reg_12p0_main: regulator-12p0-main { - compatible = "regulator-fixed"; - regulator-name = "12V_MAIN"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - reg_5p0_main: regulator-5p0-main { - compatible = "regulator-fixed"; - vin-supply = <®_12p0_main>; - regulator-name = "5V_MAIN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_3p3_main: regulator-3p3-main { - compatible = "regulator-fixed"; - vin-supply = <®_12p0_main>; - regulator-name = "3V3_MAIN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_gen_3p3: regulator-gen-3p3 { - compatible = "regulator-fixed"; - vin-supply = <®_3p3_main>; - regulator-name = "GEN_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usdhc2_vmmc: regulator-vsd-3v3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2>; - compatible = "regulator-fixed"; - vin-supply = <®_gen_3p3>; - regulator-name = "3V3_SD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_arm: regulator-arm { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_arm>; - compatible = "regulator-gpio"; - vin-supply = <®_12p0_main>; - regulator-name = "0V9_ARM"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1000000>; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - states = <1000000 0x1 - 900000 0x0>; - regulator-always-on; - }; -}; - -&A53_0 { - cpu-supply = <®_arm>; -}; - -&A53_1 { - cpu-supply = <®_arm>; -}; - -&A53_2 { - cpu-supply = <®_arm>; -}; - -&A53_3 { - cpu-supply = <®_arm>; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - - phy-handle = <&phy0>; - phy-mode = "rmii"; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <12500000>; - suppress-preamble; - status = "okay"; - - switch: switch@0 { - compatible = "marvell,mv88e6085"; - pinctrl-0 = <&pinctrl_switch_irq>; - pinctrl-names = "default"; - reg = <0>; - dsa,member = <0 0>; - eeprom-length = <512>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "gigabit_proc"; - phy-handle = <&switchphy0>; - }; - - port@1 { - reg = <1>; - label = "netaux"; - phy-handle = <&switchphy1>; - }; - - port@2 { - reg = <2>; - label = "cpu"; - ethernet = <&fec1>; - - fixed-link { - speed = <100>; - full-duplex; - }; - }; - - port@3 { - reg = <3>; - label = "netright"; - phy-handle = <&switchphy3>; - }; - - port@4 { - reg = <4>; - label = "netleft"; - phy-handle = <&switchphy4>; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switchphy0: switchphy@0 { - reg = <0>; - interrupt-parent = <&switch>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy1: switchphy@1 { - reg = <1>; - interrupt-parent = <&switch>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy2: switchphy@2 { - reg = <2>; - interrupt-parent = <&switch>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy3: switchphy@3 { - reg = <3>; - interrupt-parent = <&switch>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; - }; - - switchphy4: switchphy@4 { - reg = <4>; - interrupt-parent = <&switch>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; - }; -}; - -&gpio3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio3_hog>; - - usb-emulation-hog { - gpio-hog; - gpios = <10 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "usb-emulation"; - }; - - usb-mode1-hog { - gpio-hog; - gpios = <11 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb-mode1"; - }; - - usb-pwr-hog { - gpio-hog; - gpios = <12 GPIO_ACTIVE_LOW>; - output-high; - line-name = "usb-pwr-ctrl-en-n"; - }; - - usb-mode2-hog { - gpio-hog; - gpios = <13 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb-mode2"; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - accelerometer@1c { - compatible = "fsl,mma8451"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_accel>; - reg = <0x1c>; - interrupt-parent = <&gpio3>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT2"; - vdd-supply = <®_gen_3p3>; - vddio-supply = <®_gen_3p3>; - }; - - ucs1002: charger@32 { - compatible = "microchip,ucs1002"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ucs1002>; - reg = <0x32>; - interrupt-parent = <&gpio3>; - interrupts = <17 IRQ_TYPE_EDGE_BOTH>, - <18 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "a_det", "alert"; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x8>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - }; - - sw1c_reg: sw1c { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - sw3a_reg: sw3ab { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <975000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1675000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1625000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3625000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - - eeprom@54 { - compatible = "atmel,24c128"; - reg = <0x54>; - }; - - ds1341: rtc@68 { - compatible = "dallas,ds1341"; - reg = <0x68>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - usbhub: usbhub@2c { - compatible ="microchip,usb2513b"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbhub>; - reg = <0x2c>; - reset-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; - }; - - watchdog@38 { - compatible = "zii,rave-wdt"; - reg = <0x38>; - }; -}; - -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; - - rave-sp { - compatible = "zii,rave-sp-rdu2"; - current-speed = <1000000>; - #address-cells = <1>; - #size-cells = <1>; - - watchdog { - compatible = "zii,rave-sp-watchdog"; - }; - - backlight { - compatible = "zii,rave-sp-backlight"; - }; - - pwrbutton { - compatible = "zii,rave-sp-pwrbutton"; - }; - - eeprom@a3 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa3 0x4000>; - zii,eeprom-name = "dds-eeprom"; - }; - - eeprom@a4 { - compatible = "zii,rave-sp-eeprom"; - reg = <0xa4 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - zii,eeprom-name = "main-eeprom"; - }; - }; -}; - -&usb3_phy0 { - vbus-supply = <&ucs1002>; - status = "okay"; -}; - -&usb_dwc3_0 { - dr_mode = "host"; - status = "okay"; -}; - -&usb3_phy1 { - vbus-supply = <®_5p0_main>; - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, - <&clk IMX8MQ_CLK_PCIE1_AUX>, - <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; - status = "okay"; -}; - -&pcie1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie1>; - reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, - <&clk IMX8MQ_CLK_PCIE2_AUX>, - <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&pcie1_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; - status = "okay"; -}; - -&pgc_gpu { - power-supply = <&sw1a_reg>; -}; - -&pgc_vpu { - power-supply = <&sw1c_reg>; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - vqmmc-supply = <&sw4_reg>; - bus-width = <8>; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&snvs_rtc { - status = "disabled"; -}; - -&iomuxc { - pinctrl_accel: accelgrp { - fsl,pins = < - MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x1f - MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x91 - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - >; - }; - - pinctrl_fec1_phy_reset: fec1phyresetgrp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x11 - >; - }; - - pinctrl_gpio3_hog: gpio3hoggrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x6 - MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x6 - MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x6 - MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x6 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f - MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f - MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f - MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f - >; - }; - - pinctrl_mdio_bitbang: bitbangmdiogrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x44 - MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x64 - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x66 - MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x6 - >; - }; - - pinctrl_pcie1: pcie1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x66 - MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x6 - >; - }; - - pinctrl_reg_arm: regarmgrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 - >; - }; - - pinctrl_reg_usdhc2: regusdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_switch_irq: switchgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 - >; - }; - - pinctrl_ts: tsgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x96 - MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x96 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 - MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 - >; - }; - - pinctrl_ucs1002: ucs1002grp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x41 - MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x41 - >; - }; - - pinctrl_usbhub: usbhubgrp { - fsl,pins = < - MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x41 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi deleted file mode 100644 index 8d0d41973..000000000 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ /dev/null @@ -1,1339 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2017 NXP - * Copyright (C) 2017-2018 Pengutronix, Lucas Stach - */ - -#include -#include -#include -#include -#include "dt-bindings/input/input.h" -#include -#include -#include "imx8mq-pinfunc.h" - -/ { - interrupt-parent = <&gpc>; - - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet0 = &fec1; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - }; - - ckil: clock-ckil { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ckil"; - }; - - osc_25m: clock-osc-25m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "osc_25m"; - }; - - osc_27m: clock-osc-27m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - clock-output-names = "osc_27m"; - }; - - clk_ext1: clock-ext1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext1"; - }; - - clk_ext2: clock-ext2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext2"; - }; - - clk_ext3: clock-ext3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext3"; - }; - - clk_ext4: clock-ext4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency= <133000000>; - clock-output-names = "clk_ext4"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - A53_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MQ_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - #cooling-cells = <2>; - nvmem-cells = <&cpu_speed_grade>; - nvmem-cell-names = "speed_grade"; - }; - - A53_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MQ_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - #cooling-cells = <2>; - }; - - A53_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x2>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MQ_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - #cooling-cells = <2>; - }; - - A53_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x3>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MQ_CLK_ARM>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - #cooling-cells = <2>; - }; - - A53_L2: l2-cache0 { - compatible = "cache"; - }; - }; - - a53_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <900000>; - /* Industrial only */ - opp-supported-hw = <0xf>, <0x4>; - clock-latency-ns = <150000>; - opp-suspend; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <900000>; - /* Consumer only */ - opp-supported-hw = <0xe>, <0x3>; - clock-latency-ns = <150000>; - opp-suspend; - }; - - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1000000>; - opp-supported-hw = <0xc>, <0x4>; - clock-latency-ns = <150000>; - opp-suspend; - }; - - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1000000>; - opp-supported-hw = <0x8>, <0x3>; - clock-latency-ns = <150000>; - opp-suspend; - }; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - interrupt-parent = <&gic>; - interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu 0>; - - trips { - cpu_alert: cpu-alert { - temperature = <80000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu 1>; - - trips { - gpu_alert: gpu-alert { - temperature = <80000>; - hysteresis = <2000>; - type = "passive"; - }; - - gpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_alert>; - cooling-device = - <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - vpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu 2>; - - trips { - vpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , /* Physical Secure */ - , /* Physical Non-Secure */ - , /* Virtual */ - ; /* Hypervisor */ - interrupt-parent = <&gic>; - arm,no-tick-in-suspend; - }; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x3e000000>; - dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; - - bus@30000000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x30000000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x30000000 0x30000000 0x400000>; - - sai1: sai@30010000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x30010000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, - <&clk IMX8MQ_CLK_SAI1_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai6: sai@30030000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x30030000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, - <&clk IMX8MQ_CLK_SAI6_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai5: sai@30040000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x30040000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, - <&clk IMX8MQ_CLK_SAI5_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai4: sai@30050000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x30050000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, - <&clk IMX8MQ_CLK_SAI4_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - gpio1: gpio@30200000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30200000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 10 30>; - }; - - gpio2: gpio@30210000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30210000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 40 21>; - }; - - gpio3: gpio@30220000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30220000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 61 26>; - }; - - gpio4: gpio@30230000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30230000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 87 32>; - }; - - gpio5: gpio@30240000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30240000 0x10000>; - interrupts = , - ; - clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 119 30>; - }; - - tmu: tmu@30260000 { - compatible = "fsl,imx8mq-tmu"; - reg = <0x30260000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_TMU_ROOT>; - little-endian; - fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; - fsl,tmu-calibration = <0x00000000 0x00000023 - 0x00000001 0x00000029 - 0x00000002 0x0000002f - 0x00000003 0x00000035 - 0x00000004 0x0000003d - 0x00000005 0x00000043 - 0x00000006 0x0000004b - 0x00000007 0x00000051 - 0x00000008 0x00000057 - 0x00000009 0x0000005f - 0x0000000a 0x00000067 - 0x0000000b 0x0000006f - - 0x00010000 0x0000001b - 0x00010001 0x00000023 - 0x00010002 0x0000002b - 0x00010003 0x00000033 - 0x00010004 0x0000003b - 0x00010005 0x00000043 - 0x00010006 0x0000004b - 0x00010007 0x00000055 - 0x00010008 0x0000005d - 0x00010009 0x00000067 - 0x0001000a 0x00000070 - - 0x00020000 0x00000017 - 0x00020001 0x00000023 - 0x00020002 0x0000002d - 0x00020003 0x00000037 - 0x00020004 0x00000041 - 0x00020005 0x0000004b - 0x00020006 0x00000057 - 0x00020007 0x00000063 - 0x00020008 0x0000006f - - 0x00030000 0x00000015 - 0x00030001 0x00000021 - 0x00030002 0x0000002d - 0x00030003 0x00000039 - 0x00030004 0x00000045 - 0x00030005 0x00000053 - 0x00030006 0x0000005f - 0x00030007 0x00000071>; - #thermal-sensor-cells = <1>; - }; - - wdog1: watchdog@30280000 { - compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; - reg = <0x30280000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; - status = "disabled"; - }; - - wdog2: watchdog@30290000 { - compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; - reg = <0x30290000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; - status = "disabled"; - }; - - wdog3: watchdog@302a0000 { - compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; - reg = <0x302a0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; - status = "disabled"; - }; - - sdma2: sdma@302c0000 { - compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; - reg = <0x302c0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>, - <&clk IMX8MQ_CLK_SDMA2_ROOT>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - lcdif: lcd-controller@30320000 { - compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; - reg = <0x30320000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; - clock-names = "pix"; - assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, - <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, - <&clk IMX8MQ_CLK_LCDIF_PIXEL>, - <&clk IMX8MQ_VIDEO_PLL1>; - assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, - <&clk IMX8MQ_VIDEO_PLL1>, - <&clk IMX8MQ_VIDEO_PLL1_OUT>; - assigned-clock-rates = <0>, <0>, <0>, <594000000>; - status = "disabled"; - - port { - lcdif_mipi_dsi: endpoint { - remote-endpoint = <&mipi_dsi_lcdif_in>; - }; - }; - }; - - iomuxc: pinctrl@30330000 { - compatible = "fsl,imx8mq-iomuxc"; - reg = <0x30330000 0x10000>; - }; - - iomuxc_gpr: syscon@30340000 { - compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", - "syscon", "simple-mfd"; - reg = <0x30340000 0x10000>; - - mux: mux-controller { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */ - }; - }; - - ocotp: efuse@30350000 { - compatible = "fsl,imx8mq-ocotp", "syscon"; - reg = <0x30350000 0x10000>; - clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; - #address-cells = <1>; - #size-cells = <1>; - - cpu_speed_grade: speed-grade@10 { - reg = <0x10 4>; - }; - }; - - anatop: syscon@30360000 { - compatible = "fsl,imx8mq-anatop", "syscon"; - reg = <0x30360000 0x10000>; - interrupts = ; - }; - - snvs: snvs@30370000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x30370000 0x10000>; - - snvs_rtc: snvs-rtc-lp{ - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap =<&snvs>; - offset = <0x34>; - interrupts = , - ; - clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; - clock-names = "snvs-rtc"; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; - clock-names = "snvs-pwrkey"; - linux,keycode = ; - wakeup-source; - status = "disabled"; - }; - }; - - clk: clock-controller@30380000 { - compatible = "fsl,imx8mq-ccm"; - reg = <0x30380000 0x10000>; - interrupts = , - ; - #clock-cells = <1>; - clocks = <&ckil>, <&osc_25m>, <&osc_27m>, - <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; - clock-names = "ckil", "osc_25m", "osc_27m", - "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; - assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>, - <&clk IMX8MQ_CLK_A53_CORE>, - <&clk IMX8MQ_CLK_NOC>; - assigned-clock-rates = <0>, <0>, - <800000000>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, - <&clk IMX8MQ_ARM_PLL_OUT>; - }; - - src: reset-controller@30390000 { - compatible = "fsl,imx8mq-src", "syscon"; - reg = <0x30390000 0x10000>; - interrupts = ; - #reset-cells = <1>; - }; - - gpc: gpc@303a0000 { - compatible = "fsl,imx8mq-gpc"; - reg = <0x303a0000 0x10000>; - interrupts = ; - interrupt-parent = <&gic>; - interrupt-controller; - #interrupt-cells = <3>; - - pgc { - #address-cells = <1>; - #size-cells = <0>; - - pgc_mipi: power-domain@0 { - #power-domain-cells = <0>; - reg = ; - }; - - /* - * As per comment in ATF source code: - * - * PCIE1 and PCIE2 share the - * same reset signal, if we - * power down PCIE2, PCIE1 - * will be held in reset too. - * - * So instead of creating two - * separate power domains for - * PCIE1 and PCIE2 we create a - * link between both and use - * it as a shared PCIE power - * domain. - */ - pgc_pcie: power-domain@1 { - #power-domain-cells = <0>; - reg = ; - power-domains = <&pgc_pcie2>; - }; - - pgc_otg1: power-domain@2 { - #power-domain-cells = <0>; - reg = ; - }; - - pgc_otg2: power-domain@3 { - #power-domain-cells = <0>; - reg = ; - }; - - pgc_ddr1: power-domain@4 { - #power-domain-cells = <0>; - reg = ; - }; - - pgc_gpu: power-domain@5 { - #power-domain-cells = <0>; - reg = ; - clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, - <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, - <&clk IMX8MQ_CLK_GPU_AXI>, - <&clk IMX8MQ_CLK_GPU_AHB>; - }; - - pgc_vpu: power-domain@6 { - #power-domain-cells = <0>; - reg = ; - clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; - }; - - pgc_disp: power-domain@7 { - #power-domain-cells = <0>; - reg = ; - }; - - pgc_mipi_csi1: power-domain@8 { - #power-domain-cells = <0>; - reg = ; - }; - - pgc_mipi_csi2: power-domain@9 { - #power-domain-cells = <0>; - reg = ; - }; - - pgc_pcie2: power-domain@a { - #power-domain-cells = <0>; - reg = ; - }; - }; - }; - }; - - bus@30400000 { /* AIPS2 */ - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x30400000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x30400000 0x30400000 0x400000>; - - pwm1: pwm@30660000 { - compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; - reg = <0x30660000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, - <&clk IMX8MQ_CLK_PWM1_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@30670000 { - compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; - reg = <0x30670000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, - <&clk IMX8MQ_CLK_PWM2_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@30680000 { - compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; - reg = <0x30680000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, - <&clk IMX8MQ_CLK_PWM3_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@30690000 { - compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; - reg = <0x30690000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, - <&clk IMX8MQ_CLK_PWM4_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - system_counter: timer@306a0000 { - compatible = "nxp,sysctr-timer"; - reg = <0x306a0000 0x20000>; - interrupts = ; - clocks = <&osc_25m>; - clock-names = "per"; - }; - }; - - bus@30800000 { /* AIPS3 */ - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x30800000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x30800000 0x30800000 0x400000>, - <0x08000000 0x08000000 0x10000000>; - - ecspi1: spi@30820000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; - reg = <0x30820000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, - <&clk IMX8MQ_CLK_ECSPI1_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi2: spi@30830000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; - reg = <0x30830000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, - <&clk IMX8MQ_CLK_ECSPI2_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - ecspi3: spi@30840000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; - reg = <0x30840000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, - <&clk IMX8MQ_CLK_ECSPI3_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart1: serial@30860000 { - compatible = "fsl,imx8mq-uart", - "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, - <&clk IMX8MQ_CLK_UART1_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart3: serial@30880000 { - compatible = "fsl,imx8mq-uart", - "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, - <&clk IMX8MQ_CLK_UART3_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@30890000 { - compatible = "fsl,imx8mq-uart", - "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, - <&clk IMX8MQ_CLK_UART2_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - sai2: sai@308b0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x308b0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, - <&clk IMX8MQ_CLK_SAI2_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai3: sai@308c0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x308c0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, - <&clk IMX8MQ_CLK_SAI3_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - crypto: crypto@30900000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30900000 0x40000>; - ranges = <0 0x30900000 0x40000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_AHB>, - <&clk IMX8MQ_CLK_IPG_ROOT>; - clock-names = "aclk", "ipg"; - - sec_jr0: jr@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - sec_jr1: jr@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = ; - }; - - sec_jr2: jr@3000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x3000 0x1000>; - interrupts = ; - }; - }; - - mipi_dsi: mipi-dsi@30a00000 { - compatible = "fsl,imx8mq-nwl-dsi"; - reg = <0x30a00000 0x300>; - clocks = <&clk IMX8MQ_CLK_DSI_CORE>, - <&clk IMX8MQ_CLK_DSI_AHB>, - <&clk IMX8MQ_CLK_DSI_IPG_DIV>, - <&clk IMX8MQ_CLK_DSI_PHY_REF>, - <&clk IMX8MQ_CLK_LCDIF_PIXEL>; - clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif"; - assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>, - <&clk IMX8MQ_CLK_DSI_CORE>, - <&clk IMX8MQ_CLK_DSI_IPG_DIV>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>, - <&clk IMX8MQ_SYS1_PLL_266M>; - assigned-clock-rates = <80000000>, <266000000>, <20000000>; - interrupts = ; - mux-controls = <&mux 0>; - power-domains = <&pgc_mipi>; - phys = <&dphy>; - phy-names = "dphy"; - resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>, - <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>, - <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>, - <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>; - reset-names = "byte", "dpi", "esc", "pclk"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - mipi_dsi_lcdif_in: endpoint@0 { - reg = <0>; - remote-endpoint = <&lcdif_mipi_dsi>; - }; - }; - }; - }; - - dphy: dphy@30a00300 { - compatible = "fsl,imx8mq-mipi-dphy"; - reg = <0x30a00300 0x100>; - clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; - clock-names = "phy_ref"; - assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; - assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>; - assigned-clock-rates = <24000000>; - #phy-cells = <0>; - power-domains = <&pgc_mipi>; - status = "disabled"; - }; - - i2c1: i2c@30a20000 { - compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; - reg = <0x30a20000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@30a30000 { - compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; - reg = <0x30a30000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@30a40000 { - compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; - reg = <0x30a40000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@30a50000 { - compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; - reg = <0x30a50000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart4: serial@30a60000 { - compatible = "fsl,imx8mq-uart", - "fsl,imx6q-uart"; - reg = <0x30a60000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, - <&clk IMX8MQ_CLK_UART4_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - mu: mailbox@30aa0000 { - compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; - reg = <0x30aa0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_MU_ROOT>; - #mbox-cells = <2>; - }; - - usdhc1: mmc@30b40000 { - compatible = "fsl,imx8mq-usdhc", - "fsl,imx7d-usdhc"; - reg = <0x30b40000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, - <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, - <&clk IMX8MQ_CLK_USDHC1_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step = <2>; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: mmc@30b50000 { - compatible = "fsl,imx8mq-usdhc", - "fsl,imx7d-usdhc"; - reg = <0x30b50000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, - <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, - <&clk IMX8MQ_CLK_USDHC2_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step = <2>; - bus-width = <4>; - status = "disabled"; - }; - - qspi0: spi@30bb0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi"; - reg = <0x30bb0000 0x10000>, - <0x08000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>, - <&clk IMX8MQ_CLK_QSPI_ROOT>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - sdma1: sdma@30bd0000 { - compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; - reg = <0x30bd0000 0x10000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>, - <&clk IMX8MQ_CLK_AHB>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - fec1: ethernet@30be0000 { - compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; - reg = <0x30be0000 0x10000>; - interrupts = , - , - , - ; - clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, - <&clk IMX8MQ_CLK_ENET1_ROOT>, - <&clk IMX8MQ_CLK_ENET_TIMER>, - <&clk IMX8MQ_CLK_ENET_REF>, - <&clk IMX8MQ_CLK_ENET_PHY_REF>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; - status = "disabled"; - }; - }; - - bus@32c00000 { /* AIPS4 */ - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x32c00000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x32c00000 0x32c00000 0x400000>; - - irqsteer: interrupt-controller@32e2d000 { - compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; - reg = <0x32e2d000 0x1000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; - clock-names = "ipg"; - fsl,channel = <0>; - fsl,num-irqs = <64>; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - gpu: gpu@38000000 { - compatible = "vivante,gc"; - reg = <0x38000000 0x40000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, - <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, - <&clk IMX8MQ_CLK_GPU_AXI>, - <&clk IMX8MQ_CLK_GPU_AHB>; - clock-names = "core", "shader", "bus", "reg"; - #cooling-cells = <2>; - assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, - <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, - <&clk IMX8MQ_CLK_GPU_AXI>, - <&clk IMX8MQ_CLK_GPU_AHB>, - <&clk IMX8MQ_GPU_PLL_BYPASS>; - assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL>; - assigned-clock-rates = <800000000>, <800000000>, - <800000000>, <800000000>, <0>; - power-domains = <&pgc_gpu>; - }; - - usb_dwc3_0: usb@38100000 { - compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; - reg = <0x38100000 0x10000>; - clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>, - <&clk IMX8MQ_CLK_USB_CORE_REF>, - <&clk IMX8MQ_CLK_32K>; - clock-names = "bus_early", "ref", "suspend"; - assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, - <&clk IMX8MQ_CLK_USB_CORE_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, - <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <500000000>, <100000000>; - interrupts = ; - phys = <&usb3_phy0>, <&usb3_phy0>; - phy-names = "usb2-phy", "usb3-phy"; - power-domains = <&pgc_otg1>; - usb3-resume-missing-cas; - status = "disabled"; - }; - - usb3_phy0: usb-phy@381f0040 { - compatible = "fsl,imx8mq-usb-phy"; - reg = <0x381f0040 0x40>; - clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; - clock-names = "phy"; - assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <100000000>; - #phy-cells = <0>; - status = "disabled"; - }; - - usb_dwc3_1: usb@38200000 { - compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; - reg = <0x38200000 0x10000>; - clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>, - <&clk IMX8MQ_CLK_USB_CORE_REF>, - <&clk IMX8MQ_CLK_32K>; - clock-names = "bus_early", "ref", "suspend"; - assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, - <&clk IMX8MQ_CLK_USB_CORE_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, - <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <500000000>, <100000000>; - interrupts = ; - phys = <&usb3_phy1>, <&usb3_phy1>; - phy-names = "usb2-phy", "usb3-phy"; - power-domains = <&pgc_otg2>; - usb3-resume-missing-cas; - status = "disabled"; - }; - - usb3_phy1: usb-phy@382f0040 { - compatible = "fsl,imx8mq-usb-phy"; - reg = <0x382f0040 0x40>; - clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; - clock-names = "phy"; - assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <100000000>; - #phy-cells = <0>; - status = "disabled"; - }; - - vpu: video-codec@38300000 { - compatible = "nxp,imx8mq-vpu"; - reg = <0x38300000 0x10000>, - <0x38310000 0x10000>, - <0x38320000 0x10000>; - reg-names = "g1", "g2", "ctrl"; - interrupts = , - ; - interrupt-names = "g1", "g2"; - clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, - <&clk IMX8MQ_CLK_VPU_G2_ROOT>, - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; - clock-names = "g1", "g2", "bus"; - assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, - <&clk IMX8MQ_CLK_VPU_G2>, - <&clk IMX8MQ_CLK_VPU_BUS>, - <&clk IMX8MQ_VPU_PLL_BYPASS>; - assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, - <&clk IMX8MQ_VPU_PLL_OUT>, - <&clk IMX8MQ_SYS1_PLL_800M>, - <&clk IMX8MQ_VPU_PLL>; - assigned-clock-rates = <600000000>, <600000000>, - <800000000>, <0>; - power-domains = <&pgc_vpu>; - }; - - pcie0: pcie@33800000 { - compatible = "fsl,imx8mq-pcie"; - reg = <0x33800000 0x400000>, - <0x1ff00000 0x80000>; - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ - 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ - num-lanes = <1>; - num-viewport = <4>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - fsl,max-link-speed = <2>; - power-domains = <&pgc_pcie>; - resets = <&src IMX8MQ_RESET_PCIEPHY>, - <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, - <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; - reset-names = "pciephy", "apps", "turnoff"; - assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>, - <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&clk IMX8MQ_CLK_PCIE1_AUX>; - assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, - <&clk IMX8MQ_SYS2_PLL_100M>, - <&clk IMX8MQ_SYS1_PLL_80M>; - assigned-clock-rates = <250000000>, <100000000>, - <10000000>; - status = "disabled"; - }; - - pcie1: pcie@33c00000 { - compatible = "fsl,imx8mq-pcie"; - reg = <0x33c00000 0x400000>, - <0x27f00000 0x80000>; - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */ - 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ - num-lanes = <1>; - num-viewport = <4>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - fsl,max-link-speed = <2>; - power-domains = <&pgc_pcie>; - resets = <&src IMX8MQ_RESET_PCIEPHY2>, - <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, - <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; - reset-names = "pciephy", "apps", "turnoff"; - assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, - <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&clk IMX8MQ_CLK_PCIE2_AUX>; - assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, - <&clk IMX8MQ_SYS2_PLL_100M>, - <&clk IMX8MQ_SYS1_PLL_80M>; - assigned-clock-rates = <250000000>, <100000000>, - <10000000>; - status = "disabled"; - }; - - gic: interrupt-controller@38800000 { - compatible = "arm,gic-v3"; - reg = <0x38800000 0x10000>, /* GIC Dist */ - <0x38880000 0xc0000>, /* GICR */ - <0x31000000 0x2000>, /* GICC */ - <0x31010000 0x2000>, /* GICV */ - <0x31020000 0x2000>; /* GICH */ - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - interrupt-parent = <&gic>; - }; - - ddrc: memory-controller@3d400000 { - compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc"; - reg = <0x3d400000 0x400000>; - clock-names = "core", "pll", "alt", "apb"; - clocks = <&clk IMX8MQ_CLK_DRAM_CORE>, - <&clk IMX8MQ_DRAM_PLL_OUT>, - <&clk IMX8MQ_CLK_DRAM_ALT>, - <&clk IMX8MQ_CLK_DRAM_APB>; - }; - - ddr-pmu@3d800000 { - compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu"; - reg = <0x3d800000 0x400000>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts deleted file mode 100644 index a3f8cf195..000000000 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts +++ /dev/null @@ -1,253 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018 Einfochips - * Copyright 2019 Linaro Ltd. - */ - -/dts-v1/; - -#include "imx8qxp.dtsi" - -/ { - model = "Einfochips i.MX8QXP AI_ML"; - compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp"; - - aliases { - serial1 = &adma_lpuart1; - serial2 = &adma_lpuart2; - serial3 = &adma_lpuart3; - }; - - chosen { - stdout-path = &adma_lpuart2; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - user-led1 { - label = "green:user1"; - gpios = <&lsio_gpio4 16 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - user-led2 { - label = "green:user2"; - gpios = <&lsio_gpio0 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - }; - - user-led3 { - label = "green:user3"; - gpios = <&lsio_gpio0 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - user-led4 { - label = "green:user4"; - gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; - panic-indicator; - linux,default-trigger = "none"; - }; - - wlan-active-led { - label = "yellow:wlan"; - gpios = <&lsio_gpio4 17 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - bt-active-led { - label = "blue:bt"; - gpios = <&lsio_gpio4 18 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "hci0-power"; - default-state = "off"; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_reg_on>; - reset-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_LOW>; - }; -}; - -/* BT */ -&adma_lpuart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart0>; - uart-has-rtscts; - status = "okay"; -}; - -/* LS-UART0 */ -&adma_lpuart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart1>; - status = "okay"; -}; - -/* Debug */ -&adma_lpuart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart2>; - status = "okay"; -}; - -/* PCI-E UART */ -&adma_lpuart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart3>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -/* WiFi */ -&usdhc1 { - #address-cells = <1>; - #size-cells = <0>; - assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <4>; - no-sd; - non-removable; - mmc-pwrseq = <&sdio_pwrseq>; - status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD */ -&usdhc2 { - assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 - IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 - IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 - IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 - IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 - IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 - IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 - IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 - IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 - IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 - IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 - IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 - IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 - IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 - >; - }; - - pinctrl_leds: ledsgrp{ - fsl,pins = < - IMX8QXP_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 0x00000021 - IMX8QXP_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 0x00000021 - IMX8QXP_EMMC0_DATA7_LSIO_GPIO4_IO16 0x00000021 - IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 - IMX8QXP_EMMC0_STROBE_LSIO_GPIO4_IO17 0x00000021 - IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18 0x00000021 - >; - }; - - pinctrl_lpuart0: lpuart0grp { - fsl,pins = < - IMX8QXP_UART0_RX_ADMA_UART0_RX 0X06000020 - IMX8QXP_UART0_TX_ADMA_UART0_TX 0X06000020 - IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 - IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 - >; - }; - - pinctrl_lpuart1: lpuart1grp { - fsl,pins = < - IMX8QXP_UART1_RX_ADMA_UART1_RX 0X06000020 - IMX8QXP_UART1_TX_ADMA_UART1_TX 0X06000020 - >; - }; - - pinctrl_lpuart2: lpuart2grp { - fsl,pins = < - IMX8QXP_UART2_RX_ADMA_UART2_RX 0X06000020 - IMX8QXP_UART2_TX_ADMA_UART2_TX 0X06000020 - >; - }; - - pinctrl_lpuart3: lpuart3grp { - fsl,pins = < - IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0X06000020 - IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0X06000020 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 - IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 - >; - }; - - pinctrl_wifi_reg_on: wifiregongrp { - fsl,pins = < - IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x00000021 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts deleted file mode 100644 index 6b21a295c..000000000 --- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2019 Toradex - */ - -/dts-v1/; - -#include "imx8qxp-colibri.dtsi" -#include "imx8qxp-colibri-eval-v3.dtsi" - -/ { - model = "Toradex Colibri iMX8QXP/DX on Colibri Evaluation Board V3"; - compatible = "toradex,colibri-imx8x-eval-v3", - "toradex,colibri-imx8x", "fsl,imx8qxp"; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi deleted file mode 100644 index c7336f387..000000000 --- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2019 Toradex - */ - -#include "dt-bindings/input/linux-event-codes.h" - -/ { - aliases { - rtc0 = &rtc_i2c; - rtc1 = &rtc; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - - wakeup { - label = "Wake-Up"; - gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; -}; - -&adma_i2c1 { - status = "okay"; - - /* M41T0M6 real time clock on carrier board */ - rtc_i2c: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -/* Colibri UART_B */ -&adma_lpuart0 { - status= "okay"; -}; - -/* Colibri UART_C */ -&adma_lpuart2 { - status= "okay"; -}; - -/* Colibri UART_A */ -&adma_lpuart3 { - status= "okay"; -}; - -/* Colibri FastEthernet */ -&fec1 { - status = "okay"; -}; - -/* Colibri SD/MMC Card */ -&usdhc2 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi deleted file mode 100644 index f38acff0d..000000000 --- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi +++ /dev/null @@ -1,598 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2019 Toradex - */ - -#include "imx8qxp.dtsi" - -/ { - model = "Toradex Colibri iMX8QXP/DX Module"; - compatible = "toradex,colibri-imx8x", "fsl,imx8qxp"; - - chosen { - stdout-path = &adma_lpuart3; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -/* On-module I2C */ -&adma_i2c0 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>; - status = "okay"; - - /* Touch controller */ - touchscreen@2c { - compatible = "adi,ad7879-1"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ad7879_int>; - reg = <0x2c>; - interrupt-parent = <&lsio_gpio3>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - touchscreen-max-pressure = <4096>; - adi,resistance-plate-x = <120>; - adi,first-conversion-delay = /bits/ 8 <3>; - adi,acquisition-time = /bits/ 8 <1>; - adi,median-filter-size = /bits/ 8 <2>; - adi,averaging = /bits/ 8 <1>; - adi,conversion-interval = /bits/ 8 <255>; - }; -}; - -/* Colibri I2C */ -&adma_i2c1 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; -}; - -/* Colibri UART_B */ -&adma_lpuart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart0>; -}; - -/* Colibri UART_C */ -&adma_lpuart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart2>; -}; - -/* Colibri UART_A */ -&adma_lpuart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>; -}; - -/* Colibri FastEthernet */ -&fec1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_fec1>; - pinctrl-1 = <&pinctrl_fec1_sleep>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - fsl,magic-packet; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@2 { - compatible = "ethernet-phy-ieee802.3-c22"; - max-speed = <100>; - reg = <2>; - }; - }; -}; - -/* On-module eMMC */ -&usdhc1 { - bus-width = <8>; - non-removable; - no-sd; - no-sdio; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - status = "okay"; -}; - -/* Colibri SD/MMC Card */ -&usdhc2 { - bus-width = <4>; - cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_module_3v3>; - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; - disable-wp; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>; - - /* On-module touch pen-down interrupt */ - pinctrl_ad7879_int: ad7879intgrp { - fsl,pins = < - IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21 - >; - }; - - /* Colibri Analogue Inputs */ - pinctrl_adc0: adc0grp { - fsl,pins = < - IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60 /* SODIMM 8 */ - IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60 /* SODIMM 6 */ - IMX8QXP_ADC_IN4_ADMA_ADC_IN4 0x60 /* SODIMM 4 */ - IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60 /* SODIMM 2 */ - >; - }; - - pinctrl_can_int: canintgrp { - fsl,pins = < - IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 73 */ - >; - }; - - pinctrl_csi_ctl: csictlgrp { - fsl,pins = < - IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20 /* SODIMM 77 */ - IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20 /* SODIMM 89 */ - >; - }; - - pinctrl_ext_io0: extio0grp { - fsl,pins = < - IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040 /* SODIMM 135 */ - >; - }; - - /* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */ - pinctrl_fec1: fec1grp { - fsl,pins = < - IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 - IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 - IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61 - IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061 - IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61 - IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61 - IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61 - IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61 - IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61 - IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61 - >; - }; - - pinctrl_fec1_sleep: fec1slpgrp { - fsl,pins = < - IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041 - IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041 - IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41 - IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41 - IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41 - IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41 - IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41 - IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41 - IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41 - IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41 - >; - }; - - /* Colibri optional CAN on UART_B RTS/CTS */ - pinctrl_flexcan1: flexcan0grp { - fsl,pins = < - IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 /* SODIMM 32 */ - IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 /* SODIMM 34 */ - >; - }; - - /* Colibri optional CAN on PS2 */ - pinctrl_flexcan2: flexcan1grp { - fsl,pins = < - IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* SODIMM 55 */ - IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 /* SODIMM 63 */ - >; - }; - - /* Colibri optional CAN on UART_A TXD/RXD */ - pinctrl_flexcan3: flexcan2grp { - fsl,pins = < - IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 /* SODIMM 35 */ - IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 /* SODIMM 33 */ - >; - }; - - /* Colibri LCD Back-Light GPIO */ - pinctrl_gpio_bl_on: gpioblongrp { - fsl,pins = < - IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60 /* SODIMM 71 */ - >; - }; - - pinctrl_gpiokeys: gpiokeysgrp { - fsl,pins = < - IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041 /* SODIMM 45 */ - >; - }; - - pinctrl_hog0: hog0grp { - fsl,pins = < - IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* SODIMM 65 */ - IMX8QXP_CSI_D07_CI_PI_D09 0x61 /* SODIMM 65 */ - IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20 /* SODIMM 69 */ - IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20 /* SODIMM 79 */ - IMX8QXP_CSI_D02_CI_PI_D04 0x61 /* SODIMM 79 */ - IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* SODIMM 85 */ - IMX8QXP_CSI_D06_CI_PI_D08 0x61 /* SODIMM 85 */ - IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20 /* SODIMM 95 */ - IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20 /* SODIMM 97 */ - IMX8QXP_CSI_D03_CI_PI_D05 0x61 /* SODIMM 97 */ - IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20 /* SODIMM 99 */ - IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20 /* SODIMM 101 */ - IMX8QXP_CSI_D00_CI_PI_D02 0x61 /* SODIMM 101 */ - IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20 /* SODIMM 103 */ - IMX8QXP_CSI_D01_CI_PI_D03 0x61 /* SODIMM 103 */ - IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20 /* SODIMM 105 */ - IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x20 /* SODIMM 107 */ - IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20 /* SODIMM 127 */ - IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20 /* SODIMM 131 */ - IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20 /* SODIMM 133 */ - IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20 /* SODIMM 96 */ - IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20 /* SODIMM 98 */ - IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20 /* SODIMM 100 */ - IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20 /* SODIMM 102 */ - IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20 /* SODIMM 104 */ - IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x20 /* SODIMM 106 */ - >; - }; - - pinctrl_hog1: hog1grp { - fsl,pins = < - IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20 /* SODIMM 75 */ - IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20 /* SODIMM 93 */ - >; - }; - - /* - * This pin is used in the SCFW as a UART. Using it from - * Linux would require rewritting the SCFW board file. - */ - pinctrl_hog_scfw: hogscfwgrp { - fsl,pins = < - IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20 /* SODIMM 144 */ - >; - }; - - /* On Module I2C */ - pinctrl_i2c0: i2c0grp { - fsl,pins = < - IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021 - IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021 - >; - }; - - /* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */ - pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp { - fsl,pins = < - IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 /* SODIMM 140 */ - IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 /* SODIMM 142 */ - >; - }; - - /* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */ - pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp { - fsl,pins = < - IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 /* SODIMM 186 */ - IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 /* SODIMM 188 */ - >; - }; - - /* Colibri I2C */ - pinctrl_i2c1: i2c1grp { - fsl,pins = < - IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 /* SODIMM 196 */ - IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 /* SODIMM 194 */ - >; - }; - - /* Colibri Parallel RGB LCD Interface */ - pinctrl_lcdif: lcdifgrp { - fsl,pins = < - IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* SODIMM 56 */ - IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* SODIMM 68 */ - IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* SODIMM 82 */ - IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x60 /* SODIMM 44 */ - IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x60 /* SODIMM 44 */ - IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60 /* SODIMM 76 */ - IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60 /* SODIMM 76 */ - IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60 /* SODIMM 70 */ - IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60 /* SODIMM 60 */ - IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60 /* SODIMM 58 */ - IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x60 /* SODIMM 78 */ - IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x60 /* SODIMM 72 */ - IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60 /* SODIMM 80 */ - IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60 /* SODIMM 46 */ - IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60 /* SODIMM 62 */ - IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60 /* SODIMM 48 */ - IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60 /* SODIMM 74 */ - IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60 /* SODIMM 50 */ - IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* SODIMM 52 */ - IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60 /* SODIMM 54 */ - IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* SODIMM 66 */ - IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60 /* SODIMM 64 */ - IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* SODIMM 57 */ - IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60 /* SODIMM 57 */ - IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* SODIMM 61 */ - >; - }; - - /* Colibri SPI */ - pinctrl_lpspi2: lpspi2grp { - fsl,pins = < - IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21 /* SODIMM 86 */ - IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* SODIMM 92 */ - IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* SODIMM 90 */ - IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 /* SODIMM 88 */ - >; - }; - - /* Colibri UART_B */ - pinctrl_lpuart0: lpuart0grp { - fsl,pins = < - IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 /* SODIMM 36 */ - IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 /* SODIMM 38 */ - IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 /* SODIMM 34 */ - IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 /* SODIMM 32 */ - >; - }; - - /* Colibri UART_C */ - pinctrl_lpuart2: lpuart2grp { - fsl,pins = < - IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 /* SODIMM 19 */ - IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 /* SODIMM 21 */ - >; - }; - - /* Colibri UART_A */ - pinctrl_lpuart3: lpuart3grp { - fsl,pins = < - IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 /* SODIMM 33 */ - IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 /* SODIMM 35 */ - >; - }; - - /* Colibri UART_A Control */ - pinctrl_lpuart3_ctrl: lpuart3ctrlgrp { - fsl,pins = < - IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20 /* SODIMM 23 */ - IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x20 /* SODIMM 25 */ - IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x20 /* SODIMM 27 */ - IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x20 /* SODIMM 29 */ - IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20 /* SODIMM 31 */ - IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20 /* SODIMM 37 */ - >; - }; - - /* On module wifi module */ - pinctrl_pcieb: pciebgrp { - fsl,pins = < - IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061 /* SODIMM 178 */ - IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061 /* SODIMM 94 */ - IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60 /* SODIMM 81 */ - >; - }; - - /* Colibri PWM_A */ - pinctrl_pwm_a: pwmagrp { - /* both pins are connected together, reserve the unused CSI_D05 */ - fsl,pins = < - IMX8QXP_CSI_D05_CI_PI_D07 0x61 /* SODIMM 59 */ - IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60 /* SODIMM 59 */ - >; - }; - - /* Colibri PWM_B */ - pinctrl_pwm_b: pwmbgrp { - fsl,pins = < - IMX8QXP_UART1_TX_LSIO_PWM0_OUT 0x60 /* SODIMM 28 */ - >; - }; - - /* Colibri PWM_C */ - pinctrl_pwm_c: pwmcgrp { - fsl,pins = < - IMX8QXP_UART1_RX_LSIO_PWM1_OUT 0x60 /* SODIMM 30 */ - >; - }; - - /* Colibri PWM_D */ - pinctrl_pwm_d: pwmdgrp { - /* both pins are connected together, reserve the unused CSI_D04 */ - fsl,pins = < - IMX8QXP_CSI_D04_CI_PI_D06 0x61 /* SODIMM 67 */ - IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* SODIMM 67 */ - >; - }; - - /* On-module I2S */ - pinctrl_sai0: sai0grp { - fsl,pins = < - IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD 0x06000040 - IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD 0x06000040 - IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC 0x06000040 - IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040 - >; - }; - - /* Colibri Audio Analogue Microphone GND */ - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - /* MIC GND EN */ - IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41 - >; - }; - - /* On-module SGTL5000 clock */ - pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp { - fsl,pins = < - IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21 - >; - }; - - /* On-module USB interrupt */ - pinctrl_usb3503a: usb3503agrp { - fsl,pins = < - IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61 - >; - }; - - /* Colibri USB Client Cable Detect */ - pinctrl_usbc_det: usbcdetgrp { - fsl,pins = < - IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040 /* SODIMM 137 */ - >; - }; - - /* USB Host Power Enable */ - pinctrl_usbh1_reg: usbh1reggrp { - fsl,pins = < - IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040 /* SODIMM 129 */ - >; - }; - - /* On-module eMMC */ - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - /* Colibri SD/MMC Card Detect */ - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021 /* SODIMM 43 */ - >; - }; - - pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp { - fsl,pins = < - IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x60 /* SODIMM 43 */ - >; - }; - - /* Colibri SD/MMC Card */ - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_sleep: usdhc2slpgrp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 47 */ - IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 190 */ - IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 192 */ - IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 49 */ - IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 51 */ - IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 53 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_wifi: wifigrp { - fsl,pins = < - IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts deleted file mode 100644 index 46437d3c7..000000000 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ /dev/null @@ -1,272 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2017~2018 NXP - */ - -/dts-v1/; - -#include "imx8qxp.dtsi" - -/ { - model = "Freescale i.MX8QXP MEK"; - compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; - - chosen { - stdout-path = &adma_lpuart0; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x40000000>; - }; - - reg_usdhc2_vmmc: usdhc2-vmmc { - compatible = "regulator-fixed"; - regulator-name = "SD1_SPWR"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&adma_dsp { - status = "okay"; -}; - -&adma_i2c1 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; - status = "okay"; - - i2c-switch@71 { - compatible = "nxp,pca9646", "nxp,pca9546"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - max7322: gpio@68 { - compatible = "maxim,max7322"; - reg = <0x68>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - pressure-sensor@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - pca9557_a: gpio@1a { - compatible = "nxp,pca9557"; - reg = <0x1a>; - gpio-controller; - #gpio-cells = <2>; - }; - - pca9557_b: gpio@1d { - compatible = "nxp,pca9557"; - reg = <0x1d>; - gpio-controller; - #gpio-cells = <2>; - }; - - light-sensor@44 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_isl29023>; - compatible = "isil,isl29023"; - reg = <0x44>; - interrupt-parent = <&lsio_gpio1>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - }; - }; - }; -}; - -&adma_lpuart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart0>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - -&scu_key { - status = "okay"; -}; - -&thermal_zones { - pmic-thermal0 { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; - - trips { - pmic_alert0: trip0 { - temperature = <110000>; - hysteresis = <2000>; - type = "passive"; - }; - - pmic_crit0: trip1 { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&pmic_alert0>; - cooling-device = - <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <8>; - no-sd; - no-sdio; - non-removable; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; - wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 - IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 - IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 - IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 - IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 - IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 - IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 - IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 - IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 - IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 - IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 - IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 - IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 - IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 - >; - }; - - pinctrl_ioexp_rst: ioexprstgrp { - fsl,pins = < - IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 - >; - }; - - pinctrl_isl29023: isl29023grp { - fsl,pins = < - IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 - >; - }; - - pinctrl_lpi2c1: lpi2c1grp { - fsl,pins = < - IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 - IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 - >; - }; - - pinctrl_lpuart0: lpuart0grp { - fsl,pins = < - IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 - IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 - >; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi deleted file mode 100644 index e46faac1f..000000000 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ /dev/null @@ -1,632 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP - * Dong Aisheng - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet0 = &fec1; - ethernet1 = &fec2; - gpio0 = &lsio_gpio0; - gpio1 = &lsio_gpio1; - gpio2 = &lsio_gpio2; - gpio3 = &lsio_gpio3; - gpio4 = &lsio_gpio4; - gpio5 = &lsio_gpio5; - gpio6 = &lsio_gpio6; - gpio7 = &lsio_gpio7; - i2c0 = &adma_i2c0; - i2c1 = &adma_i2c1; - i2c2 = &adma_i2c2; - i2c3 = &adma_i2c3; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - mu0 = &lsio_mu0; - mu1 = &lsio_mu1; - mu2 = &lsio_mu2; - mu3 = &lsio_mu3; - mu4 = &lsio_mu4; - serial0 = &adma_lpuart0; - serial1 = &adma_lpuart1; - serial2 = &adma_lpuart2; - serial3 = &adma_lpuart3; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - /* We have 1 clusters with 4 Cortex-A35 cores */ - A35_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&A35_L2>; - clocks = <&clk IMX_A35_CLK>; - operating-points-v2 = <&a35_opp_table>; - #cooling-cells = <2>; - }; - - A35_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&A35_L2>; - clocks = <&clk IMX_A35_CLK>; - operating-points-v2 = <&a35_opp_table>; - #cooling-cells = <2>; - }; - - A35_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&A35_L2>; - clocks = <&clk IMX_A35_CLK>; - operating-points-v2 = <&a35_opp_table>; - #cooling-cells = <2>; - }; - - A35_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&A35_L2>; - clocks = <&clk IMX_A35_CLK>; - operating-points-v2 = <&a35_opp_table>; - #cooling-cells = <2>; - }; - - A35_L2: l2-cache0 { - compatible = "cache"; - }; - }; - - a35_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <150000>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <150000>; - opp-suspend; - }; - }; - - gic: interrupt-controller@51a00000 { - compatible = "arm,gic-v3"; - reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ - <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dsp_reserved: dsp@92400000 { - reg = <0 0x92400000 0 0x2000000>; - no-map; - }; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - scu { - compatible = "fsl,imx-scu"; - mbox-names = "tx0", - "rx0", - "gip3"; - mboxes = <&lsio_mu1 0 0 - &lsio_mu1 1 0 - &lsio_mu1 3 3>; - - clk: clock-controller { - compatible = "fsl,imx8qxp-clk"; - #clock-cells = <1>; - clocks = <&xtal32k &xtal24m>; - clock-names = "xtal_32KHz", "xtal_24Mhz"; - }; - - iomuxc: pinctrl { - compatible = "fsl,imx8qxp-iomuxc"; - }; - - ocotp: imx8qx-ocotp { - compatible = "fsl,imx8qxp-scu-ocotp"; - #address-cells = <1>; - #size-cells = <1>; - }; - - pd: imx8qx-pd { - compatible = "fsl,imx8qxp-scu-pd"; - #power-domain-cells = <1>; - }; - - scu_key: scu-key { - compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; - linux,keycodes = ; - status = "disabled"; - }; - - rtc: rtc { - compatible = "fsl,imx8qxp-sc-rtc"; - }; - - watchdog { - compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; - timeout-sec = <60>; - }; - - tsens: thermal-sensor { - compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; - #thermal-sensor-cells = <1>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , /* Physical Secure */ - , /* Physical Non-Secure */ - , /* Virtual */ - ; /* Hypervisor */ - }; - - xtal32k: clock-xtal32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xtal_32KHz"; - }; - - xtal24m: clock-xtal24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "xtal_24MHz"; - }; - - adma_subsys: bus@59000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x59000000 0x0 0x59000000 0x2000000>; - - adma_lpcg: clock-controller@59000000 { - compatible = "fsl,imx8qxp-lpcg-adma"; - reg = <0x59000000 0x2000000>; - #clock-cells = <1>; - }; - - adma_dsp: dsp@596e8000 { - compatible = "fsl,imx8qxp-dsp"; - reg = <0x596e8000 0x88000>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>; - clock-names = "ipg", "ocram", "core"; - power-domains = <&pd IMX_SC_R_MU_13A>, - <&pd IMX_SC_R_MU_13B>, - <&pd IMX_SC_R_DSP>, - <&pd IMX_SC_R_DSP_RAM>; - mbox-names = "txdb0", "txdb1", - "rxdb0", "rxdb1"; - mboxes = <&lsio_mu13 2 0>, - <&lsio_mu13 2 1>, - <&lsio_mu13 3 0>, - <&lsio_mu13 3 1>; - memory-region = <&dsp_reserved>; - status = "disabled"; - }; - - adma_lpuart0: serial@5a060000 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x5a060000 0x1000>; - interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; - clock-names = "ipg", "baud"; - power-domains = <&pd IMX_SC_R_UART_0>; - status = "disabled"; - }; - - adma_lpuart1: serial@5a070000 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x5a070000 0x1000>; - interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; - clock-names = "ipg", "baud"; - power-domains = <&pd IMX_SC_R_UART_1>; - status = "disabled"; - }; - - adma_lpuart2: serial@5a080000 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x5a080000 0x1000>; - interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; - clock-names = "ipg", "baud"; - power-domains = <&pd IMX_SC_R_UART_2>; - status = "disabled"; - }; - - adma_lpuart3: serial@5a090000 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x5a090000 0x1000>; - interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>, - <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; - clock-names = "ipg", "baud"; - power-domains = <&pd IMX_SC_R_UART_3>; - status = "disabled"; - }; - - adma_i2c0: i2c@5a800000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x5a800000 0x4000>; - interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; - clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_0>; - status = "disabled"; - }; - - adma_i2c1: i2c@5a810000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x5a810000 0x4000>; - interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; - clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_1>; - status = "disabled"; - }; - - adma_i2c2: i2c@5a820000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x5a820000 0x4000>; - interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; - clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_2>; - status = "disabled"; - }; - - adma_i2c3: i2c@5a830000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x5a830000 0x4000>; - interrupts = ; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; - clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_3>; - status = "disabled"; - }; - }; - - conn_subsys: bus@5b000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; - - conn_lpcg: clock-controller@5b200000 { - compatible = "fsl,imx8qxp-lpcg-conn"; - reg = <0x5b200000 0xb0000>; - #clock-cells = <1>; - }; - - usdhc1: mmc@5b010000 { - compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; - interrupts = ; - reg = <0x5b010000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; - clock-names = "ipg", "per", "ahb"; - power-domains = <&pd IMX_SC_R_SDHC_0>; - status = "disabled"; - }; - - usdhc2: mmc@5b020000 { - compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; - interrupts = ; - reg = <0x5b020000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; - clock-names = "ipg", "per", "ahb"; - power-domains = <&pd IMX_SC_R_SDHC_1>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - status = "disabled"; - }; - - usdhc3: mmc@5b030000 { - compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; - interrupts = ; - reg = <0x5b030000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; - clock-names = "ipg", "per", "ahb"; - power-domains = <&pd IMX_SC_R_SDHC_2>; - status = "disabled"; - }; - - fec1: ethernet@5b040000 { - compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; - reg = <0x5b040000 0x10000>; - interrupts = , - , - , - ; - clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; - power-domains = <&pd IMX_SC_R_ENET_0>; - status = "disabled"; - }; - - fec2: ethernet@5b050000 { - compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; - reg = <0x5b050000 0x10000>; - interrupts = , - , - , - ; - clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; - power-domains = <&pd IMX_SC_R_ENET_1>; - status = "disabled"; - }; - }; - - ddr_subsyss: bus@5c000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; - - ddr-pmu@5c020000 { - compatible = "fsl,imx8-ddr-pmu"; - reg = <0x5c020000 0x10000>; - interrupts = ; - }; - }; - - lsio_subsys: bus@5d000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; - - lsio_gpio0: gpio@5d080000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d080000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_0>; - }; - - lsio_gpio1: gpio@5d090000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d090000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_1>; - }; - - lsio_gpio2: gpio@5d0a0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0a0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_2>; - }; - - lsio_gpio3: gpio@5d0b0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0b0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_3>; - }; - - lsio_gpio4: gpio@5d0c0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0c0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_4>; - }; - - lsio_gpio5: gpio@5d0d0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0d0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_5>; - }; - - lsio_gpio6: gpio@5d0e0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0e0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_6>; - }; - - lsio_gpio7: gpio@5d0f0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0f0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_7>; - }; - - lsio_mu0: mailbox@5d1b0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1b0000 0x10000>; - interrupts = ; - #mbox-cells = <2>; - status = "disabled"; - }; - - lsio_mu1: mailbox@5d1c0000 { - compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1c0000 0x10000>; - interrupts = ; - #mbox-cells = <2>; - }; - - lsio_mu2: mailbox@5d1d0000 { - compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1d0000 0x10000>; - interrupts = ; - #mbox-cells = <2>; - status = "disabled"; - }; - - lsio_mu3: mailbox@5d1e0000 { - compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1e0000 0x10000>; - interrupts = ; - #mbox-cells = <2>; - status = "disabled"; - }; - - lsio_mu4: mailbox@5d1f0000 { - compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1f0000 0x10000>; - interrupts = ; - #mbox-cells = <2>; - status = "disabled"; - }; - - lsio_mu13: mailbox@5d280000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d280000 0x10000>; - interrupts = ; - #mbox-cells = <2>; - power-domains = <&pd IMX_SC_R_MU_13A>; - }; - - lsio_lpcg: clock-controller@5d400000 { - compatible = "fsl,imx8qxp-lpcg-lsio"; - reg = <0x5d400000 0x400000>; - #clock-cells = <1>; - }; - }; - - thermal_zones: thermal-zones { - cpu-thermal0 { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; - - trips { - cpu_alert0: trip0 { - temperature = <107000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit0: trip1 { - temperature = <127000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi b/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi deleted file mode 100644 index ff1aba5fa..000000000 --- a/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ BMan Portals device tree - * - * Copyright 2011-2016 Freescale Semiconductor Inc. - * - */ - -&bportals { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - - bman-portal@0 { - /* - * bootloader fix-ups are expected to provide the - * "fsl,bman-portal-" compatible - */ - compatible = "fsl,bman-portal"; - reg = <0x0 0x4000>, <0x4000000 0x4000>; - interrupts = ; - }; - - bman-portal@10000 { - compatible = "fsl,bman-portal"; - reg = <0x10000 0x4000>, <0x4010000 0x4000>; - interrupts = ; - }; - - bman-portal@20000 { - compatible = "fsl,bman-portal"; - reg = <0x20000 0x4000>, <0x4020000 0x4000>; - interrupts = ; - }; - - bman-portal@30000 { - compatible = "fsl,bman-portal"; - reg = <0x30000 0x4000>, <0x4030000 0x4000>; - interrupts = ; - }; - - bman-portal@40000 { - compatible = "fsl,bman-portal"; - reg = <0x40000 0x4000>, <0x4040000 0x4000>; - interrupts = ; - }; - - bman-portal@50000 { - compatible = "fsl,bman-portal"; - reg = <0x50000 0x4000>, <0x4050000 0x4000>; - interrupts = ; - }; - - bman-portal@60000 { - compatible = "fsl,bman-portal"; - reg = <0x60000 0x4000>, <0x4060000 0x4000>; - interrupts = ; - }; - - bman-portal@70000 { - compatible = "fsl,bman-portal"; - reg = <0x70000 0x4000>, <0x4070000 0x4000>; - interrupts = ; - }; - - bman-portal@80000 { - compatible = "fsl,bman-portal"; - reg = <0x80000 0x4000>, <0x4080000 0x4000>; - interrupts = ; - }; - - bman-portal@90000 { - compatible = "fsl,bman-portal"; - reg = <0x90000 0x4000>, <0x4090000 0x4000>; - interrupts = ; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi deleted file mode 100644 index dbd2fc3ba..000000000 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ FMan v3 10g port #0 device tree - * - * Copyright 2012-2015 Freescale Semiconductor Inc. - * - */ - -fman@1a00000 { - fman0_rx_0x10: port@90000 { - cell-index = <0x10>; - compatible = "fsl,fman-v3-port-rx"; - reg = <0x90000 0x1000>; - fsl,fman-10g-port; - }; - - fman0_tx_0x30: port@b0000 { - cell-index = <0x30>; - compatible = "fsl,fman-v3-port-tx"; - reg = <0xb0000 0x1000>; - fsl,fman-10g-port; - }; - - ethernet@f0000 { - cell-index = <0x8>; - compatible = "fsl,fman-memac"; - reg = <0xf0000 0x1000>; - fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>; - pcsphy-handle = <&pcsphy6>; - }; - - mdio@f1000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; - reg = <0xf1000 0x1000>; - - pcsphy6: ethernet-phy@0 { - reg = <0x0>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi deleted file mode 100644 index 6fc5d2560..000000000 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ FMan v3 10g port #1 device tree - * - * Copyright 2012-2015 Freescale Semiconductor Inc. - * - */ - -fman@1a00000 { - fman0_rx_0x11: port@91000 { - cell-index = <0x11>; - compatible = "fsl,fman-v3-port-rx"; - reg = <0x91000 0x1000>; - fsl,fman-10g-port; - }; - - fman0_tx_0x31: port@b1000 { - cell-index = <0x31>; - compatible = "fsl,fman-v3-port-tx"; - reg = <0xb1000 0x1000>; - fsl,fman-10g-port; - }; - - ethernet@f2000 { - cell-index = <0x9>; - compatible = "fsl,fman-memac"; - reg = <0xf2000 0x1000>; - fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>; - pcsphy-handle = <&pcsphy7>; - }; - - mdio@f3000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; - reg = <0xf3000 0x1000>; - - pcsphy7: ethernet-phy@0 { - reg = <0x0>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi deleted file mode 100644 index 4e02276fc..000000000 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ FMan v3 1g port #0 device tree - * - * Copyright 2012-2015 Freescale Semiconductor Inc. - * - */ - -fman@1a00000 { - fman0_rx_0x08: port@88000 { - cell-index = <0x8>; - compatible = "fsl,fman-v3-port-rx"; - reg = <0x88000 0x1000>; - }; - - fman0_tx_0x28: port@a8000 { - cell-index = <0x28>; - compatible = "fsl,fman-v3-port-tx"; - reg = <0xa8000 0x1000>; - }; - - ethernet@e0000 { - cell-index = <0>; - compatible = "fsl,fman-memac"; - reg = <0xe0000 0x1000>; - fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>; - ptp-timer = <&ptp_timer0>; - pcsphy-handle = <&pcsphy0>; - }; - - mdio@e1000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; - reg = <0xe1000 0x1000>; - - pcsphy0: ethernet-phy@0 { - reg = <0x0>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi deleted file mode 100644 index 0312fa43f..000000000 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ FMan v3 1g port #1 device tree - * - * Copyright 2012-2015 Freescale Semiconductor Inc. - * - */ - -fman@1a00000 { - fman0_rx_0x09: port@89000 { - cell-index = <0x9>; - compatible = "fsl,fman-v3-port-rx"; - reg = <0x89000 0x1000>; - }; - - fman0_tx_0x29: port@a9000 { - cell-index = <0x29>; - compatible = "fsl,fman-v3-port-tx"; - reg = <0xa9000 0x1000>; - }; - - ethernet@e2000 { - cell-index = <1>; - compatible = "fsl,fman-memac"; - reg = <0xe2000 0x1000>; - fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>; - ptp-timer = <&ptp_timer0>; - pcsphy-handle = <&pcsphy1>; - }; - - mdio@e3000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; - reg = <0xe3000 0x1000>; - - pcsphy1: ethernet-phy@0 { - reg = <0x0>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi deleted file mode 100644 index af2df0797..000000000 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ FMan v3 1g port #2 device tree - * - * Copyright 2012-2015 Freescale Semiconductor Inc. - * - */ - -fman@1a00000 { - fman0_rx_0x0a: port@8a000 { - cell-index = <0xa>; - compatible = "fsl,fman-v3-port-rx"; - reg = <0x8a000 0x1000>; - }; - - fman0_tx_0x2a: port@aa000 { - cell-index = <0x2a>; - compatible = "fsl,fman-v3-port-tx"; - reg = <0xaa000 0x1000>; - }; - - ethernet@e4000 { - cell-index = <2>; - compatible = "fsl,fman-memac"; - reg = <0xe4000 0x1000>; - fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>; - ptp-timer = <&ptp_timer0>; - pcsphy-handle = <&pcsphy2>; - }; - - mdio@e5000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; - reg = <0xe5000 0x1000>; - - pcsphy2: ethernet-phy@0 { - reg = <0x0>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi deleted file mode 100644 index 4ac98dc8b..000000000 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ FMan v3 1g port #3 device tree - * - * Copyright 2012-2015 Freescale Semiconductor Inc. - * - */ - -fman@1a00000 { - fman0_rx_0x0b: port@8b000 { - cell-index = <0xb>; - compatible = "fsl,fman-v3-port-rx"; - reg = <0x8b000 0x1000>; - }; - - fman0_tx_0x2b: port@ab000 { - cell-index = <0x2b>; - compatible = "fsl,fman-v3-port-tx"; - reg = <0xab000 0x1000>; - }; - - ethernet@e6000 { - cell-index = <3>; - compatible = "fsl,fman-memac"; - reg = <0xe6000 0x1000>; - fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>; - ptp-timer = <&ptp_timer0>; - pcsphy-handle = <&pcsphy3>; - }; - - mdio@e7000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; - reg = <0xe7000 0x1000>; - - pcsphy3: ethernet-phy@0 { - reg = <0x0>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi deleted file mode 100644 index bd932d8b0..000000000 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ FMan v3 1g port #4 device tree - * - * Copyright 2012-2015 Freescale Semiconductor Inc. - * - */ - -fman@1a00000 { - fman0_rx_0x0c: port@8c000 { - cell-index = <0xc>; - compatible = "fsl,fman-v3-port-rx"; - reg = <0x8c000 0x1000>; - }; - - fman0_tx_0x2c: port@ac000 { - cell-index = <0x2c>; - compatible = "fsl,fman-v3-port-tx"; - reg = <0xac000 0x1000>; - }; - - ethernet@e8000 { - cell-index = <4>; - compatible = "fsl,fman-memac"; - reg = <0xe8000 0x1000>; - fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>; - ptp-timer = <&ptp_timer0>; - pcsphy-handle = <&pcsphy4>; - }; - - mdio@e9000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; - reg = <0xe9000 0x1000>; - - pcsphy4: ethernet-phy@0 { - reg = <0x0>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi deleted file mode 100644 index 7de1c5203..000000000 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ FMan v3 1g port #5 device tree - * - * Copyright 2012-2015 Freescale Semiconductor Inc. - * - */ - -fman@1a00000 { - fman0_rx_0x0d: port@8d000 { - cell-index = <0xd>; - compatible = "fsl,fman-v3-port-rx"; - reg = <0x8d000 0x1000>; - }; - - fman0_tx_0x2d: port@ad000 { - cell-index = <0x2d>; - compatible = "fsl,fman-v3-port-tx"; - reg = <0xad000 0x1000>; - }; - - ethernet@ea000 { - cell-index = <5>; - compatible = "fsl,fman-memac"; - reg = <0xea000 0x1000>; - fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>; - ptp-timer = <&ptp_timer0>; - pcsphy-handle = <&pcsphy5>; - }; - - mdio@eb000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; - reg = <0xeb000 0x1000>; - - pcsphy5: ethernet-phy@0 { - reg = <0x0>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi deleted file mode 100644 index 4338db14c..000000000 --- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ FMan v3 device tree - * - * Copyright 2012-2015 Freescale Semiconductor Inc. - * - */ - -fman0: fman@1a00000 { - #address-cells = <1>; - #size-cells = <1>; - cell-index = <0>; - compatible = "fsl,fman"; - ranges = <0x0 0x0 0x1a00000 0xfe000>; - reg = <0x0 0x1a00000 0x0 0xfe000>; - interrupts = , - ; - clocks = <&clockgen 3 0>; - clock-names = "fmanclk"; - fsl,qman-channel-range = <0x800 0x10>; - ptimer-handle = <&ptp_timer0>; - dma-coherent; - - muram@0 { - compatible = "fsl,fman-muram"; - reg = <0x0 0x60000>; - }; - - fman0_oh_0x2: port@82000 { - cell-index = <0x2>; - compatible = "fsl,fman-v3-port-oh"; - reg = <0x82000 0x1000>; - }; - - fman0_oh_0x3: port@83000 { - cell-index = <0x3>; - compatible = "fsl,fman-v3-port-oh"; - reg = <0x83000 0x1000>; - }; - - fman0_oh_0x4: port@84000 { - cell-index = <0x4>; - compatible = "fsl,fman-v3-port-oh"; - reg = <0x84000 0x1000>; - }; - - fman0_oh_0x5: port@85000 { - cell-index = <0x5>; - compatible = "fsl,fman-v3-port-oh"; - reg = <0x85000 0x1000>; - }; - - fman0_oh_0x6: port@86000 { - cell-index = <0x6>; - compatible = "fsl,fman-v3-port-oh"; - reg = <0x86000 0x1000>; - }; - - fman0_oh_0x7: port@87000 { - cell-index = <0x7>; - compatible = "fsl,fman-v3-port-oh"; - reg = <0x87000 0x1000>; - }; - - mdio0: mdio@fc000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; - reg = <0xfc000 0x1000>; - }; - - xmdio0: mdio@fd000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; - reg = <0xfd000 0x1000>; - }; -}; - -ptp_timer0: ptp-timer@1afe000 { - compatible = "fsl,fman-ptp-timer"; - reg = <0x0 0x1afe000 0x0 0x1000>; - interrupts = ; - clocks = <&clockgen 3 0>; - fsl,extts-fifo; -}; diff --git a/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi b/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi deleted file mode 100644 index e3bec08b1..000000000 --- a/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * QorIQ QMan Portals device tree - * - * Copyright 2011-2016 Freescale Semiconductor Inc. - * - */ - -&qportals { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - - qportal0: qman-portal@0 { - /* - * bootloader fix-ups are expected to provide the - * "fsl,bman-portal-" compatible - */ - compatible = "fsl,qman-portal"; - reg = <0x0 0x4000>, <0x4000000 0x4000>; - interrupts = ; - cell-index = <0>; - }; - - qportal1: qman-portal@10000 { - compatible = "fsl,qman-portal"; - reg = <0x10000 0x4000>, <0x4010000 0x4000>; - interrupts = ; - cell-index = <1>; - }; - - qportal2: qman-portal@20000 { - compatible = "fsl,qman-portal"; - reg = <0x20000 0x4000>, <0x4020000 0x4000>; - interrupts = ; - cell-index = <2>; - }; - - qportal3: qman-portal@30000 { - compatible = "fsl,qman-portal"; - reg = <0x30000 0x4000>, <0x4030000 0x4000>; - interrupts = ; - cell-index = <3>; - }; - - qportal4: qman-portal@40000 { - compatible = "fsl,qman-portal"; - reg = <0x40000 0x4000>, <0x4040000 0x4000>; - interrupts = ; - cell-index = <4>; - }; - - qportal5: qman-portal@50000 { - compatible = "fsl,qman-portal"; - reg = <0x50000 0x4000>, <0x4050000 0x4000>; - interrupts = ; - cell-index = <5>; - }; - - qportal6: qman-portal@60000 { - compatible = "fsl,qman-portal"; - reg = <0x60000 0x4000>, <0x4060000 0x4000>; - interrupts = ; - cell-index = <6>; - }; - - qportal7: qman-portal@70000 { - compatible = "fsl,qman-portal"; - reg = <0x70000 0x4000>, <0x4070000 0x4000>; - interrupts = ; - cell-index = <7>; - }; - - qportal8: qman-portal@80000 { - compatible = "fsl,qman-portal"; - reg = <0x80000 0x4000>, <0x4080000 0x4000>; - interrupts = ; - cell-index = <8>; - }; - - qportal9: qman-portal@90000 { - compatible = "fsl,qman-portal"; - reg = <0x90000 0x4000>, <0x4090000 0x4000>; - interrupts = ; - cell-index = <9>; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/s32v234-evb.dts b/arch/arm64/boot/dts/freescale/s32v234-evb.dts deleted file mode 100644 index 4b802518c..000000000 --- a/arch/arm64/boot/dts/freescale/s32v234-evb.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2015-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - */ - -/dts-v1/; -#include "s32v234.dtsi" - -/ { - model = "NXP S32V234-EVB2 Board"; - compatible = "fsl,s32v234-evb", "fsl,s32v234"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi deleted file mode 100644 index ba0b5305d..000000000 --- a/arch/arm64/boot/dts/freescale/s32v234.dtsi +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2015-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - */ - -#include - -/memreserve/ 0x80000000 0x00010000; - -/ { - compatible = "fsl,s32v234"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x80000000>; - next-level-cache = <&cluster0_l2_cache>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x80000000>; - next-level-cache = <&cluster0_l2_cache>; - }; - - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x80000000>; - next-level-cache = <&cluster1_l2_cache>; - }; - - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x80000000>; - next-level-cache = <&cluster1_l2_cache>; - }; - - cluster0_l2_cache: l2-cache0 { - compatible = "cache"; - }; - - cluster1_l2_cache: l2-cache1 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - /* clock-frequency might be modified by u-boot, depending on the - * chip version. - */ - clock-frequency = <10000000>; - }; - - gic: interrupt-controller@7d001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0x7d001000 0 0x1000>, - <0 0x7d002000 0 0x2000>, - <0 0x7d004000 0 0x2000>, - <0 0x7d006000 0 0x2000>; - interrupts = ; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - aips0: bus@40000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - reg = <0x0 0x40000000 0x0 0x7d000>; - ranges; - - uart0: serial@40053000 { - compatible = "fsl,s32v234-linflexuart"; - reg = <0x0 0x40053000 0x0 0x1000>; - interrupts = ; - status = "disabled"; - }; - }; - - aips1: bus@40080000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - reg = <0x0 0x40080000 0x0 0x70000>; - ranges; - - uart1: serial@400bc000 { - compatible = "fsl,s32v234-linflexuart"; - reg = <0x0 0x400bc000 0x0 0x1000>; - interrupts = ; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile deleted file mode 100644 index f4d68caeb..000000000 --- a/arch/arm64/boot/dts/hisilicon/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb -dtb-$(CONFIG_ARCH_HISI) += hi3670-hikey970.dtb -dtb-$(CONFIG_ARCH_HISI) += hi3798cv200-poplar.dtb -dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb -dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb -dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb -dtb-$(CONFIG_ARCH_HISI) += hip07-d05.dtb diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi deleted file mode 100644 index d607f2f66..000000000 --- a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi +++ /dev/null @@ -1,456 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* - * dtsi for Hisilicon Hi3660 Coresight - * - * Copyright (C) 2016-2018 Hisilicon Ltd. - * - * Author: Wanglai Shi - * - */ -/ { - soc { - /* A53 cluster internals */ - etm@ecc40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xecc40000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - cpu = <&cpu0>; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = - <&cluster0_funnel_in0>; - }; - }; - }; - }; - - etm@ecd40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xecd40000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - cpu = <&cpu1>; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = - <&cluster0_funnel_in1>; - }; - }; - }; - }; - - etm@ece40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xece40000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - cpu = <&cpu2>; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = - <&cluster0_funnel_in2>; - }; - }; - }; - }; - - etm@ecf40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xecf40000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - cpu = <&cpu3>; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = - <&cluster0_funnel_in3>; - }; - }; - }; - }; - - funnel@ec801000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0xec801000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - - out-ports { - port { - cluster0_funnel_out: endpoint { - remote-endpoint = - <&cluster0_etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - cluster0_funnel_in0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - cluster0_funnel_in1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - - port@2 { - reg = <2>; - cluster0_funnel_in2: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - - port@3 { - reg = <3>; - cluster0_funnel_in3: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - }; - }; - - etf@ec802000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0xec802000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - - in-ports { - port { - cluster0_etf_in: endpoint { - remote-endpoint = - <&cluster0_funnel_out>; - }; - }; - }; - - out-ports { - port { - cluster0_etf_out: endpoint { - remote-endpoint = - <&combo_funnel_in0>; - }; - }; - }; - }; - - /* A73 cluster internals */ - etm@ed440000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xed440000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - cpu = <&cpu4>; - - out-ports { - port { - etm4_out: endpoint { - remote-endpoint = - <&cluster1_funnel_in0>; - }; - }; - }; - }; - - etm@ed540000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xed540000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - cpu = <&cpu5>; - - out-ports { - port { - etm5_out: endpoint { - remote-endpoint = - <&cluster1_funnel_in1>; - }; - }; - }; - }; - - etm@ed640000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xed640000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - cpu = <&cpu6>; - - out-ports { - port { - etm6_out: endpoint { - remote-endpoint = - <&cluster1_funnel_in2>; - }; - }; - }; - }; - - etm@ed740000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xed740000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - cpu = <&cpu7>; - - out-ports { - port { - etm7_out: endpoint { - remote-endpoint = - <&cluster1_funnel_in3>; - }; - }; - }; - }; - - funnel@ed001000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0xed001000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - out-ports { - port { - cluster1_funnel_out: endpoint { - remote-endpoint = - <&cluster1_etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - cluster1_funnel_in0: endpoint { - remote-endpoint = <&etm4_out>; - }; - }; - - port@1 { - reg = <1>; - cluster1_funnel_in1: endpoint { - remote-endpoint = <&etm5_out>; - }; - }; - - port@2 { - reg = <2>; - cluster1_funnel_in2: endpoint { - remote-endpoint = <&etm6_out>; - }; - }; - - port@3 { - reg = <3>; - cluster1_funnel_in3: endpoint { - remote-endpoint = <&etm7_out>; - }; - }; - }; - }; - - etf@ed002000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0xed002000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - - in-ports { - port { - cluster1_etf_in: endpoint { - remote-endpoint = - <&cluster1_funnel_out>; - }; - }; - }; - - out-ports { - port { - cluster1_etf_out: endpoint { - remote-endpoint = - <&combo_funnel_in1>; - }; - }; - }; - }; - - /* An invisible combo funnel between clusters and top funnel */ - funnel { - compatible = "arm,coresight-static-funnel"; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - - out-ports { - port { - combo_funnel_out: endpoint { - remote-endpoint = - <&top_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - combo_funnel_in0: endpoint { - remote-endpoint = - <&cluster0_etf_out>; - }; - }; - - port@1 { - reg = <1>; - combo_funnel_in1: endpoint { - remote-endpoint = - <&cluster1_etf_out>; - }; - }; - }; - }; - - /* Top internals */ - funnel@ec031000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0xec031000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - - out-ports { - port { - top_funnel_out: endpoint { - remote-endpoint = - <&top_etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - top_funnel_in: endpoint { - remote-endpoint = - <&combo_funnel_out>; - }; - }; - }; - }; - - etf@ec036000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0xec036000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - - in-ports { - port { - top_etf_in: endpoint { - remote-endpoint = - <&top_funnel_out>; - }; - }; - }; - - out-ports { - port { - top_etf_out: endpoint { - remote-endpoint = - <&replicator_in>; - }; - }; - }; - }; - - replicator { - compatible = "arm,coresight-static-replicator"; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = - <&top_etf_out>; - }; - }; - }; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator0_out0: endpoint { - remote-endpoint = <&etr_in>; - }; - }; - - port@1 { - reg = <1>; - replicator0_out1: endpoint { - remote-endpoint = <&tpiu_in>; - }; - }; - }; - }; - - etr@ec033000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0xec033000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = - <&replicator0_out0>; - }; - }; - }; - }; - - tpiu@ec032000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0 0xec032000 0 0x1000>; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - - in-ports { - port { - tpiu_in: endpoint { - remote-endpoint = - <&replicator0_out1>; - }; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts deleted file mode 100644 index 963300eed..000000000 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ /dev/null @@ -1,697 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for Hisilicon HiKey960 Development Board - * - * Copyright (C) 2016, Hisilicon Ltd. - * - */ - -/dts-v1/; - -#include "hi3660.dtsi" -#include "hikey960-pinctrl.dtsi" -#include -#include -#include -#include - -/ { - model = "HiKey960"; - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; - - aliases { - mshc1 = &dwmmc1; - mshc2 = &dwmmc2; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - serial6 = &uart6; - }; - - chosen { - stdout-path = "serial6:115200n8"; - }; - - memory@0 { - device_type = "memory"; - /* rewrite this at bootloader */ - reg = <0x0 0x0 0x0 0x0>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ramoops@32000000 { - compatible = "ramoops"; - reg = <0x0 0x32000000 0x0 0x00100000>; - record-size = <0x00020000>; - console-size = <0x00020000>; - ftrace-size = <0x00020000>; - }; - }; - - reboot-mode-syscon@32100000 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0x32100000 0x0 0x00001000>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x0>; - - mode-normal = <0x77665501>; - mode-bootloader = <0x77665500>; - mode-recovery = <0x77665502>; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key_pmx_func &pwr_key_cfg_func>; - - power { - wakeup-source; - gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - - user_led1 { - label = "green:user1"; - /* gpio_150_user_led1 */ - gpios = <&gpio18 6 0>; - linux,default-trigger = "heartbeat"; - }; - - user_led2 { - label = "green:user2"; - /* gpio_151_user_led2 */ - gpios = <&gpio18 7 0>; - linux,default-trigger = "none"; - }; - - user_led3 { - label = "green:user3"; - /* gpio_189_user_led3 */ - gpios = <&gpio23 5 0>; - linux,default-trigger = "mmc0"; - }; - - user_led4 { - label = "green:user4"; - /* gpio_190_user_led4 */ - gpios = <&gpio23 6 0>; - panic-indicator; - linux,default-trigger = "none"; - }; - - wlan_active_led { - label = "yellow:wlan"; - /* gpio_205_wifi_active */ - gpios = <&gpio25 5 0>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - bt_active_led { - label = "blue:bt"; - gpios = <&gpio25 7 0>; - /* gpio_207_user_led1 */ - linux,default-trigger = "hci0-power"; - default-state = "off"; - }; - }; - - pmic: pmic@fff34000 { - compatible = "hisilicon,hi6421v530-pmic"; - reg = <0x0 0xfff34000 0x0 0x1000>; - interrupt-controller; - #interrupt-cells = <2>; - - regulators { - ldo3: LDO3 { /* HDMI */ - regulator-name = "VOUT3_1V85"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2200000>; - regulator-enable-ramp-delay = <120>; - }; - - ldo9: LDO9 { /* SDCARD I/O */ - regulator-name = "VOUT9_1V8_2V95"; - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <240>; - }; - - ldo11: LDO11 { /* Low Speed Connector */ - regulator-name = "VOUT11_1V8_2V95"; - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <240>; - }; - - ldo15: LDO15 { /* UFS VCC */ - regulator-name = "VOUT15_3V0"; - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - regulator-enable-ramp-delay = <120>; - }; - - ldo16: LDO16 { /* SD VDD */ - regulator-name = "VOUT16_2V95"; - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <360>; - }; - }; - }; - - wlan_en: wlan-en-1-8v { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - /* GPIO_051_WIFI_EN */ - gpio = <&gpio6 3 0>; - - /* WLAN card specific delay */ - startup-delay-us = <70000>; - enable-active-high; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; -}; - -/* - * Legend: proper name = the GPIO line is used as GPIO - * NC = not connected (pin out but not routed from the chip to - * anything the board) - * "[PER]" = pin is muxed for [peripheral] (not GPIO) - * "" = no idea, schematic doesn't say, could be - * unrouted (not connected to any external pin) - * LSEC = Low Speed External Connector - * HSEC = High Speed External Connector - * - * Line names are taken from "HiKey 960 Board ver A" schematics - * from Huawei. The 40 pin low speed expansion connector is named - * J2002 63453-140LF. - * - * For the lines routed to the external connectors the - * lines are named after the 96Boards CE Specification 1.0, - * Appendix "Expansion Connector Signal Description". - * - * When the 96Board naming of a line and the schematic name of - * the same line are in conflict, the 96Board specification - * takes precedence, which means that the external UART on the - * LSEC is named UART0 while the schematic and SoC names this - * UART3. This is only for the informational lines i.e. "[FOO]", - * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only - * ones actually used for GPIO. - */ -&gpio0 { - /* GPIO_000-GPIO_007 */ - gpio-line-names = - "", - "TP901", /* TEST_MODE connected to TP901 */ - "[PMU0_SSI]", - "[PMU1_SSI]", - "[PMU2_SSI]", - "[PMU0_CLKOUT]", - "[JTAG_TCK]", - "[JTAG_TMS]"; -}; - -&gpio1 { - /* GPIO_008-GPIO_015 */ - gpio-line-names = - "[JTAG_TRST_N]", - "[JTAG_TDI]", - "[JTAG_TDO]", - "NC", "NC", - "[I2C3_SCL]", - "[I2C3_SDA]", - "NC"; -}; - -&gpio2 { - /* GPIO_016-GPIO_023 */ - gpio-line-names = - "NC", "NC", "NC", - "GPIO-J", /* LSEC pin 32: GPIO_019 */ - "GPIO_020_HDMI_SEL", - "GPIO-L", /* LSEC pin 34: GPIO_021 */ - "GPIO_022_UFSBUCK_INT_N", - "GPIO-G"; /* LSEC pin 29: LCD_TE0 */ -}; - -&gpio3 { - /* GPIO_024-GPIO_031 */ - /* The rail from pin BK36 is named LCD_TE0, we assume to be muxed as GPIO for GPIO-G */ - gpio-line-names = - "[CSI0_MCLK]", /* HSEC pin 15: ISP_CCLK0_MCAM */ - "[CSI1_MCLK]", /* HSEC pin 17: ISP_CCLK1_SCAM */ - "NC", - "[I2C2_SCL]", /* HSEC pin 32: ISP_SCL0 */ - "[I2C2_SDA]", /* HSEC pin 34: ISP_SDA0 */ - "[I2C3_SCL]", /* HSEC pin 36: ISP_SCL1 */ - "[I2C3_SDA]", /* HSEC pin 38: ISP_SDA1 */ - "NC"; -}; - -&gpio4 { - /* GPIO_032-GPIO_039 */ - gpio-line-names = - "NC", "NC", - "PWR_BTN_N", /* LSEC pin 4: GPIO_034_PWRON_DET */ - "GPIO_035_PMU2_EN", - "GPIO_036_USB_HUB_RESET", - "NC", "NC", "NC"; -}; - -&gpio5 { - /* GPIO_040-GPIO_047 */ - gpio-line-names = - "GPIO-H", /* LSEC pin 30: GPIO_040_LCD_RST_N */ - "GPIO_041_HDMI_PD", - "TP904", /* Test point */ - "TP905", /* Test point */ - "NC", "NC", - "GPIO_046_HUB_VDD33_EN", - "GPIO_047_PMU1_EN"; -}; - -&gpio6 { - /* GPIO_048-GPIO_055 */ - gpio-line-names = - "NC", "NC", "NC", - "GPIO_051_WIFI_EN", - "GPIO-I", /* LSEC pin 31: GPIO_052_CAM0_RST_N */ - /* - * These two pins should be used for SD(IO) data according to the - * 96boards specification but seems to be repurposed for a IRDA UART. - * They are however named according to the spec. - */ - "[SD_DAT1]", /* HSEC pin 3: UART0_IRDA_RXD */ - "[SD_DAT2]", /* HSEC pin 5: UART0_IRDA_TXD */ - "[UART1_RXD]"; /* LSEC pin 13: DEBUG_UART6_RXD */ -}; - -&gpio7 { - /* GPIO_056-GPIO_063 */ - gpio-line-names = - "[UART1_TXD]", /* LSEC pin 11: DEBUG_UART6_TXD */ - "[UART0_CTS]", /* LSEC pin 3: UART3_CTS_N */ - "[UART0_RTS]", /* LSEC pin 9: UART3_RTS_N */ - "[UART0_RXD]", /* LSEC pin 7: UART3_RXD */ - "[UART0_TXD]", /* LSEC pin 5: UART3_TXD */ - "[SOC_BT_UART4_CTS_N]", - "[SOC_BT_UART4_RTS_N]", - "[SOC_BT_UART4_RXD]"; -}; - -&gpio8 { - /* GPIO_064-GPIO_071 */ - gpio-line-names = - "[SOC_BT_UART4_TXD]", - "NC", - "[PMU_HKADC_SSI]", - "NC", - "GPIO_068_SEL", - "NC", "NC", "NC"; - -}; - -&gpio9 { - /* GPIO_072-GPIO_079 */ - gpio-line-names = - "NC", "NC", "NC", - "GPIO-K", /* LSEC pin 33: GPIO_075_CAM1_RST_N */ - "NC", "NC", "NC", "NC"; -}; - -&gpio10 { - /* GPIO_080-GPIO_087 */ - gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; -}; - -&gpio11 { - /* GPIO_088-GPIO_095 */ - gpio-line-names = - "NC", - "[PCIE_PERST_N]", - "NC", "NC", "NC", "NC", "NC", "NC"; -}; - -&gpio12 { - /* GPIO_096-GPIO_103 */ - gpio-line-names = "NC", "NC", "NC", "", "", "", "", "NC"; -}; - -&gpio13 { - /* GPIO_104-GPIO_111 */ - gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; -}; - -&gpio14 { - /* GPIO_112-GPIO_119 */ - gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; -}; - -&gpio15 { - /* GPIO_120-GPIO_127 */ - gpio-line-names = - "NC", "NC", "NC", "NC", "NC", "NC", - "GPIO_126_BT_EN", - "TP902"; /* GPIO_127_JTAG_SEL0 */ -}; - -&gpio16 { - /* GPIO_128-GPIO_135 */ - gpio-line-names = "", "", "", "", "", "", "", ""; -}; - -&gpio17 { - /* GPIO_136-GPIO_143 */ - gpio-line-names = "", "", "", "", "", "", "", ""; -}; - -&gpio18 { - /* GPIO_144-GPIO_151 */ - gpio-line-names = - "[UFS_REF_CLK]", - "[UFS_RST_N]", - "[SPI1_SCLK]", /* HSEC pin 9: GPIO_146_SPI3_CLK */ - "[SPI1_DIN]", /* HSEC pin 11: GPIO_147_SPI3_DI */ - "[SPI1_DOUT]", /* HSEC pin 1: GPIO_148_SPI3_DO */ - "[SPI1_CS]", /* HSEC pin 7: GPIO_149_SPI3_CS0_N */ - "GPIO_150_USER_LED1", - "GPIO_151_USER_LED2"; -}; - -&gpio19 { - /* GPIO_152-GPIO_159 */ - gpio-line-names = "NC", "NC", "NC", "NC", "", "", "", ""; -}; - -&gpio20 { - /* GPIO_160-GPIO_167 */ - gpio-line-names = - "[SD_CLK]", - "[SD_CMD]", - "[SD_DATA0]", - "[SD_DATA1]", - "[SD_DATA2]", - "[SD_DATA3]", - "", ""; -}; - -&gpio21 { - /* GPIO_168-GPIO_175 */ - gpio-line-names = - "[WL_SDIO_CLK]", - "[WL_SDIO_CMD]", - "[WL_SDIO_DATA0]", - "[WL_SDIO_DATA1]", - "[WL_SDIO_DATA2]", - "[WL_SDIO_DATA3]", - "", ""; -}; - -&gpio22 { - /* GPIO_176-GPIO_183 */ - gpio-line-names = - "[GPIO_176_PMU_PWR_HOLD]", - "NA", - "[SYSCLK_EN]", - "GPIO_179_WL_WAKEUP_AP", - "GPIO_180_HDMI_INT", - "NA", - "GPIO-F", /* LSEC pin 28: LCD_BL_PWM */ - "[I2C0_SCL]"; /* LSEC pin 15 */ -}; - -&gpio23 { - /* GPIO_184-GPIO_191 */ - gpio-line-names = - "[I2C0_SDA]", /* LSEC pin 17 */ - "[I2C1_SCL]", /* Actual SoC I2C1 */ - "[I2C1_SDA]", /* Actual SoC I2C1 */ - "[I2C1_SCL]", /* LSEC pin 19: I2C7_SCL */ - "[I2C1_SDA]", /* LSEC pin 21: I2C7_SDA */ - "GPIO_189_USER_LED3", - "GPIO_190_USER_LED4", - ""; -}; - -&gpio24 { - /* GPIO_192-GPIO_199 */ - gpio-line-names = - "[PCM_DI]", /* LSEC pin 22: GPIO_192_I2S0_DI */ - "[PCM_DO]", /* LSEC pin 20: GPIO_193_I2S0_DO */ - "[PCM_CLK]", /* LSEC pin 18: GPIO_194_I2S0_XCLK */ - "[PCM_FS]", /* LSEC pin 16: GPIO_195_I2S0_XFS */ - "[GPIO_196_I2S2_DI]", - "[GPIO_197_I2S2_DO]", - "[GPIO_198_I2S2_XCLK]", - "[GPIO_199_I2S2_XFS]"; -}; - -&gpio25 { - /* GPIO_200-GPIO_207 */ - gpio-line-names = - "NC", - "NC", - "GPIO_202_VBUS_TYPEC", - "GPIO_203_SD_DET", - "GPIO_204_PMU12_IRQ_N", - "GPIO_205_WIFI_ACTIVE", - "GPIO_206_USBSW_SEL", - "GPIO_207_BT_ACTIVE"; -}; - -&gpio26 { - /* GPIO_208-GPIO_215 */ - gpio-line-names = - "GPIO-A", /* LSEC pin 23: GPIO_208 */ - "GPIO-B", /* LSEC pin 24: GPIO_209 */ - "GPIO-C", /* LSEC pin 25: GPIO_210 */ - "GPIO-D", /* LSEC pin 26: GPIO_211 */ - "GPIO-E", /* LSEC pin 27: GPIO_212 */ - "[PCIE_CLKREQ_N]", - "[PCIE_WAKE_N]", - "[SPI0_CLK]"; /* LSEC pin 8: SPI2_CLK */ -}; - -&gpio27 { - /* GPIO_216-GPIO_223 */ - gpio-line-names = - "[SPI0_DIN]", /* LSEC pin 10: SPI2_DI */ - "[SPI0_DOUT]", /* LSEC pin 14: SPI2_DO */ - "[SPI0_CS]", /* LSEC pin 12: SPI2_CS0_N */ - "GPIO_219_CC_INT", - "NC", - "NC", - "[PMU_INT]", - ""; -}; - -&gpio28 { - /* GPIO_224-GPIO_231 */ - gpio-line-names = - "", "", "", "", "", "", "", ""; -}; - -&i2c0 { - /* On Low speed expansion */ - label = "LS-I2C0"; - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - rt1711h: rt1711h@4e { - compatible = "richtek,rt1711h"; - reg = <0x4e>; - status = "okay"; - interrupt-parent = <&gpio27>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_cfg_func>; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <10000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@1 { - reg = <1>; - usb_con_ss: endpoint { - remote-endpoint = <&dwc3_ss>; - }; - }; - }; - }; - port { - #address-cells = <1>; - #size-cells = <0>; - - rt1711h_ep: endpoint@0 { - reg = <0>; - remote-endpoint = <&dwc3_role_switch>; - }; - }; - }; - - adv7533: adv7533@39 { - status = "okay"; - compatible = "adi,adv7533"; - reg = <0x39>; - adi,dsi-lanes = <4>; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - }; - port@1 { - reg = <1>; - }; - }; - }; -}; - -&i2c7 { - /* On Low speed expansion */ - label = "LS-I2C1"; - status = "okay"; -}; - -&uart3 { - /* On Low speed expansion */ - label = "LS-UART0"; - status = "okay"; -}; - -&uart4 { - status = "okay"; - - bluetooth { - compatible = "ti,wl1837-st"; - enable-gpios = <&gpio15 6 GPIO_ACTIVE_HIGH>; - max-speed = <3000000>; - }; -}; - -&uart6 { - /* On Low speed expansion */ - label = "LS-UART1"; - status = "okay"; -}; - -&spi2 { - /* On Low speed expansion */ - label = "LS-SPI0"; - status = "okay"; -}; - -&spi3 { - /* On High speed expansion */ - label = "HS-SPI1"; - status = "okay"; -}; - -&dwmmc1 { - bus-width = <0x4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - disable-wp; - cd-gpios = <&gpio25 3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sd_pmx_func - &sd_clk_cfg_func - &sd_cfg_func>; - vmmc-supply = <&ldo16>; - vqmmc-supply = <&ldo9>; - status = "okay"; -}; - -&dwmmc2 { /* WIFI */ - bus-width = <0x4>; - non-removable; - broken-cd; - cap-power-off-card; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_pmx_func - &sdio_clk_cfg_func - &sdio_cfg_func>; - /* WL_EN */ - vmmc-supply = <&wlan_en>; - status = "okay"; - - wlcore: wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; /* sdio func num */ - /* WL_IRQ, GPIO_179_WL_WAKEUP_AP */ - interrupt-parent = <&gpio22>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&dwc3 { /* USB */ - dr_mode = "otg"; - maximum-speed = "super-speed"; - phy_type = "utmi"; - snps,dis-del-phy-power-chg-quirk; - snps,lfps_filter_quirk; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - snps,tx_de_emphasis_quirk; - snps,tx_de_emphasis = <1>; - snps,dis_enblslpm_quirk; - snps,gctl-reset-quirk; - usb-role-switch; - role-switch-default-mode = "host"; - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&rt1711h_ep>; - }; - - dwc3_ss: endpoint@1 { - reg = <1>; - remote-endpoint = <&usb_con_ss>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi deleted file mode 100644 index fe4dce23e..000000000 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ /dev/null @@ -1,1194 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for Hisilicon Hi3660 SoC - * - * Copyright (C) 2016, Hisilicon Ltd. - */ - -#include -#include -#include - -/ { - compatible = "hisilicon,hi3660"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <592>; - clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - dynamic-power-coefficient = <110>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <592>; - clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <592>; - clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&A53_L2>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <592>; - clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - }; - - cpu4: cpu@100 { - compatible = "arm,cortex-a73"; - device_type = "cpu"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&A73_L2>; - cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; - capacity-dmips-mhz = <1024>; - clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; - operating-points-v2 = <&cluster1_opp>; - #cooling-cells = <2>; - dynamic-power-coefficient = <550>; - }; - - cpu5: cpu@101 { - compatible = "arm,cortex-a73"; - device_type = "cpu"; - reg = <0x0 0x101>; - enable-method = "psci"; - next-level-cache = <&A73_L2>; - cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; - capacity-dmips-mhz = <1024>; - clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; - operating-points-v2 = <&cluster1_opp>; - #cooling-cells = <2>; - }; - - cpu6: cpu@102 { - compatible = "arm,cortex-a73"; - device_type = "cpu"; - reg = <0x0 0x102>; - enable-method = "psci"; - next-level-cache = <&A73_L2>; - cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; - capacity-dmips-mhz = <1024>; - clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; - operating-points-v2 = <&cluster1_opp>; - #cooling-cells = <2>; - }; - - cpu7: cpu@103 { - compatible = "arm,cortex-a73"; - device_type = "cpu"; - reg = <0x0 0x103>; - enable-method = "psci"; - next-level-cache = <&A73_L2>; - cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; - capacity-dmips-mhz = <1024>; - clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; - operating-points-v2 = <&cluster1_opp>; - #cooling-cells = <2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <400>; - exit-latency-us = <650>; - min-residency-us = <1500>; - }; - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <500>; - exit-latency-us = <1600>; - min-residency-us = <3500>; - }; - - - CPU_SLEEP_1: cpu-sleep-1 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <400>; - exit-latency-us = <550>; - min-residency-us = <1500>; - }; - - CLUSTER_SLEEP_1: cluster-sleep-1 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <800>; - exit-latency-us = <2900>; - min-residency-us = <3500>; - }; - }; - - A53_L2: l2-cache0 { - compatible = "cache"; - }; - - A73_L2: l2-cache1 { - compatible = "cache"; - }; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <533000000>; - opp-microvolt = <700000>; - clock-latency-ns = <300000>; - }; - - opp01 { - opp-hz = /bits/ 64 <999000000>; - opp-microvolt = <800000>; - clock-latency-ns = <300000>; - }; - - opp02 { - opp-hz = /bits/ 64 <1402000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - }; - - opp03 { - opp-hz = /bits/ 64 <1709000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <300000>; - }; - - opp04 { - opp-hz = /bits/ 64 <1844000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <300000>; - }; - }; - - cluster1_opp: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp10 { - opp-hz = /bits/ 64 <903000000>; - opp-microvolt = <700000>; - clock-latency-ns = <300000>; - }; - - opp11 { - opp-hz = /bits/ 64 <1421000000>; - opp-microvolt = <800000>; - clock-latency-ns = <300000>; - }; - - opp12 { - opp-hz = /bits/ 64 <1805000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - }; - - opp13 { - opp-hz = /bits/ 64 <2112000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <300000>; - }; - - opp14 { - opp-hz = /bits/ 64 <2362000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <300000>; - }; - }; - - gic: interrupt-controller@e82b0000 { - compatible = "arm,gic-400"; - reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ - <0x0 0xe82b2000 0 0x2000>, /* GICC */ - <0x0 0xe82b4000 0 0x2000>, /* GICH */ - <0x0 0xe82b6000 0 0x2000>; /* GICV */ - #address-cells = <0>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - }; - - a53-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - a73-pmu { - compatible = "arm,cortex-a73-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu4>, - <&cpu5>, - <&cpu6>, - <&cpu7>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - crg_ctrl: crg_ctrl@fff35000 { - compatible = "hisilicon,hi3660-crgctrl", "syscon"; - reg = <0x0 0xfff35000 0x0 0x1000>; - #clock-cells = <1>; - }; - - crg_rst: crg_rst_controller { - compatible = "hisilicon,hi3660-reset"; - #reset-cells = <2>; - hisi,rst-syscon = <&crg_ctrl>; - }; - - - pctrl: pctrl@e8a09000 { - compatible = "hisilicon,hi3660-pctrl", "syscon"; - reg = <0x0 0xe8a09000 0x0 0x2000>; - #clock-cells = <1>; - }; - - pmuctrl: crg_ctrl@fff34000 { - compatible = "hisilicon,hi3660-pmuctrl", "syscon"; - reg = <0x0 0xfff34000 0x0 0x1000>; - #clock-cells = <1>; - }; - - sctrl: sctrl@fff0a000 { - compatible = "hisilicon,hi3660-sctrl", "syscon"; - reg = <0x0 0xfff0a000 0x0 0x1000>; - #clock-cells = <1>; - }; - - iomcu: iomcu@ffd7e000 { - compatible = "hisilicon,hi3660-iomcu", "syscon"; - reg = <0x0 0xffd7e000 0x0 0x1000>; - #clock-cells = <1>; - - }; - - iomcu_rst: reset { - compatible = "hisilicon,hi3660-reset"; - hisi,rst-syscon = <&iomcu>; - #reset-cells = <2>; - }; - - mailbox: mailbox@e896b000 { - compatible = "hisilicon,hi3660-mbox"; - reg = <0x0 0xe896b000 0x0 0x1000>; - interrupts = , - ; - #mbox-cells = <3>; - }; - - stub_clock: stub_clock@e896b500 { - compatible = "hisilicon,hi3660-stub-clk"; - reg = <0x0 0xe896b500 0x0 0x0100>; - #clock-cells = <1>; - mboxes = <&mailbox 13 3 0>; - }; - - dual_timer0: timer@fff14000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x0 0xfff14000 0x0 0x1000>; - interrupts = , - ; - clocks = <&crg_ctrl HI3660_OSC32K>, - <&crg_ctrl HI3660_OSC32K>, - <&crg_ctrl HI3660_OSC32K>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - i2c0: i2c@ffd71000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0xffd71000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; - resets = <&iomcu_rst 0x20 3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; - status = "disabled"; - }; - - i2c1: i2c@ffd72000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0xffd72000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; - resets = <&iomcu_rst 0x20 4>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; - status = "disabled"; - }; - - i2c3: i2c@fdf0c000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0xfdf0c000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; - resets = <&crg_rst 0x78 7>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; - status = "disabled"; - }; - - i2c7: i2c@fdf0b000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0xfdf0b000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; - resets = <&crg_rst 0x60 14>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; - status = "disabled"; - }; - - uart0: serial@fdf02000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfdf02000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, - <&crg_ctrl HI3660_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; - status = "disabled"; - }; - - uart1: serial@fdf00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfdf00000 0x0 0x1000>; - interrupts = ; - dma-names = "rx", "tx"; - dmas = <&dma0 2 &dma0 3>; - clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, - <&crg_ctrl HI3660_CLK_GATE_UART1>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; - status = "disabled"; - }; - - uart2: serial@fdf03000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfdf03000 0x0 0x1000>; - interrupts = ; - dma-names = "rx", "tx"; - dmas = <&dma0 4 &dma0 5>; - clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, - <&crg_ctrl HI3660_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; - status = "disabled"; - }; - - uart3: serial@ffd74000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xffd74000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3660_FACTOR_UART3>, - <&crg_ctrl HI3660_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; - status = "disabled"; - }; - - uart4: serial@fdf01000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfdf01000 0x0 0x1000>; - interrupts = ; - dma-names = "rx", "tx"; - dmas = <&dma0 6 &dma0 7>; - clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, - <&crg_ctrl HI3660_CLK_GATE_UART4>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; - status = "disabled"; - }; - - uart5: serial@fdf05000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfdf05000 0x0 0x1000>; - interrupts = ; - dma-names = "rx", "tx"; - dmas = <&dma0 8 &dma0 9>; - clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, - <&crg_ctrl HI3660_CLK_GATE_UART5>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; - status = "disabled"; - }; - - uart6: serial@fff32000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfff32000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_UART6>, - <&crg_ctrl HI3660_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; - status = "disabled"; - }; - - dma0: dma@fdf30000 { - compatible = "hisilicon,k3-dma-1.0"; - reg = <0x0 0xfdf30000 0x0 0x1000>; - #dma-cells = <1>; - dma-channels = <16>; - dma-requests = <32>; - dma-channel-mask = <0xfffe>; - interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>; - dma-no-cci; - dma-type = "hi3660_dma"; - }; - - asp_dmac: dma-controller@e804b000 { - compatible = "hisilicon,hisi-pcm-asp-dma-1.0"; - reg = <0x0 0xe804b000 0x0 0x1000>; - #dma-cells = <1>; - dma-channels = <16>; - dma-requests = <32>; - interrupts = ; - interrupt-names = "asp_dma_irq"; - }; - - rtc0: rtc@fff04000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x0 0Xfff04000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3660_PCLK>; - clock-names = "apb_pclk"; - }; - - gpio0: gpio@e8a0b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a0b000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 1 0 7>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@e8a0c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a0c000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 1 7 7>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; - clock-names = "apb_pclk"; - }; - - gpio2: gpio@e8a0d000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a0d000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 14 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; - clock-names = "apb_pclk"; - }; - - gpio3: gpio@e8a0e000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a0e000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 22 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; - clock-names = "apb_pclk"; - }; - - gpio4: gpio@e8a0f000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a0f000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 30 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; - clock-names = "apb_pclk"; - }; - - gpio5: gpio@e8a10000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a10000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 38 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; - clock-names = "apb_pclk"; - }; - - gpio6: gpio@e8a11000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a11000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 46 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; - clock-names = "apb_pclk"; - }; - - gpio7: gpio@e8a12000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a12000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 54 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; - clock-names = "apb_pclk"; - }; - - gpio8: gpio@e8a13000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a13000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 62 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; - clock-names = "apb_pclk"; - }; - - gpio9: gpio@e8a14000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a14000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 70 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; - clock-names = "apb_pclk"; - }; - - gpio10: gpio@e8a15000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a15000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 78 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; - clock-names = "apb_pclk"; - }; - - gpio11: gpio@e8a16000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a16000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 86 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; - clock-names = "apb_pclk"; - }; - - gpio12: gpio@e8a17000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a17000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; - clock-names = "apb_pclk"; - }; - - gpio13: gpio@e8a18000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a18000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 102 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; - clock-names = "apb_pclk"; - }; - - gpio14: gpio@e8a19000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a19000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 110 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; - clock-names = "apb_pclk"; - }; - - gpio15: gpio@e8a1a000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a1a000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 118 6>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; - clock-names = "apb_pclk"; - }; - - gpio16: gpio@e8a1b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a1b000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; - clock-names = "apb_pclk"; - }; - - gpio17: gpio@e8a1c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a1c000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; - clock-names = "apb_pclk"; - }; - - gpio18: gpio@ff3b4000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xff3b4000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx2 0 0 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; - clock-names = "apb_pclk"; - }; - - gpio19: gpio@ff3b5000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xff3b5000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx2 0 8 4>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; - clock-names = "apb_pclk"; - }; - - gpio20: gpio@e8a1f000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a1f000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx1 0 0 6>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; - clock-names = "apb_pclk"; - }; - - gpio21: gpio@e8a20000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xe8a20000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx3 0 0 6>; - clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; - clock-names = "apb_pclk"; - }; - - gpio22: gpio@fff0b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xfff0b000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO176 */ - gpio-ranges = <&pmx4 2 0 6>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; - clock-names = "apb_pclk"; - }; - - gpio23: gpio@fff0c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xfff0c000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO184 */ - gpio-ranges = <&pmx4 0 6 7>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; - clock-names = "apb_pclk"; - }; - - gpio24: gpio@fff0d000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xfff0d000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO192 */ - gpio-ranges = <&pmx4 0 13 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; - clock-names = "apb_pclk"; - }; - - gpio25: gpio@fff0e000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xfff0e000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO200 */ - gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; - clock-names = "apb_pclk"; - }; - - gpio26: gpio@fff0f000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xfff0f000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO208 */ - gpio-ranges = <&pmx4 0 28 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; - clock-names = "apb_pclk"; - }; - - gpio27: gpio@fff10000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xfff10000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO216 */ - gpio-ranges = <&pmx4 0 36 6>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; - clock-names = "apb_pclk"; - }; - - gpio28: gpio@fff1d000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0 0xfff1d000 0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; - clock-names = "apb_pclk"; - }; - - spi2: spi@ffd68000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x0 0xffd68000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; - clock-names = "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>; - num-cs = <1>; - cs-gpios = <&gpio27 2 0>; - status = "disabled"; - }; - - spi3: spi@ff3b3000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x0 0xff3b3000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; - clock-names = "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>; - num-cs = <1>; - cs-gpios = <&gpio18 5 0>; - status = "disabled"; - }; - - pcie@f4000000 { - compatible = "hisilicon,kirin960-pcie"; - reg = <0x0 0xf4000000 0x0 0x1000>, - <0x0 0xff3fe000 0x0 0x1000>, - <0x0 0xf3f20000 0x0 0x40000>, - <0x0 0xf5000000 0x0 0x2000>; - reg-names = "dbi", "apb", "phy", "config"; - bus-range = <0x0 0x1>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x02000000 0x0 0x00000000 - 0x0 0xf6000000 - 0x0 0x02000000>; - num-lanes = <1>; - #interrupt-cells = <1>; - interrupts = <0 283 4>; - interrupt-names = "msi"; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = <0x0 0 0 1 - &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, - <0x0 0 0 2 - &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, - <0x0 0 0 3 - &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, - <0x0 0 0 4 - &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, - <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, - <&crg_ctrl HI3660_ACLK_GATE_PCIE>; - clock-names = "pcie_phy_ref", "pcie_aux", - "pcie_apb_phy", "pcie_apb_sys", - "pcie_aclk"; - reset-gpios = <&gpio11 1 0 >; - }; - - /* UFS */ - ufs: ufs@ff3b0000 { - compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1"; - /* 0: HCI standard */ - /* 1: UFS SYS CTRL */ - reg = <0x0 0xff3b0000 0x0 0x1000>, - <0x0 0xff3b1000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, - <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; - clock-names = "ref_clk", "phy_clk"; - freq-table-hz = <0 0>, <0 0>; - /* offset: 0x84; bit: 12 */ - resets = <&crg_rst 0x84 12>; - reset-names = "rst"; - }; - - /* SD */ - dwmmc1: dwmmc1@ff37f000 { - compatible = "hisilicon,hi3660-dw-mshc"; - reg = <0x0 0xff37f000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, - <&crg_ctrl HI3660_HCLK_GATE_SD>; - clock-names = "ciu", "biu"; - clock-frequency = <3200000>; - resets = <&crg_rst 0x94 18>; - reset-names = "reset"; - hisilicon,peripheral-syscon = <&sctrl>; - card-detect-delay = <200>; - status = "disabled"; - }; - - /* SDIO */ - dwmmc2: dwmmc2@ff3ff000 { - compatible = "hisilicon,hi3660-dw-mshc"; - reg = <0x0 0xff3ff000 0x0 0x1000>; - #address-cells = <0x1>; - #size-cells = <0x0>; - interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, - <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; - clock-names = "ciu", "biu"; - resets = <&crg_rst 0x94 20>; - reset-names = "reset"; - card-detect-delay = <200>; - status = "disabled"; - }; - - watchdog0: watchdog@e8a06000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xe8a06000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3660_OSC32K>, - <&crg_ctrl HI3660_OSC32K>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - watchdog1: watchdog@e8a07000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xe8a07000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3660_OSC32K>, - <&crg_ctrl HI3660_OSC32K>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - tsensor: tsensor@fff30000 { - compatible = "hisilicon,hi3660-tsensor"; - reg = <0x0 0xfff30000 0x0 0x1000>; - interrupts = ; - #thermal-sensor-cells = <1>; - }; - - thermal-zones { - - cls0: cls0 { - polling-delay = <1000>; - polling-delay-passive = <100>; - sustainable-power = <4500>; - - /* sensor ID */ - thermal-sensors = <&tsensor 1>; - - trips { - threshold: trip-point@0 { - temperature = <65000>; - hysteresis = <1000>; - type = "passive"; - }; - - target: trip-point@1 { - temperature = <75000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - contribution = <1024>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&target>; - contribution = <512>; - cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - usb3_otg_bc: usb3_otg_bc@ff200000 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0xff200000 0x0 0x1000>; - - usb_phy: usb-phy { - compatible = "hisilicon,hi3660-usb-phy"; - #phy-cells = <0>; - hisilicon,pericrg-syscon = <&crg_ctrl>; - hisilicon,pctrl-syscon = <&pctrl>; - hisilicon,eye-diagram-param = <0x22466e4>; - }; - }; - - dwc3: dwc3@ff100000 { - compatible = "snps,dwc3"; - reg = <0x0 0xff100000 0x0 0x100000>; - - clocks = <&crg_ctrl HI3660_CLK_ABB_USB>, - <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; - clock-names = "ref", "bus_early"; - - assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; - assigned-clock-rates = <229000000>; - - resets = <&crg_rst 0x90 8>, - <&crg_rst 0x90 7>, - <&crg_rst 0x90 6>, - <&crg_rst 0x90 5>; - - interrupts = <0 159 4>, <0 161 4>; - phys = <&usb_phy>; - phy-names = "usb3-phy"; - }; - }; -}; - -#include "hi3660-coresight.dtsi" diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts deleted file mode 100644 index 7f9f9886c..000000000 --- a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts +++ /dev/null @@ -1,448 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for Hisilicon HiKey970 Development Board - * - * Copyright (C) 2016, Hisilicon Ltd. - * Copyright (C) 2018, Linaro Ltd. - * - */ - -/dts-v1/; -#include - -#include "hi3670.dtsi" -#include "hikey970-pinctrl.dtsi" - -/ { - model = "HiKey970"; - compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670"; - - aliases { - mshc1 = &dwmmc1; - mshc2 = &dwmmc2; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - serial6 = &uart6; /* console UART */ - }; - - chosen { - stdout-path = "serial6:115200n8"; - }; - - memory@0 { - device_type = "memory"; - /* expect bootloader to fill in this region */ - reg = <0x0 0x0 0x0 0x0>; - }; - - sd_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - sd_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - wlan_en: wlan-en-1-8v { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - /* GPIO_051_WIFI_EN */ - gpio = <&gpio6 3 0>; - - /* WLAN card specific delay */ - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -/* - * Legend: proper name = the GPIO line is used as GPIO - * NC = not connected (pin out but not routed from the chip to - * anything the board) - * "[PER]" = pin is muxed for [peripheral] (not GPIO) - * "" = no idea, schematic doesn't say, could be - * unrouted (not connected to any external pin) - * LSEC = Low Speed External Connector - * HSEC = High Speed External Connector - * - * Line names are taken from "hikey970-schematics.pdf" from HiSilicon. - * - * For the lines routed to the external connectors the - * lines are named after the 96Boards CE Specification 1.0, - * Appendix "Expansion Connector Signal Description". - * - * When the 96Board naming of a line and the schematic name of - * the same line are in conflict, the 96Board specification - * takes precedence, which means that the external UART on the - * LSEC is named UART0 while the schematic and SoC names this - * UART2. This is only for the informational lines i.e. "[FOO]", - * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only - * ones actually used for GPIO. - */ -&gpio0 { - /* GPIO_000-GPIO_007 */ - gpio-line-names = - "", - "TP901", /* TEST_MODE connected to TP901 */ - "", - "GPIO_003_USB_HUB_RESET_N", - "NC", - "[AP_GPS_REF_CLK]", - "[I2C3_SCL]", - "[I2C3_SDA]"; -}; - -&gpio1 { - /* GPIO_008-GPIO_015 */ - gpio-line-names = - "[UART0_CTS]", /* LSEC pin 3: GPIO_008_UART2_CTS_N */ - "[UART0_RTS]", /* LSEC pin 9: GPIO_009_UART2_RTS_N */ - "[UART0_TXD]", /* LSEC pin 5: GPIO_010_UART2_TXD */ - "[UART0_RXD]", /* LSEC pin 7: GPIO_011_UART2_RXD */ - "[USER_LED5]", - "GPIO-I", /* LSEC pin 31: GPIO_013_CAM0_RST_N */ - "[USER_LED3]", - "[USER_LED4]"; -}; - -&gpio2 { - /* GPIO_016-GPIO_023 */ - gpio-line-names = - "GPIO-G", /* LSEC pin 29: GPIO_016_LCD_TE0 */ - "[CSI0_MCLK]", /* HSEC pin 15: ISP_CCLK0_MCAM */ - "[CSI1_MCLK]", /* HSEC pin 17: ISP_CCLK1_SCAM */ - "GPIO_019_BT_ACTIVE", - "[I2C2_SCL]", /* HSEC pin 32: ISP_SCL0 */ - "[I2C2_SDA]", /* HSEC pin 34: ISP_SDA0 */ - "[I2C3_SCL]", /* HSEC pin 36: ISP_SCL1 */ - "[I2C3_SDA]"; /* HSEC pin 38: ISP_SDA1 */ -}; - -&gpio3 { - /* GPIO_024-GPIO_031 */ - gpio-line-names = - "GPIO_024_WIFI_ACTIVE", - "GPIO_025_PERST_M.2", - "[I2C4_SCL]", - "[I2C4_SDA]", - "NC", - "GPIO-H", /* LSEC pin 30: GPIO_029_LCD_RST_N */ - "[USER_LED1]", - "GPIO-L"; /* LSEC pin 34: GPIO_031 */ -}; - -&gpio4 { - /* GPIO_032-GPIO_039 */ - gpio-line-names = - "GPIO-K", /* LSEC pin 33: GPIO_032_CAM1_RST_N */ - "GPIO_033_PMU1_EN", - "GPIO_034_USBSW_SEL", - /* - * These two pins should be used for SD(IO) data according - * to the 96boards specification but seems to be repurposed - * for UART 0. They are however named according to the spec. - */ - "[SD_DAT1]", /* HSEC pin 3: GPIO_035_UART0_RXD */ - "[SD_DAT2]", /* HSEC pin 5: GPIO_036_UART0_TXD */ - "[UART1_RXD]", /* LSEC pin 13: DEBUG_UART6_RXD */ - "[UART1_TXD]", /* LSEC pin 11: DEBUG_UART6_TXD */ - "[SOC_GPS_UART3_CTS_N]"; /* TP2304 */ -}; - -&gpio5 { - /* GPIO_040-GPIO_047 */ - gpio-line-names = - "[SOC_GPS_UART3_RTS_N]", /* TP2302 */ - "[SOC_GPS_UART3_RXD]", /* TP2303 */ - "[SOC_GPS_UART3_TXD]", /* TP2305 */ - "[SOC_BT_UART4_CTS_N]", - "[SOC_BT_UART4_RTS_N]", - "[SOC_BT_UART4_RXD]", - "[SOC_BT_UART4_TXD]", - "NC"; -}; - -&gpio6 { - /* GPIO_048-GPIO_055 */ - gpio-line-names = - "NC", - "GPIO_049_USER_LED6", - "GPIO_050_CAN_RST", - "GPIO_051_WIFI_EN", - "GPIO-D", /* LSEC pin 26 */ - "GPIO-J", /* LSEC pin 32 */ - "GPIO_054_BT_EN", - "[GPIO_055_SEL]"; -}; - -&gpio7 { - /* GPIO_056-GPIO_063 */ - gpio-line-names = - "[PCIE_PERST_L]", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; -}; - -&gpio8 { - /* GPIO_064-GPIO_071 */ - gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; -}; - -&gpio9 { - /* GPIO_072-GPIO_079 */ - gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; -}; - -&gpio10 { - /* GPIO_080-GPIO_087 */ - gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; -}; - -&gpio11 { - /* GPIO_088-GPIO_095 */ - gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC"; -}; - -&gpio12 { - /* GPIO_096-GPIO_103 */ - gpio-line-names = "NC", "", "", "", "", "", "", ""; -}; - -&gpio13 { - /* GPIO_104-GPIO_111 */ - gpio-line-names = "", "", "", "", "", "", "", ""; -}; - -&gpio14 { - /* GPIO_112-GPIO_119 */ - gpio-line-names = "", "", "", "", "", "", "", ""; -}; - -&gpio15 { - /* GPIO_120-GPIO_127 */ - gpio-line-names = "", "", "", "", "", "", "", ""; -}; - -&gpio16 { - /* GPIO_128-GPIO_135 */ - gpio-line-names = - "[WL_SDIO_CLK]", - "[WL_SDIO_CMD]", - "[WL_SDIO_DATA0]", - "[WL_SDIO_DATA1]", - "[WL_SDIO_DATA2]", - "[WL_SDIO_DATA3]", - "[ETH_ISOLATE]", - "NC"; -}; - -&gpio17 { - /* GPIO_136-GPIO_143 */ - gpio-line-names = - "[MINI1CLK_EN]", "NC", "", "", "", "", "", ""; -}; - -&gpio18 { - /* GPIO_144-GPIO_151 */ - gpio-line-names = - "[SPI1_SCLK]", /* HSEC pin 9: GPIO_144_SPI3_CLK */ - "[SPI1_DIN]", /* HSEC pin 11: GPIO_145_SPI3_DI */ - "[SPI1_DOUT]", /* HSEC pin 1: GPIO_146_SPI3_DO */ - "[SPI1_CS]", /* HSEC pin 7: GPIO_147_SPI3_CS0_N */ - "[POWER_INT_N]", - "[CDMA_GPS_SYNC]", - "GPIO_150_PEX_INTA", - "GPIO_151_CAN_INT"; -}; - -&gpio19 { - /* GPIO_152-GPIO_159 */ - gpio-line-names = "", "", "", "", "", "", "", ""; -}; - -&gpio20 { - /* GPIO_160-GPIO_167 */ - gpio-line-names = - "[SD_CLK]", - "[SD_CMD]", - "[SD_DATA0]", - "[SD_DATA1]", - "[SD_DATA2]", - "[SD_DATA3]", - "GPIO_166_ETHCLK_EN", - "GPIO_167_USER_LED2"; -}; - -&gpio21 { - /* GPIO_168-GPIO_175 */ - gpio-line-names = - "GPIO_168_GPS_EN", - "GPIO-C", /* LSEC pin 25: GPIO_169_USIM1_CLK */ - "GPIO-E", /* LSEC pin 27: GPIO_170_USIM1_RST */ - "GPIO-B", /* LSEC pin 24: GPIO_171_USIM1_DATA */ - "", "", "", "", ""; -}; - -&gpio22 { - /* GPIO_176-GPIO_183 */ - gpio-line-names = - "[PMU_PWR_HOLD]", - "GPIO_177_WL_WAKEUP_AP", - "[JTAG_TCK]", - "[JTAG_TMS]", - "[JTAG_TDI]", - "[JTAG_TMS]", - "GPIO_182_FATAL_ERR", - "NC"; -}; - -&gpio23 { - /* GPIO_184-GPIO_191 */ - gpio-line-names = - "GPIO_184_JTAG_SEL", - "GPIO-F", /* LSEC pin 28: GPIO_185_LCD_BL_PWM */ - "[I2C0_SCL]", /* LSEC pin 15: GPIO_186_I2C0_SCL */ - "[I2C0_SDA]", /* LSEC pin 17: GPIO_187_I2C0_SDA */ - "[GPIO_188_I2C1_SCL]", /* Actual SoC I2C1_SCL */ - "[GPIO_189_I2C1_SDA]", /* Actual SoC I2C1_SDA */ - "[I2C1_SCL]", /* LSEC pin 19: GPIO_190_I2C2_SCL */ - "[I2C2_SDA]"; /* LSEC pin 21: GPIO_191_I2C2_SDA */ -}; - -&gpio24 { - /* GPIO_192-GPIO_199 */ - gpio-line-names = - "[SD_LED]", - "NC", - "[PCM_DI]", /* LSEC pin 22: GPIO_194_I2S0_DI */ - "[PCM_DO]", /* LSEC pin 20: GPIO_195_I2S0_DO */ - "[PCM_CLK]", /* LSEC pin 18: GPIO_196_I2S0_XCLK */ - "[PCM_FS]", /* LSEC pin 16: GPIO_197_I2S0_XFS */ - "", - "[I2S2_DO]"; -}; - -&gpio25 { - /* GPIO_200-GPIO_207 */ - gpio-line-names = - "[I2S2_XCLK]", - "[I2S2_XFS]", - "GPIO_202_PERST_ETH", - "GPIO_203_PWRON_DET", - "GPIO_204_PMU1_IRQ_N", - "GPIO_205_SD_DET", - "GPIO_206_GPS_MOTION_INT", - "GPIO_207_HDMI_SEL"; -}; - -&gpio26 { - /* GPIO_208-GPIO_215 */ - gpio-line-names = - "GPIO-A", /* LSEC pin 23: GPIO_208_WAKEUP_SOC */ - "GPIO_209_VBUS_TYPEC", - "NC", - "NC", - "NC", - "[SPI0_SCLK]", /* LSEC pin 8: GPIO_213_SPI2_CLK */ - "[SPI0_DIN]", /* LSEC pin 10: GPIO_214_SPI2_DI */ - "[SPI0_DOUT]"; /* LSEC pin 14: GPIO_215_SPI2_DO */ -}; - -&gpio27 { - /* GPIO_216-GPIO_223 */ - gpio-line-names = - "[SPI0_CS]", /* LSEC pin 12: GPIO_216_SPI2_CS0_N */ - "GPIO_217_HDMI_PD", - "GPIO_218_GPS_WAKEUP_AP", - "GPIO_219_M.2CLK_EN", - "GPIO_220_PERST_MINI", - "GPIO_221_CC_INT", - "[PCIE_CLKREQ_L]", - "NC"; -}; - -&gpio28 { - /* GPIO_224-GPIO_231 */ - gpio-line-names = - "[PMU0_INT]", - "[SPMI_DATA]", - "[SPMI_CLK]", - "[CAN_SPI_CLK]", - "[CAN_SPI_DI]", - "[CAN_SPI_DO]", - "[CAN_SPI_CS]", - "GPIO_231_HDMI_INT"; -}; - -&dwmmc1 { - bus-width = <0x4>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - cap-sd-highspeed; - disable-wp; - cd-inverted; - cd-gpios = <&gpio25 5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sd_pmx_func - &sd_clk_cfg_func - &sd_cfg_func>; - vmmc-supply = <&sd_3v3>; - vqmmc-supply = <&sd_1v8>; - status = "okay"; -}; - -&dwmmc2 { /* WIFI */ - bus-width = <0x4>; - non-removable; - broken-cd; - cap-power-off-card; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_pmx_func - &sdio_clk_cfg_func - &sdio_cfg_func>; - /* WL_EN */ - vmmc-supply = <&wlan_en>; - status = "okay"; - - wlcore: wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; /* sdio func num */ - /* WL_IRQ, GPIO_177_WL_WAKEUP_AP */ - interrupt-parent = <&gpio22>; - interrupts = <1 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&uart0 { - /* On High speed expansion header */ - label = "HS-UART0"; - status = "okay"; -}; - -&uart2 { - /* On Low speed expansion header */ - label = "LS-UART0"; - status = "okay"; -}; - -&uart6 { - /* On Low speed expansion header */ - label = "LS-UART1"; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi deleted file mode 100644 index 2dcffa3ed..000000000 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ /dev/null @@ -1,713 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for Hisilicon Hi3670 SoC - * - * Copyright (C) 2016, Hisilicon Ltd. - * Copyright (C) 2018, Linaro Ltd. - */ - -#include -#include - -/ { - compatible = "hisilicon,hi3670"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - - cpu4: cpu@100 { - compatible = "arm,cortex-a73"; - device_type = "cpu"; - reg = <0x0 0x100>; - enable-method = "psci"; - }; - - cpu5: cpu@101 { - compatible = "arm,cortex-a73"; - device_type = "cpu"; - reg = <0x0 0x101>; - enable-method = "psci"; - }; - - cpu6: cpu@102 { - compatible = "arm,cortex-a73"; - device_type = "cpu"; - reg = <0x0 0x102>; - enable-method = "psci"; - }; - - cpu7: cpu@103 { - compatible = "arm,cortex-a73"; - device_type = "cpu"; - reg = <0x0 0x103>; - enable-method = "psci"; - }; - }; - - gic: interrupt-controller@e82b0000 { - compatible = "arm,gic-400"; - reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ - <0x0 0xe82b2000 0 0x2000>, /* GICC */ - <0x0 0xe82b4000 0 0x2000>, /* GICH */ - <0x0 0xe82b6000 0 0x2000>; /* GICV */ - #interrupt-cells = <3>; - #address-cells = <0>; - interrupts = ; - interrupt-controller; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - clock-frequency = <1920000>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - crg_ctrl: crg_ctrl@fff35000 { - compatible = "hisilicon,hi3670-crgctrl", "syscon"; - reg = <0x0 0xfff35000 0x0 0x1000>; - #clock-cells = <1>; - }; - - crg_rst: crg_rst_controller { - compatible = "hisilicon,hi3670-reset", - "hisilicon,hi3660-reset"; - #reset-cells = <2>; - hisi,rst-syscon = <&crg_ctrl>; - }; - - pctrl: pctrl@e8a09000 { - compatible = "hisilicon,hi3670-pctrl", "syscon"; - reg = <0x0 0xe8a09000 0x0 0x1000>; - #clock-cells = <1>; - }; - - pmuctrl: crg_ctrl@fff34000 { - compatible = "hisilicon,hi3670-pmuctrl", "syscon"; - reg = <0x0 0xfff34000 0x0 0x1000>; - #clock-cells = <1>; - }; - - sctrl: sctrl@fff0a000 { - compatible = "hisilicon,hi3670-sctrl", "syscon"; - reg = <0x0 0xfff0a000 0x0 0x1000>; - #clock-cells = <1>; - }; - - iomcu: iomcu@ffd7e000 { - compatible = "hisilicon,hi3670-iomcu", "syscon"; - reg = <0x0 0xffd7e000 0x0 0x1000>; - #clock-cells = <1>; - }; - - media1_crg: media1_crgctrl@e87ff000 { - compatible = "hisilicon,hi3670-media1-crg", "syscon"; - reg = <0x0 0xe87ff000 0x0 0x1000>; - #clock-cells = <1>; - }; - - media2_crg: media2_crgctrl@e8900000 { - compatible = "hisilicon,hi3670-media2-crg","syscon"; - reg = <0x0 0xe8900000 0x0 0x1000>; - #clock-cells = <1>; - }; - - uart0: serial@fdf02000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfdf02000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>, - <&crg_ctrl HI3670_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; - status = "disabled"; - }; - - uart1: serial@fdf00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfdf00000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>, - <&crg_ctrl HI3670_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart2: serial@fdf03000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfdf03000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3670_CLK_GATE_UART2>, - <&crg_ctrl HI3670_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; - status = "disabled"; - }; - - uart3: serial@ffd74000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xffd74000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3670_CLK_GATE_UART3>, - <&crg_ctrl HI3670_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; - status = "disabled"; - }; - - uart4: serial@fdf01000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfdf01000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3670_CLK_GATE_UART4>, - <&crg_ctrl HI3670_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; - status = "disabled"; - }; - - uart5: serial@fdf05000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfdf05000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3670_CLK_GATE_UART5>, - <&crg_ctrl HI3670_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart6: serial@fff32000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfff32000 0x0 0x1000>; - interrupts = ; - clocks = <&crg_ctrl HI3670_CLK_UART6>, - <&crg_ctrl HI3670_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; - status = "disabled"; - }; - - gpio0: gpio@e8a0b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a0b000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 1 0 1 &pmx0 3 1 5>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO0>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@e8a0c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a0c000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO1>; - clock-names = "apb_pclk"; - }; - - gpio2: gpio@e8a0d000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a0d000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 1 6 7>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO2>; - clock-names = "apb_pclk"; - }; - - gpio3: gpio@e8a0e000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a0e000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 13 4 &pmx0 7 17 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO3>; - clock-names = "apb_pclk"; - }; - - gpio4: gpio@e8a0f000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a0f000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 18 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO4>; - clock-names = "apb_pclk"; - }; - - gpio5: gpio@e8a10000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a10000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 26 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO5>; - clock-names = "apb_pclk"; - }; - - gpio6: gpio@e8a11000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a11000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 1 34 7>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO6>; - clock-names = "apb_pclk"; - }; - - gpio7: gpio@e8a12000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a12000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 41 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO7>; - clock-names = "apb_pclk"; - }; - - gpio8: gpio@e8a13000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a13000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 49 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO8>; - clock-names = "apb_pclk"; - }; - - gpio9: gpio@e8a14000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a14000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 57 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO9>; - clock-names = "apb_pclk"; - }; - - gpio10: gpio@e8a15000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a15000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 65 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO10>; - clock-names = "apb_pclk"; - }; - - gpio11: gpio@e8a16000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a16000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 73 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO11>; - clock-names = "apb_pclk"; - }; - - gpio12: gpio@e8a17000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a17000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 81 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO12>; - clock-names = "apb_pclk"; - }; - - gpio13: gpio@e8a18000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a18000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO13>; - clock-names = "apb_pclk"; - }; - - gpio14: gpio@e8a19000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a19000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO14>; - clock-names = "apb_pclk"; - }; - - gpio15: gpio@e8a1a000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a1a000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO15>; - clock-names = "apb_pclk"; - }; - - gpio16: gpio@e8a1b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a1b000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx5 0 0 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO16>; - clock-names = "apb_pclk"; - }; - - gpio17: gpio@e8a1c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a1c000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx5 0 8 2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO17>; - clock-names = "apb_pclk"; - }; - - gpio18: gpio@fff28000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xfff28000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx1 4 42 4>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3670_PCLK_GPIO18>; - clock-names = "apb_pclk"; - }; - - gpio19: gpio@fff29000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xfff29000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx1 0 61 2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3670_PCLK_GPIO19>; - clock-names = "apb_pclk"; - }; - - gpio20: gpio@e8a1f000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a1f000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx7 0 0 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO20>; - clock-names = "apb_pclk"; - }; - - gpio21: gpio@e8a20000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xe8a20000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx7 0 8 4>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg_ctrl HI3670_PCLK_GPIO21>; - clock-names = "apb_pclk"; - }; - - gpio22: gpio@fff0b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xfff0b000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO176 */ - gpio-ranges = <&pmx1 2 0 6>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3670_PCLK_AO_GPIO0>; - clock-names = "apb_pclk"; - }; - - gpio23: gpio@fff0c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xfff0c000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO184 */ - gpio-ranges = <&pmx1 0 6 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3670_PCLK_AO_GPIO1>; - clock-names = "apb_pclk"; - }; - - gpio24: gpio@fff0d000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xfff0d000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO192 */ - gpio-ranges = <&pmx1 0 14 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3670_PCLK_AO_GPIO2>; - clock-names = "apb_pclk"; - }; - - gpio25: gpio@fff0e000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xfff0e000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO200 */ - gpio-ranges = <&pmx1 0 22 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3670_PCLK_AO_GPIO3>; - clock-names = "apb_pclk"; - }; - - gpio26: gpio@fff0f000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xfff0f000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO208 */ - gpio-ranges = <&pmx1 0 30 1>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3670_PCLK_AO_GPIO4>; - clock-names = "apb_pclk"; - }; - - gpio27: gpio@fff10000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xfff10000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - /* GPIO216 */ - gpio-ranges = <&pmx1 4 31 4>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3670_PCLK_AO_GPIO5>; - clock-names = "apb_pclk"; - }; - - gpio28: gpio@fff1d000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xfff1d000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx1 1 35 7>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&sctrl HI3670_PCLK_AO_GPIO6>; - clock-names = "apb_pclk"; - }; - - /* UFS */ - ufs: ufs@ff3c0000 { - compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1"; - /* 0: HCI standard */ - /* 1: UFS SYS CTRL */ - reg = <0x0 0xff3c0000 0x0 0x1000>, - <0x0 0xff3e0000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>, - <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>; - clock-names = "ref_clk", "phy_clk"; - freq-table-hz = <0 0>, <0 0>; - /* offset: 0x84; bit: 12 */ - resets = <&crg_rst 0x84 12>; - reset-names = "rst"; - }; - - /* SD */ - dwmmc1: dwmmc1@ff37f000 { - compatible = "hisilicon,hi3670-dw-mshc", - "hisilicon,hi3660-dw-mshc"; - reg = <0x0 0xff37f000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&crg_ctrl HI3670_CLK_GATE_SD>, - <&crg_ctrl HI3670_HCLK_GATE_SD>; - clock-names = "ciu", "biu"; - clock-frequency = <3200000>; - resets = <&crg_rst 0x94 18>; - reset-names = "reset"; - hisilicon,peripheral-syscon = <&sctrl>; - card-detect-delay = <200>; - status = "disabled"; - }; - - /* SDIO */ - dwmmc2: dwmmc2@fc183000 { - compatible = "hisilicon,hi3670-dw-mshc", - "hisilicon,hi3660-dw-mshc"; - reg = <0x0 0xfc183000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&crg_ctrl HI3670_CLK_GATE_SDIO>, - <&crg_ctrl HI3670_HCLK_GATE_SDIO>; - clock-names = "ciu", "biu"; - clock-frequency = <3200000>; - resets = <&crg_rst 0x94 20>; - reset-names = "reset"; - card-detect-delay = <200>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts deleted file mode 100644 index 7d370dac4..000000000 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts +++ /dev/null @@ -1,206 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DTS File for HiSilicon Poplar Development Board - * - * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. - */ - -/dts-v1/; - -#include -#include "hi3798cv200.dtsi" -#include "poplar-pinctrl.dtsi" - -/ { - model = "HiSilicon Poplar Development Board"; - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200"; - - aliases { - serial0 = &uart0; - serial2 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - leds { - compatible = "gpio-leds"; - - user-led0 { - label = "green:user1"; - gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - user-led1 { - label = "green:user2"; - gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - user-led2 { - label = "green:user3"; - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - user-led3 { - label = "green:user4"; - gpios = <&gpio10 6 GPIO_ACTIVE_LOW>; - linux,default-trigger = "none"; - panic-indicator; - default-state = "off"; - }; - }; - - reg_pcie: regulator-pcie { - compatible = "regulator-fixed"; - regulator-name = "3V3_PCIE0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio6 7 0>; - enable-active-high; - }; -}; - -&ehci { - status = "okay"; -}; - -&emmc { - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pins_1 &emmc_pins_2 - &emmc_pins_3 &emmc_pins_4>; - fifo-depth = <256>; - clock-frequency = <200000000>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - bus-width = <8>; - status = "okay"; -}; - -&gmac1 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - phy-handle = <ð_phy1>; - phy-mode = "rgmii"; - hisilicon,phy-reset-delays-us = <10000 10000 30000>; - - eth_phy1: phy@3 { - reg = <3>; - }; -}; - -&gpio1 { - status = "okay"; - gpio-line-names = "GPIO-E", "", - "", "", - "", "GPIO-F", - "", "GPIO-J"; -}; - -&gpio2 { - status = "okay"; - gpio-line-names = "GPIO-H", "GPIO-I", - "GPIO-L", "GPIO-G", - "GPIO-K", "", - "", ""; -}; - -&gpio3 { - status = "okay"; - gpio-line-names = "", "", - "", "", - "GPIO-C", "", - "", "GPIO-B"; -}; - -&gpio4 { - status = "okay"; - gpio-line-names = "", "", - "", "", - "", "GPIO-D", - "", ""; -}; - -&gpio5 { - status = "okay"; - gpio-line-names = "", "USER-LED-1", - "USER-LED-2", "", - "", "GPIO-A", - "", ""; -}; - -&gpio6 { - status = "okay"; - gpio-line-names = "", "", - "", "USER-LED-0", - "", "", - "", ""; -}; - -&gpio10 { - status = "okay"; - gpio-line-names = "", "", - "", "", - "", "", - "USER-LED-3", ""; -}; - -&i2c0 { - status = "okay"; - label = "LS-I2C0"; -}; - -&i2c2 { - status = "okay"; - label = "LS-I2C1"; -}; - -&ir { - linux,rc-map-name = "rc-hisi-poplar"; - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -&pcie { - reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; - vpcie-supply = <®_pcie>; - status = "okay"; -}; - -&sd0 { - bus-width = <4>; - cap-sd-highspeed; - status = "okay"; -}; - -&spi0 { - status = "okay"; - label = "LS-SPI0"; -}; - -&uart0 { - status = "okay"; -}; - -&uart2 { - status = "okay"; - label = "LS-UART0"; -}; -/* No optional LS-UART1 on Low Speed Expansion Connector. */ diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi deleted file mode 100644 index 12bc1d3ed..000000000 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ /dev/null @@ -1,620 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DTS File for HiSilicon Hi3798cv200 SoC. - * - * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. - */ - -#include -#include -#include -#include -#include - -/ { - compatible = "hisilicon,hi3798cv200"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - gic: interrupt-controller@f1001000 { - compatible = "arm,gic-400"; - reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ - <0x0 0xf1002000 0x0 0x100>; /* GICC */ - #address-cells = <0>; - #interrupt-cells = <3>; - interrupt-controller; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - soc: soc@f0000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0xf0000000 0x10000000>; - - crg: clock-reset-controller@8a22000 { - compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd"; - reg = <0x8a22000 0x1000>; - #clock-cells = <1>; - #reset-cells = <2>; - - gmacphyrst: reset-controller { - compatible = "ti,syscon-reset"; - #reset-cells = <1>; - ti,reset-bits = - <0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | - DEASSERT_SET|STATUS_NONE)>, - <0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | - DEASSERT_SET|STATUS_NONE)>; - }; - }; - - sysctrl: system-controller@8000000 { - compatible = "hisilicon,hi3798cv200-sysctrl", "syscon"; - reg = <0x8000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <2>; - }; - - perictrl: peripheral-controller@8a20000 { - compatible = "hisilicon,hi3798cv200-perictrl", "syscon", - "simple-mfd"; - reg = <0x8a20000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x8a20000 0x1000>; - - usb2_phy1: usb2-phy@120 { - compatible = "hisilicon,hi3798cv200-usb2-phy"; - reg = <0x120 0x4>; - clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; - resets = <&crg 0xbc 4>; - #address-cells = <1>; - #size-cells = <0>; - - usb2_phy1_port0: phy@0 { - reg = <0>; - #phy-cells = <0>; - resets = <&crg 0xbc 8>; - }; - - usb2_phy1_port1: phy@1 { - reg = <1>; - #phy-cells = <0>; - resets = <&crg 0xbc 9>; - }; - }; - - usb2_phy2: usb2-phy@124 { - compatible = "hisilicon,hi3798cv200-usb2-phy"; - reg = <0x124 0x4>; - clocks = <&crg HISTB_USB2_PHY2_REF_CLK>; - resets = <&crg 0xbc 6>; - #address-cells = <1>; - #size-cells = <0>; - - usb2_phy2_port0: phy@0 { - reg = <0>; - #phy-cells = <0>; - resets = <&crg 0xbc 10>; - }; - }; - - combphy0: phy@850 { - compatible = "hisilicon,hi3798cv200-combphy"; - reg = <0x850 0x8>; - #phy-cells = <1>; - clocks = <&crg HISTB_COMBPHY0_CLK>; - resets = <&crg 0x188 4>; - assigned-clocks = <&crg HISTB_COMBPHY0_CLK>; - assigned-clock-rates = <100000000>; - hisilicon,fixed-mode = ; - }; - - combphy1: phy@858 { - compatible = "hisilicon,hi3798cv200-combphy"; - reg = <0x858 0x8>; - #phy-cells = <1>; - clocks = <&crg HISTB_COMBPHY1_CLK>; - resets = <&crg 0x188 12>; - assigned-clocks = <&crg HISTB_COMBPHY1_CLK>; - assigned-clock-rates = <100000000>; - hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>; - }; - }; - - pmx0: pinconf@8a21000 { - compatible = "pinconf-single"; - reg = <0x8a21000 0x180>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <7>; - pinctrl-single,gpio-range = < - &range 0 8 2 /* GPIO 0 */ - &range 8 1 0 /* GPIO 1 */ - &range 9 4 2 - &range 13 1 0 - &range 14 1 1 - &range 15 1 0 - &range 16 5 0 /* GPIO 2 */ - &range 21 3 1 - &range 24 4 1 /* GPIO 3 */ - &range 28 2 2 - &range 86 1 1 - &range 87 1 0 - &range 30 4 2 /* GPIO 4 */ - &range 34 3 0 - &range 37 1 2 - &range 38 3 2 /* GPIO 6 */ - &range 41 5 0 - &range 46 8 1 /* GPIO 7 */ - &range 54 8 1 /* GPIO 8 */ - &range 64 7 1 /* GPIO 9 */ - &range 71 1 0 - &range 72 6 1 /* GPIO 10 */ - &range 78 1 0 - &range 79 1 1 - &range 80 6 1 /* GPIO 11 */ - &range 70 2 1 - &range 88 8 0 /* GPIO 12 */ - >; - - range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; - }; - - uart0: serial@8b00000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x8b00000 0x1000>; - interrupts = ; - clocks = <&sysctrl HISTB_UART0_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - uart2: serial@8b02000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x8b02000 0x1000>; - interrupts = ; - clocks = <&crg HISTB_UART2_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - i2c0: i2c@8b10000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0x8b10000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <400000>; - clocks = <&crg HISTB_I2C0_CLK>; - status = "disabled"; - }; - - i2c1: i2c@8b11000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0x8b11000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <400000>; - clocks = <&crg HISTB_I2C1_CLK>; - status = "disabled"; - }; - - i2c2: i2c@8b12000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0x8b12000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <400000>; - clocks = <&crg HISTB_I2C2_CLK>; - status = "disabled"; - }; - - i2c3: i2c@8b13000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0x8b13000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <400000>; - clocks = <&crg HISTB_I2C3_CLK>; - status = "disabled"; - }; - - i2c4: i2c@8b14000 { - compatible = "hisilicon,hix5hd2-i2c"; - reg = <0x8b14000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clock-frequency = <400000>; - clocks = <&crg HISTB_I2C4_CLK>; - status = "disabled"; - }; - - spi0: spi@8b1a000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x8b1a000 0x1000>; - interrupts = ; - num-cs = <1>; - cs-gpios = <&gpio7 1 0>; - clocks = <&crg HISTB_SPI0_CLK>; - clock-names = "apb_pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sd0: mmc@9820000 { - compatible = "snps,dw-mshc"; - reg = <0x9820000 0x10000>; - interrupts = ; - clocks = <&crg HISTB_SDIO0_CIU_CLK>, - <&crg HISTB_SDIO0_BIU_CLK>; - clock-names = "ciu", "biu"; - resets = <&crg 0x9c 4>; - reset-names = "reset"; - status = "disabled"; - }; - - emmc: mmc@9830000 { - compatible = "hisilicon,hi3798cv200-dw-mshc"; - reg = <0x9830000 0x10000>; - interrupts = ; - clocks = <&crg HISTB_MMC_CIU_CLK>, - <&crg HISTB_MMC_BIU_CLK>, - <&crg HISTB_MMC_SAMPLE_CLK>, - <&crg HISTB_MMC_DRV_CLK>; - clock-names = "ciu", "biu", "ciu-sample", "ciu-drive"; - resets = <&crg 0xa0 4>; - reset-names = "reset"; - status = "disabled"; - }; - - gpio0: gpio@8b20000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b20000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx0 0 0 8>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio1: gpio@8b21000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b21000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = < - &pmx0 0 8 1 - &pmx0 1 9 4 - &pmx0 5 13 1 - &pmx0 6 14 1 - &pmx0 7 15 1 - >; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio2: gpio@8b22000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b22000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio3: gpio@8b23000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b23000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = < - &pmx0 0 24 4 - &pmx0 4 28 2 - &pmx0 6 86 1 - &pmx0 7 87 1 - >; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio4: gpio@8b24000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b24000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio5: gpio@8004000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8004000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio6: gpio@8b26000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b26000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio7: gpio@8b27000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b27000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx0 0 46 8>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio8: gpio@8b28000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b28000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx0 0 54 8>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio9: gpio@8b29000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b29000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio10: gpio@8b2a000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b2a000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio11: gpio@8b2b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b2b000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio12: gpio@8b2c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x8b2c000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&pmx0 0 88 8>; - clocks = <&crg HISTB_APB_CLK>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gmac0: ethernet@9840000 { - compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; - reg = <0x9840000 0x1000>, - <0x984300c 0x4>; - interrupts = ; - clocks = <&crg HISTB_ETH0_MAC_CLK>, - <&crg HISTB_ETH0_MACIF_CLK>; - clock-names = "mac_core", "mac_ifc"; - resets = <&crg 0xcc 8>, - <&crg 0xcc 10>, - <&gmacphyrst 0>; - reset-names = "mac_core", "mac_ifc", "phy"; - status = "disabled"; - }; - - gmac1: ethernet@9841000 { - compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; - reg = <0x9841000 0x1000>, - <0x9843010 0x4>; - interrupts = ; - clocks = <&crg HISTB_ETH1_MAC_CLK>, - <&crg HISTB_ETH1_MACIF_CLK>; - clock-names = "mac_core", "mac_ifc"; - resets = <&crg 0xcc 9>, - <&crg 0xcc 11>, - <&gmacphyrst 1>; - reset-names = "mac_core", "mac_ifc", "phy"; - status = "disabled"; - }; - - ir: ir@8001000 { - compatible = "hisilicon,hix5hd2-ir"; - reg = <0x8001000 0x1000>; - interrupts = ; - clocks = <&sysctrl HISTB_IR_CLK>; - status = "disabled"; - }; - - pcie: pcie@9860000 { - compatible = "hisilicon,hi3798cv200-pcie"; - reg = <0x9860000 0x1000>, - <0x0 0x2000>, - <0x2000000 0x01000000>; - reg-names = "control", "rc-dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x00 0xff>; - num-lanes = <1>; - ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000 - 0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&crg HISTB_PCIE_AUX_CLK>, - <&crg HISTB_PCIE_PIPE_CLK>, - <&crg HISTB_PCIE_SYS_CLK>, - <&crg HISTB_PCIE_BUS_CLK>; - clock-names = "aux", "pipe", "sys", "bus"; - resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>; - reset-names = "soft", "sys", "bus"; - phys = <&combphy1 PHY_TYPE_PCIE>; - phy-names = "phy"; - status = "disabled"; - }; - - ohci: ohci@9880000 { - compatible = "generic-ohci"; - reg = <0x9880000 0x10000>; - interrupts = ; - clocks = <&crg HISTB_USB2_BUS_CLK>, - <&crg HISTB_USB2_12M_CLK>, - <&crg HISTB_USB2_48M_CLK>; - clock-names = "bus", "clk12", "clk48"; - resets = <&crg 0xb8 12>; - reset-names = "bus"; - phys = <&usb2_phy1_port0>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci: ehci@9890000 { - compatible = "generic-ehci"; - reg = <0x9890000 0x10000>; - interrupts = ; - clocks = <&crg HISTB_USB2_BUS_CLK>, - <&crg HISTB_USB2_PHY_CLK>, - <&crg HISTB_USB2_UTMI_CLK>; - clock-names = "bus", "phy", "utmi"; - resets = <&crg 0xb8 12>, - <&crg 0xb8 16>, - <&crg 0xb8 13>; - reset-names = "bus", "phy", "utmi"; - phys = <&usb2_phy1_port0>; - phy-names = "usb"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi deleted file mode 100644 index 7b3010f44..000000000 --- a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi +++ /dev/null @@ -1,482 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * dtsi file for Hisilicon Hi6220 coresight - * - * Copyright (C) 2017 Hisilicon Ltd. - * - * Author: Pengcheng Li - * Leo Yan - */ - -/ { - soc { - funnel@f6401000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0xf6401000 0 0x1000>; - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - out-ports { - port { - soc_funnel_out: endpoint { - remote-endpoint = - <&etf_in>; - }; - }; - }; - - in-ports { - port { - soc_funnel_in: endpoint { - remote-endpoint = - <&acpu_funnel_out>; - }; - }; - }; - }; - - etf@f6402000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0xf6402000 0 0x1000>; - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - in-ports { - port { - etf_in: endpoint { - remote-endpoint = - <&soc_funnel_out>; - }; - }; - }; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = - <&replicator_in>; - }; - }; - }; - }; - - replicator { - compatible = "arm,coresight-static-replicator"; - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = - <&etf_out>; - }; - }; - }; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = - <&etr_in>; - }; - }; - - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = - <&tpiu_in>; - }; - }; - }; - }; - - etr@f6404000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0xf6404000 0 0x1000>; - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = - <&replicator_out0>; - }; - }; - }; - }; - - tpiu@f6405000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0 0xf6405000 0 0x1000>; - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - in-ports { - port { - tpiu_in: endpoint { - remote-endpoint = - <&replicator_out1>; - }; - }; - }; - }; - - funnel@f6501000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0xf6501000 0 0x1000>; - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - out-ports { - port { - acpu_funnel_out: endpoint { - remote-endpoint = - <&soc_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - acpu_funnel_in0: endpoint { - remote-endpoint = - <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - acpu_funnel_in1: endpoint { - remote-endpoint = - <&etm1_out>; - }; - }; - - port@2 { - reg = <2>; - acpu_funnel_in2: endpoint { - remote-endpoint = - <&etm2_out>; - }; - }; - - port@3 { - reg = <3>; - acpu_funnel_in3: endpoint { - remote-endpoint = - <&etm3_out>; - }; - }; - - port@4 { - reg = <4>; - acpu_funnel_in4: endpoint { - remote-endpoint = - <&etm4_out>; - }; - }; - - port@5 { - reg = <5>; - acpu_funnel_in5: endpoint { - remote-endpoint = - <&etm5_out>; - }; - }; - - port@6 { - reg = <6>; - acpu_funnel_in6: endpoint { - remote-endpoint = - <&etm6_out>; - }; - }; - - port@7 { - reg = <7>; - acpu_funnel_in7: endpoint { - remote-endpoint = - <&etm7_out>; - }; - }; - }; - }; - - etm0: etm@f659c000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xf659c000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu0>; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = - <&acpu_funnel_in0>; - }; - }; - }; - }; - - etm1: etm@f659d000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xf659d000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu1>; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = - <&acpu_funnel_in1>; - }; - }; - }; - }; - - etm2: etm@f659e000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xf659e000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu2>; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = - <&acpu_funnel_in2>; - }; - }; - }; - }; - - etm3: etm@f659f000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xf659f000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu3>; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = - <&acpu_funnel_in3>; - }; - }; - }; - }; - - etm4: etm@f65dc000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xf65dc000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu4>; - - out-ports { - port { - etm4_out: endpoint { - remote-endpoint = - <&acpu_funnel_in4>; - }; - }; - }; - }; - - etm5: etm@f65dd000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xf65dd000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu5>; - - out-ports { - port { - etm5_out: endpoint { - remote-endpoint = - <&acpu_funnel_in5>; - }; - }; - }; - }; - - etm6: etm@f65de000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xf65de000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu6>; - - out-ports { - port { - etm6_out: endpoint { - remote-endpoint = - <&acpu_funnel_in6>; - }; - }; - }; - }; - - etm7: etm@f65df000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0xf65df000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu7>; - - out-ports { - port { - etm7_out: endpoint { - remote-endpoint = - <&acpu_funnel_in7>; - }; - }; - }; - }; - - /* System CTIs */ - /* CTI 0 - TMC and TPIU connections */ - cti@f6403000 { - compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0 0xf6403000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - }; - - /* CTI - CPU-0 */ - cti@f6598000 { - compatible = "arm,coresight-cti-v8-arch", - "arm,coresight-cti", "arm,primecell"; - reg = <0 0xf6598000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu0>; - arm,cs-dev-assoc = <&etm0>; - }; - - /* CTI - CPU-1 */ - cti@f6599000 { - compatible = "arm,coresight-cti-v8-arch", - "arm,coresight-cti", "arm,primecell"; - reg = <0 0xf6599000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu1>; - arm,cs-dev-assoc = <&etm1>; - }; - - /* CTI - CPU-2 */ - cti@f659a000 { - compatible = "arm,coresight-cti-v8-arch", - "arm,coresight-cti", "arm,primecell"; - reg = <0 0xf659a000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu2>; - arm,cs-dev-assoc = <&etm2>; - }; - - /* CTI - CPU-3 */ - cti@f659b000 { - compatible = "arm,coresight-cti-v8-arch", - "arm,coresight-cti", "arm,primecell"; - reg = <0 0xf659b000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu3>; - arm,cs-dev-assoc = <&etm3>; - }; - - /* CTI - CPU-4 */ - cti@f65d8000 { - compatible = "arm,coresight-cti-v8-arch", - "arm,coresight-cti", "arm,primecell"; - reg = <0 0xf65d8000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu4>; - arm,cs-dev-assoc = <&etm4>; - }; - - /* CTI - CPU-5 */ - cti@f65d9000 { - compatible = "arm,coresight-cti-v8-arch", - "arm,coresight-cti", "arm,primecell"; - reg = <0 0xf65d9000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu5>; - arm,cs-dev-assoc = <&etm5>; - }; - - /* CTI - CPU-6 */ - cti@f65da000 { - compatible = "arm,coresight-cti-v8-arch", - "arm,coresight-cti", "arm,primecell"; - reg = <0 0xf65da000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu6>; - arm,cs-dev-assoc = <&etm6>; - }; - - /* CTI - CPU-7 */ - cti@f65db000 { - compatible = "arm,coresight-cti-v8-arch", - "arm,coresight-cti", "arm,primecell"; - reg = <0 0xf65db000 0 0x1000>; - - clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; - clock-names = "apb_pclk"; - - cpu = <&cpu7>; - arm,cs-dev-assoc = <&etm7>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts deleted file mode 100644 index 91d08673c..000000000 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ /dev/null @@ -1,545 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for Hisilicon HiKey Development Board - * - * Copyright (C) 2015, Hisilicon Ltd. - * - */ - -/dts-v1/; -#include "hi6220.dtsi" -#include "hikey-pinctrl.dtsi" -#include - -/ { - model = "HiKey Development Board"; - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; - - aliases { - serial0 = &uart0; /* On board UART0 */ - serial1 = &uart1; /* BT UART */ - serial2 = &uart2; /* LS Expansion UART0 */ - serial3 = &uart3; /* LS Expansion UART1 */ - }; - - chosen { - stdout-path = "serial3:115200n8"; - }; - - /* - * Reserve below regions from memory node: - * - * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using - * 0x05f0,1000 - 0x05f0,1fff: Reboot reason - * 0x06df,f000 - 0x06df,ffff: Mailbox message data - * 0x0740,f000 - 0x0740,ffff: MCU firmware section - * 0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer - * 0x3e00,0000 - 0x3fff,ffff: OP-TEE - */ - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x05e00000>, - <0x00000000 0x05f00000 0x00000000 0x00001000>, - <0x00000000 0x05f02000 0x00000000 0x00efd000>, - <0x00000000 0x06e00000 0x00000000 0x0060f000>, - <0x00000000 0x07410000 0x00000000 0x1aaf0000>, - <0x00000000 0x22000000 0x00000000 0x1c000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ramoops@21f00000 { - compatible = "ramoops"; - reg = <0x0 0x21f00000 0x0 0x00100000>; - record-size = <0x00020000>; - console-size = <0x00020000>; - ftrace-size = <0x00020000>; - }; - - /* global autoconfigured region for contiguous allocations */ - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x00000000 0x08000000>; - linux,cma-default; - }; - }; - - reboot-mode-syscon@5f01000 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0x05f01000 0x0 0x00001000>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x0>; - - mode-normal = <0x77665501>; - mode-bootloader = <0x77665500>; - mode-recovery = <0x77665502>; - }; - }; - - reg_sys_5v: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "SYS_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vdd_3v3: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - vin-supply = <®_sys_5v>; - }; - - reg_5v_hub: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "5V_HUB"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - gpio = <&gpio0 7 0>; - regulator-always-on; - vin-supply = <®_sys_5v>; - }; - - wl1835_pwrseq: wl1835-pwrseq { - compatible = "mmc-pwrseq-simple"; - /* WLAN_EN GPIO */ - reset-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - clocks = <&pmic>; - clock-names = "ext_clock"; - post-power-on-delay-ms = <10>; - power-off-delay-us = <10>; - }; - - leds { - compatible = "gpio-leds"; - - user_led1 { - label = "green:user1"; - gpios = <&gpio4 0 0>; /* <&gpio_user_led_1>; */ - linux,default-trigger = "heartbeat"; - }; - - user_led2 { - label = "green:user2"; - gpios = <&gpio4 1 0>; /* <&gpio_user_led_2>; */ - linux,default-trigger = "mmc0"; - }; - - user_led3 { - label = "green:user3"; - gpios = <&gpio4 2 0>; /* <&gpio_user_led_3>; */ - linux,default-trigger = "mmc1"; - }; - - user_led4 { - label = "green:user4"; - gpios = <&gpio4 3 0>; /* <&gpio_user_led_4>; */ - panic-indicator; - linux,default-trigger = "none"; - }; - - wlan_active_led { - label = "yellow:wlan"; - gpios = <&gpio3 5 0>; /* <&gpio_wlan_active_led>; */ - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - bt_active_led { - label = "blue:bt"; - gpios = <&gpio4 7 0>; /* <&gpio_bt_active_led>; */ - linux,default-trigger = "hci0-power"; - default-state = "off"; - }; - }; - - pmic: pmic@f8000000 { - compatible = "hisilicon,hi655x-pmic"; - reg = <0x0 0xf8000000 0x0 0x1000>; - #clock-cells = <0>; - interrupt-controller; - #interrupt-cells = <2>; - pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - - regulators { - ldo2: LDO2 { - regulator-name = "LDO2_2V8"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3200000>; - regulator-enable-ramp-delay = <120>; - }; - - ldo7: LDO7 { - regulator-name = "LDO7_SDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <120>; - }; - - ldo10: LDO10 { - regulator-name = "LDO10_2V85"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <360>; - }; - - ldo13: LDO13 { - regulator-name = "LDO13_1V8"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1950000>; - regulator-enable-ramp-delay = <120>; - }; - - ldo14: LDO14 { - regulator-name = "LDO14_2V8"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3200000>; - regulator-enable-ramp-delay = <120>; - }; - - ldo15: LDO15 { - regulator-name = "LDO15_1V8"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <1950000>; - regulator-boot-on; - regulator-always-on; - regulator-enable-ramp-delay = <120>; - }; - - ldo17: LDO17 { - regulator-name = "LDO17_2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3200000>; - regulator-enable-ramp-delay = <120>; - }; - - ldo19: LDO19 { - regulator-name = "LDO19_3V0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <360>; - }; - - ldo21: LDO21 { - regulator-name = "LDO21_1V8"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - regulator-enable-ramp-delay = <120>; - }; - - ldo22: LDO22 { - regulator-name = "LDO22_1V2"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - regulator-enable-ramp-delay = <120>; - }; - }; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; - - sound_card { - compatible = "audio-graph-card"; - dais = <&i2s0_port0>; - }; -}; - -&uart1 { - assigned-clocks = <&sys_ctrl HI6220_UART1_SRC>; - assigned-clock-rates = <150000000>; - status = "okay"; - - bluetooth { - compatible = "ti,wl1835-st"; - enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - clocks = <&pmic>; - clock-names = "ext_clock"; - }; -}; - -&uart2 { - status = "okay"; - label = "LS-UART0"; -}; - -&uart3 { - status = "okay"; - label = "LS-UART1"; -}; - -&ade { - status = "okay"; -}; - -&dsi { - status = "okay"; - - ports { - /* 1 for output port */ - port@1 { - reg = <1>; - - dsi_out0: endpoint@0 { - remote-endpoint = <&adv7533_in>; - }; - }; - }; -}; - -&dwmmc_0 { - cap-mmc-highspeed; - non-removable; - bus-width = <0x8>; - vmmc-supply = <&ldo19>; -}; - -&dwmmc_1 { - card-detect-delay = <200>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - vqmmc-supply = <&ldo7>; - vmmc-supply = <&ldo10>; - bus-width = <0x4>; - disable-wp; - cd-gpios = <&gpio1 0 1>; -}; - -&dwmmc_2 { - bus-width = <0x4>; - non-removable; - cap-power-off-card; - vmmc-supply = <®_vdd_3v3>; - mmc-pwrseq = <&wl1835_pwrseq>; - - #address-cells = <0x1>; - #size-cells = <0x0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; /* sdio func num */ - /* WL_IRQ, WL_HOST_WAKE_GPIO1_3 */ - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>; - }; -}; - -/* - * Legend: proper name = the GPIO line is used as GPIO - * NC = not connected (not routed from the SoC) - * "[PER]" = pin is muxed for peripheral (not GPIO) - * "" = no idea, schematic doesn't say, could be - * unrouted (not connected to any external pin) - * LSEC = Low Speed External Connector - * HSEC = High Speed External Connector - * - * Pin assignments taken from LeMaker and CircuitCo Schematics - * Rev A1. - * - * For the lines routed to the external connectors the - * lines are named after the 96Boards CE Specification 1.0, - * Appendix "Expansion Connector Signal Description". - * - * When the 96Board naming of a line and the schematic name of - * the same line are in conflict, the 96Board specification - * takes precedence, which means that the external UART on the - * LSEC is named UART0 while the schematic and SoC names this - * UART2. This is only for the informational lines i.e. "[FOO]", - * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only - * ones actually used for GPIO. - */ -&gpio0 { - gpio-line-names = "PWR_HOLD", "DSI_SEL", - "USB_HUB_RESET_N", "USB_SEL", "HDMI_PD", "WL_REG_ON", - "PWRON_DET", "5V_HUB_EN"; -}; - -&gpio1 { - gpio-line-names = "SD_DET", "HDMI_INT", "PMU_IRQ_N", - "WL_HOST_WAKE", "NC", "NC", "NC", "BT_REG_ON"; -}; - -&gpio2 { - gpio-line-names = - "GPIO-A", /* LSEC Pin 23: GPIO2_0 */ - "GPIO-B", /* LSEC Pin 24: GPIO2_1 */ - "GPIO-C", /* LSEC Pin 25: GPIO2_2 */ - "GPIO-D", /* LSEC Pin 26: GPIO2_3 */ - "GPIO-E", /* LSEC Pin 27: GPIO2_4 */ - "USB_ID_DET", "USB_VBUS_DET", - "GPIO-H"; /* LSEC Pin 30: GPIO2_7 */ -}; - -&gpio3 { - gpio-line-names = "GPIO3_0", "NC", "NC", "", "NC", "", - "WLAN_ACTIVE", "NC", "NC"; -}; - -&gpio4 { - gpio-line-names = "USER_LED1", "USER_LED2", "USER_LED3", - "USER_LED4", "SD_SEL", "NC", "NC", "BT_ACTIVE"; -}; - -&gpio5 { - gpio-line-names = "NC", "NC", - "[UART1_RxD]", /* LSEC Pin 11: UART3_RX */ - "[UART1_TxD]", /* LSEC Pin 13: UART3_TX */ - "[AUX_SSI1]", "NC", - "[PCM_CLK]", /* LSEC Pin 18: MODEM_PCM_XCLK */ - "[PCM_FS]"; /* LSEC Pin 16: MODEM_PCM_XFS */ -}; - -&gpio6 { - gpio-line-names = - "[SPI0_DIN]", /* Pin 10: SPI0_DI */ - "[SPI0_DOUT]", /* Pin 14: SPI0_DO */ - "[SPI0_CS]", /* Pin 12: SPI0_CS_N */ - "[SPI0_SCLK]", /* Pin 8: SPI0_SCLK */ - "NC", "NC", "NC", - "GPIO-G"; /* Pin 29: GPIO6_7_DSI_TE0 */ -}; - -&gpio7 { - gpio-line-names = "NC", "NC", "NC", "NC", - "[PCM_DI]", /* Pin 22: MODEM_PCM_DI */ - "[PCM_DO]", /* Pin 20: MODEM_PCM_DO */ - "NC", "NC"; -}; - -&gpio8 { - gpio-line-names = "NC", "[CEC_CLK_19_2MHZ]", "NC", - "", "", "", "", "", ""; -}; - -&gpio9 { - gpio-line-names = "", - "GPIO-J", /* LSEC Pin 32: ISP_PWDN0_GPIO9_1 */ - "GPIO-L", /* LSEC Pin 34: ISP_PWDN1_GPIO9_2 */ - "NC", "NC", "NC", "NC", "[ISP_CCLK0]"; -}; - -&gpio10 { - gpio-line-names = "BOOT_SEL", - "[ISP_CCLK1]", - "GPIO-I", /* LSEC Pin 31: ISP_RSTB0_GPIO10_2 */ - "GPIO-K", /* LSEC Pin 33: ISP_RSTB1_GPIO10_3 */ - "NC", "NC", - "[I2C2_SDA]", /* HSEC Pin 34: ISP0_SDA */ - "[I2C2_SCL]"; /* HSEC Pin 32: ISP0_SCL */ -}; - -&gpio11 { - gpio-line-names = - "[I2C3_SDA]", /* HSEC Pin 38: ISP1_SDA */ - "[I2C3_SCL]", /* HSEC Pin 36: ISP1_SCL */ - "", "NC", "NC", "NC", "", ""; -}; - -&gpio12 { - gpio-line-names = "[BT_PCM_XFS]", "[BT_PCM_DI]", - "[BT_PCM_DO]", - "NC", "NC", "NC", "NC", - "GPIO-F"; /* LSEC Pin 28: BL_PWM_GPIO12_7 */ -}; - -&gpio13 { - gpio-line-names = "[UART0_RX]", "[UART0_TX]", - "[BT_UART1_CTS]", "[BT_UART1_RTS]", - "[BT_UART1_RX]", "[BT_UART1_TX]", - "[UART0_CTS]", /* LSEC Pin 3: UART2_CTS_N */ - "[UART0_RTS]"; /* LSEC Pin 9: UART2_RTS_N */ -}; - -&gpio14 { - gpio-line-names = - "[UART0_RxD]", /* LSEC Pin 7: UART2_RX */ - "[UART0_TxD]", /* LSEC Pin 5: UART2_TX */ - "[I2C0_SCL]", /* LSEC Pin 15: I2C0_SCL */ - "[I2C0_SDA]", /* LSEC Pin 17: I2C0_SDA */ - "[I2C1_SCL]", /* LSEC Pin 19: I2C1_SCL */ - "[I2C1_SDA]", /* LSEC Pin 21: I2C1_SDA */ - "[I2C2_SCL]", "[I2C2_SDA]"; -}; - -&gpio15 { - gpio-line-names = "", "", "", "", "", "", "NC", ""; -}; - -/* GPIO blocks 16 thru 19 do not appear to be routed to pins */ - - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - adv7533: adv7533@39 { - compatible = "adi,adv7533"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <1 2>; - pd-gpios = <&gpio0 4 0>; - adi,dsi-lanes = <4>; - #sound-dai-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - adv7533_in: endpoint { - remote-endpoint = <&dsi_out0>; - }; - }; - port@2 { - reg = <2>; - codec_endpoint: endpoint { - remote-endpoint = <&i2s0_cpu_endpoint>; - }; - }; - }; - }; -}; - -&i2s0 { - - ports { - i2s0_port0: port@0 { - i2s0_cpu_endpoint: endpoint { - remote-endpoint = <&codec_endpoint>; - dai-format = "i2s"; - }; - }; - }; -}; - -&spi0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi deleted file mode 100644 index fbce014bd..000000000 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ /dev/null @@ -1,1066 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for Hisilicon Hi6220 SoC - * - * Copyright (C) 2015, Hisilicon Ltd. - */ - -#include -#include -#include -#include -#include - -/ { - compatible = "hisilicon,hi6220"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <700>; - exit-latency-us = <250>; - min-residency-us = <1000>; - }; - - CLUSTER_SLEEP: cluster-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <1000>; - exit-latency-us = <700>; - min-residency-us = <2700>; - wakeup-latency-us = <1500>; - }; - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - clocks = <&stub_clock 0>; - operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <311>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - clocks = <&stub_clock 0>; - operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <311>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - clocks = <&stub_clock 0>; - operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <311>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&CLUSTER0_L2>; - clocks = <&stub_clock 0>; - operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <311>; - }; - - cpu4: cpu@100 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&CLUSTER1_L2>; - clocks = <&stub_clock 0>; - operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <311>; - }; - - cpu5: cpu@101 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x101>; - enable-method = "psci"; - next-level-cache = <&CLUSTER1_L2>; - clocks = <&stub_clock 0>; - operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <311>; - }; - - cpu6: cpu@102 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x102>; - enable-method = "psci"; - next-level-cache = <&CLUSTER1_L2>; - clocks = <&stub_clock 0>; - operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <311>; - }; - - cpu7: cpu@103 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x103>; - enable-method = "psci"; - next-level-cache = <&CLUSTER1_L2>; - clocks = <&stub_clock 0>; - operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - #cooling-cells = <2>; /* min followed by max */ - dynamic-power-coefficient = <311>; - }; - - CLUSTER0_L2: l2-cache0 { - compatible = "cache"; - }; - - CLUSTER1_L2: l2-cache1 { - compatible = "cache"; - }; - }; - - cpu_opp_table: cpu_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <208000000>; - opp-microvolt = <1040000>; - clock-latency-ns = <500000>; - }; - opp01 { - opp-hz = /bits/ 64 <432000000>; - opp-microvolt = <1040000>; - clock-latency-ns = <500000>; - }; - opp02 { - opp-hz = /bits/ 64 <729000000>; - opp-microvolt = <1090000>; - clock-latency-ns = <500000>; - }; - opp03 { - opp-hz = /bits/ 64 <960000000>; - opp-microvolt = <1180000>; - clock-latency-ns = <500000>; - }; - opp04 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1330000>; - clock-latency-ns = <500000>; - }; - }; - - gic: interrupt-controller@f6801000 { - compatible = "arm,gic-400"; - reg = <0x0 0xf6801000 0 0x1000>, /* GICD */ - <0x0 0xf6802000 0 0x2000>, /* GICC */ - <0x0 0xf6804000 0 0x2000>, /* GICH */ - <0x0 0xf6806000 0 0x2000>; /* GICV */ - #address-cells = <0>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - sram: sram@fff80000 { - compatible = "hisilicon,hi6220-sramctrl", "syscon"; - reg = <0x0 0xfff80000 0x0 0x12000>; - }; - - ao_ctrl: ao_ctrl@f7800000 { - compatible = "hisilicon,hi6220-aoctrl", "syscon"; - reg = <0x0 0xf7800000 0x0 0x2000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - sys_ctrl: sys_ctrl@f7030000 { - compatible = "hisilicon,hi6220-sysctrl", "syscon"; - reg = <0x0 0xf7030000 0x0 0x2000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - media_ctrl: media_ctrl@f4410000 { - compatible = "hisilicon,hi6220-mediactrl", "syscon"; - reg = <0x0 0xf4410000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pm_ctrl: pm_ctrl@f7032000 { - compatible = "hisilicon,hi6220-pmctrl", "syscon"; - reg = <0x0 0xf7032000 0x0 0x1000>; - #clock-cells = <1>; - }; - - acpu_sctrl: acpu_sctrl@f6504000 { - compatible = "hisilicon,hi6220-acpu-sctrl", "syscon"; - reg = <0x0 0xf6504000 0x0 0x1000>; - #clock-cells = <1>; - }; - - medianoc_ade: medianoc_ade@f4520000 { - compatible = "syscon"; - reg = <0x0 0xf4520000 0x0 0x4000>; - }; - - stub_clock: stub_clock { - compatible = "hisilicon,hi6220-stub-clk"; - hisilicon,hi6220-clk-sram = <&sram>; - #clock-cells = <1>; - mbox-names = "mbox-tx"; - mboxes = <&mailbox 1 0 11>; - }; - - uart0: serial@f8015000 { /* console */ - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xf8015000 0x0 0x1000>; - interrupts = ; - clocks = <&ao_ctrl HI6220_UART0_PCLK>, - <&ao_ctrl HI6220_UART0_PCLK>; - clock-names = "uartclk", "apb_pclk"; - }; - - uart1: serial@f7111000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xf7111000 0x0 0x1000>; - interrupts = ; - clocks = <&sys_ctrl HI6220_UART1_PCLK>, - <&sys_ctrl HI6220_UART1_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>; - dmas = <&dma0 8 &dma0 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: serial@f7112000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xf7112000 0x0 0x1000>; - interrupts = ; - clocks = <&sys_ctrl HI6220_UART2_PCLK>, - <&sys_ctrl HI6220_UART2_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; - status = "disabled"; - }; - - uart3: serial@f7113000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xf7113000 0x0 0x1000>; - interrupts = ; - clocks = <&sys_ctrl HI6220_UART3_PCLK>, - <&sys_ctrl HI6220_UART3_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; - status = "disabled"; - }; - - uart4: serial@f7114000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xf7114000 0x0 0x1000>; - interrupts = ; - clocks = <&sys_ctrl HI6220_UART4_PCLK>, - <&sys_ctrl HI6220_UART4_PCLK>; - clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; - status = "disabled"; - }; - - dma0: dma@f7370000 { - compatible = "hisilicon,k3-dma-1.0"; - reg = <0x0 0xf7370000 0x0 0x1000>; - #dma-cells = <1>; - dma-channels = <15>; - dma-requests = <32>; - interrupts = <0 84 4>; - clocks = <&sys_ctrl HI6220_EDMAC_ACLK>; - dma-no-cci; - dma-type = "hi6220_dma"; - status = "okay"; - }; - - dual_timer0: timer@f8008000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x0 0xf8008000 0x0 0x1000>; - interrupts = , - ; - clocks = <&ao_ctrl HI6220_TIMER0_PCLK>, - <&ao_ctrl HI6220_TIMER0_PCLK>, - <&ao_ctrl HI6220_TIMER0_PCLK>; - clock-names = "timer1", "timer2", "apb_pclk"; - }; - - rtc0: rtc@f8003000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x0 0xf8003000 0x0 0x1000>; - interrupts = <0 12 4>; - clocks = <&ao_ctrl HI6220_RTC0_PCLK>; - clock-names = "apb_pclk"; - }; - - rtc1: rtc@f8004000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x0 0xf8004000 0x0 0x1000>; - interrupts = <0 8 4>; - clocks = <&ao_ctrl HI6220_RTC1_PCLK>; - clock-names = "apb_pclk"; - }; - - pmx0: pinmux@f7010000 { - compatible = "pinctrl-single"; - reg = <0x0 0xf7010000 0x0 0x27c>; - #address-cells = <1>; - #size-cells = <1>; - #pinctrl-cells = <1>; - #gpio-range-cells = <3>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <7>; - pinctrl-single,gpio-range = < - &range 80 8 MUX_M0 /* gpio 3: [0..7] */ - &range 88 8 MUX_M0 /* gpio 4: [0..7] */ - &range 96 8 MUX_M0 /* gpio 5: [0..7] */ - &range 104 8 MUX_M0 /* gpio 6: [0..7] */ - &range 112 8 MUX_M0 /* gpio 7: [0..7] */ - &range 120 2 MUX_M0 /* gpio 8: [0..1] */ - &range 2 6 MUX_M1 /* gpio 8: [2..7] */ - &range 8 8 MUX_M1 /* gpio 9: [0..7] */ - &range 0 1 MUX_M1 /* gpio 10: [0] */ - &range 16 7 MUX_M1 /* gpio 10: [1..7] */ - &range 23 3 MUX_M1 /* gpio 11: [0..2] */ - &range 28 5 MUX_M1 /* gpio 11: [3..7] */ - &range 33 3 MUX_M1 /* gpio 12: [0..2] */ - &range 43 5 MUX_M1 /* gpio 12: [3..7] */ - &range 48 8 MUX_M1 /* gpio 13: [0..7] */ - &range 56 8 MUX_M1 /* gpio 14: [0..7] */ - &range 74 6 MUX_M1 /* gpio 15: [0..5] */ - &range 122 1 MUX_M1 /* gpio 15: [6] */ - &range 126 1 MUX_M1 /* gpio 15: [7] */ - &range 127 8 MUX_M1 /* gpio 16: [0..7] */ - &range 135 8 MUX_M1 /* gpio 17: [0..7] */ - &range 143 8 MUX_M1 /* gpio 18: [0..7] */ - &range 151 8 MUX_M1 /* gpio 19: [0..7] */ - >; - range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; - }; - - pmx1: pinmux@f7010800 { - compatible = "pinconf-single"; - reg = <0x0 0xf7010800 0x0 0x28c>; - #address-cells = <1>; - #size-cells = <1>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - }; - - pmx2: pinmux@f8001800 { - compatible = "pinconf-single"; - reg = <0x0 0xf8001800 0x0 0x78>; - #address-cells = <1>; - #size-cells = <1>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - }; - - gpio0: gpio@f8011000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf8011000 0x0 0x1000>; - interrupts = <0 52 0x4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio1: gpio@f8012000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf8012000 0x0 0x1000>; - interrupts = <0 53 0x4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio2: gpio@f8013000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf8013000 0x0 0x1000>; - interrupts = <0 54 0x4>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio3: gpio@f8014000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf8014000 0x0 0x1000>; - interrupts = <0 55 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 80 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio4: gpio@f7020000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf7020000 0x0 0x1000>; - interrupts = <0 56 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 88 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio5: gpio@f7021000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf7021000 0x0 0x1000>; - interrupts = <0 57 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 96 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio6: gpio@f7022000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf7022000 0x0 0x1000>; - interrupts = <0 58 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 104 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio7: gpio@f7023000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf7023000 0x0 0x1000>; - interrupts = <0 59 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 112 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio8: gpio@f7024000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf7024000 0x0 0x1000>; - interrupts = <0 60 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio9: gpio@f7025000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf7025000 0x0 0x1000>; - interrupts = <0 61 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 8 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio10: gpio@f7026000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf7026000 0x0 0x1000>; - interrupts = <0 62 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio11: gpio@f7027000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf7027000 0x0 0x1000>; - interrupts = <0 63 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio12: gpio@f7028000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf7028000 0x0 0x1000>; - interrupts = <0 64 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio13: gpio@f7029000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf7029000 0x0 0x1000>; - interrupts = <0 65 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 48 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio14: gpio@f702a000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf702a000 0x0 0x1000>; - interrupts = <0 66 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 56 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio15: gpio@f702b000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf702b000 0x0 0x1000>; - interrupts = <0 67 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = < - &pmx0 0 74 6 - &pmx0 6 122 1 - &pmx0 7 126 1 - >; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio16: gpio@f702c000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf702c000 0x0 0x1000>; - interrupts = <0 68 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 127 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio17: gpio@f702d000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf702d000 0x0 0x1000>; - interrupts = <0 69 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 135 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio18: gpio@f702e000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf702e000 0x0 0x1000>; - interrupts = <0 70 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 143 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - gpio19: gpio@f702f000 { - compatible = "arm,pl061", "arm,primecell"; - reg = <0x0 0xf702f000 0x0 0x1000>; - interrupts = <0 71 0x4>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmx0 0 151 8>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&ao_ctrl 2>; - clock-names = "apb_pclk"; - }; - - spi0: spi@f7106000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x0 0xf7106000 0x0 0x1000>; - interrupts = <0 50 4>; - bus-id = <0>; - enable-dma = <0>; - clocks = <&sys_ctrl HI6220_SPI_CLK>; - clock-names = "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>; - num-cs = <1>; - cs-gpios = <&gpio6 2 0>; - status = "disabled"; - }; - - i2c0: i2c@f7100000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0xf7100000 0x0 0x1000>; - interrupts = <0 44 4>; - clocks = <&sys_ctrl HI6220_I2C0_CLK>; - i2c-sda-hold-time-ns = <300>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; - status = "disabled"; - }; - - i2c1: i2c@f7101000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0xf7101000 0x0 0x1000>; - clocks = <&sys_ctrl HI6220_I2C1_CLK>; - interrupts = <0 45 4>; - i2c-sda-hold-time-ns = <300>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; - status = "disabled"; - }; - - i2c2: i2c@f7102000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0xf7102000 0x0 0x1000>; - clocks = <&sys_ctrl HI6220_I2C2_CLK>; - interrupts = <0 46 4>; - i2c-sda-hold-time-ns = <300>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; - status = "disabled"; - }; - - usb_phy: usbphy { - compatible = "hisilicon,hi6220-usb-phy"; - #phy-cells = <0>; - phy-supply = <®_5v_hub>; - hisilicon,peripheral-syscon = <&sys_ctrl>; - }; - - usb: usb@f72c0000 { - compatible = "hisilicon,hi6220-usb"; - reg = <0x0 0xf72c0000 0x0 0x40000>; - phys = <&usb_phy>; - phy-names = "usb2-phy"; - clocks = <&sys_ctrl HI6220_USBOTG_HCLK>; - clock-names = "otg"; - dr_mode = "otg"; - g-rx-fifo-size = <512>; - g-np-tx-fifo-size = <128>; - g-tx-fifo-size = <128 128 128 128 128 128 128 128 - 16 16 16 16 16 16 16>; - interrupts = <0 77 0x4>; - }; - - mailbox: mailbox@f7510000 { - compatible = "hisilicon,hi6220-mbox"; - reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */ - <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */ - interrupts = ; - #mbox-cells = <3>; - }; - - dwmmc_0: dwmmc0@f723d000 { - compatible = "hisilicon,hi6220-dw-mshc"; - reg = <0x0 0xf723d000 0x0 0x1000>; - interrupts = <0x0 0x48 0x4>; - clocks = <&sys_ctrl 2>, <&sys_ctrl 1>; - clock-names = "ciu", "biu"; - resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>; - reset-names = "reset"; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func - &emmc_cfg_func &emmc_rst_cfg_func>; - }; - - dwmmc_1: dwmmc1@f723e000 { - compatible = "hisilicon,hi6220-dw-mshc"; - hisilicon,peripheral-syscon = <&ao_ctrl>; - reg = <0x0 0xf723e000 0x0 0x1000>; - interrupts = <0x0 0x49 0x4>; - #address-cells = <0x1>; - #size-cells = <0x0>; - clocks = <&sys_ctrl 4>, <&sys_ctrl 3>; - clock-names = "ciu", "biu"; - resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>; - reset-names = "reset"; - pinctrl-names = "default", "idle"; - pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>; - pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>; - }; - - dwmmc_2: dwmmc2@f723f000 { - compatible = "hisilicon,hi6220-dw-mshc"; - reg = <0x0 0xf723f000 0x0 0x1000>; - interrupts = <0x0 0x4a 0x4>; - clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>; - clock-names = "ciu", "biu"; - resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>; - reset-names = "reset"; - pinctrl-names = "default", "idle"; - pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>; - pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>; - }; - - watchdog0: watchdog@f8005000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xf8005000 0x0 0x1000>; - interrupts = ; - clocks = <&ao_ctrl HI6220_WDT0_PCLK>, - <&ao_ctrl HI6220_WDT0_PCLK>; - clock-names = "wdog_clk", "apb_pclk"; - }; - - tsensor: tsensor@0,f7030700 { - compatible = "hisilicon,tsensor"; - reg = <0x0 0xf7030700 0x0 0x1000>; - interrupts = ; - clocks = <&sys_ctrl 22>; - clock-names = "thermal_clk"; - #thermal-sensor-cells = <1>; - }; - - i2s0: i2s@f7118000{ - compatible = "hisilicon,hi6210-i2s"; - reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */ - interrupts = ; /* 155 "DigACodec_intr"-32 */ - clocks = <&sys_ctrl HI6220_DACODEC_PCLK>, - <&sys_ctrl HI6220_BBPPLL0_DIV>; - clock-names = "dacodec", "i2s-base"; - dmas = <&dma0 15 &dma0 14>; - dma-names = "rx", "tx"; - hisilicon,sysctrl-syscon = <&sys_ctrl>; - #sound-dai-cells = <1>; - }; - - thermal-zones { - - cls0: cls0 { - polling-delay = <1000>; - polling-delay-passive = <100>; - sustainable-power = <3326>; - - /* sensor ID */ - thermal-sensors = <&tsensor 2>; - - trips { - threshold: trip-point@0 { - temperature = <65000>; - hysteresis = <0>; - type = "passive"; - }; - - target: trip-point@1 { - temperature = <75000>; - hysteresis = <0>; - type = "passive"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - ade: ade@f4100000 { - compatible = "hisilicon,hi6220-ade"; - reg = <0x0 0xf4100000 0x0 0x7800>; - reg-names = "ade_base"; - hisilicon,noc-syscon = <&medianoc_ade>; - resets = <&media_ctrl MEDIA_ADE>; - interrupts = <0 115 4>; /* ldi interrupt */ - - clocks = <&media_ctrl HI6220_ADE_CORE>, - <&media_ctrl HI6220_CODEC_JPEG>, - <&media_ctrl HI6220_ADE_PIX_SRC>; - /*clock name*/ - clock-names = "clk_ade_core", - "clk_codec_jpeg", - "clk_ade_pix"; - - assigned-clocks = <&media_ctrl HI6220_ADE_CORE>, - <&media_ctrl HI6220_CODEC_JPEG>; - assigned-clock-rates = <360000000>, <288000000>; - dma-coherent; - status = "disabled"; - - port { - ade_out: endpoint { - remote-endpoint = <&dsi_in>; - }; - }; - }; - - dsi: dsi@f4107800 { - compatible = "hisilicon,hi6220-dsi"; - reg = <0x0 0xf4107800 0x0 0x100>; - clocks = <&media_ctrl HI6220_DSI_PCLK>; - clock-names = "pclk"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* 0 for input port */ - port@0 { - reg = <0>; - dsi_in: endpoint { - remote-endpoint = <&ade_out>; - }; - }; - }; - }; - - debug@f6590000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0 0xf6590000 0 0x1000>; - clocks = <&sys_ctrl HI6220_DAPB_CLK>; - clock-names = "apb_pclk"; - cpu = <&cpu0>; - }; - - debug@f6592000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0 0xf6592000 0 0x1000>; - clocks = <&sys_ctrl HI6220_DAPB_CLK>; - clock-names = "apb_pclk"; - cpu = <&cpu1>; - }; - - debug@f6594000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0 0xf6594000 0 0x1000>; - clocks = <&sys_ctrl HI6220_DAPB_CLK>; - clock-names = "apb_pclk"; - cpu = <&cpu2>; - }; - - debug@f6596000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0 0xf6596000 0 0x1000>; - clocks = <&sys_ctrl HI6220_DAPB_CLK>; - clock-names = "apb_pclk"; - cpu = <&cpu3>; - }; - - debug@f65d0000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0 0xf65d0000 0 0x1000>; - clocks = <&sys_ctrl HI6220_DAPB_CLK>; - clock-names = "apb_pclk"; - cpu = <&cpu4>; - }; - - debug@f65d2000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0 0xf65d2000 0 0x1000>; - clocks = <&sys_ctrl HI6220_DAPB_CLK>; - clock-names = "apb_pclk"; - cpu = <&cpu5>; - }; - - debug@f65d4000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0 0xf65d4000 0 0x1000>; - clocks = <&sys_ctrl HI6220_DAPB_CLK>; - clock-names = "apb_pclk"; - cpu = <&cpu6>; - }; - - debug@f65d6000 { - compatible = "arm,coresight-cpu-debug","arm,primecell"; - reg = <0 0xf65d6000 0 0x1000>; - clocks = <&sys_ctrl HI6220_DAPB_CLK>; - clock-names = "apb_pclk"; - cpu = <&cpu7>; - }; - - mali: gpu@f4080000 { - compatible = "hisilicon,hi6220-mali", "arm,mali-450"; - reg = <0x0 0xf4080000 0x0 0x00040000>; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - , - , - , - ; - - interrupt-names = "gp", - "gpmmu", - "pp", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pp2", - "ppmmu2", - "pp3", - "ppmmu3"; - clocks = <&media_ctrl HI6220_G3D_CLK>, - <&media_ctrl HI6220_G3D_PCLK>; - clock-names = "core", "bus"; - assigned-clocks = <&media_ctrl HI6220_G3D_CLK>, - <&media_ctrl HI6220_G3D_PCLK>; - assigned-clock-rates = <500000000>, <144000000>; - reset-names = "ao_g3d", "media_g3d"; - resets = <&ao_ctrl AO_G3D>, <&media_ctrl MEDIA_G3D>; - }; - }; -}; - -#include "hi6220-coresight.dtsi" diff --git a/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi deleted file mode 100644 index e7d22619a..000000000 --- a/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi +++ /dev/null @@ -1,706 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * pinctrl dts fils for Hislicon HiKey development board - * - */ -#include - -/ { - soc { - pmx0: pinmux@f7010000 { - pinctrl-names = "default"; - pinctrl-0 = < - &boot_sel_pmx_func - &hkadc_ssi_pmx_func - &codec_clk_pmx_func - &pwm_in_pmx_func - &bl_pwm_pmx_func - >; - - boot_sel_pmx_func: boot_sel_pmx_func { - pinctrl-single,pins = < - 0x0 MUX_M0 /* BOOT_SEL (IOMG000) */ - >; - }; - - emmc_pmx_func: emmc_pmx_func { - pinctrl-single,pins = < - 0x100 MUX_M0 /* EMMC_CLK (IOMG064) */ - 0x104 MUX_M0 /* EMMC_CMD (IOMG065) */ - 0x108 MUX_M0 /* EMMC_DATA0 (IOMG066) */ - 0x10c MUX_M0 /* EMMC_DATA1 (IOMG067) */ - 0x110 MUX_M0 /* EMMC_DATA2 (IOMG068) */ - 0x114 MUX_M0 /* EMMC_DATA3 (IOMG069) */ - 0x118 MUX_M0 /* EMMC_DATA4 (IOMG070) */ - 0x11c MUX_M0 /* EMMC_DATA5 (IOMG071) */ - 0x120 MUX_M0 /* EMMC_DATA6 (IOMG072) */ - 0x124 MUX_M0 /* EMMC_DATA7 (IOMG073) */ - >; - }; - - sd_pmx_func: sd_pmx_func { - pinctrl-single,pins = < - 0xc MUX_M0 /* SD_CLK (IOMG003) */ - 0x10 MUX_M0 /* SD_CMD (IOMG004) */ - 0x14 MUX_M0 /* SD_DATA0 (IOMG005) */ - 0x18 MUX_M0 /* SD_DATA1 (IOMG006) */ - 0x1c MUX_M0 /* SD_DATA2 (IOMG007) */ - 0x20 MUX_M0 /* SD_DATA3 (IOMG008) */ - >; - }; - sd_pmx_idle: sd_pmx_idle { - pinctrl-single,pins = < - 0xc MUX_M1 /* SD_CLK (IOMG003) */ - 0x10 MUX_M1 /* SD_CMD (IOMG004) */ - 0x14 MUX_M1 /* SD_DATA0 (IOMG005) */ - 0x18 MUX_M1 /* SD_DATA1 (IOMG006) */ - 0x1c MUX_M1 /* SD_DATA2 (IOMG007) */ - 0x20 MUX_M1 /* SD_DATA3 (IOMG008) */ - >; - }; - - sdio_pmx_func: sdio_pmx_func { - pinctrl-single,pins = < - 0x128 MUX_M0 /* SDIO_CLK (IOMG074) */ - 0x12c MUX_M0 /* SDIO_CMD (IOMG075) */ - 0x130 MUX_M0 /* SDIO_DATA0 (IOMG076) */ - 0x134 MUX_M0 /* SDIO_DATA1 (IOMG077) */ - 0x138 MUX_M0 /* SDIO_DATA2 (IOMG078) */ - 0x13c MUX_M0 /* SDIO_DATA3 (IOMG079) */ - >; - }; - sdio_pmx_idle: sdio_pmx_idle { - pinctrl-single,pins = < - 0x128 MUX_M1 /* SDIO_CLK (IOMG074) */ - 0x12c MUX_M1 /* SDIO_CMD (IOMG075) */ - 0x130 MUX_M1 /* SDIO_DATA0 (IOMG076) */ - 0x134 MUX_M1 /* SDIO_DATA1 (IOMG077) */ - 0x138 MUX_M1 /* SDIO_DATA2 (IOMG078) */ - 0x13c MUX_M1 /* SDIO_DATA3 (IOMG079) */ - >; - }; - - isp_pmx_func: isp_pmx_func { - pinctrl-single,pins = < - 0x24 MUX_M0 /* ISP_PWDN0 (IOMG009) */ - 0x28 MUX_M0 /* ISP_PWDN1 (IOMG010) */ - 0x2c MUX_M0 /* ISP_PWDN2 (IOMG011) */ - 0x30 MUX_M1 /* ISP_SHUTTER0 (IOMG012) */ - 0x34 MUX_M1 /* ISP_SHUTTER1 (IOMG013) */ - 0x38 MUX_M1 /* ISP_PWM (IOMG014) */ - 0x3c MUX_M0 /* ISP_CCLK0 (IOMG015) */ - 0x40 MUX_M0 /* ISP_CCLK1 (IOMG016) */ - 0x44 MUX_M0 /* ISP_RESETB0 (IOMG017) */ - 0x48 MUX_M0 /* ISP_RESETB1 (IOMG018) */ - 0x4c MUX_M1 /* ISP_STROBE0 (IOMG019) */ - 0x50 MUX_M1 /* ISP_STROBE1 (IOMG020) */ - 0x54 MUX_M0 /* ISP_SDA0 (IOMG021) */ - 0x58 MUX_M0 /* ISP_SCL0 (IOMG022) */ - 0x5c MUX_M0 /* ISP_SDA1 (IOMG023) */ - 0x60 MUX_M0 /* ISP_SCL1 (IOMG024) */ - >; - }; - - hkadc_ssi_pmx_func: hkadc_ssi_pmx_func { - pinctrl-single,pins = < - 0x68 MUX_M0 /* HKADC_SSI (IOMG026) */ - >; - }; - - codec_clk_pmx_func: codec_clk_pmx_func { - pinctrl-single,pins = < - 0x6c MUX_M0 /* CODEC_CLK (IOMG027) */ - >; - }; - - codec_pmx_func: codec_pmx_func { - pinctrl-single,pins = < - 0x70 MUX_M1 /* DMIC_CLK (IOMG028) */ - 0x74 MUX_M0 /* CODEC_SYNC (IOMG029) */ - 0x78 MUX_M0 /* CODEC_DI (IOMG030) */ - 0x7c MUX_M0 /* CODEC_DO (IOMG031) */ - >; - }; - - fm_pmx_func: fm_pmx_func { - pinctrl-single,pins = < - 0x80 MUX_M1 /* FM_XCLK (IOMG032) */ - 0x84 MUX_M1 /* FM_XFS (IOMG033) */ - 0x88 MUX_M1 /* FM_DI (IOMG034) */ - 0x8c MUX_M1 /* FM_DO (IOMG035) */ - >; - }; - - bt_pmx_func: bt_pmx_func { - pinctrl-single,pins = < - 0x90 MUX_M0 /* BT_XCLK (IOMG036) */ - 0x94 MUX_M0 /* BT_XFS (IOMG037) */ - 0x98 MUX_M0 /* BT_DI (IOMG038) */ - 0x9c MUX_M0 /* BT_DO (IOMG039) */ - >; - }; - - pwm_in_pmx_func: pwm_in_pmx_func { - pinctrl-single,pins = < - 0xb8 MUX_M1 /* PWM_IN (IOMG046) */ - >; - }; - - bl_pwm_pmx_func: bl_pwm_pmx_func { - pinctrl-single,pins = < - 0xbc MUX_M1 /* BL_PWM (IOMG047) */ - >; - }; - - uart0_pmx_func: uart0_pmx_func { - pinctrl-single,pins = < - 0xc0 MUX_M0 /* UART0_RXD (IOMG048) */ - 0xc4 MUX_M0 /* UART0_TXD (IOMG049) */ - >; - }; - - uart1_pmx_func: uart1_pmx_func { - pinctrl-single,pins = < - 0xc8 MUX_M0 /* UART1_CTS_N (IOMG050) */ - 0xcc MUX_M0 /* UART1_RTS_N (IOMG051) */ - 0xd0 MUX_M0 /* UART1_RXD (IOMG052) */ - 0xd4 MUX_M0 /* UART1_TXD (IOMG053) */ - >; - }; - - uart2_pmx_func: uart2_pmx_func { - pinctrl-single,pins = < - 0xd8 MUX_M0 /* UART2_CTS_N (IOMG054) */ - 0xdc MUX_M0 /* UART2_RTS_N (IOMG055) */ - 0xe0 MUX_M0 /* UART2_RXD (IOMG056) */ - 0xe4 MUX_M0 /* UART2_TXD (IOMG057) */ - >; - }; - - uart3_pmx_func: uart3_pmx_func { - pinctrl-single,pins = < - 0x180 MUX_M1 /* UART3_CTS_N (IOMG096) */ - 0x184 MUX_M1 /* UART3_RTS_N (IOMG097) */ - 0x188 MUX_M1 /* UART3_RXD (IOMG098) */ - 0x18c MUX_M1 /* UART3_TXD (IOMG099) */ - >; - }; - - uart4_pmx_func: uart4_pmx_func { - pinctrl-single,pins = < - 0x1d0 MUX_M1 /* UART4_CTS_N (IOMG116) */ - 0x1d4 MUX_M1 /* UART4_RTS_N (IOMG117) */ - 0x1d8 MUX_M1 /* UART4_RXD (IOMG118) */ - 0x1dc MUX_M1 /* UART4_TXD (IOMG119) */ - >; - }; - - uart5_pmx_func: uart5_pmx_func { - pinctrl-single,pins = < - 0x1c8 MUX_M1 /* UART5_RXD (IOMG114) */ - 0x1cc MUX_M1 /* UART5_TXD (IOMG115) */ - >; - }; - - i2c0_pmx_func: i2c0_pmx_func { - pinctrl-single,pins = < - 0xe8 MUX_M0 /* I2C0_SCL (IOMG058) */ - 0xec MUX_M0 /* I2C0_SDA (IOMG059) */ - >; - }; - - i2c1_pmx_func: i2c1_pmx_func { - pinctrl-single,pins = < - 0xf0 MUX_M0 /* I2C1_SCL (IOMG060) */ - 0xf4 MUX_M0 /* I2C1_SDA (IOMG061) */ - >; - }; - - i2c2_pmx_func: i2c2_pmx_func { - pinctrl-single,pins = < - 0xf8 MUX_M0 /* I2C2_SCL (IOMG062) */ - 0xfc MUX_M0 /* I2C2_SDA (IOMG063) */ - >; - }; - - spi0_pmx_func: spi0_pmx_func { - pinctrl-single,pins = < - 0x1a0 MUX_M1 /* SPI0_DI (IOMG104) */ - 0x1a4 MUX_M1 /* SPI0_DO (IOMG105) */ - 0x1a8 MUX_M1 /* SPI0_CS_N (IOMG106) */ - 0x1ac MUX_M1 /* SPI0_CLK (IOMG107) */ - >; - }; - }; - - pmx1: pinmux@f7010800 { - - pinctrl-names = "default"; - pinctrl-0 = < - &boot_sel_cfg_func - &hkadc_ssi_cfg_func - &codec_clk_cfg_func - &pwm_in_cfg_func - &bl_pwm_cfg_func - >; - - boot_sel_cfg_func: boot_sel_cfg_func { - pinctrl-single,pins = < - 0x0 0x0 /* BOOT_SEL (IOCFG000) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - hkadc_ssi_cfg_func: hkadc_ssi_cfg_func { - pinctrl-single,pins = < - 0x6c 0x0 /* HKADC_SSI (IOCFG027) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - emmc_clk_cfg_func: emmc_clk_cfg_func { - pinctrl-single,pins = < - 0x104 0x0 /* EMMC_CLK (IOCFG065) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - emmc_cfg_func: emmc_cfg_func { - pinctrl-single,pins = < - 0x108 0x0 /* EMMC_CMD (IOCFG066) */ - 0x10c 0x0 /* EMMC_DATA0 (IOCFG067) */ - 0x110 0x0 /* EMMC_DATA1 (IOCFG068) */ - 0x114 0x0 /* EMMC_DATA2 (IOCFG069) */ - 0x118 0x0 /* EMMC_DATA3 (IOCFG070) */ - 0x11c 0x0 /* EMMC_DATA4 (IOCFG071) */ - 0x120 0x0 /* EMMC_DATA5 (IOCFG072) */ - 0x124 0x0 /* EMMC_DATA6 (IOCFG073) */ - 0x128 0x0 /* EMMC_DATA7 (IOCFG074) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - emmc_rst_cfg_func: emmc_rst_cfg_func { - pinctrl-single,pins = < - 0x12c 0x0 /* EMMC_RST_N (IOCFG075) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - sd_clk_cfg_func: sd_clk_cfg_func { - pinctrl-single,pins = < - 0xc 0x0 /* SD_CLK (IOCFG003) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - sd_clk_cfg_idle: sd_clk_cfg_idle { - pinctrl-single,pins = < - 0xc 0x0 /* SD_CLK (IOCFG003) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - sd_cfg_func: sd_cfg_func { - pinctrl-single,pins = < - 0x10 0x0 /* SD_CMD (IOCFG004) */ - 0x14 0x0 /* SD_DATA0 (IOCFG005) */ - 0x18 0x0 /* SD_DATA1 (IOCFG006) */ - 0x1c 0x0 /* SD_DATA2 (IOCFG007) */ - 0x20 0x0 /* SD_DATA3 (IOCFG008) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - sd_cfg_idle: sd_cfg_idle { - pinctrl-single,pins = < - 0x10 0x0 /* SD_CMD (IOCFG004) */ - 0x14 0x0 /* SD_DATA0 (IOCFG005) */ - 0x18 0x0 /* SD_DATA1 (IOCFG006) */ - 0x1c 0x0 /* SD_DATA2 (IOCFG007) */ - 0x20 0x0 /* SD_DATA3 (IOCFG008) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - sdio_clk_cfg_func: sdio_clk_cfg_func { - pinctrl-single,pins = < - 0x134 0x0 /* SDIO_CLK (IOCFG077) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - sdio_clk_cfg_idle: sdio_clk_cfg_idle { - pinctrl-single,pins = < - 0x134 0x0 /* SDIO_CLK (IOCFG077) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - sdio_cfg_func: sdio_cfg_func { - pinctrl-single,pins = < - 0x138 0x0 /* SDIO_CMD (IOCFG078) */ - 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */ - 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */ - 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */ - 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - sdio_cfg_idle: sdio_cfg_idle { - pinctrl-single,pins = < - 0x138 0x0 /* SDIO_CMD (IOCFG078) */ - 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */ - 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */ - 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */ - 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - isp_cfg_func1: isp_cfg_func1 { - pinctrl-single,pins = < - 0x28 0x0 /* ISP_PWDN0 (IOCFG010) */ - 0x2c 0x0 /* ISP_PWDN1 (IOCFG011) */ - 0x30 0x0 /* ISP_PWDN2 (IOCFG012) */ - 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */ - 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */ - 0x3c 0x0 /* ISP_PWM (IOCFG015) */ - 0x40 0x0 /* ISP_CCLK0 (IOCFG016) */ - 0x44 0x0 /* ISP_CCLK1 (IOCFG017) */ - 0x48 0x0 /* ISP_RESETB0 (IOCFG018) */ - 0x4c 0x0 /* ISP_RESETB1 (IOCFG019) */ - 0x50 0x0 /* ISP_STROBE0 (IOCFG020) */ - 0x58 0x0 /* ISP_SDA0 (IOCFG022) */ - 0x5c 0x0 /* ISP_SCL0 (IOCFG023) */ - 0x60 0x0 /* ISP_SDA1 (IOCFG024) */ - 0x64 0x0 /* ISP_SCL1 (IOCFG025) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - isp_cfg_idle1: isp_cfg_idle1 { - pinctrl-single,pins = < - 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */ - 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - isp_cfg_func2: isp_cfg_func2 { - pinctrl-single,pins = < - 0x54 0x0 /* ISP_STROBE1 (IOCFG021) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - codec_clk_cfg_func: codec_clk_cfg_func { - pinctrl-single,pins = < - 0x70 0x0 /* CODEC_CLK (IOCFG028) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - codec_clk_cfg_idle: codec_clk_cfg_idle { - pinctrl-single,pins = < - 0x70 0x0 /* CODEC_CLK (IOCFG028) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - codec_cfg_func1: codec_cfg_func1 { - pinctrl-single,pins = < - 0x74 0x0 /* DMIC_CLK (IOCFG029) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - codec_cfg_func2: codec_cfg_func2 { - pinctrl-single,pins = < - 0x78 0x0 /* CODEC_SYNC (IOCFG030) */ - 0x7c 0x0 /* CODEC_DI (IOCFG031) */ - 0x80 0x0 /* CODEC_DO (IOCFG032) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - codec_cfg_idle2: codec_cfg_idle2 { - pinctrl-single,pins = < - 0x78 0x0 /* CODEC_SYNC (IOCFG030) */ - 0x7c 0x0 /* CODEC_DI (IOCFG031) */ - 0x80 0x0 /* CODEC_DO (IOCFG032) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - fm_cfg_func: fm_cfg_func { - pinctrl-single,pins = < - 0x84 0x0 /* FM_XCLK (IOCFG033) */ - 0x88 0x0 /* FM_XFS (IOCFG034) */ - 0x8c 0x0 /* FM_DI (IOCFG035) */ - 0x90 0x0 /* FM_DO (IOCFG036) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - bt_cfg_func: bt_cfg_func { - pinctrl-single,pins = < - 0x94 0x0 /* BT_XCLK (IOCFG037) */ - 0x98 0x0 /* BT_XFS (IOCFG038) */ - 0x9c 0x0 /* BT_DI (IOCFG039) */ - 0xa0 0x0 /* BT_DO (IOCFG040) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - bt_cfg_idle: bt_cfg_idle { - pinctrl-single,pins = < - 0x94 0x0 /* BT_XCLK (IOCFG037) */ - 0x98 0x0 /* BT_XFS (IOCFG038) */ - 0x9c 0x0 /* BT_DI (IOCFG039) */ - 0xa0 0x0 /* BT_DO (IOCFG040) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - pwm_in_cfg_func: pwm_in_cfg_func { - pinctrl-single,pins = < - 0xbc 0x0 /* PWM_IN (IOCFG047) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - bl_pwm_cfg_func: bl_pwm_cfg_func { - pinctrl-single,pins = < - 0xc0 0x0 /* BL_PWM (IOCFG048) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - uart0_cfg_func1: uart0_cfg_func1 { - pinctrl-single,pins = < - 0xc4 0x0 /* UART0_RXD (IOCFG049) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - uart0_cfg_func2: uart0_cfg_func2 { - pinctrl-single,pins = < - 0xc8 0x0 /* UART0_TXD (IOCFG050) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - uart1_cfg_func1: uart1_cfg_func1 { - pinctrl-single,pins = < - 0xcc 0x0 /* UART1_CTS_N (IOCFG051) */ - 0xd4 0x0 /* UART1_RXD (IOCFG053) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - uart1_cfg_func2: uart1_cfg_func2 { - pinctrl-single,pins = < - 0xd0 0x0 /* UART1_RTS_N (IOCFG052) */ - 0xd8 0x0 /* UART1_TXD (IOCFG054) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - uart2_cfg_func: uart2_cfg_func { - pinctrl-single,pins = < - 0xdc 0x0 /* UART2_CTS_N (IOCFG055) */ - 0xe0 0x0 /* UART2_RTS_N (IOCFG056) */ - 0xe4 0x0 /* UART2_RXD (IOCFG057) */ - 0xe8 0x0 /* UART2_TXD (IOCFG058) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - uart3_cfg_func: uart3_cfg_func { - pinctrl-single,pins = < - 0x190 0x0 /* UART3_CTS_N (IOCFG100) */ - 0x194 0x0 /* UART3_RTS_N (IOCFG101) */ - 0x198 0x0 /* UART3_RXD (IOCFG102) */ - 0x19c 0x0 /* UART3_TXD (IOCFG103) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - uart4_cfg_func: uart4_cfg_func { - pinctrl-single,pins = < - 0x1e0 0x0 /* UART4_CTS_N (IOCFG120) */ - 0x1e4 0x0 /* UART4_RTS_N (IOCFG121) */ - 0x1e8 0x0 /* UART4_RXD (IOCFG122) */ - 0x1ec 0x0 /* UART4_TXD (IOCFG123) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - uart5_cfg_func: uart5_cfg_func { - pinctrl-single,pins = < - 0x1d8 0x0 /* UART4_RXD (IOCFG118) */ - 0x1dc 0x0 /* UART4_TXD (IOCFG119) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - i2c0_cfg_func: i2c0_cfg_func { - pinctrl-single,pins = < - 0xec 0x0 /* I2C0_SCL (IOCFG059) */ - 0xf0 0x0 /* I2C0_SDA (IOCFG060) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - i2c1_cfg_func: i2c1_cfg_func { - pinctrl-single,pins = < - 0xf4 0x0 /* I2C1_SCL (IOCFG061) */ - 0xf8 0x0 /* I2C1_SDA (IOCFG062) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - i2c2_cfg_func: i2c2_cfg_func { - pinctrl-single,pins = < - 0xfc 0x0 /* I2C2_SCL (IOCFG063) */ - 0x100 0x0 /* I2C2_SDA (IOCFG064) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - spi0_cfg_func: spi0_cfg_func { - pinctrl-single,pins = < - 0x1b0 0x0 /* SPI0_DI (IOCFG108) */ - 0x1b4 0x0 /* SPI0_DO (IOCFG109) */ - 0x1b8 0x0 /* SPI0_CS_N (IOCFG110) */ - 0x1bc 0x0 /* SPI0_CLK (IOCFG111) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - }; - - pmx2: pinmux@f8001800 { - - pinctrl-names = "default"; - pinctrl-0 = < - &rstout_n_cfg_func - >; - - rstout_n_cfg_func: rstout_n_cfg_func { - pinctrl-single,pins = < - 0x0 0x0 /* RSTOUT_N (IOCFG000) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - pmu_peri_en_cfg_func: pmu_peri_en_cfg_func { - pinctrl-single,pins = < - 0x4 0x0 /* PMU_PERI_EN (IOCFG001) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - sysclk0_en_cfg_func: sysclk0_en_cfg_func { - pinctrl-single,pins = < - 0x8 0x0 /* SYSCLK0_EN (IOCFG002) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - jtag_tdo_cfg_func: jtag_tdo_cfg_func { - pinctrl-single,pins = < - 0xc 0x0 /* JTAG_TDO (IOCFG003) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - - rf_reset_cfg_func: rf_reset_cfg_func { - pinctrl-single,pins = < - 0x70 0x0 /* RF_RESET0 (IOCFG028) */ - 0x74 0x0 /* RF_RESET1 (IOCFG029) */ - >; - pinctrl-single,bias-pulldown = ; - pinctrl-single,bias-pullup = ; - pinctrl-single,drive-strength = ; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi deleted file mode 100644 index 920a3111c..000000000 --- a/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi +++ /dev/null @@ -1,1060 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * pinctrl dts fils for Hislicon HiKey960 development board - * - */ - -#include - -/ { - soc { - /* [IOMG_000, IOMG_123] */ - range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; - - pmx0: pinmux@e896c000 { - compatible = "pinctrl-single"; - reg = <0x0 0xe896c000 0x0 0x1f0>; - #pinctrl-cells = <1>; - #gpio-range-cells = <0x3>; - pinctrl-single,register-width = <0x20>; - pinctrl-single,function-mask = <0x7>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = < - &range 0 7 0 - &range 8 116 0>; - - pmu_pmx_func: pmu_pmx_func { - pinctrl-single,pins = < - 0x008 MUX_M1 /* PMU1_SSI */ - 0x00c MUX_M1 /* PMU2_SSI */ - 0x010 MUX_M1 /* PMU_CLKOUT */ - 0x100 MUX_M1 /* PMU_HKADC_SSI */ - >; - }; - - csi0_pwd_n_pmx_func: csi0_pwd_n_pmx_func { - pinctrl-single,pins = < - 0x044 MUX_M0 /* CSI0_PWD_N */ - >; - }; - - csi1_pwd_n_pmx_func: csi1_pwd_n_pmx_func { - pinctrl-single,pins = < - 0x04c MUX_M0 /* CSI1_PWD_N */ - >; - }; - - isp0_pmx_func: isp0_pmx_func { - pinctrl-single,pins = < - 0x058 MUX_M1 /* ISP_CLK0 */ - 0x064 MUX_M1 /* ISP_SCL0 */ - 0x068 MUX_M1 /* ISP_SDA0 */ - >; - }; - - isp1_pmx_func: isp1_pmx_func { - pinctrl-single,pins = < - 0x05c MUX_M1 /* ISP_CLK1 */ - 0x06c MUX_M1 /* ISP_SCL1 */ - 0x070 MUX_M1 /* ISP_SDA1 */ - >; - }; - - pwr_key_pmx_func: pwr_key_pmx_func { - pinctrl-single,pins = < - 0x080 MUX_M0 /* GPIO_034 */ - >; - }; - - i2c3_pmx_func: i2c3_pmx_func { - pinctrl-single,pins = < - 0x02c MUX_M1 /* I2C3_SCL */ - 0x030 MUX_M1 /* I2C3_SDA */ - >; - }; - - i2c4_pmx_func: i2c4_pmx_func { - pinctrl-single,pins = < - 0x090 MUX_M1 /* I2C4_SCL */ - 0x094 MUX_M1 /* I2C4_SDA */ - >; - }; - - pcie_perstn_pmx_func: pcie_perstn_pmx_func { - pinctrl-single,pins = < - 0x15c MUX_M1 /* PCIE_PERST_N */ - >; - }; - - usbhub5734_pmx_func: usbhub5734_pmx_func { - pinctrl-single,pins = < - 0x11c MUX_M0 /* GPIO_073 */ - 0x120 MUX_M0 /* GPIO_074 */ - >; - }; - - uart0_pmx_func: uart0_pmx_func { - pinctrl-single,pins = < - 0x0cc MUX_M2 /* UART0_RXD */ - 0x0d0 MUX_M2 /* UART0_TXD */ - >; - }; - - uart1_pmx_func: uart1_pmx_func { - pinctrl-single,pins = < - 0x0b0 MUX_M2 /* UART1_CTS_N */ - 0x0b4 MUX_M2 /* UART1_RTS_N */ - 0x0a8 MUX_M2 /* UART1_RXD */ - 0x0ac MUX_M2 /* UART1_TXD */ - >; - }; - - uart2_pmx_func: uart2_pmx_func { - pinctrl-single,pins = < - 0x0bc MUX_M2 /* UART2_CTS_N */ - 0x0c0 MUX_M2 /* UART2_RTS_N */ - 0x0c8 MUX_M2 /* UART2_RXD */ - 0x0c4 MUX_M2 /* UART2_TXD */ - >; - }; - - uart3_pmx_func: uart3_pmx_func { - pinctrl-single,pins = < - 0x0dc MUX_M1 /* UART3_CTS_N */ - 0x0e0 MUX_M1 /* UART3_RTS_N */ - 0x0e4 MUX_M1 /* UART3_RXD */ - 0x0e8 MUX_M1 /* UART3_TXD */ - >; - }; - - uart4_pmx_func: uart4_pmx_func { - pinctrl-single,pins = < - 0x0ec MUX_M1 /* UART4_CTS_N */ - 0x0f0 MUX_M1 /* UART4_RTS_N */ - 0x0f4 MUX_M1 /* UART4_RXD */ - 0x0f8 MUX_M1 /* UART4_TXD */ - >; - }; - - uart5_pmx_func: uart5_pmx_func { - pinctrl-single,pins = < - 0x0c4 MUX_M3 /* UART5_CTS_N */ - 0x0c8 MUX_M3 /* UART5_RTS_N */ - 0x0bc MUX_M3 /* UART5_RXD */ - 0x0c0 MUX_M3 /* UART5_TXD */ - >; - }; - - uart6_pmx_func: uart6_pmx_func { - pinctrl-single,pins = < - 0x0cc MUX_M1 /* UART6_CTS_N */ - 0x0d0 MUX_M1 /* UART6_RTS_N */ - 0x0d4 MUX_M1 /* UART6_RXD */ - 0x0d8 MUX_M1 /* UART6_TXD */ - >; - }; - - cam0_rst_pmx_func: cam0_rst_pmx_func { - pinctrl-single,pins = < - 0x0c8 MUX_M0 /* CAM0_RST */ - >; - }; - - cam1_rst_pmx_func: cam1_rst_pmx_func { - pinctrl-single,pins = < - 0x124 MUX_M0 /* CAM1_RST */ - >; - }; - }; - - /* [IOMG_MMC0_000, IOMG_MMC0_005] */ - pmx1: pinmux@ff37e000 { - compatible = "pinctrl-single"; - reg = <0x0 0xff37e000 0x0 0x18>; - #gpio-range-cells = <0x3>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - pinctrl-single,function-mask = <0x7>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 6 0>; - - sd_pmx_func: sd_pmx_func { - pinctrl-single,pins = < - 0x000 MUX_M1 /* SD_CLK */ - 0x004 MUX_M1 /* SD_CMD */ - 0x008 MUX_M1 /* SD_DATA0 */ - 0x00c MUX_M1 /* SD_DATA1 */ - 0x010 MUX_M1 /* SD_DATA2 */ - 0x014 MUX_M1 /* SD_DATA3 */ - >; - }; - }; - - /* [IOMG_FIX_000, IOMG_FIX_011] */ - pmx2: pinmux@ff3b6000 { - compatible = "pinctrl-single"; - reg = <0x0 0xff3b6000 0x0 0x30>; - #pinctrl-cells = <1>; - #gpio-range-cells = <0x3>; - pinctrl-single,register-width = <0x20>; - pinctrl-single,function-mask = <0x7>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 12 0>; - - ufs_pmx_func: ufs_pmx_func { - pinctrl-single,pins = < - 0x000 MUX_M1 /* UFS_REF_CLK */ - 0x004 MUX_M1 /* UFS_RST_N */ - >; - }; - - spi3_pmx_func: spi3_pmx_func { - pinctrl-single,pins = < - 0x008 MUX_M1 /* SPI3_CLK */ - 0x00c MUX_M1 /* SPI3_DI */ - 0x010 MUX_M1 /* SPI3_DO */ - 0x014 MUX_M1 /* SPI3_CS0_N */ - >; - }; - }; - - /* [IOMG_MMC1_000, IOMG_MMC1_005] */ - pmx3: pinmux@ff3fd000 { - compatible = "pinctrl-single"; - reg = <0x0 0xff3fd000 0x0 0x18>; - #pinctrl-cells = <1>; - #gpio-range-cells = <0x3>; - pinctrl-single,register-width = <0x20>; - pinctrl-single,function-mask = <0x7>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 6 0>; - - sdio_pmx_func: sdio_pmx_func { - pinctrl-single,pins = < - 0x000 MUX_M1 /* SDIO_CLK */ - 0x004 MUX_M1 /* SDIO_CMD */ - 0x008 MUX_M1 /* SDIO_DATA0 */ - 0x00c MUX_M1 /* SDIO_DATA1 */ - 0x010 MUX_M1 /* SDIO_DATA2 */ - 0x014 MUX_M1 /* SDIO_DATA3 */ - >; - }; - }; - - /* [IOMG_AO_000, IOMG_AO_041] */ - pmx4: pinmux@fff11000 { - compatible = "pinctrl-single"; - reg = <0x0 0xfff11000 0x0 0xa8>; - #pinctrl-cells = <1>; - #gpio-range-cells = <0x3>; - pinctrl-single,register-width = <0x20>; - pinctrl-single,function-mask = <0x7>; - /* pin base in node, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 42 0>; - - i2s2_pmx_func: i2s2_pmx_func { - pinctrl-single,pins = < - 0x044 MUX_M1 /* I2S2_DI */ - 0x048 MUX_M1 /* I2S2_DO */ - 0x04c MUX_M1 /* I2S2_XCLK */ - 0x050 MUX_M1 /* I2S2_XFS */ - >; - }; - - slimbus_pmx_func: slimbus_pmx_func { - pinctrl-single,pins = < - 0x02c MUX_M1 /* SLIMBUS_CLK */ - 0x030 MUX_M1 /* SLIMBUS_DATA */ - >; - }; - - i2c0_pmx_func: i2c0_pmx_func { - pinctrl-single,pins = < - 0x014 MUX_M1 /* I2C0_SCL */ - 0x018 MUX_M1 /* I2C0_SDA */ - >; - }; - - i2c1_pmx_func: i2c1_pmx_func { - pinctrl-single,pins = < - 0x01c MUX_M1 /* I2C1_SCL */ - 0x020 MUX_M1 /* I2C1_SDA */ - >; - }; - - i2c7_pmx_func: i2c7_pmx_func { - pinctrl-single,pins = < - 0x024 MUX_M3 /* I2C7_SCL */ - 0x028 MUX_M3 /* I2C7_SDA */ - >; - }; - - pcie_pmx_func: pcie_pmx_func { - pinctrl-single,pins = < - 0x084 MUX_M1 /* PCIE_CLKREQ_N */ - 0x088 MUX_M1 /* PCIE_WAKE_N */ - >; - }; - - spi2_pmx_func: spi2_pmx_func { - pinctrl-single,pins = < - 0x08c MUX_M1 /* SPI2_CLK */ - 0x090 MUX_M1 /* SPI2_DI */ - 0x094 MUX_M1 /* SPI2_DO */ - 0x098 MUX_M1 /* SPI2_CS0_N */ - >; - }; - - i2s0_pmx_func: i2s0_pmx_func { - pinctrl-single,pins = < - 0x034 MUX_M1 /* I2S0_DI */ - 0x038 MUX_M1 /* I2S0_DO */ - 0x03c MUX_M1 /* I2S0_XCLK */ - 0x040 MUX_M1 /* I2S0_XFS */ - >; - }; - }; - - pmx5: pinmux@e896c800 { - compatible = "pinconf-single"; - reg = <0x0 0xe896c800 0x0 0x200>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - - pmu_cfg_func: pmu_cfg_func { - pinctrl-single,pins = < - 0x010 0x0 /* PMU1_SSI */ - 0x014 0x0 /* PMU2_SSI */ - 0x018 0x0 /* PMU_CLKOUT */ - 0x10c 0x0 /* PMU_HKADC_SSI */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_06MA DRIVE6_MASK - >; - }; - - i2c3_cfg_func: i2c3_cfg_func { - pinctrl-single,pins = < - 0x038 0x0 /* I2C3_SCL */ - 0x03c 0x0 /* I2C3_SDA */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - csi0_pwd_n_cfg_func: csi0_pwd_n_cfg_func { - pinctrl-single,pins = < - 0x050 0x0 /* CSI0_PWD_N */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_04MA DRIVE6_MASK - >; - }; - - csi1_pwd_n_cfg_func: csi1_pwd_n_cfg_func { - pinctrl-single,pins = < - 0x058 0x0 /* CSI1_PWD_N */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_04MA DRIVE6_MASK - >; - }; - - isp0_cfg_func: isp0_cfg_func { - pinctrl-single,pins = < - 0x064 0x0 /* ISP_CLK0 */ - 0x070 0x0 /* ISP_SCL0 */ - 0x074 0x0 /* ISP_SDA0 */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_04MA DRIVE6_MASK>; - }; - - isp1_cfg_func: isp1_cfg_func { - pinctrl-single,pins = < - 0x068 0x0 /* ISP_CLK1 */ - 0x078 0x0 /* ISP_SCL1 */ - 0x07c 0x0 /* ISP_SDA1 */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_04MA DRIVE6_MASK - >; - }; - - pwr_key_cfg_func: pwr_key_cfg_func { - pinctrl-single,pins = < - 0x08c 0x0 /* GPIO_034 */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - uart1_cfg_func: uart1_cfg_func { - pinctrl-single,pins = < - 0x0b4 0x0 /* UART1_RXD */ - 0x0b8 0x0 /* UART1_TXD */ - 0x0bc 0x0 /* UART1_CTS_N */ - 0x0c0 0x0 /* UART1_RTS_N */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - uart2_cfg_func: uart2_cfg_func { - pinctrl-single,pins = < - 0x0c8 0x0 /* UART2_CTS_N */ - 0x0cc 0x0 /* UART2_RTS_N */ - 0x0d0 0x0 /* UART2_TXD */ - 0x0d4 0x0 /* UART2_RXD */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - uart5_cfg_func: uart5_cfg_func { - pinctrl-single,pins = < - 0x0c8 0x0 /* UART5_RXD */ - 0x0cc 0x0 /* UART5_TXD */ - 0x0d0 0x0 /* UART5_CTS_N */ - 0x0d4 0x0 /* UART5_RTS_N */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - cam0_rst_cfg_func: cam0_rst_cfg_func { - pinctrl-single,pins = < - 0x0d4 0x0 /* CAM0_RST */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_04MA DRIVE6_MASK - >; - }; - - uart0_cfg_func: uart0_cfg_func { - pinctrl-single,pins = < - 0x0d8 0x0 /* UART0_RXD */ - 0x0dc 0x0 /* UART0_TXD */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - uart6_cfg_func: uart6_cfg_func { - pinctrl-single,pins = < - 0x0d8 0x0 /* UART6_CTS_N */ - 0x0dc 0x0 /* UART6_RTS_N */ - 0x0e0 0x0 /* UART6_RXD */ - 0x0e4 0x0 /* UART6_TXD */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - uart3_cfg_func: uart3_cfg_func { - pinctrl-single,pins = < - 0x0e8 0x0 /* UART3_CTS_N */ - 0x0ec 0x0 /* UART3_RTS_N */ - 0x0f0 0x0 /* UART3_RXD */ - 0x0f4 0x0 /* UART3_TXD */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - uart4_cfg_func: uart4_cfg_func { - pinctrl-single,pins = < - 0x0f8 0x0 /* UART4_CTS_N */ - 0x0fc 0x0 /* UART4_RTS_N */ - 0x100 0x0 /* UART4_RXD */ - 0x104 0x0 /* UART4_TXD */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - cam1_rst_cfg_func: cam1_rst_cfg_func { - pinctrl-single,pins = < - 0x130 0x0 /* CAM1_RST */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_04MA DRIVE6_MASK - >; - }; - }; - - pmx6: pinmux@ff3b6800 { - compatible = "pinconf-single"; - reg = <0x0 0xff3b6800 0x0 0x18>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - - ufs_cfg_func: ufs_cfg_func { - pinctrl-single,pins = < - 0x000 0x0 /* UFS_REF_CLK */ - 0x004 0x0 /* UFS_RST_N */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_08MA DRIVE6_MASK - >; - }; - - spi3_cfg_func: spi3_cfg_func { - pinctrl-single,pins = < - 0x008 0x0 /* SPI3_CLK */ - 0x00c 0x0 /* SPI3_DI */ - 0x010 0x0 /* SPI3_DO */ - 0x014 0x0 /* SPI3_CS0_N */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_06MA DRIVE6_MASK - >; - }; - }; - - pmx7: pinmux@ff3fd800 { - compatible = "pinconf-single"; - reg = <0x0 0xff3fd800 0x0 0x18>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - - sdio_clk_cfg_func: sdio_clk_cfg_func { - pinctrl-single,pins = < - 0x000 0x0 /* SDIO_CLK */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE6_32MA DRIVE6_MASK - >; - }; - - sdio_cfg_func: sdio_cfg_func { - pinctrl-single,pins = < - 0x004 0x0 /* SDIO_CMD */ - 0x008 0x0 /* SDIO_DATA0 */ - 0x00c 0x0 /* SDIO_DATA1 */ - 0x010 0x0 /* SDIO_DATA2 */ - 0x014 0x0 /* SDIO_DATA3 */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE6_19MA DRIVE6_MASK - >; - }; - }; - - pmx8: pinmux@ff37e800 { - compatible = "pinconf-single"; - reg = <0x0 0xff37e800 0x0 0x18>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - - sd_clk_cfg_func: sd_clk_cfg_func { - pinctrl-single,pins = < - 0x000 0x0 /* SD_CLK */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE6_32MA - DRIVE6_MASK - >; - }; - - sd_cfg_func: sd_cfg_func { - pinctrl-single,pins = < - 0x004 0x0 /* SD_CMD */ - 0x008 0x0 /* SD_DATA0 */ - 0x00c 0x0 /* SD_DATA1 */ - 0x010 0x0 /* SD_DATA2 */ - 0x014 0x0 /* SD_DATA3 */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE6_19MA - DRIVE6_MASK - >; - }; - }; - - pmx9: pinmux@fff11800 { - compatible = "pinconf-single"; - reg = <0x0 0xfff11800 0x0 0xbc>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - - i2c0_cfg_func: i2c0_cfg_func { - pinctrl-single,pins = < - 0x01c 0x0 /* I2C0_SCL */ - 0x020 0x0 /* I2C0_SDA */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - i2c1_cfg_func: i2c1_cfg_func { - pinctrl-single,pins = < - 0x024 0x0 /* I2C1_SCL */ - 0x028 0x0 /* I2C1_SDA */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - i2c7_cfg_func: i2c7_cfg_func { - pinctrl-single,pins = < - 0x02c 0x0 /* I2C7_SCL */ - 0x030 0x0 /* I2C7_SDA */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - slimbus_cfg_func: slimbus_cfg_func { - pinctrl-single,pins = < - 0x034 0x0 /* SLIMBUS_CLK */ - 0x038 0x0 /* SLIMBUS_DATA */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - i2s0_cfg_func: i2s0_cfg_func { - pinctrl-single,pins = < - 0x040 0x0 /* I2S0_DI */ - 0x044 0x0 /* I2S0_DO */ - 0x048 0x0 /* I2S0_XCLK */ - 0x04c 0x0 /* I2S0_XFS */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - i2s2_cfg_func: i2s2_cfg_func { - pinctrl-single,pins = < - 0x050 0x0 /* I2S2_DI */ - 0x054 0x0 /* I2S2_DO */ - 0x058 0x0 /* I2S2_XCLK */ - 0x05c 0x0 /* I2S2_XFS */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - pcie_cfg_func: pcie_cfg_func { - pinctrl-single,pins = < - 0x094 0x0 /* PCIE_CLKREQ_N */ - 0x098 0x0 /* PCIE_WAKE_N */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - - spi2_cfg_func: spi2_cfg_func { - pinctrl-single,pins = < - 0x09c 0x0 /* SPI2_CLK */ - 0x0a0 0x0 /* SPI2_DI */ - 0x0a4 0x0 /* SPI2_DO */ - 0x0a8 0x0 /* SPI2_CS0_N */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_06MA DRIVE6_MASK - >; - }; - - usb_cfg_func: usb_cfg_func { - pinctrl-single,pins = < - 0x0ac 0x0 /* GPIO_219 */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi deleted file mode 100644 index d456b0aa6..000000000 --- a/arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi +++ /dev/null @@ -1,359 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Pinctrl dts file for HiSilicon HiKey970 development board - */ - -#include - -/ { - soc { - range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; - - pmx0: pinmux@e896c000 { - compatible = "pinctrl-single"; - reg = <0x0 0xe896c000 0x0 0x72c>; - #pinctrl-cells = <1>; - #gpio-range-cells = <0x3>; - pinctrl-single,register-width = <0x20>; - pinctrl-single,function-mask = <0x7>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 82 0>; - - uart0_pmx_func: uart0_pmx_func { - pinctrl-single,pins = < - 0x054 MUX_M2 /* UART0_RXD */ - 0x058 MUX_M2 /* UART0_TXD */ - >; - }; - - uart2_pmx_func: uart2_pmx_func { - pinctrl-single,pins = < - 0x700 MUX_M2 /* UART2_CTS_N */ - 0x704 MUX_M2 /* UART2_RTS_N */ - 0x708 MUX_M2 /* UART2_RXD */ - 0x70c MUX_M2 /* UART2_TXD */ - >; - }; - - uart3_pmx_func: uart3_pmx_func { - pinctrl-single,pins = < - 0x064 MUX_M1 /* UART3_CTS_N */ - 0x068 MUX_M1 /* UART3_RTS_N */ - 0x06c MUX_M1 /* UART3_RXD */ - 0x070 MUX_M1 /* UART3_TXD */ - >; - }; - - uart4_pmx_func: uart4_pmx_func { - pinctrl-single,pins = < - 0x074 MUX_M1 /* UART4_CTS_N */ - 0x078 MUX_M1 /* UART4_RTS_N */ - 0x07c MUX_M1 /* UART4_RXD */ - 0x080 MUX_M1 /* UART4_TXD */ - >; - }; - - uart6_pmx_func: uart6_pmx_func { - pinctrl-single,pins = < - 0x05c MUX_M1 /* UART6_RXD */ - 0x060 MUX_M1 /* UART6_TXD */ - >; - }; - }; - - pmx2: pinmux@e896c800 { - compatible = "pinconf-single"; - reg = <0x0 0xe896c800 0x0 0x72c>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - - uart0_cfg_func: uart0_cfg_func { - pinctrl-single,pins = < - 0x058 0x0 /* UART0_RXD */ - 0x05c 0x0 /* UART0_TXD */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_04MA DRIVE6_MASK - >; - }; - - uart2_cfg_func: uart2_cfg_func { - pinctrl-single,pins = < - 0x700 0x0 /* UART2_CTS_N */ - 0x704 0x0 /* UART2_RTS_N */ - 0x708 0x0 /* UART2_RXD */ - 0x70c 0x0 /* UART2_TXD */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_04MA DRIVE6_MASK - >; - }; - - uart3_cfg_func: uart3_cfg_func { - pinctrl-single,pins = < - 0x068 0x0 /* UART3_CTS_N */ - 0x06c 0x0 /* UART3_RTS_N */ - 0x070 0x0 /* UART3_RXD */ - 0x074 0x0 /* UART3_TXD */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_04MA DRIVE6_MASK - >; - }; - - uart4_cfg_func: uart4_cfg_func { - pinctrl-single,pins = < - 0x078 0x0 /* UART4_CTS_N */ - 0x07c 0x0 /* UART4_RTS_N */ - 0x080 0x0 /* UART4_RXD */ - 0x084 0x0 /* UART4_TXD */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_04MA DRIVE6_MASK - >; - }; - - uart6_cfg_func: uart6_cfg_func { - pinctrl-single,pins = < - 0x060 0x0 /* UART6_RXD */ - 0x064 0x0 /* UART6_TXD */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK - >; - }; - }; - - pmx5: pinmux@fc182000 { - compatible = "pinctrl-single"; - reg = <0x0 0xfc182000 0x0 0x028>; - #gpio-range-cells = <3>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - pinctrl-single,function-mask = <0x7>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 10 0>; - - sdio_pmx_func: sdio_pmx_func { - pinctrl-single,pins = < - 0x000 MUX_M1 /* SDIO_CLK */ - 0x004 MUX_M1 /* SDIO_CMD */ - 0x008 MUX_M1 /* SDIO_DATA0 */ - 0x00c MUX_M1 /* SDIO_DATA1 */ - 0x010 MUX_M1 /* SDIO_DATA2 */ - 0x014 MUX_M1 /* SDIO_DATA3 */ - >; - }; - }; - - pmx6: pinmux@fc182800 { - compatible = "pinconf-single"; - reg = <0x0 0xfc182800 0x0 0x028>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - - sdio_clk_cfg_func: sdio_clk_cfg_func { - pinctrl-single,pins = < - 0x000 0x0 /* SDIO_CLK */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE6_32MA DRIVE6_MASK - >; - }; - - sdio_cfg_func: sdio_cfg_func { - pinctrl-single,pins = < - 0x004 0x0 /* SDIO_CMD */ - 0x008 0x0 /* SDIO_DATA0 */ - 0x00c 0x0 /* SDIO_DATA1 */ - 0x010 0x0 /* SDIO_DATA2 */ - 0x014 0x0 /* SDIO_DATA3 */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE6_19MA DRIVE6_MASK - >; - }; - }; - - pmx7: pinmux@ff37e000 { - compatible = "pinctrl-single"; - reg = <0x0 0xff37e000 0x0 0x030>; - #gpio-range-cells = <3>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - pinctrl-single,function-mask = <7>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 12 0>; - - sd_pmx_func: sd_pmx_func { - pinctrl-single,pins = < - 0x000 MUX_M1 /* SD_CLK */ - 0x004 MUX_M1 /* SD_CMD */ - 0x008 MUX_M1 /* SD_DATA0 */ - 0x00c MUX_M1 /* SD_DATA1 */ - 0x010 MUX_M1 /* SD_DATA2 */ - 0x014 MUX_M1 /* SD_DATA3 */ - >; - }; - }; - - pmx8: pinmux@ff37e800 { - compatible = "pinconf-single"; - reg = <0x0 0xff37e800 0x0 0x030>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - - sd_clk_cfg_func: sd_clk_cfg_func { - pinctrl-single,pins = < - 0x000 0x0 /* SD_CLK */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_DIS - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE6_32MA - DRIVE6_MASK - >; - }; - - sd_cfg_func: sd_cfg_func { - pinctrl-single,pins = < - 0x004 0x0 /* SD_CMD */ - 0x008 0x0 /* SD_DATA0 */ - 0x00c 0x0 /* SD_DATA1 */ - 0x010 0x0 /* SD_DATA2 */ - 0x014 0x0 /* SD_DATA3 */ - >; - pinctrl-single,bias-pulldown = < - PULL_DIS - PULL_DOWN - PULL_DIS - PULL_DOWN - >; - pinctrl-single,bias-pullup = < - PULL_UP - PULL_UP - PULL_DIS - PULL_UP - >; - pinctrl-single,drive-strength = < - DRIVE6_19MA - DRIVE6_MASK - >; - }; - }; - - pmx1: pinmux@fff11000 { - compatible = "pinctrl-single"; - reg = <0x0 0xfff11000 0x0 0x73c>; - #gpio-range-cells = <0x3>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - pinctrl-single,function-mask = <0x7>; - /* pin base, nr pins & gpio function */ - pinctrl-single,gpio-range = <&range 0 46 0>; - }; - - pmx16: pinmux@fff11800 { - compatible = "pinconf-single"; - reg = <0x0 0xfff11800 0x0 0x73c>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <0x20>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts deleted file mode 100644 index 369b69b17..000000000 --- a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/** - * dts file for Hisilicon D02 Development Board - * - * Copyright (C) 2014,2015 Hisilicon Ltd. - */ - -/dts-v1/; - -#include -#include "hip05.dtsi" - -/ { - model = "Hisilicon Hip05 D02 Development Board"; - compatible = "hisilicon,hip05-d02"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x00000000 0x0 0x80000000>; - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - pwrbutton { - label = "Power Button"; - gpios = <&porta 8 GPIO_ACTIVE_LOW>; - linux,code = <116>; - debounce-interval = <0>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&peri_gpio0 { - status = "okay"; -}; - -&lbc { - status = "okay"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x0 0x90000000 0x08000000>, - <1 0 0x0 0x98000000 0x08000000>; - - nor-flash@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "numonyx,js28f00a", "cfi-flash"; - reg = <0 0x0 0x08000000>; - bank-width = <2>; - /* The three parts may not used */ - partition@0 { - label = "BIOS"; - reg = <0x0 0x300000>; - }; - partition@300000 { - label = "Linux"; - reg = <0x300000 0xa00000>; - }; - partition@1000000 { - label = "Rootfs"; - reg = <0x01000000 0x02000000>; - }; - }; - - cpld@1,0 { - compatible = "hisilicon,hip05-cpld"; - reg = <1 0x0 0x100>; - }; -}; diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi deleted file mode 100644 index bc4995536..000000000 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ /dev/null @@ -1,365 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/** - * dts file for Hisilicon D02 Development Board - * - * Copyright (C) 2014,2015 Hisilicon Ltd. - */ - -#include - -/ { - compatible = "hisilicon,hip05-d02"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - cluster2 { - core0 { - cpu = <&cpu8>; - }; - core1 { - cpu = <&cpu9>; - }; - core2 { - cpu = <&cpu10>; - }; - core3 { - cpu = <&cpu11>; - }; - }; - cluster3 { - core0 { - cpu = <&cpu12>; - }; - core1 { - cpu = <&cpu13>; - }; - core2 { - cpu = <&cpu14>; - }; - core3 { - cpu = <&cpu15>; - }; - }; - }; - - cpu0: cpu@20000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20000>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu1: cpu@20001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20001>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu2: cpu@20002 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20002>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu3: cpu@20003 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20003>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu4: cpu@20100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20100>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu5: cpu@20101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20101>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu6: cpu@20102 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20102>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu7: cpu@20103 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20103>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu8: cpu@20200 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20200>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu9: cpu@20201 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20201>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu10: cpu@20202 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20202>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu11: cpu@20203 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20203>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu12: cpu@20300 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20300>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cpu13: cpu@20301 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20301>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cpu14: cpu@20302 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20302>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cpu15: cpu@20303 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x20303>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cluster0_l2: l2-cache0 { - compatible = "cache"; - }; - - cluster1_l2: l2-cache1 { - compatible = "cache"; - }; - - cluster2_l2: l2-cache2 { - compatible = "cache"; - }; - - cluster3_l2: l2-cache3 { - compatible = "cache"; - }; - }; - - gic: interrupt-controller@8d000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x30000>; - reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ - <0x0 0x8d100000 0 0x300000>, /* GICR */ - <0x0 0xfe000000 0 0x10000>, /* GICC */ - <0x0 0xfe010000 0 0x10000>, /* GICH */ - <0x0 0xfe020000 0 0x10000>; /* GICV */ - interrupts = ; - - its_peri: interrupt-controller@8c000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0x8c000000 0x0 0x40000>; - }; - - its_m3: interrupt-controller@a3000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0xa3000000 0x0 0x40000>; - }; - - its_pcie: interrupt-controller@b7000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0xb7000000 0x0 0x40000>; - }; - - its_dsa: interrupt-controller@c6000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0xc6000000 0x0 0x40000>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a57-pmu"; - interrupts = ; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - refclk200mhz: refclk200mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - uart0: uart@80300000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x80300000 0x0 0x10000>; - interrupts = ; - clocks = <&refclk200mhz>; - clock-names = "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: uart@80310000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x80310000 0x0 0x10000>; - interrupts = ; - clocks = <&refclk200mhz>; - clock-names = "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - lbc: localbus@80380000 { - compatible = "hisilicon,hisi-localbus", "simple-bus"; - reg = <0x0 0x80380000 0x0 0x10000>; - status = "disabled"; - }; - - peri_gpio0: gpio@802e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0x0 0x802e0000 0x0 0x10000>; - status = "disabled"; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - }; - - peri_gpio1: gpio@802f0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0x0 0x802f0000 0x0 0x10000>; - status = "disabled"; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts deleted file mode 100644 index 9f4a930e7..000000000 --- a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/** - * dts file for Hisilicon D03 Development Board - * - * Copyright (C) 2016 Hisilicon Ltd. - */ - -/dts-v1/; - -#include "hip06.dtsi" - -/ { - model = "Hisilicon Hip06 D03 Development Board"; - compatible = "hisilicon,hip06-d03"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x00000000 0x0 0x40000000>; - }; - - chosen { }; -}; - -&ipmi0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -ð0 { - status = "okay"; -}; - -ð1 { - status = "okay"; -}; - -ð2 { - status = "okay"; -}; - -ð3 { - status = "okay"; -}; - -&sas1 { - status = "okay"; -}; - -&usb_ohci { - status = "okay"; -}; - -&usb_ehci { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi deleted file mode 100644 index 50ceaa959..000000000 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ /dev/null @@ -1,754 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/** - * dts file for Hisilicon D03 Development Board - * - * Copyright (C) 2016 Hisilicon Ltd. - */ - -#include - -/ { - compatible = "hisilicon,hip06-d03"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - cluster2 { - core0 { - cpu = <&cpu8>; - }; - core1 { - cpu = <&cpu9>; - }; - core2 { - cpu = <&cpu10>; - }; - core3 { - cpu = <&cpu11>; - }; - }; - cluster3 { - core0 { - cpu = <&cpu12>; - }; - core1 { - cpu = <&cpu13>; - }; - core2 { - cpu = <&cpu14>; - }; - core3 { - cpu = <&cpu15>; - }; - }; - }; - - cpu0: cpu@10000 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10000>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu1: cpu@10001 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10001>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu2: cpu@10002 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10002>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu3: cpu@10003 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10003>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - }; - - cpu4: cpu@10100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10100>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu5: cpu@10101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10101>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu6: cpu@10102 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10102>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu7: cpu@10103 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10103>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - }; - - cpu8: cpu@10200 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10200>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu9: cpu@10201 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10201>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu10: cpu@10202 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10202>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu11: cpu@10203 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10203>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - }; - - cpu12: cpu@10300 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10300>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cpu13: cpu@10301 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10301>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cpu14: cpu@10302 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10302>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cpu15: cpu@10303 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x10303>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - }; - - cluster0_l2: l2-cache0 { - compatible = "cache"; - }; - - cluster1_l2: l2-cache1 { - compatible = "cache"; - }; - - cluster2_l2: l2-cache2 { - compatible = "cache"; - }; - - cluster3_l2: l2-cache3 { - compatible = "cache"; - }; - }; - - gic: interrupt-controller@4d000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x30000>; - reg = <0x0 0x4d000000 0 0x10000>, /* GICD */ - <0x0 0x4d100000 0 0x300000>, /* GICR */ - <0x0 0xfe000000 0 0x10000>, /* GICC */ - <0x0 0xfe010000 0 0x10000>, /* GICH */ - <0x0 0xfe020000 0 0x10000>; /* GICV */ - interrupts = ; - - its_dsa: interrupt-controller@c6000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0xc6000000 0x0 0x40000>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a57-pmu"; - interrupts = ; - }; - - mbigen_pcie@a0080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x0 0xa0080000 0x0 0x10000>; - - mbigen_usb: intc_usb { - msi-parent = <&its_dsa 0x40080>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <2>; - }; - - mbigen_sas1: intc_sas1 { - msi-parent = <&its_dsa 0x40000>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <128>; - }; - - mbigen_sas2: intc_sas2 { - msi-parent = <&its_dsa 0x40040>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <128>; - }; - - mbigen_pcie0: intc_pcie0 { - msi-parent = <&its_dsa 0x40085>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <10>; - }; - }; - - mbigen_dsa@c0080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x0 0xc0080000 0x0 0x10000>; - - mbigen_dsaf0: intc_dsaf0 { - msi-parent = <&its_dsa 0x40800>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <409>; - }; - - mbigen_sas0: intc-sas0 { - msi-parent = <&its_dsa 0x40900>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <128>; - }; - }; - - /** - * HiSilicon erratum 161010801: This describes the limitation - * of HiSilicon platforms hip06/hip07 to support the SMMUv3 - * mappings for PCIe MSI transactions. - * PCIe controller on these platforms has to differentiate the - * MSI payload against other DMA payload and has to modify the - * MSI payload. This makes it difficult for these platforms to - * have a SMMU translation for MSI. In order to workaround this, - * ARM SMMUv3 driver requires a quirk to treat the MSI regions - * separately. Such a quirk is currently missing for DT based - * systems. Hence please make sure that the smmu pcie node on - * hip06 is disabled as this will break the PCIe functionality - * when iommu-map entry is used along with the PCIe node. - * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html - */ - smmu0: smmu_pcie { - compatible = "arm,smmu-v3"; - reg = <0x0 0xa0040000 0x0 0x20000>; - #iommu-cells = <1>; - dma-coherent; - smmu-cb-memtype = <0x0 0x1>; - hisilicon,broken-prefetch-cmd; - status = "disabled"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - isa@a01b0000 { - compatible = "hisilicon,hip06-lpc"; - #size-cells = <1>; - #address-cells = <2>; - reg = <0x0 0xa01b0000 0x0 0x1000>; - - ipmi0: bt@e4 { - compatible = "ipmi-bt"; - device_type = "ipmi"; - reg = <0x01 0xe4 0x04>; - status = "disabled"; - }; - - uart0: lpc-uart@2f8 { - compatible = "ns16550a"; - clock-frequency = <1843200>; - reg = <0x01 0x2f8 0x08>; - status = "disabled"; - }; - }; - - refclk: refclk { - compatible = "fixed-clock"; - clock-frequency = <50000000>; - #clock-cells = <0>; - }; - - usb_ohci: ohci@a7030000 { - compatible = "generic-ohci"; - reg = <0x0 0xa7030000 0x0 0x10000>; - interrupt-parent = <&mbigen_usb>; - interrupts = <640 4>; - dma-coherent; - status = "disabled"; - }; - - usb_ehci: ehci@a7020000 { - compatible = "generic-ehci"; - reg = <0x0 0xa7020000 0x0 0x10000>; - interrupt-parent = <&mbigen_usb>; - interrupts = <641 4>; - dma-coherent; - status = "disabled"; - }; - - peri_c_subctrl: sub_ctrl_c@60000000 { - compatible = "hisilicon,peri-subctrl","syscon"; - reg = <0 0x60000000 0x0 0x10000>; - }; - - dsa_subctrl: dsa_subctrl@c0000000 { - compatible = "hisilicon,dsa-subctrl", "syscon"; - reg = <0x0 0xc0000000 0x0 0x10000>; - }; - - pcie_subctl: pcie_subctl@a0000000 { - compatible = "hisilicon,pcie-sas-subctrl", "syscon"; - reg = <0x0 0xa0000000 0x0 0x10000>; - }; - - serdes_ctrl: sds_ctrl@c2200000 { - compatible = "syscon"; - reg = <0 0xc2200000 0x0 0x80000>; - }; - - mdio@603c0000 { - compatible = "hisilicon,hns-mdio"; - reg = <0x0 0x603c0000 0x0 0x1000>; - subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>; - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; - - dsaf0: dsa@c7000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "hisilicon,hns-dsaf-v2"; - mode = "6port-16rss"; - reg = <0x0 0xc5000000 0x0 0x890000 - 0x0 0xc7000000 0x0 0x600000>; - reg-names = "ppe-base", "dsaf-base"; - interrupt-parent = <&mbigen_dsaf0>; - subctrl-syscon = <&dsa_subctrl>; - reset-field-offset = <0>; - interrupts = - <576 1>, <577 1>, <578 1>, <579 1>, <580 1>, - <581 1>, <582 1>, <583 1>, <584 1>, <585 1>, - <586 1>, <587 1>, <588 1>, <589 1>, <590 1>, - <591 1>, <592 1>, <593 1>, <594 1>, <595 1>, - <596 1>, <597 1>, <598 1>, <599 1>, <600 1>, - <960 1>, <961 1>, <962 1>, <963 1>, <964 1>, - <965 1>, <966 1>, <967 1>, <968 1>, <969 1>, - <970 1>, <971 1>, <972 1>, <973 1>, <974 1>, - <975 1>, <976 1>, <977 1>, <978 1>, <979 1>, - <980 1>, <981 1>, <982 1>, <983 1>, <984 1>, - <985 1>, <986 1>, <987 1>, <988 1>, <989 1>, - <990 1>, <991 1>, <992 1>, <993 1>, <994 1>, - <995 1>, <996 1>, <997 1>, <998 1>, <999 1>, - <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>, - <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>, - <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>, - <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>, - <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>, - <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>, - <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>, - <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>, - <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>, - <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>, - <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>, - <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>, - <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>, - <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>, - <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>, - <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>, - <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>, - <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>, - <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>, - <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>, - <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>, - <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>, - <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>, - <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>, - <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>, - <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>, - <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>, - <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>, - <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>, - <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>, - <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>, - <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>, - <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>, - <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>, - <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>, - <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>, - <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>, - <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>, - <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>, - <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>, - <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>, - <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>, - <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>, - <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>, - <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>, - <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>, - <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>, - <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>, - <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>, - <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>, - <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>, - <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>, - <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>, - <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>, - <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>, - <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>, - <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>, - <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>, - <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>, - <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>, - <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>, - <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>, - <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>, - <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>, - <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>, - <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>, - <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>, - <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>, - <1340 1>, <1341 1>, <1342 1>, <1343 1>; - - desc-num = <0x400>; - buf-size = <0x1000>; - dma-coherent; - - port@0 { - reg = <0>; - serdes-syscon = <&serdes_ctrl>; - port-rst-offset = <0>; - port-mode-offset = <0>; - media-type = "fiber"; - }; - - port@1 { - reg = <1>; - serdes-syscon= <&serdes_ctrl>; - port-rst-offset = <1>; - port-mode-offset = <1>; - media-type = "fiber"; - }; - - port@4 { - reg = <4>; - phy-handle = <&phy0>; - serdes-syscon= <&serdes_ctrl>; - port-rst-offset = <4>; - port-mode-offset = <2>; - media-type = "copper"; - }; - - port@5 { - reg = <5>; - phy-handle = <&phy1>; - serdes-syscon= <&serdes_ctrl>; - port-rst-offset = <5>; - port-mode-offset = <3>; - media-type = "copper"; - }; - }; - - eth0: ethernet-4{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <4>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth1: ethernet-5{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <5>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth2: ethernet-0{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <0>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth3: ethernet-1{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <1>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - sas0: sas@c3000000 { - compatible = "hisilicon,hip06-sas-v2"; - reg = <0 0xc3000000 0 0x10000>; - sas-addr = [50 01 88 20 16 00 00 00]; - hisilicon,sas-syscon = <&dsa_subctrl>; - ctrl-reset-reg = <0xa60>; - ctrl-reset-sts-reg = <0x5a30>; - ctrl-clock-ena-reg = <0x338>; - clocks = <&refclk 0>; - queue-count = <16>; - phy-count = <8>; - dma-coherent; - interrupt-parent = <&mbigen_sas0>; - interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, - <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, - <75 4>,<76 4>,<77 4>,<78 4>,<79 4>, - <80 4>,<81 4>,<82 4>,<83 4>,<84 4>, - <85 4>,<86 4>,<87 4>,<88 4>,<89 4>, - <90 4>,<91 4>,<92 4>,<93 4>,<94 4>, - <95 4>,<96 4>,<97 4>,<98 4>,<99 4>, - <100 4>,<101 4>,<102 4>,<103 4>,<104 4>, - <105 4>,<106 4>,<107 4>,<108 4>,<109 4>, - <110 4>,<111 4>,<112 4>,<113 4>,<114 4>, - <115 4>,<116 4>,<117 4>,<118 4>,<119 4>, - <120 4>,<121 4>,<122 4>,<123 4>,<124 4>, - <125 4>,<126 4>,<127 4>,<128 4>,<129 4>, - <130 4>,<131 4>,<132 4>,<133 4>,<134 4>, - <135 4>,<136 4>,<137 4>,<138 4>,<139 4>, - <140 4>,<141 4>,<142 4>,<143 4>,<144 4>, - <145 4>,<146 4>,<147 4>,<148 4>,<149 4>, - <150 4>,<151 4>,<152 4>,<153 4>,<154 4>, - <155 4>,<156 4>,<157 4>,<158 4>,<159 4>, - <160 4>,<601 1>,<602 1>,<603 1>,<604 1>, - <605 1>,<606 1>,<607 1>,<608 1>,<609 1>, - <610 1>,<611 1>,<612 1>,<613 1>,<614 1>, - <615 1>,<616 1>,<617 1>,<618 1>,<619 1>, - <620 1>,<621 1>,<622 1>,<623 1>,<624 1>, - <625 1>,<626 1>,<627 1>,<628 1>,<629 1>, - <630 1>,<631 1>,<632 1>; - status = "disabled"; - }; - - sas1: sas@a2000000 { - compatible = "hisilicon,hip06-sas-v2"; - reg = <0 0xa2000000 0 0x10000>; - sas-addr = [50 01 88 20 16 00 00 00]; - hisilicon,sas-syscon = <&pcie_subctl>; - hip06-sas-v2-quirk-amt; - ctrl-reset-reg = <0xa18>; - ctrl-reset-sts-reg = <0x5a0c>; - ctrl-clock-ena-reg = <0x318>; - clocks = <&refclk 0>; - queue-count = <16>; - phy-count = <8>; - dma-coherent; - interrupt-parent = <&mbigen_sas1>; - interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, - <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, - <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, - <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, - <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, - <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, - <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, - <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, - <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, - <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, - <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, - <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, - <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, - <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, - <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, - <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, - <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, - <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, - <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, - <159 4>,<576 1>,<577 1>,<578 1>,<579 1>, - <580 1>,<581 1>,<582 1>,<583 1>,<584 1>, - <585 1>,<586 1>,<587 1>,<588 1>,<589 1>, - <590 1>,<591 1>,<592 1>,<593 1>,<594 1>, - <595 1>,<596 1>,<597 1>,<598 1>,<599 1>, - <600 1>,<601 1>,<602 1>,<603 1>,<604 1>, - <605 1>,<606 1>,<607 1>; - status = "disabled"; - }; - - sas2: sas@a3000000 { - compatible = "hisilicon,hip06-sas-v2"; - reg = <0 0xa3000000 0 0x10000>; - sas-addr = [50 01 88 20 16 00 00 00]; - hisilicon,sas-syscon = <&pcie_subctl>; - ctrl-reset-reg = <0xae0>; - ctrl-reset-sts-reg = <0x5a70>; - ctrl-clock-ena-reg = <0x3a8>; - clocks = <&refclk 0>; - queue-count = <16>; - phy-count = <9>; - dma-coherent; - interrupt-parent = <&mbigen_sas2>; - interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>, - <197 4>,<198 4>,<199 4>,<200 4>,<201 4>, - <202 4>,<203 4>,<204 4>,<205 4>,<206 4>, - <207 4>,<208 4>,<209 4>,<210 4>,<211 4>, - <212 4>,<213 4>,<214 4>,<215 4>,<216 4>, - <217 4>,<218 4>,<219 4>,<220 4>,<221 4>, - <222 4>,<223 4>,<224 4>,<225 4>,<226 4>, - <227 4>,<228 4>,<229 4>,<230 4>,<231 4>, - <232 4>,<233 4>,<234 4>,<235 4>,<236 4>, - <237 4>,<238 4>,<239 4>,<240 4>,<241 4>, - <242 4>,<243 4>,<244 4>,<245 4>,<246 4>, - <247 4>,<248 4>,<249 4>,<250 4>,<251 4>, - <252 4>,<253 4>,<254 4>,<255 4>,<256 4>, - <257 4>,<258 4>,<259 4>,<260 4>,<261 4>, - <262 4>,<263 4>,<264 4>,<265 4>,<266 4>, - <267 4>,<268 4>,<269 4>,<270 4>,<271 4>, - <272 4>,<273 4>,<274 4>,<275 4>,<276 4>, - <277 4>,<278 4>,<279 4>,<280 4>,<281 4>, - <282 4>,<283 4>,<284 4>,<285 4>,<286 4>, - <287 4>,<608 1>,<609 1>,<610 1>,<611 1>, - <612 1>,<613 1>,<614 1>,<615 1>,<616 1>, - <617 1>,<618 1>,<619 1>,<620 1>,<621 1>, - <622 1>,<623 1>,<624 1>,<625 1>,<626 1>, - <627 1>,<628 1>,<629 1>,<630 1>,<631 1>, - <632 1>,<633 1>,<634 1>,<635 1>,<636 1>, - <637 1>,<638 1>,<639 1>; - status = "disabled"; - }; - - pcie0: pcie@a0090000 { - compatible = "hisilicon,hip06-pcie-ecam"; - reg = <0 0xb0000000 0 0x2000000>, - <0 0xa0090000 0 0x10000>; - bus-range = <0 31>; - msi-map = <0x0000 &its_dsa 0x0000 0x2000>; - msi-map-mask = <0xffff>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 - 0x5ff0000 0x01000000 0 0 0 0xb7ff0000 - 0 0x10000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4 - 0x0 0 0 2 &mbigen_pcie0 650 4 - 0x0 0 0 3 &mbigen_pcie0 650 4 - 0x0 0 0 4 &mbigen_pcie0 650 4>; - status = "disabled"; - }; - - }; - -}; diff --git a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts deleted file mode 100644 index 81a2312c8..000000000 --- a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/** - * dts file for Hisilicon D05 Development Board - * - * Copyright (C) 2016 Hisilicon Ltd. - */ - -/dts-v1/; - -#include "hip07.dtsi" - -/ { - model = "Hisilicon Hip07 D05 Development Board"; - compatible = "hisilicon,hip07-d05"; - - /* the mem node will be updated by UEFI. */ - memory@0 { - device_type = "memory"; - reg = <0x0 0x00000000 0x0 0x40000000>; - numa-node-id = <0>; - }; - - distance-map { - compatible = "numa-distance-map-v1"; - distance-matrix = <0 0 10>, - <0 1 15>, - <0 2 20>, - <0 3 25>, - <1 0 15>, - <1 1 10>, - <1 2 25>, - <1 3 30>, - <2 0 20>, - <2 1 25>, - <2 2 10>, - <2 3 15>, - <3 0 25>, - <3 1 30>, - <3 2 15>, - <3 3 10>; - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&ipmi0 { - status = "okay"; -}; - -&usb_ohci { - status = "okay"; -}; - -&usb_ehci { - status = "okay"; -}; - -ð0 { - status = "okay"; -}; - -ð1 { - status = "okay"; -}; - -ð2 { - status = "okay"; -}; - -ð3 { - status = "okay"; -}; - -&sas1 { - status = "okay"; -}; - -&p0_pcie2_a { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi deleted file mode 100644 index 4773a533f..000000000 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ /dev/null @@ -1,1887 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/** - * dts file for Hisilicon D05 Development Board - * - * Copyright (C) 2016 Hisilicon Ltd. - */ - -#include - -/ { - compatible = "hisilicon,hip07-d05"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - - cluster2 { - core0 { - cpu = <&cpu8>; - }; - core1 { - cpu = <&cpu9>; - }; - core2 { - cpu = <&cpu10>; - }; - core3 { - cpu = <&cpu11>; - }; - }; - - cluster3 { - core0 { - cpu = <&cpu12>; - }; - core1 { - cpu = <&cpu13>; - }; - core2 { - cpu = <&cpu14>; - }; - core3 { - cpu = <&cpu15>; - }; - }; - - cluster4 { - core0 { - cpu = <&cpu16>; - }; - core1 { - cpu = <&cpu17>; - }; - core2 { - cpu = <&cpu18>; - }; - core3 { - cpu = <&cpu19>; - }; - }; - - cluster5 { - core0 { - cpu = <&cpu20>; - }; - core1 { - cpu = <&cpu21>; - }; - core2 { - cpu = <&cpu22>; - }; - core3 { - cpu = <&cpu23>; - }; - }; - - cluster6 { - core0 { - cpu = <&cpu24>; - }; - core1 { - cpu = <&cpu25>; - }; - core2 { - cpu = <&cpu26>; - }; - core3 { - cpu = <&cpu27>; - }; - }; - - cluster7 { - core0 { - cpu = <&cpu28>; - }; - core1 { - cpu = <&cpu29>; - }; - core2 { - cpu = <&cpu30>; - }; - core3 { - cpu = <&cpu31>; - }; - }; - - cluster8 { - core0 { - cpu = <&cpu32>; - }; - core1 { - cpu = <&cpu33>; - }; - core2 { - cpu = <&cpu34>; - }; - core3 { - cpu = <&cpu35>; - }; - }; - - cluster9 { - core0 { - cpu = <&cpu36>; - }; - core1 { - cpu = <&cpu37>; - }; - core2 { - cpu = <&cpu38>; - }; - core3 { - cpu = <&cpu39>; - }; - }; - - cluster10 { - core0 { - cpu = <&cpu40>; - }; - core1 { - cpu = <&cpu41>; - }; - core2 { - cpu = <&cpu42>; - }; - core3 { - cpu = <&cpu43>; - }; - }; - - cluster11 { - core0 { - cpu = <&cpu44>; - }; - core1 { - cpu = <&cpu45>; - }; - core2 { - cpu = <&cpu46>; - }; - core3 { - cpu = <&cpu47>; - }; - }; - - cluster12 { - core0 { - cpu = <&cpu48>; - }; - core1 { - cpu = <&cpu49>; - }; - core2 { - cpu = <&cpu50>; - }; - core3 { - cpu = <&cpu51>; - }; - }; - - cluster13 { - core0 { - cpu = <&cpu52>; - }; - core1 { - cpu = <&cpu53>; - }; - core2 { - cpu = <&cpu54>; - }; - core3 { - cpu = <&cpu55>; - }; - }; - - cluster14 { - core0 { - cpu = <&cpu56>; - }; - core1 { - cpu = <&cpu57>; - }; - core2 { - cpu = <&cpu58>; - }; - core3 { - cpu = <&cpu59>; - }; - }; - - cluster15 { - core0 { - cpu = <&cpu60>; - }; - core1 { - cpu = <&cpu61>; - }; - core2 { - cpu = <&cpu62>; - }; - core3 { - cpu = <&cpu63>; - }; - }; - }; - - cpu0: cpu@10000 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10000>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - numa-node-id = <0>; - }; - - cpu1: cpu@10001 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10001>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - numa-node-id = <0>; - }; - - cpu2: cpu@10002 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10002>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - numa-node-id = <0>; - }; - - cpu3: cpu@10003 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10003>; - enable-method = "psci"; - next-level-cache = <&cluster0_l2>; - numa-node-id = <0>; - }; - - cpu4: cpu@10100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10100>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - numa-node-id = <0>; - }; - - cpu5: cpu@10101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10101>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - numa-node-id = <0>; - }; - - cpu6: cpu@10102 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10102>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - numa-node-id = <0>; - }; - - cpu7: cpu@10103 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10103>; - enable-method = "psci"; - next-level-cache = <&cluster1_l2>; - numa-node-id = <0>; - }; - - cpu8: cpu@10200 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10200>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - numa-node-id = <0>; - }; - - cpu9: cpu@10201 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10201>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - numa-node-id = <0>; - }; - - cpu10: cpu@10202 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10202>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - numa-node-id = <0>; - }; - - cpu11: cpu@10203 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10203>; - enable-method = "psci"; - next-level-cache = <&cluster2_l2>; - numa-node-id = <0>; - }; - - cpu12: cpu@10300 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10300>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - numa-node-id = <0>; - }; - - cpu13: cpu@10301 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10301>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - numa-node-id = <0>; - }; - - cpu14: cpu@10302 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10302>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - numa-node-id = <0>; - }; - - cpu15: cpu@10303 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x10303>; - enable-method = "psci"; - next-level-cache = <&cluster3_l2>; - numa-node-id = <0>; - }; - - cpu16: cpu@30000 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30000>; - enable-method = "psci"; - next-level-cache = <&cluster4_l2>; - numa-node-id = <1>; - }; - - cpu17: cpu@30001 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30001>; - enable-method = "psci"; - next-level-cache = <&cluster4_l2>; - numa-node-id = <1>; - }; - - cpu18: cpu@30002 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30002>; - enable-method = "psci"; - next-level-cache = <&cluster4_l2>; - numa-node-id = <1>; - }; - - cpu19: cpu@30003 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30003>; - enable-method = "psci"; - next-level-cache = <&cluster4_l2>; - numa-node-id = <1>; - }; - - cpu20: cpu@30100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30100>; - enable-method = "psci"; - next-level-cache = <&cluster5_l2>; - numa-node-id = <1>; - }; - - cpu21: cpu@30101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30101>; - enable-method = "psci"; - next-level-cache = <&cluster5_l2>; - numa-node-id = <1>; - }; - - cpu22: cpu@30102 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30102>; - enable-method = "psci"; - next-level-cache = <&cluster5_l2>; - numa-node-id = <1>; - }; - - cpu23: cpu@30103 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30103>; - enable-method = "psci"; - next-level-cache = <&cluster5_l2>; - numa-node-id = <1>; - }; - - cpu24: cpu@30200 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30200>; - enable-method = "psci"; - next-level-cache = <&cluster6_l2>; - numa-node-id = <1>; - }; - - cpu25: cpu@30201 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30201>; - enable-method = "psci"; - next-level-cache = <&cluster6_l2>; - numa-node-id = <1>; - }; - - cpu26: cpu@30202 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30202>; - enable-method = "psci"; - next-level-cache = <&cluster6_l2>; - numa-node-id = <1>; - }; - - cpu27: cpu@30203 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30203>; - enable-method = "psci"; - next-level-cache = <&cluster6_l2>; - numa-node-id = <1>; - }; - - cpu28: cpu@30300 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30300>; - enable-method = "psci"; - next-level-cache = <&cluster7_l2>; - numa-node-id = <1>; - }; - - cpu29: cpu@30301 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30301>; - enable-method = "psci"; - next-level-cache = <&cluster7_l2>; - numa-node-id = <1>; - }; - - cpu30: cpu@30302 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30302>; - enable-method = "psci"; - next-level-cache = <&cluster7_l2>; - numa-node-id = <1>; - }; - - cpu31: cpu@30303 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x30303>; - enable-method = "psci"; - next-level-cache = <&cluster7_l2>; - numa-node-id = <1>; - }; - - cpu32: cpu@50000 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50000>; - enable-method = "psci"; - next-level-cache = <&cluster8_l2>; - numa-node-id = <2>; - }; - - cpu33: cpu@50001 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50001>; - enable-method = "psci"; - next-level-cache = <&cluster8_l2>; - numa-node-id = <2>; - }; - - cpu34: cpu@50002 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50002>; - enable-method = "psci"; - next-level-cache = <&cluster8_l2>; - numa-node-id = <2>; - }; - - cpu35: cpu@50003 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50003>; - enable-method = "psci"; - next-level-cache = <&cluster8_l2>; - numa-node-id = <2>; - }; - - cpu36: cpu@50100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50100>; - enable-method = "psci"; - next-level-cache = <&cluster9_l2>; - numa-node-id = <2>; - }; - - cpu37: cpu@50101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50101>; - enable-method = "psci"; - next-level-cache = <&cluster9_l2>; - numa-node-id = <2>; - }; - - cpu38: cpu@50102 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50102>; - enable-method = "psci"; - next-level-cache = <&cluster9_l2>; - numa-node-id = <2>; - }; - - cpu39: cpu@50103 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50103>; - enable-method = "psci"; - next-level-cache = <&cluster9_l2>; - numa-node-id = <2>; - }; - - cpu40: cpu@50200 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50200>; - enable-method = "psci"; - next-level-cache = <&cluster10_l2>; - numa-node-id = <2>; - }; - - cpu41: cpu@50201 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50201>; - enable-method = "psci"; - next-level-cache = <&cluster10_l2>; - numa-node-id = <2>; - }; - - cpu42: cpu@50202 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50202>; - enable-method = "psci"; - next-level-cache = <&cluster10_l2>; - numa-node-id = <2>; - }; - - cpu43: cpu@50203 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50203>; - enable-method = "psci"; - next-level-cache = <&cluster10_l2>; - numa-node-id = <2>; - }; - - cpu44: cpu@50300 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50300>; - enable-method = "psci"; - next-level-cache = <&cluster11_l2>; - numa-node-id = <2>; - }; - - cpu45: cpu@50301 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50301>; - enable-method = "psci"; - next-level-cache = <&cluster11_l2>; - numa-node-id = <2>; - }; - - cpu46: cpu@50302 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50302>; - enable-method = "psci"; - next-level-cache = <&cluster11_l2>; - numa-node-id = <2>; - }; - - cpu47: cpu@50303 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x50303>; - enable-method = "psci"; - next-level-cache = <&cluster11_l2>; - numa-node-id = <2>; - }; - - cpu48: cpu@70000 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70000>; - enable-method = "psci"; - next-level-cache = <&cluster12_l2>; - numa-node-id = <3>; - }; - - cpu49: cpu@70001 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70001>; - enable-method = "psci"; - next-level-cache = <&cluster12_l2>; - numa-node-id = <3>; - }; - - cpu50: cpu@70002 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70002>; - enable-method = "psci"; - next-level-cache = <&cluster12_l2>; - numa-node-id = <3>; - }; - - cpu51: cpu@70003 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70003>; - enable-method = "psci"; - next-level-cache = <&cluster12_l2>; - numa-node-id = <3>; - }; - - cpu52: cpu@70100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70100>; - enable-method = "psci"; - next-level-cache = <&cluster13_l2>; - numa-node-id = <3>; - }; - - cpu53: cpu@70101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70101>; - enable-method = "psci"; - next-level-cache = <&cluster13_l2>; - numa-node-id = <3>; - }; - - cpu54: cpu@70102 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70102>; - enable-method = "psci"; - next-level-cache = <&cluster13_l2>; - numa-node-id = <3>; - }; - - cpu55: cpu@70103 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70103>; - enable-method = "psci"; - next-level-cache = <&cluster13_l2>; - numa-node-id = <3>; - }; - - cpu56: cpu@70200 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70200>; - enable-method = "psci"; - next-level-cache = <&cluster14_l2>; - numa-node-id = <3>; - }; - - cpu57: cpu@70201 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70201>; - enable-method = "psci"; - next-level-cache = <&cluster14_l2>; - numa-node-id = <3>; - }; - - cpu58: cpu@70202 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70202>; - enable-method = "psci"; - next-level-cache = <&cluster14_l2>; - numa-node-id = <3>; - }; - - cpu59: cpu@70203 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70203>; - enable-method = "psci"; - next-level-cache = <&cluster14_l2>; - numa-node-id = <3>; - }; - - cpu60: cpu@70300 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70300>; - enable-method = "psci"; - next-level-cache = <&cluster15_l2>; - numa-node-id = <3>; - }; - - cpu61: cpu@70301 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70301>; - enable-method = "psci"; - next-level-cache = <&cluster15_l2>; - numa-node-id = <3>; - }; - - cpu62: cpu@70302 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70302>; - enable-method = "psci"; - next-level-cache = <&cluster15_l2>; - numa-node-id = <3>; - }; - - cpu63: cpu@70303 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x70303>; - enable-method = "psci"; - next-level-cache = <&cluster15_l2>; - numa-node-id = <3>; - }; - - cluster0_l2: l2-cache0 { - compatible = "cache"; - }; - - cluster1_l2: l2-cache1 { - compatible = "cache"; - }; - - cluster2_l2: l2-cache2 { - compatible = "cache"; - }; - - cluster3_l2: l2-cache3 { - compatible = "cache"; - }; - - cluster4_l2: l2-cache4 { - compatible = "cache"; - }; - - cluster5_l2: l2-cache5 { - compatible = "cache"; - }; - - cluster6_l2: l2-cache6 { - compatible = "cache"; - }; - - cluster7_l2: l2-cache7 { - compatible = "cache"; - }; - - cluster8_l2: l2-cache8 { - compatible = "cache"; - }; - - cluster9_l2: l2-cache9 { - compatible = "cache"; - }; - - cluster10_l2: l2-cache10 { - compatible = "cache"; - }; - - cluster11_l2: l2-cache11 { - compatible = "cache"; - }; - - cluster12_l2: l2-cache12 { - compatible = "cache"; - }; - - cluster13_l2: l2-cache13 { - compatible = "cache"; - }; - - cluster14_l2: l2-cache14 { - compatible = "cache"; - }; - - cluster15_l2: l2-cache15 { - compatible = "cache"; - }; - }; - - gic: interrupt-controller@4d000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - #redistributor-regions = <4>; - redistributor-stride = <0x0 0x40000>; - reg = <0x0 0x4d000000 0x0 0x10000>, /* GICD */ - <0x0 0x4d100000 0x0 0x400000>, /* p0 GICR node 0 */ - <0x0 0x6d100000 0x0 0x400000>, /* p0 GICR node 1 */ - <0x400 0x4d100000 0x0 0x400000>, /* p1 GICR node 2 */ - <0x400 0x6d100000 0x0 0x400000>, /* p1 GICR node 3 */ - <0x0 0xfe000000 0x0 0x10000>, /* GICC */ - <0x0 0xfe010000 0x0 0x10000>, /* GICH */ - <0x0 0xfe020000 0x0 0x10000>; /* GICV */ - interrupts = ; - - p0_its_peri_a: interrupt-controller@4c000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0x4c000000 0x0 0x40000>; - }; - - p0_its_peri_b: interrupt-controller@6c000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0x6c000000 0x0 0x40000>; - }; - - p0_its_dsa_a: interrupt-controller@c6000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0xc6000000 0x0 0x40000>; - }; - - p0_its_dsa_b: interrupt-controller@8,c6000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x8 0xc6000000 0x0 0x40000>; - }; - - p1_its_peri_a: interrupt-controller@400,4c000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x400 0x4c000000 0x0 0x40000>; - }; - - p1_its_peri_b: interrupt-controller@400,6c000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x400 0x6c000000 0x0 0x40000>; - }; - - p1_its_dsa_a: interrupt-controller@400,c6000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x400 0xc6000000 0x0 0x40000>; - }; - - p1_its_dsa_b: interrupt-controller@408,c6000000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x408 0xc6000000 0x0 0x40000>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a72-pmu"; - interrupts = ; - }; - - p0_mbigen_peri_b: interrupt-controller@60080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x0 0x60080000 0x0 0x10000>; - - mbigen_uart: uart_intc { - msi-parent = <&p0_its_peri_b 0x120c7>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <1>; - }; - }; - - p0_mbigen_pcie_a: interrupt-controller@a0080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x0 0xa0080000 0x0 0x10000>; - - mbigen_pcie2_a: intc_pcie2_a { - msi-parent = <&p0_its_dsa_a 0x40087>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <10>; - }; - - mbigen_sas1: intc_sas1 { - msi-parent = <&p0_its_dsa_a 0x40000>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <128>; - }; - - mbigen_sas2: intc_sas2 { - msi-parent = <&p0_its_dsa_a 0x40040>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <128>; - }; - - mbigen_smmu_pcie: intc_smmu_pcie { - msi-parent = <&p0_its_dsa_a 0x40b0c>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <3>; - }; - - mbigen_usb: intc_usb { - msi-parent = <&p0_its_dsa_a 0x40080>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <2>; - }; - }; - p0_mbigen_alg_a:interrupt-controller@d0080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x0 0xd0080000 0x0 0x10000>; - - p0_mbigen_sec_a: intc_sec { - msi-parent = <&p0_its_dsa_a 0x40400>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <33>; - }; - p0_mbigen_smmu_alg_a: intc_smmu_alg { - msi-parent = <&p0_its_dsa_a 0x40b1b>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <3>; - }; - }; - p0_mbigen_alg_b:interrupt-controller@8,d0080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x8 0xd0080000 0x0 0x10000>; - - p0_mbigen_sec_b: intc_sec { - msi-parent = <&p0_its_dsa_b 0x42400>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <33>; - }; - p0_mbigen_smmu_alg_b: intc_smmu_alg { - msi-parent = <&p0_its_dsa_b 0x42b1b>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <3>; - }; - }; - p1_mbigen_alg_a:interrupt-controller@400,d0080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x400 0xd0080000 0x0 0x10000>; - - p1_mbigen_sec_a: intc_sec { - msi-parent = <&p1_its_dsa_a 0x44400>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <33>; - }; - p1_mbigen_smmu_alg_a: intc_smmu_alg { - msi-parent = <&p1_its_dsa_a 0x44b1b>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <3>; - }; - }; - p1_mbigen_alg_b:interrupt-controller@408,d0080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x408 0xd0080000 0x0 0x10000>; - - p1_mbigen_sec_b: intc_sec { - msi-parent = <&p1_its_dsa_b 0x46400>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <33>; - }; - p1_mbigen_smmu_alg_b: intc_smmu_alg { - msi-parent = <&p1_its_dsa_b 0x46b1b>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <3>; - }; - }; - p0_mbigen_dsa_a: interrupt-controller@c0080000 { - compatible = "hisilicon,mbigen-v2"; - reg = <0x0 0xc0080000 0x0 0x10000>; - - mbigen_dsaf0: intc_dsaf0 { - msi-parent = <&p0_its_dsa_a 0x40800>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <409>; - }; - - mbigen_dsa_roce: intc-roce { - msi-parent = <&p0_its_dsa_a 0x40B1E>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <34>; - }; - - mbigen_sas0: intc-sas0 { - msi-parent = <&p0_its_dsa_a 0x40900>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <128>; - }; - - mbigen_smmu_dsa: intc_smmu_dsa { - msi-parent = <&p0_its_dsa_a 0x40b20>; - interrupt-controller; - #interrupt-cells = <2>; - num-pins = <3>; - }; - }; - - /** - * HiSilicon erratum 161010801: This describes the limitation - * of HiSilicon platforms hip06/hip07 to support the SMMUv3 - * mappings for PCIe MSI transactions. - * PCIe controller on these platforms has to differentiate the - * MSI payload against other DMA payload and has to modify the - * MSI payload. This makes it difficult for these platforms to - * have a SMMU translation for MSI. In order to workaround this, - * ARM SMMUv3 driver requires a quirk to treat the MSI regions - * separately. Such a quirk is currently missing for DT based - * systems. Hence please make sure that the smmu pcie node on - * hip07 is disabled as this will break the PCIe functionality - * when iommu-map entry is used along with the PCIe node. - * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html - */ - smmu0: smmu_pcie { - compatible = "arm,smmu-v3"; - reg = <0x0 0xa0040000 0x0 0x20000>; - #iommu-cells = <1>; - dma-coherent; - smmu-cb-memtype = <0x0 0x1>; - hisilicon,broken-prefetch-cmd; - status = "disabled"; - }; - p0_smmu_alg_a: smmu_alg@d0040000 { - compatible = "arm,smmu-v3"; - reg = <0x0 0xd0040000 0x0 0x20000>; - interrupt-parent = <&p0_mbigen_smmu_alg_a>; - interrupts = <733 1>, - <734 1>, - <735 1>; - interrupt-names = "eventq", "gerror", "priq"; - #iommu-cells = <1>; - dma-coherent; - hisilicon,broken-prefetch-cmd; - /* smmu-cb-memtype = <0x0 0x1>;*/ - }; - p0_smmu_alg_b: smmu_alg@8,d0040000 { - compatible = "arm,smmu-v3"; - reg = <0x8 0xd0040000 0x0 0x20000>; - interrupt-parent = <&p0_mbigen_smmu_alg_b>; - interrupts = <733 1>, - <734 1>, - <735 1>; - interrupt-names = "eventq", "gerror", "priq"; - #iommu-cells = <1>; - dma-coherent; - hisilicon,broken-prefetch-cmd; - /* smmu-cb-memtype = <0x0 0x1>;*/ - }; - p1_smmu_alg_a: smmu_alg@400,d0040000 { - compatible = "arm,smmu-v3"; - reg = <0x400 0xd0040000 0x0 0x20000>; - interrupt-parent = <&p1_mbigen_smmu_alg_a>; - interrupts = <733 1>, - <734 1>, - <735 1>; - interrupt-names = "eventq", "gerror", "priq"; - #iommu-cells = <1>; - dma-coherent; - hisilicon,broken-prefetch-cmd; - /* smmu-cb-memtype = <0x0 0x1>;*/ - }; - p1_smmu_alg_b: smmu_alg@408,d0040000 { - compatible = "arm,smmu-v3"; - reg = <0x408 0xd0040000 0x0 0x20000>; - interrupt-parent = <&p1_mbigen_smmu_alg_b>; - interrupts = <733 1>, - <734 1>, - <735 1>; - interrupt-names = "eventq", "gerror", "priq"; - #iommu-cells = <1>; - dma-coherent; - hisilicon,broken-prefetch-cmd; - /* smmu-cb-memtype = <0x0 0x1>;*/ - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - isa@a01b0000 { - compatible = "hisilicon,hip07-lpc"; - #size-cells = <1>; - #address-cells = <2>; - reg = <0x0 0xa01b0000 0x0 0x1000>; - - ipmi0: bt@e4 { - compatible = "ipmi-bt"; - device_type = "ipmi"; - reg = <0x01 0xe4 0x04>; - status = "disabled"; - }; - }; - - uart0: uart@602b0000 { - compatible = "arm,sbsa-uart"; - reg = <0x0 0x602b0000 0x0 0x1000>; - interrupt-parent = <&mbigen_uart>; - interrupts = <807 4>; - current-speed = <115200>; - reg-io-width = <4>; - status = "disabled"; - }; - - usb_ohci: ohci@a7030000 { - compatible = "generic-ohci"; - reg = <0x0 0xa7030000 0x0 0x10000>; - interrupt-parent = <&mbigen_usb>; - interrupts = <640 4>; - dma-coherent; - status = "disabled"; - }; - - usb_ehci: ehci@a7020000 { - compatible = "generic-ehci"; - reg = <0x0 0xa7020000 0x0 0x10000>; - interrupt-parent = <&mbigen_usb>; - interrupts = <641 4>; - dma-coherent; - status = "disabled"; - }; - - peri_c_subctrl: sub_ctrl_c@60000000 { - compatible = "hisilicon,peri-subctrl","syscon"; - reg = <0 0x60000000 0x0 0x10000>; - }; - - dsa_subctrl: dsa_subctrl@c0000000 { - compatible = "hisilicon,dsa-subctrl", "syscon"; - reg = <0x0 0xc0000000 0x0 0x10000>; - }; - - dsa_cpld: dsa_cpld@78000010 { - compatible = "syscon"; - reg = <0x0 0x78000010 0x0 0x100>; - reg-io-width = <2>; - }; - - pcie_subctl: pcie_subctl@a0000000 { - compatible = "hisilicon,pcie-sas-subctrl", "syscon"; - reg = <0x0 0xa0000000 0x0 0x10000>; - }; - - serdes_ctrl: sds_ctrl@c2200000 { - compatible = "syscon"; - reg = <0 0xc2200000 0x0 0x80000>; - }; - - mdio@603c0000 { - compatible = "hisilicon,hns-mdio"; - reg = <0x0 0x603c0000 0x0 0x1000>; - subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 - 0x531c 0x5a1c>; - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; - - dsaf0: dsa@c7000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "hisilicon,hns-dsaf-v2"; - mode = "6port-16rss"; - reg = <0x0 0xc5000000 0x0 0x890000 - 0x0 0xc7000000 0x0 0x600000>; - reg-names = "ppe-base", "dsaf-base"; - interrupt-parent = <&mbigen_dsaf0>; - subctrl-syscon = <&dsa_subctrl>; - reset-field-offset = <0>; - interrupts = - <576 1>, <577 1>, <578 1>, <579 1>, <580 1>, - <581 1>, <582 1>, <583 1>, <584 1>, <585 1>, - <586 1>, <587 1>, <588 1>, <589 1>, <590 1>, - <591 1>, <592 1>, <593 1>, <594 1>, <595 1>, - <596 1>, <597 1>, <598 1>, <599 1>, <600 1>, - <960 1>, <961 1>, <962 1>, <963 1>, <964 1>, - <965 1>, <966 1>, <967 1>, <968 1>, <969 1>, - <970 1>, <971 1>, <972 1>, <973 1>, <974 1>, - <975 1>, <976 1>, <977 1>, <978 1>, <979 1>, - <980 1>, <981 1>, <982 1>, <983 1>, <984 1>, - <985 1>, <986 1>, <987 1>, <988 1>, <989 1>, - <990 1>, <991 1>, <992 1>, <993 1>, <994 1>, - <995 1>, <996 1>, <997 1>, <998 1>, <999 1>, - <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>, - <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>, - <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>, - <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>, - <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>, - <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>, - <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>, - <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>, - <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>, - <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>, - <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>, - <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>, - <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>, - <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>, - <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>, - <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>, - <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>, - <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>, - <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>, - <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>, - <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>, - <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>, - <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>, - <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>, - <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>, - <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>, - <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>, - <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>, - <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>, - <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>, - <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>, - <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>, - <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>, - <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>, - <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>, - <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>, - <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>, - <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>, - <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>, - <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>, - <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>, - <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>, - <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>, - <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>, - <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>, - <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>, - <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>, - <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>, - <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>, - <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>, - <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>, - <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>, - <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>, - <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>, - <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>, - <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>, - <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>, - <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>, - <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>, - <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>, - <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>, - <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>, - <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>, - <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>, - <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>, - <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>, - <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>, - <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>, - <1340 1>, <1341 1>, <1342 1>, <1343 1>; - - desc-num = <0x400>; - buf-size = <0x1000>; - dma-coherent; - - port@0 { - reg = <0>; - serdes-syscon = <&serdes_ctrl>; - cpld-syscon = <&dsa_cpld 0x0>; - port-rst-offset = <0>; - port-mode-offset = <0>; - mc-mac-mask = [ff f0 00 00 00 00]; - media-type = "fiber"; - }; - - port@1 { - reg = <1>; - serdes-syscon= <&serdes_ctrl>; - cpld-syscon = <&dsa_cpld 0x4>; - port-rst-offset = <1>; - port-mode-offset = <1>; - mc-mac-mask = [ff f0 00 00 00 00]; - media-type = "fiber"; - }; - - port@4 { - reg = <4>; - phy-handle = <&phy0>; - serdes-syscon= <&serdes_ctrl>; - port-rst-offset = <4>; - port-mode-offset = <2>; - mc-mac-mask = [ff f0 00 00 00 00]; - media-type = "copper"; - }; - - port@5 { - reg = <5>; - phy-handle = <&phy1>; - serdes-syscon= <&serdes_ctrl>; - port-rst-offset = <5>; - port-mode-offset = <3>; - mc-mac-mask = [ff f0 00 00 00 00]; - media-type = "copper"; - }; - }; - - eth0: ethernet@4{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <4>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth1: ethernet@5{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <5>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth2: ethernet@0{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <0>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth3: ethernet@1{ - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <1>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - infiniband@c4000000 { - compatible = "hisilicon,hns-roce-v1"; - reg = <0x0 0xc4000000 0x0 0x100000>; - dma-coherent; - eth-handle = <ð2 ð3 0 0 ð0 ð1>; - dsaf-handle = <&dsaf0>; - node-guid = [00 9A CD 00 00 01 02 03]; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&mbigen_dsa_roce>; - interrupts = <722 1>, - <723 1>, - <724 1>, - <725 1>, - <726 1>, - <727 1>, - <728 1>, - <729 1>, - <730 1>, - <731 1>, - <732 1>, - <733 1>, - <734 1>, - <735 1>, - <736 1>, - <737 1>, - <738 1>, - <739 1>, - <740 1>, - <741 1>, - <742 1>, - <743 1>, - <744 1>, - <745 1>, - <746 1>, - <747 1>, - <748 1>, - <749 1>, - <750 1>, - <751 1>, - <752 1>, - <753 1>, - <785 1>, - <754 4>; - - interrupt-names = "hns-roce-comp-0", - "hns-roce-comp-1", - "hns-roce-comp-2", - "hns-roce-comp-3", - "hns-roce-comp-4", - "hns-roce-comp-5", - "hns-roce-comp-6", - "hns-roce-comp-7", - "hns-roce-comp-8", - "hns-roce-comp-9", - "hns-roce-comp-10", - "hns-roce-comp-11", - "hns-roce-comp-12", - "hns-roce-comp-13", - "hns-roce-comp-14", - "hns-roce-comp-15", - "hns-roce-comp-16", - "hns-roce-comp-17", - "hns-roce-comp-18", - "hns-roce-comp-19", - "hns-roce-comp-20", - "hns-roce-comp-21", - "hns-roce-comp-22", - "hns-roce-comp-23", - "hns-roce-comp-24", - "hns-roce-comp-25", - "hns-roce-comp-26", - "hns-roce-comp-27", - "hns-roce-comp-28", - "hns-roce-comp-29", - "hns-roce-comp-30", - "hns-roce-comp-31", - "hns-roce-async", - "hns-roce-common"; - }; - - sas0: sas@c3000000 { - compatible = "hisilicon,hip07-sas-v2"; - reg = <0 0xc3000000 0 0x10000>; - sas-addr = [50 01 88 20 16 00 00 00]; - hisilicon,sas-syscon = <&dsa_subctrl>; - ctrl-reset-reg = <0xa60>; - ctrl-reset-sts-reg = <0x5a30>; - ctrl-clock-ena-reg = <0x338>; - queue-count = <16>; - phy-count = <8>; - dma-coherent; - interrupt-parent = <&mbigen_sas0>; - interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, - <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, - <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, - <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, - <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, - <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, - <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, - <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, - <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, - <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, - <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, - <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, - <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, - <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, - <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, - <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, - <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, - <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, - <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, - <159 4>,<601 1>,<602 1>,<603 1>,<604 1>, - <605 1>,<606 1>,<607 1>,<608 1>,<609 1>, - <610 1>,<611 1>,<612 1>,<613 1>,<614 1>, - <615 1>,<616 1>,<617 1>,<618 1>,<619 1>, - <620 1>,<621 1>,<622 1>,<623 1>,<624 1>, - <625 1>,<626 1>,<627 1>,<628 1>,<629 1>, - <630 1>,<631 1>,<632 1>; - status = "disabled"; - }; - - sas1: sas@a2000000 { - compatible = "hisilicon,hip07-sas-v2"; - reg = <0 0xa2000000 0 0x10000>; - sas-addr = [50 01 88 20 16 00 00 00]; - hisilicon,sas-syscon = <&pcie_subctl>; - hip06-sas-v2-quirk-amt; - ctrl-reset-reg = <0xa18>; - ctrl-reset-sts-reg = <0x5a0c>; - ctrl-clock-ena-reg = <0x318>; - queue-count = <16>; - phy-count = <8>; - dma-coherent; - interrupt-parent = <&mbigen_sas1>; - interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>, - <69 4>,<70 4>,<71 4>,<72 4>,<73 4>, - <74 4>,<75 4>,<76 4>,<77 4>,<78 4>, - <79 4>,<80 4>,<81 4>,<82 4>,<83 4>, - <84 4>,<85 4>,<86 4>,<87 4>,<88 4>, - <89 4>,<90 4>,<91 4>,<92 4>,<93 4>, - <94 4>,<95 4>,<96 4>,<97 4>,<98 4>, - <99 4>,<100 4>,<101 4>,<102 4>,<103 4>, - <104 4>,<105 4>,<106 4>,<107 4>,<108 4>, - <109 4>,<110 4>,<111 4>,<112 4>,<113 4>, - <114 4>,<115 4>,<116 4>,<117 4>,<118 4>, - <119 4>,<120 4>,<121 4>,<122 4>,<123 4>, - <124 4>,<125 4>,<126 4>,<127 4>,<128 4>, - <129 4>,<130 4>,<131 4>,<132 4>,<133 4>, - <134 4>,<135 4>,<136 4>,<137 4>,<138 4>, - <139 4>,<140 4>,<141 4>,<142 4>,<143 4>, - <144 4>,<145 4>,<146 4>,<147 4>,<148 4>, - <149 4>,<150 4>,<151 4>,<152 4>,<153 4>, - <154 4>,<155 4>,<156 4>,<157 4>,<158 4>, - <159 4>,<576 1>,<577 1>,<578 1>,<579 1>, - <580 1>,<581 1>,<582 1>,<583 1>,<584 1>, - <585 1>,<586 1>,<587 1>,<588 1>,<589 1>, - <590 1>,<591 1>,<592 1>,<593 1>,<594 1>, - <595 1>,<596 1>,<597 1>,<598 1>,<599 1>, - <600 1>,<601 1>,<602 1>,<603 1>,<604 1>, - <605 1>,<606 1>,<607 1>; - status = "disabled"; - }; - - sas2: sas@a3000000 { - compatible = "hisilicon,hip07-sas-v2"; - reg = <0 0xa3000000 0 0x10000>; - sas-addr = [50 01 88 20 16 00 00 00]; - hisilicon,sas-syscon = <&pcie_subctl>; - ctrl-reset-reg = <0xae0>; - ctrl-reset-sts-reg = <0x5a70>; - ctrl-clock-ena-reg = <0x3a8>; - queue-count = <16>; - phy-count = <9>; - dma-coherent; - interrupt-parent = <&mbigen_sas2>; - interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>, - <197 4>,<198 4>,<199 4>,<200 4>,<201 4>, - <202 4>,<203 4>,<204 4>,<205 4>,<206 4>, - <207 4>,<208 4>,<209 4>,<210 4>,<211 4>, - <212 4>,<213 4>,<214 4>,<215 4>,<216 4>, - <217 4>,<218 4>,<219 4>,<220 4>,<221 4>, - <222 4>,<223 4>,<224 4>,<225 4>,<226 4>, - <227 4>,<228 4>,<229 4>,<230 4>,<231 4>, - <232 4>,<233 4>,<234 4>,<235 4>,<236 4>, - <237 4>,<238 4>,<239 4>,<240 4>,<241 4>, - <242 4>,<243 4>,<244 4>,<245 4>,<246 4>, - <247 4>,<248 4>,<249 4>,<250 4>,<251 4>, - <252 4>,<253 4>,<254 4>,<255 4>,<256 4>, - <257 4>,<258 4>,<259 4>,<260 4>,<261 4>, - <262 4>,<263 4>,<264 4>,<265 4>,<266 4>, - <267 4>,<268 4>,<269 4>,<270 4>,<271 4>, - <272 4>,<273 4>,<274 4>,<275 4>,<276 4>, - <277 4>,<278 4>,<279 4>,<280 4>,<281 4>, - <282 4>,<283 4>,<284 4>,<285 4>,<286 4>, - <287 4>,<608 1>,<609 1>,<610 1>,<611 1>, - <612 1>,<613 1>,<614 1>,<615 1>,<616 1>, - <617 1>,<618 1>,<619 1>,<620 1>,<621 1>, - <622 1>,<623 1>,<624 1>,<625 1>,<626 1>, - <627 1>,<628 1>,<629 1>,<630 1>,<631 1>, - <632 1>,<633 1>,<634 1>,<635 1>,<636 1>, - <637 1>,<638 1>,<639 1>; - status = "disabled"; - }; - - p0_pcie2_a: pcie@a00a0000 { - compatible = "hisilicon,hip07-pcie-ecam"; - reg = <0 0xaf800000 0 0x800000>, - <0 0xa00a0000 0 0x10000>; - bus-range = <0xf8 0xff>; - msi-map = <0xf800 &p0_its_dsa_a 0xf800 0x800>; - msi-map-mask = <0xffff>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - ranges = <0x02000000 0 0xa8000000 0 0xa8000000 0 0x77f0000 - 0x01000000 0 0 0 0xaf7f0000 0 0x10000>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4 - 0x0 0 0 2 &mbigen_pcie2_a 671 4 - 0x0 0 0 3 &mbigen_pcie2_a 671 4 - 0x0 0 0 4 &mbigen_pcie2_a 671 4>; - status = "disabled"; - }; - p0_sec_a: crypto@d2000000 { - compatible = "hisilicon,hip07-sec"; - reg = <0x0 0xd0000000 0x0 0x10000 - 0x0 0xd2000000 0x0 0x10000 - 0x0 0xd2010000 0x0 0x10000 - 0x0 0xd2020000 0x0 0x10000 - 0x0 0xd2030000 0x0 0x10000 - 0x0 0xd2040000 0x0 0x10000 - 0x0 0xd2050000 0x0 0x10000 - 0x0 0xd2060000 0x0 0x10000 - 0x0 0xd2070000 0x0 0x10000 - 0x0 0xd2080000 0x0 0x10000 - 0x0 0xd2090000 0x0 0x10000 - 0x0 0xd20a0000 0x0 0x10000 - 0x0 0xd20b0000 0x0 0x10000 - 0x0 0xd20c0000 0x0 0x10000 - 0x0 0xd20d0000 0x0 0x10000 - 0x0 0xd20e0000 0x0 0x10000 - 0x0 0xd20f0000 0x0 0x10000 - 0x0 0xd2100000 0x0 0x10000>; - interrupt-parent = <&p0_mbigen_sec_a>; - iommus = <&p0_smmu_alg_a 0x600>; - dma-coherent; - interrupts = <576 4>, - <577 1>, <578 4>, - <579 1>, <580 4>, - <581 1>, <582 4>, - <583 1>, <584 4>, - <585 1>, <586 4>, - <587 1>, <588 4>, - <589 1>, <590 4>, - <591 1>, <592 4>, - <593 1>, <594 4>, - <595 1>, <596 4>, - <597 1>, <598 4>, - <599 1>, <600 4>, - <601 1>, <602 4>, - <603 1>, <604 4>, - <605 1>, <606 4>, - <607 1>, <608 4>; - }; - p0_sec_b: crypto@8,d2000000 { - compatible = "hisilicon,hip07-sec"; - reg = <0x8 0xd0000000 0x0 0x10000 - 0x8 0xd2000000 0x0 0x10000 - 0x8 0xd2010000 0x0 0x10000 - 0x8 0xd2020000 0x0 0x10000 - 0x8 0xd2030000 0x0 0x10000 - 0x8 0xd2040000 0x0 0x10000 - 0x8 0xd2050000 0x0 0x10000 - 0x8 0xd2060000 0x0 0x10000 - 0x8 0xd2070000 0x0 0x10000 - 0x8 0xd2080000 0x0 0x10000 - 0x8 0xd2090000 0x0 0x10000 - 0x8 0xd20a0000 0x0 0x10000 - 0x8 0xd20b0000 0x0 0x10000 - 0x8 0xd20c0000 0x0 0x10000 - 0x8 0xd20d0000 0x0 0x10000 - 0x8 0xd20e0000 0x0 0x10000 - 0x8 0xd20f0000 0x0 0x10000 - 0x8 0xd2100000 0x0 0x10000>; - interrupt-parent = <&p0_mbigen_sec_b>; - iommus = <&p0_smmu_alg_b 0x600>; - dma-coherent; - interrupts = <576 4>, - <577 1>, <578 4>, - <579 1>, <580 4>, - <581 1>, <582 4>, - <583 1>, <584 4>, - <585 1>, <586 4>, - <587 1>, <588 4>, - <589 1>, <590 4>, - <591 1>, <592 4>, - <593 1>, <594 4>, - <595 1>, <596 4>, - <597 1>, <598 4>, - <599 1>, <600 4>, - <601 1>, <602 4>, - <603 1>, <604 4>, - <605 1>, <606 4>, - <607 1>, <608 4>; - }; - p1_sec_a: crypto@400,d2000000 { - compatible = "hisilicon,hip07-sec"; - reg = <0x400 0xd0000000 0x0 0x10000 - 0x400 0xd2000000 0x0 0x10000 - 0x400 0xd2010000 0x0 0x10000 - 0x400 0xd2020000 0x0 0x10000 - 0x400 0xd2030000 0x0 0x10000 - 0x400 0xd2040000 0x0 0x10000 - 0x400 0xd2050000 0x0 0x10000 - 0x400 0xd2060000 0x0 0x10000 - 0x400 0xd2070000 0x0 0x10000 - 0x400 0xd2080000 0x0 0x10000 - 0x400 0xd2090000 0x0 0x10000 - 0x400 0xd20a0000 0x0 0x10000 - 0x400 0xd20b0000 0x0 0x10000 - 0x400 0xd20c0000 0x0 0x10000 - 0x400 0xd20d0000 0x0 0x10000 - 0x400 0xd20e0000 0x0 0x10000 - 0x400 0xd20f0000 0x0 0x10000 - 0x400 0xd2100000 0x0 0x10000>; - interrupt-parent = <&p1_mbigen_sec_a>; - iommus = <&p1_smmu_alg_a 0x600>; - dma-coherent; - interrupts = <576 4>, - <577 1>, <578 4>, - <579 1>, <580 4>, - <581 1>, <582 4>, - <583 1>, <584 4>, - <585 1>, <586 4>, - <587 1>, <588 4>, - <589 1>, <590 4>, - <591 1>, <592 4>, - <593 1>, <594 4>, - <595 1>, <596 4>, - <597 1>, <598 4>, - <599 1>, <600 4>, - <601 1>, <602 4>, - <603 1>, <604 4>, - <605 1>, <606 4>, - <607 1>, <608 4>; - }; - p1_sec_b: crypto@408,d2000000 { - compatible = "hisilicon,hip07-sec"; - reg = <0x408 0xd0000000 0x0 0x10000 - 0x408 0xd2000000 0x0 0x10000 - 0x408 0xd2010000 0x0 0x10000 - 0x408 0xd2020000 0x0 0x10000 - 0x408 0xd2030000 0x0 0x10000 - 0x408 0xd2040000 0x0 0x10000 - 0x408 0xd2050000 0x0 0x10000 - 0x408 0xd2060000 0x0 0x10000 - 0x408 0xd2070000 0x0 0x10000 - 0x408 0xd2080000 0x0 0x10000 - 0x408 0xd2090000 0x0 0x10000 - 0x408 0xd20a0000 0x0 0x10000 - 0x408 0xd20b0000 0x0 0x10000 - 0x408 0xd20c0000 0x0 0x10000 - 0x408 0xd20d0000 0x0 0x10000 - 0x408 0xd20e0000 0x0 0x10000 - 0x408 0xd20f0000 0x0 0x10000 - 0x408 0xd2100000 0x0 0x10000>; - interrupt-parent = <&p1_mbigen_sec_b>; - iommus = <&p1_smmu_alg_b 0x600>; - dma-coherent; - interrupts = <576 4>, - <577 1>, <578 4>, - <579 1>, <580 4>, - <581 1>, <582 4>, - <583 1>, <584 4>, - <585 1>, <586 4>, - <587 1>, <588 4>, - <589 1>, <590 4>, - <591 1>, <592 4>, - <593 1>, <594 4>, - <595 1>, <596 4>, - <597 1>, <598 4>, - <599 1>, <600 4>, - <601 1>, <602 4>, - <603 1>, <604 4>, - <605 1>, <606 4>, - <607 1>, <608 4>; - }; - - }; -}; diff --git a/arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi deleted file mode 100644 index 7bb19e4b0..000000000 --- a/arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Pinctrl dts file for HiSilicon Poplar board - * - * Copyright (c) 2016-2018 HiSilicon Technologies Co., Ltd. - */ - -#include - -/* value, enable bits, disable bits, mask */ -#define PINCTRL_PULLDOWN(value, enable, disable, mask) \ - (value << 13) (enable << 13) (disable << 13) (mask << 13) -#define PINCTRL_PULLUP(value, enable, disable, mask) \ - (value << 12) (enable << 12) (disable << 12) (mask << 12) -#define PINCTRL_SLEW_RATE(value, mask) (value << 8) (mask << 8) -#define PINCTRL_DRV_STRENGTH(value, mask) (value << 4) (mask << 4) - -&pmx0 { - emmc_pins_1: emmc-pins-1 { - pinctrl-single,pins = < - 0x000 MUX_M2 - 0x004 MUX_M2 - 0x008 MUX_M2 - 0x00c MUX_M2 - 0x010 MUX_M2 - 0x014 MUX_M2 - 0x018 MUX_M2 - 0x01c MUX_M2 - 0x024 MUX_M2 - >; - pinctrl-single,bias-pulldown = < - PINCTRL_PULLDOWN(0, 1, 0, 1) - >; - pinctrl-single,bias-pullup = < - PINCTRL_PULLUP(0, 1, 0, 1) - >; - pinctrl-single,slew-rate = < - PINCTRL_SLEW_RATE(1, 1) - >; - pinctrl-single,drive-strength = < - PINCTRL_DRV_STRENGTH(0xb, 0xf) - >; - }; - - emmc_pins_2: emmc-pins-2 { - pinctrl-single,pins = < - 0x028 MUX_M2 - >; - pinctrl-single,bias-pulldown = < - PINCTRL_PULLDOWN(0, 1, 0, 1) - >; - pinctrl-single,bias-pullup = < - PINCTRL_PULLUP(0, 1, 0, 1) - >; - pinctrl-single,slew-rate = < - PINCTRL_SLEW_RATE(1, 1) - >; - pinctrl-single,drive-strength = < - PINCTRL_DRV_STRENGTH(0x9, 0xf) - >; - }; - - emmc_pins_3: emmc-pins-3 { - pinctrl-single,pins = < - 0x02c MUX_M2 - >; - pinctrl-single,bias-pulldown = < - PINCTRL_PULLDOWN(0, 1, 0, 1) - >; - pinctrl-single,bias-pullup = < - PINCTRL_PULLUP(0, 1, 0, 1) - >; - pinctrl-single,slew-rate = < - PINCTRL_SLEW_RATE(1, 1) - >; - pinctrl-single,drive-strength = < - PINCTRL_DRV_STRENGTH(3, 3) - >; - }; - - emmc_pins_4: emmc-pins-4 { - pinctrl-single,pins = < - 0x030 MUX_M2 - >; - pinctrl-single,bias-pulldown = < - PINCTRL_PULLDOWN(1, 1, 0, 1) - >; - pinctrl-single,bias-pullup = < - PINCTRL_PULLUP(0, 1, 0, 1) - >; - pinctrl-single,slew-rate = < - PINCTRL_SLEW_RATE(1, 1) - >; - pinctrl-single,drive-strength = < - PINCTRL_DRV_STRENGTH(3, 3) - >; - }; -}; diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile deleted file mode 100644 index 296eceec4..000000000 --- a/arch/arm64/boot/dts/intel/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb \ - socfpga_agilex_socdk_nand.dtb -dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/keembay-evm.dts b/arch/arm64/boot/dts/intel/keembay-evm.dts deleted file mode 100644 index 466c85363..000000000 --- a/arch/arm64/boot/dts/intel/keembay-evm.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) -/* - * Copyright (C) 2020, Intel Corporation - * - * Device tree describing Keem Bay EVM board. - */ - -/dts-v1/; - -#include "keembay-soc.dtsi" - -/ { - model = "Keem Bay EVM"; - compatible = "intel,keembay-evm", "intel,keembay"; - - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - /* 2GB of DDR memory. */ - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - -}; - -&uart3 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/intel/keembay-soc.dtsi b/arch/arm64/boot/dts/intel/keembay-soc.dtsi deleted file mode 100644 index 781761d29..000000000 --- a/arch/arm64/boot/dts/intel/keembay-soc.dtsi +++ /dev/null @@ -1,123 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) -/* - * Copyright (C) 2020, Intel Corporation. - * - * Device tree describing Keem Bay SoC. - */ - -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0>; - enable-method = "psci"; - }; - - cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x1>; - enable-method = "psci"; - }; - - cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x2>; - enable-method = "psci"; - }; - - cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x3>; - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - gic: interrupt-controller@20500000 { - compatible = "arm,gic-v3"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0 0x20500000 0x0 0x20000>, /* GICD */ - <0x0 0x20580000 0x0 0x80000>; /* GICR */ - /* VGIC maintenance interrupt */ - interrupts = ; - }; - - timer { - compatible = "arm,armv8-timer"; - /* Secure, non-secure, virtual, and hypervisor */ - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - uart0: serial@20150000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x20150000 0x0 0x100>; - interrupts = ; - clock-frequency = <24000000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: serial@20160000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x20160000 0x0 0x100>; - interrupts = ; - clock-frequency = <24000000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@20170000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x20170000 0x0 0x100>; - interrupts = ; - clock-frequency = <24000000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart3: serial@20180000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x20180000 0x0 0x100>; - interrupts = ; - clock-frequency = <24000000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi deleted file mode 100644 index 1e0c9415b..000000000 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ /dev/null @@ -1,631 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019, Intel Corporation - */ - -/dts-v1/; -#include -#include -#include - -/ { - compatible = "intel,socfpga-agilex"; - #address-cells = <2>; - #size-cells = <2>; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - service_reserved: svcbuffer@0 { - compatible = "shared-dma-pool"; - reg = <0x0 0x0 0x0 0x2000000>; - alignment = <0x1000>; - no-map; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x1>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x3>; - }; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <0 170 4>, - <0 171 4>, - <0 172 4>, - <0 173 4>; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - interrupt-parent = <&intc>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - intc: intc@fffc1000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0xfffc1000 0x0 0x1000>, - <0x0 0xfffc2000 0x0 0x2000>, - <0x0 0xfffc4000 0x0 0x2000>, - <0x0 0xfffc6000 0x0 0x2000>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - device_type = "soc"; - interrupt-parent = <&intc>; - ranges = <0 0 0 0xffffffff>; - - base_fpga_region { - #address-cells = <0x1>; - #size-cells = <0x1>; - compatible = "fpga-region"; - fpga-mgr = <&fpga_mgr>; - }; - - clkmgr: clock-controller@ffd10000 { - compatible = "intel,agilex-clkmgr"; - reg = <0xffd10000 0x1000>; - #clock-cells = <1>; - }; - - clocks { - cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - cb_intosc_ls_clk: cb-intosc-ls-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - f2s_free_clk: f2s-free-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - osc1: osc1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - qspi_clk: qspi-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; - }; - - gmac0: ethernet@ff800000 { - compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; - reg = <0xff800000 0x2000>; - interrupts = <0 90 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - tx-fifo-depth = <16384>; - rx-fifo-depth = <16384>; - snps,multicast-filter-bins = <256>; - iommus = <&smmu 1>; - altr,sysmgr-syscon = <&sysmgr 0x44 0>; - clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; - clock-names = "stmmaceth", "ptp_ref"; - status = "disabled"; - }; - - gmac1: ethernet@ff802000 { - compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; - reg = <0xff802000 0x2000>; - interrupts = <0 91 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - tx-fifo-depth = <16384>; - rx-fifo-depth = <16384>; - snps,multicast-filter-bins = <256>; - iommus = <&smmu 2>; - altr,sysmgr-syscon = <&sysmgr 0x48 0>; - clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; - clock-names = "stmmaceth", "ptp_ref"; - status = "disabled"; - }; - - gmac2: ethernet@ff804000 { - compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; - reg = <0xff804000 0x2000>; - interrupts = <0 92 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - tx-fifo-depth = <16384>; - rx-fifo-depth = <16384>; - snps,multicast-filter-bins = <256>; - iommus = <&smmu 3>; - altr,sysmgr-syscon = <&sysmgr 0x4c 0>; - clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; - clock-names = "stmmaceth", "ptp_ref"; - status = "disabled"; - }; - - gpio0: gpio@ffc03200 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc03200 0x100>; - resets = <&rst GPIO0_RESET>; - status = "disabled"; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <24>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 110 4>; - }; - }; - - gpio1: gpio@ffc03300 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc03300 0x100>; - resets = <&rst GPIO1_RESET>; - status = "disabled"; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <24>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 111 4>; - }; - }; - - i2c0: i2c@ffc02800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02800 0x100>; - interrupts = <0 103 4>; - resets = <&rst I2C0_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - status = "disabled"; - }; - - i2c1: i2c@ffc02900 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02900 0x100>; - interrupts = <0 104 4>; - resets = <&rst I2C1_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - status = "disabled"; - }; - - i2c2: i2c@ffc02a00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02a00 0x100>; - interrupts = <0 105 4>; - resets = <&rst I2C2_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - status = "disabled"; - }; - - i2c3: i2c@ffc02b00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02b00 0x100>; - interrupts = <0 106 4>; - resets = <&rst I2C3_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - status = "disabled"; - }; - - i2c4: i2c@ffc02c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02c00 0x100>; - interrupts = <0 107 4>; - resets = <&rst I2C4_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - status = "disabled"; - }; - - mmc: dwmmc0@ff808000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "altr,socfpga-dw-mshc"; - reg = <0xff808000 0x1000>; - interrupts = <0 96 4>; - fifo-depth = <0x400>; - resets = <&rst SDMMC_RESET>; - reset-names = "reset"; - clocks = <&clkmgr AGILEX_L4_MP_CLK>, - <&clkmgr AGILEX_SDMMC_CLK>; - clock-names = "biu", "ciu"; - iommus = <&smmu 5>; - status = "disabled"; - }; - - nand: nand@ffb90000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "altr,socfpga-denali-nand"; - reg = <0xffb90000 0x10000>, - <0xffb80000 0x1000>; - reg-names = "nand_data", "denali_reg"; - interrupts = <0 97 4>; - clocks = <&clkmgr AGILEX_NAND_CLK>, - <&clkmgr AGILEX_NAND_X_CLK>, - <&clkmgr AGILEX_NAND_ECC_CLK>; - clock-names = "nand", "nand_x", "ecc"; - resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; - status = "disabled"; - }; - - ocram: sram@ffe00000 { - compatible = "mmio-sram"; - reg = <0xffe00000 0x40000>; - }; - - pdma: pdma@ffda0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xffda0000 0x1000>; - interrupts = <0 81 4>, - <0 82 4>, - <0 83 4>, - <0 84 4>, - <0 85 4>, - <0 86 4>, - <0 87 4>, - <0 88 4>, - <0 89 4>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; - reset-names = "dma", "dma-ocp"; - clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; - clock-names = "apb_pclk"; - }; - - rst: rstmgr@ffd11000 { - #reset-cells = <1>; - compatible = "altr,stratix10-rst-mgr"; - reg = <0xffd11000 0x100>; - }; - - smmu: iommu@fa000000 { - compatible = "arm,mmu-500", "arm,smmu-v2"; - reg = <0xfa000000 0x40000>; - #global-interrupts = <2>; - #iommu-cells = <1>; - interrupt-parent = <&intc>; - interrupts = <0 128 4>, /* Global Secure Fault */ - <0 129 4>, /* Global Non-secure Fault */ - /* Non-secure Context Interrupts (32) */ - <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, - <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, - <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, - <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, - <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, - <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, - <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, - <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; - stream-match-mask = <0x7ff0>; - clocks = <&clkmgr AGILEX_MPU_CCU_CLK>, - <&clkmgr AGILEX_L3_MAIN_FREE_CLK>, - <&clkmgr AGILEX_L4_MAIN_CLK>; - status = "disabled"; - }; - - spi0: spi@ffda4000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xffda4000 0x1000>; - interrupts = <0 99 4>; - resets = <&rst SPIM0_RESET>; - reset-names = "spi"; - reg-io-width = <4>; - num-cs = <4>; - clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; - status = "disabled"; - }; - - spi1: spi@ffda5000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xffda5000 0x1000>; - interrupts = <0 100 4>; - resets = <&rst SPIM1_RESET>; - reset-names = "spi"; - reg-io-width = <4>; - num-cs = <4>; - clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; - status = "disabled"; - }; - - sysmgr: sysmgr@ffd12000 { - compatible = "altr,sys-mgr-s10","altr,sys-mgr"; - reg = <0xffd12000 0x500>; - }; - - /* Local timer */ - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - timer0: timer0@ffc03000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 113 4>; - reg = <0xffc03000 0x100>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - clock-names = "timer"; - }; - - timer1: timer1@ffc03100 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 114 4>; - reg = <0xffc03100 0x100>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - clock-names = "timer"; - }; - - timer2: timer2@ffd00000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 115 4>; - reg = <0xffd00000 0x100>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - clock-names = "timer"; - }; - - timer3: timer3@ffd00100 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 116 4>; - reg = <0xffd00100 0x100>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - clock-names = "timer"; - }; - - uart0: serial0@ffc02000 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02000 0x100>; - interrupts = <0 108 4>; - reg-shift = <2>; - reg-io-width = <4>; - resets = <&rst UART0_RESET>; - status = "disabled"; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - }; - - uart1: serial1@ffc02100 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02100 0x100>; - interrupts = <0 109 4>; - reg-shift = <2>; - reg-io-width = <4>; - resets = <&rst UART1_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - status = "disabled"; - }; - - usbphy0: usbphy@0 { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - status = "okay"; - }; - - usb0: usb@ffb00000 { - compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; - reg = <0xffb00000 0x40000>; - interrupts = <0 93 4>; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; - reset-names = "dwc2", "dwc2-ecc"; - clocks = <&clkmgr AGILEX_USB_CLK>; - iommus = <&smmu 6>; - status = "disabled"; - }; - - usb1: usb@ffb40000 { - compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; - reg = <0xffb40000 0x40000>; - interrupts = <0 94 4>; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; - reset-names = "dwc2", "dwc2-ecc"; - iommus = <&smmu 7>; - clocks = <&clkmgr AGILEX_USB_CLK>; - status = "disabled"; - }; - - watchdog0: watchdog@ffd00200 { - compatible = "snps,dw-wdt"; - reg = <0xffd00200 0x100>; - interrupts = <0 117 4>; - resets = <&rst WATCHDOG0_RESET>; - clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; - status = "disabled"; - }; - - watchdog1: watchdog@ffd00300 { - compatible = "snps,dw-wdt"; - reg = <0xffd00300 0x100>; - interrupts = <0 118 4>; - resets = <&rst WATCHDOG1_RESET>; - clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; - status = "disabled"; - }; - - watchdog2: watchdog@ffd00400 { - compatible = "snps,dw-wdt"; - reg = <0xffd00400 0x100>; - interrupts = <0 125 4>; - resets = <&rst WATCHDOG2_RESET>; - clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; - status = "disabled"; - }; - - watchdog3: watchdog@ffd00500 { - compatible = "snps,dw-wdt"; - reg = <0xffd00500 0x100>; - interrupts = <0 126 4>; - resets = <&rst WATCHDOG3_RESET>; - clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; - status = "disabled"; - }; - - sdr: sdr@f8011100 { - compatible = "altr,sdr-ctl", "syscon"; - reg = <0xf8011100 0xc0>; - }; - - eccmgr { - compatible = "altr,socfpga-s10-ecc-manager", - "altr,socfpga-a10-ecc-manager"; - altr,sysmgr-syscon = <&sysmgr>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = <0 15 4>; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - sdramedac { - compatible = "altr,sdram-edac-s10"; - altr,sdr-syscon = <&sdr>; - interrupts = <16 4>; - }; - - ocram-ecc@ff8cc000 { - compatible = "altr,socfpga-s10-ocram-ecc", - "altr,socfpga-a10-ocram-ecc"; - reg = <0xff8cc000 0x100>; - altr,ecc-parent = <&ocram>; - interrupts = <1 4>; - }; - - usb0-ecc@ff8c4000 { - compatible = "altr,socfpga-s10-usb-ecc", - "altr,socfpga-usb-ecc"; - reg = <0xff8c4000 0x100>; - altr,ecc-parent = <&usb0>; - interrupts = <2 4>; - }; - - emac0-rx-ecc@ff8c0000 { - compatible = "altr,socfpga-s10-eth-mac-ecc", - "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0000 0x100>; - altr,ecc-parent = <&gmac0>; - interrupts = <4 4>; - }; - - emac0-tx-ecc@ff8c0400 { - compatible = "altr,socfpga-s10-eth-mac-ecc", - "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0400 0x100>; - altr,ecc-parent = <&gmac0>; - interrupts = <5 4>; - }; - - sdmmca-ecc@ff8c8c00 { - compatible = "altr,socfpga-s10-sdmmc-ecc", - "altr,socfpga-sdmmc-ecc"; - reg = <0xff8c8c00 0x100>; - altr,ecc-parent = <&mmc>; - interrupts = <14 4>, - <15 4>; - }; - }; - - qspi: spi@ff8d2000 { - compatible = "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff8d2000 0x100>, - <0xff900000 0x100000>; - interrupts = <0 3 4>; - cdns,fifo-depth = <128>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x00000000>; - clocks = <&qspi_clk>; - - status = "disabled"; - }; - - firmware { - svc { - compatible = "intel,agilex-svc"; - method = "smc"; - memory-region = <&service_reserved>; - - fpga_mgr: fpga-mgr { - compatible = "intel,agilex-soc-fpga-mgr"; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts deleted file mode 100644 index a7a83f29f..000000000 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019, Intel Corporation - */ -#include "socfpga_agilex.dtsi" - -/ { - model = "SoCFPGA Agilex SoCDK"; - - aliases { - serial0 = &uart0; - ethernet0 = &gmac0; - ethernet1 = &gmac1; - ethernet2 = &gmac2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - hps0 { - label = "hps_led0"; - gpios = <&portb 20 GPIO_ACTIVE_HIGH>; - }; - - hps1 { - label = "hps_led1"; - gpios = <&portb 19 GPIO_ACTIVE_HIGH>; - }; - - hps2 { - label = "hps_led2"; - gpios = <&portb 21 GPIO_ACTIVE_HIGH>; - }; - }; - - memory { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; - }; - - soc { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - - max-frame-size = <9000>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <4>; - - txd0-skew-ps = <0>; /* -420ps */ - txd1-skew-ps = <0>; /* -420ps */ - txd2-skew-ps = <0>; /* -420ps */ - txd3-skew-ps = <0>; /* -420ps */ - rxd0-skew-ps = <420>; /* 0ps */ - rxd1-skew-ps = <420>; /* 0ps */ - rxd2-skew-ps = <420>; /* 0ps */ - rxd3-skew-ps = <420>; /* 0ps */ - txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <900>; /* 0ps */ - rxdv-skew-ps = <420>; /* 0ps */ - rxc-skew-ps = <1680>; /* 780ps */ - }; - }; -}; - -&mmc { - status = "okay"; - cap-sd-highspeed; - broken-cd; - bus-width = <4>; -}; - -&uart0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - disable-over-current; -}; - -&watchdog0 { - status = "okay"; -}; - -&qspi { - status = "okay"; - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,mt25qu02g", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <100000000>; - - m25p,fast-read; - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <1>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - qspi_boot: partition@0 { - label = "Boot and fpga data"; - reg = <0x0 0x03FE0000>; - }; - - qspi_rootfs: partition@3FE0000 { - label = "Root Filesystem - JFFS2"; - reg = <0x03FE0000 0x0C020000>; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts deleted file mode 100644 index 979aa59a6..000000000 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts +++ /dev/null @@ -1,135 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019, Intel Corporation - */ -#include "socfpga_agilex.dtsi" - -/ { - model = "SoCFPGA Agilex SoCDK"; - - aliases { - serial0 = &uart0; - ethernet0 = &gmac0; - ethernet1 = &gmac1; - ethernet2 = &gmac2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - hps0 { - label = "hps_led0"; - gpios = <&portb 20 GPIO_ACTIVE_HIGH>; - }; - - hps1 { - label = "hps_led1"; - gpios = <&portb 19 GPIO_ACTIVE_HIGH>; - }; - - hps2 { - label = "hps_led2"; - gpios = <&portb 21 GPIO_ACTIVE_HIGH>; - }; - }; - - memory { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; - }; - - soc { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&gmac2 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - - max-frame-size = <9000>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <4>; - - txd0-skew-ps = <0>; /* -420ps */ - txd1-skew-ps = <0>; /* -420ps */ - txd2-skew-ps = <0>; /* -420ps */ - txd3-skew-ps = <0>; /* -420ps */ - rxd0-skew-ps = <420>; /* 0ps */ - rxd1-skew-ps = <420>; /* 0ps */ - rxd2-skew-ps = <420>; /* 0ps */ - rxd3-skew-ps = <420>; /* 0ps */ - txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <900>; /* 0ps */ - rxdv-skew-ps = <420>; /* 0ps */ - rxc-skew-ps = <1680>; /* 780ps */ - }; - }; -}; - -&nand { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - nand-bus-width = <16>; - - partition@0 { - label = "u-boot"; - reg = <0 0x200000>; - }; - partition@200000 { - label = "env"; - reg = <0x200000 0x40000>; - }; - partition@240000 { - label = "dtb"; - reg = <0x240000 0x40000>; - }; - partition@280000 { - label = "kernel"; - reg = <0x280000 0x2000000>; - }; - partition@2280000 { - label = "misc"; - reg = <0x2280000 0x2000000>; - }; - partition@4280000 { - label = "rootfs"; - reg = <0x4280000 0x3bd80000>; - }; - }; -}; - -&uart0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - disable-over-current; -}; - -&watchdog0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/lg/Makefile b/arch/arm64/boot/dts/lg/Makefile deleted file mode 100644 index 4c3959e24..000000000 --- a/arch/arm64/boot/dts/lg/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_LG1K) += lg1312-ref.dtb -dtb-$(CONFIG_ARCH_LG1K) += lg1313-ref.dtb diff --git a/arch/arm64/boot/dts/lg/lg1312-ref.dts b/arch/arm64/boot/dts/lg/lg1312-ref.dts deleted file mode 100644 index 260a2c5b1..000000000 --- a/arch/arm64/boot/dts/lg/lg1312-ref.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for lg1312 Reference Board. - * - * Copyright (C) 2016, LG Electronics - */ - -/dts-v1/; - -#include "lg1312.dtsi" - -/ { - #address-cells = <2>; - #size-cells = <1>; - - model = "LG Electronics, DTV SoC LG1312 Reference Board"; - compatible = "lge,lg1312-ref", "lge,lg1312"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x00000000 0x20000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi deleted file mode 100644 index 081fe7a9f..000000000 --- a/arch/arm64/boot/dts/lg/lg1312.dtsi +++ /dev/null @@ -1,352 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for lg1312 SoC - * - * Copyright (C) 2016, LG Electronics - */ - -#include -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - - compatible = "lge,lg1312"; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - next-level-cache = <&L2_0>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - psci { - compatible = "arm,psci-0.2", "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000001>; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; - }; - - gic: interrupt-controller@c0001000 { - #interrupt-cells = <3>; - compatible = "arm,gic-400"; - interrupt-controller; - reg = <0x0 0xc0001000 0x1000>, - <0x0 0xc0002000 0x2000>, - <0x0 0xc0004000 0x2000>, - <0x0 0xc0006000 0x2000>; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - clk_bus: clk_bus { - #clock-cells = <0>; - - compatible = "fixed-clock"; - clock-frequency = <198000000>; - clock-output-names = "BUSCLK"; - }; - - soc { - #address-cells = <2>; - #size-cells = <1>; - - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - eth0: ethernet@c1b00000 { - compatible = "cdns,gem"; - reg = <0x0 0xc1b00000 0x1000>; - interrupts = ; - clocks = <&clk_bus>, <&clk_bus>; - clock-names = "hclk", "pclk"; - phy-mode = "rmii"; - /* Filled in by boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - }; - - amba { - #address-cells = <2>; - #size-cells = <1>; - #interrupt-cells = <3>; - - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - timers: timer@fd100000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x0 0xfd100000 0x1000>; - interrupts = ; - clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>; - clock-names = "timer0clk", "timer1clk", "apb_pclk"; - }; - wdog: watchdog@fd200000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xfd200000 0x1000>; - interrupts = ; - clocks = <&clk_bus>, <&clk_bus>; - clock-names = "wdog_clk", "apb_pclk"; - }; - uart0: serial@fe000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfe000000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - uart1: serial@fe100000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfe100000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - uart2: serial@fe200000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfe200000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - spi0: spi@fe800000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x0 0xfe800000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - spi1: spi@fe900000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x0 0xfe900000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - dmac0: dma@c1128000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xc1128000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - gpio0: gpio@fd400000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd400000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio1: gpio@fd410000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd410000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio2: gpio@fd420000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd420000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio3: gpio@fd430000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd430000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - gpio4: gpio@fd440000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd440000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio5: gpio@fd450000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd450000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio6: gpio@fd460000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd460000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio7: gpio@fd470000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd470000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio8: gpio@fd480000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd480000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio9: gpio@fd490000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd490000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio10: gpio@fd4a0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4a0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio11: gpio@fd4b0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4b0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - gpio12: gpio@fd4c0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4c0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio13: gpio@fd4d0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4d0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio14: gpio@fd4e0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4e0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio15: gpio@fd4f0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4f0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio16: gpio@fd500000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd500000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio17: gpio@fd510000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd510000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/lg/lg1313-ref.dts b/arch/arm64/boot/dts/lg/lg1313-ref.dts deleted file mode 100644 index e89ae8537..000000000 --- a/arch/arm64/boot/dts/lg/lg1313-ref.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for lg1313 Reference Board. - * - * Copyright (C) 2016, LG Electronics - */ - -/dts-v1/; - -#include "lg1313.dtsi" - -/ { - #address-cells = <2>; - #size-cells = <1>; - - model = "LG Electronics, DTV SoC LG1313 Reference Board"; - compatible = "lge,lg1313-ref", "lge,lg1313"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x00000000 0x20000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi deleted file mode 100644 index 604bb6975..000000000 --- a/arch/arm64/boot/dts/lg/lg1313.dtsi +++ /dev/null @@ -1,352 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for lg1313 SoC - * - * Copyright (C) 2016, LG Electronics - */ - -#include -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - - compatible = "lge,lg1313"; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - next-level-cache = <&L2_0>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - psci { - compatible = "arm,psci-0.2", "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000001>; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; - }; - - gic: interrupt-controller@c0001000 { - #interrupt-cells = <3>; - compatible = "arm,gic-400"; - interrupt-controller; - reg = <0x0 0xc0001000 0x1000>, - <0x0 0xc0002000 0x2000>, - <0x0 0xc0004000 0x2000>, - <0x0 0xc0006000 0x2000>; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - clk_bus: clk_bus { - #clock-cells = <0>; - - compatible = "fixed-clock"; - clock-frequency = <198000000>; - clock-output-names = "BUSCLK"; - }; - - soc { - #address-cells = <2>; - #size-cells = <1>; - - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - eth0: ethernet@c3700000 { - compatible = "cdns,gem"; - reg = <0x0 0xc3700000 0x1000>; - interrupts = ; - clocks = <&clk_bus>, <&clk_bus>; - clock-names = "hclk", "pclk"; - phy-mode = "rmii"; - /* Filled in by boot */ - mac-address = [ 00 00 00 00 00 00 ]; - }; - }; - - amba { - #address-cells = <2>; - #size-cells = <1>; - #interrupt-cells = <3>; - - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - timers: timer@fd100000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x0 0xfd100000 0x1000>; - interrupts = ; - clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>; - clock-names = "timer0clk", "timer1clk", "apb_pclk"; - }; - wdog: watchdog@fd200000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0 0xfd200000 0x1000>; - interrupts = ; - clocks = <&clk_bus>, <&clk_bus>; - clock-names = "wdog_clk", "apb_pclk"; - }; - uart0: serial@fe000000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfe000000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - uart1: serial@fe100000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfe100000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - uart2: serial@fe200000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xfe200000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - spi0: spi@fe800000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x0 0xfe800000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - spi1: spi@fe900000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0x0 0xfe900000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - dmac0: dma@c1128000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xc1128000 0x1000>; - interrupts = ; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - gpio0: gpio@fd400000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd400000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio1: gpio@fd410000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd410000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio2: gpio@fd420000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd420000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio3: gpio@fd430000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd430000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - gpio4: gpio@fd440000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd440000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio5: gpio@fd450000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd450000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio6: gpio@fd460000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd460000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio7: gpio@fd470000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd470000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio8: gpio@fd480000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd480000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio9: gpio@fd490000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd490000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio10: gpio@fd4a0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4a0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio11: gpio@fd4b0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4b0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - gpio12: gpio@fd4c0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4c0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio13: gpio@fd4d0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4d0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio14: gpio@fd4e0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4e0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio15: gpio@fd4f0000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd4f0000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio16: gpio@fd500000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd500000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - status="disabled"; - }; - gpio17: gpio@fd510000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x0 0xfd510000 0x1000>; - clocks = <&clk_bus>; - clock-names = "apb_pclk"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile deleted file mode 100644 index 3e5f2e7a0..000000000 --- a/arch/arm64/boot/dts/marvell/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# Mvebu SoC Family -dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb -dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb -dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-emmc.dtb -dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-v7.dtb -dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-v7-emmc.dtb -dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-turris-mox.dtb -dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-uDPU.dtb -dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb -dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-clearfog-gt-8k.dtb -dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb -dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb -dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb -dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb -dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb -dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb -dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb diff --git a/arch/arm64/boot/dts/marvell/armada-371x.dtsi b/arch/arm64/boot/dts/marvell/armada-371x.dtsi deleted file mode 100644 index dc1182ec9..000000000 --- a/arch/arm64/boot/dts/marvell/armada-371x.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 371x family of SoCs - * (also named 88F3710) - * - * Copyright (C) 2016 Marvell - * - * Gregory CLEMENT - * - */ - -#include "armada-37xx.dtsi" - -/ { - model = "Marvell Armada 3710 SoC"; - compatible = "marvell,armada3710", "marvell,armada3700"; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts deleted file mode 100644 index 3e5789f37..000000000 --- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts +++ /dev/null @@ -1,220 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada 3720 development board - * (DB-88F3720-DDR3) - * Copyright (C) 2016 Marvell - * - * Gregory CLEMENT - * - * This file is compatible with the version 1.4 and the version 2.0 of - * the board, however the CON numbers are different between the 2 - * version - */ - -/dts-v1/; - -#include -#include "armada-372x.dtsi" - -/ { - model = "Marvell Armada 3720 Development Board DB-88F3720-DDR3"; - compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x20000000>; - }; - - exp_usb3_vbus: usb3-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb3-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - gpio = <&gpio_exp 1 GPIO_ACTIVE_HIGH>; - }; - - usb3_phy: usb3-phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <&exp_usb3_vbus>; - }; - - vcc_sd_reg1: regulator { - compatible = "regulator-gpio"; - regulator-name = "vcc_sd1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - - gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - states = <1800000 0x1 - 3300000 0x0>; - enable-active-high; - }; - - vcc_sd_reg2: regulator-vmcc { - compatible = "regulator-fixed"; - regulator-name = "vcc_sd2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - gpio = <&gpio_exp 4 GPIO_ACTIVE_HIGH>; - }; -}; - -/* Gigabit module on CON19(V2.0)/CON21(V1.4) */ -ð0 { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii-id"; - phy = <&phy0>; - status = "okay"; -}; - -/* Gigabit module on CON18(V2.0)/CON20(V1.4) */ -ð1 { - phy-mode = "sgmii"; - phy = <&phy1>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; - - gpio_exp: pca9555@22 { - compatible = "nxp,pca9555"; - gpio-controller; - #gpio-cells = <2>; - - reg = <0x22>; - /* - * IO0_0: PWR_EN_USB2 IO1_0: PWR_EN_VTT - * IO0_1: PWR_EN_USB23 IO1_1: MPCIE_WDISABLE - * IO0_2: PWR_EN_SATA IO1_2: RGMII_DEV_RSTN - * IO0_3: PWR_EN_PCIE IO1_3: SGMII_DEV_RSTN - * IO0_4: PWR_EN_SD - * IO0_5: PWR_EN_EMMC - * IO0_6: PWR_EN_RGMII IO1_6: SATA_USB3.0_SEL - * IO0_7: PWR_EN_SGMII IO1_7: PWR_MCI_PS - */ - }; - - rtc@68 { - /* PT7C4337A from pericom fully compatible with the ds1337 */ - compatible = "dallas,ds1337"; - reg = <0x68>; - }; -}; - -&mdio { - status = "okay"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -/* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */ -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; - reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* CON3 */ -&sata { - status = "okay"; -}; - -&sdhci0 { - non-removable; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - marvell,pad-type = "fixed-1-8v"; - status = "okay"; -}; - -/* SD slot module on CON14(V2.0)/CON15(V1.4) */ -&sdhci1 { - wp-inverted; - cd-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>; - bus-width = <4>; - marvell,pad-type = "sd"; - vqmmc-supply = <&vcc_sd_reg1>; - vmmc-supply = <&vcc_sd_reg2>; - status = "okay"; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi_quad_pins>; - - m25p80@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <108000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "bootloader"; - reg = <0x0 0x200000>; - }; - partition@200000 { - label = "U-boot Env"; - reg = <0x200000 0x10000>; - }; - partition@210000 { - label = "Linux"; - reg = <0x210000 0xDF0000>; - }; - }; - }; -}; - -/* - * Exported on the micro USB connector CON30(V2.0)/CON32(V1.4) through - * an FTDI (also on CON24(V2.0)/CON26(V1.4)). - */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -/* CON26(V2.0)/CON28(V1.4) */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -/* CON27(V2.0)/CON29(V1.4) */ -&usb2 { - status = "okay"; -}; - -/* CON29(V2.0)/CON31(V1.4) */ -&usb3 { - status = "okay"; - usb-phy = <&usb3_phy>; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts deleted file mode 100644 index ec72a11ed..000000000 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Globalscale Marvell ESPRESSOBin Board with eMMC - * Copyright (C) 2018 Marvell - * - * Romain Perier - * Konstantin Porotchkin - * - */ -/* - * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf - */ - -/dts-v1/; - -#include "armada-3720-espressobin.dtsi" - -/ { - model = "Globalscale Marvell ESPRESSOBin Board (eMMC)"; - compatible = "globalscale,espressobin-emmc", "globalscale,espressobin", - "marvell,armada3720", "marvell,armada3710"; -}; - -/* U11 */ -&sdhci0 { - non-removable; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - marvell,xenon-emmc; - marvell,xenon-tun-count = <9>; - marvell,pad-type = "fixed-1-8v"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc_pins>; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - mmccard: mmccard@0 { - compatible = "mmc-card"; - reg = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts deleted file mode 100644 index 215d2f702..000000000 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts +++ /dev/null @@ -1,67 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Globalscale Marvell ESPRESSOBin Board V7 with eMMC - * Copyright (C) 2018 Marvell - * - * Romain Perier - * Konstantin Porotchkin - * - */ -/* - * Schematic available at http://wiki.espressobin.net/tiki-download_file.php?fileId=200 - */ - -/dts-v1/; - -#include "armada-3720-espressobin.dtsi" - -/ { - model = "Globalscale Marvell ESPRESSOBin Board V7 (eMMC)"; - compatible = "globalscale,espressobin-v7-emmc", "globalscale,espressobin-v7", - "globalscale,espressobin", "marvell,armada3720", - "marvell,armada3710"; - - aliases { - /* ethernet1 is wan port */ - ethernet1 = &switch0port3; - ethernet3 = &switch0port1; - }; -}; - -&switch0 { - ports { - switch0port1: port@1 { - reg = <1>; - label = "lan1"; - phy-handle = <&switch0phy0>; - }; - - switch0port3: port@3 { - reg = <3>; - label = "wan"; - phy-handle = <&switch0phy2>; - }; - }; -}; - -/* U11 */ -&sdhci0 { - non-removable; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - marvell,xenon-emmc; - marvell,xenon-tun-count = <9>; - marvell,pad-type = "fixed-1-8v"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc_pins>; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - mmccard: mmccard@0 { - compatible = "mmc-card"; - reg = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts deleted file mode 100644 index b6f4af8eb..000000000 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Globalscale Marvell ESPRESSOBin Board V7 - * Copyright (C) 2018 Marvell - * - * Romain Perier - * Konstantin Porotchkin - * - */ -/* - * Schematic available at http://wiki.espressobin.net/tiki-download_file.php?fileId=200 - */ - -/dts-v1/; - -#include "armada-3720-espressobin.dtsi" - -/ { - model = "Globalscale Marvell ESPRESSOBin Board V7"; - compatible = "globalscale,espressobin-v7", "globalscale,espressobin", - "marvell,armada3720", "marvell,armada3710"; - - aliases { - /* ethernet1 is wan port */ - ethernet1 = &switch0port3; - ethernet3 = &switch0port1; - }; -}; - -&switch0 { - ports { - switch0port1: port@1 { - reg = <1>; - label = "lan1"; - phy-handle = <&switch0phy0>; - }; - - switch0port3: port@3 { - reg = <3>; - label = "wan"; - phy-handle = <&switch0phy2>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts deleted file mode 100644 index 1542d836c..000000000 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Globalscale Marvell ESPRESSOBin Board - * Copyright (C) 2016 Marvell - * - * Romain Perier - * - */ -/* - * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf - */ - -/dts-v1/; - -#include "armada-3720-espressobin.dtsi" - -/ { - model = "Globalscale Marvell ESPRESSOBin Board"; - compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710"; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi deleted file mode 100644 index 0775c16e0..000000000 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi +++ /dev/null @@ -1,185 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Globalscale Marvell ESPRESSOBin Board - * Copyright (C) 2016 Marvell - * - * Romain Perier - * - */ - -#include -#include "armada-372x.dtsi" - -/ { - aliases { - ethernet0 = ð0; - /* for dsa slave device */ - ethernet1 = &switch0port1; - ethernet2 = &switch0port2; - ethernet3 = &switch0port3; - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x20000000>; - }; - - vcc_sd_reg1: regulator { - compatible = "regulator-gpio"; - regulator-name = "vcc_sd1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - - gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - states = <1800000 0x1 - 3300000 0x0>; - enable-active-high; - }; -}; - -/* J9 */ -&pcie0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; - reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; -}; - -/* J6 */ -&sata { - status = "okay"; - phys = <&comphy2 0>; - phy-names = "sata-phy"; -}; - -/* J1 */ -&sdhci1 { - wp-inverted; - bus-width = <4>; - cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>; - marvell,pad-type = "sd"; - vqmmc-supply = <&vcc_sd_reg1>; - - pinctrl-names = "default"; - pinctrl-0 = <&sdio_pins>; - status = "okay"; -}; - -&spi0 { - status = "okay"; - - flash@0 { - reg = <0>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <104000000>; - m25p,fast-read; - }; -}; - -/* Exported on the micro USB connector J5 through an FTDI */ -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -/* - * Connector J17 and J18 expose a number of different features. Some pins are - * multiplexed. This is the case for instance for the following features: - * - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of - * how to enable it. Beware that the signals are 1.8V TTL. - * - I2C - * - SPI - * - MMC - */ - -/* J7 */ -&usb3 { - status = "okay"; -}; - -/* J8 */ -&usb2 { - status = "okay"; -}; - -&mdio { - switch0: switch0@1 { - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - dsa,member = <0 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - switch0port0: port@0 { - reg = <0>; - label = "cpu"; - ethernet = <ð0>; - phy-mode = "rgmii-id"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - switch0port1: port@1 { - reg = <1>; - label = "wan"; - phy-handle = <&switch0phy0>; - }; - - switch0port2: port@2 { - reg = <2>; - label = "lan0"; - phy-handle = <&switch0phy1>; - }; - - switch0port3: port@3 { - reg = <3>; - label = "lan1"; - phy-handle = <&switch0phy2>; - }; - - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch0phy0: switch0phy0@11 { - reg = <0x11>; - }; - switch0phy1: switch0phy1@12 { - reg = <0x12>; - }; - switch0phy2: switch0phy2@13 { - reg = <0x13>; - }; - }; - }; -}; - -ð0 { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>, <&smi_pins>; - phy-mode = "rgmii-id"; - status = "okay"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts deleted file mode 100644 index 00e5dbf4b..000000000 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ /dev/null @@ -1,869 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for CZ.NIC Turris Mox Board - * 2019 by Marek Behun - */ - -/dts-v1/; - -#include -#include -#include -#include "armada-372x.dtsi" - -/ { - model = "CZ.NIC Turris Mox Board"; - compatible = "cznic,turris-mox", "marvell,armada3720", - "marvell,armada3710"; - - aliases { - spi0 = &spi0; - ethernet0 = ð0; - ethernet1 = ð1; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x20000000>; - }; - - leds { - compatible = "gpio-leds"; - red { - label = "mox:red:activity"; - gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - reset { - label = "reset"; - linux,code = ; - gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>; - debounce-interval = <60>; - }; - }; - - exp_usb3_vbus: usb3-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb3-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>; - }; - - vsdc_reg: vsdc-reg { - compatible = "regulator-gpio"; - regulator-name = "vsdc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - - gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - states = <1800000 0x1 - 3300000 0x0>; - enable-active-high; - }; - - vsdio_reg: vsdio-reg { - compatible = "regulator-gpio"; - regulator-name = "vsdio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - - gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - states = <1800000 0x1 - 3300000 0x0>; - enable-active-high; - }; - - sdhci1_pwrseq: sdhci1-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - sfp: sfp { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>; - rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>; - - /* enabled by U-Boot if SFP module is present */ - status = "disabled"; - }; - - firmware { - armada-3700-rwtm { - compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm"; - }; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <100000>; - /delete-property/ mrvl,i2c-fast-mode; - status = "okay"; - - rtc@6f { - compatible = "microchip,mcp7940x"; - reg = <0x6f>; - }; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; - status = "okay"; - reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; - /* - * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property - * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and - * 2 size cells and also expects that the second range starts at 16 MB offset. Also it - * expects that first range uses same address for PCI (child) and CPU (parent) cells (so - * no remapping) and that this address is the lowest from all specified ranges. If these - * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address - * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window - * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB. - * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in - * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix): - * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7 - * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf - * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33 - * Bug related to requirement of same child and parent addresses for first range is fixed - * in U-Boot version 2022.04 by following commit: - * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17 - */ - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */ - 0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */ - - /* enabled by U-Boot if PCIe module is present */ - status = "disabled"; -}; - -&uart0 { - status = "okay"; -}; - -ð0 { - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - phy-mode = "rgmii-id"; - phy-handle = <&phy1>; - status = "okay"; -}; - -ð1 { - phy-mode = "2500base-x"; - managed = "in-band-status"; - phys = <&comphy0 1>; -}; - -&sdhci0 { - wp-inverted; - bus-width = <4>; - cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>; - vqmmc-supply = <&vsdc_reg>; - marvell,pad-type = "sd"; - status = "okay"; -}; - -&sdhci1 { - pinctrl-names = "default"; - pinctrl-0 = <&sdio_pins>; - non-removable; - bus-width = <4>; - marvell,pad-type = "sd"; - vqmmc-supply = <&vsdio_reg>; - mmc-pwrseq = <&sdhci1_pwrseq>; - /* forbid SDR104 for FCC purposes */ - sdhci-caps-mask = <0x2 0x0>; - status = "okay"; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>; - assigned-clocks = <&nb_periph_clk 7>; - assigned-clock-parents = <&tbg 1>; - assigned-clock-rates = <20000000>; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "secure-firmware"; - reg = <0x0 0x20000>; - }; - - partition@20000 { - label = "a53-firmware"; - reg = <0x20000 0x160000>; - }; - - partition@180000 { - label = "u-boot-env"; - reg = <0x180000 0x10000>; - }; - - partition@190000 { - label = "Rescue system"; - reg = <0x190000 0x660000>; - }; - - partition@7f0000 { - label = "dtb"; - reg = <0x7f0000 0x10000>; - }; - }; - }; - - moxtet: moxtet@1 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "cznic,moxtet"; - reg = <1>; - reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>; - spi-max-frequency = <10000000>; - spi-cpol; - spi-cpha; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gpiosb>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - status = "okay"; - - moxtet_sfp: gpio@0 { - compatible = "cznic,moxtet-gpio"; - gpio-controller; - #gpio-cells = <2>; - reg = <0>; - status = "disabled"; - }; - }; -}; - -&usb2 { - status = "okay"; -}; - -&comphy2 { - connector { - compatible = "usb-a-connector"; - phy-supply = <&exp_usb3_vbus>; - }; -}; - -&usb3 { - status = "okay"; - phys = <&comphy2 0>; -}; - -&mdio { - pinctrl-names = "default"; - pinctrl-0 = <&smi_pins>; - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; - - /* switch nodes are enabled by U-Boot if modules are present */ - switch0@10 { - compatible = "marvell,mv88e6190"; - reg = <0x10 0>; - dsa,member = <0 0>; - interrupt-parent = <&moxtet>; - interrupts = ; - status = "disabled"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch0phy1: switch0phy1@1 { - reg = <0x1>; - }; - - switch0phy2: switch0phy2@2 { - reg = <0x2>; - }; - - switch0phy3: switch0phy3@3 { - reg = <0x3>; - }; - - switch0phy4: switch0phy4@4 { - reg = <0x4>; - }; - - switch0phy5: switch0phy5@5 { - reg = <0x5>; - }; - - switch0phy6: switch0phy6@6 { - reg = <0x6>; - }; - - switch0phy7: switch0phy7@7 { - reg = <0x7>; - }; - - switch0phy8: switch0phy8@8 { - reg = <0x8>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <0x1>; - label = "lan1"; - phy-handle = <&switch0phy1>; - }; - - port@2 { - reg = <0x2>; - label = "lan2"; - phy-handle = <&switch0phy2>; - }; - - port@3 { - reg = <0x3>; - label = "lan3"; - phy-handle = <&switch0phy3>; - }; - - port@4 { - reg = <0x4>; - label = "lan4"; - phy-handle = <&switch0phy4>; - }; - - port@5 { - reg = <0x5>; - label = "lan5"; - phy-handle = <&switch0phy5>; - }; - - port@6 { - reg = <0x6>; - label = "lan6"; - phy-handle = <&switch0phy6>; - }; - - port@7 { - reg = <0x7>; - label = "lan7"; - phy-handle = <&switch0phy7>; - }; - - port@8 { - reg = <0x8>; - label = "lan8"; - phy-handle = <&switch0phy8>; - }; - - port@9 { - reg = <0x9>; - label = "cpu"; - ethernet = <ð1>; - phy-mode = "2500base-x"; - managed = "in-band-status"; - }; - - switch0port10: port@a { - reg = <0xa>; - label = "dsa"; - phy-mode = "2500base-x"; - managed = "in-band-status"; - link = <&switch1port9 &switch2port9>; - status = "disabled"; - }; - - port-sfp@a { - reg = <0xa>; - label = "sfp"; - sfp = <&sfp>; - phy-mode = "sgmii"; - managed = "in-band-status"; - status = "disabled"; - }; - }; - }; - - switch0@2 { - compatible = "marvell,mv88e6085"; - reg = <0x2 0>; - dsa,member = <0 0>; - interrupt-parent = <&moxtet>; - interrupts = ; - status = "disabled"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch0phy1_topaz: switch0phy1@11 { - reg = <0x11>; - }; - - switch0phy2_topaz: switch0phy2@12 { - reg = <0x12>; - }; - - switch0phy3_topaz: switch0phy3@13 { - reg = <0x13>; - }; - - switch0phy4_topaz: switch0phy4@14 { - reg = <0x14>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <0x1>; - label = "lan1"; - phy-handle = <&switch0phy1_topaz>; - }; - - port@2 { - reg = <0x2>; - label = "lan2"; - phy-handle = <&switch0phy2_topaz>; - }; - - port@3 { - reg = <0x3>; - label = "lan3"; - phy-handle = <&switch0phy3_topaz>; - }; - - port@4 { - reg = <0x4>; - label = "lan4"; - phy-handle = <&switch0phy4_topaz>; - }; - - port@5 { - reg = <0x5>; - label = "cpu"; - phy-mode = "2500base-x"; - managed = "in-band-status"; - ethernet = <ð1>; - }; - }; - }; - - switch1@11 { - compatible = "marvell,mv88e6190"; - reg = <0x11 0>; - dsa,member = <0 1>; - interrupt-parent = <&moxtet>; - interrupts = ; - status = "disabled"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch1phy1: switch1phy1@1 { - reg = <0x1>; - }; - - switch1phy2: switch1phy2@2 { - reg = <0x2>; - }; - - switch1phy3: switch1phy3@3 { - reg = <0x3>; - }; - - switch1phy4: switch1phy4@4 { - reg = <0x4>; - }; - - switch1phy5: switch1phy5@5 { - reg = <0x5>; - }; - - switch1phy6: switch1phy6@6 { - reg = <0x6>; - }; - - switch1phy7: switch1phy7@7 { - reg = <0x7>; - }; - - switch1phy8: switch1phy8@8 { - reg = <0x8>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <0x1>; - label = "lan9"; - phy-handle = <&switch1phy1>; - }; - - port@2 { - reg = <0x2>; - label = "lan10"; - phy-handle = <&switch1phy2>; - }; - - port@3 { - reg = <0x3>; - label = "lan11"; - phy-handle = <&switch1phy3>; - }; - - port@4 { - reg = <0x4>; - label = "lan12"; - phy-handle = <&switch1phy4>; - }; - - port@5 { - reg = <0x5>; - label = "lan13"; - phy-handle = <&switch1phy5>; - }; - - port@6 { - reg = <0x6>; - label = "lan14"; - phy-handle = <&switch1phy6>; - }; - - port@7 { - reg = <0x7>; - label = "lan15"; - phy-handle = <&switch1phy7>; - }; - - port@8 { - reg = <0x8>; - label = "lan16"; - phy-handle = <&switch1phy8>; - }; - - switch1port9: port@9 { - reg = <0x9>; - label = "dsa"; - phy-mode = "2500base-x"; - managed = "in-band-status"; - link = <&switch0port10>; - }; - - switch1port10: port@a { - reg = <0xa>; - label = "dsa"; - phy-mode = "2500base-x"; - managed = "in-band-status"; - link = <&switch2port9>; - status = "disabled"; - }; - - port-sfp@a { - reg = <0xa>; - label = "sfp"; - sfp = <&sfp>; - phy-mode = "sgmii"; - managed = "in-band-status"; - status = "disabled"; - }; - }; - }; - - switch1@2 { - compatible = "marvell,mv88e6085"; - reg = <0x2 0>; - dsa,member = <0 1>; - interrupt-parent = <&moxtet>; - interrupts = ; - status = "disabled"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch1phy1_topaz: switch1phy1@11 { - reg = <0x11>; - }; - - switch1phy2_topaz: switch1phy2@12 { - reg = <0x12>; - }; - - switch1phy3_topaz: switch1phy3@13 { - reg = <0x13>; - }; - - switch1phy4_topaz: switch1phy4@14 { - reg = <0x14>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <0x1>; - label = "lan9"; - phy-handle = <&switch1phy1_topaz>; - }; - - port@2 { - reg = <0x2>; - label = "lan10"; - phy-handle = <&switch1phy2_topaz>; - }; - - port@3 { - reg = <0x3>; - label = "lan11"; - phy-handle = <&switch1phy3_topaz>; - }; - - port@4 { - reg = <0x4>; - label = "lan12"; - phy-handle = <&switch1phy4_topaz>; - }; - - port@5 { - reg = <0x5>; - label = "dsa"; - phy-mode = "2500base-x"; - managed = "in-band-status"; - link = <&switch0port10>; - }; - }; - }; - - switch2@12 { - compatible = "marvell,mv88e6190"; - reg = <0x12 0>; - dsa,member = <0 2>; - interrupt-parent = <&moxtet>; - interrupts = ; - status = "disabled"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch2phy1: switch2phy1@1 { - reg = <0x1>; - }; - - switch2phy2: switch2phy2@2 { - reg = <0x2>; - }; - - switch2phy3: switch2phy3@3 { - reg = <0x3>; - }; - - switch2phy4: switch2phy4@4 { - reg = <0x4>; - }; - - switch2phy5: switch2phy5@5 { - reg = <0x5>; - }; - - switch2phy6: switch2phy6@6 { - reg = <0x6>; - }; - - switch2phy7: switch2phy7@7 { - reg = <0x7>; - }; - - switch2phy8: switch2phy8@8 { - reg = <0x8>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <0x1>; - label = "lan17"; - phy-handle = <&switch2phy1>; - }; - - port@2 { - reg = <0x2>; - label = "lan18"; - phy-handle = <&switch2phy2>; - }; - - port@3 { - reg = <0x3>; - label = "lan19"; - phy-handle = <&switch2phy3>; - }; - - port@4 { - reg = <0x4>; - label = "lan20"; - phy-handle = <&switch2phy4>; - }; - - port@5 { - reg = <0x5>; - label = "lan21"; - phy-handle = <&switch2phy5>; - }; - - port@6 { - reg = <0x6>; - label = "lan22"; - phy-handle = <&switch2phy6>; - }; - - port@7 { - reg = <0x7>; - label = "lan23"; - phy-handle = <&switch2phy7>; - }; - - port@8 { - reg = <0x8>; - label = "lan24"; - phy-handle = <&switch2phy8>; - }; - - switch2port9: port@9 { - reg = <0x9>; - label = "dsa"; - phy-mode = "2500base-x"; - managed = "in-band-status"; - link = <&switch1port10 &switch0port10>; - }; - - port-sfp@a { - reg = <0xa>; - label = "sfp"; - sfp = <&sfp>; - phy-mode = "sgmii"; - managed = "in-band-status"; - status = "disabled"; - }; - }; - }; - - switch2@2 { - compatible = "marvell,mv88e6085"; - reg = <0x2 0>; - dsa,member = <0 2>; - interrupt-parent = <&moxtet>; - interrupts = ; - status = "disabled"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch2phy1_topaz: switch2phy1@11 { - reg = <0x11>; - }; - - switch2phy2_topaz: switch2phy2@12 { - reg = <0x12>; - }; - - switch2phy3_topaz: switch2phy3@13 { - reg = <0x13>; - }; - - switch2phy4_topaz: switch2phy4@14 { - reg = <0x14>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <0x1>; - label = "lan17"; - phy-handle = <&switch2phy1_topaz>; - }; - - port@2 { - reg = <0x2>; - label = "lan18"; - phy-handle = <&switch2phy2_topaz>; - }; - - port@3 { - reg = <0x3>; - label = "lan19"; - phy-handle = <&switch2phy3_topaz>; - }; - - port@4 { - reg = <0x4>; - label = "lan20"; - phy-handle = <&switch2phy4_topaz>; - }; - - port@5 { - reg = <0x5>; - label = "dsa"; - phy-mode = "2500base-x"; - managed = "in-band-status"; - link = <&switch1port10 &switch0port10>; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts deleted file mode 100644 index 95d46e8d0..000000000 --- a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts +++ /dev/null @@ -1,188 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device tree for the uDPU board. - * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3) - * Copyright (C) 2016 Marvell - * Copyright (C) 2019 Methode Electronics - * Copyright (C) 2019 Telus - * - * Vladimir Vid - */ - -/dts-v1/; - -#include -#include "armada-372x.dtsi" - -/ { - model = "Methode uDPU Board"; - compatible = "methode,udpu", "marvell,armada3720"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x20000000>; - }; - - leds { - pinctrl-names = "default"; - compatible = "gpio-leds"; - - power1 { - label = "udpu:green:power"; - gpios = <&gpionb 11 GPIO_ACTIVE_LOW>; - }; - - power2 { - label = "udpu:red:power"; - gpios = <&gpionb 12 GPIO_ACTIVE_LOW>; - }; - - network1 { - label = "udpu:green:network"; - gpios = <&gpionb 13 GPIO_ACTIVE_LOW>; - }; - - network2 { - label = "udpu:red:network"; - gpios = <&gpionb 14 GPIO_ACTIVE_LOW>; - }; - - alarm1 { - label = "udpu:green:alarm"; - gpios = <&gpionb 15 GPIO_ACTIVE_LOW>; - }; - - alarm2 { - label = "udpu:red:alarm"; - gpios = <&gpionb 16 GPIO_ACTIVE_LOW>; - }; - }; - - sfp_eth0: sfp-eth0 { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - los-gpio = <&gpiosb 2 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <3000>; - }; - - sfp_eth1: sfp-eth1 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <3000>; - }; -}; - -&sdhci0 { - status = "okay"; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - marvell,pad-type = "fixed-1-8v"; - non-removable; - no-sd; - no-sdio; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi_quad_pins>; - - m25p80@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <54000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - /* only bootloader is located on the SPI */ - partition@0 { - label = "uboot"; - reg = <0 0x400000>; - }; - }; - }; -}; - -&pinctrl_nb { - i2c1_recovery_pins: i2c1-recovery-pins { - groups = "i2c1"; - function = "gpio"; - }; - - i2c2_recovery_pins: i2c2-recovery-pins { - groups = "i2c2"; - function = "gpio"; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default", "recovery"; - pinctrl-0 = <&i2c1_pins>; - pinctrl-1 = <&i2c1_recovery_pins>; - /delete-property/mrvl,i2c-fast-mode; - scl-gpios = <&gpionb 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpionb 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default", "recovery"; - pinctrl-0 = <&i2c2_pins>; - pinctrl-1 = <&i2c2_recovery_pins>; - /delete-property/mrvl,i2c-fast-mode; - scl-gpios = <&gpionb 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpionb 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - - lm75@48 { - status = "okay"; - compatible = "lm75"; - reg = <0x48>; - }; - - lm75@49 { - status = "okay"; - compatible = "lm75"; - reg = <0x49>; - }; -}; - -ð0 { - phy-mode = "sgmii"; - status = "okay"; - managed = "in-band-status"; - phys = <&comphy1 0>; - sfp = <&sfp_eth0>; -}; - -ð1 { - phy-mode = "sgmii"; - status = "okay"; - managed = "in-band-status"; - phys = <&comphy0 1>; - sfp = <&sfp_eth1>; -}; - -&usb3 { - status = "okay"; - phys = <&usb2_utmi_otg_phy>; - phy-names = "usb2-utmi-otg-phy"; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-372x.dtsi b/arch/arm64/boot/dts/marvell/armada-372x.dtsi deleted file mode 100644 index 5ce55bdbb..000000000 --- a/arch/arm64/boot/dts/marvell/armada-372x.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 372x family of SoCs - * (also named 88F3720) - * - * Copyright (C) 2016 Marvell - * - * Gregory CLEMENT - * - */ - -#include "armada-37xx.dtsi" - -/ { - model = "Marvell Armada 3720 SoC"; - compatible = "marvell,armada3720", "marvell,armada3710"; - - cpus { - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - clocks = <&nb_periph_clk 16>; - enable-method = "psci"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi deleted file mode 100644 index 0f4bcd15d..000000000 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ /dev/null @@ -1,520 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 37xx family of SoCs. - * - * Copyright (C) 2016 Marvell - * - * Gregory CLEMENT - * - */ - -#include - -/ { - model = "Marvell Armada 37xx SoC"; - compatible = "marvell,armada3700"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* - * The PSCI firmware region depicted below is the default one - * and should be updated by the bootloader. - */ - psci-area@4000000 { - reg = <0 0x4000000 0 0x200000>; - no-map; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0>; - clocks = <&nb_periph_clk 16>; - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - internal-regs@d0000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - /* 32M internal register @ 0xd000_0000 */ - ranges = <0x0 0x0 0xd0000000 0x2000000>; - - wdt: watchdog@8300 { - compatible = "marvell,armada-3700-wdt"; - reg = <0x8300 0x40>; - marvell,system-controller = <&cpu_misc>; - clocks = <&xtalclk>; - }; - - cpu_misc: system-controller@d000 { - compatible = "marvell,armada-3700-cpu-misc", - "syscon"; - reg = <0xd000 0x1000>; - }; - - spi0: spi@10600 { - compatible = "marvell,armada-3700-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x10600 0xA00>; - clocks = <&nb_periph_clk 7>; - interrupts = ; - num-cs = <4>; - status = "disabled"; - }; - - i2c0: i2c@11000 { - compatible = "marvell,armada-3700-i2c"; - reg = <0x11000 0x24>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&nb_periph_clk 10>; - interrupts = ; - mrvl,i2c-fast-mode; - status = "disabled"; - }; - - i2c1: i2c@11080 { - compatible = "marvell,armada-3700-i2c"; - reg = <0x11080 0x24>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&nb_periph_clk 9>; - interrupts = ; - mrvl,i2c-fast-mode; - status = "disabled"; - }; - - avs: avs@11500 { - compatible = "marvell,armada-3700-avs", - "syscon"; - reg = <0x11500 0x40>; - }; - - uart0: serial@12000 { - compatible = "marvell,armada-3700-uart"; - reg = <0x12000 0x18>; - clocks = <&xtalclk>; - interrupts = - , - , - ; - interrupt-names = "uart-sum", "uart-tx", "uart-rx"; - status = "disabled"; - }; - - uart1: serial@12200 { - compatible = "marvell,armada-3700-uart-ext"; - reg = <0x12200 0x30>; - clocks = <&xtalclk>; - interrupts = - , - ; - interrupt-names = "uart-tx", "uart-rx"; - status = "disabled"; - }; - - nb_periph_clk: nb-periph-clk@13000 { - compatible = "marvell,armada-3700-periph-clock-nb", - "syscon"; - reg = <0x13000 0x100>; - clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, - <&tbg 3>, <&xtalclk>; - #clock-cells = <1>; - }; - - sb_periph_clk: sb-periph-clk@18000 { - compatible = "marvell,armada-3700-periph-clock-sb"; - reg = <0x18000 0x100>; - clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, - <&tbg 3>, <&xtalclk>; - #clock-cells = <1>; - }; - - tbg: tbg@13200 { - compatible = "marvell,armada-3700-tbg-clock"; - reg = <0x13200 0x100>; - clocks = <&xtalclk>; - #clock-cells = <1>; - }; - - pinctrl_nb: pinctrl@13800 { - compatible = "marvell,armada3710-nb-pinctrl", - "syscon", "simple-mfd"; - reg = <0x13800 0x100>, <0x13C00 0x20>; - /* MPP1[19:0] */ - gpionb: gpio { - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_nb 0 0 36>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - xtalclk: xtal-clk { - compatible = "marvell,armada-3700-xtal-clock"; - clock-output-names = "xtal"; - #clock-cells = <0>; - }; - - spi_quad_pins: spi-quad-pins { - groups = "spi_quad"; - function = "spi"; - }; - - spi_cs1_pins: spi-cs1-pins { - groups = "spi_cs1"; - function = "spi"; - }; - - i2c1_pins: i2c1-pins { - groups = "i2c1"; - function = "i2c"; - }; - - i2c2_pins: i2c2-pins { - groups = "i2c2"; - function = "i2c"; - }; - - uart1_pins: uart1-pins { - groups = "uart1"; - function = "uart"; - }; - - uart2_pins: uart2-pins { - groups = "uart2"; - function = "uart"; - }; - - mmc_pins: mmc-pins { - groups = "emmc_nb"; - function = "emmc"; - }; - }; - - nb_pm: syscon@14000 { - compatible = "marvell,armada-3700-nb-pm", - "syscon"; - reg = <0x14000 0x60>; - }; - - comphy: phy@18300 { - compatible = "marvell,comphy-a3700"; - reg = <0x18300 0x300>, - <0x1F000 0x400>, - <0x5C000 0x400>, - <0xe0178 0x8>; - reg-names = "comphy", - "lane1_pcie_gbe", - "lane0_usb3_gbe", - "lane2_sata_usb3"; - #address-cells = <1>; - #size-cells = <0>; - - comphy0: phy@0 { - reg = <0>; - #phy-cells = <1>; - }; - - comphy1: phy@1 { - reg = <1>; - #phy-cells = <1>; - }; - - comphy2: phy@2 { - reg = <2>; - #phy-cells = <1>; - }; - }; - - pinctrl_sb: pinctrl@18800 { - compatible = "marvell,armada3710-sb-pinctrl", - "syscon", "simple-mfd"; - reg = <0x18800 0x100>, <0x18C00 0x20>; - /* MPP2[23:0] */ - gpiosb: gpio { - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_sb 0 0 30>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = - , - , - , - , - ; - }; - - rgmii_pins: mii-pins { - groups = "rgmii"; - function = "mii"; - }; - - smi_pins: smi-pins { - groups = "smi"; - function = "smi"; - }; - - sdio_pins: sdio-pins { - groups = "sdio_sb"; - function = "sdio"; - }; - - pcie_reset_pins: pcie-reset-pins { - groups = "pcie1"; /* this actually controls "pcie1_reset" */ - function = "gpio"; - }; - - pcie_clkreq_pins: pcie-clkreq-pins { - groups = "pcie1_clkreq"; - function = "pcie"; - }; - }; - - eth0: ethernet@30000 { - compatible = "marvell,armada-3700-neta"; - reg = <0x30000 0x4000>; - interrupts = ; - clocks = <&sb_periph_clk 8>; - status = "disabled"; - }; - - mdio: mdio@32004 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,orion-mdio"; - reg = <0x32004 0x4>; - }; - - eth1: ethernet@40000 { - compatible = "marvell,armada-3700-neta"; - reg = <0x40000 0x4000>; - interrupts = ; - clocks = <&sb_periph_clk 7>; - status = "disabled"; - }; - - usb3: usb@58000 { - compatible = "marvell,armada3700-xhci", - "generic-xhci"; - reg = <0x58000 0x4000>; - marvell,usb-misc-reg = <&usb32_syscon>; - interrupts = ; - clocks = <&sb_periph_clk 12>; - phys = <&comphy0 0>, <&usb2_utmi_otg_phy>; - phy-names = "usb3-phy", "usb2-utmi-otg-phy"; - status = "disabled"; - }; - - usb2_utmi_otg_phy: phy@5d000 { - compatible = "marvell,a3700-utmi-otg-phy"; - reg = <0x5d000 0x800>; - marvell,usb-misc-reg = <&usb32_syscon>; - #phy-cells = <0>; - }; - - usb32_syscon: system-controller@5d800 { - compatible = "marvell,armada-3700-usb2-host-device-misc", - "syscon"; - reg = <0x5d800 0x800>; - }; - - usb2: usb@5e000 { - compatible = "marvell,armada-3700-ehci"; - reg = <0x5e000 0x1000>; - marvell,usb-misc-reg = <&usb2_syscon>; - interrupts = ; - phys = <&usb2_utmi_host_phy>; - phy-names = "usb2-utmi-host-phy"; - status = "disabled"; - }; - - usb2_utmi_host_phy: phy@5f000 { - compatible = "marvell,a3700-utmi-host-phy"; - reg = <0x5f000 0x800>; - marvell,usb-misc-reg = <&usb2_syscon>; - #phy-cells = <0>; - }; - - usb2_syscon: system-controller@5f800 { - compatible = "marvell,armada-3700-usb2-host-misc", - "syscon"; - reg = <0x5f800 0x800>; - }; - - xor@60900 { - compatible = "marvell,armada-3700-xor"; - reg = <0x60900 0x100>, - <0x60b00 0x100>; - - xor10 { - interrupts = ; - }; - xor11 { - interrupts = ; - }; - }; - - crypto: crypto@90000 { - compatible = "inside-secure,safexcel-eip97ies"; - reg = <0x90000 0x20000>; - interrupts = , - , - , - , - , - ; - interrupt-names = "mem", "ring0", "ring1", - "ring2", "ring3", "eip"; - clocks = <&nb_periph_clk 15>; - }; - - rwtm: mailbox@b0000 { - compatible = "marvell,armada-3700-rwtm-mailbox"; - reg = <0xb0000 0x100>; - interrupts = ; - #mbox-cells = <1>; - }; - - sdhci1: sdhci@d0000 { - compatible = "marvell,armada-3700-sdhci", - "marvell,sdhci-xenon"; - reg = <0xd0000 0x300>, - <0x1e808 0x4>; - interrupts = ; - clocks = <&nb_periph_clk 0>; - clock-names = "core"; - status = "disabled"; - }; - - sdhci0: sdhci@d8000 { - compatible = "marvell,armada-3700-sdhci", - "marvell,sdhci-xenon"; - reg = <0xd8000 0x300>, - <0x17808 0x4>; - interrupts = ; - clocks = <&nb_periph_clk 0>; - clock-names = "core"; - status = "disabled"; - }; - - sata: sata@e0000 { - compatible = "marvell,armada-3700-ahci"; - reg = <0xe0000 0x178>; - interrupts = ; - clocks = <&nb_periph_clk 1>; - status = "disabled"; - }; - - gic: interrupt-controller@1d00000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x1d00000 0x10000>, /* GICD */ - <0x1d40000 0x40000>, /* GICR */ - <0x1d80000 0x2000>, /* GICC */ - <0x1d90000 0x2000>, /* GICH */ - <0x1da0000 0x20000>; /* GICV */ - interrupts = ; - }; - }; - - pcie0: pcie@d0070000 { - compatible = "marvell,armada-3700-pcie"; - device_type = "pci"; - status = "disabled"; - reg = <0 0xd0070000 0 0x20000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - interrupts = ; - #interrupt-cells = <1>; - msi-parent = <&pcie0>; - msi-controller; - /* - * The 128 MiB address range [0xe8000000-0xf0000000] is - * dedicated for PCIe and can be assigned to 8 windows - * with size a power of two. Use one 64 KiB window for - * IO at the end and the remaining seven windows - * (totaling 127 MiB) for MEM. - */ - ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */ - 0x81000000 0 0x00000000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */ - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - max-link-speed = <2>; - phys = <&comphy1 0>; - pcie_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - }; - - firmware { - armada-3700-rwtm { - compatible = "marvell,armada-3700-rwtm-firmware"; - mboxes = <&rwtm 0>; - status = "okay"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-7020.dtsi b/arch/arm64/boot/dts/marvell/armada-7020.dtsi deleted file mode 100644 index 4e46326dd..000000000 --- a/arch/arm64/boot/dts/marvell/armada-7020.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 7020 SoC, made of an AP806 Dual and - * one CP110. - */ - -#include "armada-ap806-dual.dtsi" -#include "armada-70x0.dtsi" - -/ { - model = "Marvell Armada 7020"; - compatible = "marvell,armada7020", "marvell,armada-ap806-dual", - "marvell,armada-ap806"; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts deleted file mode 100644 index a7eb4e769..000000000 --- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts +++ /dev/null @@ -1,302 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada 7040 Development board platform - */ - -#include -#include "armada-7040.dtsi" - -/ { - model = "Marvell Armada 7040 DB board"; - compatible = "marvell,armada7040-db", "marvell,armada7040", - "marvell,armada-ap806-quad", "marvell,armada-ap806"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - aliases { - ethernet0 = &cp0_eth0; - ethernet1 = &cp0_eth1; - ethernet2 = &cp0_eth2; - }; - - cp0_exp_usb3_0_current_regulator: gpio-regulator { - compatible = "regulator-gpio"; - regulator-name = "cp0-usb3-0-current-regulator"; - regulator-type = "current"; - regulator-min-microamp = <500000>; - regulator-max-microamp = <900000>; - gpios = <&expander0 4 GPIO_ACTIVE_HIGH>; - states = <500000 0x0 - 900000 0x1>; - enable-active-high; - gpios-states = <0>; - }; - - cp0_exp_usb3_1_current_regulator: gpio-regulator { - compatible = "regulator-gpio"; - regulator-name = "cp0-usb3-1-current-regulator"; - regulator-type = "current"; - regulator-min-microamp = <500000>; - regulator-max-microamp = <900000>; - gpios = <&expander0 5 GPIO_ACTIVE_HIGH>; - states = <500000 0x0 - 900000 0x1>; - enable-active-high; - gpios-states = <0>; - }; - - cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb3h0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; - vin-supply = <&cp0_exp_usb3_0_current_regulator>; - }; - - cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb3h1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; - vin-supply = <&cp0_exp_usb3_1_current_regulator>; - }; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x200000>; - }; - partition@400000 { - label = "Filesystem"; - reg = <0x200000 0xce0000>; - }; - }; - }; -}; - -&uart0 { - status = "okay"; - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - - -&cp0_pcie2 { - status = "okay"; - phys = <&cp0_comphy5 2>; - phy-names = "cp0-pcie2-x1-phy"; -}; - -&cp0_i2c0 { - status = "okay"; - clock-frequency = <100000>; - - expander0: pca9555@21 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x21>; - /* - * IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect - * IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit - * IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN - * IO0_3: USB2_DEVICE_DETECT - * IO0_4: GPIO_0 IO1_4: SD_Status - * IO0_5: GPIO_1 IO1_5: LDO_5V_Enable - * IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC - * IO0_7: IO1_7: SDIO_Vcntrl - */ - }; -}; - -&cp0_nand_controller { - /* - * SPI on CPM and NAND have common pins on this board. We can - * use only one at a time. To enable the NAND (which will - * disable the SPI), the "status = "okay";" line have to be - * added here. - */ - pinctrl-0 = <&nand_pins>, <&nand_rb>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x200000>; - }; - - partition@200000 { - label = "Linux"; - reg = <0x200000 0xe00000>; - }; - - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - - }; - }; -}; - -&cp0_spi1 { - status = "okay"; - - spi-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-max-frequency = <20000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0x0 0x200000>; - }; - - partition@400000 { - label = "Filesystem"; - reg = <0x200000 0xe00000>; - }; - }; - }; -}; - -&cp0_sata0 { - status = "okay"; - - sata-port@1 { - phys = <&cp0_comphy3 1>; - phy-names = "cp0-sata0-1-phy"; - }; -}; - -&cp0_comphy1 { - cp0_usbh0_con: connector { - compatible = "usb-a-connector"; - phy-supply = <&cp0_reg_usb3_0_vbus>; - }; -}; - -&cp0_usb3_0 { - phys = <&cp0_comphy1 0>; - phy-names = "cp0-usb3h0-comphy"; - status = "okay"; -}; - -&cp0_comphy4 { - cp0_usbh1_con: connector { - compatible = "usb-a-connector"; - phy-supply = <&cp0_reg_usb3_1_vbus>; - }; -}; - -&cp0_usb3_1 { - phys = <&cp0_comphy4 1>; - phy-names = "cp0-usb3h1-comphy"; - status = "okay"; -}; - -&ap_sdhci0 { - status = "okay"; - bus-width = <4>; - no-1-8-v; - non-removable; -}; - -&cp0_sdhci0 { - status = "okay"; - bus-width = <4>; - no-1-8-v; - cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>; -}; - -&cp0_mdio { - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&cp0_ethernet { - status = "okay"; -}; - -&cp0_eth0 { - status = "okay"; - /* Network PHY */ - phy-mode = "10gbase-kr"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp0_comphy2 0>; - - fixed-link { - speed = <10000>; - full-duplex; - }; -}; - -&cp0_eth1 { - status = "okay"; - /* Network PHY */ - phy = <&phy0>; - phy-mode = "sgmii"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp0_comphy0 1>; -}; - -&cp0_eth2 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-7040.dtsi b/arch/arm64/boot/dts/marvell/armada-7040.dtsi deleted file mode 100644 index 2f440711d..000000000 --- a/arch/arm64/boot/dts/marvell/armada-7040.dtsi +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 7040 SoC, made of an AP806 Quad and - * one CP110. - */ - -#include "armada-ap806-quad.dtsi" -#include "armada-70x0.dtsi" - -/ { - model = "Marvell Armada 7040"; - compatible = "marvell,armada7040", "marvell,armada-ap806-quad", - "marvell,armada-ap806"; -}; - -&cp0_pcie0 { - iommu-map = - <0x0 &smmu 0x480 0x20>, - <0x100 &smmu 0x4a0 0x20>, - <0x200 &smmu 0x4c0 0x20>; - iommu-map-mask = <0x031f>; -}; - -&cp0_sata0 { - iommus = <&smmu 0x444>; -}; - -&cp0_sdhci0 { - iommus = <&smmu 0x445>; -}; - -&cp0_usb3_0 { - iommus = <&smmu 0x440>; -}; - -&cp0_usb3_1 { - iommus = <&smmu 0x441>; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi deleted file mode 100644 index 293403a1a..000000000 --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 70x0 SoC - */ - -/ { - aliases { - gpio1 = &cp0_gpio1; - gpio2 = &cp0_gpio2; - spi1 = &cp0_spi0; - spi2 = &cp0_spi1; - }; -}; - -/* - * Instantiate the CP110 - */ -#define CP11X_NAME cp0 -#define CP11X_BASE f2000000 -#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000)) -#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 -#define CP11X_PCIE0_BASE f2600000 -#define CP11X_PCIE1_BASE f2620000 -#define CP11X_PCIE2_BASE f2640000 - -#include "armada-cp110.dtsi" - -#undef CP11X_NAME -#undef CP11X_BASE -#undef CP11X_PCIEx_MEM_BASE -#undef CP11X_PCIEx_MEM_SIZE -#undef CP11X_PCIE0_BASE -#undef CP11X_PCIE1_BASE -#undef CP11X_PCIE2_BASE - -&cp0_gpio1 { - status = "okay"; -}; - -&cp0_gpio2 { - status = "okay"; -}; - -&cp0_syscon0 { - cp0_pinctrl: pinctrl { - compatible = "marvell,armada-7k-pinctrl"; - - nand_pins: nand-pins { - marvell,pins = - "mpp15", "mpp16", "mpp17", "mpp18", - "mpp19", "mpp20", "mpp21", "mpp22", - "mpp23", "mpp24", "mpp25", "mpp26", - "mpp27"; - marvell,function = "dev"; - }; - - nand_rb: nand-rb { - marvell,pins = "mpp13"; - marvell,function = "nf"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-8020.dtsi b/arch/arm64/boot/dts/marvell/armada-8020.dtsi deleted file mode 100644 index ba1307c0f..000000000 --- a/arch/arm64/boot/dts/marvell/armada-8020.dtsi +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and - * two CP110. - */ - -#include "armada-ap806-dual.dtsi" -#include "armada-80x0.dtsi" - -/ { - model = "Marvell Armada 8020"; - compatible = "marvell,armada8020", "marvell,armada-ap806-dual", - "marvell,armada-ap806"; -}; - -/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock - * in CP master is not connected (by package) to the oscillator. So - * disable it. However, the RTC clock in CP slave is connected to the - * oscillator so this one is let enabled. - */ - -&cp0_rtc { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts deleted file mode 100644 index eb01cc96b..000000000 --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts +++ /dev/null @@ -1,483 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2018 SolidRun ltd. - * Based on Marvell MACCHIATOBin board - * - * Device Tree file for SolidRun's ClearFog GT 8K - */ - -#include "armada-8040.dtsi" - -#include -#include - -/ { - model = "SolidRun ClearFog GT 8K"; - compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040", - "marvell,armada-ap806-quad", "marvell,armada-ap806"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@00000000 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - aliases { - ethernet0 = &cp1_eth1; - ethernet1 = &cp0_eth0; - ethernet2 = &cp1_eth2; - }; - - v_3_3: regulator-3-3v { - compatible = "regulator-fixed"; - regulator-name = "v_3_3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - status = "okay"; - }; - - v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { - compatible = "regulator-fixed"; - gpio = <&cp0_gpio2 15 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_xhci_vbus_pins>; - regulator-name = "v_5v0_usb3_hst_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - status = "okay"; - }; - - sfp_cp0_eth0: sfp-cp0-eth0 { - compatible = "sff,sfp"; - i2c-bus = <&cp0_i2c1>; - mod-def0-gpio = <&cp0_gpio2 17 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_sfp_present_pins &cp1_sfp_tx_disable_pins>; - maximum-power-milliwatt = <2000>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&cp0_led0_pins - &cp0_led1_pins>; - pinctrl-names = "default"; - /* No designated function for these LEDs at the moment */ - led0 { - label = "clearfog-gt-8k:green:led0"; - gpios = <&cp0_gpio2 8 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - led1 { - label = "clearfog-gt-8k:green:led1"; - gpios = <&cp0_gpio2 9 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&cp0_gpio_reset_pins &cp1_wps_button_pins>; - pinctrl-names = "default"; - - button_0 { - /* The rear button */ - label = "Rear Button"; - gpios = <&cp0_gpio2 7 GPIO_ACTIVE_LOW>; - linux,can-disable; - linux,code = ; - }; - - button_1 { - /* The wps button */ - label = "WPS Button"; - gpios = <&cp1_gpio1 30 GPIO_ACTIVE_LOW>; - linux,can-disable; - linux,code = ; - }; - }; -}; - -&uart0 { - status = "okay"; - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - -&ap_sdhci0 { - bus-width = <8>; - no-1-8-v; - no-sd; - no-sdio; - non-removable; - status = "okay"; - vqmmc-supply = <&v_3_3>; -}; - -&cp0_i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_i2c0_pins>; - status = "okay"; -}; - -&cp0_i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_i2c1_pins>; - status = "okay"; -}; - -&cp0_pinctrl { - /* - * MPP Bus: - * [0-31] = 0xff: Keep default CP0_shared_pins: - * [11] CLKOUT_MPP_11 (out) - * [23] LINK_RD_IN_CP2CP (in) - * [25] CLKOUT_MPP_25 (out) - * [29] AVS_FB_IN_CP2CP (in) - * [32, 33, 34] pci0/1/2 reset - * [35-38] CP0 I2C1 and I2C0 - * [39] GPIO reset button - * [40,41] LED0 and LED1 - * [43] 1512 phy reset - * [47] USB VBUS EN (active low) - * [48] FAN PWM - * [49] SFP+ present signal - * [50] TPM interrupt - * [51] WLAN0 disable - * [52] WLAN1 disable - * [53] LTE disable - * [54] NFC reset - * [55] Micro SD card detect - * [56-61] Micro SD - */ - - cp0_pci0_reset_pins: pci0-reset-pins { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; - - cp0_pci1_reset_pins: pci1-reset-pins { - marvell,pins = "mpp33"; - marvell,function = "gpio"; - }; - - cp0_pci2_reset_pins: pci2-reset-pins { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - - cp0_i2c1_pins: i2c1-pins { - marvell,pins = "mpp35", "mpp36"; - marvell,function = "i2c1"; - }; - - cp0_i2c0_pins: i2c0-pins { - marvell,pins = "mpp37", "mpp38"; - marvell,function = "i2c0"; - }; - - cp0_gpio_reset_pins: gpio-reset-pins { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - cp0_led0_pins: led0-pins { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - - cp0_led1_pins: led1-pins { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - cp0_copper_eth_phy_reset: copper-eth-phy-reset { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - - cp0_xhci_vbus_pins: xhci0-vbus-pins { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - cp0_fan_pwm_pins: fan-pwm-pins { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - cp0_sfp_present_pins: sfp-present-pins { - marvell,pins = "mpp49"; - marvell,function = "gpio"; - }; - - cp0_tpm_irq_pins: tpm-irq-pins { - marvell,pins = "mpp50"; - marvell,function = "gpio"; - }; - - cp0_wlan_disable_pins: wlan-disable-pins { - marvell,pins = "mpp51"; - marvell,function = "gpio"; - }; - - cp0_sdhci_pins: sdhci-pins { - marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59", - "mpp60", "mpp61"; - marvell,function = "sdio"; - }; -}; - -&cp0_pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&cp0_pci0_reset_pins &cp0_wlan_disable_pins>; - reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>; - phys = <&cp0_comphy0 0>; - phy-names = "cp0-pcie0-x1-phy"; - status = "okay"; -}; - -&cp0_gpio2 { - sata_reset { - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - output-high; - }; - - lte_reset { - gpio-hog; - gpios = <2 GPIO_ACTIVE_LOW>; - output-low; - }; - - wlan_disable { - gpio-hog; - gpios = <19 GPIO_ACTIVE_LOW>; - output-low; - }; - - lte_disable { - gpio-hog; - gpios = <21 GPIO_ACTIVE_LOW>; - output-low; - }; -}; - -&cp0_ethernet { - status = "okay"; -}; - -/* SFP */ -&cp0_eth0 { - status = "okay"; - phy-mode = "10gbase-r"; - managed = "in-band-status"; - phys = <&cp0_comphy2 0>; - sfp = <&sfp_cp0_eth0>; -}; - -&cp0_sdhci0 { - broken-cd; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_sdhci_pins>; - status = "okay"; - vqmmc-supply = <&v_3_3>; -}; - -&cp0_usb3_1 { - status = "okay"; -}; - -&cp1_pinctrl { - /* - * MPP Bus: - * [0-5] TDM - * [6] VHV Enable - * [7] CP1 SPI0 CSn1 (FXS) - * [8] CP1 SPI0 CSn0 (TPM) - * [9.11]CP1 SPI0 MOSI/MISO/CLK - * [13] CP1 SPI1 MISO (TDM and SPI ROM shared) - * [14] CP1 SPI1 CS0n (64Mb SPI ROM) - * [15] CP1 SPI1 MOSI (TDM and SPI ROM shared) - * [16] CP1 SPI1 CLK (TDM and SPI ROM shared) - * [24] Topaz switch reset - * [26] Buzzer - * [27] CP1 SMI MDIO - * [28] CP1 SMI MDC - * [29] CP0 10G SFP TX Disable - * [30] WPS button - * [31] Front panel button - */ - - cp1_spi1_pins: spi1-pins { - marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; - marvell,function = "spi1"; - }; - - cp1_switch_reset_pins: switch-reset-pins { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - cp1_ge_mdio_pins: ge-mdio-pins { - marvell,pins = "mpp27", "mpp28"; - marvell,function = "ge"; - }; - - cp1_sfp_tx_disable_pins: sfp-tx-disable-pins { - marvell,pins = "mpp29"; - marvell,function = "gpio"; - }; - - cp1_wps_button_pins: wps-button-pins { - marvell,pins = "mpp30"; - marvell,function = "gpio"; - }; -}; - -&cp1_sata0 { - pinctrl-0 = <&cp0_pci1_reset_pins>; - status = "okay"; - - sata-port@1 { - phys = <&cp1_comphy0 1>; - phy-names = "cp1-sata0-1-phy"; - }; -}; - -&cp1_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&cp1_ge_mdio_pins>; - status = "okay"; - - ge_phy: ethernet-phy@0 { - /* LED0 - GB link - * LED1 - on: link, blink: activity - */ - marvell,reg-init = <3 16 0 0x1017>; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_copper_eth_phy_reset>; - reset-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <10000>; - }; - - switch0: switch0@4 { - compatible = "marvell,mv88e6085"; - reg = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&cp1_switch_reset_pins>; - reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - label = "lan2"; - phy-handle = <&switch0phy0>; - }; - - port@2 { - reg = <2>; - label = "lan1"; - phy-handle = <&switch0phy1>; - }; - - port@3 { - reg = <3>; - label = "lan4"; - phy-handle = <&switch0phy2>; - }; - - port@4 { - reg = <4>; - label = "lan3"; - phy-handle = <&switch0phy3>; - }; - - port@5 { - reg = <5>; - label = "cpu"; - ethernet = <&cp1_eth2>; - phy-mode = "2500base-x"; - managed = "in-band-status"; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch0phy0: switch0phy0@11 { - reg = <0x11>; - }; - - switch0phy1: switch0phy1@12 { - reg = <0x12>; - }; - - switch0phy2: switch0phy2@13 { - reg = <0x13>; - }; - - switch0phy3: switch0phy3@14 { - reg = <0x14>; - }; - }; - }; -}; - -&cp1_ethernet { - status = "okay"; -}; - -/* 1G copper */ -&cp1_eth1 { - status = "okay"; - phy-mode = "sgmii"; - phy = <&ge_phy>; - phys = <&cp1_comphy3 1>; -}; - -/* Switch uplink */ -&cp1_eth2 { - status = "okay"; - phy-mode = "2500base-x"; - phys = <&cp1_comphy5 2>; - managed = "in-band-status"; -}; - -&cp1_spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&cp1_spi1_pins>; - status = "okay"; - - spi-flash@0 { - compatible = "st,w25q32"; - spi-max-frequency = <50000000>; - reg = <0>; - }; -}; - -&cp1_comphy2 { - cp1_usbh0_con: connector { - compatible = "usb-a-connector"; - phy-supply = <&v_5v0_usb3_hst_vbus>; - }; -}; - -&cp1_usb3_0 { - phys = <&cp1_comphy2 0>; - phy-names = "cp1-usb3h0-comphy"; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts deleted file mode 100644 index 09fb5256f..000000000 --- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts +++ /dev/null @@ -1,358 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada 8040 Development board platform - */ - -#include -#include "armada-8040.dtsi" - -/ { - model = "Marvell Armada 8040 DB board"; - compatible = "marvell,armada8040-db", "marvell,armada8040", - "marvell,armada-ap806-quad", "marvell,armada-ap806"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - aliases { - ethernet0 = &cp0_eth0; - ethernet1 = &cp0_eth2; - ethernet2 = &cp1_eth0; - ethernet3 = &cp1_eth1; - i2c1 = &cp0_i2c0; - i2c2 = &cp1_i2c0; - }; - - cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { - compatible = "regulator-fixed"; - regulator-name = "cp0-usb3h0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; - }; - - cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { - compatible = "regulator-fixed"; - regulator-name = "cp0-usb3h1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; - }; - - cp0_usb3_0_phy: cp0-usb3-0-phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <&cp0_reg_usb3_0_vbus>; - }; - - cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus { - compatible = "regulator-fixed"; - regulator-name = "cp1-usb3h0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&expander1 0 GPIO_ACTIVE_HIGH>; - }; - - cp1_usb3_0_phy: cp1-usb3-0-phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <&cp1_reg_usb3_0_vbus>; - }; -}; - -&spi0 { - status = "okay"; - - spi-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x200000>; - }; - partition@400000 { - label = "Filesystem"; - reg = <0x200000 0xce0000>; - }; - }; - }; -}; - -/* Accessible over the mini-USB CON9 connector on the main board */ -&uart0 { - status = "okay"; - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - -/* CON6 on CP0 expansion */ -&cp0_pcie0 { - phys = <&cp0_comphy0 0>; - phy-names = "cp0-pcie0-x1-phy"; - status = "okay"; -}; - -/* CON5 on CP0 expansion */ -&cp0_pcie2 { - phys = <&cp0_comphy5 2>; - phy-names = "cp0-pcie2-x1-phy"; - status = "okay"; -}; - -&cp0_i2c0 { - status = "okay"; - clock-frequency = <100000>; - - /* U31 */ - expander0: pca9555@21 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x21>; - }; - - /* U25 */ - expander1: pca9555@25 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x25>; - }; - -}; - -/* CON4 on CP0 expansion */ -&cp0_sata0 { - status = "okay"; - - sata-port@0 { - phys = <&cp0_comphy1 0>; - phy-names = "cp0-sata0-0-phy"; - }; - sata-port@1 { - phys = <&cp0_comphy3 1>; - phy-names = "cp0-sata0-1-phy"; - }; -}; - -/* CON9 on CP0 expansion */ -&cp0_usb3_0 { - usb-phy = <&cp0_usb3_0_phy>; - status = "okay"; -}; - -&cp0_comphy4 { - cp0_usbh1_con: connector { - compatible = "usb-a-connector"; - phy-supply = <&cp0_reg_usb3_1_vbus>; - }; -}; - -/* CON10 on CP0 expansion */ -&cp0_usb3_1 { - phys = <&cp0_comphy4 1>; - phy-names = "cp0-usb3h1-comphy"; - status = "okay"; -}; - -&cp0_mdio { - status = "okay"; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&cp0_ethernet { - status = "okay"; -}; - -&cp0_eth0 { - status = "okay"; - phy-mode = "10gbase-kr"; - - fixed-link { - speed = <10000>; - full-duplex; - }; -}; - -&cp0_eth2 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; -}; - -/* CON6 on CP1 expansion */ -&cp1_pcie0 { - phys = <&cp1_comphy0 0>; - phy-names = "cp1-pcie0-x1-phy"; - status = "okay"; -}; - -/* CON7 on CP1 expansion */ -&cp1_pcie1 { - phys = <&cp1_comphy4 1>; - phy-names = "cp1-pcie1-x1-phy"; - status = "okay"; -}; - -/* CON5 on CP1 expansion */ -&cp1_pcie2 { - phys = <&cp1_comphy5 2>; - phy-names = "cp1-pcie2-x1-phy"; - status = "okay"; -}; - -&cp1_i2c0 { - status = "okay"; - clock-frequency = <100000>; -}; - -&cp1_spi1 { - status = "okay"; - - spi-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-max-frequency = <20000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "Boot"; - reg = <0x0 0x200000>; - }; - partition@200000 { - label = "Filesystem"; - reg = <0x200000 0xd00000>; - }; - partition@f00000 { - label = "Boot_2nd"; - reg = <0xf00000 0x100000>; - }; - }; - }; -}; - -/* - * Proper NAND usage will require DPR-76 to be in position 1-2, which disables - * MDIO signal of CP1. - */ -&cp1_nand_controller { - pinctrl-0 = <&nand_pins>, <&nand_rb>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - nand-rb = <0>; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x200000>; - }; - partition@200000 { - label = "Linux"; - reg = <0x200000 0xe00000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - }; -}; - -/* CON4 on CP1 expansion */ -&cp1_sata0 { - status = "okay"; - - sata-port@0 { - phys = <&cp1_comphy1 0>; - phy-names = "cp1-sata0-0-phy"; - }; - sata-port@1 { - phys = <&cp1_comphy3 1>; - phy-names = "cp1-sata0-1-phy"; - }; -}; - -/* CON9 on CP1 expansion */ -&cp1_usb3_0 { - usb-phy = <&cp1_usb3_0_phy>; - status = "okay"; -}; - -/* CON10 on CP1 expansion */ -&cp1_usb3_1 { - status = "okay"; -}; - -&cp1_mdio { - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&cp1_ethernet { - status = "okay"; -}; - -&cp1_eth0 { - status = "okay"; - phy-mode = "10gbase-kr"; - - fixed-link { - speed = <10000>; - full-duplex; - }; -}; - -&cp1_eth1 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; -}; - -&ap_sdhci0 { - status = "okay"; - bus-width = <4>; - non-removable; -}; - -&cp0_sdhci0 { - status = "okay"; - bus-width = <8>; - non-removable; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts deleted file mode 100644 index 2e6832d02..000000000 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for MACCHIATOBin Armada 8040 community board platform - */ - -#include "armada-8040-mcbin.dtsi" - -/ { - model = "Marvell 8040 MACCHIATOBin Single-shot"; - compatible = "marvell,armada8040-mcbin-singleshot", - "marvell,armada8040-mcbin", "marvell,armada8040", - "marvell,armada-ap806-quad", "marvell,armada-ap806"; -}; - -&cp0_eth0 { - status = "okay"; - phy-mode = "10gbase-r"; - managed = "in-band-status"; - sfp = <&sfp_eth0>; -}; - -&cp1_eth0 { - status = "okay"; - phy-mode = "10gbase-r"; - managed = "in-band-status"; - sfp = <&sfp_eth1>; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts deleted file mode 100644 index 1766cf581..000000000 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for MACCHIATOBin Armada 8040 community board platform - */ - -#include "armada-8040-mcbin.dtsi" - -/ { - model = "Marvell 8040 MACCHIATOBin Double-shot"; - compatible = "marvell,armada8040-mcbin-doubleshot", - "marvell,armada8040-mcbin", "marvell,armada8040", - "marvell,armada-ap806-quad", "marvell,armada-ap806"; -}; - -&cp0_xmdio { - status = "okay"; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <0>; - sfp = <&sfp_eth0>; - }; - - phy8: ethernet-phy@8 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <8>; - sfp = <&sfp_eth1>; - }; -}; - -&cp0_eth0 { - status = "okay"; - /* Network PHY */ - phy = <&phy0>; - phy-mode = "10gbase-r"; -}; - -&cp1_eth0 { - status = "okay"; - /* Network PHY */ - phy = <&phy8>; - phy-mode = "10gbase-r"; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi deleted file mode 100644 index cbcb210cb..000000000 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi +++ /dev/null @@ -1,372 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for MACCHIATOBin Armada 8040 community board platform - */ - -#include "armada-8040.dtsi" - -#include - -/ { - model = "Marvell 8040 MACCHIATOBin"; - compatible = "marvell,armada8040-mcbin", "marvell,armada8040", - "marvell,armada-ap806-quad", "marvell,armada-ap806"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - aliases { - ethernet0 = &cp0_eth0; - ethernet1 = &cp1_eth0; - ethernet2 = &cp1_eth1; - ethernet3 = &cp1_eth2; - }; - - /* Regulator labels correspond with schematics */ - v_3_3: regulator-3-3v { - compatible = "regulator-fixed"; - regulator-name = "v_3_3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - status = "okay"; - }; - - v_vddo_h: regulator-1-8v { - compatible = "regulator-fixed"; - regulator-name = "v_vddo_h"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - status = "okay"; - }; - - v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_xhci_vbus_pins>; - regulator-name = "v_5v0_usb3_hst_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - status = "okay"; - }; - - sfp_eth0: sfp-eth0 { - /* CON15,16 - CPM lane 4 */ - compatible = "sff,sfp"; - i2c-bus = <&sfpp0_i2c>; - los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cp1_sfpp0_pins>; - maximum-power-milliwatt = <2000>; - }; - - sfp_eth1: sfp-eth1 { - /* CON17,18 - CPS lane 4 */ - compatible = "sff,sfp"; - i2c-bus = <&sfpp1_i2c>; - los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>; - maximum-power-milliwatt = <2000>; - }; - - sfp_eth3: sfp-eth3 { - /* CON13,14 - CPS lane 5 */ - compatible = "sff,sfp"; - i2c-bus = <&sfp_1g_i2c>; - los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>; - maximum-power-milliwatt = <2000>; - }; -}; - -&uart0 { - status = "okay"; - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - -&ap_sdhci0 { - bus-width = <8>; - /* - * Not stable in HS modes - phy needs "more calibration", so add - * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes. - */ - marvell,xenon-phy-slow-mode; - no-1-8-v; - no-sd; - no-sdio; - non-removable; - status = "okay"; - vqmmc-supply = <&v_vddo_h>; -}; - -&cp0_i2c0 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_i2c0_pins>; - status = "okay"; -}; - -&cp0_i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_i2c1_pins>; - status = "okay"; - - i2c-switch@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - sfpp0_i2c: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - sfpp1_i2c: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - sfp_1g_i2c: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - }; -}; - -/* J25 UART header */ -&cp0_uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&cp0_uart1_pins>; - status = "okay"; -}; - -&cp0_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&cp0_ge_mdio_pins>; - status = "okay"; - - ge_phy: ethernet-phy@0 { - reg = <0>; - }; -}; - -&cp0_pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&cp0_pcie_pins>; - num-lanes = <4>; - num-viewport = <8>; - reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>; - ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>; - phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, - <&cp0_comphy2 0>, <&cp0_comphy3 0>; - phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy", - "cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy"; - status = "okay"; -}; - -&cp0_pinctrl { - cp0_ge_mdio_pins: ge-mdio-pins { - marvell,pins = "mpp32", "mpp34"; - marvell,function = "ge"; - }; - cp0_i2c1_pins: i2c1-pins { - marvell,pins = "mpp35", "mpp36"; - marvell,function = "i2c1"; - }; - cp0_i2c0_pins: i2c0-pins { - marvell,pins = "mpp37", "mpp38"; - marvell,function = "i2c0"; - }; - cp0_uart1_pins: uart1-pins { - marvell,pins = "mpp40", "mpp41"; - marvell,function = "uart1"; - }; - cp0_xhci_vbus_pins: xhci0-vbus-pins { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - cp0_sfp_1g_pins: sfp-1g-pins { - marvell,pins = "mpp51", "mpp53", "mpp54"; - marvell,function = "gpio"; - }; - cp0_pcie_pins: pcie-pins { - marvell,pins = "mpp52"; - marvell,function = "gpio"; - }; - cp0_sdhci_pins: sdhci-pins { - marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59", - "mpp60", "mpp61"; - marvell,function = "sdio"; - }; - cp0_sfpp1_pins: sfpp1-pins { - marvell,pins = "mpp62"; - marvell,function = "gpio"; - }; -}; - -&cp0_ethernet { - status = "okay"; -}; - -&cp0_eth0 { - /* Generic PHY, providing serdes lanes */ - phys = <&cp0_comphy4 0>; -}; - -&cp0_sata0 { - status = "okay"; - - /* CPM Lane 5 - U29 */ - sata-port@1 { - phys = <&cp0_comphy5 1>; - phy-names = "cp0-sata0-1-phy"; - }; -}; - -&cp0_sdhci0 { - /* U6 */ - broken-cd; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_sdhci_pins>; - status = "okay"; - vqmmc-supply = <&v_3_3>; -}; - -&cp0_usb3_0 { - /* J38? - USB2.0 only */ - status = "okay"; -}; - -&cp0_usb3_1 { - /* J38? - USB2.0 only */ - status = "okay"; -}; - -&cp1_ethernet { - status = "okay"; -}; - -&cp1_eth0 { - /* Generic PHY, providing serdes lanes */ - phys = <&cp1_comphy4 0>; -}; - -&cp1_eth1 { - /* CPS Lane 0 - J5 (Gigabit RJ45) */ - status = "okay"; - /* Network PHY */ - phy = <&ge_phy>; - phy-mode = "sgmii"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp1_comphy0 1>; -}; - -&cp1_eth2 { - /* CPS Lane 5 */ - status = "okay"; - /* Network PHY */ - phy-mode = "2500base-x"; - managed = "in-band-status"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp1_comphy5 2>; - sfp = <&sfp_eth3>; -}; - -&cp1_pinctrl { - cp1_sfpp1_pins: sfpp1-pins { - marvell,pins = "mpp8", "mpp10", "mpp11"; - marvell,function = "gpio"; - }; - cp1_spi1_pins: spi1-pins { - marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16"; - marvell,function = "spi1"; - }; - cp1_uart0_pins: uart0-pins { - marvell,pins = "mpp6", "mpp7"; - marvell,function = "uart0"; - }; - cp1_sfp_1g_pins: sfp-1g-pins { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - cp1_sfpp0_pins: sfpp0-pins { - marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29"; - marvell,function = "gpio"; - }; -}; - -/* J27 UART header */ -&cp1_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&cp1_uart0_pins>; - status = "okay"; -}; - -&cp1_sata0 { - status = "okay"; - - /* CPS Lane 1 - U32 */ - sata-port@0 { - phys = <&cp1_comphy1 0>; - phy-names = "cp1-sata0-0-phy"; - }; - - /* CPS Lane 3 - U31 */ - sata-port@1 { - phys = <&cp1_comphy3 1>; - phy-names = "cp1-sata0-1-phy"; - }; -}; - -&cp1_spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&cp1_spi1_pins>; - status = "okay"; - - spi-flash@0 { - compatible = "st,w25q32"; - spi-max-frequency = <50000000>; - reg = <0>; - }; -}; - -&cp1_comphy2 { - cp1_usbh0_con: connector { - compatible = "usb-a-connector"; - phy-supply = <&v_5v0_usb3_hst_vbus>; - }; -}; - -&cp1_usb3_0 { - /* CPS Lane 2 - CON7 */ - phys = <&cp1_comphy2 0>; - phy-names = "cp1-usb3h0-comphy"; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi b/arch/arm64/boot/dts/marvell/armada-8040.dtsi deleted file mode 100644 index 22c2d6ebf..000000000 --- a/arch/arm64/boot/dts/marvell/armada-8040.dtsi +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 8040 SoC, made of an AP806 Quad and - * two CP110. - */ - -#include "armada-ap806-quad.dtsi" -#include "armada-80x0.dtsi" - -/ { - model = "Marvell Armada 8040"; - compatible = "marvell,armada8040", "marvell,armada-ap806-quad", - "marvell,armada-ap806"; -}; - -&cp0_pcie0 { - iommu-map = - <0x0 &smmu 0x480 0x20>, - <0x100 &smmu 0x4a0 0x20>, - <0x200 &smmu 0x4c0 0x20>; - iommu-map-mask = <0x031f>; -}; - -/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock - * in CP master is not connected (by package) to the oscillator. So - * disable it. However, the RTC clock in CP slave is connected to the - * oscillator so this one is let enabled. - */ -&cp0_rtc { - status = "disabled"; -}; - -&cp0_sata0 { - iommus = <&smmu 0x444>; -}; - -&cp0_sdhci0 { - iommus = <&smmu 0x445>; -}; - -&cp0_usb3_0 { - iommus = <&smmu 0x440>; -}; - -&cp0_usb3_1 { - iommus = <&smmu 0x441>; -}; - -&cp1_sata0 { - iommus = <&smmu 0x454>; -}; - -&cp1_usb3_0 { - iommus = <&smmu 0x450>; -}; - -&cp1_usb3_1 { - iommus = <&smmu 0x451>; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-8080-db.dts b/arch/arm64/boot/dts/marvell/armada-8080-db.dts deleted file mode 100644 index 4ba158f41..000000000 --- a/arch/arm64/boot/dts/marvell/armada-8080-db.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada-8080 Development board platform - */ - -#include "armada-8080.dtsi" - -/ { - model = "Marvell 8080 board"; - compatible = "marvell,armada-8080-db", "marvell,armada-8080", - "marvell,armada-ap810-octa", "marvell,armada-ap810"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; -}; - -&uart0_ap0 { - clock-frequency = <384000>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-8080.dtsi b/arch/arm64/boot/dts/marvell/armada-8080.dtsi deleted file mode 100644 index 299e814d1..000000000 --- a/arch/arm64/boot/dts/marvell/armada-8080.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada-8080 SoC, made of an AP810 OCTA. - */ - -#include "armada-ap810-ap0-octa-core.dtsi" - -/ { - model = "Marvell 8080 board"; - compatible = "marvell,armada-8080", "marvell,armada-ap810-octa", - "marvell,armada-ap810"; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi deleted file mode 100644 index ee67c70bf..000000000 --- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 80x0 SoC family - */ - -/ { - aliases { - gpio1 = &cp1_gpio1; - gpio2 = &cp0_gpio2; - spi1 = &cp0_spi0; - spi2 = &cp0_spi1; - spi3 = &cp1_spi0; - spi4 = &cp1_spi1; - }; -}; - -/* - * Instantiate the master CP110 - */ -#define CP11X_NAME cp0 -#define CP11X_BASE f2000000 -#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000)) -#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 -#define CP11X_PCIE0_BASE f2600000 -#define CP11X_PCIE1_BASE f2620000 -#define CP11X_PCIE2_BASE f2640000 - -#include "armada-cp110.dtsi" - -#undef CP11X_NAME -#undef CP11X_BASE -#undef CP11X_PCIEx_MEM_BASE -#undef CP11X_PCIEx_MEM_SIZE -#undef CP11X_PCIE0_BASE -#undef CP11X_PCIE1_BASE -#undef CP11X_PCIE2_BASE - -/* - * Instantiate the slave CP110 - */ -#define CP11X_NAME cp1 -#define CP11X_BASE f4000000 -#define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000)) -#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 -#define CP11X_PCIE0_BASE f4600000 -#define CP11X_PCIE1_BASE f4620000 -#define CP11X_PCIE2_BASE f4640000 - -#include "armada-cp110.dtsi" - -#undef CP11X_NAME -#undef CP11X_BASE -#undef CP11X_PCIEx_MEM_BASE -#undef CP11X_PCIEx_MEM_SIZE -#undef CP11X_PCIE0_BASE -#undef CP11X_PCIE1_BASE -#undef CP11X_PCIE2_BASE - -/* The 80x0 has two CP blocks, but uses only one block from each. */ -&cp1_gpio1 { - status = "okay"; -}; - -&cp0_gpio2 { - status = "okay"; -}; - -&cp0_syscon0 { - cp0_pinctrl: pinctrl { - compatible = "marvell,armada-8k-cpm-pinctrl"; - }; -}; - -&cp1_syscon0 { - cp1_pinctrl: pinctrl { - compatible = "marvell,armada-8k-cps-pinctrl"; - - nand_pins: nand-pins { - marvell,pins = - "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp6", "mpp7", - "mpp8", "mpp9", "mpp10", "mpp11", - "mpp15", "mpp16", "mpp17", "mpp18", - "mpp19", "mpp20", "mpp21", "mpp22", - "mpp23", "mpp24", "mpp25", "mpp26", - "mpp27"; - marvell,function = "dev"; - }; - - nand_rb: nand-rb { - marvell,pins = "mpp13", "mpp12"; - marvell,function = "nf"; - }; - }; -}; - -&cp1_crypto { - /* - * The cryptographic engine found on the cp110 - * master is enabled by default at the SoC - * level. Because it is not possible as of now - * to enable two cryptographic engines in - * parallel, disable this one by default. - */ - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi deleted file mode 100644 index fcab5173f..000000000 --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada AP806. - */ - -#include "armada-ap806.dtsi" - -/ { - model = "Marvell Armada AP806 Dual"; - compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x000>; - enable-method = "psci"; - #cooling-cells = <2>; - clocks = <&cpu_clk 0>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x001>; - enable-method = "psci"; - #cooling-cells = <2>; - clocks = <&cpu_clk 0>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2>; - }; - - l2: l2-cache { - compatible = "cache"; - cache-size = <0x80000>; - cache-line-size = <64>; - cache-sets = <512>; - }; - }; - - thermal-zones { - /delete-node/ ap-thermal-cpu2; - /delete-node/ ap-thermal-cpu3; - }; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi deleted file mode 100644 index 3db427122..000000000 --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada AP806. - */ - -#include "armada-ap806.dtsi" - -/ { - model = "Marvell Armada AP806 Quad"; - compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x000>; - enable-method = "psci"; - #cooling-cells = <2>; - clocks = <&cpu_clk 0>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_0>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x001>; - enable-method = "psci"; - #cooling-cells = <2>; - clocks = <&cpu_clk 0>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_0>; - }; - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x100>; - enable-method = "psci"; - #cooling-cells = <2>; - clocks = <&cpu_clk 1>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_1>; - }; - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x101>; - enable-method = "psci"; - #cooling-cells = <2>; - clocks = <&cpu_clk 1>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_1>; - }; - - l2_0: l2-cache0 { - compatible = "cache"; - cache-size = <0x80000>; - cache-line-size = <64>; - cache-sets = <512>; - }; - - l2_1: l2-cache1 { - compatible = "cache"; - cache-size = <0x80000>; - cache-line-size = <64>; - cache-sets = <512>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi deleted file mode 100644 index 866628679..000000000 --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada AP806. - */ - -#define AP_NAME ap806 -#include "armada-ap80x.dtsi" - -/ { - model = "Marvell Armada AP806"; - compatible = "marvell,armada-ap806"; -}; - -&ap_syscon0 { - ap_clk: clock { - compatible = "marvell,ap806-clock"; - #clock-cells = <1>; - }; -}; - -&ap_syscon1 { - cpu_clk: clock-cpu@278 { - compatible = "marvell,ap806-cpu-clock"; - clocks = <&ap_clk 0>, <&ap_clk 1>; - #clock-cells = <1>; - reg = <0x278 0xa30>; - }; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi deleted file mode 100644 index 68782f161..000000000 --- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada AP807 Quad - * - * Copyright (C) 2019 Marvell Technology Group Ltd. - */ - -#include "armada-ap807.dtsi" - -/ { - model = "Marvell Armada AP807 Quad"; - compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x000>; - enable-method = "psci"; - #cooling-cells = <2>; - clocks = <&cpu_clk 0>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_0>; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x001>; - enable-method = "psci"; - #cooling-cells = <2>; - clocks = <&cpu_clk 0>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_0>; - }; - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x100>; - enable-method = "psci"; - #cooling-cells = <2>; - clocks = <&cpu_clk 1>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_1>; - }; - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x101>; - enable-method = "psci"; - #cooling-cells = <2>; - clocks = <&cpu_clk 1>; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_1>; - }; - - l2_0: l2-cache0 { - compatible = "cache"; - cache-size = <0x80000>; - cache-line-size = <64>; - cache-sets = <512>; - }; - - l2_1: l2-cache1 { - compatible = "cache"; - cache-size = <0x80000>; - cache-line-size = <64>; - cache-sets = <512>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-ap807.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807.dtsi deleted file mode 100644 index 623010f3c..000000000 --- a/arch/arm64/boot/dts/marvell/armada-ap807.dtsi +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Marvell Armada AP807 - * - * Copyright (C) 2019 Marvell Technology Group Ltd. - */ - -#define AP_NAME ap807 -#include "armada-ap80x.dtsi" - -/ { - model = "Marvell Armada AP807"; - compatible = "marvell,armada-ap807"; -}; - -&ap_syscon0 { - ap_clk: clock { - compatible = "marvell,ap807-clock"; - #clock-cells = <1>; - }; -}; - -&ap_syscon1 { - cpu_clk: clock-cpu { - compatible = "marvell,ap807-cpu-clock"; - clocks = <&ap_clk 0>, <&ap_clk 1>; - #clock-cells = <1>; - }; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi deleted file mode 100644 index 12e477f1a..000000000 --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi +++ /dev/null @@ -1,461 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada AP80x. - */ - -#include -#include - -/dts-v1/; - -/ { - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - gpio0 = &ap_gpio; - spi0 = &spi0; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* - * This area matches the mapping done with a - * mainline U-Boot, and should be updated by the - * bootloader. - */ - - psci-area@4000000 { - reg = <0x0 0x4000000 0x0 0x200000>; - no-map; - }; - }; - - AP_NAME { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - config-space@f0000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x0 0x0 0xf0000000 0x1000000>; - - smmu: iommu@5000000 { - compatible = "marvell,ap806-smmu-500", "arm,mmu-500"; - reg = <0x100000 0x100000>; - dma-coherent; - #iommu-cells = <1>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - ; - status = "disabled"; - }; - - gic: interrupt-controller@210000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-controller; - interrupts = ; - reg = <0x210000 0x10000>, - <0x220000 0x20000>, - <0x240000 0x20000>, - <0x260000 0x20000>; - - gic_v2m0: v2m@280000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x280000 0x1000>; - arm,msi-base-spi = <160>; - arm,msi-num-spis = <32>; - }; - gic_v2m1: v2m@290000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x290000 0x1000>; - arm,msi-base-spi = <192>; - arm,msi-num-spis = <32>; - }; - gic_v2m2: v2m@2a0000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x2a0000 0x1000>; - arm,msi-base-spi = <224>; - arm,msi-num-spis = <32>; - }; - gic_v2m3: v2m@2b0000 { - compatible = "arm,gic-v2m-frame"; - msi-controller; - reg = <0x2b0000 0x1000>; - arm,msi-base-spi = <256>; - arm,msi-num-spis = <32>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a72-pmu"; - interrupt-parent = <&pic>; - interrupts = <17>; - }; - - odmi: odmi@300000 { - compatible = "marvell,odmi-controller"; - interrupt-controller; - msi-controller; - marvell,odmi-frames = <4>; - reg = <0x300000 0x4000>, - <0x304000 0x4000>, - <0x308000 0x4000>, - <0x30C000 0x4000>; - marvell,spi-base = <128>, <136>, <144>, <152>; - }; - - gicp: gicp@3f0040 { - compatible = "marvell,ap806-gicp"; - reg = <0x3f0040 0x10>; - marvell,spi-ranges = <64 64>, <288 64>; - msi-controller; - }; - - pic: interrupt-controller@3f0100 { - compatible = "marvell,armada-8k-pic"; - reg = <0x3f0100 0x10>; - #interrupt-cells = <1>; - interrupt-controller; - interrupts = ; - }; - - sei: interrupt-controller@3f0200 { - compatible = "marvell,ap806-sei"; - reg = <0x3f0200 0x40>; - interrupts = ; - #interrupt-cells = <1>; - interrupt-controller; - msi-controller; - }; - - xor@400000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x400000 0x1000>, - <0x410000 0x1000>; - msi-parent = <&gic_v2m0>; - clocks = <&ap_clk 3>; - dma-coherent; - }; - - xor@420000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x420000 0x1000>, - <0x430000 0x1000>; - msi-parent = <&gic_v2m0>; - clocks = <&ap_clk 3>; - dma-coherent; - }; - - xor@440000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x440000 0x1000>, - <0x450000 0x1000>; - msi-parent = <&gic_v2m0>; - clocks = <&ap_clk 3>; - dma-coherent; - }; - - xor@460000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x460000 0x1000>, - <0x470000 0x1000>; - msi-parent = <&gic_v2m0>; - clocks = <&ap_clk 3>; - dma-coherent; - }; - - spi0: spi@510600 { - compatible = "marvell,armada-380-spi"; - reg = <0x510600 0x50>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&ap_clk 3>; - status = "disabled"; - }; - - i2c0: i2c@511000 { - compatible = "marvell,mv78230-i2c"; - reg = <0x511000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&ap_clk 3>; - status = "disabled"; - }; - - uart0: serial@512000 { - compatible = "snps,dw-apb-uart"; - reg = <0x512000 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&ap_clk 3>; - status = "disabled"; - }; - - uart1: serial@512100 { - compatible = "snps,dw-apb-uart"; - reg = <0x512100 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - clocks = <&ap_clk 3>; - status = "disabled"; - - }; - - watchdog: watchdog@610000 { - compatible = "arm,sbsa-gwdt"; - reg = <0x610000 0x1000>, <0x600000 0x1000>; - interrupts = ; - }; - - ap_sdhci0: sdhci@6e0000 { - compatible = "marvell,armada-ap806-sdhci"; - reg = <0x6e0000 0x300>; - interrupts = ; - clock-names = "core"; - clocks = <&ap_clk 4>; - dma-coherent; - marvell,xenon-phy-slow-mode; - status = "disabled"; - }; - - ap_syscon0: system-controller@6f4000 { - compatible = "syscon", "simple-mfd"; - reg = <0x6f4000 0x2000>; - - ap_pinctrl: pinctrl { - compatible = "marvell,ap806-pinctrl"; - - uart0_pins: uart0-pins { - marvell,pins = "mpp11", "mpp19"; - marvell,function = "uart0"; - }; - }; - - ap_gpio: gpio@1040 { - compatible = "marvell,armada-8k-gpio"; - offset = <0x1040>; - ngpios = <20>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&ap_pinctrl 0 0 20>; - }; - }; - - ap_syscon1: system-controller@6f8000 { - compatible = "syscon", "simple-mfd"; - reg = <0x6f8000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - ap_thermal: thermal-sensor@80 { - compatible = "marvell,armada-ap806-thermal"; - reg = <0x80 0x10>; - interrupt-parent = <&sei>; - interrupts = <18>; - #thermal-sensor-cells = <1>; - }; - }; - }; - }; - - /* - * The thermal IP features one internal sensor plus, if applicable, one - * remote channel wired to one sensor per CPU. - * - * Only one thermal zone per AP/CP may trigger interrupts at a time, the - * first one that will have a critical trip point will be chosen. - */ - thermal-zones { - ap_thermal_ic: ap-thermal-ic { - polling-delay-passive = <0>; /* Interrupt driven */ - polling-delay = <0>; /* Interrupt driven */ - - thermal-sensors = <&ap_thermal 0>; - - trips { - ap_crit: ap-crit { - temperature = <100000>; /* mC degrees */ - hysteresis = <2000>; /* mC degrees */ - type = "critical"; - }; - }; - - cooling-maps { }; - }; - - ap_thermal_cpu0: ap-thermal-cpu0 { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = <&ap_thermal 1>; - - trips { - cpu0_hot: cpu0-hot { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu0_emerg: cpu0-emerg { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - map0_hot: map0-hot { - trip = <&cpu0_hot>; - cooling-device = <&cpu0 1 2>, - <&cpu1 1 2>; - }; - map0_emerg: map0-ermerg { - trip = <&cpu0_emerg>; - cooling-device = <&cpu0 3 3>, - <&cpu1 3 3>; - }; - }; - }; - - ap_thermal_cpu1: ap-thermal-cpu1 { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = <&ap_thermal 2>; - - trips { - cpu1_hot: cpu1-hot { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu1_emerg: cpu1-emerg { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - map1_hot: map1-hot { - trip = <&cpu1_hot>; - cooling-device = <&cpu0 1 2>, - <&cpu1 1 2>; - }; - map1_emerg: map1-emerg { - trip = <&cpu1_emerg>; - cooling-device = <&cpu0 3 3>, - <&cpu1 3 3>; - }; - }; - }; - - ap_thermal_cpu2: ap-thermal-cpu2 { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = <&ap_thermal 3>; - - trips { - cpu2_hot: cpu2-hot { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu2_emerg: cpu2-emerg { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - map2_hot: map2-hot { - trip = <&cpu2_hot>; - cooling-device = <&cpu2 1 2>, - <&cpu3 1 2>; - }; - map2_emerg: map2-emerg { - trip = <&cpu2_emerg>; - cooling-device = <&cpu2 3 3>, - <&cpu3 3 3>; - }; - }; - }; - - ap_thermal_cpu3: ap-thermal-cpu3 { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = <&ap_thermal 4>; - - trips { - cpu3_hot: cpu3-hot { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu3_emerg: cpu3-emerg { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - map3_hot: map3-bhot { - trip = <&cpu3_hot>; - cooling-device = <&cpu2 1 2>, - <&cpu3 1 2>; - }; - map3_emerg: map3-emerg { - trip = <&cpu3_emerg>; - cooling-device = <&cpu2 3 3>, - <&cpu3 3 3>; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi b/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi deleted file mode 100644 index d1a7143ef..000000000 --- a/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada AP810 OCTA cores. - */ - -#include "armada-ap810-ap0.dtsi" - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,armada-ap810-octa"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x000>; - enable-method = "psci"; - }; - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x001>; - enable-method = "psci"; - }; - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x100>; - enable-method = "psci"; - }; - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x101>; - enable-method = "psci"; - }; - cpu4: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x200>; - enable-method = "psci"; - }; - cpu5: cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x201>; - enable-method = "psci"; - }; - cpu6: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x300>; - enable-method = "psci"; - }; - cpu7: cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x301>; - enable-method = "psci"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi b/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi deleted file mode 100644 index 8107d120a..000000000 --- a/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2017 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada AP810. - */ - -#include - -/dts-v1/; - -/ { - model = "Marvell Armada AP810"; - compatible = "marvell,armada-ap810"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &uart0_ap0; - serial1 = &uart1_ap0; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - ap810-ap0 { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - config-space@e8000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x0 0x0 0xe8000000 0x4000000>; - interrupt-parent = <&gic>; - - gic: interrupt-controller@3000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - interrupt-controller; - interrupts = ; - ranges; - - reg = <0x3000000 0x10000>, /* GICD */ - <0x3060000 0x100000>, /* GICR */ - <0x00c0000 0x2000>, /* GICC */ - <0x00d0000 0x1000>, /* GICH */ - <0x00e0000 0x2000>; /* GICV */ - - gic_its_ap0: interrupt-controller@3040000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x3040000 0x20000>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - xor@400000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x400000 0x1000>, - <0x410000 0x1000>; - msi-parent = <&gic_its_ap0 0xa0>; - dma-coherent; - }; - - xor@420000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x420000 0x1000>, - <0x430000 0x1000>; - msi-parent = <&gic_its_ap0 0xa1>; - dma-coherent; - }; - - xor@440000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x440000 0x1000>, - <0x450000 0x1000>; - msi-parent = <&gic_its_ap0 0xa2>; - dma-coherent; - }; - - xor@460000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x460000 0x1000>, - <0x470000 0x1000>; - msi-parent = <&gic_its_ap0 0xa3>; - dma-coherent; - }; - - uart0_ap0: serial@512000 { - compatible = "snps,dw-apb-uart"; - reg = <0x512000 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - status = "disabled"; - }; - - uart1_ap0: serial@512100 { - compatible = "snps,dw-apb-uart"; - reg = <0x512100 0x100>; - reg-shift = <2>; - interrupts = ; - reg-io-width = <1>; - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-common.dtsi b/arch/arm64/boot/dts/marvell/armada-common.dtsi deleted file mode 100644 index c04c6c475..000000000 --- a/arch/arm64/boot/dts/marvell/armada-common.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - */ - -/* Common definitions used by Armada 7K/8K DTs */ -#define PASTER(x, y) x ## y -#define EVALUATOR(x, y) PASTER(x, y) -#define CP11X_LABEL(name) EVALUATOR(CP11X_NAME, EVALUATOR(_, name)) -#define CP11X_NODE_NAME(name) EVALUATOR(CP11X_NAME, EVALUATOR(-, name)) -#define ADDRESSIFY(addr) EVALUATOR(0x, addr) diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi deleted file mode 100644 index 4fd33b0fa..000000000 --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada CP110. - */ - -#define CP11X_TYPE cp110 - -#include "armada-cp11x.dtsi" - -#undef CP11X_TYPE diff --git a/arch/arm64/boot/dts/marvell/armada-cp115.dtsi b/arch/arm64/boot/dts/marvell/armada-cp115.dtsi deleted file mode 100644 index 1d0a9653e..000000000 --- a/arch/arm64/boot/dts/marvell/armada-cp115.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada CP115. - */ - -#define CP11X_TYPE cp115 - -#include "armada-cp11x.dtsi" - -#undef CP11X_TYPE diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi deleted file mode 100644 index 9dcf16bea..000000000 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ /dev/null @@ -1,568 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for Marvell Armada CP11x. - */ - -#include -#include - -#include "armada-common.dtsi" - -#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface)) - -/ { - /* - * The contents of the node are defined below, in order to - * save one indentation level - */ - CP11X_NAME: CP11X_NAME { }; - - /* - * CPs only have one sensor in the thermal IC. - * - * The cooling maps are empty as there are no cooling devices. - */ - thermal-zones { - CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) { - polling-delay-passive = <0>; /* Interrupt driven */ - polling-delay = <0>; /* Interrupt driven */ - - thermal-sensors = <&CP11X_LABEL(thermal) 0>; - - trips { - CP11X_LABEL(crit): crit { - temperature = <100000>; /* mC degrees */ - hysteresis = <2000>; /* mC degrees */ - type = "critical"; - }; - }; - - cooling-maps { }; - }; - }; -}; - -&CP11X_NAME { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - interrupt-parent = <&CP11X_LABEL(icu_nsr)>; - ranges; - - config-space@CP11X_BASE { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>; - - CP11X_LABEL(ethernet): ethernet@0 { - compatible = "marvell,armada-7k-pp22"; - reg = <0x0 0x100000>, <0x129000 0xb000>; - clocks = <&CP11X_LABEL(clk) 1 3>, <&CP11X_LABEL(clk) 1 9>, - <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>, - <&CP11X_LABEL(clk) 1 18>; - clock-names = "pp_clk", "gop_clk", - "mg_clk", "mg_core_clk", "axi_clk"; - marvell,system-controller = <&CP11X_LABEL(syscon0)>; - status = "disabled"; - dma-coherent; - - CP11X_LABEL(eth0): eth0 { - interrupts = <39 IRQ_TYPE_LEVEL_HIGH>, - <43 IRQ_TYPE_LEVEL_HIGH>, - <47 IRQ_TYPE_LEVEL_HIGH>, - <51 IRQ_TYPE_LEVEL_HIGH>, - <55 IRQ_TYPE_LEVEL_HIGH>, - <59 IRQ_TYPE_LEVEL_HIGH>, - <63 IRQ_TYPE_LEVEL_HIGH>, - <67 IRQ_TYPE_LEVEL_HIGH>, - <71 IRQ_TYPE_LEVEL_HIGH>, - <129 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hif0", "hif1", "hif2", - "hif3", "hif4", "hif5", "hif6", "hif7", - "hif8", "link"; - port-id = <0>; - gop-port-id = <0>; - status = "disabled"; - }; - - CP11X_LABEL(eth1): eth1 { - interrupts = <40 IRQ_TYPE_LEVEL_HIGH>, - <44 IRQ_TYPE_LEVEL_HIGH>, - <48 IRQ_TYPE_LEVEL_HIGH>, - <52 IRQ_TYPE_LEVEL_HIGH>, - <56 IRQ_TYPE_LEVEL_HIGH>, - <60 IRQ_TYPE_LEVEL_HIGH>, - <64 IRQ_TYPE_LEVEL_HIGH>, - <68 IRQ_TYPE_LEVEL_HIGH>, - <72 IRQ_TYPE_LEVEL_HIGH>, - <128 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hif0", "hif1", "hif2", - "hif3", "hif4", "hif5", "hif6", "hif7", - "hif8", "link"; - port-id = <1>; - gop-port-id = <2>; - status = "disabled"; - }; - - CP11X_LABEL(eth2): eth2 { - interrupts = <41 IRQ_TYPE_LEVEL_HIGH>, - <45 IRQ_TYPE_LEVEL_HIGH>, - <49 IRQ_TYPE_LEVEL_HIGH>, - <53 IRQ_TYPE_LEVEL_HIGH>, - <57 IRQ_TYPE_LEVEL_HIGH>, - <61 IRQ_TYPE_LEVEL_HIGH>, - <65 IRQ_TYPE_LEVEL_HIGH>, - <69 IRQ_TYPE_LEVEL_HIGH>, - <73 IRQ_TYPE_LEVEL_HIGH>, - <127 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hif0", "hif1", "hif2", - "hif3", "hif4", "hif5", "hif6", "hif7", - "hif8", "link"; - port-id = <2>; - gop-port-id = <3>; - status = "disabled"; - }; - }; - - CP11X_LABEL(comphy): phy@120000 { - compatible = "marvell,comphy-cp110"; - reg = <0x120000 0x6000>; - marvell,system-controller = <&CP11X_LABEL(syscon0)>; - clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>, - <&CP11X_LABEL(clk) 1 18>; - clock-names = "mg_clk", "mg_core_clk", "axi_clk"; - #address-cells = <1>; - #size-cells = <0>; - - CP11X_LABEL(comphy0): phy@0 { - reg = <0>; - #phy-cells = <1>; - }; - - CP11X_LABEL(comphy1): phy@1 { - reg = <1>; - #phy-cells = <1>; - }; - - CP11X_LABEL(comphy2): phy@2 { - reg = <2>; - #phy-cells = <1>; - }; - - CP11X_LABEL(comphy3): phy@3 { - reg = <3>; - #phy-cells = <1>; - }; - - CP11X_LABEL(comphy4): phy@4 { - reg = <4>; - #phy-cells = <1>; - }; - - CP11X_LABEL(comphy5): phy@5 { - reg = <5>; - #phy-cells = <1>; - }; - }; - - CP11X_LABEL(mdio): mdio@12a200 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,orion-mdio"; - reg = <0x12a200 0x10>; - clocks = <&CP11X_LABEL(clk) 1 9>, <&CP11X_LABEL(clk) 1 5>, - <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>; - status = "disabled"; - }; - - CP11X_LABEL(xmdio): mdio@12a600 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,xmdio"; - reg = <0x12a600 0x10>; - clocks = <&CP11X_LABEL(clk) 1 5>, - <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>; - status = "disabled"; - }; - - CP11X_LABEL(icu): interrupt-controller@1e0000 { - compatible = "marvell,cp110-icu"; - reg = <0x1e0000 0x440>; - #address-cells = <1>; - #size-cells = <1>; - - CP11X_LABEL(icu_nsr): interrupt-controller@10 { - compatible = "marvell,cp110-icu-nsr"; - reg = <0x10 0x20>; - #interrupt-cells = <2>; - interrupt-controller; - msi-parent = <&gicp>; - }; - - CP11X_LABEL(icu_sei): interrupt-controller@50 { - compatible = "marvell,cp110-icu-sei"; - reg = <0x50 0x10>; - #interrupt-cells = <2>; - interrupt-controller; - msi-parent = <&sei>; - }; - }; - - CP11X_LABEL(rtc): rtc@284000 { - compatible = "marvell,armada-8k-rtc"; - reg = <0x284000 0x20>, <0x284080 0x24>; - reg-names = "rtc", "rtc-soc"; - interrupts = <77 IRQ_TYPE_LEVEL_HIGH>; - }; - - CP11X_LABEL(syscon0): system-controller@440000 { - compatible = "syscon", "simple-mfd"; - reg = <0x440000 0x2000>; - - CP11X_LABEL(clk): clock { - compatible = "marvell,cp110-clock"; - #clock-cells = <2>; - }; - - CP11X_LABEL(gpio1): gpio@100 { - compatible = "marvell,armada-8k-gpio"; - offset = <0x100>; - ngpios = <32>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>; - interrupt-controller; - interrupts = <86 IRQ_TYPE_LEVEL_HIGH>, - <85 IRQ_TYPE_LEVEL_HIGH>, - <84 IRQ_TYPE_LEVEL_HIGH>, - <83 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <2>; - status = "disabled"; - }; - - CP11X_LABEL(gpio2): gpio@140 { - compatible = "marvell,armada-8k-gpio"; - offset = <0x140>; - ngpios = <31>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>; - interrupt-controller; - interrupts = <82 IRQ_TYPE_LEVEL_HIGH>, - <81 IRQ_TYPE_LEVEL_HIGH>, - <80 IRQ_TYPE_LEVEL_HIGH>, - <79 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <2>; - status = "disabled"; - }; - }; - - CP11X_LABEL(syscon1): system-controller@400000 { - compatible = "syscon", "simple-mfd"; - reg = <0x400000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - CP11X_LABEL(thermal): thermal-sensor@70 { - compatible = "marvell,armada-cp110-thermal"; - reg = <0x70 0x10>; - interrupts-extended = - <&CP11X_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>; - #thermal-sensor-cells = <1>; - }; - }; - - CP11X_LABEL(usb3_0): usb3@500000 { - compatible = "marvell,armada-8k-xhci", - "generic-xhci"; - reg = <0x500000 0x4000>; - dma-coherent; - interrupts = <106 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 22>, - <&CP11X_LABEL(clk) 1 16>; - status = "disabled"; - }; - - CP11X_LABEL(usb3_1): usb3@510000 { - compatible = "marvell,armada-8k-xhci", - "generic-xhci"; - reg = <0x510000 0x4000>; - dma-coherent; - interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 23>, - <&CP11X_LABEL(clk) 1 16>; - status = "disabled"; - }; - - CP11X_LABEL(sata0): sata@540000 { - compatible = "marvell,armada-8k-ahci", - "generic-ahci"; - reg = <0x540000 0x30000>; - dma-coherent; - interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&CP11X_LABEL(clk) 1 15>, - <&CP11X_LABEL(clk) 1 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata-port@0 { - reg = <0>; - }; - - sata-port@1 { - reg = <1>; - }; - }; - - CP11X_LABEL(xor0): xor@6a0000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>; - dma-coherent; - msi-parent = <&gic_v2m0>; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 8>, - <&CP11X_LABEL(clk) 1 14>; - }; - - CP11X_LABEL(xor1): xor@6c0000 { - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; - reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>; - dma-coherent; - msi-parent = <&gic_v2m0>; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 7>, - <&CP11X_LABEL(clk) 1 14>; - }; - - CP11X_LABEL(spi0): spi@700600 { - compatible = "marvell,armada-380-spi"; - reg = <0x700600 0x50>; - #address-cells = <0x1>; - #size-cells = <0x0>; - clock-names = "core", "axi"; - clocks = <&CP11X_LABEL(clk) 1 21>, - <&CP11X_LABEL(clk) 1 17>; - status = "disabled"; - }; - - CP11X_LABEL(spi1): spi@700680 { - compatible = "marvell,armada-380-spi"; - reg = <0x700680 0x50>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "core", "axi"; - clocks = <&CP11X_LABEL(clk) 1 21>, - <&CP11X_LABEL(clk) 1 17>; - status = "disabled"; - }; - - CP11X_LABEL(i2c0): i2c@701000 { - compatible = "marvell,mv78230-i2c"; - reg = <0x701000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <120 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 21>, - <&CP11X_LABEL(clk) 1 17>; - status = "disabled"; - }; - - CP11X_LABEL(i2c1): i2c@701100 { - compatible = "marvell,mv78230-i2c"; - reg = <0x701100 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <121 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 21>, - <&CP11X_LABEL(clk) 1 17>; - status = "disabled"; - }; - - CP11X_LABEL(uart0): serial@702000 { - compatible = "snps,dw-apb-uart"; - reg = <0x702000 0x100>; - reg-shift = <2>; - interrupts = <122 IRQ_TYPE_LEVEL_HIGH>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&CP11X_LABEL(clk) 1 21>, - <&CP11X_LABEL(clk) 1 17>; - status = "disabled"; - }; - - CP11X_LABEL(uart1): serial@702100 { - compatible = "snps,dw-apb-uart"; - reg = <0x702100 0x100>; - reg-shift = <2>; - interrupts = <123 IRQ_TYPE_LEVEL_HIGH>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&CP11X_LABEL(clk) 1 21>, - <&CP11X_LABEL(clk) 1 17>; - status = "disabled"; - }; - - CP11X_LABEL(uart2): serial@702200 { - compatible = "snps,dw-apb-uart"; - reg = <0x702200 0x100>; - reg-shift = <2>; - interrupts = <124 IRQ_TYPE_LEVEL_HIGH>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&CP11X_LABEL(clk) 1 21>, - <&CP11X_LABEL(clk) 1 17>; - status = "disabled"; - }; - - CP11X_LABEL(uart3): serial@702300 { - compatible = "snps,dw-apb-uart"; - reg = <0x702300 0x100>; - reg-shift = <2>; - interrupts = <125 IRQ_TYPE_LEVEL_HIGH>; - reg-io-width = <1>; - clock-names = "baudclk", "apb_pclk"; - clocks = <&CP11X_LABEL(clk) 1 21>, - <&CP11X_LABEL(clk) 1 17>; - status = "disabled"; - }; - - CP11X_LABEL(nand_controller): nand@720000 { - /* - * Due to the limitation of the pins available - * this controller is only usable on the CPM - * for A7K and on the CPS for A8K. - */ - compatible = "marvell,armada-8k-nand-controller", - "marvell,armada370-nand-controller"; - reg = <0x720000 0x54>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <115 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 2>, - <&CP11X_LABEL(clk) 1 17>; - marvell,system-controller = <&CP11X_LABEL(syscon0)>; - status = "disabled"; - }; - - CP11X_LABEL(trng): trng@760000 { - compatible = "marvell,armada-8k-rng", - "inside-secure,safexcel-eip76"; - reg = <0x760000 0x7d>; - interrupts = <95 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 25>, - <&CP11X_LABEL(clk) 1 17>; - status = "okay"; - }; - - CP11X_LABEL(sdhci0): sdhci@780000 { - compatible = "marvell,armada-cp110-sdhci"; - reg = <0x780000 0x300>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "core", "axi"; - clocks = <&CP11X_LABEL(clk) 1 4>, <&CP11X_LABEL(clk) 1 18>; - dma-coherent; - status = "disabled"; - }; - - CP11X_LABEL(crypto): crypto@800000 { - compatible = "inside-secure,safexcel-eip197b"; - reg = <0x800000 0x200000>; - interrupts = <87 IRQ_TYPE_LEVEL_HIGH>, - <88 IRQ_TYPE_LEVEL_HIGH>, - <89 IRQ_TYPE_LEVEL_HIGH>, - <90 IRQ_TYPE_LEVEL_HIGH>, - <91 IRQ_TYPE_LEVEL_HIGH>, - <92 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mem", "ring0", "ring1", - "ring2", "ring3", "eip"; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 26>, - <&CP11X_LABEL(clk) 1 17>; - dma-coherent; - }; - }; - - CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE { - compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; - reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>, - <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>; - reg-names = "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - device_type = "pci"; - dma-coherent; - msi-parent = <&gic_v2m0>; - - bus-range = <0 0xff>; - /* non-prefetchable memory */ - ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; - num-lanes = <1>; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>; - status = "disabled"; - }; - - CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE { - compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; - reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>, - <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>; - reg-names = "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - device_type = "pci"; - dma-coherent; - msi-parent = <&gic_v2m0>; - - bus-range = <0 0xff>; - /* non-prefetchable memory */ - ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; - - num-lanes = <1>; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>; - status = "disabled"; - }; - - CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE { - compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; - reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>, - <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>; - reg-names = "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - device_type = "pci"; - dma-coherent; - msi-parent = <&gic_v2m0>; - - bus-range = <0 0xff>; - /* non-prefetchable memory */ - ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; - - num-lanes = <1>; - clock-names = "core", "reg"; - clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>; - status = "disabled"; - }; -}; diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts b/arch/arm64/boot/dts/marvell/cn9130-db.dts deleted file mode 100644 index d24294888..000000000 --- a/arch/arm64/boot/dts/marvell/cn9130-db.dts +++ /dev/null @@ -1,403 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Marvell International Ltd. - * - * Device tree for the CN9130-DB board. - */ - -#include "cn9130.dtsi" - -#include - -/ { - model = "Marvell Armada CN9130-DB"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - gpio1 = &cp0_gpio1; - gpio2 = &cp0_gpio2; - i2c0 = &cp0_i2c0; - ethernet0 = &cp0_eth0; - ethernet1 = &cp0_eth1; - ethernet2 = &cp0_eth2; - spi1 = &cp0_spi0; - spi2 = &cp0_spi1; - }; - - memory@00000000 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - ap0_reg_sd_vccq: ap0_sd_vccq@0 { - compatible = "regulator-gpio"; - regulator-name = "ap0_sd_vccq"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios = <&expander0 8 GPIO_ACTIVE_HIGH>; - states = <1800000 0x1 3300000 0x0>; - }; - - cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 { - compatible = "regulator-fixed"; - regulator-name = "cp0-xhci0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; - }; - - cp0_usb3_0_phy0: cp0_usb3_phy@0 { - compatible = "usb-nop-xceiv"; - vcc-supply = <&cp0_reg_usb3_vbus0>; - }; - - cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 { - compatible = "regulator-fixed"; - regulator-name = "cp0-xhci1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; - }; - - cp0_usb3_0_phy1: cp0_usb3_phy@1 { - compatible = "usb-nop-xceiv"; - vcc-supply = <&cp0_reg_usb3_vbus1>; - }; - - cp0_reg_sd_vccq: cp0_sd_vccq@0 { - compatible = "regulator-gpio"; - regulator-name = "cp0_sd_vccq"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios = <&expander0 15 GPIO_ACTIVE_HIGH>; - states = <1800000 0x1 - 3300000 0x0>; - }; - - cp0_reg_sd_vcc: cp0_sd_vcc@0 { - compatible = "regulator-fixed"; - regulator-name = "cp0_sd_vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - cp0_sfp_eth0: sfp-eth@0 { - compatible = "sff,sfp"; - i2c-bus = <&cp0_sfpp0_i2c>; - los-gpio = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>; - /* - * SFP cages are unconnected on early PCBs because of an the I2C - * lanes not being connected. Prevent the port for being - * unusable by disabling the SFP node. - */ - status = "disabled"; - }; -}; - -&uart0 { - status = "okay"; -}; - -/* on-board eMMC - U9 */ -&ap_sdhci0 { - pinctrl-names = "default"; - bus-width = <8>; - vqmmc-supply = <&ap0_reg_sd_vccq>; - status = "okay"; -}; - -&cp0_crypto { - status = "disabled"; -}; - -&cp0_ethernet { - status = "okay"; -}; - -/* SLM-1521-V2, CON9 */ -&cp0_eth0 { - status = "disabled"; - phy-mode = "10gbase-kr"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp0_comphy4 0>; - managed = "in-band-status"; - sfp = <&cp0_sfp_eth0>; -}; - -/* CON56 */ -&cp0_eth1 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; -}; - -/* CON57 */ -&cp0_eth2 { - status = "okay"; - phy = <&phy1>; - phy-mode = "rgmii-id"; -}; - -&cp0_gpio1 { - status = "okay"; -}; - -&cp0_gpio2 { - status = "okay"; -}; - -&cp0_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_i2c0_pins>; - clock-frequency = <100000>; - - /* U36 */ - expander0: pca953x@21 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x21>; - status = "okay"; - }; - - /* U42 */ - eeprom0: eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <0x20>; - }; - - /* U38 */ - eeprom1: eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - pagesize = <0x20>; - }; -}; - -&cp0_i2c1 { - status = "okay"; - clock-frequency = <100000>; - - /* SLM-1521-V2 - U3 */ - i2c-mux@72 { /* verify address - depends on dpr */ - compatible = "nxp,pca9544"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72>; - cp0_sfpp0_i2c: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - /* U12 */ - cp0_module_expander1: pca9555@21 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x21>; - }; - - }; - }; -}; - -&cp0_mdio { - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -/* U54 */ -&cp0_nand_controller { - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins &nand_rb>; - - nand@0 { - reg = <0>; - label = "main-storage"; - nand-rb = <0>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x200000>; - }; - partition@200000 { - label = "Linux"; - reg = <0x200000 0xe00000>; - }; - partition@1000000 { - label = "Filesystem"; - reg = <0x1000000 0x3f000000>; - }; - }; - }; -}; - -/* SLM-1521-V2, CON6 */ -&cp0_pcie0 { - status = "okay"; - num-lanes = <4>; - num-viewport = <8>; - /* Generic PHY, providing serdes lanes */ - phys = <&cp0_comphy0 0 - &cp0_comphy1 0 - &cp0_comphy2 0 - &cp0_comphy3 0>; -}; - -&cp0_sata0 { - status = "okay"; - - /* SLM-1521-V2, CON2 */ - sata-port@1 { - status = "okay"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp0_comphy5 1>; - }; -}; - -/* CON 28 */ -&cp0_sdhci0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_sdhci_pins - &cp0_sdhci_cd_pins>; - bus-width = <4>; - cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>; - no-1-8-v; - vqmmc-supply = <&cp0_reg_sd_vccq>; - vmmc-supply = <&cp0_reg_sd_vcc>; -}; - -/* U55 */ -&cp0_spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&cp0_spi0_pins>; - reg = <0x700680 0x50>; - - spi-flash@0 { - #address-cells = <0x1>; - #size-cells = <0x1>; - compatible = "jedec,spi-nor"; - reg = <0x0>; - /* On-board MUX does not allow higher frequencies */ - spi-max-frequency = <40000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot-0"; - reg = <0x0 0x200000>; - }; - - partition@400000 { - label = "Filesystem-0"; - reg = <0x200000 0xe00000>; - }; - }; - }; -}; - -&cp0_syscon0 { - cp0_pinctrl: pinctrl { - compatible = "marvell,cp115-standalone-pinctrl"; - - cp0_i2c0_pins: cp0-i2c-pins-0 { - marvell,pins = "mpp37", "mpp38"; - marvell,function = "i2c0"; - }; - cp0_i2c1_pins: cp0-i2c-pins-1 { - marvell,pins = "mpp35", "mpp36"; - marvell,function = "i2c1"; - }; - cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 { - marvell,pins = "mpp0", "mpp1", "mpp2", - "mpp3", "mpp4", "mpp5", - "mpp6", "mpp7", "mpp8", - "mpp9", "mpp10", "mpp11"; - marvell,function = "ge0"; - }; - cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 { - marvell,pins = "mpp44", "mpp45", "mpp46", - "mpp47", "mpp48", "mpp49", - "mpp50", "mpp51", "mpp52", - "mpp53", "mpp54", "mpp55"; - marvell,function = "ge1"; - }; - cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 { - marvell,pins = "mpp43"; - marvell,function = "gpio"; - }; - cp0_sdhci_pins: cp0-sdhi-pins-0 { - marvell,pins = "mpp56", "mpp57", "mpp58", - "mpp59", "mpp60", "mpp61"; - marvell,function = "sdio"; - }; - cp0_spi0_pins: cp0-spi-pins-0 { - marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; - marvell,function = "spi1"; - }; - nand_pins: nand-pins { - marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18", - "mpp19", "mpp20", "mpp21", "mpp22", - "mpp23", "mpp24", "mpp25", "mpp26", - "mpp27"; - marvell,function = "dev"; - }; - nand_rb: nand-rb { - marvell,pins = "mpp13"; - marvell,function = "nf"; - }; - }; -}; - -&cp0_usb3_0 { - status = "okay"; - usb-phy = <&cp0_usb3_0_phy0>; - phy-names = "usb"; -}; - -&cp0_usb3_1 { - status = "okay"; - usb-phy = <&cp0_usb3_0_phy1>; - phy-names = "usb"; -}; diff --git a/arch/arm64/boot/dts/marvell/cn9130.dtsi b/arch/arm64/boot/dts/marvell/cn9130.dtsi deleted file mode 100644 index 327b04134..000000000 --- a/arch/arm64/boot/dts/marvell/cn9130.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Marvell International Ltd. - * - * Device tree for the CN9130 SoC. - */ - -#include "armada-ap807-quad.dtsi" - -/ { - model = "Marvell Armada CN9130 SoC"; - compatible = "marvell,cn9130", "marvell,armada-ap807-quad", - "marvell,armada-ap807"; - - aliases { - gpio1 = &cp0_gpio1; - gpio2 = &cp0_gpio2; - spi1 = &cp0_spi0; - spi2 = &cp0_spi1; - }; -}; - -/* - * Instantiate the internal CP115 - */ - -#define CP11X_NAME cp0 -#define CP11X_BASE f2000000 -#define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \ - 0xe0000000 + ((iface - 1) * 0x1000000)) -#define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000) -#define CP11X_PCIE0_BASE f2600000 -#define CP11X_PCIE1_BASE f2620000 -#define CP11X_PCIE2_BASE f2640000 - -#include "armada-cp115.dtsi" - -#undef CP11X_NAME -#undef CP11X_BASE -#undef CP11X_PCIEx_MEM_BASE -#undef CP11X_PCIEx_MEM_SIZE -#undef CP11X_PCIE0_BASE -#undef CP11X_PCIE1_BASE -#undef CP11X_PCIE2_BASE - -&cp0_gpio1 { - status = "okay"; -}; - -&cp0_gpio2 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dts b/arch/arm64/boot/dts/marvell/cn9131-db.dts deleted file mode 100644 index 3c975f98b..000000000 --- a/arch/arm64/boot/dts/marvell/cn9131-db.dts +++ /dev/null @@ -1,202 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Marvell International Ltd. - * - * Device tree for the CN9131-DB board. - */ - -#include "cn9130-db.dts" - -/ { - model = "Marvell Armada CN9131-DB"; - compatible = "marvell,cn9131", "marvell,cn9130", - "marvell,armada-ap807-quad", "marvell,armada-ap807"; - - aliases { - gpio3 = &cp1_gpio1; - gpio4 = &cp1_gpio2; - ethernet3 = &cp1_eth0; - ethernet4 = &cp1_eth1; - }; - - cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&cp1_xhci0_vbus_pins>; - regulator-name = "cp1-xhci0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>; - }; - - cp1_usb3_0_phy0: cp1_usb3_phy0 { - compatible = "usb-nop-xceiv"; - vcc-supply = <&cp1_reg_usb3_vbus0>; - }; - - cp1_sfp_eth1: sfp-eth1 { - compatible = "sff,sfp"; - i2c-bus = <&cp1_i2c0>; - los-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cp1_sfp_pins>; - /* - * SFP cages are unconnected on early PCBs because of an the I2C - * lanes not being connected. Prevent the port for being - * unusable by disabling the SFP node. - */ - status = "disabled"; - }; -}; - -/* - * Instantiate the first slave CP115 - */ - -#define CP11X_NAME cp1 -#define CP11X_BASE f4000000 -#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000)) -#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 -#define CP11X_PCIE0_BASE f4600000 -#define CP11X_PCIE1_BASE f4620000 -#define CP11X_PCIE2_BASE f4640000 - -#include "armada-cp115.dtsi" - -#undef CP11X_NAME -#undef CP11X_BASE -#undef CP11X_PCIEx_MEM_BASE -#undef CP11X_PCIEx_MEM_SIZE -#undef CP11X_PCIE0_BASE -#undef CP11X_PCIE1_BASE -#undef CP11X_PCIE2_BASE - -&cp1_crypto { - status = "disabled"; -}; - -&cp1_ethernet { - status = "okay"; -}; - -/* CON50 */ -&cp1_eth0 { - status = "disabled"; - phy-mode = "10gbase-kr"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp1_comphy4 0>; - managed = "in-band-status"; - sfp = <&cp1_sfp_eth1>; -}; - -&cp1_gpio1 { - status = "okay"; -}; - -&cp1_gpio2 { - status = "okay"; -}; - -&cp1_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&cp1_i2c0_pins>; - clock-frequency = <100000>; -}; - -/* CON40 */ -&cp1_pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&cp1_pcie_reset_pins>; - num-lanes = <2>; - num-viewport = <8>; - marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>; - status = "okay"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp1_comphy0 0 - &cp1_comphy1 0>; -}; - -&cp1_sata0 { - status = "okay"; - - /* CON32 */ - sata-port@1 { - /* Generic PHY, providing serdes lanes */ - phys = <&cp1_comphy5 1>; - }; -}; - -/* U24 */ -&cp1_spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&cp1_spi0_pins>; - reg = <0x700680 0x50>; - - spi-flash@0 { - #address-cells = <0x1>; - #size-cells = <0x1>; - compatible = "jedec,spi-nor"; - reg = <0x0>; - /* On-board MUX does not allow higher frequencies */ - spi-max-frequency = <40000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot-1"; - reg = <0x0 0x200000>; - }; - - partition@400000 { - label = "Filesystem-1"; - reg = <0x200000 0xe00000>; - }; - }; - }; - -}; - -&cp1_syscon0 { - cp1_pinctrl: pinctrl { - compatible = "marvell,cp115-standalone-pinctrl"; - - cp1_i2c0_pins: cp1-i2c-pins-0 { - marvell,pins = "mpp37", "mpp38"; - marvell,function = "i2c0"; - }; - cp1_spi0_pins: cp1-spi-pins-0 { - marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16"; - marvell,function = "spi1"; - }; - cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins { - marvell,pins = "mpp3"; - marvell,function = "gpio"; - }; - cp1_sfp_pins: sfp-pins { - marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11"; - marvell,function = "gpio"; - }; - cp1_pcie_reset_pins: cp1-pcie-reset-pins { - marvell,pins = "mpp0"; - marvell,function = "gpio"; - }; - }; -}; - -/* CON58 */ -&cp1_usb3_1 { - status = "okay"; - usb-phy = <&cp1_usb3_0_phy0>; - /* Generic PHY, providing serdes lanes */ - phys = <&cp1_comphy3 1>; - phy-names = "usb"; -}; diff --git a/arch/arm64/boot/dts/marvell/cn9132-db.dts b/arch/arm64/boot/dts/marvell/cn9132-db.dts deleted file mode 100644 index 4ef0df309..000000000 --- a/arch/arm64/boot/dts/marvell/cn9132-db.dts +++ /dev/null @@ -1,221 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Marvell International Ltd. - * - * Device tree for the CN9132-DB board. - */ - -#include "cn9131-db.dts" - -/ { - model = "Marvell Armada CN9132-DB"; - compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130", - "marvell,armada-ap807-quad", "marvell,armada-ap807"; - - aliases { - gpio5 = &cp2_gpio1; - gpio6 = &cp2_gpio2; - ethernet5 = &cp2_eth0; - }; - - cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 { - compatible = "regulator-fixed"; - regulator-name = "cp2-xhci0-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>; - }; - - cp2_usb3_0_phy0: cp2_usb3_phy0 { - compatible = "usb-nop-xceiv"; - vcc-supply = <&cp2_reg_usb3_vbus0>; - }; - - cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 { - compatible = "regulator-fixed"; - regulator-name = "cp2-xhci1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>; - }; - - cp2_usb3_0_phy1: cp2_usb3_phy1 { - compatible = "usb-nop-xceiv"; - vcc-supply = <&cp2_reg_usb3_vbus1>; - }; - - cp2_reg_sd_vccq: cp2_sd_vccq@0 { - compatible = "regulator-gpio"; - regulator-name = "cp2_sd_vcc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios = <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>; - states = <1800000 0x1 3300000 0x0>; - }; - - cp2_sfp_eth0: sfp-eth0 { - compatible = "sff,sfp"; - i2c-bus = <&cp2_sfpp0_i2c>; - los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>; - /* - * SFP cages are unconnected on early PCBs because of an the I2C - * lanes not being connected. Prevent the port for being - * unusable by disabling the SFP node. - */ - status = "disabled"; - }; -}; - -/* - * Instantiate the second slave CP115 - */ - -#define CP11X_NAME cp2 -#define CP11X_BASE f6000000 -#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000)) -#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 -#define CP11X_PCIE0_BASE f6600000 -#define CP11X_PCIE1_BASE f6620000 -#define CP11X_PCIE2_BASE f6640000 - -#include "armada-cp115.dtsi" - -#undef CP11X_NAME -#undef CP11X_BASE -#undef CP11X_PCIEx_MEM_BASE -#undef CP11X_PCIEx_MEM_SIZE -#undef CP11X_PCIE0_BASE -#undef CP11X_PCIE1_BASE -#undef CP11X_PCIE2_BASE - -&cp2_crypto { - status = "disabled"; -}; - -&cp2_ethernet { - status = "okay"; -}; - -/* SLM-1521-V2, CON9 */ -&cp2_eth0 { - status = "disabled"; - phy-mode = "10gbase-kr"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp2_comphy4 0>; - managed = "in-band-status"; - sfp = <&cp2_sfp_eth0>; -}; - -&cp2_gpio1 { - status = "okay"; -}; - -&cp2_gpio2 { - status = "okay"; -}; - -&cp2_i2c0 { - clock-frequency = <100000>; - - /* SLM-1521-V2 - U3 */ - i2c-mux@72 { - compatible = "nxp,pca9544"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72>; - cp2_sfpp0_i2c: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - /* U12 */ - cp2_module_expander1: pca9555@21 { - compatible = "nxp,pca9555"; - pinctrl-names = "default"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x21>; - }; - }; - }; -}; - -/* SLM-1521-V2, CON6 */ -&cp2_pcie0 { - status = "okay"; - num-lanes = <2>; - num-viewport = <8>; - /* Generic PHY, providing serdes lanes */ - phys = <&cp2_comphy0 0 - &cp2_comphy1 0>; -}; - -/* SLM-1521-V2, CON8 */ -&cp2_pcie2 { - status = "okay"; - num-lanes = <1>; - num-viewport = <8>; - /* Generic PHY, providing serdes lanes */ - phys = <&cp2_comphy5 2>; -}; - -&cp2_sata0 { - status = "okay"; - - /* SLM-1521-V2, CON4 */ - sata-port@0 { - /* Generic PHY, providing serdes lanes */ - phys = <&cp2_comphy2 0>; - }; -}; - -/* CON 2 on SLM-1683 - microSD */ -&cp2_sdhci0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&cp2_sdhci_pins>; - bus-width = <4>; - cd-gpios = <&cp2_gpio2 23 GPIO_ACTIVE_LOW>; - vqmmc-supply = <&cp2_reg_sd_vccq>; -}; - -&cp2_syscon0 { - cp2_pinctrl: pinctrl { - compatible = "marvell,cp115-standalone-pinctrl"; - - cp2_i2c0_pins: cp2-i2c-pins-0 { - marvell,pins = "mpp37", "mpp38"; - marvell,function = "i2c0"; - }; - cp2_sdhci_pins: cp2-sdhi-pins-0 { - marvell,pins = "mpp56", "mpp57", "mpp58", - "mpp59", "mpp60", "mpp61"; - marvell,function = "sdio"; - }; - }; -}; - -&cp2_usb3_0 { - status = "okay"; - usb-phy = <&cp2_usb3_0_phy0>; - phy-names = "usb"; -}; - -/* SLM-1521-V2, CON11 */ -&cp2_usb3_1 { - status = "okay"; - usb-phy = <&cp2_usb3_0_phy1>; - phy-names = "usb"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp2_comphy3 1>; -}; diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile deleted file mode 100644 index 3ee682c26..000000000 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb -dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb -dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb -dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb -dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb -dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb -dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb -dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb -dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb -dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb -dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb -dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb -dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb -dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts deleted file mode 100644 index 7d369fdd3..000000000 --- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: YT Shen - * - * SPDX-License-Identifier: (GPL-2.0 OR MIT) - */ - -/dts-v1/; -#include -#include "mt2712e.dtsi" - -/ { - model = "MediaTek MT2712 evaluation board"; - compatible = "mediatek,mt2712-evb", "mediatek,mt2712"; - - aliases { - serial0 = &uart0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x80000000>; - }; - - chosen { - stdout-path = "serial0:921600n8"; - }; - - cpus_fixed_vproc0: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vproc_buck0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - cpus_fixed_vproc1: fixedregulator@1 { - compatible = "regulator-fixed"; - regulator-name = "vproc_buck1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - extcon_usb: extcon_iddig { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pio 12 GPIO_ACTIVE_HIGH>; - }; - - extcon_usb1: extcon_iddig1 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pio 14 GPIO_ACTIVE_HIGH>; - }; - - usb_p0_vbus: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "p0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 13 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usb_p1_vbus: regulator@3 { - compatible = "regulator-fixed"; - regulator-name = "p1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usb_p2_vbus: regulator@4 { - compatible = "regulator-fixed"; - regulator-name = "p2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usb_p3_vbus: regulator@5 { - compatible = "regulator-fixed"; - regulator-name = "p3_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - -}; - -&auxadc { - status = "okay"; -}; - -&cpu0 { - proc-supply = <&cpus_fixed_vproc0>; -}; - -&cpu1 { - proc-supply = <&cpus_fixed_vproc0>; -}; - -&cpu2 { - proc-supply = <&cpus_fixed_vproc1>; -}; - -ð { - phy-mode ="rgmii-rxid"; - phy-handle = <ðernet_phy0>; - mediatek,tx-delay-ps = <1530>; - snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <ð_default>; - pinctrl-1 = <ð_sleep>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - ethernet_phy0: ethernet-phy@5 { - compatible = "ethernet-phy-id0243.0d90"; - reg = <0x5>; - }; - }; -}; - -&pio { - eth_default: eth_default { - tx_pins { - pinmux = , - , - , - , - , - ; - drive-strength = ; - }; - rx_pins { - pinmux = , - , - , - , - , - ; - input-enable; - }; - mdio_pins { - pinmux = , - ; - drive-strength = ; - input-enable; - }; - }; - - eth_sleep: eth_sleep { - tx_pins { - pinmux = , - , - , - , - , - ; - }; - rx_pins { - pinmux = , - , - , - , - , - ; - input-disable; - }; - mdio_pins { - pinmux = , - ; - input-disable; - bias-disable; - }; - }; - - usb0_id_pins_float: usb0_iddig { - pins_iddig { - pinmux = ; - bias-pull-up; - }; - }; - - usb1_id_pins_float: usb1_iddig { - pins_iddig { - pinmux = ; - bias-pull-up; - }; - }; -}; - -&ssusb { - vbus-supply = <&usb_p0_vbus>; - extcon = <&extcon_usb>; - dr_mode = "otg"; - wakeup-source; - mediatek,u3p-dis-msk = <0x1>; - //enable-manual-drd; - //maximum-speed = "full-speed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_pins_float>; - status = "okay"; -}; - -&ssusb1 { - vbus-supply = <&usb_p1_vbus>; - extcon = <&extcon_usb1>; - dr_mode = "otg"; - //mediatek,u3p-dis-msk = <0x1>; - enable-manual-drd; - wakeup-source; - //maximum-speed = "full-speed"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_id_pins_float>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&usb_host0 { - vbus-supply = <&usb_p2_vbus>; - status = "okay"; -}; - -&usb_host1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h deleted file mode 100644 index 385c455a7..000000000 --- a/arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h +++ /dev/null @@ -1,1123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 MediaTek Inc. - * Author: Zhiyong Tao - * - */ -#ifndef __DTS_MT2712_PINFUNC_H -#define __DTS_MT2712_PINFUNC_H - -#include - -#define MT2712_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) -#define MT2712_PIN_0_EINT0__FUNC_EINT0 (MTK_PIN_NO(0) | 1) -#define MT2712_PIN_0_EINT0__FUNC_MBIST_DIAG_SCANOUT (MTK_PIN_NO(0) | 2) -#define MT2712_PIN_0_EINT0__FUNC_DSIA_TE (MTK_PIN_NO(0) | 3) -#define MT2712_PIN_0_EINT0__FUNC_DSIC_TE (MTK_PIN_NO(0) | 4) -#define MT2712_PIN_0_EINT0__FUNC_DIN_D3 (MTK_PIN_NO(0) | 5) -#define MT2712_PIN_0_EINT0__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(0) | 6) - -#define MT2712_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) -#define MT2712_PIN_1_EINT1__FUNC_EINT1 (MTK_PIN_NO(1) | 1) -#define MT2712_PIN_1_EINT1__FUNC_IR_IN (MTK_PIN_NO(1) | 2) -#define MT2712_PIN_1_EINT1__FUNC_DSIB_TE (MTK_PIN_NO(1) | 3) -#define MT2712_PIN_1_EINT1__FUNC_DSID_TE (MTK_PIN_NO(1) | 4) -#define MT2712_PIN_1_EINT1__FUNC_DIN_D4 (MTK_PIN_NO(1) | 5) - -#define MT2712_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) -#define MT2712_PIN_2_EINT2__FUNC_EINT2 (MTK_PIN_NO(2) | 1) -#define MT2712_PIN_2_EINT2__FUNC_IR_IN (MTK_PIN_NO(2) | 2) -#define MT2712_PIN_2_EINT2__FUNC_LCM_RST1 (MTK_PIN_NO(2) | 3) -#define MT2712_PIN_2_EINT2__FUNC_DIN_D5 (MTK_PIN_NO(2) | 5) - -#define MT2712_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) -#define MT2712_PIN_3_EINT3__FUNC_EINT3 (MTK_PIN_NO(3) | 1) -#define MT2712_PIN_3_EINT3__FUNC_IR_IN (MTK_PIN_NO(3) | 2) -#define MT2712_PIN_3_EINT3__FUNC_LCM_RST0 (MTK_PIN_NO(3) | 3) -#define MT2712_PIN_3_EINT3__FUNC_DIN_D6 (MTK_PIN_NO(3) | 5) - -#define MT2712_PIN_4_PWM0__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) -#define MT2712_PIN_4_PWM0__FUNC_PWM0 (MTK_PIN_NO(4) | 1) -#define MT2712_PIN_4_PWM0__FUNC_DISP0_PWM (MTK_PIN_NO(4) | 2) -#define MT2712_PIN_4_PWM0__FUNC_DISP1_PWM (MTK_PIN_NO(4) | 3) -#define MT2712_PIN_4_PWM0__FUNC_DIN_CLK (MTK_PIN_NO(4) | 5) - -#define MT2712_PIN_5_PWM1__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) -#define MT2712_PIN_5_PWM1__FUNC_PWM1 (MTK_PIN_NO(5) | 1) -#define MT2712_PIN_5_PWM1__FUNC_DISP1_PWM (MTK_PIN_NO(5) | 2) -#define MT2712_PIN_5_PWM1__FUNC_DISP0_PWM (MTK_PIN_NO(5) | 3) -#define MT2712_PIN_5_PWM1__FUNC_DIN_VSYNC (MTK_PIN_NO(5) | 5) - -#define MT2712_PIN_6_PWM2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) -#define MT2712_PIN_6_PWM2__FUNC_PWM2 (MTK_PIN_NO(6) | 1) -#define MT2712_PIN_6_PWM2__FUNC_DISP0_PWM (MTK_PIN_NO(6) | 2) -#define MT2712_PIN_6_PWM2__FUNC_DISP1_PWM (MTK_PIN_NO(6) | 3) -#define MT2712_PIN_6_PWM2__FUNC_DISP2_PWM (MTK_PIN_NO(6) | 4) -#define MT2712_PIN_6_PWM2__FUNC_DIN_HSYNC (MTK_PIN_NO(6) | 5) - -#define MT2712_PIN_7_PWM3__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) -#define MT2712_PIN_7_PWM3__FUNC_PWM3 (MTK_PIN_NO(7) | 1) -#define MT2712_PIN_7_PWM3__FUNC_DISP1_PWM (MTK_PIN_NO(7) | 2) -#define MT2712_PIN_7_PWM3__FUNC_DISP0_PWM (MTK_PIN_NO(7) | 3) -#define MT2712_PIN_7_PWM3__FUNC_LCM_RST2 (MTK_PIN_NO(7) | 4) -#define MT2712_PIN_7_PWM3__FUNC_DIN_D0 (MTK_PIN_NO(7) | 5) - -#define MT2712_PIN_8_PWM4__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) -#define MT2712_PIN_8_PWM4__FUNC_PWM4 (MTK_PIN_NO(8) | 1) -#define MT2712_PIN_8_PWM4__FUNC_DISP0_PWM (MTK_PIN_NO(8) | 2) -#define MT2712_PIN_8_PWM4__FUNC_DISP1_PWM (MTK_PIN_NO(8) | 3) -#define MT2712_PIN_8_PWM4__FUNC_DSIA_TE (MTK_PIN_NO(8) | 4) -#define MT2712_PIN_8_PWM4__FUNC_DIN_D1 (MTK_PIN_NO(8) | 5) - -#define MT2712_PIN_9_PWM5__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) -#define MT2712_PIN_9_PWM5__FUNC_PWM5 (MTK_PIN_NO(9) | 1) -#define MT2712_PIN_9_PWM5__FUNC_DISP1_PWM (MTK_PIN_NO(9) | 2) -#define MT2712_PIN_9_PWM5__FUNC_DISP0_PWM (MTK_PIN_NO(9) | 3) -#define MT2712_PIN_9_PWM5__FUNC_DSIB_TE (MTK_PIN_NO(9) | 4) -#define MT2712_PIN_9_PWM5__FUNC_DIN_D2 (MTK_PIN_NO(9) | 5) - -#define MT2712_PIN_10_PWM6__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) -#define MT2712_PIN_10_PWM6__FUNC_PWM6 (MTK_PIN_NO(10) | 1) -#define MT2712_PIN_10_PWM6__FUNC_DISP0_PWM (MTK_PIN_NO(10) | 2) -#define MT2712_PIN_10_PWM6__FUNC_DISP1_PWM (MTK_PIN_NO(10) | 3) -#define MT2712_PIN_10_PWM6__FUNC_LCM_RST0 (MTK_PIN_NO(10) | 4) - -#define MT2712_PIN_11_PWM7__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) -#define MT2712_PIN_11_PWM7__FUNC_PWM7 (MTK_PIN_NO(11) | 1) -#define MT2712_PIN_11_PWM7__FUNC_DISP1_PWM (MTK_PIN_NO(11) | 2) -#define MT2712_PIN_11_PWM7__FUNC_DISP0_PWM (MTK_PIN_NO(11) | 3) -#define MT2712_PIN_11_PWM7__FUNC_LCM_RST1 (MTK_PIN_NO(11) | 4) - -#define MT2712_PIN_12_IDDIG_P0__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) -#define MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A (MTK_PIN_NO(12) | 1) -#define MT2712_PIN_12_IDDIG_P0__FUNC_DIN_D7 (MTK_PIN_NO(12) | 5) - -#define MT2712_PIN_13_DRV_VBUS_P0__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) -#define MT2712_PIN_13_DRV_VBUS_P0__FUNC_DRV_VBUS_A (MTK_PIN_NO(13) | 1) - -#define MT2712_PIN_14_IDDIG_P1__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) -#define MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B (MTK_PIN_NO(14) | 1) - -#define MT2712_PIN_15_DRV_VBUS_P1__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) -#define MT2712_PIN_15_DRV_VBUS_P1__FUNC_DRV_VBUS_B (MTK_PIN_NO(15) | 1) - -#define MT2712_PIN_16_DRV_VBUS_P2__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) -#define MT2712_PIN_16_DRV_VBUS_P2__FUNC_DRV_VBUS_C (MTK_PIN_NO(16) | 1) - -#define MT2712_PIN_17_DRV_VBUS_P3__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) -#define MT2712_PIN_17_DRV_VBUS_P3__FUNC_DRV_VBUS_D (MTK_PIN_NO(17) | 1) - -#define MT2712_PIN_18_KPROW0__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) -#define MT2712_PIN_18_KPROW0__FUNC_KROW0 (MTK_PIN_NO(18) | 1) - -#define MT2712_PIN_19_KPCOL0__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) -#define MT2712_PIN_19_KPCOL0__FUNC_KCOL0 (MTK_PIN_NO(19) | 1) - -#define MT2712_PIN_20_KPROW1__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) -#define MT2712_PIN_20_KPROW1__FUNC_KROW1 (MTK_PIN_NO(20) | 1) - -#define MT2712_PIN_21_KPCOL1__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) -#define MT2712_PIN_21_KPCOL1__FUNC_KCOL1 (MTK_PIN_NO(21) | 1) - -#define MT2712_PIN_22_KPROW2__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) -#define MT2712_PIN_22_KPROW2__FUNC_KROW2 (MTK_PIN_NO(22) | 1) -#define MT2712_PIN_22_KPROW2__FUNC_DISP1_PWM (MTK_PIN_NO(22) | 2) - -#define MT2712_PIN_23_KPCOL2__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) -#define MT2712_PIN_23_KPCOL2__FUNC_KCOL2 (MTK_PIN_NO(23) | 1) -#define MT2712_PIN_23_KPCOL2__FUNC_DISP0_PWM (MTK_PIN_NO(23) | 2) - -#define MT2712_PIN_24_CMMCLK__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) -#define MT2712_PIN_24_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(24) | 1) -#define MT2712_PIN_24_CMMCLK__FUNC_DBG_MON_A_1_ (MTK_PIN_NO(24) | 7) - -#define MT2712_PIN_25_CM2MCLK__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) -#define MT2712_PIN_25_CM2MCLK__FUNC_CM2MCLK (MTK_PIN_NO(25) | 1) -#define MT2712_PIN_25_CM2MCLK__FUNC_DBG_MON_A_2_ (MTK_PIN_NO(25) | 7) - -#define MT2712_PIN_26_PCM_TX__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) -#define MT2712_PIN_26_PCM_TX__FUNC_PCM1_DO (MTK_PIN_NO(26) | 1) -#define MT2712_PIN_26_PCM_TX__FUNC_MRG_TX (MTK_PIN_NO(26) | 2) -#define MT2712_PIN_26_PCM_TX__FUNC_DAI_TX (MTK_PIN_NO(26) | 3) -#define MT2712_PIN_26_PCM_TX__FUNC_MRG_RX (MTK_PIN_NO(26) | 4) -#define MT2712_PIN_26_PCM_TX__FUNC_DAI_RX (MTK_PIN_NO(26) | 5) -#define MT2712_PIN_26_PCM_TX__FUNC_PCM1_DI (MTK_PIN_NO(26) | 6) -#define MT2712_PIN_26_PCM_TX__FUNC_DBG_MON_A_3_ (MTK_PIN_NO(26) | 7) - -#define MT2712_PIN_27_PCM_CLK__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) -#define MT2712_PIN_27_PCM_CLK__FUNC_PCM1_CLK (MTK_PIN_NO(27) | 1) -#define MT2712_PIN_27_PCM_CLK__FUNC_MRG_CLK (MTK_PIN_NO(27) | 2) -#define MT2712_PIN_27_PCM_CLK__FUNC_DAI_CLK (MTK_PIN_NO(27) | 3) -#define MT2712_PIN_27_PCM_CLK__FUNC_DBG_MON_A_4_ (MTK_PIN_NO(27) | 7) - -#define MT2712_PIN_28_PCM_RX__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) -#define MT2712_PIN_28_PCM_RX__FUNC_PCM1_DI (MTK_PIN_NO(28) | 1) -#define MT2712_PIN_28_PCM_RX__FUNC_MRG_RX (MTK_PIN_NO(28) | 2) -#define MT2712_PIN_28_PCM_RX__FUNC_DAI_RX (MTK_PIN_NO(28) | 3) -#define MT2712_PIN_28_PCM_RX__FUNC_MRG_TX (MTK_PIN_NO(28) | 4) -#define MT2712_PIN_28_PCM_RX__FUNC_DAI_TX (MTK_PIN_NO(28) | 5) -#define MT2712_PIN_28_PCM_RX__FUNC_PCM1_DO (MTK_PIN_NO(28) | 6) -#define MT2712_PIN_28_PCM_RX__FUNC_DBG_MON_A_5_ (MTK_PIN_NO(28) | 7) - -#define MT2712_PIN_29_PCM_SYNC__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) -#define MT2712_PIN_29_PCM_SYNC__FUNC_PCM1_SYNC (MTK_PIN_NO(29) | 1) -#define MT2712_PIN_29_PCM_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(29) | 2) -#define MT2712_PIN_29_PCM_SYNC__FUNC_DAI_SYNC (MTK_PIN_NO(29) | 3) -#define MT2712_PIN_29_PCM_SYNC__FUNC_DBG_MON_A_6_ (MTK_PIN_NO(29) | 7) - -#define MT2712_PIN_30_NCEB0__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) -#define MT2712_PIN_30_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(30) | 1) -#define MT2712_PIN_30_NCEB0__FUNC_USB0_FT_SDA (MTK_PIN_NO(30) | 2) -#define MT2712_PIN_30_NCEB0__FUNC_DBG_MON_A_7_ (MTK_PIN_NO(30) | 7) - -#define MT2712_PIN_31_NCEB1__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) -#define MT2712_PIN_31_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(31) | 1) -#define MT2712_PIN_31_NCEB1__FUNC_USB1_FT_SCL (MTK_PIN_NO(31) | 2) -#define MT2712_PIN_31_NCEB1__FUNC_DBG_MON_A_8_ (MTK_PIN_NO(31) | 7) - -#define MT2712_PIN_32_NF_DQS__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) -#define MT2712_PIN_32_NF_DQS__FUNC_NF_DQS (MTK_PIN_NO(32) | 1) -#define MT2712_PIN_32_NF_DQS__FUNC_USB1_FT_SDA (MTK_PIN_NO(32) | 2) -#define MT2712_PIN_32_NF_DQS__FUNC_DBG_MON_A_9_ (MTK_PIN_NO(32) | 7) - -#define MT2712_PIN_33_NWEB__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) -#define MT2712_PIN_33_NWEB__FUNC_NWEB (MTK_PIN_NO(33) | 1) -#define MT2712_PIN_33_NWEB__FUNC_USB2_FT_SCL (MTK_PIN_NO(33) | 2) -#define MT2712_PIN_33_NWEB__FUNC_DBG_MON_A_10_ (MTK_PIN_NO(33) | 7) - -#define MT2712_PIN_34_NREB__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) -#define MT2712_PIN_34_NREB__FUNC_NREB (MTK_PIN_NO(34) | 1) -#define MT2712_PIN_34_NREB__FUNC_USB2_FT_SDA (MTK_PIN_NO(34) | 2) -#define MT2712_PIN_34_NREB__FUNC_DBG_MON_A_11_ (MTK_PIN_NO(34) | 7) - -#define MT2712_PIN_35_NCLE__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) -#define MT2712_PIN_35_NCLE__FUNC_NCLE (MTK_PIN_NO(35) | 1) -#define MT2712_PIN_35_NCLE__FUNC_USB3_FT_SCL (MTK_PIN_NO(35) | 2) -#define MT2712_PIN_35_NCLE__FUNC_DBG_MON_A_12_ (MTK_PIN_NO(35) | 7) - -#define MT2712_PIN_36_NALE__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) -#define MT2712_PIN_36_NALE__FUNC_NALE (MTK_PIN_NO(36) | 1) -#define MT2712_PIN_36_NALE__FUNC_USB3_FT_SDA (MTK_PIN_NO(36) | 2) -#define MT2712_PIN_36_NALE__FUNC_DBG_MON_A_13_ (MTK_PIN_NO(36) | 7) - -#define MT2712_PIN_37_MSDC0E_CLK__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) -#define MT2712_PIN_37_MSDC0E_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(37) | 1) -#define MT2712_PIN_37_MSDC0E_CLK__FUNC_USB0_FT_SCL (MTK_PIN_NO(37) | 2) -#define MT2712_PIN_37_MSDC0E_CLK__FUNC_DBG_MON_A_0_ (MTK_PIN_NO(37) | 7) - -#define MT2712_PIN_38_MSDC0E_DAT7__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) -#define MT2712_PIN_38_MSDC0E_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(38) | 1) -#define MT2712_PIN_38_MSDC0E_DAT7__FUNC_NAND_ND7 (MTK_PIN_NO(38) | 2) -#define MT2712_PIN_38_MSDC0E_DAT7__FUNC_DBG_MON_A_14_ (MTK_PIN_NO(38) | 7) - -#define MT2712_PIN_39_MSDC0E_DAT6__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) -#define MT2712_PIN_39_MSDC0E_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(39) | 1) -#define MT2712_PIN_39_MSDC0E_DAT6__FUNC_NAND_ND6 (MTK_PIN_NO(39) | 2) -#define MT2712_PIN_39_MSDC0E_DAT6__FUNC_DBG_MON_A_15_ (MTK_PIN_NO(39) | 7) - -#define MT2712_PIN_40_MSDC0E_DAT5__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) -#define MT2712_PIN_40_MSDC0E_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(40) | 1) -#define MT2712_PIN_40_MSDC0E_DAT5__FUNC_NAND_ND5 (MTK_PIN_NO(40) | 2) -#define MT2712_PIN_40_MSDC0E_DAT5__FUNC_DBG_MON_A_16_ (MTK_PIN_NO(40) | 7) - -#define MT2712_PIN_41_MSDC0E_DAT4__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) -#define MT2712_PIN_41_MSDC0E_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(41) | 1) -#define MT2712_PIN_41_MSDC0E_DAT4__FUNC_NAND_ND4 (MTK_PIN_NO(41) | 2) -#define MT2712_PIN_41_MSDC0E_DAT4__FUNC_DBG_MON_A_17_ (MTK_PIN_NO(41) | 7) - -#define MT2712_PIN_42_MSDC0E_DAT3__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) -#define MT2712_PIN_42_MSDC0E_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(42) | 1) -#define MT2712_PIN_42_MSDC0E_DAT3__FUNC_NAND_ND3 (MTK_PIN_NO(42) | 2) -#define MT2712_PIN_42_MSDC0E_DAT3__FUNC_DBG_MON_A_18_ (MTK_PIN_NO(42) | 7) - -#define MT2712_PIN_43_MSDC0E_DAT2__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) -#define MT2712_PIN_43_MSDC0E_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(43) | 1) -#define MT2712_PIN_43_MSDC0E_DAT2__FUNC_NAND_ND2 (MTK_PIN_NO(43) | 2) -#define MT2712_PIN_43_MSDC0E_DAT2__FUNC_DBG_MON_A_19_ (MTK_PIN_NO(43) | 7) - -#define MT2712_PIN_44_MSDC0E_DAT1__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) -#define MT2712_PIN_44_MSDC0E_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(44) | 1) -#define MT2712_PIN_44_MSDC0E_DAT1__FUNC_NAND_ND1 (MTK_PIN_NO(44) | 2) -#define MT2712_PIN_44_MSDC0E_DAT1__FUNC_DBG_MON_A_20_ (MTK_PIN_NO(44) | 7) - -#define MT2712_PIN_45_MSDC0E_DAT0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) -#define MT2712_PIN_45_MSDC0E_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(45) | 1) -#define MT2712_PIN_45_MSDC0E_DAT0__FUNC_NAND_ND0 (MTK_PIN_NO(45) | 2) -#define MT2712_PIN_45_MSDC0E_DAT0__FUNC_DBG_MON_A_21_ (MTK_PIN_NO(45) | 7) - -#define MT2712_PIN_46_MSDC0E_CMD__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) -#define MT2712_PIN_46_MSDC0E_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(46) | 1) -#define MT2712_PIN_46_MSDC0E_CMD__FUNC_NAND_NRNB (MTK_PIN_NO(46) | 2) -#define MT2712_PIN_46_MSDC0E_CMD__FUNC_DBG_MON_A_22_ (MTK_PIN_NO(46) | 7) - -#define MT2712_PIN_47_MSDC0E_DSL__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) -#define MT2712_PIN_47_MSDC0E_DSL__FUNC_MSDC0_DSL (MTK_PIN_NO(47) | 1) -#define MT2712_PIN_47_MSDC0E_DSL__FUNC_DBG_MON_A_23_ (MTK_PIN_NO(47) | 7) - -#define MT2712_PIN_48_MSDC0E_RSTB__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) -#define MT2712_PIN_48_MSDC0E_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(48) | 1) -#define MT2712_PIN_48_MSDC0E_RSTB__FUNC_DBG_MON_A_24_ (MTK_PIN_NO(48) | 7) - -#define MT2712_PIN_49_MSDC3_DAT3__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) -#define MT2712_PIN_49_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(49) | 1) -#define MT2712_PIN_49_MSDC3_DAT3__FUNC_DBG_MON_A_25_ (MTK_PIN_NO(49) | 7) - -#define MT2712_PIN_50_MSDC3_DAT2__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) -#define MT2712_PIN_50_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(50) | 1) -#define MT2712_PIN_50_MSDC3_DAT2__FUNC_DBG_MON_A_26_ (MTK_PIN_NO(50) | 7) - -#define MT2712_PIN_51_MSDC3_DAT1__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) -#define MT2712_PIN_51_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(51) | 1) -#define MT2712_PIN_51_MSDC3_DAT1__FUNC_DBG_MON_A_27_ (MTK_PIN_NO(51) | 7) - -#define MT2712_PIN_52_MSDC3_DAT0__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) -#define MT2712_PIN_52_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(52) | 1) -#define MT2712_PIN_52_MSDC3_DAT0__FUNC_DBG_MON_A_28_ (MTK_PIN_NO(52) | 7) - -#define MT2712_PIN_53_MSDC3_CMD__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) -#define MT2712_PIN_53_MSDC3_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(53) | 1) -#define MT2712_PIN_53_MSDC3_CMD__FUNC_DBG_MON_A_29_ (MTK_PIN_NO(53) | 7) - -#define MT2712_PIN_54_MSDC3_INS__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) -#define MT2712_PIN_54_MSDC3_INS__FUNC_MSDC3_INS (MTK_PIN_NO(54) | 1) -#define MT2712_PIN_54_MSDC3_INS__FUNC_DBG_MON_A_30_ (MTK_PIN_NO(54) | 7) - -#define MT2712_PIN_55_MSDC3_DSL__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) -#define MT2712_PIN_55_MSDC3_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(55) | 1) -#define MT2712_PIN_55_MSDC3_DSL__FUNC_DBG_MON_A_31_ (MTK_PIN_NO(55) | 7) - -#define MT2712_PIN_56_MSDC3_CLK__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) -#define MT2712_PIN_56_MSDC3_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(56) | 1) -#define MT2712_PIN_56_MSDC3_CLK__FUNC_DBG_MON_A_32_ (MTK_PIN_NO(56) | 7) - -#define MT2712_PIN_57_NOR_CS__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) -#define MT2712_PIN_57_NOR_CS__FUNC_NOR_CS (MTK_PIN_NO(57) | 1) - -#define MT2712_PIN_58_NOR_CK__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) -#define MT2712_PIN_58_NOR_CK__FUNC_NOR_CK (MTK_PIN_NO(58) | 1) - -#define MT2712_PIN_59_NOR_IO0__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) -#define MT2712_PIN_59_NOR_IO0__FUNC_NOR_IO0 (MTK_PIN_NO(59) | 1) - -#define MT2712_PIN_60_NOR_IO1__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) -#define MT2712_PIN_60_NOR_IO1__FUNC_NOR_IO1 (MTK_PIN_NO(60) | 1) - -#define MT2712_PIN_61_NOR_IO2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) -#define MT2712_PIN_61_NOR_IO2__FUNC_NOR_IO2 (MTK_PIN_NO(61) | 1) - -#define MT2712_PIN_62_NOR_IO3__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) -#define MT2712_PIN_62_NOR_IO3__FUNC_NOR_IO3 (MTK_PIN_NO(62) | 1) - -#define MT2712_PIN_63_MSDC1_CLK__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) -#define MT2712_PIN_63_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(63) | 1) -#define MT2712_PIN_63_MSDC1_CLK__FUNC_UDI_TCK (MTK_PIN_NO(63) | 2) - -#define MT2712_PIN_64_MSDC1_DAT3__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) -#define MT2712_PIN_64_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(64) | 1) -#define MT2712_PIN_64_MSDC1_DAT3__FUNC_UDI_TDI (MTK_PIN_NO(64) | 2) - -#define MT2712_PIN_65_MSDC1_DAT1__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) -#define MT2712_PIN_65_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(65) | 1) -#define MT2712_PIN_65_MSDC1_DAT1__FUNC_UDI_TMS (MTK_PIN_NO(65) | 2) - -#define MT2712_PIN_66_MSDC1_DAT2__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) -#define MT2712_PIN_66_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(66) | 1) -#define MT2712_PIN_66_MSDC1_DAT2__FUNC_UDI_TDO (MTK_PIN_NO(66) | 2) - -#define MT2712_PIN_67_MSDC1_PSW__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) -#define MT2712_PIN_67_MSDC1_PSW__FUNC_UDI_NTRST (MTK_PIN_NO(67) | 2) - -#define MT2712_PIN_68_MSDC1_DAT0__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) -#define MT2712_PIN_68_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(68) | 1) - -#define MT2712_PIN_69_MSDC1_CMD__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) -#define MT2712_PIN_69_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(69) | 1) - -#define MT2712_PIN_70_MSDC1_INS__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) - -#define MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) -#define MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3 (MTK_PIN_NO(71) | 1) -#define MT2712_PIN_71_GBE_TXD3__FUNC_DBG_MON_B_0_ (MTK_PIN_NO(71) | 7) - -#define MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) -#define MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2 (MTK_PIN_NO(72) | 1) -#define MT2712_PIN_72_GBE_TXD2__FUNC_DBG_MON_B_1_ (MTK_PIN_NO(72) | 7) - -#define MT2712_PIN_73_GBE_TXD1__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) -#define MT2712_PIN_73_GBE_TXD1__FUNC_GBE_TXD1 (MTK_PIN_NO(73) | 1) -#define MT2712_PIN_73_GBE_TXD1__FUNC_DBG_MON_B_2_ (MTK_PIN_NO(73) | 7) - -#define MT2712_PIN_74_GBE_TXD0__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) -#define MT2712_PIN_74_GBE_TXD0__FUNC_GBE_TXD0 (MTK_PIN_NO(74) | 1) -#define MT2712_PIN_74_GBE_TXD0__FUNC_DBG_MON_B_3_ (MTK_PIN_NO(74) | 7) - -#define MT2712_PIN_75_GBE_TXC__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) -#define MT2712_PIN_75_GBE_TXC__FUNC_GBE_TXC (MTK_PIN_NO(75) | 1) -#define MT2712_PIN_75_GBE_TXC__FUNC_DBG_MON_B_4_ (MTK_PIN_NO(75) | 7) - -#define MT2712_PIN_76_GBE_TXEN__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) -#define MT2712_PIN_76_GBE_TXEN__FUNC_GBE_TXEN (MTK_PIN_NO(76) | 1) -#define MT2712_PIN_76_GBE_TXEN__FUNC_DBG_MON_B_5_ (MTK_PIN_NO(76) | 7) - -#define MT2712_PIN_77_GBE_TXER__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) -#define MT2712_PIN_77_GBE_TXER__FUNC_GBE_TXER (MTK_PIN_NO(77) | 1) -#define MT2712_PIN_77_GBE_TXER__FUNC_DBG_MON_B_6_ (MTK_PIN_NO(77) | 7) - -#define MT2712_PIN_78_GBE_RXD3__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) -#define MT2712_PIN_78_GBE_RXD3__FUNC_GBE_RXD3 (MTK_PIN_NO(78) | 1) -#define MT2712_PIN_78_GBE_RXD3__FUNC_DBG_MON_B_7_ (MTK_PIN_NO(78) | 7) - -#define MT2712_PIN_79_GBE_RXD2__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) -#define MT2712_PIN_79_GBE_RXD2__FUNC_GBE_RXD2 (MTK_PIN_NO(79) | 1) -#define MT2712_PIN_79_GBE_RXD2__FUNC_DBG_MON_B_8_ (MTK_PIN_NO(79) | 7) - -#define MT2712_PIN_80_GBE_RXD1__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) -#define MT2712_PIN_80_GBE_RXD1__FUNC_GBE_RXD1 (MTK_PIN_NO(80) | 1) -#define MT2712_PIN_80_GBE_RXD1__FUNC_DBG_MON_B_9_ (MTK_PIN_NO(80) | 7) - -#define MT2712_PIN_81_GBE_RXD0__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) -#define MT2712_PIN_81_GBE_RXD0__FUNC_GBE_RXD0 (MTK_PIN_NO(81) | 1) -#define MT2712_PIN_81_GBE_RXD0__FUNC_DBG_MON_B_10_ (MTK_PIN_NO(81) | 7) - -#define MT2712_PIN_82_GBE_RXDV__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) -#define MT2712_PIN_82_GBE_RXDV__FUNC_GBE_RXDV (MTK_PIN_NO(82) | 1) -#define MT2712_PIN_82_GBE_RXDV__FUNC_DBG_MON_B_11_ (MTK_PIN_NO(82) | 7) - -#define MT2712_PIN_83_GBE_RXER__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) -#define MT2712_PIN_83_GBE_RXER__FUNC_GBE_RXER (MTK_PIN_NO(83) | 1) -#define MT2712_PIN_83_GBE_RXER__FUNC_DBG_MON_B_12_ (MTK_PIN_NO(83) | 7) - -#define MT2712_PIN_84_GBE_RXC__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) -#define MT2712_PIN_84_GBE_RXC__FUNC_GBE_RXC (MTK_PIN_NO(84) | 1) -#define MT2712_PIN_84_GBE_RXC__FUNC_DBG_MON_B_13_ (MTK_PIN_NO(84) | 7) - -#define MT2712_PIN_85_GBE_MDC__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) -#define MT2712_PIN_85_GBE_MDC__FUNC_GBE_MDC (MTK_PIN_NO(85) | 1) -#define MT2712_PIN_85_GBE_MDC__FUNC_DBG_MON_B_14_ (MTK_PIN_NO(85) | 7) - -#define MT2712_PIN_86_GBE_MDIO__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) -#define MT2712_PIN_86_GBE_MDIO__FUNC_GBE_MDIO (MTK_PIN_NO(86) | 1) -#define MT2712_PIN_86_GBE_MDIO__FUNC_DBG_MON_B_15_ (MTK_PIN_NO(86) | 7) - -#define MT2712_PIN_87_GBE_COL__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) -#define MT2712_PIN_87_GBE_COL__FUNC_GBE_COL (MTK_PIN_NO(87) | 1) -#define MT2712_PIN_87_GBE_COL__FUNC_DBG_MON_B_16_ (MTK_PIN_NO(87) | 7) - -#define MT2712_PIN_88_GBE_INTR__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) -#define MT2712_PIN_88_GBE_INTR__FUNC_GBE_INTR (MTK_PIN_NO(88) | 1) -#define MT2712_PIN_88_GBE_INTR__FUNC_GBE_CRS (MTK_PIN_NO(88) | 2) -#define MT2712_PIN_88_GBE_INTR__FUNC_DBG_MON_B_17_ (MTK_PIN_NO(88) | 7) - -#define MT2712_PIN_89_MSDC2_CLK__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) -#define MT2712_PIN_89_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(89) | 1) -#define MT2712_PIN_89_MSDC2_CLK__FUNC_DBG_MON_B_18_ (MTK_PIN_NO(89) | 7) - -#define MT2712_PIN_90_MSDC2_DAT3__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) -#define MT2712_PIN_90_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(90) | 1) -#define MT2712_PIN_90_MSDC2_DAT3__FUNC_DBG_MON_B_19_ (MTK_PIN_NO(90) | 7) - -#define MT2712_PIN_91_MSDC2_DAT2__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) -#define MT2712_PIN_91_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(91) | 1) -#define MT2712_PIN_91_MSDC2_DAT2__FUNC_DBG_MON_B_20_ (MTK_PIN_NO(91) | 7) - -#define MT2712_PIN_92_MSDC2_DAT1__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) -#define MT2712_PIN_92_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(92) | 1) -#define MT2712_PIN_92_MSDC2_DAT1__FUNC_DBG_MON_B_21_ (MTK_PIN_NO(92) | 7) - -#define MT2712_PIN_93_MSDC2_DAT0__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) -#define MT2712_PIN_93_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(93) | 1) -#define MT2712_PIN_93_MSDC2_DAT0__FUNC_DBG_MON_B_22_ (MTK_PIN_NO(93) | 7) - -#define MT2712_PIN_94_MSDC2_INS__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) -#define MT2712_PIN_94_MSDC2_INS__FUNC_DBG_MON_B_23_ (MTK_PIN_NO(94) | 7) - -#define MT2712_PIN_95_MSDC2_CMD__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) -#define MT2712_PIN_95_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(95) | 1) -#define MT2712_PIN_95_MSDC2_CMD__FUNC_DBG_MON_B_24_ (MTK_PIN_NO(95) | 7) - -#define MT2712_PIN_96_MSDC2_PSW__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) -#define MT2712_PIN_96_MSDC2_PSW__FUNC_DBG_MON_B_25_ (MTK_PIN_NO(96) | 7) - -#define MT2712_PIN_97_URXD4__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) -#define MT2712_PIN_97_URXD4__FUNC_URXD4 (MTK_PIN_NO(97) | 1) -#define MT2712_PIN_97_URXD4__FUNC_UTXD4 (MTK_PIN_NO(97) | 2) -#define MT2712_PIN_97_URXD4__FUNC_MRG_CLK (MTK_PIN_NO(97) | 3) -#define MT2712_PIN_97_URXD4__FUNC_PCM1_CLK (MTK_PIN_NO(97) | 4) -#define MT2712_PIN_97_URXD4__FUNC_I2S_IQ2_SDQB (MTK_PIN_NO(97) | 5) -#define MT2712_PIN_97_URXD4__FUNC_I2SO1_WS (MTK_PIN_NO(97) | 6) -#define MT2712_PIN_97_URXD4__FUNC_DBG_MON_B_26_ (MTK_PIN_NO(97) | 7) - -#define MT2712_PIN_98_URTS4__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) -#define MT2712_PIN_98_URTS4__FUNC_URTS4 (MTK_PIN_NO(98) | 1) -#define MT2712_PIN_98_URTS4__FUNC_UCTS4 (MTK_PIN_NO(98) | 2) -#define MT2712_PIN_98_URTS4__FUNC_MRG_RX (MTK_PIN_NO(98) | 3) -#define MT2712_PIN_98_URTS4__FUNC_PCM1_DI (MTK_PIN_NO(98) | 4) -#define MT2712_PIN_98_URTS4__FUNC_I2S_IQ1_SDIB (MTK_PIN_NO(98) | 5) -#define MT2712_PIN_98_URTS4__FUNC_I2SO1_MCK (MTK_PIN_NO(98) | 6) -#define MT2712_PIN_98_URTS4__FUNC_DBG_MON_B_27_ (MTK_PIN_NO(98) | 7) - -#define MT2712_PIN_99_UTXD4__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) -#define MT2712_PIN_99_UTXD4__FUNC_UTXD4 (MTK_PIN_NO(99) | 1) -#define MT2712_PIN_99_UTXD4__FUNC_URXD4 (MTK_PIN_NO(99) | 2) -#define MT2712_PIN_99_UTXD4__FUNC_MRG_SYNC (MTK_PIN_NO(99) | 3) -#define MT2712_PIN_99_UTXD4__FUNC_PCM1_SYNC (MTK_PIN_NO(99) | 4) -#define MT2712_PIN_99_UTXD4__FUNC_I2S_IQ0_SDQB (MTK_PIN_NO(99) | 5) -#define MT2712_PIN_99_UTXD4__FUNC_I2SO1_BCK (MTK_PIN_NO(99) | 6) -#define MT2712_PIN_99_UTXD4__FUNC_DBG_MON_B_28_ (MTK_PIN_NO(99) | 7) - -#define MT2712_PIN_100_UCTS4__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) -#define MT2712_PIN_100_UCTS4__FUNC_UCTS4 (MTK_PIN_NO(100) | 1) -#define MT2712_PIN_100_UCTS4__FUNC_URTS4 (MTK_PIN_NO(100) | 2) -#define MT2712_PIN_100_UCTS4__FUNC_MRG_TX (MTK_PIN_NO(100) | 3) -#define MT2712_PIN_100_UCTS4__FUNC_PCM1_DO (MTK_PIN_NO(100) | 4) -#define MT2712_PIN_100_UCTS4__FUNC_I2S_IQ0_SDIB (MTK_PIN_NO(100) | 5) -#define MT2712_PIN_100_UCTS4__FUNC_I2SO1_DO (MTK_PIN_NO(100) | 6) -#define MT2712_PIN_100_UCTS4__FUNC_DBG_MON_B_29_ (MTK_PIN_NO(100) | 7) - -#define MT2712_PIN_101_URXD5__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) -#define MT2712_PIN_101_URXD5__FUNC_URXD5 (MTK_PIN_NO(101) | 1) -#define MT2712_PIN_101_URXD5__FUNC_UTXD5 (MTK_PIN_NO(101) | 2) -#define MT2712_PIN_101_URXD5__FUNC_I2SO3_WS (MTK_PIN_NO(101) | 3) -#define MT2712_PIN_101_URXD5__FUNC_TDMIN_LRCK (MTK_PIN_NO(101) | 4) -#define MT2712_PIN_101_URXD5__FUNC_I2SO0_WS (MTK_PIN_NO(101) | 6) -#define MT2712_PIN_101_URXD5__FUNC_DBG_MON_B_30_ (MTK_PIN_NO(101) | 7) - -#define MT2712_PIN_102_URTS5__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) -#define MT2712_PIN_102_URTS5__FUNC_URTS5 (MTK_PIN_NO(102) | 1) -#define MT2712_PIN_102_URTS5__FUNC_UCTS5 (MTK_PIN_NO(102) | 2) -#define MT2712_PIN_102_URTS5__FUNC_I2SO3_MCK (MTK_PIN_NO(102) | 3) -#define MT2712_PIN_102_URTS5__FUNC_TDMIN_MCLK (MTK_PIN_NO(102) | 4) -#define MT2712_PIN_102_URTS5__FUNC_IR_IN (MTK_PIN_NO(102) | 5) -#define MT2712_PIN_102_URTS5__FUNC_I2SO0_MCK (MTK_PIN_NO(102) | 6) -#define MT2712_PIN_102_URTS5__FUNC_DBG_MON_B_31_ (MTK_PIN_NO(102) | 7) - -#define MT2712_PIN_103_UTXD5__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) -#define MT2712_PIN_103_UTXD5__FUNC_UTXD5 (MTK_PIN_NO(103) | 1) -#define MT2712_PIN_103_UTXD5__FUNC_URXD5 (MTK_PIN_NO(103) | 2) -#define MT2712_PIN_103_UTXD5__FUNC_I2SO3_BCK (MTK_PIN_NO(103) | 3) -#define MT2712_PIN_103_UTXD5__FUNC_TDMIN_BCK (MTK_PIN_NO(103) | 4) -#define MT2712_PIN_103_UTXD5__FUNC_I2SO0_BCK (MTK_PIN_NO(103) | 6) -#define MT2712_PIN_103_UTXD5__FUNC_DBG_MON_B_32_ (MTK_PIN_NO(103) | 7) - -#define MT2712_PIN_104_UCTS5__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) -#define MT2712_PIN_104_UCTS5__FUNC_UCTS5 (MTK_PIN_NO(104) | 1) -#define MT2712_PIN_104_UCTS5__FUNC_URTS5 (MTK_PIN_NO(104) | 2) -#define MT2712_PIN_104_UCTS5__FUNC_I2SO0_DO1 (MTK_PIN_NO(104) | 3) -#define MT2712_PIN_104_UCTS5__FUNC_TDMIN_DI (MTK_PIN_NO(104) | 4) -#define MT2712_PIN_104_UCTS5__FUNC_IR_IN (MTK_PIN_NO(104) | 5) -#define MT2712_PIN_104_UCTS5__FUNC_I2SO0_DO0 (MTK_PIN_NO(104) | 6) - -#define MT2712_PIN_105_I2C_SDA0__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) -#define MT2712_PIN_105_I2C_SDA0__FUNC_SDA0 (MTK_PIN_NO(105) | 1) - -#define MT2712_PIN_106_I2C_SDA1__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) -#define MT2712_PIN_106_I2C_SDA1__FUNC_SDA1 (MTK_PIN_NO(106) | 1) - -#define MT2712_PIN_107_I2C_SDA2__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) -#define MT2712_PIN_107_I2C_SDA2__FUNC_SDA2 (MTK_PIN_NO(107) | 1) - -#define MT2712_PIN_108_I2C_SDA3__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) -#define MT2712_PIN_108_I2C_SDA3__FUNC_SDA3 (MTK_PIN_NO(108) | 1) - -#define MT2712_PIN_109_I2C_SDA4__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) -#define MT2712_PIN_109_I2C_SDA4__FUNC_SDA4 (MTK_PIN_NO(109) | 1) - -#define MT2712_PIN_110_I2C_SDA5__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) -#define MT2712_PIN_110_I2C_SDA5__FUNC_SDA5 (MTK_PIN_NO(110) | 1) - -#define MT2712_PIN_111_I2C_SCL0__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) -#define MT2712_PIN_111_I2C_SCL0__FUNC_SCL0 (MTK_PIN_NO(111) | 1) - -#define MT2712_PIN_112_I2C_SCL1__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) -#define MT2712_PIN_112_I2C_SCL1__FUNC_SCL1 (MTK_PIN_NO(112) | 1) - -#define MT2712_PIN_113_I2C_SCL2__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) -#define MT2712_PIN_113_I2C_SCL2__FUNC_SCL2 (MTK_PIN_NO(113) | 1) - -#define MT2712_PIN_114_I2C_SCL3__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) -#define MT2712_PIN_114_I2C_SCL3__FUNC_SCL3 (MTK_PIN_NO(114) | 1) - -#define MT2712_PIN_115_I2C_SCL4__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) -#define MT2712_PIN_115_I2C_SCL4__FUNC_SCL4 (MTK_PIN_NO(115) | 1) - -#define MT2712_PIN_116_I2C_SCL5__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) -#define MT2712_PIN_116_I2C_SCL5__FUNC_SCL5 (MTK_PIN_NO(116) | 1) - -#define MT2712_PIN_117_URXD0__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) -#define MT2712_PIN_117_URXD0__FUNC_URXD0 (MTK_PIN_NO(117) | 1) -#define MT2712_PIN_117_URXD0__FUNC_UTXD0 (MTK_PIN_NO(117) | 2) - -#define MT2712_PIN_118_URXD1__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) -#define MT2712_PIN_118_URXD1__FUNC_URXD1 (MTK_PIN_NO(118) | 1) -#define MT2712_PIN_118_URXD1__FUNC_UTXD1 (MTK_PIN_NO(118) | 2) - -#define MT2712_PIN_119_URXD2__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) -#define MT2712_PIN_119_URXD2__FUNC_URXD2 (MTK_PIN_NO(119) | 1) -#define MT2712_PIN_119_URXD2__FUNC_UTXD2 (MTK_PIN_NO(119) | 2) - -#define MT2712_PIN_120_UTXD0__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) -#define MT2712_PIN_120_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(120) | 1) -#define MT2712_PIN_120_UTXD0__FUNC_URXD0 (MTK_PIN_NO(120) | 2) - -#define MT2712_PIN_121_UTXD1__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) -#define MT2712_PIN_121_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(121) | 1) -#define MT2712_PIN_121_UTXD1__FUNC_URXD1 (MTK_PIN_NO(121) | 2) - -#define MT2712_PIN_122_UTXD2__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) -#define MT2712_PIN_122_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(122) | 1) -#define MT2712_PIN_122_UTXD2__FUNC_URXD2 (MTK_PIN_NO(122) | 2) - -#define MT2712_PIN_123_URXD3__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) -#define MT2712_PIN_123_URXD3__FUNC_URXD3 (MTK_PIN_NO(123) | 1) -#define MT2712_PIN_123_URXD3__FUNC_UTXD3 (MTK_PIN_NO(123) | 2) -#define MT2712_PIN_123_URXD3__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(123) | 3) - -#define MT2712_PIN_124_UTXD3__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) -#define MT2712_PIN_124_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(124) | 1) -#define MT2712_PIN_124_UTXD3__FUNC_URXD3 (MTK_PIN_NO(124) | 2) -#define MT2712_PIN_124_UTXD3__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(124) | 3) - -#define MT2712_PIN_125_URTS3__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) -#define MT2712_PIN_125_URTS3__FUNC_URTS3 (MTK_PIN_NO(125) | 1) -#define MT2712_PIN_125_URTS3__FUNC_UCTS3 (MTK_PIN_NO(125) | 2) -#define MT2712_PIN_125_URTS3__FUNC_WATCH_DOG (MTK_PIN_NO(125) | 3) - -#define MT2712_PIN_126_UCTS3__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) -#define MT2712_PIN_126_UCTS3__FUNC_UCTS3 (MTK_PIN_NO(126) | 1) -#define MT2712_PIN_126_UCTS3__FUNC_URTS3 (MTK_PIN_NO(126) | 2) -#define MT2712_PIN_126_UCTS3__FUNC_SRCLKENA0 (MTK_PIN_NO(126) | 3) - -#define MT2712_PIN_127_SPI2_CSN__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) -#define MT2712_PIN_127_SPI2_CSN__FUNC_SPI_CS_2_ (MTK_PIN_NO(127) | 1) -#define MT2712_PIN_127_SPI2_CSN__FUNC_SPI_CS_1_ (MTK_PIN_NO(127) | 2) - -#define MT2712_PIN_128_SPI2_MO__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) -#define MT2712_PIN_128_SPI2_MO__FUNC_SPI_MO_2_ (MTK_PIN_NO(128) | 1) -#define MT2712_PIN_128_SPI2_MO__FUNC_SPI_SO_1_ (MTK_PIN_NO(128) | 2) - -#define MT2712_PIN_129_SPI2_MI__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) -#define MT2712_PIN_129_SPI2_MI__FUNC_SPI_MI_2_ (MTK_PIN_NO(129) | 1) -#define MT2712_PIN_129_SPI2_MI__FUNC_SPI_SI_1_ (MTK_PIN_NO(129) | 2) - -#define MT2712_PIN_130_SPI2_CK__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) -#define MT2712_PIN_130_SPI2_CK__FUNC_SPI_CK_2_ (MTK_PIN_NO(130) | 1) -#define MT2712_PIN_130_SPI2_CK__FUNC_SPI_CK_1_ (MTK_PIN_NO(130) | 2) - -#define MT2712_PIN_131_SPI3_CSN__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) -#define MT2712_PIN_131_SPI3_CSN__FUNC_SPI_CS_3_ (MTK_PIN_NO(131) | 1) - -#define MT2712_PIN_132_SPI3_MO__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) -#define MT2712_PIN_132_SPI3_MO__FUNC_SPI_MO_3_ (MTK_PIN_NO(132) | 1) - -#define MT2712_PIN_133_SPI3_MI__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) -#define MT2712_PIN_133_SPI3_MI__FUNC_SPI_MI_3_ (MTK_PIN_NO(133) | 1) - -#define MT2712_PIN_134_SPI3_CK__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) -#define MT2712_PIN_134_SPI3_CK__FUNC_SPI_CK_3_ (MTK_PIN_NO(134) | 1) - -#define MT2712_PIN_135_KPROW3__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) -#define MT2712_PIN_135_KPROW3__FUNC_KROW3 (MTK_PIN_NO(135) | 1) -#define MT2712_PIN_135_KPROW3__FUNC_DSIC_TE (MTK_PIN_NO(135) | 2) - -#define MT2712_PIN_136_KPROW4__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) -#define MT2712_PIN_136_KPROW4__FUNC_KROW4 (MTK_PIN_NO(136) | 1) -#define MT2712_PIN_136_KPROW4__FUNC_DSID_TE (MTK_PIN_NO(136) | 2) - -#define MT2712_PIN_137_KPCOL3__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) -#define MT2712_PIN_137_KPCOL3__FUNC_KCOL3 (MTK_PIN_NO(137) | 1) -#define MT2712_PIN_137_KPCOL3__FUNC_DISP2_PWM (MTK_PIN_NO(137) | 2) - -#define MT2712_PIN_138_KPCOL4__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) -#define MT2712_PIN_138_KPCOL4__FUNC_KCOL4 (MTK_PIN_NO(138) | 1) -#define MT2712_PIN_138_KPCOL4__FUNC_LCM_RST2 (MTK_PIN_NO(138) | 2) - -#define MT2712_PIN_139_KPCOL5__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) -#define MT2712_PIN_139_KPCOL5__FUNC_KCOL5 (MTK_PIN_NO(139) | 1) -#define MT2712_PIN_139_KPCOL5__FUNC_DSIA_TE (MTK_PIN_NO(139) | 3) -#define MT2712_PIN_139_KPCOL5__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(139) | 4) - -#define MT2712_PIN_140_KPCOL6__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) -#define MT2712_PIN_140_KPCOL6__FUNC_KCOL6 (MTK_PIN_NO(140) | 1) -#define MT2712_PIN_140_KPCOL6__FUNC_WATCH_DOG (MTK_PIN_NO(140) | 2) -#define MT2712_PIN_140_KPCOL6__FUNC_LCM_RST1 (MTK_PIN_NO(140) | 3) - -#define MT2712_PIN_141_KPROW5__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) -#define MT2712_PIN_141_KPROW5__FUNC_KROW5 (MTK_PIN_NO(141) | 1) -#define MT2712_PIN_141_KPROW5__FUNC_LCM_RST0 (MTK_PIN_NO(141) | 3) -#define MT2712_PIN_141_KPROW5__FUNC_PURE_HW_PROTECT (MTK_PIN_NO(141) | 4) - -#define MT2712_PIN_142_KPROW6__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) -#define MT2712_PIN_142_KPROW6__FUNC_KROW6 (MTK_PIN_NO(142) | 1) -#define MT2712_PIN_142_KPROW6__FUNC_SRCLKENA0 (MTK_PIN_NO(142) | 2) -#define MT2712_PIN_142_KPROW6__FUNC_DSIB_TE (MTK_PIN_NO(142) | 3) - -#define MT2712_PIN_143_JTDO_ICE__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) -#define MT2712_PIN_143_JTDO_ICE__FUNC_JTDO_ICE (MTK_PIN_NO(143) | 1) -#define MT2712_PIN_143_JTDO_ICE__FUNC_DFD_TDO (MTK_PIN_NO(143) | 3) - -#define MT2712_PIN_144_JTCK_ICE__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) -#define MT2712_PIN_144_JTCK_ICE__FUNC_JTCK_ICE (MTK_PIN_NO(144) | 1) -#define MT2712_PIN_144_JTCK_ICE__FUNC_DFD_TCK (MTK_PIN_NO(144) | 3) - -#define MT2712_PIN_145_JTDI_ICE__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) -#define MT2712_PIN_145_JTDI_ICE__FUNC_JTDI_ICE (MTK_PIN_NO(145) | 1) -#define MT2712_PIN_145_JTDI_ICE__FUNC_DFD_TDI (MTK_PIN_NO(145) | 3) - -#define MT2712_PIN_146_JTMS_ICE__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) -#define MT2712_PIN_146_JTMS_ICE__FUNC_JTMS_ICE (MTK_PIN_NO(146) | 1) -#define MT2712_PIN_146_JTMS_ICE__FUNC_DFD_TMS (MTK_PIN_NO(146) | 3) - -#define MT2712_PIN_147_JTRSTB_ICE__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) -#define MT2712_PIN_147_JTRSTB_ICE__FUNC_JTRST_B_ICE (MTK_PIN_NO(147) | 1) -#define MT2712_PIN_147_JTRSTB_ICE__FUNC_DFD_NTRST (MTK_PIN_NO(147) | 3) - -#define MT2712_PIN_148_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) -#define MT2712_PIN_148_GPIO148__FUNC_JTRSTB_CM4 (MTK_PIN_NO(148) | 1) -#define MT2712_PIN_148_GPIO148__FUNC_DFD_NTRST (MTK_PIN_NO(148) | 3) - -#define MT2712_PIN_149_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) -#define MT2712_PIN_149_GPIO149__FUNC_JTCK_CM4 (MTK_PIN_NO(149) | 1) -#define MT2712_PIN_149_GPIO149__FUNC_DFD_TCK (MTK_PIN_NO(149) | 3) - -#define MT2712_PIN_150_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) -#define MT2712_PIN_150_GPIO150__FUNC_JTMS_CM4 (MTK_PIN_NO(150) | 1) -#define MT2712_PIN_150_GPIO150__FUNC_DFD_TMS (MTK_PIN_NO(150) | 3) - -#define MT2712_PIN_151_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) -#define MT2712_PIN_151_GPIO151__FUNC_JTDI_CM4 (MTK_PIN_NO(151) | 1) -#define MT2712_PIN_151_GPIO151__FUNC_DFD_TDI (MTK_PIN_NO(151) | 3) - -#define MT2712_PIN_152_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) -#define MT2712_PIN_152_GPIO152__FUNC_JTDO_CM4 (MTK_PIN_NO(152) | 1) -#define MT2712_PIN_152_GPIO152__FUNC_DFD_TDO (MTK_PIN_NO(152) | 3) - -#define MT2712_PIN_153_SPI0_CSN__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) -#define MT2712_PIN_153_SPI0_CSN__FUNC_SPI_CS_0_ (MTK_PIN_NO(153) | 1) -#define MT2712_PIN_153_SPI0_CSN__FUNC_SRCLKENA0 (MTK_PIN_NO(153) | 2) -#define MT2712_PIN_153_SPI0_CSN__FUNC_UTXD0 (MTK_PIN_NO(153) | 3) -#define MT2712_PIN_153_SPI0_CSN__FUNC_I2SO0_DO1 (MTK_PIN_NO(153) | 4) -#define MT2712_PIN_153_SPI0_CSN__FUNC_TDMO0_DATA1 (MTK_PIN_NO(153) | 6) -#define MT2712_PIN_153_SPI0_CSN__FUNC_I2S_IQ2_SDQB (MTK_PIN_NO(153) | 7) - -#define MT2712_PIN_154_SPI0_MI__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) -#define MT2712_PIN_154_SPI0_MI__FUNC_SPI_MI_0_ (MTK_PIN_NO(154) | 1) -#define MT2712_PIN_154_SPI0_MI__FUNC_SRCLKENA0 (MTK_PIN_NO(154) | 2) -#define MT2712_PIN_154_SPI0_MI__FUNC_URXD0 (MTK_PIN_NO(154) | 3) -#define MT2712_PIN_154_SPI0_MI__FUNC_I2SO0_DO0 (MTK_PIN_NO(154) | 4) -#define MT2712_PIN_154_SPI0_MI__FUNC_I2SO1_DO (MTK_PIN_NO(154) | 5) -#define MT2712_PIN_154_SPI0_MI__FUNC_TDMO0_DATA (MTK_PIN_NO(154) | 6) -#define MT2712_PIN_154_SPI0_MI__FUNC_I2S_IQ1_SDIB (MTK_PIN_NO(154) | 7) - -#define MT2712_PIN_155_SPI0_CK__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) -#define MT2712_PIN_155_SPI0_CK__FUNC_SPI_CK_0_ (MTK_PIN_NO(155) | 1) -#define MT2712_PIN_155_SPI0_CK__FUNC_SC_APBIAS_OFF (MTK_PIN_NO(155) | 2) -#define MT2712_PIN_155_SPI0_CK__FUNC_UTXD1 (MTK_PIN_NO(155) | 3) -#define MT2712_PIN_155_SPI0_CK__FUNC_I2SO0_BCK (MTK_PIN_NO(155) | 4) -#define MT2712_PIN_155_SPI0_CK__FUNC_I2SO1_BCK (MTK_PIN_NO(155) | 5) -#define MT2712_PIN_155_SPI0_CK__FUNC_TDMO0_BCK (MTK_PIN_NO(155) | 6) -#define MT2712_PIN_155_SPI0_CK__FUNC_I2S_IQ0_SDQB (MTK_PIN_NO(155) | 7) - -#define MT2712_PIN_156_SPI0_MO__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) -#define MT2712_PIN_156_SPI0_MO__FUNC_SPI_MO_0_ (MTK_PIN_NO(156) | 1) -#define MT2712_PIN_156_SPI0_MO__FUNC_SC_APBIAS_OFF (MTK_PIN_NO(156) | 2) -#define MT2712_PIN_156_SPI0_MO__FUNC_URXD1 (MTK_PIN_NO(156) | 3) -#define MT2712_PIN_156_SPI0_MO__FUNC_I2SO0_WS (MTK_PIN_NO(156) | 4) -#define MT2712_PIN_156_SPI0_MO__FUNC_I2SO1_WS (MTK_PIN_NO(156) | 5) -#define MT2712_PIN_156_SPI0_MO__FUNC_TDMO0_LRCK (MTK_PIN_NO(156) | 6) -#define MT2712_PIN_156_SPI0_MO__FUNC_I2S_IQ0_SDIB (MTK_PIN_NO(156) | 7) - -#define MT2712_PIN_157_SPI5_CSN__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) -#define MT2712_PIN_157_SPI5_CSN__FUNC_SPI_CS_5_ (MTK_PIN_NO(157) | 1) -#define MT2712_PIN_157_SPI5_CSN__FUNC_LCM_RST0 (MTK_PIN_NO(157) | 2) -#define MT2712_PIN_157_SPI5_CSN__FUNC_UTXD2 (MTK_PIN_NO(157) | 3) -#define MT2712_PIN_157_SPI5_CSN__FUNC_I2SO0_MCK (MTK_PIN_NO(157) | 4) -#define MT2712_PIN_157_SPI5_CSN__FUNC_I2SO1_MCK (MTK_PIN_NO(157) | 5) -#define MT2712_PIN_157_SPI5_CSN__FUNC_TDMO0_MCLK (MTK_PIN_NO(157) | 6) - -#define MT2712_PIN_158_SPI5_MI__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) -#define MT2712_PIN_158_SPI5_MI__FUNC_SPI_MI_5_ (MTK_PIN_NO(158) | 1) -#define MT2712_PIN_158_SPI5_MI__FUNC_DSIA_TE (MTK_PIN_NO(158) | 2) -#define MT2712_PIN_158_SPI5_MI__FUNC_URXD2 (MTK_PIN_NO(158) | 3) - -#define MT2712_PIN_159_SPI5_MO__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) -#define MT2712_PIN_159_SPI5_MO__FUNC_SPI_MO_5_ (MTK_PIN_NO(159) | 1) -#define MT2712_PIN_159_SPI5_MO__FUNC_DSIB_TE (MTK_PIN_NO(159) | 2) -#define MT2712_PIN_159_SPI5_MO__FUNC_UTXD3 (MTK_PIN_NO(159) | 3) - -#define MT2712_PIN_160_SPI5_CK__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) -#define MT2712_PIN_160_SPI5_CK__FUNC_SPI_CK_5_ (MTK_PIN_NO(160) | 1) -#define MT2712_PIN_160_SPI5_CK__FUNC_LCM_RST1 (MTK_PIN_NO(160) | 2) -#define MT2712_PIN_160_SPI5_CK__FUNC_URXD3 (MTK_PIN_NO(160) | 3) - -#define MT2712_PIN_161_SPI1_CSN__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) -#define MT2712_PIN_161_SPI1_CSN__FUNC_SPI_CS_1_ (MTK_PIN_NO(161) | 1) -#define MT2712_PIN_161_SPI1_CSN__FUNC_SPI_CS_4_ (MTK_PIN_NO(161) | 2) -#define MT2712_PIN_161_SPI1_CSN__FUNC_I2S_IQ2_SDQB (MTK_PIN_NO(161) | 4) -#define MT2712_PIN_161_SPI1_CSN__FUNC_I2SO2_DO (MTK_PIN_NO(161) | 5) -#define MT2712_PIN_161_SPI1_CSN__FUNC_TDMO0_DATA1 (MTK_PIN_NO(161) | 6) -#define MT2712_PIN_161_SPI1_CSN__FUNC_I2SO0_DO1 (MTK_PIN_NO(161) | 7) - -#define MT2712_PIN_162_SPI1_SI__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) -#define MT2712_PIN_162_SPI1_SI__FUNC_SPI_SI_1_ (MTK_PIN_NO(162) | 1) -#define MT2712_PIN_162_SPI1_SI__FUNC_SPI_MI_4_ (MTK_PIN_NO(162) | 2) -#define MT2712_PIN_162_SPI1_SI__FUNC_I2S_IQ1_SDIB (MTK_PIN_NO(162) | 4) -#define MT2712_PIN_162_SPI1_SI__FUNC_I2SO2_BCK (MTK_PIN_NO(162) | 5) -#define MT2712_PIN_162_SPI1_SI__FUNC_TDMO0_DATA (MTK_PIN_NO(162) | 6) -#define MT2712_PIN_162_SPI1_SI__FUNC_I2SO0_DO0 (MTK_PIN_NO(162) | 7) - -#define MT2712_PIN_163_SPI1_CK__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) -#define MT2712_PIN_163_SPI1_CK__FUNC_SPI_CK_1_ (MTK_PIN_NO(163) | 1) -#define MT2712_PIN_163_SPI1_CK__FUNC_SPI_CK_4_ (MTK_PIN_NO(163) | 2) -#define MT2712_PIN_163_SPI1_CK__FUNC_I2S_IQ0_SDQB (MTK_PIN_NO(163) | 4) -#define MT2712_PIN_163_SPI1_CK__FUNC_I2SO2_WS (MTK_PIN_NO(163) | 5) -#define MT2712_PIN_163_SPI1_CK__FUNC_TDMO0_BCK (MTK_PIN_NO(163) | 6) -#define MT2712_PIN_163_SPI1_CK__FUNC_I2SO0_BCK (MTK_PIN_NO(163) | 7) - -#define MT2712_PIN_164_SPI1_SO__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) -#define MT2712_PIN_164_SPI1_SO__FUNC_SPI_SO_1_ (MTK_PIN_NO(164) | 1) -#define MT2712_PIN_164_SPI1_SO__FUNC_SPI_MO_4_ (MTK_PIN_NO(164) | 2) -#define MT2712_PIN_164_SPI1_SO__FUNC_I2S_IQ0_SDIB (MTK_PIN_NO(164) | 4) -#define MT2712_PIN_164_SPI1_SO__FUNC_I2SO2_MCK (MTK_PIN_NO(164) | 5) -#define MT2712_PIN_164_SPI1_SO__FUNC_TDMO0_LRCK (MTK_PIN_NO(164) | 6) -#define MT2712_PIN_164_SPI1_SO__FUNC_I2SO0_WS (MTK_PIN_NO(164) | 7) - -#define MT2712_PIN_165_SPI4_CSN__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) -#define MT2712_PIN_165_SPI4_CSN__FUNC_SPI_CS_4_ (MTK_PIN_NO(165) | 1) -#define MT2712_PIN_165_SPI4_CSN__FUNC_LCM_RST0 (MTK_PIN_NO(165) | 2) -#define MT2712_PIN_165_SPI4_CSN__FUNC_SPI_CS_1_ (MTK_PIN_NO(165) | 3) -#define MT2712_PIN_165_SPI4_CSN__FUNC_UTXD4 (MTK_PIN_NO(165) | 4) -#define MT2712_PIN_165_SPI4_CSN__FUNC_I2SO1_DO (MTK_PIN_NO(165) | 5) -#define MT2712_PIN_165_SPI4_CSN__FUNC_TDMO0_MCLK (MTK_PIN_NO(165) | 6) -#define MT2712_PIN_165_SPI4_CSN__FUNC_I2SO0_MCK (MTK_PIN_NO(165) | 7) - -#define MT2712_PIN_166_SPI4_MI__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) -#define MT2712_PIN_166_SPI4_MI__FUNC_SPI_MI_4_ (MTK_PIN_NO(166) | 1) -#define MT2712_PIN_166_SPI4_MI__FUNC_DSIA_TE (MTK_PIN_NO(166) | 2) -#define MT2712_PIN_166_SPI4_MI__FUNC_SPI_SI_1_ (MTK_PIN_NO(166) | 3) -#define MT2712_PIN_166_SPI4_MI__FUNC_URXD4 (MTK_PIN_NO(166) | 4) -#define MT2712_PIN_166_SPI4_MI__FUNC_I2SO1_BCK (MTK_PIN_NO(166) | 5) - -#define MT2712_PIN_167_SPI4_MO__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) -#define MT2712_PIN_167_SPI4_MO__FUNC_SPI_MO_4_ (MTK_PIN_NO(167) | 1) -#define MT2712_PIN_167_SPI4_MO__FUNC_DSIB_TE (MTK_PIN_NO(167) | 2) -#define MT2712_PIN_167_SPI4_MO__FUNC_SPI_SO_1_ (MTK_PIN_NO(167) | 3) -#define MT2712_PIN_167_SPI4_MO__FUNC_UTXD5 (MTK_PIN_NO(167) | 4) -#define MT2712_PIN_167_SPI4_MO__FUNC_I2SO1_WS (MTK_PIN_NO(167) | 5) - -#define MT2712_PIN_168_SPI4_CK__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) -#define MT2712_PIN_168_SPI4_CK__FUNC_SPI_CK_4_ (MTK_PIN_NO(168) | 1) -#define MT2712_PIN_168_SPI4_CK__FUNC_LCM_RST1 (MTK_PIN_NO(168) | 2) -#define MT2712_PIN_168_SPI4_CK__FUNC_SPI_CK_1_ (MTK_PIN_NO(168) | 3) -#define MT2712_PIN_168_SPI4_CK__FUNC_URXD5 (MTK_PIN_NO(168) | 4) -#define MT2712_PIN_168_SPI4_CK__FUNC_I2SO1_MCK (MTK_PIN_NO(168) | 5) - -#define MT2712_PIN_169_I2SI0_DATA__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) -#define MT2712_PIN_169_I2SI0_DATA__FUNC_I2SI0_DI (MTK_PIN_NO(169) | 1) -#define MT2712_PIN_169_I2SI0_DATA__FUNC_I2SI1_DI (MTK_PIN_NO(169) | 2) -#define MT2712_PIN_169_I2SI0_DATA__FUNC_I2SI2_DI (MTK_PIN_NO(169) | 3) -#define MT2712_PIN_169_I2SI0_DATA__FUNC_TDMIN_DI (MTK_PIN_NO(169) | 4) - -#define MT2712_PIN_170_I2SI0_LRCK__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) -#define MT2712_PIN_170_I2SI0_LRCK__FUNC_I2SI0_WS (MTK_PIN_NO(170) | 1) -#define MT2712_PIN_170_I2SI0_LRCK__FUNC_I2SI1_WS (MTK_PIN_NO(170) | 2) -#define MT2712_PIN_170_I2SI0_LRCK__FUNC_I2SI2_WS (MTK_PIN_NO(170) | 3) -#define MT2712_PIN_170_I2SI0_LRCK__FUNC_TDMIN_LRCK (MTK_PIN_NO(170) | 4) -#define MT2712_PIN_170_I2SI0_LRCK__FUNC_TDMO0_DATA3 (MTK_PIN_NO(170) | 5) -#define MT2712_PIN_170_I2SI0_LRCK__FUNC_TDMO1_DATA3 (MTK_PIN_NO(170) | 6) - -#define MT2712_PIN_171_I2SI0_MCLK__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) -#define MT2712_PIN_171_I2SI0_MCLK__FUNC_I2SI0_MCK (MTK_PIN_NO(171) | 1) -#define MT2712_PIN_171_I2SI0_MCLK__FUNC_I2SI1_MCK (MTK_PIN_NO(171) | 2) -#define MT2712_PIN_171_I2SI0_MCLK__FUNC_I2SI2_MCK (MTK_PIN_NO(171) | 3) -#define MT2712_PIN_171_I2SI0_MCLK__FUNC_TDMIN_MCLK (MTK_PIN_NO(171) | 4) -#define MT2712_PIN_171_I2SI0_MCLK__FUNC_TDMO0_DATA2 (MTK_PIN_NO(171) | 5) -#define MT2712_PIN_171_I2SI0_MCLK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(171) | 6) - -#define MT2712_PIN_172_I2SI0_BCK__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) -#define MT2712_PIN_172_I2SI0_BCK__FUNC_I2SI0_BCK (MTK_PIN_NO(172) | 1) -#define MT2712_PIN_172_I2SI0_BCK__FUNC_I2SI1_BCK (MTK_PIN_NO(172) | 2) -#define MT2712_PIN_172_I2SI0_BCK__FUNC_I2SI2_BCK (MTK_PIN_NO(172) | 3) -#define MT2712_PIN_172_I2SI0_BCK__FUNC_TDMIN_BCK (MTK_PIN_NO(172) | 4) -#define MT2712_PIN_172_I2SI0_BCK__FUNC_TDMO0_DATA1 (MTK_PIN_NO(172) | 5) -#define MT2712_PIN_172_I2SI0_BCK__FUNC_TDMO1_DATA1 (MTK_PIN_NO(172) | 6) - -#define MT2712_PIN_173_I2SI2_DATA__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) -#define MT2712_PIN_173_I2SI2_DATA__FUNC_I2SI2_DI (MTK_PIN_NO(173) | 1) -#define MT2712_PIN_173_I2SI2_DATA__FUNC_I2SI0_DI (MTK_PIN_NO(173) | 2) -#define MT2712_PIN_173_I2SI2_DATA__FUNC_I2SI1_DI (MTK_PIN_NO(173) | 3) -#define MT2712_PIN_173_I2SI2_DATA__FUNC_PCM1_DI (MTK_PIN_NO(173) | 4) -#define MT2712_PIN_173_I2SI2_DATA__FUNC_TDMIN_DI (MTK_PIN_NO(173) | 5) -#define MT2712_PIN_173_I2SI2_DATA__FUNC_PCM1_DO (MTK_PIN_NO(173) | 6) - -#define MT2712_PIN_174_I2SI2_MCLK__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) -#define MT2712_PIN_174_I2SI2_MCLK__FUNC_I2SI2_MCK (MTK_PIN_NO(174) | 1) -#define MT2712_PIN_174_I2SI2_MCLK__FUNC_I2SI0_MCK (MTK_PIN_NO(174) | 2) -#define MT2712_PIN_174_I2SI2_MCLK__FUNC_I2SI1_MCK (MTK_PIN_NO(174) | 3) -#define MT2712_PIN_174_I2SI2_MCLK__FUNC_PCM1_DO (MTK_PIN_NO(174) | 4) -#define MT2712_PIN_174_I2SI2_MCLK__FUNC_TDMIN_MCLK (MTK_PIN_NO(174) | 5) -#define MT2712_PIN_174_I2SI2_MCLK__FUNC_PCM1_DI (MTK_PIN_NO(174) | 6) -#define MT2712_PIN_174_I2SI2_MCLK__FUNC_I2S_IQ2_SDQB (MTK_PIN_NO(174) | 7) - -#define MT2712_PIN_175_I2SI2_BCK__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) -#define MT2712_PIN_175_I2SI2_BCK__FUNC_I2SI2_BCK (MTK_PIN_NO(175) | 1) -#define MT2712_PIN_175_I2SI2_BCK__FUNC_I2SI0_BCK (MTK_PIN_NO(175) | 2) -#define MT2712_PIN_175_I2SI2_BCK__FUNC_I2SI1_BCK (MTK_PIN_NO(175) | 3) -#define MT2712_PIN_175_I2SI2_BCK__FUNC_PCM1_CLK (MTK_PIN_NO(175) | 4) -#define MT2712_PIN_175_I2SI2_BCK__FUNC_TDMIN_BCK (MTK_PIN_NO(175) | 5) - -#define MT2712_PIN_176_I2SI2_LRCK__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) -#define MT2712_PIN_176_I2SI2_LRCK__FUNC_I2SI2_WS (MTK_PIN_NO(176) | 1) -#define MT2712_PIN_176_I2SI2_LRCK__FUNC_I2SI0_WS (MTK_PIN_NO(176) | 2) -#define MT2712_PIN_176_I2SI2_LRCK__FUNC_I2SI1_WS (MTK_PIN_NO(176) | 3) -#define MT2712_PIN_176_I2SI2_LRCK__FUNC_PCM1_SYNC (MTK_PIN_NO(176) | 4) -#define MT2712_PIN_176_I2SI2_LRCK__FUNC_TDMIN_LRCK (MTK_PIN_NO(176) | 5) - -#define MT2712_PIN_177_I2SI1_DATA__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) -#define MT2712_PIN_177_I2SI1_DATA__FUNC_I2SI1_DI (MTK_PIN_NO(177) | 1) -#define MT2712_PIN_177_I2SI1_DATA__FUNC_I2SI0_DI (MTK_PIN_NO(177) | 2) -#define MT2712_PIN_177_I2SI1_DATA__FUNC_I2SI2_DI (MTK_PIN_NO(177) | 3) -#define MT2712_PIN_177_I2SI1_DATA__FUNC_TDMIN_DI (MTK_PIN_NO(177) | 4) - -#define MT2712_PIN_178_I2SI1_BCK__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) -#define MT2712_PIN_178_I2SI1_BCK__FUNC_I2SI1_BCK (MTK_PIN_NO(178) | 1) -#define MT2712_PIN_178_I2SI1_BCK__FUNC_I2SI0_BCK (MTK_PIN_NO(178) | 2) -#define MT2712_PIN_178_I2SI1_BCK__FUNC_I2SI2_BCK (MTK_PIN_NO(178) | 3) -#define MT2712_PIN_178_I2SI1_BCK__FUNC_TDMIN_BCK (MTK_PIN_NO(178) | 4) -#define MT2712_PIN_178_I2SI1_BCK__FUNC_TDMO0_DATA3 (MTK_PIN_NO(178) | 5) -#define MT2712_PIN_178_I2SI1_BCK__FUNC_TDMO1_DATA3 (MTK_PIN_NO(178) | 6) - -#define MT2712_PIN_179_I2SI1_LRCK__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) -#define MT2712_PIN_179_I2SI1_LRCK__FUNC_I2SI1_WS (MTK_PIN_NO(179) | 1) -#define MT2712_PIN_179_I2SI1_LRCK__FUNC_I2SI0_WS (MTK_PIN_NO(179) | 2) -#define MT2712_PIN_179_I2SI1_LRCK__FUNC_I2SI2_WS (MTK_PIN_NO(179) | 3) -#define MT2712_PIN_179_I2SI1_LRCK__FUNC_TDMIN_LRCK (MTK_PIN_NO(179) | 4) -#define MT2712_PIN_179_I2SI1_LRCK__FUNC_TDMO0_DATA2 (MTK_PIN_NO(179) | 5) -#define MT2712_PIN_179_I2SI1_LRCK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(179) | 6) - -#define MT2712_PIN_180_I2SI1_MCLK__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) -#define MT2712_PIN_180_I2SI1_MCLK__FUNC_I2SI1_MCK (MTK_PIN_NO(180) | 1) -#define MT2712_PIN_180_I2SI1_MCLK__FUNC_I2SI0_MCK (MTK_PIN_NO(180) | 2) -#define MT2712_PIN_180_I2SI1_MCLK__FUNC_I2SI2_MCK (MTK_PIN_NO(180) | 3) -#define MT2712_PIN_180_I2SI1_MCLK__FUNC_TDMIN_MCLK (MTK_PIN_NO(180) | 4) -#define MT2712_PIN_180_I2SI1_MCLK__FUNC_TDMO0_DATA1 (MTK_PIN_NO(180) | 5) -#define MT2712_PIN_180_I2SI1_MCLK__FUNC_TDMO1_DATA1 (MTK_PIN_NO(180) | 6) -#define MT2712_PIN_180_I2SI1_MCLK__FUNC_I2S_IQ2_SDIB (MTK_PIN_NO(180) | 7) - -#define MT2712_PIN_181_I2SO1_DATA0__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) -#define MT2712_PIN_181_I2SO1_DATA0__FUNC_I2SO1_DO (MTK_PIN_NO(181) | 1) -#define MT2712_PIN_181_I2SO1_DATA0__FUNC_I2SO0_DO0 (MTK_PIN_NO(181) | 2) -#define MT2712_PIN_181_I2SO1_DATA0__FUNC_I2SO2_DO (MTK_PIN_NO(181) | 3) -#define MT2712_PIN_181_I2SO1_DATA0__FUNC_DAI_TX (MTK_PIN_NO(181) | 4) -#define MT2712_PIN_181_I2SO1_DATA0__FUNC_TDMIN_MCLK (MTK_PIN_NO(181) | 5) -#define MT2712_PIN_181_I2SO1_DATA0__FUNC_I2S_IQ2_SDIA (MTK_PIN_NO(181) | 7) - -#define MT2712_PIN_182_I2SO1_BCK__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) -#define MT2712_PIN_182_I2SO1_BCK__FUNC_I2SO1_BCK (MTK_PIN_NO(182) | 1) -#define MT2712_PIN_182_I2SO1_BCK__FUNC_I2SO0_BCK (MTK_PIN_NO(182) | 2) -#define MT2712_PIN_182_I2SO1_BCK__FUNC_I2SO2_BCK (MTK_PIN_NO(182) | 3) -#define MT2712_PIN_182_I2SO1_BCK__FUNC_DAI_SYNC (MTK_PIN_NO(182) | 4) -#define MT2712_PIN_182_I2SO1_BCK__FUNC_TDMIN_BCK (MTK_PIN_NO(182) | 5) -#define MT2712_PIN_182_I2SO1_BCK__FUNC_TDMO0_DATA3 (MTK_PIN_NO(182) | 6) -#define MT2712_PIN_182_I2SO1_BCK__FUNC_I2S_IQ2_BCK (MTK_PIN_NO(182) | 7) - -#define MT2712_PIN_183_I2SO1_LRCK__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) -#define MT2712_PIN_183_I2SO1_LRCK__FUNC_I2SO1_WS (MTK_PIN_NO(183) | 1) -#define MT2712_PIN_183_I2SO1_LRCK__FUNC_I2SO0_WS (MTK_PIN_NO(183) | 2) -#define MT2712_PIN_183_I2SO1_LRCK__FUNC_I2SO2_WS (MTK_PIN_NO(183) | 3) -#define MT2712_PIN_183_I2SO1_LRCK__FUNC_DAI_CLK (MTK_PIN_NO(183) | 4) -#define MT2712_PIN_183_I2SO1_LRCK__FUNC_TDMIN_DI (MTK_PIN_NO(183) | 5) -#define MT2712_PIN_183_I2SO1_LRCK__FUNC_TDMO0_DATA2 (MTK_PIN_NO(183) | 6) -#define MT2712_PIN_183_I2SO1_LRCK__FUNC_I2S_IQ2_WS (MTK_PIN_NO(183) | 7) - -#define MT2712_PIN_184_I2SO1_MCLK__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) -#define MT2712_PIN_184_I2SO1_MCLK__FUNC_I2SO1_MCK (MTK_PIN_NO(184) | 1) -#define MT2712_PIN_184_I2SO1_MCLK__FUNC_I2SO0_MCK (MTK_PIN_NO(184) | 2) -#define MT2712_PIN_184_I2SO1_MCLK__FUNC_I2SO2_MCK (MTK_PIN_NO(184) | 3) -#define MT2712_PIN_184_I2SO1_MCLK__FUNC_DAI_RX (MTK_PIN_NO(184) | 4) -#define MT2712_PIN_184_I2SO1_MCLK__FUNC_TDMIN_LRCK (MTK_PIN_NO(184) | 5) -#define MT2712_PIN_184_I2SO1_MCLK__FUNC_TDMO0_DATA1 (MTK_PIN_NO(184) | 6) -#define MT2712_PIN_184_I2SO1_MCLK__FUNC_I2S_IQ2_SDQA (MTK_PIN_NO(184) | 7) - -#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) -#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(185) | 1) -#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(185) | 2) -#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_I2SO1_DO (MTK_PIN_NO(185) | 3) -#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_I2SI2_DI (MTK_PIN_NO(185) | 4) -#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_MRG_RX (MTK_PIN_NO(185) | 5) -#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_PCM1_DI (MTK_PIN_NO(185) | 6) -#define MT2712_PIN_185_AUD_EXT_CK2__FUNC_I2S_IQ0_SDQB (MTK_PIN_NO(185) | 7) - -#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) -#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(186) | 1) -#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(186) | 2) -#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_I2SO0_DO1 (MTK_PIN_NO(186) | 3) -#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_I2SI1_DI (MTK_PIN_NO(186) | 4) -#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_MRG_TX (MTK_PIN_NO(186) | 5) -#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_PCM1_DO (MTK_PIN_NO(186) | 6) -#define MT2712_PIN_186_AUD_EXT_CK1__FUNC_I2S_IQ0_SDIB (MTK_PIN_NO(186) | 7) - -#define MT2712_PIN_187_I2SO2_BCK__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) -#define MT2712_PIN_187_I2SO2_BCK__FUNC_I2SO2_BCK (MTK_PIN_NO(187) | 1) -#define MT2712_PIN_187_I2SO2_BCK__FUNC_I2SO0_BCK (MTK_PIN_NO(187) | 2) -#define MT2712_PIN_187_I2SO2_BCK__FUNC_I2SO1_BCK (MTK_PIN_NO(187) | 3) -#define MT2712_PIN_187_I2SO2_BCK__FUNC_PCM1_CLK (MTK_PIN_NO(187) | 4) -#define MT2712_PIN_187_I2SO2_BCK__FUNC_MRG_SYNC (MTK_PIN_NO(187) | 5) -#define MT2712_PIN_187_I2SO2_BCK__FUNC_TDMO1_DATA3 (MTK_PIN_NO(187) | 6) -#define MT2712_PIN_187_I2SO2_BCK__FUNC_I2S_IQ0_BCK (MTK_PIN_NO(187) | 7) - -#define MT2712_PIN_188_I2SO2_LRCK__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) -#define MT2712_PIN_188_I2SO2_LRCK__FUNC_I2SO2_WS (MTK_PIN_NO(188) | 1) -#define MT2712_PIN_188_I2SO2_LRCK__FUNC_I2SO0_WS (MTK_PIN_NO(188) | 2) -#define MT2712_PIN_188_I2SO2_LRCK__FUNC_I2SO1_WS (MTK_PIN_NO(188) | 3) -#define MT2712_PIN_188_I2SO2_LRCK__FUNC_PCM1_SYNC (MTK_PIN_NO(188) | 4) -#define MT2712_PIN_188_I2SO2_LRCK__FUNC_MRG_CLK (MTK_PIN_NO(188) | 5) -#define MT2712_PIN_188_I2SO2_LRCK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(188) | 6) -#define MT2712_PIN_188_I2SO2_LRCK__FUNC_I2S_IQ0_WS (MTK_PIN_NO(188) | 7) - -#define MT2712_PIN_189_I2SO2_MCLK__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) -#define MT2712_PIN_189_I2SO2_MCLK__FUNC_I2SO2_MCK (MTK_PIN_NO(189) | 1) -#define MT2712_PIN_189_I2SO2_MCLK__FUNC_I2SO0_MCK (MTK_PIN_NO(189) | 2) -#define MT2712_PIN_189_I2SO2_MCLK__FUNC_I2SO1_MCK (MTK_PIN_NO(189) | 3) -#define MT2712_PIN_189_I2SO2_MCLK__FUNC_PCM1_DO (MTK_PIN_NO(189) | 4) -#define MT2712_PIN_189_I2SO2_MCLK__FUNC_MRG_RX (MTK_PIN_NO(189) | 5) -#define MT2712_PIN_189_I2SO2_MCLK__FUNC_TDMO1_DATA1 (MTK_PIN_NO(189) | 6) -#define MT2712_PIN_189_I2SO2_MCLK__FUNC_I2S_IQ0_SDQA (MTK_PIN_NO(189) | 7) - -#define MT2712_PIN_190_I2SO2_DATA0__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) -#define MT2712_PIN_190_I2SO2_DATA0__FUNC_I2SO2_DO (MTK_PIN_NO(190) | 1) -#define MT2712_PIN_190_I2SO2_DATA0__FUNC_I2SO0_DO0 (MTK_PIN_NO(190) | 2) -#define MT2712_PIN_190_I2SO2_DATA0__FUNC_I2SO1_DO (MTK_PIN_NO(190) | 3) -#define MT2712_PIN_190_I2SO2_DATA0__FUNC_PCM1_DI (MTK_PIN_NO(190) | 4) -#define MT2712_PIN_190_I2SO2_DATA0__FUNC_MRG_TX (MTK_PIN_NO(190) | 5) -#define MT2712_PIN_190_I2SO2_DATA0__FUNC_PCM1_DO (MTK_PIN_NO(190) | 6) -#define MT2712_PIN_190_I2SO2_DATA0__FUNC_I2S_IQ0_SDIA (MTK_PIN_NO(190) | 7) - -#define MT2712_PIN_191_I2SO0_DATA1__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) -#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2SO0_DO1 (MTK_PIN_NO(191) | 1) -#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2SI0_DI (MTK_PIN_NO(191) | 2) -#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2SI1_DI (MTK_PIN_NO(191) | 3) -#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2SI2_DI (MTK_PIN_NO(191) | 4) -#define MT2712_PIN_191_I2SO0_DATA1__FUNC_DAI_TX (MTK_PIN_NO(191) | 5) -#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2S_IQ0_SDQB (MTK_PIN_NO(191) | 6) -#define MT2712_PIN_191_I2SO0_DATA1__FUNC_I2S_IQ1_SDQB (MTK_PIN_NO(191) | 7) - -#define MT2712_PIN_192_I2SO0_MCLK__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) -#define MT2712_PIN_192_I2SO0_MCLK__FUNC_I2SO0_MCK (MTK_PIN_NO(192) | 1) -#define MT2712_PIN_192_I2SO0_MCLK__FUNC_I2SO1_MCK (MTK_PIN_NO(192) | 2) -#define MT2712_PIN_192_I2SO0_MCLK__FUNC_I2SO2_MCK (MTK_PIN_NO(192) | 3) -#define MT2712_PIN_192_I2SO0_MCLK__FUNC_USB4_FT_SCL (MTK_PIN_NO(192) | 4) -#define MT2712_PIN_192_I2SO0_MCLK__FUNC_TDMO1_DATA3 (MTK_PIN_NO(192) | 5) -#define MT2712_PIN_192_I2SO0_MCLK__FUNC_I2S_IQ0_SDIB (MTK_PIN_NO(192) | 6) -#define MT2712_PIN_192_I2SO0_MCLK__FUNC_I2S_IQ1_SDQA (MTK_PIN_NO(192) | 7) - -#define MT2712_PIN_193_I2SO0_DATA0__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) -#define MT2712_PIN_193_I2SO0_DATA0__FUNC_I2SO0_DO0 (MTK_PIN_NO(193) | 1) -#define MT2712_PIN_193_I2SO0_DATA0__FUNC_I2SO1_DO (MTK_PIN_NO(193) | 2) -#define MT2712_PIN_193_I2SO0_DATA0__FUNC_I2SO2_DO (MTK_PIN_NO(193) | 3) -#define MT2712_PIN_193_I2SO0_DATA0__FUNC_USB4_FT_SDA (MTK_PIN_NO(193) | 4) -#define MT2712_PIN_193_I2SO0_DATA0__FUNC_I2S_IQ1_SDIA (MTK_PIN_NO(193) | 7) - -#define MT2712_PIN_194_I2SO0_LRCK__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) -#define MT2712_PIN_194_I2SO0_LRCK__FUNC_I2SO0_WS (MTK_PIN_NO(194) | 1) -#define MT2712_PIN_194_I2SO0_LRCK__FUNC_I2SO1_WS (MTK_PIN_NO(194) | 2) -#define MT2712_PIN_194_I2SO0_LRCK__FUNC_I2SO2_WS (MTK_PIN_NO(194) | 3) -#define MT2712_PIN_194_I2SO0_LRCK__FUNC_USB5_FT_SCL (MTK_PIN_NO(194) | 4) -#define MT2712_PIN_194_I2SO0_LRCK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(194) | 5) -#define MT2712_PIN_194_I2SO0_LRCK__FUNC_I2S_IQ1_WS (MTK_PIN_NO(194) | 7) - -#define MT2712_PIN_195_I2SO0_BCK__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) -#define MT2712_PIN_195_I2SO0_BCK__FUNC_I2SO0_BCK (MTK_PIN_NO(195) | 1) -#define MT2712_PIN_195_I2SO0_BCK__FUNC_I2SO1_BCK (MTK_PIN_NO(195) | 2) -#define MT2712_PIN_195_I2SO0_BCK__FUNC_I2SO2_BCK (MTK_PIN_NO(195) | 3) -#define MT2712_PIN_195_I2SO0_BCK__FUNC_USB5_FT_SDA (MTK_PIN_NO(195) | 4) -#define MT2712_PIN_195_I2SO0_BCK__FUNC_TDMO1_DATA1 (MTK_PIN_NO(195) | 5) -#define MT2712_PIN_195_I2SO0_BCK__FUNC_I2S_IQ1_BCK (MTK_PIN_NO(195) | 7) - -#define MT2712_PIN_196_TDMO1_MCLK__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) -#define MT2712_PIN_196_TDMO1_MCLK__FUNC_TDMO1_MCLK (MTK_PIN_NO(196) | 1) -#define MT2712_PIN_196_TDMO1_MCLK__FUNC_TDMO0_MCLK (MTK_PIN_NO(196) | 2) -#define MT2712_PIN_196_TDMO1_MCLK__FUNC_TDMIN_MCLK (MTK_PIN_NO(196) | 3) -#define MT2712_PIN_196_TDMO1_MCLK__FUNC_I2SO0_DO1 (MTK_PIN_NO(196) | 6) -#define MT2712_PIN_196_TDMO1_MCLK__FUNC_I2S_IQ1_SDIB (MTK_PIN_NO(196) | 7) - -#define MT2712_PIN_197_TDMO1_LRCK__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) -#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMO1_LRCK (MTK_PIN_NO(197) | 1) -#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMO0_LRCK (MTK_PIN_NO(197) | 2) -#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMIN_LRCK (MTK_PIN_NO(197) | 3) -#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMO0_DATA3 (MTK_PIN_NO(197) | 4) -#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMO1_DATA3 (MTK_PIN_NO(197) | 5) -#define MT2712_PIN_197_TDMO1_LRCK__FUNC_I2SO3_MCK (MTK_PIN_NO(197) | 6) -#define MT2712_PIN_197_TDMO1_LRCK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(197) | 7) - -#define MT2712_PIN_198_TDMO1_BCK__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) -#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMO1_BCK (MTK_PIN_NO(198) | 1) -#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMO0_BCK (MTK_PIN_NO(198) | 2) -#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMIN_BCK (MTK_PIN_NO(198) | 3) -#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMO0_DATA2 (MTK_PIN_NO(198) | 4) -#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMO1_DATA2 (MTK_PIN_NO(198) | 5) -#define MT2712_PIN_198_TDMO1_BCK__FUNC_I2SO3_BCK (MTK_PIN_NO(198) | 6) -#define MT2712_PIN_198_TDMO1_BCK__FUNC_TDMO1_DATA1 (MTK_PIN_NO(198) | 7) - -#define MT2712_PIN_199_TDMO1_DATA__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) -#define MT2712_PIN_199_TDMO1_DATA__FUNC_TDMO1_DATA (MTK_PIN_NO(199) | 1) -#define MT2712_PIN_199_TDMO1_DATA__FUNC_TDMO0_DATA (MTK_PIN_NO(199) | 2) -#define MT2712_PIN_199_TDMO1_DATA__FUNC_TDMIN_DI (MTK_PIN_NO(199) | 3) -#define MT2712_PIN_199_TDMO1_DATA__FUNC_TDMO0_DATA1 (MTK_PIN_NO(199) | 4) -#define MT2712_PIN_199_TDMO1_DATA__FUNC_TDMO1_DATA1 (MTK_PIN_NO(199) | 5) -#define MT2712_PIN_199_TDMO1_DATA__FUNC_I2SO3_WS (MTK_PIN_NO(199) | 6) - -#define MT2712_PIN_200_TDMO0_MCLK__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) -#define MT2712_PIN_200_TDMO0_MCLK__FUNC_TDMO0_MCLK0 (MTK_PIN_NO(200) | 1) -#define MT2712_PIN_200_TDMO0_MCLK__FUNC_TDMO1_MCLK0 (MTK_PIN_NO(200) | 2) -#define MT2712_PIN_200_TDMO0_MCLK__FUNC_PCM1_DI (MTK_PIN_NO(200) | 3) -#define MT2712_PIN_200_TDMO0_MCLK__FUNC_TDMO0_MCLK1 (MTK_PIN_NO(200) | 4) -#define MT2712_PIN_200_TDMO0_MCLK__FUNC_TDMO1_MCLK1 (MTK_PIN_NO(200) | 5) -#define MT2712_PIN_200_TDMO0_MCLK__FUNC_MRG_TX (MTK_PIN_NO(200) | 6) -#define MT2712_PIN_200_TDMO0_MCLK__FUNC_I2SO2_MCK (MTK_PIN_NO(200) | 7) - -#define MT2712_PIN_201_TDMO0_LRCK__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) -#define MT2712_PIN_201_TDMO0_LRCK__FUNC_TDMO0_LRCK0 (MTK_PIN_NO(201) | 1) -#define MT2712_PIN_201_TDMO0_LRCK__FUNC_TDMO1_LRCK0 (MTK_PIN_NO(201) | 2) -#define MT2712_PIN_201_TDMO0_LRCK__FUNC_PCM1_SYNC (MTK_PIN_NO(201) | 3) -#define MT2712_PIN_201_TDMO0_LRCK__FUNC_TDMO0_LRCK1 (MTK_PIN_NO(201) | 4) -#define MT2712_PIN_201_TDMO0_LRCK__FUNC_TDMO1_LRCK1 (MTK_PIN_NO(201) | 5) -#define MT2712_PIN_201_TDMO0_LRCK__FUNC_MRG_RX (MTK_PIN_NO(201) | 6) -#define MT2712_PIN_201_TDMO0_LRCK__FUNC_I2SO2_WS (MTK_PIN_NO(201) | 7) - -#define MT2712_PIN_202_TDMO0_BCK__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) -#define MT2712_PIN_202_TDMO0_BCK__FUNC_TDMO0_BCK0 (MTK_PIN_NO(202) | 1) -#define MT2712_PIN_202_TDMO0_BCK__FUNC_TDMO1_BCK0 (MTK_PIN_NO(202) | 2) -#define MT2712_PIN_202_TDMO0_BCK__FUNC_PCM1_CLK (MTK_PIN_NO(202) | 3) -#define MT2712_PIN_202_TDMO0_BCK__FUNC_TDMO0_BCK1 (MTK_PIN_NO(202) | 4) -#define MT2712_PIN_202_TDMO0_BCK__FUNC_TDMO1_BCK1 (MTK_PIN_NO(202) | 5) -#define MT2712_PIN_202_TDMO0_BCK__FUNC_MRG_SYNC (MTK_PIN_NO(202) | 6) -#define MT2712_PIN_202_TDMO0_BCK__FUNC_I2SO2_BCK (MTK_PIN_NO(202) | 7) - -#define MT2712_PIN_203_TDMO0_DATA__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) -#define MT2712_PIN_203_TDMO0_DATA__FUNC_TDMO0_DATA0 (MTK_PIN_NO(203) | 1) -#define MT2712_PIN_203_TDMO0_DATA__FUNC_TDMO1_DATA0 (MTK_PIN_NO(203) | 2) -#define MT2712_PIN_203_TDMO0_DATA__FUNC_PCM1_DO (MTK_PIN_NO(203) | 3) -#define MT2712_PIN_203_TDMO0_DATA__FUNC_TDMO0_DATA1 (MTK_PIN_NO(203) | 4) -#define MT2712_PIN_203_TDMO0_DATA__FUNC_TDMO1_DATA1 (MTK_PIN_NO(203) | 5) -#define MT2712_PIN_203_TDMO0_DATA__FUNC_MRG_CLK (MTK_PIN_NO(203) | 6) -#define MT2712_PIN_203_TDMO0_DATA__FUNC_I2SO2_DO (MTK_PIN_NO(203) | 7) - -#define MT2712_PIN_204_PERSTB_P0__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) -#define MT2712_PIN_204_PERSTB_P0__FUNC_PERST_B_P0 (MTK_PIN_NO(204) | 1) - -#define MT2712_PIN_205_CLKREQN_P0__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) -#define MT2712_PIN_205_CLKREQN_P0__FUNC_CLKREQ_N_P0 (MTK_PIN_NO(205) | 1) - -#define MT2712_PIN_206_WAKEEN_P0__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) -#define MT2712_PIN_206_WAKEEN_P0__FUNC_WAKE_EN_P0 (MTK_PIN_NO(206) | 1) - -#define MT2712_PIN_207_PERSTB_P1__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) -#define MT2712_PIN_207_PERSTB_P1__FUNC_PERST_B_P1 (MTK_PIN_NO(207) | 1) - -#define MT2712_PIN_208_CLKREQN_P1__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) -#define MT2712_PIN_208_CLKREQN_P1__FUNC_CLKREQ_N_P1 (MTK_PIN_NO(208) | 1) - -#define MT2712_PIN_209_WAKEEN_P1__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) -#define MT2712_PIN_209_WAKEEN_P1__FUNC_WAKE_EN_P1 (MTK_PIN_NO(209) | 1) - -#endif /* __DTS_MT2712_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi deleted file mode 100644 index db17d0a4e..000000000 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ /dev/null @@ -1,1127 +0,0 @@ -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: YT Shen - * - * SPDX-License-Identifier: (GPL-2.0 OR MIT) - */ - -#include -#include -#include -#include -#include -#include -#include "mt2712-pinfunc.h" - -/ { - compatible = "mediatek,mt2712"; - interrupt-parent = <&sysirq>; - #address-cells = <2>; - #size-cells = <2>; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - opp00 { - opp-hz = /bits/ 64 <598000000>; - opp-microvolt = <1000000>; - }; - opp01 { - opp-hz = /bits/ 64 <702000000>; - opp-microvolt = <1000000>; - }; - opp02 { - opp-hz = /bits/ 64 <793000000>; - opp-microvolt = <1000000>; - }; - }; - - cluster1_opp: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - opp00 { - opp-hz = /bits/ 64 <598000000>; - opp-microvolt = <1000000>; - }; - opp01 { - opp-hz = /bits/ 64 <702000000>; - opp-microvolt = <1000000>; - }; - opp02 { - opp-hz = /bits/ 64 <793000000>; - opp-microvolt = <1000000>; - }; - opp03 { - opp-hz = /bits/ 64 <897000000>; - opp-microvolt = <1000000>; - }; - opp04 { - opp-hz = /bits/ 64 <1001000000>; - opp-microvolt = <1000000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu2>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x000>; - clocks = <&mcucfg CLK_MCU_MP0_SEL>, - <&topckgen CLK_TOP_F_MP0_PLL1>; - clock-names = "cpu", "intermediate"; - proc-supply = <&cpus_fixed_vproc0>; - operating-points-v2 = <&cluster0_opp>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x001>; - enable-method = "psci"; - clocks = <&mcucfg CLK_MCU_MP0_SEL>, - <&topckgen CLK_TOP_F_MP0_PLL1>; - clock-names = "cpu", "intermediate"; - proc-supply = <&cpus_fixed_vproc0>; - operating-points-v2 = <&cluster0_opp>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - }; - - cpu2: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x200>; - enable-method = "psci"; - clocks = <&mcucfg CLK_MCU_MP2_SEL>, - <&topckgen CLK_TOP_F_BIG_PLL1>; - clock-names = "cpu", "intermediate"; - proc-supply = <&cpus_fixed_vproc1>; - operating-points-v2 = <&cluster1_opp>; - cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <100>; - exit-latency-us = <80>; - min-residency-us = <2000>; - arm,psci-suspend-param = <0x0010000>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <350>; - exit-latency-us = <80>; - min-residency-us = <3000>; - arm,psci-suspend-param = <0x1010000>; - }; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - baud_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - - sys_clk: dummyclk { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - - clk26m: oscillator@0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "clk26m"; - }; - - clk32k: oscillator@1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "clk32k"; - }; - - clkfpc: oscillator@2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "clkfpc"; - }; - - clkaud_ext_i_0: oscillator@3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <6500000>; - clock-output-names = "clkaud_ext_i_0"; - }; - - clkaud_ext_i_1: oscillator@4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <196608000>; - clock-output-names = "clkaud_ext_i_1"; - }; - - clkaud_ext_i_2: oscillator@5 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <180633600>; - clock-output-names = "clkaud_ext_i_2"; - }; - - clki2si0_mck_i: oscillator@6 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <30000000>; - clock-output-names = "clki2si0_mck_i"; - }; - - clki2si1_mck_i: oscillator@7 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <30000000>; - clock-output-names = "clki2si1_mck_i"; - }; - - clki2si2_mck_i: oscillator@8 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <30000000>; - clock-output-names = "clki2si2_mck_i"; - }; - - clktdmin_mclk_i: oscillator@9 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <30000000>; - clock-output-names = "clktdmin_mclk_i"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - topckgen: syscon@10000000 { - compatible = "mediatek,mt2712-topckgen", "syscon"; - reg = <0 0x10000000 0 0x1000>; - #clock-cells = <1>; - }; - - infracfg: syscon@10001000 { - compatible = "mediatek,mt2712-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - }; - - pericfg: syscon@10003000 { - compatible = "mediatek,mt2712-pericfg", "syscon"; - reg = <0 0x10003000 0 0x1000>; - #clock-cells = <1>; - }; - - syscfg_pctl_a: syscfg_pctl_a@10005000 { - compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; - }; - - pio: pinctrl@10005000 { - compatible = "mediatek,mt2712-pinctrl"; - reg = <0 0x1000b000 0 0x1000>; - mediatek,pctl-regmap = <&syscfg_pctl_a>; - pins-are-numbered; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - scpsys: power-controller@10006000 { - compatible = "mediatek,mt2712-scpsys", "syscon"; - #power-domain-cells = <1>; - reg = <0 0x10006000 0 0x1000>; - clocks = <&topckgen CLK_TOP_MM_SEL>, - <&topckgen CLK_TOP_MFG_SEL>, - <&topckgen CLK_TOP_VENC_SEL>, - <&topckgen CLK_TOP_JPGDEC_SEL>, - <&topckgen CLK_TOP_A1SYS_HP_SEL>, - <&topckgen CLK_TOP_VDEC_SEL>; - clock-names = "mm", "mfg", "venc", - "jpgdec", "audio", "vdec"; - infracfg = <&infracfg>; - }; - - uart5: serial@1000f000 { - compatible = "mediatek,mt2712-uart", - "mediatek,mt6577-uart"; - reg = <0 0x1000f000 0 0x400>; - interrupts = ; - clocks = <&baud_clk>, <&sys_clk>; - clock-names = "baud", "bus"; - dmas = <&apdma 10 - &apdma 11>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - rtc: rtc@10011000 { - compatible = "mediatek,mt2712-rtc"; - reg = <0 0x10011000 0 0x1000>; - interrupts = ; - }; - - spis1: spi@10013000 { - compatible = "mediatek,mt2712-spi-slave"; - reg = <0 0x10013000 0 0x100>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_AO_SPI1>; - clock-names = "spi"; - assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; - status = "disabled"; - }; - - iommu0: iommu@10205000 { - compatible = "mediatek,mt2712-m4u"; - reg = <0 0x10205000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_M4U>; - clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2 - &larb3 &larb6>; - #iommu-cells = <1>; - }; - - apmixedsys: syscon@10209000 { - compatible = "mediatek,mt2712-apmixedsys", "syscon"; - reg = <0 0x10209000 0 0x1000>; - #clock-cells = <1>; - }; - - iommu1: iommu@1020a000 { - compatible = "mediatek,mt2712-m4u"; - reg = <0 0x1020a000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_M4U>; - clock-names = "bclk"; - mediatek,larbs = <&larb4 &larb5 &larb7>; - #iommu-cells = <1>; - }; - - mcucfg: syscon@10220000 { - compatible = "mediatek,mt2712-mcucfg", "syscon"; - reg = <0 0x10220000 0 0x1000>; - #clock-cells = <1>; - }; - - sysirq: interrupt-controller@10220a80 { - compatible = "mediatek,mt2712-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10220a80 0 0x40>; - }; - - gic: interrupt-controller@10510000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; - reg = <0 0x10510000 0 0x10000>, - <0 0x10520000 0 0x20000>, - <0 0x10540000 0 0x20000>, - <0 0x10560000 0 0x20000>; - interrupts = ; - }; - - apdma: dma-controller@11000400 { - compatible = "mediatek,mt2712-uart-dma", - "mediatek,mt6577-uart-dma"; - reg = <0 0x11000400 0 0x80>, - <0 0x11000480 0 0x80>, - <0 0x11000500 0 0x80>, - <0 0x11000580 0 0x80>, - <0 0x11000600 0 0x80>, - <0 0x11000680 0 0x80>, - <0 0x11000700 0 0x80>, - <0 0x11000780 0 0x80>, - <0 0x11000800 0 0x80>, - <0 0x11000880 0 0x80>, - <0 0x11000900 0 0x80>, - <0 0x11000980 0 0x80>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; - dma-requests = <12>; - clocks = <&pericfg CLK_PERI_AP_DMA>; - clock-names = "apdma"; - #dma-cells = <1>; - }; - - auxadc: adc@11001000 { - compatible = "mediatek,mt2712-auxadc"; - reg = <0 0x11001000 0 0x1000>; - clocks = <&pericfg CLK_PERI_AUXADC>; - clock-names = "main"; - #io-channel-cells = <1>; - status = "disabled"; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt2712-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&baud_clk>, <&sys_clk>; - clock-names = "baud", "bus"; - dmas = <&apdma 0 - &apdma 1>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt2712-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&baud_clk>, <&sys_clk>; - clock-names = "baud", "bus"; - dmas = <&apdma 2 - &apdma 3>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt2712-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&baud_clk>, <&sys_clk>; - clock-names = "baud", "bus"; - dmas = <&apdma 4 - &apdma 5>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt2712-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11005000 0 0x400>; - interrupts = ; - clocks = <&baud_clk>, <&sys_clk>; - clock-names = "baud", "bus"; - dmas = <&apdma 6 - &apdma 7>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - pwm: pwm@11006000 { - compatible = "mediatek,mt2712-pwm"; - reg = <0 0x11006000 0 0x1000>; - #pwm-cells = <2>; - interrupts = ; - clocks = <&topckgen CLK_TOP_PWM_SEL>, - <&pericfg CLK_PERI_PWM>, - <&pericfg CLK_PERI_PWM0>, - <&pericfg CLK_PERI_PWM1>, - <&pericfg CLK_PERI_PWM2>, - <&pericfg CLK_PERI_PWM3>, - <&pericfg CLK_PERI_PWM4>, - <&pericfg CLK_PERI_PWM5>, - <&pericfg CLK_PERI_PWM6>, - <&pericfg CLK_PERI_PWM7>; - clock-names = "top", - "main", - "pwm1", - "pwm2", - "pwm3", - "pwm4", - "pwm5", - "pwm6", - "pwm7", - "pwm8"; - status = "disabled"; - }; - - i2c0: i2c@11007000 { - compatible = "mediatek,mt2712-i2c"; - reg = <0 0x11007000 0 0x90>, - <0 0x11000180 0 0x80>; - interrupts = ; - clock-div = <4>; - clocks = <&pericfg CLK_PERI_I2C0>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", - "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@11008000 { - compatible = "mediatek,mt2712-i2c"; - reg = <0 0x11008000 0 0x90>, - <0 0x11000200 0 0x80>; - interrupts = ; - clock-div = <4>; - clocks = <&pericfg CLK_PERI_I2C1>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", - "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@11009000 { - compatible = "mediatek,mt2712-i2c"; - reg = <0 0x11009000 0 0x90>, - <0 0x11000280 0 0x80>; - interrupts = ; - clock-div = <4>; - clocks = <&pericfg CLK_PERI_I2C2>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", - "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@1100a000 { - compatible = "mediatek,mt2712-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100a000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, - <&topckgen CLK_TOP_SPI_SEL>, - <&pericfg CLK_PERI_SPI0>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - nandc: nfi@1100e000 { - compatible = "mediatek,mt2712-nfc"; - reg = <0 0x1100e000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_NFI2X_EN>, <&pericfg CLK_PERI_NFI>; - clock-names = "nfi_clk", "pad_clk"; - ecc-engine = <&bch>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - bch: ecc@1100f000 { - compatible = "mediatek,mt2712-ecc"; - reg = <0 0x1100f000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_NFI1X_CK_EN>; - clock-names = "nfiecc_clk"; - status = "disabled"; - }; - - i2c3: i2c@11010000 { - compatible = "mediatek,mt2712-i2c"; - reg = <0 0x11010000 0 0x90>, - <0 0x11000300 0 0x80>; - interrupts = ; - clock-div = <4>; - clocks = <&pericfg CLK_PERI_I2C3>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", - "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@11011000 { - compatible = "mediatek,mt2712-i2c"; - reg = <0 0x11011000 0 0x90>, - <0 0x11000380 0 0x80>; - interrupts = ; - clock-div = <4>; - clocks = <&pericfg CLK_PERI_I2C4>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", - "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@11013000 { - compatible = "mediatek,mt2712-i2c"; - reg = <0 0x11013000 0 0x90>, - <0 0x11000100 0 0x80>; - interrupts = ; - clock-div = <4>; - clocks = <&pericfg CLK_PERI_I2C5>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", - "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@11015000 { - compatible = "mediatek,mt2712-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11015000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, - <&topckgen CLK_TOP_SPI_SEL>, - <&pericfg CLK_PERI_SPI2>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - spi3: spi@11016000 { - compatible = "mediatek,mt2712-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11016000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, - <&topckgen CLK_TOP_SPI_SEL>, - <&pericfg CLK_PERI_SPI3>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - spi4: spi@10012000 { - compatible = "mediatek,mt2712-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x10012000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_AO_SPI0>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - spi5: spi@11018000 { - compatible = "mediatek,mt2712-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11018000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, - <&topckgen CLK_TOP_SPI_SEL>, - <&pericfg CLK_PERI_SPI5>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - uart4: serial@11019000 { - compatible = "mediatek,mt2712-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11019000 0 0x400>; - interrupts = ; - clocks = <&baud_clk>, <&sys_clk>; - clock-names = "baud", "bus"; - dmas = <&apdma 8 - &apdma 9>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - stmmac_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <0x7>; - snps,rd_osr_lmt = <0x7>; - snps,blen = <0 0 0 0 16 8 4>; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <1>; - snps,rx-sched-sp; - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x0>; - snps,priority = <0x0>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <3>; - snps,tx-sched-wrr; - queue0 { - snps,weight = <0x10>; - snps,dcb-algorithm; - snps,priority = <0x0>; - }; - queue1 { - snps,weight = <0x11>; - snps,dcb-algorithm; - snps,priority = <0x1>; - }; - queue2 { - snps,weight = <0x12>; - snps,dcb-algorithm; - snps,priority = <0x2>; - }; - }; - - eth: ethernet@1101c000 { - compatible = "mediatek,mt2712-gmac"; - reg = <0 0x1101c000 0 0x1300>; - interrupts = ; - interrupt-names = "macirq"; - mac-address = [00 55 7b b5 7d f7]; - clock-names = "axi", - "apb", - "mac_main", - "ptp_ref"; - clocks = <&pericfg CLK_PERI_GMAC>, - <&pericfg CLK_PERI_GMAC_PCLK>, - <&topckgen CLK_TOP_ETHER_125M_SEL>, - <&topckgen CLK_TOP_ETHER_50M_SEL>; - assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>, - <&topckgen CLK_TOP_ETHER_50M_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>, - <&topckgen CLK_TOP_APLL1_D3>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>; - mediatek,pericfg = <&pericfg>; - snps,axi-config = <&stmmac_axi_setup>; - snps,mtl-rx-config = <&mtl_rx_setup>; - snps,mtl-tx-config = <&mtl_tx_setup>; - snps,txpbl = <1>; - snps,rxpbl = <1>; - clk_csr = <0>; - status = "disabled"; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt2712-mmc"; - reg = <0 0x11230000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_MSDC30_0>, - <&pericfg CLK_PERI_MSDC50_0_HCLK_EN>, - <&pericfg CLK_PERI_MSDC30_0_QTR_EN>, - <&pericfg CLK_PERI_MSDC50_0_EN>; - clock-names = "source", "hclk", "bus_clk", "source_cg"; - status = "disabled"; - }; - - mmc1: mmc@11240000 { - compatible = "mediatek,mt2712-mmc"; - reg = <0 0x11240000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_MSDC30_1>, - <&topckgen CLK_TOP_AXI_SEL>, - <&pericfg CLK_PERI_MSDC30_1_EN>; - clock-names = "source", "hclk", "source_cg"; - status = "disabled"; - }; - - mmc2: mmc@11250000 { - compatible = "mediatek,mt2712-mmc"; - reg = <0 0x11250000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_MSDC30_2>, - <&topckgen CLK_TOP_AXI_SEL>, - <&pericfg CLK_PERI_MSDC30_2_EN>; - clock-names = "source", "hclk", "source_cg"; - status = "disabled"; - }; - - ssusb: usb@11271000 { - compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; - reg = <0 0x11271000 0 0x3000>, - <0 0x11280700 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&u2port0 PHY_TYPE_USB2>, - <&u2port1 PHY_TYPE_USB2>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; - clocks = <&topckgen CLK_TOP_USB30_SEL>; - clock-names = "sys_ck"; - mediatek,syscon-wakeup = <&pericfg 0x510 2>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - usb_host0: xhci@11270000 { - compatible = "mediatek,mt2712-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11270000 0 0x1000>; - reg-names = "mac"; - interrupts = ; - power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; - clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; - clock-names = "sys_ck", "ref_ck"; - status = "disabled"; - }; - }; - - u3phy0: usb-phy@11290000 { - compatible = "mediatek,mt2712-tphy", - "mediatek,generic-tphy-v2"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x11290000 0x9000>; - status = "okay"; - - u2port0: usb-phy@0 { - reg = <0x0 0x700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u2port1: usb-phy@8000 { - reg = <0x8000 0x700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u3port0: usb-phy@8700 { - reg = <0x8700 0x900>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - ssusb1: usb@112c1000 { - compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; - reg = <0 0x112c1000 0 0x3000>, - <0 0x112d0700 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&u2port2 PHY_TYPE_USB2>, - <&u2port3 PHY_TYPE_USB2>, - <&u3port1 PHY_TYPE_USB3>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; - clocks = <&topckgen CLK_TOP_USB30_SEL>; - clock-names = "sys_ck"; - mediatek,syscon-wakeup = <&pericfg 0x514 2>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - usb_host1: xhci@112c0000 { - compatible = "mediatek,mt2712-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x112c0000 0 0x1000>; - reg-names = "mac"; - interrupts = ; - power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; - clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; - clock-names = "sys_ck", "ref_ck"; - status = "disabled"; - }; - }; - - u3phy1: usb-phy@112e0000 { - compatible = "mediatek,mt2712-tphy", - "mediatek,generic-tphy-v2"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x112e0000 0x9000>; - status = "okay"; - - u2port2: usb-phy@0 { - reg = <0x0 0x700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u2port3: usb-phy@8000 { - reg = <0x8000 0x700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u3port1: usb-phy@8700 { - reg = <0x8700 0x900>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - pcie: pcie@11700000 { - compatible = "mediatek,mt2712-pcie"; - device_type = "pci"; - reg = <0 0x11700000 0 0x1000>, - <0 0x112ff000 0 0x1000>; - reg-names = "port0", "port1"; - #address-cells = <3>; - #size-cells = <2>; - interrupts = , - ; - clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, - <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, - <&pericfg CLK_PERI_PCIE0>, - <&pericfg CLK_PERI_PCIE1>; - clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; - phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>; - phy-names = "pcie-phy0", "pcie-phy1"; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; - - pcie0: pcie@0,0 { - device_type = "pci"; - status = "disabled"; - reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - pcie1: pcie@1,0 { - device_type = "pci"; - status = "disabled"; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - }; - - mfgcfg: syscon@13000000 { - compatible = "mediatek,mt2712-mfgcfg", "syscon"; - reg = <0 0x13000000 0 0x1000>; - #clock-cells = <1>; - }; - - mmsys: syscon@14000000 { - compatible = "mediatek,mt2712-mmsys", "syscon"; - reg = <0 0x14000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb0: larb@14021000 { - compatible = "mediatek,mt2712-smi-larb"; - reg = <0 0x14021000 0 0x1000>; - mediatek,smi = <&smi_common0>; - mediatek,larb-id = <0>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_SMI_LARB0>, - <&mmsys CLK_MM_SMI_LARB0>; - clock-names = "apb", "smi"; - }; - - smi_common0: smi@14022000 { - compatible = "mediatek,mt2712-smi-common"; - reg = <0 0x14022000 0 0x1000>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_SMI_COMMON>, - <&mmsys CLK_MM_SMI_COMMON>; - clock-names = "apb", "smi"; - }; - - larb4: larb@14027000 { - compatible = "mediatek,mt2712-smi-larb"; - reg = <0 0x14027000 0 0x1000>; - mediatek,smi = <&smi_common1>; - mediatek,larb-id = <4>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_SMI_LARB4>, - <&mmsys CLK_MM_SMI_LARB4>; - clock-names = "apb", "smi"; - }; - - larb5: larb@14030000 { - compatible = "mediatek,mt2712-smi-larb"; - reg = <0 0x14030000 0 0x1000>; - mediatek,smi = <&smi_common1>; - mediatek,larb-id = <5>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_SMI_LARB5>, - <&mmsys CLK_MM_SMI_LARB5>; - clock-names = "apb", "smi"; - }; - - smi_common1: smi@14031000 { - compatible = "mediatek,mt2712-smi-common"; - reg = <0 0x14031000 0 0x1000>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_SMI_COMMON1>, - <&mmsys CLK_MM_SMI_COMMON1>; - clock-names = "apb", "smi"; - }; - - larb7: larb@14032000 { - compatible = "mediatek,mt2712-smi-larb"; - reg = <0 0x14032000 0 0x1000>; - mediatek,smi = <&smi_common1>; - mediatek,larb-id = <7>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_SMI_LARB7>, - <&mmsys CLK_MM_SMI_LARB7>; - clock-names = "apb", "smi"; - }; - - imgsys: syscon@15000000 { - compatible = "mediatek,mt2712-imgsys", "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb2: larb@15001000 { - compatible = "mediatek,mt2712-smi-larb"; - reg = <0 0x15001000 0 0x1000>; - mediatek,smi = <&smi_common0>; - mediatek,larb-id = <2>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>; - clocks = <&imgsys CLK_IMG_SMI_LARB2>, - <&imgsys CLK_IMG_SMI_LARB2>; - clock-names = "apb", "smi"; - }; - - bdpsys: syscon@15010000 { - compatible = "mediatek,mt2712-bdpsys", "syscon"; - reg = <0 0x15010000 0 0x1000>; - #clock-cells = <1>; - }; - - vdecsys: syscon@16000000 { - compatible = "mediatek,mt2712-vdecsys", "syscon"; - reg = <0 0x16000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb1: larb@16010000 { - compatible = "mediatek,mt2712-smi-larb"; - reg = <0 0x16010000 0 0x1000>; - mediatek,smi = <&smi_common0>; - mediatek,larb-id = <1>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>; - clocks = <&vdecsys CLK_VDEC_CKEN>, - <&vdecsys CLK_VDEC_LARB1_CKEN>; - clock-names = "apb", "smi"; - }; - - vencsys: syscon@18000000 { - compatible = "mediatek,mt2712-vencsys", "syscon"; - reg = <0 0x18000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb3: larb@18001000 { - compatible = "mediatek,mt2712-smi-larb"; - reg = <0 0x18001000 0 0x1000>; - mediatek,smi = <&smi_common0>; - mediatek,larb-id = <3>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>; - clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>, - <&vencsys CLK_VENC_VENC>; - clock-names = "apb", "smi"; - }; - - larb6: larb@18002000 { - compatible = "mediatek,mt2712-smi-larb"; - reg = <0 0x18002000 0 0x1000>; - mediatek,smi = <&smi_common0>; - mediatek,larb-id = <6>; - power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>; - clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>, - <&vencsys CLK_VENC_VENC>; - clock-names = "apb", "smi"; - }; - - jpgdecsys: syscon@19000000 { - compatible = "mediatek,mt2712-jpgdecsys", "syscon"; - reg = <0 0x19000000 0 0x1000>; - #clock-cells = <1>; - }; -}; - diff --git a/arch/arm64/boot/dts/mediatek/mt6358.dtsi b/arch/arm64/boot/dts/mediatek/mt6358.dtsi deleted file mode 100644 index fa159b203..000000000 --- a/arch/arm64/boot/dts/mediatek/mt6358.dtsi +++ /dev/null @@ -1,360 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (c) 2020 MediaTek Inc. - */ - -&pwrap { - pmic: mt6358 { - compatible = "mediatek,mt6358"; - interrupt-controller; - interrupt-parent = <&pio>; - interrupts = <182 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <2>; - - mt6358codec: mt6358codec { - compatible = "mediatek,mt6358-sound"; - }; - - mt6358regulator: mt6358regulator { - compatible = "mediatek,mt6358-regulator"; - - mt6358_vdram1_reg: buck_vdram1 { - regulator-name = "vdram1"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <2087500>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <0>; - regulator-always-on; - regulator-allowed-modes = <0 1>; - }; - - mt6358_vcore_reg: buck_vcore { - regulator-name = "vcore"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1293750>; - regulator-ramp-delay = <6250>; - regulator-enable-ramp-delay = <200>; - regulator-always-on; - regulator-allowed-modes = <0 1>; - }; - - mt6358_vpa_reg: buck_vpa { - regulator-name = "vpa"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3650000>; - regulator-ramp-delay = <50000>; - regulator-enable-ramp-delay = <250>; - regulator-allowed-modes = <0 1>; - }; - - mt6358_vproc11_reg: buck_vproc11 { - regulator-name = "vproc11"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1293750>; - regulator-ramp-delay = <6250>; - regulator-enable-ramp-delay = <200>; - regulator-always-on; - regulator-allowed-modes = <0 1>; - }; - - mt6358_vproc12_reg: buck_vproc12 { - regulator-name = "vproc12"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1293750>; - regulator-ramp-delay = <6250>; - regulator-enable-ramp-delay = <200>; - regulator-always-on; - regulator-allowed-modes = <0 1>; - }; - - mt6358_vgpu_reg: buck_vgpu { - regulator-name = "vgpu"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1293750>; - regulator-ramp-delay = <6250>; - regulator-enable-ramp-delay = <200>; - regulator-allowed-modes = <0 1>; - }; - - mt6358_vs2_reg: buck_vs2 { - regulator-name = "vs2"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <2087500>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <0>; - regulator-always-on; - }; - - mt6358_vmodem_reg: buck_vmodem { - regulator-name = "vmodem"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1293750>; - regulator-ramp-delay = <6250>; - regulator-enable-ramp-delay = <900>; - regulator-always-on; - regulator-allowed-modes = <0 1>; - }; - - mt6358_vs1_reg: buck_vs1 { - regulator-name = "vs1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <2587500>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <0>; - regulator-always-on; - }; - - mt6358_vdram2_reg: ldo_vdram2 { - regulator-name = "vdram2"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <3300>; - }; - - mt6358_vsim1_reg: ldo_vsim1 { - regulator-name = "vsim1"; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <3100000>; - regulator-enable-ramp-delay = <540>; - }; - - mt6358_vibr_reg: ldo_vibr { - regulator-name = "vibr"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <60>; - }; - - mt6358_vrf12_reg: ldo_vrf12 { - compatible = "regulator-fixed"; - regulator-name = "vrf12"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-enable-ramp-delay = <120>; - }; - - mt6358_vio18_reg: ldo_vio18 { - compatible = "regulator-fixed"; - regulator-name = "vio18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <2700>; - regulator-always-on; - }; - - mt6358_vusb_reg: ldo_vusb { - regulator-name = "vusb"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3100000>; - regulator-enable-ramp-delay = <270>; - regulator-always-on; - }; - - mt6358_vcamio_reg: ldo_vcamio { - compatible = "regulator-fixed"; - regulator-name = "vcamio"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <325>; - }; - - mt6358_vcamd_reg: ldo_vcamd { - regulator-name = "vcamd"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <325>; - }; - - mt6358_vcn18_reg: ldo_vcn18 { - compatible = "regulator-fixed"; - regulator-name = "vcn18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <270>; - }; - - mt6358_vfe28_reg: ldo_vfe28 { - compatible = "regulator-fixed"; - regulator-name = "vfe28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <270>; - }; - - mt6358_vsram_proc11_reg: ldo_vsram_proc11 { - regulator-name = "vsram_proc11"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1293750>; - regulator-ramp-delay = <6250>; - regulator-enable-ramp-delay = <240>; - regulator-always-on; - }; - - mt6358_vcn28_reg: ldo_vcn28 { - compatible = "regulator-fixed"; - regulator-name = "vcn28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <270>; - }; - - mt6358_vsram_others_reg: ldo_vsram_others { - regulator-name = "vsram_others"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1293750>; - regulator-ramp-delay = <6250>; - regulator-enable-ramp-delay = <240>; - regulator-always-on; - }; - - mt6358_vsram_gpu_reg: ldo_vsram_gpu { - regulator-name = "vsram_gpu"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1293750>; - regulator-ramp-delay = <6250>; - regulator-enable-ramp-delay = <240>; - }; - - mt6358_vxo22_reg: ldo_vxo22 { - compatible = "regulator-fixed"; - regulator-name = "vxo22"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - regulator-enable-ramp-delay = <120>; - regulator-always-on; - }; - - mt6358_vefuse_reg: ldo_vefuse { - regulator-name = "vefuse"; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - regulator-enable-ramp-delay = <270>; - }; - - mt6358_vaux18_reg: ldo_vaux18 { - compatible = "regulator-fixed"; - regulator-name = "vaux18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <270>; - }; - - mt6358_vmch_reg: ldo_vmch { - regulator-name = "vmch"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <60>; - }; - - mt6358_vbif28_reg: ldo_vbif28 { - compatible = "regulator-fixed"; - regulator-name = "vbif28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <270>; - }; - - mt6358_vsram_proc12_reg: ldo_vsram_proc12 { - regulator-name = "vsram_proc12"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1293750>; - regulator-ramp-delay = <6250>; - regulator-enable-ramp-delay = <240>; - regulator-always-on; - }; - - mt6358_vcama1_reg: ldo_vcama1 { - regulator-name = "vcama1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <325>; - }; - - mt6358_vemc_reg: ldo_vemc { - regulator-name = "vemc"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <60>; - }; - - mt6358_vio28_reg: ldo_vio28 { - compatible = "regulator-fixed"; - regulator-name = "vio28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <270>; - }; - - mt6358_va12_reg: ldo_va12 { - compatible = "regulator-fixed"; - regulator-name = "va12"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-enable-ramp-delay = <270>; - regulator-always-on; - }; - - mt6358_vrf18_reg: ldo_vrf18 { - compatible = "regulator-fixed"; - regulator-name = "vrf18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <120>; - }; - - mt6358_vcn33_bt_reg: ldo_vcn33_bt { - regulator-name = "vcn33_bt"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3500000>; - regulator-enable-ramp-delay = <270>; - }; - - mt6358_vcn33_wifi_reg: ldo_vcn33_wifi { - regulator-name = "vcn33_wifi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3500000>; - regulator-enable-ramp-delay = <270>; - }; - - mt6358_vcama2_reg: ldo_vcama2 { - regulator-name = "vcama2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <325>; - }; - - mt6358_vmc_reg: ldo_vmc { - regulator-name = "vmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <60>; - }; - - mt6358_vldo28_reg: ldo_vldo28 { - regulator-name = "vldo28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <270>; - }; - - mt6358_vaud28_reg: ldo_vaud28 { - compatible = "regulator-fixed"; - regulator-name = "vaud28"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <270>; - }; - - mt6358_vsim2_reg: ldo_vsim2 { - regulator-name = "vsim2"; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <3100000>; - regulator-enable-ramp-delay = <540>; - }; - }; - - mt6358rtc: mt6358rtc { - compatible = "mediatek,mt6358-rtc"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt6380.dtsi b/arch/arm64/boot/dts/mediatek/mt6380.dtsi deleted file mode 100644 index 53b335d2d..000000000 --- a/arch/arm64/boot/dts/mediatek/mt6380.dtsi +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dts file for MediaTek MT6380 regulator - * - * Copyright (c) 2018 MediaTek Inc. - * Author: Chenglin Xu - * Sean Wang - */ - -&pwrap { - regulators { - compatible = "mediatek,mt6380-regulator"; - - mt6380_vcpu_reg: buck-vcore1 { - regulator-name = "vcore1"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1393750>; - regulator-ramp-delay = <6250>; - regulator-always-on; - regulator-boot-on; - }; - - mt6380_vcore_reg: buck-vcore { - regulator-name = "vcore"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1393750>; - regulator-ramp-delay = <6250>; - regulator-always-on; - regulator-boot-on; - }; - - mt6380_vrf_reg: buck-vrf { - regulator-name = "vrf"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1575000>; - regulator-ramp-delay = <0>; - regulator-always-on; - regulator-boot-on; - }; - - mt6380_vm_reg: ldo-vm { - regulator-name = "vm"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1400000>; - regulator-ramp-delay = <0>; - regulator-always-on; - regulator-boot-on; - }; - - mt6380_va_reg: ldo-va { - regulator-name = "va"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <0>; - regulator-always-on; - regulator-boot-on; - }; - - mt6380_vphy_reg: ldo-vphy { - regulator-name = "vphy"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <0>; - regulator-always-on; - regulator-boot-on; - }; - - mt6380_vddr_reg: ldo-vddr { - regulator-name = "vddr"; - regulator-min-microvolt = <1240000>; - regulator-max-microvolt = <1840000>; - regulator-ramp-delay = <0>; - regulator-always-on; - regulator-boot-on; - }; - - mt6380_vt_reg: ldo-vt { - regulator-name = "vt"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <0>; - regulator-always-on; - regulator-boot-on; - }; - }; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt6755-evb.dts b/arch/arm64/boot/dts/mediatek/mt6755-evb.dts deleted file mode 100644 index e079b7932..000000000 --- a/arch/arm64/boot/dts/mediatek/mt6755-evb.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2016 MediaTek Inc. - * Author: Mars.C - */ - -/dts-v1/; -#include "mt6755.dtsi" - -/ { - model = "MediaTek MT6755 EVB"; - compatible = "mediatek,mt6755-evb", "mediatek,mt6755"; - - aliases { - serial0 = &uart0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x1e800000>; - }; - - chosen { - stdout-path = "serial0:921600n8"; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt6755.dtsi b/arch/arm64/boot/dts/mediatek/mt6755.dtsi deleted file mode 100644 index 01ba77669..000000000 --- a/arch/arm64/boot/dts/mediatek/mt6755.dtsi +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2016 MediaTek Inc. - * Author: Mars.C - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -/ { - compatible = "mediatek,mt6755"; - interrupt-parent = <&sysirq>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x001>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x002>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x003>; - }; - - cpu4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x100>; - }; - - cpu5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x101>; - }; - - cpu6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x102>; - }; - - cpu7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x103>; - }; - }; - - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - sysirq: intpol-controller@10200620 { - compatible = "mediatek,mt6755-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200620 0 0x20>; - }; - - gic: interrupt-controller@10231000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; - reg = <0 0x10231000 0 0x1000>, - <0 0x10232000 0 0x2000>, - <0 0x10234000 0 0x2000>, - <0 0x10236000 0 0x2000>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt6755-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt6755-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt6795-evb.dts b/arch/arm64/boot/dts/mediatek/mt6795-evb.dts deleted file mode 100644 index 1ed2f81ed..000000000 --- a/arch/arm64/boot/dts/mediatek/mt6795-evb.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2015 MediaTek Inc. - * Author: Mars.C - */ - -/dts-v1/; -#include "mt6795.dtsi" - -/ { - model = "MediaTek MT6795 Evaluation Board"; - compatible = "mediatek,mt6795-evb", "mediatek,mt6795"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x1e800000>; - }; - - chosen { - stdout-path = "serial0:921600n8"; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi deleted file mode 100644 index c85659d0f..000000000 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (c) 2015 MediaTek Inc. - * Author: Mars.C - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -/ { - compatible = "mediatek,mt6795"; - interrupt-parent = <&sysirq>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x001>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x002>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x003>; - }; - - cpu4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x100>; - }; - - cpu5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x101>; - }; - - cpu6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x102>; - }; - - cpu7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x103>; - }; - }; - - system_clk: dummy13m { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; - - rtc_clk: dummy32k { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - sysirq: intpol-controller@10200620 { - compatible = "mediatek,mt6795-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200620 0 0x20>; - }; - - gic: interrupt-controller@10221000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; - reg = <0 0x10221000 0 0x1000>, - <0 0x10222000 0 0x2000>, - <0 0x10224000 0 0x2000>, - <0 0x10226000 0 0x2000>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt6795-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt6795-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt6795-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt6795-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11005000 0 0x400>; - interrupts = ; - clocks = <&uart_clk>; - status = "disabled"; - }; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt6797-evb.dts b/arch/arm64/boot/dts/mediatek/mt6797-evb.dts deleted file mode 100644 index 2327e752d..000000000 --- a/arch/arm64/boot/dts/mediatek/mt6797-evb.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: Mars.C - */ - -/dts-v1/; -#include "mt6797.dtsi" - -/ { - model = "MediaTek MT6797 Evaluation Board"; - compatible = "mediatek,mt6797-evb", "mediatek,mt6797"; - - aliases { - serial0 = &uart0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x1e800000>; - }; - - chosen {}; -}; - -&uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts deleted file mode 100644 index eff9e8dbd..000000000 --- a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for MediaTek X20 Development Board - * - * Copyright (C) 2018, Linaro Ltd. - * - */ - -/dts-v1/; - -#include "mt6797.dtsi" - -/ { - model = "Mediatek X20 Development Board"; - compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797"; - - aliases { - serial0 = &uart1; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x80000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -/* HDMI */ -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -/* HS - I2C2 */ -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; -}; - -/* HS - I2C3 */ -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins_a>; - status = "okay"; -}; - -/* LS - I2C0 */ -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_a>; - status = "okay"; -}; - -/* LS - I2C1 */ -&i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins_a>; - status = "okay"; -}; - -/* POWER_VPROC */ -&i2c6 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_pins_a>; - status = "okay"; -}; - -/* FAN53555 */ -&i2c7 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_pins_a>; - status = "okay"; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_a>; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi deleted file mode 100644 index 156162310..000000000 --- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi +++ /dev/null @@ -1,483 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: Mars.C - */ - -#include -#include -#include -#include - -/ { - compatible = "mediatek,mt6797"; - interrupt-parent = <&sysirq>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x001>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x002>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x003>; - }; - - cpu4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x100>; - }; - - cpu5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x101>; - }; - - cpu6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x102>; - }; - - cpu7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x103>; - }; - - cpu8: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x200>; - }; - - cpu9: cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - enable-method = "psci"; - reg = <0x201>; - }; - }; - - clk26m: oscillator@0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "clk26m"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - topckgen: topckgen@10000000 { - compatible = "mediatek,mt6797-topckgen"; - reg = <0 0x10000000 0 0x1000>; - #clock-cells = <1>; - }; - - infrasys: infracfg_ao@10001000 { - compatible = "mediatek,mt6797-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - }; - - pio: pinctrl@10005000 { - compatible = "mediatek,mt6797-pinctrl"; - reg = <0 0x10005000 0 0x1000>, - <0 0x10002000 0 0x400>, - <0 0x10002400 0 0x400>, - <0 0x10002800 0 0x400>, - <0 0x10002C00 0 0x400>; - reg-names = "gpio", "iocfgl", "iocfgb", - "iocfgr", "iocfgt"; - gpio-controller; - #gpio-cells = <2>; - - uart0_pins_a: uart0 { - pins0 { - pinmux = , - ; - }; - }; - - uart1_pins_a: uart1 { - pins1 { - pinmux = , - ; - }; - }; - - i2c0_pins_a: i2c0 { - pins0 { - pinmux = , - ; - }; - }; - - i2c1_pins_a: i2c1 { - pins1 { - pinmux = , - ; - }; - }; - - i2c2_pins_a: i2c2 { - pins2 { - pinmux = , - ; - }; - }; - - i2c3_pins_a: i2c3 { - pins3 { - pinmux = , - ; - }; - }; - - i2c4_pins_a: i2c4 { - pins4 { - pinmux = , - ; - }; - }; - - i2c5_pins_a: i2c5 { - pins5 { - pinmux = , - ; - }; - }; - - i2c6_pins_a: i2c6 { - pins6 { - pinmux = , - ; - }; - }; - - i2c7_pins_a: i2c7 { - pins7 { - pinmux = , - ; - }; - }; - }; - - scpsys: power-controller@10006000 { - compatible = "mediatek,mt6797-scpsys"; - #power-domain-cells = <1>; - reg = <0 0x10006000 0 0x1000>; - clocks = <&topckgen CLK_TOP_MUX_MFG>, - <&topckgen CLK_TOP_MUX_MM>, - <&topckgen CLK_TOP_MUX_VDEC>; - clock-names = "mfg", "mm", "vdec"; - infracfg = <&infrasys>; - }; - - watchdog: watchdog@10007000 { - compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt"; - reg = <0 0x10007000 0 0x100>; - }; - - apmixedsys: apmixed@1000c000 { - compatible = "mediatek,mt6797-apmixedsys"; - reg = <0 0x1000c000 0 0x1000>; - #clock-cells = <1>; - }; - - sysirq: intpol-controller@10200620 { - compatible = "mediatek,mt6797-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10220620 0 0x20>, - <0 0x10220690 0 0x10>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt6797-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&infrasys CLK_INFRA_UART0>, - <&infrasys CLK_INFRA_AP_DMA>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt6797-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&infrasys CLK_INFRA_UART1>, - <&infrasys CLK_INFRA_AP_DMA>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt6797-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&infrasys CLK_INFRA_UART2>, - <&infrasys CLK_INFRA_AP_DMA>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt6797-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11005000 0 0x400>; - interrupts = ; - clocks = <&infrasys CLK_INFRA_UART3>, - <&infrasys CLK_INFRA_AP_DMA>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - i2c0: i2c@11007000 { - compatible = "mediatek,mt6797-i2c", - "mediatek,mt6577-i2c"; - id = <0>; - reg = <0 0x11007000 0 0x1000>, - <0 0x11000100 0 0x80>; - interrupts = ; - clocks = <&infrasys CLK_INFRA_I2C0>, - <&infrasys CLK_INFRA_AP_DMA>; - clock-names = "main", "dma"; - clock-div = <10>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@11008000 { - compatible = "mediatek,mt6797-i2c", - "mediatek,mt6577-i2c"; - id = <1>; - reg = <0 0x11008000 0 0x1000>, - <0 0x11000180 0 0x80>; - interrupts = ; - clocks = <&infrasys CLK_INFRA_I2C1>, - <&infrasys CLK_INFRA_AP_DMA>; - clock-names = "main", "dma"; - clock-div = <10>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c8: i2c@11009000 { - compatible = "mediatek,mt6797-i2c", - "mediatek,mt6577-i2c"; - id = <8>; - reg = <0 0x11009000 0 0x1000>, - <0 0x11000200 0 0x80>; - interrupts = ; - clocks = <&infrasys CLK_INFRA_I2C2>, - <&infrasys CLK_INFRA_AP_DMA>, - <&infrasys CLK_INFRA_I2C2_ARB>; - clock-names = "main", "dma", "arb"; - clock-div = <10>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c9: i2c@1100d000 { - compatible = "mediatek,mt6797-i2c", - "mediatek,mt6577-i2c"; - id = <9>; - reg = <0 0x1100d000 0 0x1000>, - <0 0x11000280 0 0x80>; - interrupts = ; - clocks = <&infrasys CLK_INFRA_I2C3>, - <&infrasys CLK_INFRA_AP_DMA>, - <&infrasys CLK_INFRA_I2C3_ARB>; - clock-names = "main", "dma", "arb"; - clock-div = <10>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c6: i2c@1100e000 { - compatible = "mediatek,mt6797-i2c", - "mediatek,mt6577-i2c"; - id = <6>; - reg = <0 0x1100e000 0 0x1000>, - <0 0x11000500 0 0x80>; - interrupts = ; - clocks = <&infrasys CLK_INFRA_I2C_APPM>, - <&infrasys CLK_INFRA_AP_DMA>; - clock-names = "main", "dma"; - clock-div = <10>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c7: i2c@11010000 { - compatible = "mediatek,mt6797-i2c", - "mediatek,mt6577-i2c"; - id = <7>; - reg = <0 0x11010000 0 0x1000>, - <0 0x11000580 0 0x80>; - interrupts = ; - clocks = <&infrasys CLK_INFRA_I2C_GPUPM>, - <&infrasys CLK_INFRA_AP_DMA>; - clock-names = "main", "dma"; - clock-div = <10>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@11011000 { - compatible = "mediatek,mt6797-i2c", - "mediatek,mt6577-i2c"; - id = <4>; - reg = <0 0x11011000 0 0x1000>, - <0 0x11000300 0 0x80>; - interrupts = ; - clocks = <&infrasys CLK_INFRA_I2C4>, - <&infrasys CLK_INFRA_AP_DMA>; - clock-names = "main", "dma"; - clock-div = <10>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@11013000 { - compatible = "mediatek,mt6797-i2c", - "mediatek,mt6577-i2c"; - id = <2>; - reg = <0 0x11013000 0 0x1000>, - <0 0x11000400 0 0x80>; - interrupts = ; - clocks = <&infrasys CLK_INFRA_I2C2_IMM>, - <&infrasys CLK_INFRA_AP_DMA>, - <&infrasys CLK_INFRA_I2C2_ARB>; - clock-names = "main", "dma", "arb"; - clock-div = <10>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@11014000 { - compatible = "mediatek,mt6797-i2c", - "mediatek,mt6577-i2c"; - id = <3>; - reg = <0 0x11014000 0 0x1000>, - <0 0x11000480 0 0x80>; - interrupts = ; - clocks = <&infrasys CLK_INFRA_I2C3_IMM>, - <&infrasys CLK_INFRA_AP_DMA>, - <&infrasys CLK_INFRA_I2C3_ARB>; - clock-names = "main", "dma", "arb"; - clock-div = <10>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@1101c000 { - compatible = "mediatek,mt6797-i2c", - "mediatek,mt6577-i2c"; - id = <5>; - reg = <0 0x1101c000 0 0x1000>, - <0 0x11000380 0 0x80>; - interrupts = ; - clocks = <&infrasys CLK_INFRA_I2C5>, - <&infrasys CLK_INFRA_AP_DMA>; - clock-names = "main", "dma"; - clock-div = <10>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmsys: syscon@14000000 { - compatible = "mediatek,mt6797-mmsys", "syscon"; - reg = <0 0x14000000 0 0x1000>; - #clock-cells = <1>; - }; - - imgsys: imgsys_config@15000000 { - compatible = "mediatek,mt6797-imgsys", "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - }; - - vdecsys: vdec_gcon@16000000 { - compatible = "mediatek,mt6797-vdecsys", "syscon"; - reg = <0 0x16000000 0 0x10000>; - #clock-cells = <1>; - }; - - vencsys: venc_gcon@17000000 { - compatible = "mediatek,mt6797-vencsys", "syscon"; - reg = <0 0x17000000 0 0x1000>; - #clock-cells = <1>; - }; - - gic: interrupt-controller@19000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupts = ; - interrupt-controller; - reg = <0 0x19000000 0 0x10000>, /* GICD */ - <0 0x19200000 0 0x200000>, /* GICR */ - <0 0x10240000 0 0x2000>; /* GICC */ - }; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts deleted file mode 100644 index 9a11e5c60..000000000 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ /dev/null @@ -1,599 +0,0 @@ -/* - * Copyright (c) 2018 MediaTek Inc. - * Author: Ryder Lee - * - * SPDX-License-Identifier: (GPL-2.0 OR MIT) - */ - -/dts-v1/; -#include -#include - -#include "mt7622.dtsi" -#include "mt6380.dtsi" - -/ { - model = "Bananapi BPI-R64"; - compatible = "bananapi,bpi-r64", "mediatek,mt7622"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; - }; - - cpus { - cpu@0 { - proc-supply = <&mt6380_vcpu_reg>; - sram-supply = <&mt6380_vm_reg>; - }; - - cpu@1 { - proc-supply = <&mt6380_vcpu_reg>; - sram-supply = <&mt6380_vm_reg>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - factory { - label = "factory"; - linux,code = ; - gpios = <&pio 0 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "wps"; - linux,code = ; - gpios = <&pio 102 GPIO_ACTIVE_HIGH>; - }; - }; - - leds { - compatible = "gpio-leds"; - - green { - label = "bpi-r64:pio:green"; - gpios = <&pio 89 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - red { - label = "bpi-r64:pio:red"; - gpios = <&pio 88 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - memory { - reg = <0 0x40000000 0 0x40000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&bch { - status = "disabled"; -}; - -&btif { - status = "okay"; -}; - -&cir { - pinctrl-names = "default"; - pinctrl-0 = <&irrx_pins>; - status = "okay"; -}; - -ð { - status = "okay"; - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "rgmii"; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - }; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - switch@0 { - compatible = "mediatek,mt7531"; - reg = <0>; - reset-gpios = <&pio 54 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "wan"; - }; - - port@1 { - reg = <1>; - label = "lan0"; - }; - - port@2 { - reg = <2>; - label = "lan1"; - }; - - port@3 { - reg = <3>; - label = "lan2"; - }; - - port@4 { - reg = <4>; - label = "lan3"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - }; - }; - - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&emmc_pins_default>; - pinctrl-1 = <&emmc_pins_uhs>; - status = "okay"; - bus-width = <8>; - max-frequency = <50000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; - non-removable; -}; - -&mmc1 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&sd0_pins_default>; - pinctrl-1 = <&sd0_pins_uhs>; - status = "okay"; - bus-width = <4>; - max-frequency = <50000000>; - cap-sd-highspeed; - r_smpl = <1>; - cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; -}; - -&nandc { - pinctrl-names = "default"; - pinctrl-0 = <¶llel_nand_pins>; - status = "disabled"; -}; - -&nor_flash { - pinctrl-names = "default"; - pinctrl-0 = <&spi_nor_pins>; - status = "disabled"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; - status = "okay"; - - pcie@0,0 { - status = "okay"; - }; - - pcie@1,0 { - status = "okay"; - }; -}; - -&pio { - /* Attention: GPIO 90 is used to switch between PCIe@1,0 and - * SATA functions. i.e. output-high: PCIe, output-low: SATA - */ - asm_sel { - gpio-hog; - gpios = <90 GPIO_ACTIVE_HIGH>; - output-high; - }; - - /* eMMC is shared pin with parallel NAND */ - emmc_pins_default: emmc-pins-default { - mux { - function = "emmc", "emmc_rst"; - groups = "emmc"; - }; - - /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", - * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, - * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively - */ - conf-cmd-dat { - pins = "NDL0", "NDL1", "NDL2", - "NDL3", "NDL4", "NDL5", - "NDL6", "NDL7", "NRB"; - input-enable; - bias-pull-up; - }; - - conf-clk { - pins = "NCLE"; - bias-pull-down; - }; - }; - - emmc_pins_uhs: emmc-pins-uhs { - mux { - function = "emmc"; - groups = "emmc"; - }; - - conf-cmd-dat { - pins = "NDL0", "NDL1", "NDL2", - "NDL3", "NDL4", "NDL5", - "NDL6", "NDL7", "NRB"; - input-enable; - drive-strength = <4>; - bias-pull-up; - }; - - conf-clk { - pins = "NCLE"; - drive-strength = <4>; - bias-pull-down; - }; - }; - - eth_pins: eth-pins { - mux { - function = "eth"; - groups = "mdc_mdio", "rgmii_via_gmac2"; - }; - }; - - i2c1_pins: i2c1-pins { - mux { - function = "i2c"; - groups = "i2c1_0"; - }; - }; - - i2c2_pins: i2c2-pins { - mux { - function = "i2c"; - groups = "i2c2_0"; - }; - }; - - i2s1_pins: i2s1-pins { - mux { - function = "i2s"; - groups = "i2s_out_mclk_bclk_ws", - "i2s1_in_data", - "i2s1_out_data"; - }; - - conf { - pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK", - "I2S_WS", "I2S_MCLK"; - drive-strength = <12>; - bias-pull-down; - }; - }; - - irrx_pins: irrx-pins { - mux { - function = "ir"; - groups = "ir_1_rx"; - }; - }; - - irtx_pins: irtx-pins { - mux { - function = "ir"; - groups = "ir_1_tx"; - }; - }; - - /* Parallel nand is shared pin with eMMC */ - parallel_nand_pins: parallel-nand-pins { - mux { - function = "flash"; - groups = "par_nand"; - }; - }; - - pcie0_pins: pcie0-pins { - mux { - function = "pcie"; - groups = "pcie0_pad_perst", - "pcie0_1_waken", - "pcie0_1_clkreq"; - }; - }; - - pcie1_pins: pcie1-pins { - mux { - function = "pcie"; - groups = "pcie1_pad_perst", - "pcie1_0_waken", - "pcie1_0_clkreq"; - }; - }; - - pmic_bus_pins: pmic-bus-pins { - mux { - function = "pmic"; - groups = "pmic_bus"; - }; - }; - - pwm7_pins: pwm1-2-pins { - mux { - function = "pwm"; - groups = "pwm_ch7_2"; - }; - }; - - wled_pins: wled-pins { - mux { - function = "led"; - groups = "wled"; - }; - }; - - sd0_pins_default: sd0-pins-default { - mux { - function = "sd"; - groups = "sd_0"; - }; - - /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN", - * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1, - * DAT2, DAT3, CMD, CLK for SD respectively. - */ - conf-cmd-data { - pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", - "I2S2_IN","I2S4_OUT"; - input-enable; - drive-strength = <8>; - bias-pull-up; - }; - conf-clk { - pins = "I2S3_OUT"; - drive-strength = <12>; - bias-pull-down; - }; - conf-cd { - pins = "TXD3"; - bias-pull-up; - }; - }; - - sd0_pins_uhs: sd0-pins-uhs { - mux { - function = "sd"; - groups = "sd_0"; - }; - - conf-cmd-data { - pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", - "I2S2_IN","I2S4_OUT"; - input-enable; - bias-pull-up; - }; - - conf-clk { - pins = "I2S3_OUT"; - bias-pull-down; - }; - }; - - /* Serial NAND is shared pin with SPI-NOR */ - serial_nand_pins: serial-nand-pins { - mux { - function = "flash"; - groups = "snfi"; - }; - }; - - spic0_pins: spic0-pins { - mux { - function = "spi"; - groups = "spic0_0"; - }; - }; - - spic1_pins: spic1-pins { - mux { - function = "spi"; - groups = "spic1_0"; - }; - }; - - /* SPI-NOR is shared pin with serial NAND */ - spi_nor_pins: spi-nor-pins { - mux { - function = "flash"; - groups = "spi_nor"; - }; - }; - - /* serial NAND is shared pin with SPI-NOR */ - serial_nand_pins: serial-nand-pins { - mux { - function = "flash"; - groups = "snfi"; - }; - }; - - uart0_pins: uart0-pins { - mux { - function = "uart"; - groups = "uart0_0_tx_rx" ; - }; - }; - - uart2_pins: uart2-pins { - mux { - function = "uart"; - groups = "uart2_1_tx_rx" ; - }; - }; - - watchdog_pins: watchdog-pins { - mux { - function = "watchdog"; - groups = "watchdog"; - }; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm7_pins>; - status = "okay"; -}; - -&pwrap { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_bus_pins>; - - status = "okay"; -}; - -&sata { - status = "disable"; -}; - -&sata_phy { - status = "disable"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spic0_pins>; - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spic1_pins>; - status = "okay"; -}; - -&ssusb { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&u3phy { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&watchdog { - pinctrl-names = "default"; - pinctrl-0 = <&watchdog_pins>; - status = "okay"; -}; - -&wmac { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts deleted file mode 100644 index 08ad0ffb2..000000000 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ /dev/null @@ -1,563 +0,0 @@ -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: Ming Huang - * Sean Wang - * - * SPDX-License-Identifier: (GPL-2.0 OR MIT) - */ - -/dts-v1/; -#include -#include - -#include "mt7622.dtsi" -#include "mt6380.dtsi" - -/ { - model = "MediaTek MT7622 RFB1 board"; - compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; - }; - - cpus { - cpu@0 { - proc-supply = <&mt6380_vcpu_reg>; - sram-supply = <&mt6380_vm_reg>; - }; - - cpu@1 { - proc-supply = <&mt6380_vcpu_reg>; - sram-supply = <&mt6380_vm_reg>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - poll-interval = <100>; - - factory { - label = "factory"; - linux,code = ; - gpios = <&pio 0 0>; - }; - - wps { - label = "wps"; - linux,code = ; - gpios = <&pio 102 0>; - }; - }; - - memory { - reg = <0 0x40000000 0 0x20000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&bch { - status = "disabled"; -}; - -&btif { - status = "okay"; -}; - -&cir { - pinctrl-names = "default"; - pinctrl-0 = <&irrx_pins>; - status = "okay"; -}; - -ð { - pinctrl-names = "default"; - pinctrl-0 = <ð_pins>; - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - switch@0 { - compatible = "mediatek,mt7531"; - reg = <0>; - reset-gpios = <&pio 54 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan0"; - }; - - port@1 { - reg = <1>; - label = "lan1"; - }; - - port@2 { - reg = <2>; - label = "lan2"; - }; - - port@3 { - reg = <3>; - label = "lan3"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@6 { - reg = <6>; - label = "cpu"; - ethernet = <&gmac0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - }; - }; - - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&emmc_pins_default>; - pinctrl-1 = <&emmc_pins_uhs>; - status = "okay"; - bus-width = <8>; - max-frequency = <50000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; - non-removable; -}; - -&mmc1 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&sd0_pins_default>; - pinctrl-1 = <&sd0_pins_uhs>; - status = "okay"; - bus-width = <4>; - max-frequency = <50000000>; - cap-sd-highspeed; - r_smpl = <1>; - cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_3p3v>; - assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; -}; - -&nandc { - pinctrl-names = "default"; - pinctrl-0 = <¶llel_nand_pins>; - status = "disabled"; -}; - -&nor_flash { - pinctrl-names = "default"; - pinctrl-0 = <&spi_nor_pins>; - status = "disabled"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pins>; - status = "okay"; - - pcie@0,0 { - status = "okay"; - }; -}; - -&pio { - /* eMMC is shared pin with parallel NAND */ - emmc_pins_default: emmc-pins-default { - mux { - function = "emmc", "emmc_rst"; - groups = "emmc"; - }; - - /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", - * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, - * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively - */ - conf-cmd-dat { - pins = "NDL0", "NDL1", "NDL2", - "NDL3", "NDL4", "NDL5", - "NDL6", "NDL7", "NRB"; - input-enable; - bias-pull-up; - }; - - conf-clk { - pins = "NCLE"; - bias-pull-down; - }; - }; - - emmc_pins_uhs: emmc-pins-uhs { - mux { - function = "emmc"; - groups = "emmc"; - }; - - conf-cmd-dat { - pins = "NDL0", "NDL1", "NDL2", - "NDL3", "NDL4", "NDL5", - "NDL6", "NDL7", "NRB"; - input-enable; - drive-strength = <4>; - bias-pull-up; - }; - - conf-clk { - pins = "NCLE"; - drive-strength = <4>; - bias-pull-down; - }; - }; - - eth_pins: eth-pins { - mux { - function = "eth"; - groups = "mdc_mdio", "rgmii_via_gmac2"; - }; - }; - - i2c1_pins: i2c1-pins { - mux { - function = "i2c"; - groups = "i2c1_0"; - }; - }; - - i2c2_pins: i2c2-pins { - mux { - function = "i2c"; - groups = "i2c2_0"; - }; - }; - - i2s1_pins: i2s1-pins { - mux { - function = "i2s"; - groups = "i2s_out_mclk_bclk_ws", - "i2s1_in_data", - "i2s1_out_data"; - }; - - conf { - pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK", - "I2S_WS", "I2S_MCLK"; - drive-strength = <12>; - bias-pull-down; - }; - }; - - irrx_pins: irrx-pins { - mux { - function = "ir"; - groups = "ir_1_rx"; - }; - }; - - irtx_pins: irtx-pins { - mux { - function = "ir"; - groups = "ir_1_tx"; - }; - }; - - /* Parallel nand is shared pin with eMMC */ - parallel_nand_pins: parallel-nand-pins { - mux { - function = "flash"; - groups = "par_nand"; - }; - }; - - pcie0_pins: pcie0-pins { - mux { - function = "pcie"; - groups = "pcie0_pad_perst", - "pcie0_1_waken", - "pcie0_1_clkreq"; - }; - }; - - pcie1_pins: pcie1-pins { - mux { - function = "pcie"; - groups = "pcie1_pad_perst", - "pcie1_0_waken", - "pcie1_0_clkreq"; - }; - }; - - pmic_bus_pins: pmic-bus-pins { - mux { - function = "pmic"; - groups = "pmic_bus"; - }; - }; - - pwm7_pins: pwm1-2-pins { - mux { - function = "pwm"; - groups = "pwm_ch7_2"; - }; - }; - - wled_pins: wled-pins { - mux { - function = "led"; - groups = "wled"; - }; - }; - - sd0_pins_default: sd0-pins-default { - mux { - function = "sd"; - groups = "sd_0"; - }; - - /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN", - * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1, - * DAT2, DAT3, CMD, CLK for SD respectively. - */ - conf-cmd-data { - pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", - "I2S2_IN","I2S4_OUT"; - input-enable; - drive-strength = <8>; - bias-pull-up; - }; - conf-clk { - pins = "I2S3_OUT"; - drive-strength = <12>; - bias-pull-down; - }; - conf-cd { - pins = "TXD3"; - bias-pull-up; - }; - }; - - sd0_pins_uhs: sd0-pins-uhs { - mux { - function = "sd"; - groups = "sd_0"; - }; - - conf-cmd-data { - pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", - "I2S2_IN","I2S4_OUT"; - input-enable; - bias-pull-up; - }; - - conf-clk { - pins = "I2S3_OUT"; - bias-pull-down; - }; - }; - - /* Serial NAND is shared pin with SPI-NOR */ - serial_nand_pins: serial-nand-pins { - mux { - function = "flash"; - groups = "snfi"; - }; - }; - - spic0_pins: spic0-pins { - mux { - function = "spi"; - groups = "spic0_0"; - }; - }; - - spic1_pins: spic1-pins { - mux { - function = "spi"; - groups = "spic1_0"; - }; - }; - - /* SPI-NOR is shared pin with serial NAND */ - spi_nor_pins: spi-nor-pins { - mux { - function = "flash"; - groups = "spi_nor"; - }; - }; - - /* serial NAND is shared pin with SPI-NOR */ - serial_nand_pins: serial-nand-pins { - mux { - function = "flash"; - groups = "snfi"; - }; - }; - - uart0_pins: uart0-pins { - mux { - function = "uart"; - groups = "uart0_0_tx_rx" ; - }; - }; - - uart2_pins: uart2-pins { - mux { - function = "uart"; - groups = "uart2_1_tx_rx" ; - }; - }; - - watchdog_pins: watchdog-pins { - mux { - function = "watchdog"; - groups = "watchdog"; - }; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm7_pins>; - status = "okay"; -}; - -&pwrap { - pinctrl-names = "default"; - pinctrl-0 = <&pmic_bus_pins>; - - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&sata_phy { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spic0_pins>; - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spic1_pins>; - status = "okay"; -}; - -&ssusb { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&u3phy { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&watchdog { - pinctrl-names = "default"; - pinctrl-0 = <&watchdog_pins>; - status = "okay"; -}; - -&wmac { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi deleted file mode 100644 index 7c6d87153..000000000 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ /dev/null @@ -1,950 +0,0 @@ -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: Ming Huang - * Sean Wang - * - * SPDX-License-Identifier: (GPL-2.0 OR MIT) - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "mediatek,mt7622"; - interrupt-parent = <&sysirq>; - #address-cells = <2>; - #size-cells = <2>; - - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - opp-300000000 { - opp-hz = /bits/ 64 <30000000>; - opp-microvolt = <950000>; - }; - - opp-437500000 { - opp-hz = /bits/ 64 <437500000>; - opp-microvolt = <1000000>; - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1050000>; - }; - - opp-812500000 { - opp-hz = /bits/ 64 <812500000>; - opp-microvolt = <1100000>; - }; - - opp-1025000000 { - opp-hz = /bits/ 64 <1025000000>; - opp-microvolt = <1150000>; - }; - - opp-1137500000 { - opp-hz = /bits/ 64 <1137500000>; - opp-microvolt = <1200000>; - }; - - opp-1262500000 { - opp-hz = /bits/ 64 <1262500000>; - opp-microvolt = <1250000>; - }; - - opp-1350000000 { - opp-hz = /bits/ 64 <1350000000>; - opp-microvolt = <1310000>; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - clocks = <&infracfg CLK_INFRA_MUX1_SEL>, - <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - enable-method = "psci"; - clock-frequency = <1300000000>; - cci-control-port = <&cci_control2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - clocks = <&infracfg CLK_INFRA_MUX1_SEL>, - <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - enable-method = "psci"; - clock-frequency = <1300000000>; - cci-control-port = <&cci_control2>; - }; - }; - - pwrap_clk: dummy40m { - compatible = "fixed-clock"; - clock-frequency = <40000000>; - #clock-cells = <0>; - }; - - clk25m: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "clkxtal"; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; - no-map; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = <&thermal 0>; - - trips { - cpu_passive: cpu-passive { - temperature = <47000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_active: cpu-active { - temperature = <67000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_hot: cpu-hot { - temperature = <87000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu-crit { - temperature = <107000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map1 { - trip = <&cpu_active>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - - map2 { - trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - infracfg: infracfg@10000000 { - compatible = "mediatek,mt7622-infracfg", - "syscon"; - reg = <0 0x10000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pwrap: pwrap@10001000 { - compatible = "mediatek,mt7622-pwrap"; - reg = <0 0x10001000 0 0x250>; - reg-names = "pwrap"; - clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>; - clock-names = "spi", "wrap"; - resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>; - reset-names = "pwrap"; - interrupts = ; - status = "disabled"; - }; - - pericfg: pericfg@10002000 { - compatible = "mediatek,mt7622-pericfg", - "syscon"; - reg = <0 0x10002000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - scpsys: power-controller@10006000 { - compatible = "mediatek,mt7622-scpsys", - "syscon"; - #power-domain-cells = <1>; - reg = <0 0x10006000 0 0x1000>; - interrupts = , - , - , - ; - infracfg = <&infracfg>; - clocks = <&topckgen CLK_TOP_HIF_SEL>; - clock-names = "hif_sel"; - }; - - cir: cir@10009000 { - compatible = "mediatek,mt7622-cir"; - reg = <0 0x10009000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_IRRX_PD>, - <&topckgen CLK_TOP_AXI_SEL>; - clock-names = "clk", "bus"; - status = "disabled"; - }; - - sysirq: interrupt-controller@10200620 { - compatible = "mediatek,mt7622-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200620 0 0x20>; - }; - - efuse: efuse@10206000 { - compatible = "mediatek,mt7622-efuse", - "mediatek,efuse"; - reg = <0 0x10206000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - thermal_calibration: calib@198 { - reg = <0x198 0xc>; - }; - }; - - apmixedsys: apmixedsys@10209000 { - compatible = "mediatek,mt7622-apmixedsys", - "syscon"; - reg = <0 0x10209000 0 0x1000>; - #clock-cells = <1>; - }; - - topckgen: topckgen@10210000 { - compatible = "mediatek,mt7622-topckgen", - "syscon"; - reg = <0 0x10210000 0 0x1000>; - #clock-cells = <1>; - }; - - rng: rng@1020f000 { - compatible = "mediatek,mt7622-rng", - "mediatek,mt7623-rng"; - reg = <0 0x1020f000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_TRNG>; - clock-names = "rng"; - }; - - pio: pinctrl@10211000 { - compatible = "mediatek,mt7622-pinctrl"; - reg = <0 0x10211000 0 0x1000>, - <0 0x10005000 0 0x1000>; - reg-names = "base", "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 103>; - interrupt-controller; - interrupts = ; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - }; - - watchdog: watchdog@10212000 { - compatible = "mediatek,mt7622-wdt", - "mediatek,mt6589-wdt"; - reg = <0 0x10212000 0 0x800>; - }; - - rtc: rtc@10212800 { - compatible = "mediatek,mt7622-rtc", - "mediatek,soc-rtc"; - reg = <0 0x10212800 0 0x200>; - interrupts = ; - clocks = <&topckgen CLK_TOP_RTC>; - clock-names = "rtc"; - }; - - gic: interrupt-controller@10300000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10310000 0 0x1000>, - <0 0x10320000 0 0x1000>, - <0 0x10340000 0 0x2000>, - <0 0x10360000 0 0x2000>; - }; - - cci: cci@10390000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0x10390000 0 0x1000>; - ranges = <0 0 0x10390000 0x10000>; - - cci_control0: slave-if@1000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace-lite"; - reg = <0x1000 0x1000>; - }; - - cci_control1: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - - cci_control2: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - - pmu@9000 { - compatible = "arm,cci-400-pmu,r1"; - reg = <0x9000 0x5000>; - interrupts = , - , - , - , - ; - }; - }; - - auxadc: adc@11001000 { - compatible = "mediatek,mt7622-auxadc"; - reg = <0 0x11001000 0 0x1000>; - clocks = <&pericfg CLK_PERI_AUXADC_PD>; - clock-names = "main"; - #io-channel-cells = <1>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt7622-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&pericfg CLK_PERI_UART0_PD>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt7622-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&pericfg CLK_PERI_UART1_PD>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt7622-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&pericfg CLK_PERI_UART2_PD>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt7622-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11005000 0 0x400>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&pericfg CLK_PERI_UART3_PD>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - pwm: pwm@11006000 { - compatible = "mediatek,mt7622-pwm"; - reg = <0 0x11006000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_PWM_SEL>, - <&pericfg CLK_PERI_PWM_PD>, - <&pericfg CLK_PERI_PWM1_PD>, - <&pericfg CLK_PERI_PWM2_PD>, - <&pericfg CLK_PERI_PWM3_PD>, - <&pericfg CLK_PERI_PWM4_PD>, - <&pericfg CLK_PERI_PWM5_PD>, - <&pericfg CLK_PERI_PWM6_PD>; - clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4", - "pwm5", "pwm6"; - status = "disabled"; - }; - - i2c0: i2c@11007000 { - compatible = "mediatek,mt7622-i2c"; - reg = <0 0x11007000 0 0x90>, - <0 0x11000100 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C0_PD>, - <&pericfg CLK_PERI_AP_DMA_PD>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@11008000 { - compatible = "mediatek,mt7622-i2c"; - reg = <0 0x11008000 0 0x90>, - <0 0x11000180 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C1_PD>, - <&pericfg CLK_PERI_AP_DMA_PD>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@11009000 { - compatible = "mediatek,mt7622-i2c"; - reg = <0 0x11009000 0 0x90>, - <0 0x11000200 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C2_PD>, - <&pericfg CLK_PERI_AP_DMA_PD>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@1100a000 { - compatible = "mediatek,mt7622-spi"; - reg = <0 0x1100a000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, - <&topckgen CLK_TOP_SPI0_SEL>, - <&pericfg CLK_PERI_SPI0_PD>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - thermal: thermal@1100b000 { - #thermal-sensor-cells = <1>; - compatible = "mediatek,mt7622-thermal"; - reg = <0 0x1100b000 0 0x1000>; - interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>; - clocks = <&pericfg CLK_PERI_THERM_PD>, - <&pericfg CLK_PERI_AUXADC_PD>; - clock-names = "therm", "auxadc"; - resets = <&pericfg MT7622_PERI_THERM_SW_RST>; - reset-names = "therm"; - mediatek,auxadc = <&auxadc>; - mediatek,apmixedsys = <&apmixedsys>; - nvmem-cells = <&thermal_calibration>; - nvmem-cell-names = "calibration-data"; - }; - - btif: serial@1100c000 { - compatible = "mediatek,mt7622-btif", - "mediatek,mtk-btif"; - reg = <0 0x1100c000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_BTIF_PD>; - clock-names = "main"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - - bluetooth { - compatible = "mediatek,mt7622-bluetooth"; - power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>; - clocks = <&clk25m>; - clock-names = "ref"; - }; - }; - - nandc: nfi@1100d000 { - compatible = "mediatek,mt7622-nfc"; - reg = <0 0x1100D000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_NFI_PD>, - <&pericfg CLK_PERI_SNFI_PD>; - clock-names = "nfi_clk", "pad_clk"; - ecc-engine = <&bch>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - bch: ecc@1100e000 { - compatible = "mediatek,mt7622-ecc"; - reg = <0 0x1100e000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_NFIECC_PD>; - clock-names = "nfiecc_clk"; - status = "disabled"; - }; - - nor_flash: spi@11014000 { - compatible = "mediatek,mt7622-nor", - "mediatek,mt8173-nor"; - reg = <0 0x11014000 0 0xe0>; - clocks = <&pericfg CLK_PERI_FLASH_PD>, - <&topckgen CLK_TOP_FLASH_SEL>; - clock-names = "spi", "sf"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@11016000 { - compatible = "mediatek,mt7622-spi"; - reg = <0 0x11016000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, - <&topckgen CLK_TOP_SPI1_SEL>, - <&pericfg CLK_PERI_SPI1_PD>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart4: serial@11019000 { - compatible = "mediatek,mt7622-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11019000 0 0x400>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&pericfg CLK_PERI_UART4_PD>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - audsys: clock-controller@11220000 { - compatible = "mediatek,mt7622-audsys", "syscon"; - reg = <0 0x11220000 0 0x2000>; - #clock-cells = <1>; - - afe: audio-controller { - compatible = "mediatek,mt7622-audio"; - interrupts = , - ; - interrupt-names = "afe", "asys"; - - clocks = <&infracfg CLK_INFRA_AUDIO_PD>, - <&topckgen CLK_TOP_AUD1_SEL>, - <&topckgen CLK_TOP_AUD2_SEL>, - <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>, - <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>, - <&topckgen CLK_TOP_I2S0_MCK_SEL>, - <&topckgen CLK_TOP_I2S1_MCK_SEL>, - <&topckgen CLK_TOP_I2S2_MCK_SEL>, - <&topckgen CLK_TOP_I2S3_MCK_SEL>, - <&topckgen CLK_TOP_I2S0_MCK_DIV>, - <&topckgen CLK_TOP_I2S1_MCK_DIV>, - <&topckgen CLK_TOP_I2S2_MCK_DIV>, - <&topckgen CLK_TOP_I2S3_MCK_DIV>, - <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>, - <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>, - <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>, - <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>, - <&audsys CLK_AUDIO_I2SO1>, - <&audsys CLK_AUDIO_I2SO2>, - <&audsys CLK_AUDIO_I2SO3>, - <&audsys CLK_AUDIO_I2SO4>, - <&audsys CLK_AUDIO_I2SIN1>, - <&audsys CLK_AUDIO_I2SIN2>, - <&audsys CLK_AUDIO_I2SIN3>, - <&audsys CLK_AUDIO_I2SIN4>, - <&audsys CLK_AUDIO_ASRCO1>, - <&audsys CLK_AUDIO_ASRCO2>, - <&audsys CLK_AUDIO_ASRCO3>, - <&audsys CLK_AUDIO_ASRCO4>, - <&audsys CLK_AUDIO_AFE>, - <&audsys CLK_AUDIO_AFE_CONN>, - <&audsys CLK_AUDIO_A1SYS>, - <&audsys CLK_AUDIO_A2SYS>; - - clock-names = "infra_sys_audio_clk", - "top_audio_mux1_sel", - "top_audio_mux2_sel", - "top_audio_a1sys_hp", - "top_audio_a2sys_hp", - "i2s0_src_sel", - "i2s1_src_sel", - "i2s2_src_sel", - "i2s3_src_sel", - "i2s0_src_div", - "i2s1_src_div", - "i2s2_src_div", - "i2s3_src_div", - "i2s0_mclk_en", - "i2s1_mclk_en", - "i2s2_mclk_en", - "i2s3_mclk_en", - "i2so0_hop_ck", - "i2so1_hop_ck", - "i2so2_hop_ck", - "i2so3_hop_ck", - "i2si0_hop_ck", - "i2si1_hop_ck", - "i2si2_hop_ck", - "i2si3_hop_ck", - "asrc0_out_ck", - "asrc1_out_ck", - "asrc2_out_ck", - "asrc3_out_ck", - "audio_afe_pd", - "audio_afe_conn_pd", - "audio_a1sys_pd", - "audio_a2sys_pd"; - - assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>, - <&topckgen CLK_TOP_A2SYS_HP_SEL>, - <&topckgen CLK_TOP_A1SYS_HP_DIV>, - <&topckgen CLK_TOP_A2SYS_HP_DIV>; - assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>, - <&topckgen CLK_TOP_AUD2PLL>; - assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; - }; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt7622-mmc"; - reg = <0 0x11230000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_MSDC30_0_PD>, - <&topckgen CLK_TOP_MSDC50_0_SEL>; - clock-names = "source", "hclk"; - resets = <&pericfg MT7622_PERI_MSDC0_SW_RST>; - reset-names = "hrst"; - status = "disabled"; - }; - - mmc1: mmc@11240000 { - compatible = "mediatek,mt7622-mmc"; - reg = <0 0x11240000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_MSDC30_1_PD>, - <&topckgen CLK_TOP_AXI_SEL>; - clock-names = "source", "hclk"; - resets = <&pericfg MT7622_PERI_MSDC1_SW_RST>; - reset-names = "hrst"; - status = "disabled"; - }; - - wmac: wmac@18000000 { - compatible = "mediatek,mt7622-wmac"; - reg = <0 0x18000000 0 0x100000>; - interrupts = ; - - mediatek,infracfg = <&infracfg>; - status = "disabled"; - - power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>; - }; - - ssusbsys: ssusbsys@1a000000 { - compatible = "mediatek,mt7622-ssusbsys", - "syscon"; - reg = <0 0x1a000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - ssusb: usb@1a0c0000 { - compatible = "mediatek,mt7622-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x1a0c0000 0 0x01000>, - <0 0x1a0c4700 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>; - clocks = <&ssusbsys CLK_SSUSB_SYS_EN>, - <&ssusbsys CLK_SSUSB_REF_EN>, - <&ssusbsys CLK_SSUSB_MCU_EN>, - <&ssusbsys CLK_SSUSB_DMA_EN>; - clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; - phys = <&u2port0 PHY_TYPE_USB2>, - <&u3port0 PHY_TYPE_USB3>, - <&u2port1 PHY_TYPE_USB2>; - - status = "disabled"; - }; - - u3phy: usb-phy@1a0c4000 { - compatible = "mediatek,mt7622-u3phy", - "mediatek,generic-tphy-v1"; - reg = <0 0x1a0c4000 0 0x700>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - u2port0: usb-phy@1a0c4800 { - reg = <0 0x1a0c4800 0 0x0100>; - #phy-cells = <1>; - clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>; - clock-names = "ref"; - }; - - u3port0: usb-phy@1a0c4900 { - reg = <0 0x1a0c4900 0 0x0700>; - #phy-cells = <1>; - clocks = <&clk25m>; - clock-names = "ref"; - }; - - u2port1: usb-phy@1a0c5000 { - reg = <0 0x1a0c5000 0 0x0100>; - #phy-cells = <1>; - clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>; - clock-names = "ref"; - }; - }; - - pciesys: pciesys@1a100800 { - compatible = "mediatek,mt7622-pciesys", - "syscon"; - reg = <0 0x1a100800 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pcie: pcie@1a140000 { - compatible = "mediatek,mt7622-pcie"; - device_type = "pci"; - reg = <0 0x1a140000 0 0x1000>, - <0 0x1a143000 0 0x1000>, - <0 0x1a145000 0 0x1000>; - reg-names = "subsys", "port0", "port1"; - #address-cells = <3>; - #size-cells = <2>; - interrupts = , - ; - clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, - <&pciesys CLK_PCIE_P1_MAC_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P0_AUX_EN>, - <&pciesys CLK_PCIE_P1_AUX_EN>, - <&pciesys CLK_PCIE_P0_AXI_EN>, - <&pciesys CLK_PCIE_P1_AXI_EN>, - <&pciesys CLK_PCIE_P0_OBFF_EN>, - <&pciesys CLK_PCIE_P1_OBFF_EN>, - <&pciesys CLK_PCIE_P0_PIPE_EN>, - <&pciesys CLK_PCIE_P1_PIPE_EN>; - clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1", - "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1", - "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1"; - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; - status = "disabled"; - - pcie0: pcie@0,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - status = "disabled"; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - pcie1: pcie@1,0 { - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - status = "disabled"; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - }; - - sata: sata@1a200000 { - compatible = "mediatek,mt7622-ahci", - "mediatek,mtk-ahci"; - reg = <0 0x1a200000 0 0x1100>; - interrupts = ; - interrupt-names = "hostc"; - clocks = <&pciesys CLK_SATA_AHB_EN>, - <&pciesys CLK_SATA_AXI_EN>, - <&pciesys CLK_SATA_ASIC_EN>, - <&pciesys CLK_SATA_RBC_EN>, - <&pciesys CLK_SATA_PM_EN>; - clock-names = "ahb", "axi", "asic", "rbc", "pm"; - phys = <&sata_port PHY_TYPE_SATA>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, - <&pciesys MT7622_SATA_PHY_SW_RST>, - <&pciesys MT7622_SATA_PHY_REG_RST>; - reset-names = "axi", "sw", "reg"; - mediatek,phy-mode = <&pciesys>; - status = "disabled"; - }; - - sata_phy: sata-phy@1a243000 { - compatible = "mediatek,generic-tphy-v1"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - sata_port: sata-phy@1a243000 { - reg = <0 0x1a243000 0 0x0100>; - clocks = <&topckgen CLK_TOP_ETH_500M>; - clock-names = "ref"; - #phy-cells = <1>; - }; - }; - - ethsys: syscon@1b000000 { - compatible = "mediatek,mt7622-ethsys", - "syscon"; - reg = <0 0x1b000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - hsdma: dma-controller@1b007000 { - compatible = "mediatek,mt7622-hsdma"; - reg = <0 0x1b007000 0 0x1000>; - interrupts = ; - clocks = <ðsys CLK_ETH_HSDMA_EN>; - clock-names = "hsdma"; - power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; - #dma-cells = <1>; - }; - - eth: ethernet@1b100000 { - compatible = "mediatek,mt7622-eth", - "mediatek,mt2701-eth", - "syscon"; - reg = <0 0x1b100000 0 0x20000>; - interrupts = , - , - ; - clocks = <&topckgen CLK_TOP_ETH_SEL>, - <ðsys CLK_ETH_ESW_EN>, - <ðsys CLK_ETH_GP0_EN>, - <ðsys CLK_ETH_GP1_EN>, - <ðsys CLK_ETH_GP2_EN>, - <&sgmiisys CLK_SGMII_TX250M_EN>, - <&sgmiisys CLK_SGMII_RX250M_EN>, - <&sgmiisys CLK_SGMII_CDR_REF>, - <&sgmiisys CLK_SGMII_CDR_FB>, - <&topckgen CLK_TOP_SGMIIPLL>, - <&apmixedsys CLK_APMIXED_ETH2PLL>; - clock-names = "ethif", "esw", "gp0", "gp1", "gp2", - "sgmii_tx250m", "sgmii_rx250m", - "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", - "eth2pll"; - power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; - mediatek,ethsys = <ðsys>; - mediatek,sgmiisys = <&sgmiisys>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sgmiisys: sgmiisys@1b128000 { - compatible = "mediatek,mt7622-sgmiisys", - "syscon"; - reg = <0 0x1b128000 0 0x3000>; - #clock-cells = <1>; - }; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts deleted file mode 100644 index 44f6149c1..000000000 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2019 MediaTek Inc. - */ - -/dts-v1/; -#include "mt8173-elm-hana.dtsi" - -/ { - model = "Google Hanawl"; - compatible = "google,hana-rev7", "mediatek,mt8173"; -}; - -&cpu_thermal { - trips { - cpu_crit: cpu_crit0 { - temperature = <100000>; - type = "critical"; - }; - }; -}; - -&gpio_keys { - /delete-node/tablet_mode; - /delete-node/volume_down; - /delete-node/volume_up; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts deleted file mode 100644 index c23429675..000000000 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2016 MediaTek Inc. - */ - -/dts-v1/; -#include "mt8173-elm-hana.dtsi" - -/ { - model = "Google Hana"; - compatible = "google,hana-rev6", "google,hana-rev5", - "google,hana-rev4", "google,hana-rev3", - "google,hana", "mediatek,mt8173"; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi deleted file mode 100644 index bdcd35cec..000000000 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2016 MediaTek Inc. - */ - -#include "mt8173-elm.dtsi" - -&i2c0 { - clock-frequency = <200000>; -}; - -&i2c3 { - touchscreen2: touchscreen@34 { - compatible = "melfas,mip4_ts"; - reg = <0x34>; - interrupt-parent = <&pio>; - interrupts = <88 IRQ_TYPE_LEVEL_LOW>; - }; - - /* - * Lenovo 100e Chromebook 2nd Gen (MTK) and Lenovo 300e Chromebook 2nd - * Gen (MTK) are using synaptics touchscreen (hid-over-i2c driver) as a - * second source touchscreen. - */ - touchscreen3: touchscreen@20 { - compatible = "hid-over-i2c"; - reg = <0x20>; - hid-descr-addr = <0x0020>; - interrupt-parent = <&pio>; - interrupts = <88 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c4 { - /* - * Lenovo 100e Chromebook 2nd Gen (MTK) and Lenovo 300e Chromebook 2nd - * Gen (MTK) are using synaptics trackpad (hid-over-i2c driver) as a - * second source trackpad. - */ - trackpad2: trackpad@2c { - compatible = "hid-over-i2c"; - interrupt-parent = <&pio>; - interrupts = <117 IRQ_TYPE_LEVEL_LOW>; - reg = <0x2c>; - hid-descr-addr = <0x0020>; - wakeup-source; - }; -}; - -&mmc1 { - wp-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; -}; - -&pio { - hdmi_mux_pins: hdmi_mux_pins { - pins2 { - pinmux = ; - bias-pull-up; - output-high; - }; - }; - - mmc1_pins_default: mmc1default { - pins_wp { - pinmux = ; - input-enable; - bias-pull-up; - }; - }; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dts b/arch/arm64/boot/dts/mediatek/mt8173-elm.dts deleted file mode 100644 index e9e4ac0b7..000000000 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2016 MediaTek Inc. - */ - -/dts-v1/; -#include "mt8173-elm.dtsi" - -/ { - model = "Google Elm"; - compatible = "google,elm-rev8", "google,elm-rev7", "google,elm-rev6", - "google,elm-rev5", "google,elm-rev4", "google,elm-rev3", - "google,elm", "mediatek,mt8173"; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi deleted file mode 100644 index 44a034613..000000000 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ /dev/null @@ -1,1174 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2016 MediaTek Inc. - */ - -#include -#include -#include -#include -#include "mt8173.dtsi" - -/ { - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x80000000>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm0 0 1000000>; - power-supply = <&bl_fixed_reg>; - enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&disp_pwm0_pins>; - status = "okay"; - }; - - bl_fixed_reg: fixedregulator2 { - compatible = "regulator-fixed"; - regulator-name = "bl_fixed"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <1000>; - enable-active-high; - gpio = <&pio 32 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_fixed_pins>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pins>; - - lid { - label = "Lid"; - gpios = <&pio 69 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - gpio-key,wakeup; - }; - - power { - label = "Power"; - gpios = <&pio 14 GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <30>; - gpio-key,wakeup; - }; - - tablet_mode { - label = "Tablet_mode"; - gpios = <&pio 121 GPIO_ACTIVE_HIGH>; - linux,code = ; - linux,input-type = ; - gpio-key,wakeup; - }; - - volume_down { - label = "Volume_down"; - gpios = <&pio 123 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume_up { - label = "Volume_up"; - gpios = <&pio 124 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - panel: panel { - compatible = "lg,lp120up1"; - power-supply = <&panel_fixed_3v3>; - ddc-i2c-bus = <&i2c0>; - backlight = <&backlight>; - - port { - panel_in: endpoint { - remote-endpoint = <&ps8640_out>; - }; - }; - }; - - panel_fixed_3v3: regulator1 { - compatible = "regulator-fixed"; - regulator-name = "PANEL_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pio 41 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&panel_fixed_pins>; - }; - - ps8640_fixed_1v2: regulator2 { - compatible = "regulator-fixed"; - regulator-name = "PS8640_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-enable-ramp-delay = <2000>; - enable-active-high; - regulator-boot-on; - gpio = <&pio 30 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&ps8640_fixed_pins>; - }; - - sdio_fixed_3v3: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pio 85 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_fixed_3v3_pins>; - }; - - sound: sound { - compatible = "mediatek,mt8173-rt5650"; - mediatek,audio-codec = <&rt5650 &hdmi0>; - mediatek,platform = <&afe>; - pinctrl-names = "default"; - pinctrl-0 = <&aud_i2s2>; - - mediatek,mclk = <1>; - codec-capture { - sound-dai = <&rt5650 1>; - }; - }; - - hdmicon: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - type = "a"; - ddc-i2c-bus = <&hdmiddc0>; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi0_out>; - }; - }; - }; -}; - -&cec { - status = "okay"; -}; - -&cpu0 { - proc-supply = <&mt6397_vpca15_reg>; -}; - -&cpu1 { - proc-supply = <&mt6397_vpca15_reg>; -}; - -&cpu2 { - proc-supply = <&da9211_vcpu_reg>; - sram-supply = <&mt6397_vsramca7_reg>; -}; - -&cpu3 { - proc-supply = <&da9211_vcpu_reg>; - sram-supply = <&mt6397_vsramca7_reg>; -}; - -&cpu_thermal { - sustainable-power = <4500>; /* milliwatts */ - trips { - threshold: trip-point0 { - temperature = <60000>; - }; - - target: trip-point1 { - temperature = <65000>; - }; - }; -}; - -&dsi0 { - status = "okay"; - ports { - port { - dsi0_out: endpoint { - remote-endpoint = <&ps8640_in>; - }; - }; - }; -}; - -&dpi0 { - status = "okay"; -}; - -&hdmi0 { - status = "okay"; - ports { - port@1 { - reg = <1>; - - hdmi0_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; -}; - -&hdmi_phy { - status = "okay"; - mediatek,ibias = <0xc>; -}; - -&i2c0 { - status = "okay"; - - rt5650: audio-codec@1a { - compatible = "realtek,rt5650"; - reg = <0x1a>; - avdd-supply = <&mt6397_vgp1_reg>; - cpvdd-supply = <&mt6397_vcama_reg>; - interrupt-parent = <&pio>; - interrupts = <3 IRQ_TYPE_EDGE_BOTH>; - pinctrl-names = "default"; - pinctrl-0 = <&rt5650_irq>; - #sound-dai-cells = <1>; - realtek,dmic1-data-pin = <2>; - realtek,jd-mode = <2>; - }; - - ps8640: edp-bridge@8 { - compatible = "parade,ps8640"; - reg = <0x8>; - powerdown-gpios = <&pio 127 GPIO_ACTIVE_LOW>; - reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ps8640_pins>; - vdd12-supply = <&ps8640_fixed_1v2>; - vdd33-supply = <&mt6397_vgp2_reg>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - ps8640_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - - ps8640_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; -}; - -&i2c1 { - clock-frequency = <1500000>; - status = "okay"; - - da9211: da9211@68 { - compatible = "dlg,da9211"; - reg = <0x68>; - interrupt-parent = <&pio>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - - regulators { - da9211_vcpu_reg: BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1310000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <4400000>; - regulator-ramp-delay = <10000>; - regulator-always-on; - regulator-allowed-modes = ; - }; - - da9211_vgpu_reg: BUCKB { - regulator-name = "VBUCKB"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1310000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <3000000>; - regulator-ramp-delay = <10000>; - }; - }; - }; -}; - -&i2c2 { - status = "okay"; - - tpm: tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - powered-while-suspended; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - status = "okay"; - - touchscreen: touchscreen@10 { - compatible = "elan,ekth3500"; - reg = <0x10>; - interrupt-parent = <&pio>; - interrupts = <88 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c4 { - clock-frequency = <400000>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&trackpad_irq>; - - trackpad: trackpad@15 { - compatible = "elan,ekth3000"; - interrupt-parent = <&pio>; - interrupts = <117 IRQ_TYPE_LEVEL_LOW>; - reg = <0x15>; - vcc-supply = <&mt6397_vgp6_reg>; - wakeup-source; - }; -}; - -&mipi_tx0 { - status = "okay"; -}; - -&mmc0 { - status = "okay"; - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - cap-mmc-hw-reset; - hs400-ds-delay = <0x14015>; - mediatek,hs200-cmd-int-delay=<30>; - mediatek,hs400-cmd-int-delay=<14>; - mediatek,hs400-cmd-resp-sel-rising; - vmmc-supply = <&mt6397_vemc_3v3_reg>; - vqmmc-supply = <&mt6397_vio18_reg>; - assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; - non-removable; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_uhs>; - bus-width = <4>; - max-frequency = <200000000>; - cap-sd-highspeed; - sd-uhs-sdr50; - sd-uhs-sdr104; - cd-gpios = <&pio 1 GPIO_ACTIVE_LOW>; - vmmc-supply = <&mt6397_vmch_reg>; - vqmmc-supply = <&mt6397_vmc_reg>; -}; - -&mmc3 { - status = "okay"; - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc3_pins_default>; - pinctrl-1 = <&mmc3_pins_uhs>; - bus-width = <4>; - max-frequency = <200000000>; - cap-sd-highspeed; - sd-uhs-sdr50; - sd-uhs-sdr104; - keep-power-in-suspend; - enable-sdio-wakeup; - cap-sdio-irq; - vmmc-supply = <&sdio_fixed_3v3>; - vqmmc-supply = <&mt6397_vgp3_reg>; - non-removable; - cap-power-off-card; - - #address-cells = <1>; - #size-cells = <0>; - - btmrvl: btmrvl@2 { - compatible = "marvell,sd8897-bt"; - reg = <2>; - interrupt-parent = <&pio>; - interrupts = <119 IRQ_TYPE_LEVEL_LOW>; - marvell,wakeup-pin = /bits/ 16 <0x0d>; - marvell,wakeup-gap-ms = /bits/ 16 <0x64>; - }; - - mwifiex: mwifiex@1 { - compatible = "marvell,sd8897"; - reg = <1>; - interrupt-parent = <&pio>; - interrupts = <38 IRQ_TYPE_LEVEL_LOW>; - marvell,wakeup-pin = <3>; - }; -}; - -&nor_flash { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nor_gpio1_pins>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - }; -}; - -&pio { - gpio-line-names = "EC_INT_1V8", - "SD_CD_L", - "ALC5514_IRQ", - "ALC5650_IRQ", - /* - * AP_FLASH_WP_L is crossystem ABI. Schematics - * call it SFWP_B. - */ - "AP_FLASH_WP_L", - "SFIN", - "SFCS0", - "SFHOLD", - "SFOUT", - "SFCK", - "WRAP_EVENT_S_EINT10", - "PMU_INT", - "I2S2_WS_ALC5650", - "I2S2_BCK_ALC5650", - "PWR_BTN_1V8", - "DA9212_IRQ", - "IDDIG", - "WATCHDOG", - "CEC", - "HDMISCK", - "HDMISD", - "HTPLG", - "MSDC3_DAT0", - "MSDC3_DAT1", - "MSDC3_DAT2", - "MSDC3_DAT3", - "MSDC3_CLK", - "MSDC3_CMD", - "USB_C0_OC_FLAGB", - "USBA_OC1_L", - "PS8640_1V2_ENABLE", - "THERM_ALERT_N", - "PANEL_LCD_POWER_EN", - "ANX7688_CHIP_PD_C", - "EC_IN_RW_1V8", - "ANX7688_1V_EN_C", - "USB_DP_HPD_C", - "TPM_DAVINT_N", - "MARVELL8897_IRQ", - "EN_USB_A0_PWR", - "USBA_A0_OC_L", - "EN_PP3300_DX_EDP", - "", - "SOC_I2C2_1V8_SDA_400K", - "SOC_I2C2_1V8_SCL_400K", - "SOC_I2C0_1V8_SDA_400K", - "SOC_I2C0_1V8_SCL_400K", - "EMMC_ID1", - "EMMC_ID0", - "MEM_CONFIG3", - "EMMC_ID2", - "MEM_CONFIG1", - "MEM_CONFIG2", - "BRD_ID2", - "MEM_CONFIG0", - "BRD_ID0", - "BRD_ID1", - "EMMC_DAT0", - "EMMC_DAT1", - "EMMC_DAT2", - "EMMC_DAT3", - "EMMC_DAT4", - "EMMC_DAT5", - "EMMC_DAT6", - "EMMC_DAT7", - "EMMC_CLK", - "EMMC_CMD", - "EMMC_RCLK", - "PLT_RST_L", - "LID_OPEN_1V8_L", - "AUDIO_SPI_MISO_R", - "", - "AC_OK_1V8", - "SD_DATA0", - "SD_DATA1", - "SD_DATA2", - "SD_DATA3", - "SD_CLK", - "SD_CMD", - "PWRAP_SPI0_MI", - "PWRAP_SPI0_MO", - "PWRAP_SPI0_CK", - "PWRAP_SPI0_CSN", - "", - "", - "WIFI_PDN", - "RTC32K_1V8", - "DISP_PWM0", - "TOUCHSCREEN_INT_L", - "", - "SRCLKENA0", - "SRCLKENA1", - "PS8640_MODE_CONF", - "TOUCHSCREEN_RESET_R", - "PLATFORM_PROCHOT_L", - "PANEL_POWER_EN", - "REC_MODE_L", - "EC_FW_UPDATE_L", - "ACCEL2_INT_L", - "HDMI_DP_INT", - "ACCELGYRO3_INT_L", - "ACCELGYRO4_INT_L", - "SPI_EC_CLK", - "SPI_EC_MI", - "SPI_EC_MO", - "SPI_EC_CSN", - "SOC_I2C3_1V8_SDA_400K", - "SOC_I2C3_1V8_SCL_400K", - "", - "", - "", - "", - "", - "", - "", - "PS8640_SYSRSTN_1V8", - "APIN_MAX98090_DOUT2", - "TP_INT_1V8_L_R", - "RST_USB_HUB_R", - "BT_WAKE_L", - "ACCEL1_INT_L", - "TABLET_MODE_L", - "", - "V_UP_IN_L_R", - "V_DOWN_IN_L_R", - "SOC_I2C1_1V8_SDA_1M", - "SOC_I2C1_1V8_SCL_1M", - "PS8640_PDN_1V8", - "MAX98090_LRCLK", - "MAX98090_BCLK", - "MAX98090_MCLK", - "APOUT_MAX98090_DIN", - "APIN_MAX98090_DOUT", - "SOC_I2C4_1V8_SDA_400K", - "SOC_I2C4_1V8_SCL_400K"; - - aud_i2s2: aud_i2s2 { - pins1 { - pinmux = , - , - , - , - , - , - ; - bias-pull-down; - }; - }; - - bl_fixed_pins: bl_fixed_pins { - pins1 { - pinmux = ; - output-low; - }; - }; - - bt_wake_pins: bt_wake_pins { - pins1 { - pinmux = ; - bias-pull-up; - }; - }; - - disp_pwm0_pins: disp_pwm0_pins { - pins1 { - pinmux = ; - output-low; - }; - }; - - gpio_keys_pins: gpio_keys_pins { - volume_pins { - pinmux = , - ; - bias-pull-up; - }; - - tablet_mode_pins { - pinmux = ; - bias-pull-up; - }; - }; - - hdmi_mux_pins: hdmi_mux_pins { - pins1 { - pinmux = ; - }; - }; - - i2c1_pins_a: i2c1 { - da9211_pins { - pinmux = ; - bias-pull-up; - }; - }; - - mmc0_pins_default: mmc0default { - pins_cmd_dat { - pinmux = , - , - , - , - , - , - , - , - ; - bias-pull-up; - }; - - pins_clk { - pinmux = ; - bias-pull-down; - }; - - pins_rst { - pinmux = ; - bias-pull-up; - }; - }; - - mmc1_pins_default: mmc1default { - pins_cmd_dat { - pinmux = , - , - , - , - ; - input-enable; - drive-strength = ; - bias-pull-up = ; - }; - - pins_clk { - pinmux = ; - bias-pull-down; - drive-strength = ; - }; - - pins_insert { - pinmux = ; - bias-pull-up; - }; - }; - - mmc3_pins_default: mmc3default { - pins_dat { - pinmux = , - , - , - ; - input-enable; - drive-strength = ; - bias-pull-up = ; - }; - - pins_cmd { - pinmux = ; - input-enable; - drive-strength = ; - bias-pull-up = ; - }; - - pins_clk { - pinmux = ; - bias-pull-down; - drive-strength = ; - }; - }; - - mmc0_pins_uhs: mmc0 { - pins_cmd_dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - drive-strength = ; - bias-pull-up = ; - }; - - pins_clk { - pinmux = ; - drive-strength = ; - bias-pull-down = ; - }; - - pins_ds { - pinmux = ; - drive-strength = ; - bias-pull-down = ; - }; - - pins_rst { - pinmux = ; - bias-pull-up; - }; - }; - - mmc1_pins_uhs: mmc1 { - pins_cmd_dat { - pinmux = , - , - , - , - ; - input-enable; - drive-strength = ; - bias-pull-up = ; - }; - - pins_clk { - pinmux = ; - drive-strength = ; - bias-pull-down = ; - }; - }; - - mmc3_pins_uhs: mmc3 { - pins_dat { - pinmux = , - , - , - ; - input-enable; - drive-strength = ; - bias-pull-up = ; - }; - - pins_cmd { - pinmux = ; - input-enable; - drive-strength = ; - bias-pull-up = ; - }; - - pins_clk { - pinmux = ; - drive-strength = ; - bias-pull-down = ; - }; - }; - - nor_gpio1_pins: nor { - pins1 { - pinmux = , - , - ; - input-enable; - drive-strength = ; - bias-pull-up; - }; - - pins2 { - pinmux = ; - drive-strength = ; - bias-pull-up; - }; - - pins_clk { - pinmux = ; - input-enable; - drive-strength = ; - bias-pull-up; - }; - }; - - panel_fixed_pins: panel_fixed_pins { - pins1 { - pinmux = ; - }; - }; - - ps8640_pins: ps8640_pins { - pins1 { - pinmux = , - , - ; - }; - }; - - ps8640_fixed_pins: ps8640_fixed_pins { - pins1 { - pinmux = ; - }; - }; - - rt5650_irq: rt5650_irq { - pins1 { - pinmux = ; - bias-pull-down; - }; - }; - - sdio_fixed_3v3_pins: sdio_fixed_3v3_pins { - pins1 { - pinmux = ; - output-low; - }; - }; - - spi_pins_a: spi1 { - pins1 { - pinmux = ; - bias-pull-up; - }; - - pins_spi { - pinmux = , - , - , - ; - bias-disable; - }; - }; - - trackpad_irq: trackpad_irq { - pins1 { - pinmux = ; - input-enable; - bias-pull-up; - }; - }; - - usb_pins: usb { - pins1 { - pinmux = ; - output-high; - bias-disable; - }; - }; - - wifi_wake_pins: wifi_wake_pins { - pins1 { - pinmux = ; - bias-pull-up; - }; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwrap { - pmic: mt6397 { - compatible = "mediatek,mt6397"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&pio>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - - clock: mt6397clock { - compatible = "mediatek,mt6397-clk"; - #clock-cells = <1>; - }; - - pio6397: pinctrl { - compatible = "mediatek,mt6397-pinctrl"; - pins-are-numbered; - gpio-controller; - #gpio-cells = <2>; - }; - - regulator: mt6397regulator { - compatible = "mediatek,mt6397-regulator"; - - mt6397_vpca15_reg: buck_vpca15 { - regulator-compatible = "buck_vpca15"; - regulator-name = "vpca15"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - regulator-allowed-modes = <0 1>; - }; - - mt6397_vpca7_reg: buck_vpca7 { - regulator-compatible = "buck_vpca7"; - regulator-name = "vpca7"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <115>; - regulator-always-on; - }; - - mt6397_vsramca15_reg: buck_vsramca15 { - regulator-compatible = "buck_vsramca15"; - regulator-name = "vsramca15"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vsramca7_reg: buck_vsramca7 { - regulator-compatible = "buck_vsramca7"; - regulator-name = "vsramca7"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vcore_reg: buck_vcore { - regulator-compatible = "buck_vcore"; - regulator-name = "vcore"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vgpu_reg: buck_vgpu { - regulator-compatible = "buck_vgpu"; - regulator-name = "vgpu"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <115>; - }; - - mt6397_vdrm_reg: buck_vdrm { - regulator-compatible = "buck_vdrm"; - regulator-name = "vdrm"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1400000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vio18_reg: buck_vio18 { - regulator-compatible = "buck_vio18"; - regulator-name = "vio18"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <1980000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vtcxo_reg: ldo_vtcxo { - regulator-compatible = "ldo_vtcxo"; - regulator-name = "vtcxo"; - regulator-always-on; - }; - - mt6397_va28_reg: ldo_va28 { - regulator-compatible = "ldo_va28"; - regulator-name = "va28"; - }; - - mt6397_vcama_reg: ldo_vcama { - regulator-compatible = "ldo_vcama"; - regulator-name = "vcama"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vio28_reg: ldo_vio28 { - regulator-compatible = "ldo_vio28"; - regulator-name = "vio28"; - regulator-always-on; - }; - - mt6397_vusb_reg: ldo_vusb { - regulator-compatible = "ldo_vusb"; - regulator-name = "vusb"; - }; - - mt6397_vmc_reg: ldo_vmc { - regulator-compatible = "ldo_vmc"; - regulator-name = "vmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vmch_reg: ldo_vmch { - regulator-compatible = "ldo_vmch"; - regulator-name = "vmch"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vemc_3v3_reg: ldo_vemc3v3 { - regulator-compatible = "ldo_vemc3v3"; - regulator-name = "vemc_3v3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp1_reg: ldo_vgp1 { - regulator-compatible = "ldo_vgp1"; - regulator-name = "vcamd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <240>; - }; - - mt6397_vgp2_reg: ldo_vgp2 { - regulator-compatible = "ldo_vgp2"; - regulator-name = "vcamio"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp3_reg: ldo_vgp3 { - regulator-compatible = "ldo_vgp3"; - regulator-name = "vcamaf"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp4_reg: ldo_vgp4 { - regulator-compatible = "ldo_vgp4"; - regulator-name = "vgp4"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp5_reg: ldo_vgp5 { - regulator-compatible = "ldo_vgp5"; - regulator-name = "vgp5"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp6_reg: ldo_vgp6 { - regulator-compatible = "ldo_vgp6"; - regulator-name = "vgp6"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - regulator-always-on; - }; - - mt6397_vibr_reg: ldo_vibr { - regulator-compatible = "ldo_vibr"; - regulator-name = "vibr"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - }; - - rtc: mt6397rtc { - compatible = "mediatek,mt6397-rtc"; - }; - - syscfg_pctl_pmic: syscfg_pctl_pmic@c000 { - compatible = "mediatek,mt6397-pctl-pmic-syscfg", - "syscon"; - reg = <0 0x0000c000 0 0x0108>; - }; - }; -}; - -&spi { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins_a>; - mediatek,pad-select = <1>; - status = "okay"; - /* clients */ - cros_ec: ec@0 { - compatible = "google,cros-ec-spi"; - reg = <0x0>; - spi-max-frequency = <12000000>; - interrupt-parent = <&pio>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - google,cros-ec-spi-msg-delay = <500>; - - i2c_tunnel: i2c-tunnel0 { - compatible = "google,cros-ec-i2c-tunnel"; - google,remote-bus = <0>; - #address-cells = <1>; - #size-cells = <0>; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <1>; - }; - }; - }; -}; - -&ssusb { - dr_mode = "host"; - wakeup-source; - vusb33-supply = <&mt6397_vusb_reg>; - status = "okay"; -}; - -&thermal { - bank0-supply = <&mt6397_vpca15_reg>; - bank1-supply = <&da9211_vcpu_reg>; -}; - -&uart0 { - status = "okay"; -}; - -&usb_host { - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins>; - vusb33-supply = <&mt6397_vusb_reg>; - status = "okay"; -}; - -#include diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts deleted file mode 100644 index 6dffada2e..000000000 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ /dev/null @@ -1,534 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Eddie Huang - */ - -/dts-v1/; -#include -#include "mt8173.dtsi" - -/ { - model = "MediaTek MT8173 evaluation board"; - compatible = "mediatek,mt8173-evb", "mediatek,mt8173"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x80000000>; - }; - - chosen { }; - - connector { - compatible = "hdmi-connector"; - label = "hdmi"; - type = "d"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi0_out>; - }; - }; - }; - - extcon_usb: extcon_iddig { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pio 16 GPIO_ACTIVE_HIGH>; - }; - - usb_p1_vbus: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 130 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usb_p0_vbus: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&cec { - status = "okay"; -}; - -&cpu0 { - proc-supply = <&mt6397_vpca15_reg>; -}; - -&cpu1 { - proc-supply = <&mt6397_vpca15_reg>; -}; - -&cpu2 { - proc-supply = <&da9211_vcpu_reg>; - sram-supply = <&mt6397_vsramca7_reg>; -}; - -&cpu3 { - proc-supply = <&da9211_vcpu_reg>; - sram-supply = <&mt6397_vsramca7_reg>; -}; - -&dpi0 { - status = "okay"; -}; - -&hdmi_phy { - status = "okay"; -}; - -&hdmi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - - hdmi0_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; -}; - -&i2c1 { - status = "okay"; - - buck: da9211@68 { - compatible = "dlg,da9211"; - reg = <0x68>; - - regulators { - da9211_vcpu_reg: BUCKA { - regulator-name = "VBUCKA"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1310000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <4400000>; - regulator-ramp-delay = <10000>; - regulator-always-on; - }; - - da9211_vgpu_reg: BUCKB { - regulator-name = "VBUCKB"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1310000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <3000000>; - regulator-ramp-delay = <10000>; - }; - }; - }; -}; - -&mmc0 { - status = "okay"; - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - bus-width = <8>; - max-frequency = <50000000>; - cap-mmc-highspeed; - mediatek,hs200-cmd-int-delay=<26>; - mediatek,hs400-cmd-int-delay=<14>; - mediatek,hs400-cmd-resp-sel-rising; - vmmc-supply = <&mt6397_vemc_3v3_reg>; - vqmmc-supply = <&mt6397_vio18_reg>; - non-removable; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_uhs>; - bus-width = <4>; - max-frequency = <50000000>; - cap-sd-highspeed; - sd-uhs-sdr25; - cd-gpios = <&pio 132 0>; - vmmc-supply = <&mt6397_vmch_reg>; - vqmmc-supply = <&mt6397_vmc_reg>; -}; - -&pio { - disp_pwm0_pins: disp_pwm0_pins { - pins1 { - pinmux = ; - output-low; - }; - }; - - mmc0_pins_default: mmc0default { - pins_cmd_dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - bias-pull-up; - }; - - pins_clk { - pinmux = ; - bias-pull-down; - }; - - pins_rst { - pinmux = ; - bias-pull-up; - }; - }; - - mmc1_pins_default: mmc1default { - pins_cmd_dat { - pinmux = , - , - , - , - ; - input-enable; - drive-strength = ; - bias-pull-up = ; - }; - - pins_clk { - pinmux = ; - bias-pull-down; - drive-strength = ; - }; - - pins_insert { - pinmux = ; - bias-pull-up; - }; - }; - - mmc0_pins_uhs: mmc0 { - pins_cmd_dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - drive-strength = ; - bias-pull-up = ; - }; - - pins_clk { - pinmux = ; - drive-strength = ; - bias-pull-down = ; - }; - - pins_rst { - pinmux = ; - bias-pull-up; - }; - }; - - mmc1_pins_uhs: mmc1 { - pins_cmd_dat { - pinmux = , - , - , - , - ; - input-enable; - drive-strength = ; - bias-pull-up = ; - }; - - pins_clk { - pinmux = ; - drive-strength = ; - bias-pull-down = ; - }; - }; - - usb_id_pins_float: usb_iddig_pull_up { - pins_iddig { - pinmux = ; - bias-pull-up; - }; - }; - - usb_id_pins_ground: usb_iddig_pull_down { - pins_iddig { - pinmux = ; - bias-pull-down; - }; - }; -}; - -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&disp_pwm0_pins>; - status = "okay"; -}; - -&pwrap { - /* Only MT8173 E1 needs USB power domain */ - power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; - - pmic: mt6397 { - compatible = "mediatek,mt6397"; - interrupt-parent = <&pio>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - - mt6397regulator: mt6397regulator { - compatible = "mediatek,mt6397-regulator"; - - mt6397_vpca15_reg: buck_vpca15 { - regulator-compatible = "buck_vpca15"; - regulator-name = "vpca15"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vpca7_reg: buck_vpca7 { - regulator-compatible = "buck_vpca7"; - regulator-name = "vpca7"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <115>; - }; - - mt6397_vsramca15_reg: buck_vsramca15 { - regulator-compatible = "buck_vsramca15"; - regulator-name = "vsramca15"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vsramca7_reg: buck_vsramca7 { - regulator-compatible = "buck_vsramca7"; - regulator-name = "vsramca7"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vcore_reg: buck_vcore { - regulator-compatible = "buck_vcore"; - regulator-name = "vcore"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vgpu_reg: buck_vgpu { - regulator-compatible = "buck_vgpu"; - regulator-name = "vgpu"; - regulator-min-microvolt = < 700000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <115>; - }; - - mt6397_vdrm_reg: buck_vdrm { - regulator-compatible = "buck_vdrm"; - regulator-name = "vdrm"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1400000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vio18_reg: buck_vio18 { - regulator-compatible = "buck_vio18"; - regulator-name = "vio18"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <1980000>; - regulator-ramp-delay = <12500>; - regulator-always-on; - }; - - mt6397_vtcxo_reg: ldo_vtcxo { - regulator-compatible = "ldo_vtcxo"; - regulator-name = "vtcxo"; - regulator-always-on; - }; - - mt6397_va28_reg: ldo_va28 { - regulator-compatible = "ldo_va28"; - regulator-name = "va28"; - regulator-always-on; - }; - - mt6397_vcama_reg: ldo_vcama { - regulator-compatible = "ldo_vcama"; - regulator-name = "vcama"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vio28_reg: ldo_vio28 { - regulator-compatible = "ldo_vio28"; - regulator-name = "vio28"; - regulator-always-on; - }; - - mt6397_vusb_reg: ldo_vusb { - regulator-compatible = "ldo_vusb"; - regulator-name = "vusb"; - }; - - mt6397_vmc_reg: ldo_vmc { - regulator-compatible = "ldo_vmc"; - regulator-name = "vmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vmch_reg: ldo_vmch { - regulator-compatible = "ldo_vmch"; - regulator-name = "vmch"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vemc_3v3_reg: ldo_vemc3v3 { - regulator-compatible = "ldo_vemc3v3"; - regulator-name = "vemc_3v3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp1_reg: ldo_vgp1 { - regulator-compatible = "ldo_vgp1"; - regulator-name = "vcamd"; - regulator-min-microvolt = <1220000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <240>; - }; - - mt6397_vgp2_reg: ldo_vgp2 { - regulator-compatible = "ldo_vgp2"; - regulator-name = "vcamio"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp3_reg: ldo_vgp3 { - regulator-compatible = "ldo_vgp3"; - regulator-name = "vcamaf"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp4_reg: ldo_vgp4 { - regulator-compatible = "ldo_vgp4"; - regulator-name = "vgp4"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp5_reg: ldo_vgp5 { - regulator-compatible = "ldo_vgp5"; - regulator-name = "vgp5"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3000000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vgp6_reg: ldo_vgp6 { - regulator-compatible = "ldo_vgp6"; - regulator-name = "vgp6"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - - mt6397_vibr_reg: ldo_vibr { - regulator-compatible = "ldo_vibr"; - regulator-name = "vibr"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <218>; - }; - }; - }; -}; - -&pio { - spi_pins_a: spi0 { - pins_spi { - pinmux = , - , - , - ; - }; - }; -}; - -&spi { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins_a>; - mediatek,pad-select = <0>; - status = "okay"; -}; - -&ssusb { - vusb33-supply = <&mt6397_vusb_reg>; - vbus-supply = <&usb_p0_vbus>; - extcon = <&extcon_usb>; - dr_mode = "otg"; - wakeup-source; - pinctrl-names = "default", "id_float", "id_ground"; - pinctrl-0 = <&usb_id_pins_float>; - pinctrl-1 = <&usb_id_pins_float>; - pinctrl-2 = <&usb_id_pins_ground>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&usb_host { - vusb33-supply = <&mt6397_vusb_reg>; - vbus-supply = <&usb_p1_vbus>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt8173-pinfunc.h deleted file mode 100644 index a5e308dc8..000000000 --- a/arch/arm64/boot/dts/mediatek/mt8173-pinfunc.h +++ /dev/null @@ -1,674 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Hongzhou.Yang - */ - -#ifndef __DTS_MT8173_PINFUNC_H -#define __DTS_MT8173_PINFUNC_H - -#include - -#define MT8173_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) -#define MT8173_PIN_0_EINT0__FUNC_IRDA_PDN (MTK_PIN_NO(0) | 1) -#define MT8173_PIN_0_EINT0__FUNC_I2S1_WS (MTK_PIN_NO(0) | 2) -#define MT8173_PIN_0_EINT0__FUNC_AUD_SPDIF (MTK_PIN_NO(0) | 3) -#define MT8173_PIN_0_EINT0__FUNC_UTXD0 (MTK_PIN_NO(0) | 4) -#define MT8173_PIN_0_EINT0__FUNC_DBG_MON_A_20_ (MTK_PIN_NO(0) | 7) - -#define MT8173_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) -#define MT8173_PIN_1_EINT1__FUNC_IRDA_RXD (MTK_PIN_NO(1) | 1) -#define MT8173_PIN_1_EINT1__FUNC_I2S1_BCK (MTK_PIN_NO(1) | 2) -#define MT8173_PIN_1_EINT1__FUNC_SDA5 (MTK_PIN_NO(1) | 3) -#define MT8173_PIN_1_EINT1__FUNC_URXD0 (MTK_PIN_NO(1) | 4) -#define MT8173_PIN_1_EINT1__FUNC_DBG_MON_A_21_ (MTK_PIN_NO(1) | 7) - -#define MT8173_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) -#define MT8173_PIN_2_EINT2__FUNC_IRDA_TXD (MTK_PIN_NO(2) | 1) -#define MT8173_PIN_2_EINT2__FUNC_I2S1_MCK (MTK_PIN_NO(2) | 2) -#define MT8173_PIN_2_EINT2__FUNC_SCL5 (MTK_PIN_NO(2) | 3) -#define MT8173_PIN_2_EINT2__FUNC_UTXD3 (MTK_PIN_NO(2) | 4) -#define MT8173_PIN_2_EINT2__FUNC_DBG_MON_A_22_ (MTK_PIN_NO(2) | 7) - -#define MT8173_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) -#define MT8173_PIN_3_EINT3__FUNC_DSI1_TE (MTK_PIN_NO(3) | 1) -#define MT8173_PIN_3_EINT3__FUNC_I2S1_DO_1 (MTK_PIN_NO(3) | 2) -#define MT8173_PIN_3_EINT3__FUNC_SDA3 (MTK_PIN_NO(3) | 3) -#define MT8173_PIN_3_EINT3__FUNC_URXD3 (MTK_PIN_NO(3) | 4) -#define MT8173_PIN_3_EINT3__FUNC_DBG_MON_A_23_ (MTK_PIN_NO(3) | 7) - -#define MT8173_PIN_4_EINT4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) -#define MT8173_PIN_4_EINT4__FUNC_DISP_PWM1 (MTK_PIN_NO(4) | 1) -#define MT8173_PIN_4_EINT4__FUNC_I2S1_DO_2 (MTK_PIN_NO(4) | 2) -#define MT8173_PIN_4_EINT4__FUNC_SCL3 (MTK_PIN_NO(4) | 3) -#define MT8173_PIN_4_EINT4__FUNC_UCTS3 (MTK_PIN_NO(4) | 4) -#define MT8173_PIN_4_EINT4__FUNC_SFWP_B (MTK_PIN_NO(4) | 6) - -#define MT8173_PIN_5_EINT5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) -#define MT8173_PIN_5_EINT5__FUNC_PCM1_CLK (MTK_PIN_NO(5) | 1) -#define MT8173_PIN_5_EINT5__FUNC_I2S2_WS (MTK_PIN_NO(5) | 2) -#define MT8173_PIN_5_EINT5__FUNC_SPI_CK_3_ (MTK_PIN_NO(5) | 3) -#define MT8173_PIN_5_EINT5__FUNC_URTS3 (MTK_PIN_NO(5) | 4) -#define MT8173_PIN_5_EINT5__FUNC_AP_MD32_JTAG_TMS (MTK_PIN_NO(5) | 5) -#define MT8173_PIN_5_EINT5__FUNC_SFOUT (MTK_PIN_NO(5) | 6) - -#define MT8173_PIN_6_EINT6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) -#define MT8173_PIN_6_EINT6__FUNC_PCM1_SYNC (MTK_PIN_NO(6) | 1) -#define MT8173_PIN_6_EINT6__FUNC_I2S2_BCK (MTK_PIN_NO(6) | 2) -#define MT8173_PIN_6_EINT6__FUNC_SPI_MI_3_ (MTK_PIN_NO(6) | 3) -#define MT8173_PIN_6_EINT6__FUNC_AP_MD32_JTAG_TCK (MTK_PIN_NO(6) | 5) -#define MT8173_PIN_6_EINT6__FUNC_SFCS0 (MTK_PIN_NO(6) | 6) - -#define MT8173_PIN_7_EINT7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) -#define MT8173_PIN_7_EINT7__FUNC_PCM1_DI (MTK_PIN_NO(7) | 1) -#define MT8173_PIN_7_EINT7__FUNC_I2S2_DI_1 (MTK_PIN_NO(7) | 2) -#define MT8173_PIN_7_EINT7__FUNC_SPI_MO_3_ (MTK_PIN_NO(7) | 3) -#define MT8173_PIN_7_EINT7__FUNC_AP_MD32_JTAG_TDI (MTK_PIN_NO(7) | 5) -#define MT8173_PIN_7_EINT7__FUNC_SFHOLD (MTK_PIN_NO(7) | 6) - -#define MT8173_PIN_8_EINT8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) -#define MT8173_PIN_8_EINT8__FUNC_PCM1_DO (MTK_PIN_NO(8) | 1) -#define MT8173_PIN_8_EINT8__FUNC_I2S2_DI_2 (MTK_PIN_NO(8) | 2) -#define MT8173_PIN_8_EINT8__FUNC_SPI_CS_3_ (MTK_PIN_NO(8) | 3) -#define MT8173_PIN_8_EINT8__FUNC_AUD_SPDIF (MTK_PIN_NO(8) | 4) -#define MT8173_PIN_8_EINT8__FUNC_AP_MD32_JTAG_TDO (MTK_PIN_NO(8) | 5) -#define MT8173_PIN_8_EINT8__FUNC_SFIN (MTK_PIN_NO(8) | 6) - -#define MT8173_PIN_9_EINT9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) -#define MT8173_PIN_9_EINT9__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(9) | 1) -#define MT8173_PIN_9_EINT9__FUNC_I2S2_MCK (MTK_PIN_NO(9) | 2) -#define MT8173_PIN_9_EINT9__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(9) | 4) -#define MT8173_PIN_9_EINT9__FUNC_AP_MD32_JTAG_TRST (MTK_PIN_NO(9) | 5) -#define MT8173_PIN_9_EINT9__FUNC_SFCK (MTK_PIN_NO(9) | 6) - -#define MT8173_PIN_10_EINT10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) -#define MT8173_PIN_10_EINT10__FUNC_CLKM0 (MTK_PIN_NO(10) | 1) -#define MT8173_PIN_10_EINT10__FUNC_DSI1_TE (MTK_PIN_NO(10) | 2) -#define MT8173_PIN_10_EINT10__FUNC_DISP_PWM1 (MTK_PIN_NO(10) | 3) -#define MT8173_PIN_10_EINT10__FUNC_PWM4 (MTK_PIN_NO(10) | 4) -#define MT8173_PIN_10_EINT10__FUNC_IRDA_RXD (MTK_PIN_NO(10) | 5) - -#define MT8173_PIN_11_EINT11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) -#define MT8173_PIN_11_EINT11__FUNC_CLKM1 (MTK_PIN_NO(11) | 1) -#define MT8173_PIN_11_EINT11__FUNC_I2S3_WS (MTK_PIN_NO(11) | 2) -#define MT8173_PIN_11_EINT11__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(11) | 3) -#define MT8173_PIN_11_EINT11__FUNC_PWM5 (MTK_PIN_NO(11) | 4) -#define MT8173_PIN_11_EINT11__FUNC_IRDA_TXD (MTK_PIN_NO(11) | 5) -#define MT8173_PIN_11_EINT11__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(11) | 6) -#define MT8173_PIN_11_EINT11__FUNC_DBG_MON_B_30_ (MTK_PIN_NO(11) | 7) - -#define MT8173_PIN_12_EINT12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) -#define MT8173_PIN_12_EINT12__FUNC_CLKM2 (MTK_PIN_NO(12) | 1) -#define MT8173_PIN_12_EINT12__FUNC_I2S3_BCK (MTK_PIN_NO(12) | 2) -#define MT8173_PIN_12_EINT12__FUNC_SRCLKENA0 (MTK_PIN_NO(12) | 3) -#define MT8173_PIN_12_EINT12__FUNC_I2S2_WS (MTK_PIN_NO(12) | 5) -#define MT8173_PIN_12_EINT12__FUNC_DBG_MON_B_32_ (MTK_PIN_NO(12) | 7) - -#define MT8173_PIN_13_EINT13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) -#define MT8173_PIN_13_EINT13__FUNC_CLKM3 (MTK_PIN_NO(13) | 1) -#define MT8173_PIN_13_EINT13__FUNC_I2S3_MCK (MTK_PIN_NO(13) | 2) -#define MT8173_PIN_13_EINT13__FUNC_SRCLKENA0 (MTK_PIN_NO(13) | 3) -#define MT8173_PIN_13_EINT13__FUNC_I2S2_BCK (MTK_PIN_NO(13) | 5) -#define MT8173_PIN_13_EINT13__FUNC_DBG_MON_A_32_ (MTK_PIN_NO(13) | 7) - -#define MT8173_PIN_14_EINT14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) -#define MT8173_PIN_14_EINT14__FUNC_CMDAT0 (MTK_PIN_NO(14) | 1) -#define MT8173_PIN_14_EINT14__FUNC_CMCSD0 (MTK_PIN_NO(14) | 2) -#define MT8173_PIN_14_EINT14__FUNC_CLKM2 (MTK_PIN_NO(14) | 4) -#define MT8173_PIN_14_EINT14__FUNC_DBG_MON_B_6_ (MTK_PIN_NO(14) | 7) - -#define MT8173_PIN_15_EINT15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) -#define MT8173_PIN_15_EINT15__FUNC_CMDAT1 (MTK_PIN_NO(15) | 1) -#define MT8173_PIN_15_EINT15__FUNC_CMCSD1 (MTK_PIN_NO(15) | 2) -#define MT8173_PIN_15_EINT15__FUNC_CMFLASH (MTK_PIN_NO(15) | 3) -#define MT8173_PIN_15_EINT15__FUNC_CLKM3 (MTK_PIN_NO(15) | 4) -#define MT8173_PIN_15_EINT15__FUNC_DBG_MON_B_29_ (MTK_PIN_NO(15) | 7) - -#define MT8173_PIN_16_IDDIG__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) -#define MT8173_PIN_16_IDDIG__FUNC_IDDIG (MTK_PIN_NO(16) | 1) -#define MT8173_PIN_16_IDDIG__FUNC_CMFLASH (MTK_PIN_NO(16) | 2) -#define MT8173_PIN_16_IDDIG__FUNC_PWM5 (MTK_PIN_NO(16) | 4) - -#define MT8173_PIN_17_WATCHDOG__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) -#define MT8173_PIN_17_WATCHDOG__FUNC_WATCHDOG_AO (MTK_PIN_NO(17) | 1) - -#define MT8173_PIN_18_CEC__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) -#define MT8173_PIN_18_CEC__FUNC_CEC (MTK_PIN_NO(18) | 1) - -#define MT8173_PIN_19_HDMISCK__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) -#define MT8173_PIN_19_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(19) | 1) -#define MT8173_PIN_19_HDMISCK__FUNC_HDCP_SCL (MTK_PIN_NO(19) | 2) - -#define MT8173_PIN_20_HDMISD__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) -#define MT8173_PIN_20_HDMISD__FUNC_HDMISD (MTK_PIN_NO(20) | 1) -#define MT8173_PIN_20_HDMISD__FUNC_HDCP_SDA (MTK_PIN_NO(20) | 2) - -#define MT8173_PIN_21_HTPLG__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) -#define MT8173_PIN_21_HTPLG__FUNC_HTPLG (MTK_PIN_NO(21) | 1) - -#define MT8173_PIN_22_MSDC3_DAT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) -#define MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(22) | 1) - -#define MT8173_PIN_23_MSDC3_DAT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) -#define MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(23) | 1) - -#define MT8173_PIN_24_MSDC3_DAT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) -#define MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(24) | 1) - -#define MT8173_PIN_25_MSDC3_DAT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) -#define MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(25) | 1) - -#define MT8173_PIN_26_MSDC3_CLK__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) -#define MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(26) | 1) - -#define MT8173_PIN_27_MSDC3_CMD__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) -#define MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(27) | 1) - -#define MT8173_PIN_28_MSDC3_DSL__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) -#define MT8173_PIN_28_MSDC3_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(28) | 1) - -#define MT8173_PIN_29_UCTS2__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) -#define MT8173_PIN_29_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(29) | 1) - -#define MT8173_PIN_30_URTS2__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) -#define MT8173_PIN_30_URTS2__FUNC_URTS2 (MTK_PIN_NO(30) | 1) - -#define MT8173_PIN_31_URXD2__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) -#define MT8173_PIN_31_URXD2__FUNC_URXD2 (MTK_PIN_NO(31) | 1) -#define MT8173_PIN_31_URXD2__FUNC_UTXD2 (MTK_PIN_NO(31) | 2) - -#define MT8173_PIN_32_UTXD2__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) -#define MT8173_PIN_32_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(32) | 1) -#define MT8173_PIN_32_UTXD2__FUNC_URXD2 (MTK_PIN_NO(32) | 2) - -#define MT8173_PIN_33_DAICLK__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) -#define MT8173_PIN_33_DAICLK__FUNC_MRG_CLK (MTK_PIN_NO(33) | 1) -#define MT8173_PIN_33_DAICLK__FUNC_PCM0_CLK (MTK_PIN_NO(33) | 2) - -#define MT8173_PIN_34_DAIPCMIN__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) -#define MT8173_PIN_34_DAIPCMIN__FUNC_MRG_DI (MTK_PIN_NO(34) | 1) -#define MT8173_PIN_34_DAIPCMIN__FUNC_PCM0_DI (MTK_PIN_NO(34) | 2) - -#define MT8173_PIN_35_DAIPCMOUT__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) -#define MT8173_PIN_35_DAIPCMOUT__FUNC_MRG_DO (MTK_PIN_NO(35) | 1) -#define MT8173_PIN_35_DAIPCMOUT__FUNC_PCM0_DO (MTK_PIN_NO(35) | 2) - -#define MT8173_PIN_36_DAISYNC__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) -#define MT8173_PIN_36_DAISYNC__FUNC_MRG_SYNC (MTK_PIN_NO(36) | 1) -#define MT8173_PIN_36_DAISYNC__FUNC_PCM0_SYNC (MTK_PIN_NO(36) | 2) - -#define MT8173_PIN_37_EINT16__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) -#define MT8173_PIN_37_EINT16__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(37) | 1) -#define MT8173_PIN_37_EINT16__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(37) | 2) -#define MT8173_PIN_37_EINT16__FUNC_PWM0 (MTK_PIN_NO(37) | 3) -#define MT8173_PIN_37_EINT16__FUNC_PWM1 (MTK_PIN_NO(37) | 4) -#define MT8173_PIN_37_EINT16__FUNC_PWM2 (MTK_PIN_NO(37) | 5) -#define MT8173_PIN_37_EINT16__FUNC_CLKM0 (MTK_PIN_NO(37) | 6) - -#define MT8173_PIN_38_CONN_RST__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) -#define MT8173_PIN_38_CONN_RST__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(38) | 1) -#define MT8173_PIN_38_CONN_RST__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(38) | 2) -#define MT8173_PIN_38_CONN_RST__FUNC_CLKM1 (MTK_PIN_NO(38) | 6) - -#define MT8173_PIN_39_CM2MCLK__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) -#define MT8173_PIN_39_CM2MCLK__FUNC_CM2MCLK (MTK_PIN_NO(39) | 1) -#define MT8173_PIN_39_CM2MCLK__FUNC_CMCSD0 (MTK_PIN_NO(39) | 2) -#define MT8173_PIN_39_CM2MCLK__FUNC_DBG_MON_A_17_ (MTK_PIN_NO(39) | 7) - -#define MT8173_PIN_40_CMPCLK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) -#define MT8173_PIN_40_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(40) | 1) -#define MT8173_PIN_40_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(40) | 2) -#define MT8173_PIN_40_CMPCLK__FUNC_CMCSD2 (MTK_PIN_NO(40) | 3) -#define MT8173_PIN_40_CMPCLK__FUNC_DBG_MON_A_18_ (MTK_PIN_NO(40) | 7) - -#define MT8173_PIN_41_CMMCLK__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) -#define MT8173_PIN_41_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(41) | 1) -#define MT8173_PIN_41_CMMCLK__FUNC_DBG_MON_A_19_ (MTK_PIN_NO(41) | 7) - -#define MT8173_PIN_42_DSI_TE__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) -#define MT8173_PIN_42_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(42) | 1) - -#define MT8173_PIN_43_SDA2__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) -#define MT8173_PIN_43_SDA2__FUNC_SDA2 (MTK_PIN_NO(43) | 1) - -#define MT8173_PIN_44_SCL2__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) -#define MT8173_PIN_44_SCL2__FUNC_SCL2 (MTK_PIN_NO(44) | 1) - -#define MT8173_PIN_45_SDA0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) -#define MT8173_PIN_45_SDA0__FUNC_SDA0 (MTK_PIN_NO(45) | 1) - -#define MT8173_PIN_46_SCL0__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) -#define MT8173_PIN_46_SCL0__FUNC_SCL0 (MTK_PIN_NO(46) | 1) - -#define MT8173_PIN_47_RDN0_A__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) -#define MT8173_PIN_47_RDN0_A__FUNC_CMDAT2 (MTK_PIN_NO(47) | 1) - -#define MT8173_PIN_48_RDP0_A__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) -#define MT8173_PIN_48_RDP0_A__FUNC_CMDAT3 (MTK_PIN_NO(48) | 1) - -#define MT8173_PIN_49_RDN1_A__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) -#define MT8173_PIN_49_RDN1_A__FUNC_CMDAT4 (MTK_PIN_NO(49) | 1) - -#define MT8173_PIN_50_RDP1_A__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) -#define MT8173_PIN_50_RDP1_A__FUNC_CMDAT5 (MTK_PIN_NO(50) | 1) - -#define MT8173_PIN_51_RCN_A__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) -#define MT8173_PIN_51_RCN_A__FUNC_CMDAT6 (MTK_PIN_NO(51) | 1) - -#define MT8173_PIN_52_RCP_A__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) -#define MT8173_PIN_52_RCP_A__FUNC_CMDAT7 (MTK_PIN_NO(52) | 1) - -#define MT8173_PIN_53_RDN2_A__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) -#define MT8173_PIN_53_RDN2_A__FUNC_CMDAT8 (MTK_PIN_NO(53) | 1) -#define MT8173_PIN_53_RDN2_A__FUNC_CMCSD3 (MTK_PIN_NO(53) | 2) - -#define MT8173_PIN_54_RDP2_A__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) -#define MT8173_PIN_54_RDP2_A__FUNC_CMDAT9 (MTK_PIN_NO(54) | 1) -#define MT8173_PIN_54_RDP2_A__FUNC_CMCSD2 (MTK_PIN_NO(54) | 2) - -#define MT8173_PIN_55_RDN3_A__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) -#define MT8173_PIN_55_RDN3_A__FUNC_CMHSYNC (MTK_PIN_NO(55) | 1) -#define MT8173_PIN_55_RDN3_A__FUNC_CMCSD1 (MTK_PIN_NO(55) | 2) - -#define MT8173_PIN_56_RDP3_A__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) -#define MT8173_PIN_56_RDP3_A__FUNC_CMVSYNC (MTK_PIN_NO(56) | 1) -#define MT8173_PIN_56_RDP3_A__FUNC_CMCSD0 (MTK_PIN_NO(56) | 2) - -#define MT8173_PIN_57_MSDC0_DAT0__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) -#define MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(57) | 1) -#define MT8173_PIN_57_MSDC0_DAT0__FUNC_I2S1_WS (MTK_PIN_NO(57) | 2) -#define MT8173_PIN_57_MSDC0_DAT0__FUNC_DBG_MON_B_7_ (MTK_PIN_NO(57) | 7) - -#define MT8173_PIN_58_MSDC0_DAT1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) -#define MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(58) | 1) -#define MT8173_PIN_58_MSDC0_DAT1__FUNC_I2S1_BCK (MTK_PIN_NO(58) | 2) -#define MT8173_PIN_58_MSDC0_DAT1__FUNC_DBG_MON_B_8_ (MTK_PIN_NO(58) | 7) - -#define MT8173_PIN_59_MSDC0_DAT2__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) -#define MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(59) | 1) -#define MT8173_PIN_59_MSDC0_DAT2__FUNC_I2S1_MCK (MTK_PIN_NO(59) | 2) -#define MT8173_PIN_59_MSDC0_DAT2__FUNC_DBG_MON_B_9_ (MTK_PIN_NO(59) | 7) - -#define MT8173_PIN_60_MSDC0_DAT3__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) -#define MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(60) | 1) -#define MT8173_PIN_60_MSDC0_DAT3__FUNC_I2S1_DO_1 (MTK_PIN_NO(60) | 2) -#define MT8173_PIN_60_MSDC0_DAT3__FUNC_DBG_MON_B_10_ (MTK_PIN_NO(60) | 7) - -#define MT8173_PIN_61_MSDC0_DAT4__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) -#define MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(61) | 1) -#define MT8173_PIN_61_MSDC0_DAT4__FUNC_I2S1_DO_2 (MTK_PIN_NO(61) | 2) -#define MT8173_PIN_61_MSDC0_DAT4__FUNC_DBG_MON_B_11_ (MTK_PIN_NO(61) | 7) - -#define MT8173_PIN_62_MSDC0_DAT5__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) -#define MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(62) | 1) -#define MT8173_PIN_62_MSDC0_DAT5__FUNC_I2S2_WS (MTK_PIN_NO(62) | 2) -#define MT8173_PIN_62_MSDC0_DAT5__FUNC_DBG_MON_B_12_ (MTK_PIN_NO(62) | 7) - -#define MT8173_PIN_63_MSDC0_DAT6__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) -#define MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(63) | 1) -#define MT8173_PIN_63_MSDC0_DAT6__FUNC_I2S2_BCK (MTK_PIN_NO(63) | 2) -#define MT8173_PIN_63_MSDC0_DAT6__FUNC_DBG_MON_B_13_ (MTK_PIN_NO(63) | 7) - -#define MT8173_PIN_64_MSDC0_DAT7__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) -#define MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(64) | 1) -#define MT8173_PIN_64_MSDC0_DAT7__FUNC_I2S2_DI_1 (MTK_PIN_NO(64) | 2) -#define MT8173_PIN_64_MSDC0_DAT7__FUNC_DBG_MON_B_14_ (MTK_PIN_NO(64) | 7) - -#define MT8173_PIN_65_MSDC0_CLK__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) -#define MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(65) | 1) -#define MT8173_PIN_65_MSDC0_CLK__FUNC_DBG_MON_B_16_ (MTK_PIN_NO(65) | 7) - -#define MT8173_PIN_66_MSDC0_CMD__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) -#define MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(66) | 1) -#define MT8173_PIN_66_MSDC0_CMD__FUNC_I2S2_DI_2 (MTK_PIN_NO(66) | 2) -#define MT8173_PIN_66_MSDC0_CMD__FUNC_DBG_MON_B_15_ (MTK_PIN_NO(66) | 7) - -#define MT8173_PIN_67_MSDC0_DSL__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) -#define MT8173_PIN_67_MSDC0_DSL__FUNC_MSDC0_DSL (MTK_PIN_NO(67) | 1) -#define MT8173_PIN_67_MSDC0_DSL__FUNC_DBG_MON_B_17_ (MTK_PIN_NO(67) | 7) - -#define MT8173_PIN_68_MSDC0_RST___FUNC_GPIO68 (MTK_PIN_NO(68) | 0) -#define MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB (MTK_PIN_NO(68) | 1) -#define MT8173_PIN_68_MSDC0_RST___FUNC_I2S2_MCK (MTK_PIN_NO(68) | 2) -#define MT8173_PIN_68_MSDC0_RST___FUNC_DBG_MON_B_18_ (MTK_PIN_NO(68) | 7) - -#define MT8173_PIN_69_SPI_CK__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) -#define MT8173_PIN_69_SPI_CK__FUNC_SPI_CK_0_ (MTK_PIN_NO(69) | 1) -#define MT8173_PIN_69_SPI_CK__FUNC_I2S3_DO_1 (MTK_PIN_NO(69) | 2) -#define MT8173_PIN_69_SPI_CK__FUNC_PWM0 (MTK_PIN_NO(69) | 3) -#define MT8173_PIN_69_SPI_CK__FUNC_PWM5 (MTK_PIN_NO(69) | 4) -#define MT8173_PIN_69_SPI_CK__FUNC_I2S2_MCK (MTK_PIN_NO(69) | 5) -#define MT8173_PIN_69_SPI_CK__FUNC_DBG_MON_B_19_ (MTK_PIN_NO(69) | 7) - -#define MT8173_PIN_70_SPI_MI__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) -#define MT8173_PIN_70_SPI_MI__FUNC_SPI_MI_0_ (MTK_PIN_NO(70) | 1) -#define MT8173_PIN_70_SPI_MI__FUNC_I2S3_DO_2 (MTK_PIN_NO(70) | 2) -#define MT8173_PIN_70_SPI_MI__FUNC_PWM1 (MTK_PIN_NO(70) | 3) -#define MT8173_PIN_70_SPI_MI__FUNC_SPI_MO_0_ (MTK_PIN_NO(70) | 4) -#define MT8173_PIN_70_SPI_MI__FUNC_I2S2_DI_1 (MTK_PIN_NO(70) | 5) -#define MT8173_PIN_70_SPI_MI__FUNC_DSI1_TE (MTK_PIN_NO(70) | 6) -#define MT8173_PIN_70_SPI_MI__FUNC_DBG_MON_B_20_ (MTK_PIN_NO(70) | 7) - -#define MT8173_PIN_71_SPI_MO__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) -#define MT8173_PIN_71_SPI_MO__FUNC_SPI_MO_0_ (MTK_PIN_NO(71) | 1) -#define MT8173_PIN_71_SPI_MO__FUNC_I2S3_DO_3 (MTK_PIN_NO(71) | 2) -#define MT8173_PIN_71_SPI_MO__FUNC_PWM2 (MTK_PIN_NO(71) | 3) -#define MT8173_PIN_71_SPI_MO__FUNC_SPI_MI_0_ (MTK_PIN_NO(71) | 4) -#define MT8173_PIN_71_SPI_MO__FUNC_I2S2_DI_2 (MTK_PIN_NO(71) | 5) -#define MT8173_PIN_71_SPI_MO__FUNC_DBG_MON_B_21_ (MTK_PIN_NO(71) | 7) - -#define MT8173_PIN_72_SPI_CS__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) -#define MT8173_PIN_72_SPI_CS__FUNC_SPI_CS_0_ (MTK_PIN_NO(72) | 1) -#define MT8173_PIN_72_SPI_CS__FUNC_I2S3_DO_4 (MTK_PIN_NO(72) | 2) -#define MT8173_PIN_72_SPI_CS__FUNC_PWM3 (MTK_PIN_NO(72) | 3) -#define MT8173_PIN_72_SPI_CS__FUNC_PWM6 (MTK_PIN_NO(72) | 4) -#define MT8173_PIN_72_SPI_CS__FUNC_DISP_PWM1 (MTK_PIN_NO(72) | 5) -#define MT8173_PIN_72_SPI_CS__FUNC_DBG_MON_B_22_ (MTK_PIN_NO(72) | 7) - -#define MT8173_PIN_73_MSDC1_DAT0__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) -#define MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(73) | 1) -#define MT8173_PIN_73_MSDC1_DAT0__FUNC_DBG_MON_B_24_ (MTK_PIN_NO(73) | 7) - -#define MT8173_PIN_74_MSDC1_DAT1__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) -#define MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(74) | 1) -#define MT8173_PIN_74_MSDC1_DAT1__FUNC_DBG_MON_B_25_ (MTK_PIN_NO(74) | 7) - -#define MT8173_PIN_75_MSDC1_DAT2__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) -#define MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(75) | 1) -#define MT8173_PIN_75_MSDC1_DAT2__FUNC_DBG_MON_B_26_ (MTK_PIN_NO(75) | 7) - -#define MT8173_PIN_76_MSDC1_DAT3__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) -#define MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(76) | 1) -#define MT8173_PIN_76_MSDC1_DAT3__FUNC_DBG_MON_B_27_ (MTK_PIN_NO(76) | 7) - -#define MT8173_PIN_77_MSDC1_CLK__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) -#define MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(77) | 1) -#define MT8173_PIN_77_MSDC1_CLK__FUNC_DBG_MON_B_28_ (MTK_PIN_NO(77) | 7) - -#define MT8173_PIN_78_MSDC1_CMD__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) -#define MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(78) | 1) -#define MT8173_PIN_78_MSDC1_CMD__FUNC_DBG_MON_B_23_ (MTK_PIN_NO(78) | 7) - -#define MT8173_PIN_79_PWRAP_SPI0_MI__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) -#define MT8173_PIN_79_PWRAP_SPI0_MI__FUNC_PWRAP_SPIMI (MTK_PIN_NO(79) | 1) -#define MT8173_PIN_79_PWRAP_SPI0_MI__FUNC_PWRAP_SPIMO (MTK_PIN_NO(79) | 2) - -#define MT8173_PIN_80_PWRAP_SPI0_MO__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) -#define MT8173_PIN_80_PWRAP_SPI0_MO__FUNC_PWRAP_SPIMO (MTK_PIN_NO(80) | 1) -#define MT8173_PIN_80_PWRAP_SPI0_MO__FUNC_PWRAP_SPIMI (MTK_PIN_NO(80) | 2) - -#define MT8173_PIN_81_PWRAP_SPI0_CK__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) -#define MT8173_PIN_81_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK (MTK_PIN_NO(81) | 1) - -#define MT8173_PIN_82_PWRAP_SPI0_CSN__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) -#define MT8173_PIN_82_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS (MTK_PIN_NO(82) | 1) - -#define MT8173_PIN_83_AUD_CLK_MOSI__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) -#define MT8173_PIN_83_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(83) | 1) - -#define MT8173_PIN_84_AUD_DAT_MISO__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) -#define MT8173_PIN_84_AUD_DAT_MISO__FUNC_AUD_DAT_MISO (MTK_PIN_NO(84) | 1) -#define MT8173_PIN_84_AUD_DAT_MISO__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(84) | 2) - -#define MT8173_PIN_85_AUD_DAT_MOSI__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) -#define MT8173_PIN_85_AUD_DAT_MOSI__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(85) | 1) -#define MT8173_PIN_85_AUD_DAT_MOSI__FUNC_AUD_DAT_MISO (MTK_PIN_NO(85) | 2) - -#define MT8173_PIN_86_RTC32K_CK__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) -#define MT8173_PIN_86_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(86) | 1) - -#define MT8173_PIN_87_DISP_PWM0__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) -#define MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0 (MTK_PIN_NO(87) | 1) -#define MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM1 (MTK_PIN_NO(87) | 2) -#define MT8173_PIN_87_DISP_PWM0__FUNC_DBG_MON_B_31_ (MTK_PIN_NO(87) | 7) - -#define MT8173_PIN_88_SRCLKENAI__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) -#define MT8173_PIN_88_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(88) | 1) - -#define MT8173_PIN_89_SRCLKENAI2__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) -#define MT8173_PIN_89_SRCLKENAI2__FUNC_SRCLKENAI2 (MTK_PIN_NO(89) | 1) - -#define MT8173_PIN_90_SRCLKENA0__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) -#define MT8173_PIN_90_SRCLKENA0__FUNC_SRCLKENA0 (MTK_PIN_NO(90) | 1) - -#define MT8173_PIN_91_SRCLKENA1__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) -#define MT8173_PIN_91_SRCLKENA1__FUNC_SRCLKENA1 (MTK_PIN_NO(91) | 1) - -#define MT8173_PIN_92_PCM_CLK__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) -#define MT8173_PIN_92_PCM_CLK__FUNC_PCM1_CLK (MTK_PIN_NO(92) | 1) -#define MT8173_PIN_92_PCM_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(92) | 2) -#define MT8173_PIN_92_PCM_CLK__FUNC_DBG_MON_A_24_ (MTK_PIN_NO(92) | 7) - -#define MT8173_PIN_93_PCM_SYNC__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) -#define MT8173_PIN_93_PCM_SYNC__FUNC_PCM1_SYNC (MTK_PIN_NO(93) | 1) -#define MT8173_PIN_93_PCM_SYNC__FUNC_I2S0_WS (MTK_PIN_NO(93) | 2) -#define MT8173_PIN_93_PCM_SYNC__FUNC_DBG_MON_A_25_ (MTK_PIN_NO(93) | 7) - -#define MT8173_PIN_94_PCM_RX__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) -#define MT8173_PIN_94_PCM_RX__FUNC_PCM1_DI (MTK_PIN_NO(94) | 1) -#define MT8173_PIN_94_PCM_RX__FUNC_I2S0_DI (MTK_PIN_NO(94) | 2) -#define MT8173_PIN_94_PCM_RX__FUNC_DBG_MON_A_26_ (MTK_PIN_NO(94) | 7) - -#define MT8173_PIN_95_PCM_TX__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) -#define MT8173_PIN_95_PCM_TX__FUNC_PCM1_DO (MTK_PIN_NO(95) | 1) -#define MT8173_PIN_95_PCM_TX__FUNC_I2S0_DO (MTK_PIN_NO(95) | 2) -#define MT8173_PIN_95_PCM_TX__FUNC_DBG_MON_A_27_ (MTK_PIN_NO(95) | 7) - -#define MT8173_PIN_96_URXD1__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) -#define MT8173_PIN_96_URXD1__FUNC_URXD1 (MTK_PIN_NO(96) | 1) -#define MT8173_PIN_96_URXD1__FUNC_UTXD1 (MTK_PIN_NO(96) | 2) -#define MT8173_PIN_96_URXD1__FUNC_DBG_MON_A_28_ (MTK_PIN_NO(96) | 7) - -#define MT8173_PIN_97_UTXD1__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) -#define MT8173_PIN_97_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(97) | 1) -#define MT8173_PIN_97_UTXD1__FUNC_URXD1 (MTK_PIN_NO(97) | 2) -#define MT8173_PIN_97_UTXD1__FUNC_DBG_MON_A_29_ (MTK_PIN_NO(97) | 7) - -#define MT8173_PIN_98_URTS1__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) -#define MT8173_PIN_98_URTS1__FUNC_URTS1 (MTK_PIN_NO(98) | 1) -#define MT8173_PIN_98_URTS1__FUNC_UCTS1 (MTK_PIN_NO(98) | 2) -#define MT8173_PIN_98_URTS1__FUNC_DBG_MON_A_30_ (MTK_PIN_NO(98) | 7) - -#define MT8173_PIN_99_UCTS1__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) -#define MT8173_PIN_99_UCTS1__FUNC_UCTS1 (MTK_PIN_NO(99) | 1) -#define MT8173_PIN_99_UCTS1__FUNC_URTS1 (MTK_PIN_NO(99) | 2) -#define MT8173_PIN_99_UCTS1__FUNC_DBG_MON_A_31_ (MTK_PIN_NO(99) | 7) - -#define MT8173_PIN_100_MSDC2_DAT0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) -#define MT8173_PIN_100_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(100) | 1) -#define MT8173_PIN_100_MSDC2_DAT0__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(100) | 3) -#define MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5 (MTK_PIN_NO(100) | 4) -#define MT8173_PIN_100_MSDC2_DAT0__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(100) | 5) -#define MT8173_PIN_100_MSDC2_DAT0__FUNC_DBG_MON_B_0_ (MTK_PIN_NO(100) | 7) - -#define MT8173_PIN_101_MSDC2_DAT1__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) -#define MT8173_PIN_101_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(101) | 1) -#define MT8173_PIN_101_MSDC2_DAT1__FUNC_AUD_SPDIF (MTK_PIN_NO(101) | 3) -#define MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5 (MTK_PIN_NO(101) | 4) -#define MT8173_PIN_101_MSDC2_DAT1__FUNC_DBG_MON_B_1_ (MTK_PIN_NO(101) | 7) - -#define MT8173_PIN_102_MSDC2_DAT2__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) -#define MT8173_PIN_102_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(102) | 1) -#define MT8173_PIN_102_MSDC2_DAT2__FUNC_UTXD0 (MTK_PIN_NO(102) | 3) -#define MT8173_PIN_102_MSDC2_DAT2__FUNC_PWM0 (MTK_PIN_NO(102) | 5) -#define MT8173_PIN_102_MSDC2_DAT2__FUNC_SPI_CK_1_ (MTK_PIN_NO(102) | 6) -#define MT8173_PIN_102_MSDC2_DAT2__FUNC_DBG_MON_B_2_ (MTK_PIN_NO(102) | 7) - -#define MT8173_PIN_103_MSDC2_DAT3__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) -#define MT8173_PIN_103_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(103) | 1) -#define MT8173_PIN_103_MSDC2_DAT3__FUNC_URXD0 (MTK_PIN_NO(103) | 3) -#define MT8173_PIN_103_MSDC2_DAT3__FUNC_PWM1 (MTK_PIN_NO(103) | 5) -#define MT8173_PIN_103_MSDC2_DAT3__FUNC_SPI_MI_1_ (MTK_PIN_NO(103) | 6) -#define MT8173_PIN_103_MSDC2_DAT3__FUNC_DBG_MON_B_3_ (MTK_PIN_NO(103) | 7) - -#define MT8173_PIN_104_MSDC2_CLK__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) -#define MT8173_PIN_104_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(104) | 1) -#define MT8173_PIN_104_MSDC2_CLK__FUNC_UTXD3 (MTK_PIN_NO(104) | 3) -#define MT8173_PIN_104_MSDC2_CLK__FUNC_SDA3 (MTK_PIN_NO(104) | 4) -#define MT8173_PIN_104_MSDC2_CLK__FUNC_PWM2 (MTK_PIN_NO(104) | 5) -#define MT8173_PIN_104_MSDC2_CLK__FUNC_SPI_MO_1_ (MTK_PIN_NO(104) | 6) -#define MT8173_PIN_104_MSDC2_CLK__FUNC_DBG_MON_B_4_ (MTK_PIN_NO(104) | 7) - -#define MT8173_PIN_105_MSDC2_CMD__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) -#define MT8173_PIN_105_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(105) | 1) -#define MT8173_PIN_105_MSDC2_CMD__FUNC_URXD3 (MTK_PIN_NO(105) | 3) -#define MT8173_PIN_105_MSDC2_CMD__FUNC_SCL3 (MTK_PIN_NO(105) | 4) -#define MT8173_PIN_105_MSDC2_CMD__FUNC_PWM3 (MTK_PIN_NO(105) | 5) -#define MT8173_PIN_105_MSDC2_CMD__FUNC_SPI_CS_1_ (MTK_PIN_NO(105) | 6) -#define MT8173_PIN_105_MSDC2_CMD__FUNC_DBG_MON_B_5_ (MTK_PIN_NO(105) | 7) - -#define MT8173_PIN_106_SDA3__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) -#define MT8173_PIN_106_SDA3__FUNC_SDA3 (MTK_PIN_NO(106) | 1) - -#define MT8173_PIN_107_SCL3__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) -#define MT8173_PIN_107_SCL3__FUNC_SCL3 (MTK_PIN_NO(107) | 1) - -#define MT8173_PIN_108_JTMS__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) -#define MT8173_PIN_108_JTMS__FUNC_JTMS (MTK_PIN_NO(108) | 1) -#define MT8173_PIN_108_JTMS__FUNC_MFG_JTAG_TMS (MTK_PIN_NO(108) | 2) -#define MT8173_PIN_108_JTMS__FUNC_AP_MD32_JTAG_TMS (MTK_PIN_NO(108) | 5) -#define MT8173_PIN_108_JTMS__FUNC_DFD_TMS (MTK_PIN_NO(108) | 6) - -#define MT8173_PIN_109_JTCK__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) -#define MT8173_PIN_109_JTCK__FUNC_JTCK (MTK_PIN_NO(109) | 1) -#define MT8173_PIN_109_JTCK__FUNC_MFG_JTAG_TCK (MTK_PIN_NO(109) | 2) -#define MT8173_PIN_109_JTCK__FUNC_AP_MD32_JTAG_TCK (MTK_PIN_NO(109) | 5) -#define MT8173_PIN_109_JTCK__FUNC_DFD_TCK (MTK_PIN_NO(109) | 6) - -#define MT8173_PIN_110_JTDI__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) -#define MT8173_PIN_110_JTDI__FUNC_JTDI (MTK_PIN_NO(110) | 1) -#define MT8173_PIN_110_JTDI__FUNC_MFG_JTAG_TDI (MTK_PIN_NO(110) | 2) -#define MT8173_PIN_110_JTDI__FUNC_AP_MD32_JTAG_TDI (MTK_PIN_NO(110) | 5) -#define MT8173_PIN_110_JTDI__FUNC_DFD_TDI (MTK_PIN_NO(110) | 6) - -#define MT8173_PIN_111_JTDO__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) -#define MT8173_PIN_111_JTDO__FUNC_JTDO (MTK_PIN_NO(111) | 1) -#define MT8173_PIN_111_JTDO__FUNC_MFG_JTAG_TDO (MTK_PIN_NO(111) | 2) -#define MT8173_PIN_111_JTDO__FUNC_AP_MD32_JTAG_TDO (MTK_PIN_NO(111) | 5) -#define MT8173_PIN_111_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(111) | 6) - -#define MT8173_PIN_112_JTRST_B__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) -#define MT8173_PIN_112_JTRST_B__FUNC_JTRST_B (MTK_PIN_NO(112) | 1) -#define MT8173_PIN_112_JTRST_B__FUNC_MFG_JTAG_TRSTN (MTK_PIN_NO(112) | 2) -#define MT8173_PIN_112_JTRST_B__FUNC_AP_MD32_JTAG_TRST (MTK_PIN_NO(112) | 5) -#define MT8173_PIN_112_JTRST_B__FUNC_DFD_NTRST (MTK_PIN_NO(112) | 6) - -#define MT8173_PIN_113_URXD0__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) -#define MT8173_PIN_113_URXD0__FUNC_URXD0 (MTK_PIN_NO(113) | 1) -#define MT8173_PIN_113_URXD0__FUNC_UTXD0 (MTK_PIN_NO(113) | 2) -#define MT8173_PIN_113_URXD0__FUNC_I2S2_WS (MTK_PIN_NO(113) | 6) -#define MT8173_PIN_113_URXD0__FUNC_DBG_MON_A_0_ (MTK_PIN_NO(113) | 7) - -#define MT8173_PIN_114_UTXD0__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) -#define MT8173_PIN_114_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(114) | 1) -#define MT8173_PIN_114_UTXD0__FUNC_URXD0 (MTK_PIN_NO(114) | 2) -#define MT8173_PIN_114_UTXD0__FUNC_I2S2_BCK (MTK_PIN_NO(114) | 6) -#define MT8173_PIN_114_UTXD0__FUNC_DBG_MON_A_1_ (MTK_PIN_NO(114) | 7) - -#define MT8173_PIN_115_URTS0__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) -#define MT8173_PIN_115_URTS0__FUNC_URTS0 (MTK_PIN_NO(115) | 1) -#define MT8173_PIN_115_URTS0__FUNC_UCTS0 (MTK_PIN_NO(115) | 2) -#define MT8173_PIN_115_URTS0__FUNC_I2S2_MCK (MTK_PIN_NO(115) | 6) -#define MT8173_PIN_115_URTS0__FUNC_DBG_MON_A_2_ (MTK_PIN_NO(115) | 7) - -#define MT8173_PIN_116_UCTS0__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) -#define MT8173_PIN_116_UCTS0__FUNC_UCTS0 (MTK_PIN_NO(116) | 1) -#define MT8173_PIN_116_UCTS0__FUNC_URTS0 (MTK_PIN_NO(116) | 2) -#define MT8173_PIN_116_UCTS0__FUNC_I2S2_DI_1 (MTK_PIN_NO(116) | 6) -#define MT8173_PIN_116_UCTS0__FUNC_DBG_MON_A_3_ (MTK_PIN_NO(116) | 7) - -#define MT8173_PIN_117_URXD3__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) -#define MT8173_PIN_117_URXD3__FUNC_URXD3 (MTK_PIN_NO(117) | 1) -#define MT8173_PIN_117_URXD3__FUNC_UTXD3 (MTK_PIN_NO(117) | 2) -#define MT8173_PIN_117_URXD3__FUNC_DBG_MON_A_9_ (MTK_PIN_NO(117) | 7) - -#define MT8173_PIN_118_UTXD3__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) -#define MT8173_PIN_118_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(118) | 1) -#define MT8173_PIN_118_UTXD3__FUNC_URXD3 (MTK_PIN_NO(118) | 2) -#define MT8173_PIN_118_UTXD3__FUNC_DBG_MON_A_10_ (MTK_PIN_NO(118) | 7) - -#define MT8173_PIN_119_KPROW0__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) -#define MT8173_PIN_119_KPROW0__FUNC_KROW0 (MTK_PIN_NO(119) | 1) -#define MT8173_PIN_119_KPROW0__FUNC_DBG_MON_A_11_ (MTK_PIN_NO(119) | 7) - -#define MT8173_PIN_120_KPROW1__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) -#define MT8173_PIN_120_KPROW1__FUNC_KROW1 (MTK_PIN_NO(120) | 1) -#define MT8173_PIN_120_KPROW1__FUNC_PWM6 (MTK_PIN_NO(120) | 3) -#define MT8173_PIN_120_KPROW1__FUNC_DBG_MON_A_12_ (MTK_PIN_NO(120) | 7) - -#define MT8173_PIN_121_KPROW2__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) -#define MT8173_PIN_121_KPROW2__FUNC_KROW2 (MTK_PIN_NO(121) | 1) -#define MT8173_PIN_121_KPROW2__FUNC_IRDA_PDN (MTK_PIN_NO(121) | 2) -#define MT8173_PIN_121_KPROW2__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(121) | 3) -#define MT8173_PIN_121_KPROW2__FUNC_PWM4 (MTK_PIN_NO(121) | 4) -#define MT8173_PIN_121_KPROW2__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(121) | 5) -#define MT8173_PIN_121_KPROW2__FUNC_DBG_MON_A_13_ (MTK_PIN_NO(121) | 7) - -#define MT8173_PIN_122_KPCOL0__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) -#define MT8173_PIN_122_KPCOL0__FUNC_KCOL0 (MTK_PIN_NO(122) | 1) -#define MT8173_PIN_122_KPCOL0__FUNC_DBG_MON_A_14_ (MTK_PIN_NO(122) | 7) - -#define MT8173_PIN_123_KPCOL1__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) -#define MT8173_PIN_123_KPCOL1__FUNC_KCOL1 (MTK_PIN_NO(123) | 1) -#define MT8173_PIN_123_KPCOL1__FUNC_IRDA_RXD (MTK_PIN_NO(123) | 2) -#define MT8173_PIN_123_KPCOL1__FUNC_PWM5 (MTK_PIN_NO(123) | 3) -#define MT8173_PIN_123_KPCOL1__FUNC_DBG_MON_A_15_ (MTK_PIN_NO(123) | 7) - -#define MT8173_PIN_124_KPCOL2__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) -#define MT8173_PIN_124_KPCOL2__FUNC_KCOL2 (MTK_PIN_NO(124) | 1) -#define MT8173_PIN_124_KPCOL2__FUNC_IRDA_TXD (MTK_PIN_NO(124) | 2) -#define MT8173_PIN_124_KPCOL2__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(124) | 3) -#define MT8173_PIN_124_KPCOL2__FUNC_PWM3 (MTK_PIN_NO(124) | 4) -#define MT8173_PIN_124_KPCOL2__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(124) | 5) -#define MT8173_PIN_124_KPCOL2__FUNC_DBG_MON_A_16_ (MTK_PIN_NO(124) | 7) - -#define MT8173_PIN_125_SDA1__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) -#define MT8173_PIN_125_SDA1__FUNC_SDA1 (MTK_PIN_NO(125) | 1) - -#define MT8173_PIN_126_SCL1__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) -#define MT8173_PIN_126_SCL1__FUNC_SCL1 (MTK_PIN_NO(126) | 1) - -#define MT8173_PIN_127_LCM_RST__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) -#define MT8173_PIN_127_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(127) | 1) - -#define MT8173_PIN_128_I2S0_LRCK__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) -#define MT8173_PIN_128_I2S0_LRCK__FUNC_I2S0_WS (MTK_PIN_NO(128) | 1) -#define MT8173_PIN_128_I2S0_LRCK__FUNC_I2S1_WS (MTK_PIN_NO(128) | 2) -#define MT8173_PIN_128_I2S0_LRCK__FUNC_I2S2_WS (MTK_PIN_NO(128) | 3) -#define MT8173_PIN_128_I2S0_LRCK__FUNC_SPI_CK_2_ (MTK_PIN_NO(128) | 5) -#define MT8173_PIN_128_I2S0_LRCK__FUNC_DBG_MON_A_4_ (MTK_PIN_NO(128) | 7) - -#define MT8173_PIN_129_I2S0_BCK__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) -#define MT8173_PIN_129_I2S0_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(129) | 1) -#define MT8173_PIN_129_I2S0_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(129) | 2) -#define MT8173_PIN_129_I2S0_BCK__FUNC_I2S2_BCK (MTK_PIN_NO(129) | 3) -#define MT8173_PIN_129_I2S0_BCK__FUNC_SPI_MI_2_ (MTK_PIN_NO(129) | 5) -#define MT8173_PIN_129_I2S0_BCK__FUNC_DBG_MON_A_5_ (MTK_PIN_NO(129) | 7) - -#define MT8173_PIN_130_I2S0_MCK__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) -#define MT8173_PIN_130_I2S0_MCK__FUNC_I2S0_MCK (MTK_PIN_NO(130) | 1) -#define MT8173_PIN_130_I2S0_MCK__FUNC_I2S1_MCK (MTK_PIN_NO(130) | 2) -#define MT8173_PIN_130_I2S0_MCK__FUNC_I2S2_MCK (MTK_PIN_NO(130) | 3) -#define MT8173_PIN_130_I2S0_MCK__FUNC_SPI_MO_2_ (MTK_PIN_NO(130) | 5) -#define MT8173_PIN_130_I2S0_MCK__FUNC_DBG_MON_A_6_ (MTK_PIN_NO(130) | 7) - -#define MT8173_PIN_131_I2S0_DATA0__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) -#define MT8173_PIN_131_I2S0_DATA0__FUNC_I2S0_DO (MTK_PIN_NO(131) | 1) -#define MT8173_PIN_131_I2S0_DATA0__FUNC_I2S1_DO_1 (MTK_PIN_NO(131) | 2) -#define MT8173_PIN_131_I2S0_DATA0__FUNC_I2S2_DI_1 (MTK_PIN_NO(131) | 3) -#define MT8173_PIN_131_I2S0_DATA0__FUNC_SPI_CS_2_ (MTK_PIN_NO(131) | 5) -#define MT8173_PIN_131_I2S0_DATA0__FUNC_DBG_MON_A_7_ (MTK_PIN_NO(131) | 7) - -#define MT8173_PIN_132_I2S0_DATA1__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) -#define MT8173_PIN_132_I2S0_DATA1__FUNC_I2S0_DI (MTK_PIN_NO(132) | 1) -#define MT8173_PIN_132_I2S0_DATA1__FUNC_I2S1_DO_2 (MTK_PIN_NO(132) | 2) -#define MT8173_PIN_132_I2S0_DATA1__FUNC_I2S2_DI_2 (MTK_PIN_NO(132) | 3) -#define MT8173_PIN_132_I2S0_DATA1__FUNC_DBG_MON_A_8_ (MTK_PIN_NO(132) | 7) - -#define MT8173_PIN_133_SDA4__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) -#define MT8173_PIN_133_SDA4__FUNC_SDA4 (MTK_PIN_NO(133) | 1) - -#define MT8173_PIN_134_SCL4__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) -#define MT8173_PIN_134_SCL4__FUNC_SCL4 (MTK_PIN_NO(134) | 1) - -#endif /* __DTS_MT8173_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi deleted file mode 100644 index 592c6bc10..000000000 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ /dev/null @@ -1,1468 +0,0 @@ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Eddie Huang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "mt8173-pinfunc.h" - -/ { - compatible = "mediatek,mt8173"; - interrupt-parent = <&sysirq>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ovl0 = &ovl0; - ovl1 = &ovl1; - rdma0 = &rdma0; - rdma1 = &rdma1; - rdma2 = &rdma2; - wdma0 = &wdma0; - wdma1 = &wdma1; - color0 = &color0; - color1 = &color1; - split0 = &split0; - split1 = &split1; - dpi0 = &dpi0; - dsi0 = &dsi0; - dsi1 = &dsi1; - mdp-rdma0 = &mdp_rdma0; - mdp-rdma1 = &mdp_rdma1; - mdp-rsz0 = &mdp_rsz0; - mdp-rsz1 = &mdp_rsz1; - mdp-rsz2 = &mdp_rsz2; - mdp-wdma0 = &mdp_wdma0; - mdp-wrot0 = &mdp_wrot0; - mdp-wrot1 = &mdp_wrot1; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - opp-507000000 { - opp-hz = /bits/ 64 <507000000>; - opp-microvolt = <859000>; - }; - opp-702000000 { - opp-hz = /bits/ 64 <702000000>; - opp-microvolt = <908000>; - }; - opp-1001000000 { - opp-hz = /bits/ 64 <1001000000>; - opp-microvolt = <983000>; - }; - opp-1105000000 { - opp-hz = /bits/ 64 <1105000000>; - opp-microvolt = <1009000>; - }; - opp-1209000000 { - opp-hz = /bits/ 64 <1209000000>; - opp-microvolt = <1034000>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1057000>; - }; - opp-1508000000 { - opp-hz = /bits/ 64 <1508000000>; - opp-microvolt = <1109000>; - }; - opp-1703000000 { - opp-hz = /bits/ 64 <1703000000>; - opp-microvolt = <1125000>; - }; - }; - - cluster1_opp: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - opp-507000000 { - opp-hz = /bits/ 64 <507000000>; - opp-microvolt = <828000>; - }; - opp-702000000 { - opp-hz = /bits/ 64 <702000000>; - opp-microvolt = <867000>; - }; - opp-1001000000 { - opp-hz = /bits/ 64 <1001000000>; - opp-microvolt = <927000>; - }; - opp-1209000000 { - opp-hz = /bits/ 64 <1209000000>; - opp-microvolt = <968000>; - }; - opp-1404000000 { - opp-hz = /bits/ 64 <1404000000>; - opp-microvolt = <1007000>; - }; - opp-1612000000 { - opp-hz = /bits/ 64 <1612000000>; - opp-microvolt = <1049000>; - }; - opp-1807000000 { - opp-hz = /bits/ 64 <1807000000>; - opp-microvolt = <1089000>; - }; - opp-2106000000 { - opp-hz = /bits/ 64 <2106000000>; - opp-microvolt = <1125000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu2>; - }; - core1 { - cpu = <&cpu3>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x000>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - #cooling-cells = <2>; - dynamic-power-coefficient = <263>; - clocks = <&infracfg CLK_INFRA_CA53SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <740>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x001>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - #cooling-cells = <2>; - dynamic-power-coefficient = <263>; - clocks = <&infracfg CLK_INFRA_CA53SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <740>; - }; - - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - #cooling-cells = <2>; - dynamic-power-coefficient = <530>; - clocks = <&infracfg CLK_INFRA_CA72SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <1024>; - }; - - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - #cooling-cells = <2>; - dynamic-power-coefficient = <530>; - clocks = <&infracfg CLK_INFRA_CA72SEL>, - <&apmixedsys CLK_APMIXED_MAINPLL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <1024>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - entry-latency-us = <639>; - exit-latency-us = <680>; - min-residency-us = <1088>; - arm,psci-suspend-param = <0x0010000>; - }; - }; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - pmu_a72 { - compatible = "arm,cortex-a72-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000001>; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; - }; - - clk26m: oscillator0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "clk26m"; - }; - - clk32k: oscillator1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - clock-output-names = "clk32k"; - }; - - cpum_ck: oscillator2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "cpum_ck"; - }; - - thermal-zones { - cpu_thermal: cpu_thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - - thermal-sensors = <&thermal>; - sustainable-power = <1500>; /* milliwatts */ - - trips { - threshold: trip-point0 { - temperature = <68000>; - hysteresis = <2000>; - type = "passive"; - }; - - target: trip-point1 { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu_crit0 { - temperature = <115000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - contribution = <3072>; - }; - map1 { - trip = <&target>; - cooling-device = <&cpu2 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - contribution = <1024>; - }; - }; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - vpu_dma_reserved: vpu_dma_mem_region@b7000000 { - compatible = "shared-dma-pool"; - reg = <0 0xb7000000 0 0x500000>; - alignment = <0x1000>; - no-map; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - arm,no-tick-in-suspend; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - topckgen: clock-controller@10000000 { - compatible = "mediatek,mt8173-topckgen"; - reg = <0 0x10000000 0 0x1000>; - #clock-cells = <1>; - }; - - infracfg: power-controller@10001000 { - compatible = "mediatek,mt8173-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pericfg: power-controller@10003000 { - compatible = "mediatek,mt8173-pericfg", "syscon"; - reg = <0 0x10003000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - syscfg_pctl_a: syscfg_pctl_a@10005000 { - compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; - }; - - pio: pinctrl@1000b000 { - compatible = "mediatek,mt8173-pinctrl"; - reg = <0 0x1000b000 0 0x1000>; - mediatek,pctl-regmap = <&syscfg_pctl_a>; - pins-are-numbered; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = , - , - ; - - hdmi_pin: xxx { - - /*hdmi htplg pin*/ - pins1 { - pinmux = ; - input-enable; - bias-pull-down; - }; - }; - - i2c0_pins_a: i2c0 { - pins1 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c1_pins_a: i2c1 { - pins1 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c2_pins_a: i2c2 { - pins1 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c3_pins_a: i2c3 { - pins1 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c4_pins_a: i2c4 { - pins1 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c6_pins_a: i2c6 { - pins1 { - pinmux = , - ; - bias-disable; - }; - }; - }; - - scpsys: power-controller@10006000 { - compatible = "mediatek,mt8173-scpsys"; - #power-domain-cells = <1>; - reg = <0 0x10006000 0 0x1000>; - clocks = <&clk26m>, - <&topckgen CLK_TOP_MM_SEL>, - <&topckgen CLK_TOP_VENC_SEL>, - <&topckgen CLK_TOP_VENC_LT_SEL>; - clock-names = "mfg", "mm", "venc", "venc_lt"; - infracfg = <&infracfg>; - }; - - watchdog: watchdog@10007000 { - compatible = "mediatek,mt8173-wdt", - "mediatek,mt6589-wdt"; - reg = <0 0x10007000 0 0x100>; - }; - - timer: timer@10008000 { - compatible = "mediatek,mt8173-timer", - "mediatek,mt6577-timer"; - reg = <0 0x10008000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_CLK_13M>, - <&topckgen CLK_TOP_RTC_SEL>; - }; - - pwrap: pwrap@1000d000 { - compatible = "mediatek,mt8173-pwrap"; - reg = <0 0x1000d000 0 0x1000>; - reg-names = "pwrap"; - interrupts = ; - resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; - reset-names = "pwrap"; - clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; - clock-names = "spi", "wrap"; - }; - - cec: cec@10013000 { - compatible = "mediatek,mt8173-cec"; - reg = <0 0x10013000 0 0xbc>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_CEC>; - status = "disabled"; - }; - - vpu: vpu@10020000 { - compatible = "mediatek,mt8173-vpu"; - reg = <0 0x10020000 0 0x30000>, - <0 0x10050000 0 0x100>; - reg-names = "tcm", "cfg_reg"; - interrupts = ; - clocks = <&topckgen CLK_TOP_SCP_SEL>; - clock-names = "main"; - memory-region = <&vpu_dma_reserved>; - }; - - sysirq: intpol-controller@10200620 { - compatible = "mediatek,mt8173-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200620 0 0x20>; - }; - - iommu: iommu@10205000 { - compatible = "mediatek,mt8173-m4u"; - reg = <0 0x10205000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_M4U>; - clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2 - &larb3 &larb4 &larb5>; - #iommu-cells = <1>; - }; - - efuse: efuse@10206000 { - compatible = "mediatek,mt8173-efuse"; - reg = <0 0x10206000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - thermal_calibration: calib@528 { - reg = <0x528 0xc>; - }; - }; - - apmixedsys: clock-controller@10209000 { - compatible = "mediatek,mt8173-apmixedsys"; - reg = <0 0x10209000 0 0x1000>; - #clock-cells = <1>; - }; - - hdmi_phy: hdmi-phy@10209100 { - compatible = "mediatek,mt8173-hdmi-phy"; - reg = <0 0x10209100 0 0x24>; - clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; - clock-names = "pll_ref"; - clock-output-names = "hdmitx_dig_cts"; - mediatek,ibias = <0xa>; - mediatek,ibias_up = <0x1c>; - #clock-cells = <0>; - #phy-cells = <0>; - status = "disabled"; - }; - - gce: mailbox@10212000 { - compatible = "mediatek,mt8173-gce"; - reg = <0 0x10212000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_GCE>; - clock-names = "gce"; - #mbox-cells = <2>; - }; - - mipi_tx0: mipi-dphy@10215000 { - compatible = "mediatek,mt8173-mipi-tx"; - reg = <0 0x10215000 0 0x1000>; - clocks = <&clk26m>; - clock-output-names = "mipi_tx0_pll"; - #clock-cells = <0>; - #phy-cells = <0>; - status = "disabled"; - }; - - mipi_tx1: mipi-dphy@10216000 { - compatible = "mediatek,mt8173-mipi-tx"; - reg = <0 0x10216000 0 0x1000>; - clocks = <&clk26m>; - clock-output-names = "mipi_tx1_pll"; - #clock-cells = <0>; - #phy-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@10221000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; - reg = <0 0x10221000 0 0x1000>, - <0 0x10222000 0 0x2000>, - <0 0x10224000 0 0x2000>, - <0 0x10226000 0 0x2000>; - interrupts = ; - }; - - auxadc: auxadc@11001000 { - compatible = "mediatek,mt8173-auxadc"; - reg = <0 0x11001000 0 0x1000>; - clocks = <&pericfg CLK_PERI_AUXADC>; - clock-names = "main"; - #io-channel-cells = <1>; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt8173-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt8173-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt8173-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart3: serial@11005000 { - compatible = "mediatek,mt8173-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11005000 0 0x400>; - interrupts = ; - clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - i2c0: i2c@11007000 { - compatible = "mediatek,mt8173-i2c"; - reg = <0 0x11007000 0 0x70>, - <0 0x11000100 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C0>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@11008000 { - compatible = "mediatek,mt8173-i2c"; - reg = <0 0x11008000 0 0x70>, - <0 0x11000180 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C1>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@11009000 { - compatible = "mediatek,mt8173-i2c"; - reg = <0 0x11009000 0 0x70>, - <0 0x11000200 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C2>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi: spi@1100a000 { - compatible = "mediatek,mt8173-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100a000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&pericfg CLK_PERI_SPI0>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - thermal: thermal@1100b000 { - #thermal-sensor-cells = <0>; - compatible = "mediatek,mt8173-thermal"; - reg = <0 0x1100b000 0 0x1000>; - interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; - clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; - clock-names = "therm", "auxadc"; - resets = <&pericfg MT8173_PERI_THERM_SW_RST>; - mediatek,auxadc = <&auxadc>; - mediatek,apmixedsys = <&apmixedsys>; - nvmem-cells = <&thermal_calibration>; - nvmem-cell-names = "calibration-data"; - }; - - nor_flash: spi@1100d000 { - compatible = "mediatek,mt8173-nor"; - reg = <0 0x1100d000 0 0xe0>; - clocks = <&pericfg CLK_PERI_SPI>, - <&topckgen CLK_TOP_SPINFI_IFR_SEL>; - clock-names = "spi", "sf"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@11010000 { - compatible = "mediatek,mt8173-i2c"; - reg = <0 0x11010000 0 0x70>, - <0 0x11000280 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C3>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins_a>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@11011000 { - compatible = "mediatek,mt8173-i2c"; - reg = <0 0x11011000 0 0x70>, - <0 0x11000300 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C4>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_a>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hdmiddc0: i2c@11012000 { - compatible = "mediatek,mt8173-hdmi-ddc"; - interrupts = ; - reg = <0 0x11012000 0 0x1C>; - clocks = <&pericfg CLK_PERI_I2C5>; - clock-names = "ddc-i2c"; - }; - - i2c6: i2c@11013000 { - compatible = "mediatek,mt8173-i2c"; - reg = <0 0x11013000 0 0x70>, - <0 0x11000080 0 0x80>; - interrupts = ; - clock-div = <16>; - clocks = <&pericfg CLK_PERI_I2C6>, - <&pericfg CLK_PERI_AP_DMA>; - clock-names = "main", "dma"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_pins_a>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - afe: audio-controller@11220000 { - compatible = "mediatek,mt8173-afe-pcm"; - reg = <0 0x11220000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; - clocks = <&infracfg CLK_INFRA_AUDIO>, - <&topckgen CLK_TOP_AUDIO_SEL>, - <&topckgen CLK_TOP_AUD_INTBUS_SEL>, - <&topckgen CLK_TOP_APLL1_DIV0>, - <&topckgen CLK_TOP_APLL2_DIV0>, - <&topckgen CLK_TOP_I2S0_M_SEL>, - <&topckgen CLK_TOP_I2S1_M_SEL>, - <&topckgen CLK_TOP_I2S2_M_SEL>, - <&topckgen CLK_TOP_I2S3_M_SEL>, - <&topckgen CLK_TOP_I2S3_B_SEL>; - clock-names = "infra_sys_audio_clk", - "top_pdn_audio", - "top_pdn_aud_intbus", - "bck0", - "bck1", - "i2s0_m", - "i2s1_m", - "i2s2_m", - "i2s3_m", - "i2s3_b"; - assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, - <&topckgen CLK_TOP_AUD_2_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, - <&topckgen CLK_TOP_APLL2>; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt8173-mmc"; - reg = <0 0x11230000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_MSDC30_0>, - <&topckgen CLK_TOP_MSDC50_0_H_SEL>; - clock-names = "source", "hclk"; - status = "disabled"; - }; - - mmc1: mmc@11240000 { - compatible = "mediatek,mt8173-mmc"; - reg = <0 0x11240000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_MSDC30_1>, - <&topckgen CLK_TOP_AXI_SEL>; - clock-names = "source", "hclk"; - status = "disabled"; - }; - - mmc2: mmc@11250000 { - compatible = "mediatek,mt8173-mmc"; - reg = <0 0x11250000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_MSDC30_2>, - <&topckgen CLK_TOP_AXI_SEL>; - clock-names = "source", "hclk"; - status = "disabled"; - }; - - mmc3: mmc@11260000 { - compatible = "mediatek,mt8173-mmc"; - reg = <0 0x11260000 0 0x1000>; - interrupts = ; - clocks = <&pericfg CLK_PERI_MSDC30_3>, - <&topckgen CLK_TOP_MSDC50_2_H_SEL>; - clock-names = "source", "hclk"; - status = "disabled"; - }; - - ssusb: usb@11271000 { - compatible = "mediatek,mt8173-mtu3"; - reg = <0 0x11271000 0 0x3000>, - <0 0x11280700 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&u2port0 PHY_TYPE_USB2>, - <&u3port0 PHY_TYPE_USB3>, - <&u2port1 PHY_TYPE_USB2>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; - clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; - clock-names = "sys_ck", "ref_ck"; - mediatek,syscon-wakeup = <&pericfg 0x400 1>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - usb_host: xhci@11270000 { - compatible = "mediatek,mt8173-xhci"; - reg = <0 0x11270000 0 0x1000>; - reg-names = "mac"; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; - clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; - clock-names = "sys_ck", "ref_ck"; - status = "disabled"; - }; - }; - - u3phy: usb-phy@11290000 { - compatible = "mediatek,mt8173-u3phy"; - reg = <0 0x11290000 0 0x800>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "okay"; - - u2port0: usb-phy@11290800 { - reg = <0 0x11290800 0 0x100>; - clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u3port0: usb-phy@11290900 { - reg = <0 0x11290900 0 0x700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - - u2port1: usb-phy@11291000 { - reg = <0 0x11291000 0 0x100>; - clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - mmsys: syscon@14000000 { - compatible = "mediatek,mt8173-mmsys", "syscon"; - reg = <0 0x14000000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; - assigned-clock-rates = <400000000>; - #clock-cells = <1>; - mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, - <&gce 1 CMDQ_THR_PRIO_HIGHEST>; - mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; - }; - - mdp_rdma0: rdma@14001000 { - compatible = "mediatek,mt8173-mdp-rdma", - "mediatek,mt8173-mdp"; - reg = <0 0x14001000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RDMA0>, - <&mmsys CLK_MM_MUTEX_32K>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_RDMA0>; - mediatek,larb = <&larb0>; - mediatek,vpu = <&vpu>; - }; - - mdp_rdma1: rdma@14002000 { - compatible = "mediatek,mt8173-mdp-rdma"; - reg = <0 0x14002000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RDMA1>, - <&mmsys CLK_MM_MUTEX_32K>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_RDMA1>; - mediatek,larb = <&larb4>; - }; - - mdp_rsz0: rsz@14003000 { - compatible = "mediatek,mt8173-mdp-rsz"; - reg = <0 0x14003000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RSZ0>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - }; - - mdp_rsz1: rsz@14004000 { - compatible = "mediatek,mt8173-mdp-rsz"; - reg = <0 0x14004000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RSZ1>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - }; - - mdp_rsz2: rsz@14005000 { - compatible = "mediatek,mt8173-mdp-rsz"; - reg = <0 0x14005000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_RSZ2>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - }; - - mdp_wdma0: wdma@14006000 { - compatible = "mediatek,mt8173-mdp-wdma"; - reg = <0 0x14006000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_WDMA>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_WDMA>; - mediatek,larb = <&larb0>; - }; - - mdp_wrot0: wrot@14007000 { - compatible = "mediatek,mt8173-mdp-wrot"; - reg = <0 0x14007000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_WROT0>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_WROT0>; - mediatek,larb = <&larb0>; - }; - - mdp_wrot1: wrot@14008000 { - compatible = "mediatek,mt8173-mdp-wrot"; - reg = <0 0x14008000 0 0x1000>; - clocks = <&mmsys CLK_MM_MDP_WROT1>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - iommus = <&iommu M4U_PORT_MDP_WROT1>; - mediatek,larb = <&larb4>; - }; - - ovl0: ovl@1400c000 { - compatible = "mediatek,mt8173-disp-ovl"; - reg = <0 0x1400c000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_OVL0>; - iommus = <&iommu M4U_PORT_DISP_OVL0>; - mediatek,larb = <&larb0>; - mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; - }; - - ovl1: ovl@1400d000 { - compatible = "mediatek,mt8173-disp-ovl"; - reg = <0 0x1400d000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_OVL1>; - iommus = <&iommu M4U_PORT_DISP_OVL1>; - mediatek,larb = <&larb4>; - mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; - }; - - rdma0: rdma@1400e000 { - compatible = "mediatek,mt8173-disp-rdma"; - reg = <0 0x1400e000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_RDMA0>; - iommus = <&iommu M4U_PORT_DISP_RDMA0>; - mediatek,larb = <&larb0>; - mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; - }; - - rdma1: rdma@1400f000 { - compatible = "mediatek,mt8173-disp-rdma"; - reg = <0 0x1400f000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_RDMA1>; - iommus = <&iommu M4U_PORT_DISP_RDMA1>; - mediatek,larb = <&larb4>; - mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; - }; - - rdma2: rdma@14010000 { - compatible = "mediatek,mt8173-disp-rdma"; - reg = <0 0x14010000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_RDMA2>; - iommus = <&iommu M4U_PORT_DISP_RDMA2>; - mediatek,larb = <&larb4>; - mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; - }; - - wdma0: wdma@14011000 { - compatible = "mediatek,mt8173-disp-wdma"; - reg = <0 0x14011000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_WDMA0>; - iommus = <&iommu M4U_PORT_DISP_WDMA0>; - mediatek,larb = <&larb0>; - mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; - }; - - wdma1: wdma@14012000 { - compatible = "mediatek,mt8173-disp-wdma"; - reg = <0 0x14012000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_WDMA1>; - iommus = <&iommu M4U_PORT_DISP_WDMA1>; - mediatek,larb = <&larb4>; - mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; - }; - - color0: color@14013000 { - compatible = "mediatek,mt8173-disp-color"; - reg = <0 0x14013000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_COLOR0>; - mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; - }; - - color1: color@14014000 { - compatible = "mediatek,mt8173-disp-color"; - reg = <0 0x14014000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_COLOR1>; - mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; - }; - - aal@14015000 { - compatible = "mediatek,mt8173-disp-aal"; - reg = <0 0x14015000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_AAL>; - mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; - }; - - gamma@14016000 { - compatible = "mediatek,mt8173-disp-gamma"; - reg = <0 0x14016000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_GAMMA>; - mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; - }; - - merge@14017000 { - compatible = "mediatek,mt8173-disp-merge"; - reg = <0 0x14017000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_MERGE>; - }; - - split0: split@14018000 { - compatible = "mediatek,mt8173-disp-split"; - reg = <0 0x14018000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_SPLIT0>; - }; - - split1: split@14019000 { - compatible = "mediatek,mt8173-disp-split"; - reg = <0 0x14019000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_SPLIT1>; - }; - - ufoe@1401a000 { - compatible = "mediatek,mt8173-disp-ufoe"; - reg = <0 0x1401a000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DISP_UFOE>; - }; - - dsi0: dsi@1401b000 { - compatible = "mediatek,mt8173-dsi"; - reg = <0 0x1401b000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DSI0_ENGINE>, - <&mmsys CLK_MM_DSI0_DIGITAL>, - <&mipi_tx0>; - clock-names = "engine", "digital", "hs"; - phys = <&mipi_tx0>; - phy-names = "dphy"; - status = "disabled"; - }; - - dsi1: dsi@1401c000 { - compatible = "mediatek,mt8173-dsi"; - reg = <0 0x1401c000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DSI1_ENGINE>, - <&mmsys CLK_MM_DSI1_DIGITAL>, - <&mipi_tx1>; - clock-names = "engine", "digital", "hs"; - phys = <&mipi_tx1>; - phy-names = "dphy"; - status = "disabled"; - }; - - dpi0: dpi@1401d000 { - compatible = "mediatek,mt8173-dpi"; - reg = <0 0x1401d000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_DPI_PIXEL>, - <&mmsys CLK_MM_DPI_ENGINE>, - <&apmixedsys CLK_APMIXED_TVDPLL>; - clock-names = "pixel", "engine", "pll"; - status = "disabled"; - - port { - dpi0_out: endpoint { - remote-endpoint = <&hdmi0_in>; - }; - }; - }; - - pwm0: pwm@1401e000 { - compatible = "mediatek,mt8173-disp-pwm", - "mediatek,mt6595-disp-pwm"; - reg = <0 0x1401e000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&mmsys CLK_MM_DISP_PWM026M>, - <&mmsys CLK_MM_DISP_PWM0MM>; - clock-names = "main", "mm"; - status = "disabled"; - }; - - pwm1: pwm@1401f000 { - compatible = "mediatek,mt8173-disp-pwm", - "mediatek,mt6595-disp-pwm"; - reg = <0 0x1401f000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&mmsys CLK_MM_DISP_PWM126M>, - <&mmsys CLK_MM_DISP_PWM1MM>; - clock-names = "main", "mm"; - status = "disabled"; - }; - - mutex: mutex@14020000 { - compatible = "mediatek,mt8173-disp-mutex"; - reg = <0 0x14020000 0 0x1000>; - interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_MUTEX_32K>; - mediatek,gce-events = , - ; - }; - - larb0: larb@14021000 { - compatible = "mediatek,mt8173-smi-larb"; - reg = <0 0x14021000 0 0x1000>; - mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_SMI_LARB0>, - <&mmsys CLK_MM_SMI_LARB0>; - clock-names = "apb", "smi"; - }; - - smi_common: smi@14022000 { - compatible = "mediatek,mt8173-smi-common"; - reg = <0 0x14022000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_SMI_COMMON>, - <&mmsys CLK_MM_SMI_COMMON>; - clock-names = "apb", "smi"; - }; - - od@14023000 { - compatible = "mediatek,mt8173-disp-od"; - reg = <0 0x14023000 0 0x1000>; - clocks = <&mmsys CLK_MM_DISP_OD>; - }; - - hdmi0: hdmi@14025000 { - compatible = "mediatek,mt8173-hdmi"; - reg = <0 0x14025000 0 0x400>; - interrupts = ; - clocks = <&mmsys CLK_MM_HDMI_PIXEL>, - <&mmsys CLK_MM_HDMI_PLLCK>, - <&mmsys CLK_MM_HDMI_AUDIO>, - <&mmsys CLK_MM_HDMI_SPDIF>; - clock-names = "pixel", "pll", "bclk", "spdif"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pin>; - phys = <&hdmi_phy>; - phy-names = "hdmi"; - mediatek,syscon-hdmi = <&mmsys 0x900>; - assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; - assigned-clock-parents = <&hdmi_phy>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - hdmi0_in: endpoint { - remote-endpoint = <&dpi0_out>; - }; - }; - }; - }; - - larb4: larb@14027000 { - compatible = "mediatek,mt8173-smi-larb"; - reg = <0 0x14027000 0 0x1000>; - mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_SMI_LARB4>, - <&mmsys CLK_MM_SMI_LARB4>; - clock-names = "apb", "smi"; - }; - - imgsys: clock-controller@15000000 { - compatible = "mediatek,mt8173-imgsys", "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb2: larb@15001000 { - compatible = "mediatek,mt8173-smi-larb"; - reg = <0 0x15001000 0 0x1000>; - mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; - clocks = <&imgsys CLK_IMG_LARB2_SMI>, - <&imgsys CLK_IMG_LARB2_SMI>; - clock-names = "apb", "smi"; - }; - - vdecsys: clock-controller@16000000 { - compatible = "mediatek,mt8173-vdecsys", "syscon"; - reg = <0 0x16000000 0 0x1000>; - #clock-cells = <1>; - }; - - vcodec_dec: vcodec@16000000 { - compatible = "mediatek,mt8173-vcodec-dec"; - reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ - <0 0x16020000 0 0x1000>, /* VDEC_MISC */ - <0 0x16021000 0 0x800>, /* VDEC_LD */ - <0 0x16021800 0 0x800>, /* VDEC_TOP */ - <0 0x16022000 0 0x1000>, /* VDEC_CM */ - <0 0x16023000 0 0x1000>, /* VDEC_AD */ - <0 0x16024000 0 0x1000>, /* VDEC_AV */ - <0 0x16025000 0 0x1000>, /* VDEC_PP */ - <0 0x16026800 0 0x800>, /* VDEC_HWD */ - <0 0x16027000 0 0x800>, /* VDEC_HWQ */ - <0 0x16027800 0 0x800>, /* VDEC_HWB */ - <0 0x16028400 0 0x400>; /* VDEC_HWG */ - interrupts = ; - mediatek,larb = <&larb1>; - iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, - <&iommu M4U_PORT_HW_VDEC_PP_EXT>, - <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, - <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, - <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, - <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, - <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, - <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; - mediatek,vpu = <&vpu>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; - clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, - <&topckgen CLK_TOP_UNIVPLL_D2>, - <&topckgen CLK_TOP_CCI400_SEL>, - <&topckgen CLK_TOP_VDEC_SEL>, - <&topckgen CLK_TOP_VCODECPLL>, - <&apmixedsys CLK_APMIXED_VENCPLL>, - <&topckgen CLK_TOP_VENC_LT_SEL>, - <&topckgen CLK_TOP_VCODECPLL_370P5>; - clock-names = "vcodecpll", - "univpll_d2", - "clk_cci400_sel", - "vdec_sel", - "vdecpll", - "vencpll", - "venc_lt_sel", - "vdec_bus_clk_src"; - assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, - <&topckgen CLK_TOP_CCI400_SEL>, - <&topckgen CLK_TOP_VDEC_SEL>, - <&apmixedsys CLK_APMIXED_VCODECPLL>, - <&apmixedsys CLK_APMIXED_VENCPLL>; - assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, - <&topckgen CLK_TOP_UNIVPLL_D2>, - <&topckgen CLK_TOP_VCODECPLL>; - assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; - }; - - larb1: larb@16010000 { - compatible = "mediatek,mt8173-smi-larb"; - reg = <0 0x16010000 0 0x1000>; - mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; - clocks = <&vdecsys CLK_VDEC_CKEN>, - <&vdecsys CLK_VDEC_LARB_CKEN>; - clock-names = "apb", "smi"; - }; - - vencsys: clock-controller@18000000 { - compatible = "mediatek,mt8173-vencsys", "syscon"; - reg = <0 0x18000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb3: larb@18001000 { - compatible = "mediatek,mt8173-smi-larb"; - reg = <0 0x18001000 0 0x1000>; - mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; - clocks = <&vencsys CLK_VENC_CKE1>, - <&vencsys CLK_VENC_CKE0>; - clock-names = "apb", "smi"; - }; - - vcodec_enc: vcodec@18002000 { - compatible = "mediatek,mt8173-vcodec-enc"; - reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ - <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ - interrupts = , - ; - mediatek,larb = <&larb3>, - <&larb5>; - iommus = <&iommu M4U_PORT_VENC_RCPU>, - <&iommu M4U_PORT_VENC_REC>, - <&iommu M4U_PORT_VENC_BSDMA>, - <&iommu M4U_PORT_VENC_SV_COMV>, - <&iommu M4U_PORT_VENC_RD_COMV>, - <&iommu M4U_PORT_VENC_CUR_LUMA>, - <&iommu M4U_PORT_VENC_CUR_CHROMA>, - <&iommu M4U_PORT_VENC_REF_LUMA>, - <&iommu M4U_PORT_VENC_REF_CHROMA>, - <&iommu M4U_PORT_VENC_NBM_RDMA>, - <&iommu M4U_PORT_VENC_NBM_WDMA>, - <&iommu M4U_PORT_VENC_RCPU_SET2>, - <&iommu M4U_PORT_VENC_REC_FRM_SET2>, - <&iommu M4U_PORT_VENC_BSDMA_SET2>, - <&iommu M4U_PORT_VENC_SV_COMA_SET2>, - <&iommu M4U_PORT_VENC_RD_COMA_SET2>, - <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, - <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, - <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, - <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; - mediatek,vpu = <&vpu>; - clocks = <&topckgen CLK_TOP_VENCPLL_D2>, - <&topckgen CLK_TOP_VENC_SEL>, - <&topckgen CLK_TOP_UNIVPLL1_D2>, - <&topckgen CLK_TOP_VENC_LT_SEL>; - clock-names = "venc_sel_src", - "venc_sel", - "venc_lt_sel_src", - "venc_lt_sel"; - assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, - <&topckgen CLK_TOP_VENC_LT_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>, - <&topckgen CLK_TOP_VCODECPLL_370P5>; - }; - - jpegdec: jpegdec@18004000 { - compatible = "mediatek,mt8173-jpgdec"; - reg = <0 0x18004000 0 0x1000>; - interrupts = ; - clocks = <&vencsys CLK_VENC_CKE0>, - <&vencsys CLK_VENC_CKE3>; - clock-names = "jpgdec-smi", - "jpgdec"; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; - mediatek,larb = <&larb3>; - iommus = <&iommu M4U_PORT_JPGDEC_WDMA>, - <&iommu M4U_PORT_JPGDEC_BSDMA>; - }; - - vencltsys: clock-controller@19000000 { - compatible = "mediatek,mt8173-vencltsys", "syscon"; - reg = <0 0x19000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb5: larb@19001000 { - compatible = "mediatek,mt8173-smi-larb"; - reg = <0 0x19001000 0 0x1000>; - mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; - clocks = <&vencltsys CLK_VENCLT_CKE1>, - <&vencltsys CLK_VENCLT_CKE0>; - clock-names = "apb", "smi"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts deleted file mode 100644 index cba2d8933..000000000 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ /dev/null @@ -1,394 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (c) 2018 MediaTek Inc. - * Author: Ben Ho - * Erin Lo - */ - -/dts-v1/; -#include "mt8183.dtsi" -#include "mt6358.dtsi" - -/ { - model = "MediaTek MT8183 evaluation board"; - compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; - - aliases { - serial0 = &uart0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x80000000>; - }; - - chosen { - stdout-path = "serial0:921600n8"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - scp_mem_reserved: scp_mem_region { - compatible = "shared-dma-pool"; - reg = <0 0x50000000 0 0x2900000>; - no-map; - }; - }; -}; - -&auxadc { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins_0>; - status = "okay"; - clock-frequency = <100000>; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins_1>; - status = "okay"; - clock-frequency = <100000>; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins_2>; - status = "okay"; - clock-frequency = <100000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins_3>; - status = "okay"; - clock-frequency = <100000>; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins_4>; - status = "okay"; - clock-frequency = <1000000>; -}; - -&i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins_5>; - status = "okay"; - clock-frequency = <1000000>; -}; - -&mmc0 { - status = "okay"; - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - cap-mmc-hw-reset; - no-sdio; - no-sd; - hs400-ds-delay = <0x12814>; - vmmc-supply = <&mt6358_vemc_reg>; - vqmmc-supply = <&mt6358_vio18_reg>; - assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; - assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; - non-removable; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_uhs>; - bus-width = <4>; - max-frequency = <200000000>; - cap-sd-highspeed; - sd-uhs-sdr50; - sd-uhs-sdr104; - cap-sdio-irq; - no-mmc; - no-sd; - vmmc-supply = <&mt6358_vmch_reg>; - vqmmc-supply = <&mt6358_vmc_reg>; - keep-power-in-suspend; - enable-sdio-wakeup; - non-removable; -}; - -&pio { - i2c_pins_0: i2c0{ - pins_i2c{ - pinmux = , - ; - mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; - }; - }; - - i2c_pins_1: i2c1{ - pins_i2c{ - pinmux = , - ; - mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; - }; - }; - - i2c_pins_2: i2c2{ - pins_i2c{ - pinmux = , - ; - mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; - }; - }; - - i2c_pins_3: i2c3{ - pins_i2c{ - pinmux = , - ; - mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; - }; - }; - - i2c_pins_4: i2c4{ - pins_i2c{ - pinmux = , - ; - mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; - }; - }; - - i2c_pins_5: i2c5{ - pins_i2c{ - pinmux = , - ; - mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; - }; - }; - - spi_pins_0: spi0{ - pins_spi{ - pinmux = , - , - , - ; - bias-disable; - }; - }; - - mmc0_pins_default: mmc0default { - pins_cmd_dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - bias-pull-up; - }; - - pins_clk { - pinmux = ; - bias-pull-down; - }; - - pins_rst { - pinmux = ; - bias-pull-up; - }; - }; - - mmc0_pins_uhs: mmc0 { - pins_cmd_dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - drive-strength = ; - bias-pull-up = ; - }; - - pins_clk { - pinmux = ; - drive-strength = ; - bias-pull-down = ; - }; - - pins_ds { - pinmux = ; - drive-strength = ; - bias-pull-down = ; - }; - - pins_rst { - pinmux = ; - drive-strength = ; - bias-pull-up; - }; - }; - - mmc1_pins_default: mmc1default { - pins_cmd_dat { - pinmux = , - , - , - , - ; - input-enable; - bias-pull-up; - }; - - pins_clk { - pinmux = ; - input-enable; - bias-pull-down; - }; - - pins_pmu { - pinmux = , - ; - output-high; - }; - }; - - mmc1_pins_uhs: mmc1 { - pins_cmd_dat { - pinmux = , - , - , - , - ; - drive-strength = ; - input-enable; - bias-pull-up = ; - }; - - pins_clk { - pinmux = ; - drive-strength = ; - bias-pull-down = ; - input-enable; - }; - }; - - spi_pins_1: spi1{ - pins_spi{ - pinmux = , - , - , - ; - bias-disable; - }; - }; - - spi_pins_2: spi2{ - pins_spi{ - pinmux = , - , - , - ; - bias-disable; - }; - }; - - spi_pins_3: spi3{ - pins_spi{ - pinmux = , - , - , - ; - bias-disable; - }; - }; - - spi_pins_4: spi4{ - pins_spi{ - pinmux = , - , - , - ; - bias-disable; - }; - }; - - spi_pins_5: spi5{ - pins_spi{ - pinmux = , - , - , - ; - bias-disable; - }; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins_0>; - mediatek,pad-select = <0>; - status = "okay"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins_1>; - mediatek,pad-select = <0>; - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins_2>; - mediatek,pad-select = <0>; - status = "okay"; -}; - -&spi3 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins_3>; - mediatek,pad-select = <0>; - status = "okay"; -}; - -&spi4 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins_4>; - mediatek,pad-select = <0>; - status = "okay"; -}; - -&spi5 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins_5>; - mediatek,pad-select = <0>; - status = "okay"; - -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts deleted file mode 100644 index 47113e275..000000000 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2019 Google LLC - * - * Device-tree for Krane sku176. - * - * SKU is a 8-bit value (0xb0 == 176): - * - Bits 7..4: Panel ID: 0xb (BOE) - * - Bits 3..0: SKU ID: 0x0 (default) - */ - -/dts-v1/; -#include "mt8183-kukui-krane.dtsi" - -/ { - model = "MediaTek krane sku176 board"; - compatible = "google,krane-sku176", "google,krane", "mediatek,mt8183"; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi deleted file mode 100644 index fbc471ccf..000000000 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi +++ /dev/null @@ -1,343 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2019 Google LLC - */ - -#include "mt8183-kukui.dtsi" - -/ { - ppvarn_lcd: ppvarn-lcd { - compatible = "regulator-fixed"; - regulator-name = "ppvarn_lcd"; - pinctrl-names = "default"; - pinctrl-0 = <&ppvarn_lcd_en>; - - enable-active-high; - - gpio = <&pio 66 GPIO_ACTIVE_HIGH>; - }; - - ppvarp_lcd: ppvarp-lcd { - compatible = "regulator-fixed"; - regulator-name = "ppvarp_lcd"; - pinctrl-names = "default"; - pinctrl-0 = <&ppvarp_lcd_en>; - - enable-active-high; - - gpio = <&pio 166 GPIO_ACTIVE_HIGH>; - }; - - pp1800_lcd: pp1800-lcd { - compatible = "regulator-fixed"; - regulator-name = "pp1800_lcd"; - pinctrl-names = "default"; - pinctrl-0 = <&pp1800_lcd_en>; - - enable-active-high; - - gpio = <&pio 36 GPIO_ACTIVE_HIGH>; - }; -}; - -&bluetooth { - firmware-name = "nvm_00440302_i2s_eu.bin"; -}; - -&i2c0 { - status = "okay"; - - touchscreen4: touchscreen@5d { - compatible = "hid-over-i2c"; - reg = <0x5d>; - pinctrl-names = "default"; - pinctrl-0 = <&open_touch>; - - interrupt-parent = <&pio>; - interrupts = <155 IRQ_TYPE_EDGE_FALLING>; - - post-power-on-delay-ms = <10>; - hid-descr-addr = <0x0001>; - }; -}; - -&mt6358_vcama2_reg { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "okay"; - clock-frequency = <400000>; - - eeprom@58 { - compatible = "atmel,24c32"; - reg = <0x58>; - pagesize = <32>; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - status = "okay"; - clock-frequency = <400000>; - - eeprom@54 { - compatible = "atmel,24c32"; - reg = <0x54>; - pagesize = <32>; - }; -}; - -&pio { - /* 192 lines */ - gpio-line-names = - "SPI_AP_EC_CS_L", - "SPI_AP_EC_MOSI", - "SPI_AP_EC_CLK", - "I2S3_DO", - "USB_PD_INT_ODL", - "", - "", - "", - "", - "IT6505_HPD_L", - "I2S3_TDM_D3", - "SOC_I2C6_1V8_SCL", - "SOC_I2C6_1V8_SDA", - "DPI_D0", - "DPI_D1", - "DPI_D2", - "DPI_D3", - "DPI_D4", - "DPI_D5", - "DPI_D6", - "DPI_D7", - "DPI_D8", - "DPI_D9", - "DPI_D10", - "DPI_D11", - "DPI_HSYNC", - "DPI_VSYNC", - "DPI_DE", - "DPI_CK", - "AP_MSDC1_CLK", - "AP_MSDC1_DAT3", - "AP_MSDC1_CMD", - "AP_MSDC1_DAT0", - "AP_MSDC1_DAT2", - "AP_MSDC1_DAT1", - "", - "", - "", - "", - "", - "", - "OTG_EN", - "DRVBUS", - "DISP_PWM", - "DSI_TE", - "LCM_RST_1V8", - "AP_CTS_WIFI_RTS", - "AP_RTS_WIFI_CTS", - "SOC_I2C5_1V8_SCL", - "SOC_I2C5_1V8_SDA", - "SOC_I2C3_1V8_SCL", - "SOC_I2C3_1V8_SDA", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "SOC_I2C1_1V8_SDA", - "SOC_I2C0_1V8_SDA", - "SOC_I2C0_1V8_SCL", - "SOC_I2C1_1V8_SCL", - "AP_SPI_H1_MISO", - "AP_SPI_H1_CS_L", - "AP_SPI_H1_MOSI", - "AP_SPI_H1_CLK", - "I2S5_BCK", - "I2S5_LRCK", - "I2S5_DO", - "BOOTBLOCK_EN_L", - "MT8183_KPCOL0", - "SPI_AP_EC_MISO", - "UART_DBG_TX_AP_RX", - "UART_AP_TX_DBG_RX", - "I2S2_MCK", - "I2S2_BCK", - "CLK_5M_WCAM", - "CLK_2M_UCAM", - "I2S2_LRCK", - "I2S2_DI", - "SOC_I2C2_1V8_SCL", - "SOC_I2C2_1V8_SDA", - "SOC_I2C4_1V8_SCL", - "SOC_I2C4_1V8_SDA", - "", - "SCL8", - "SDA8", - "FCAM_PWDN_L", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "I2S_PMIC", - "I2S_PMIC", - "I2S_PMIC", - "I2S_PMIC", - "I2S_PMIC", - "I2S_PMIC", - "I2S_PMIC", - "I2S_PMIC", - "", - "", - "", - "", - "", - "", - /* - * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics - * call it BIOS_FLASH_WP_R_L. - */ - "AP_FLASH_WP_L", - "EC_AP_INT_ODL", - "IT6505_INT_ODL", - "H1_INT_OD_L", - "", - "", - "", - "", - "", - "", - "", - "AP_SPI_FLASH_MISO", - "AP_SPI_FLASH_CS_L", - "AP_SPI_FLASH_MOSI", - "AP_SPI_FLASH_CLK", - "DA7219_IRQ", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - ""; - - ppvarp_lcd_en: ppvarp-lcd-en { - pins1 { - pinmux = ; - output-low; - }; - }; - - ppvarn_lcd_en: ppvarn-lcd-en { - pins1 { - pinmux = ; - output-low; - }; - }; - - pp1800_lcd_en: pp1800-lcd-en { - pins1 { - pinmux = ; - output-low; - }; - }; - - open_touch: open_touch { - irq_pin { - pinmux = ; - input-enable; - bias-pull-up; - }; - - rst_pin { - pinmux = ; - - /* - * The pen driver doesn't currently support driving - * this reset line. By specifying output-high here - * we're relying on the fact that this pin has a default - * pulldown at boot (which makes sure the pen was in - * reset if it was powered) and then we set it high here - * to take it out of reset. Better would be if the pen - * driver could control this and we could remove - * "output-high" here. - */ - output-high; - }; - }; -}; - -&qca_wifi { - qcom,ath10k-calibration-variant = "LE_Krane"; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi deleted file mode 100644 index 85f7c33ba..000000000 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ /dev/null @@ -1,818 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (c) 2018 MediaTek Inc. - * Author: Ben Ho - * Erin Lo - */ - -#include -#include -#include "mt8183.dtsi" -#include "mt6358.dtsi" - -/ { - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x80000000>; - }; - - clk32k: oscillator1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "clk32k"; - }; - - it6505_pp18_reg: regulator0 { - compatible = "regulator-fixed"; - regulator-name = "it6505_pp18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&pio 178 0>; - enable-active-high; - }; - - lcd_pp3300: regulator1 { - compatible = "regulator-fixed"; - regulator-name = "lcd_pp3300"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - bl_pp5000: regulator2 { - compatible = "regulator-fixed"; - regulator-name = "bl_pp5000"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - mmc1_fixed_power: regulator3 { - compatible = "regulator-fixed"; - regulator-name = "mmc1_power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - mmc1_fixed_io: regulator4 { - compatible = "regulator-fixed"; - regulator-name = "mmc1_io"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pp1800_alw: regulator5 { - compatible = "regulator-fixed"; - regulator-name = "pp1800_alw"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pp3300_alw: regulator6 { - compatible = "regulator-fixed"; - regulator-name = "pp3300_alw"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - scp_mem_reserved: scp_mem_region { - compatible = "shared-dma-pool"; - reg = <0 0x50000000 0 0x2900000>; - no-map; - }; - }; - - max98357a: codec0 { - compatible = "maxim,max98357a"; - sdmode-gpios = <&pio 175 0>; - }; - - btsco: codec1 { - compatible = "linux,bt-sco"; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_pins_pwrseq>; - - /* Toggle WIFI_ENABLE to reset the chip. */ - reset-gpios = <&pio 119 1>; - }; - - wifi_wakeup: wifi-wakeup { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_pins_wakeup>; - - wowlan { - label = "Wake on WiFi"; - gpios = <&pio 113 GPIO_ACTIVE_HIGH>; - linux,code = ; - wakeup-source; - }; - }; - - tboard_thermistor1: thermal-sensor1 { - compatible = "generic-adc-thermal"; - #thermal-sensor-cells = <0>; - io-channels = <&auxadc 0>; - io-channel-names = "sensor-channel"; - temperature-lookup-table = < (-5000) 4241 - 0 4063 - 5000 3856 - 10000 3621 - 15000 3364 - 20000 3091 - 25000 2810 - 30000 2526 - 35000 2247 - 40000 1982 - 45000 1734 - 50000 1507 - 55000 1305 - 60000 1122 - 65000 964 - 70000 827 - 75000 710 - 80000 606 - 85000 519 - 90000 445 - 95000 382 - 100000 330 - 105000 284 - 110000 245 - 115000 213 - 120000 183 - 125000 161>; - }; - - tboard_thermistor2: thermal-sensor2 { - compatible = "generic-adc-thermal"; - #thermal-sensor-cells = <0>; - io-channels = <&auxadc 1>; - io-channel-names = "sensor-channel"; - temperature-lookup-table = < (-5000) 4241 - 0 4063 - 5000 3856 - 10000 3621 - 15000 3364 - 20000 3091 - 25000 2810 - 30000 2526 - 35000 2247 - 40000 1982 - 45000 1734 - 50000 1507 - 55000 1305 - 60000 1122 - 65000 964 - 70000 827 - 75000 710 - 80000 606 - 85000 519 - 90000 445 - 95000 382 - 100000 330 - 105000 284 - 110000 245 - 115000 213 - 120000 183 - 125000 161>; - }; -}; - -&auxadc { - status = "okay"; -}; - -&cpu0 { - proc-supply = <&mt6358_vproc12_reg>; -}; - -&cpu1 { - proc-supply = <&mt6358_vproc12_reg>; -}; - -&cpu2 { - proc-supply = <&mt6358_vproc12_reg>; -}; - -&cpu3 { - proc-supply = <&mt6358_vproc12_reg>; -}; - -&cpu4 { - proc-supply = <&mt6358_vproc11_reg>; -}; - -&cpu5 { - proc-supply = <&mt6358_vproc11_reg>; -}; - -&cpu6 { - proc-supply = <&mt6358_vproc11_reg>; -}; - -&cpu7 { - proc-supply = <&mt6358_vproc11_reg>; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; - clock-frequency = <100000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - status = "okay"; - clock-frequency = <100000>; - #address-cells = <1>; - #size-cells = <0>; -}; - -&i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins>; - status = "okay"; - clock-frequency = <100000>; - #address-cells = <1>; - #size-cells = <0>; -}; - -&i2c6 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_pins>; - status = "okay"; - clock-frequency = <100000>; -}; - -&mmc0 { - status = "okay"; - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - cap-mmc-hw-reset; - no-sdio; - no-sd; - hs400-ds-delay = <0x12814>; - vmmc-supply = <&mt6358_vemc_reg>; - vqmmc-supply = <&mt6358_vio18_reg>; - assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; - assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; - non-removable; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc1_pins_default>; - pinctrl-1 = <&mmc1_pins_uhs>; - vmmc-supply = <&mmc1_fixed_power>; - vqmmc-supply = <&mmc1_fixed_io>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - max-frequency = <200000000>; - drv-type = <2>; - cap-sd-highspeed; - sd-uhs-sdr50; - sd-uhs-sdr104; - keep-power-in-suspend; - enable-sdio-wakeup; - cap-sdio-irq; - non-removable; - no-mmc; - no-sd; - assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>; - assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; - #address-cells = <1>; - #size-cells = <0>; - - qca_wifi: qca-wifi@1 { - compatible = "qcom,ath10k"; - reg = <1>; - }; -}; - -&mt6358_vdram2_reg { - regulator-always-on; -}; - -&mt6358codec { - Avdd-supply = <&mt6358_vaud28_reg>; -}; - -&mt6358_vsim1_reg { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; -}; - -&mt6358_vsim2_reg { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; -}; - -&pio { - bt_pins: bt-pins { - pins_bt_en { - pinmux = ; - output-low; - }; - }; - - ec_ap_int_odl: ec_ap_int_odl { - pins1 { - pinmux = ; - input-enable; - bias-pull-up; - }; - }; - - h1_int_od_l: h1_int_od_l { - pins1 { - pinmux = ; - input-enable; - }; - }; - - i2c0_pins: i2c0 { - pins_bus { - pinmux = , - ; - mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; - }; - }; - - i2c1_pins: i2c1 { - pins_bus { - pinmux = , - ; - mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; - }; - }; - - i2c2_pins: i2c2 { - pins_bus { - pinmux = , - ; - bias-disable; - mediatek,drive-strength-adv = <00>; - }; - }; - - i2c3_pins: i2c3 { - pins_bus { - pinmux = , - ; - mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; - }; - }; - - i2c4_pins: i2c4 { - pins_bus { - pinmux = , - ; - bias-disable; - mediatek,drive-strength-adv = <00>; - }; - }; - - i2c5_pins: i2c5 { - pins_bus { - pinmux = , - ; - mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; - }; - }; - - i2c6_pins: i2c6 { - pins_bus { - pinmux = , - ; - bias-disable; - }; - }; - - mmc0_pins_default: mmc0-pins-default { - pins_cmd_dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - drive-strength = ; - mediatek,pull-up-adv = <01>; - }; - - pins_clk { - pinmux = ; - drive-strength = ; - mediatek,pull-down-adv = <10>; - }; - - pins_rst { - pinmux = ; - drive-strength = ; - mediatek,pull-down-adv = <01>; - }; - }; - - mmc0_pins_uhs: mmc0-pins-uhs { - pins_cmd_dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - drive-strength = ; - mediatek,pull-up-adv = <01>; - }; - - pins_clk { - pinmux = ; - drive-strength = ; - mediatek,pull-down-adv = <10>; - }; - - pins_ds { - pinmux = ; - drive-strength = ; - mediatek,pull-down-adv = <10>; - }; - - pins_rst { - pinmux = ; - drive-strength = ; - mediatek,pull-up-adv = <01>; - }; - }; - - mmc1_pins_default: mmc1-pins-default { - pins_cmd_dat { - pinmux = , - , - , - , - ; - input-enable; - mediatek,pull-up-adv = <10>; - }; - - pins_clk { - pinmux = ; - input-enable; - mediatek,pull-down-adv = <10>; - }; - }; - - mmc1_pins_uhs: mmc1-pins-uhs { - pins_cmd_dat { - pinmux = , - , - , - , - ; - drive-strength = ; - input-enable; - mediatek,pull-up-adv = <10>; - }; - - pins_clk { - pinmux = ; - drive-strength = ; - mediatek,pull-down-adv = <10>; - input-enable; - }; - }; - - scp_pins: scp { - pins_scp_uart { - pinmux = , - ; - }; - }; - - spi0_pins: spi0 { - pins_spi{ - pinmux = , - , - , - ; - bias-disable; - }; - }; - - spi1_pins: spi1 { - pins_spi{ - pinmux = , - , - , - ; - bias-disable; - }; - }; - - spi2_pins: spi2 { - pins_spi{ - pinmux = , - , - ; - bias-disable; - }; - pins_spi_mi { - pinmux = ; - mediatek,pull-down-adv = <00>; - }; - }; - - spi3_pins: spi3 { - pins_spi{ - pinmux = , - , - , - ; - bias-disable; - }; - }; - - spi4_pins: spi4 { - pins_spi{ - pinmux = , - , - , - ; - bias-disable; - }; - }; - - spi5_pins: spi5 { - pins_spi{ - pinmux = , - , - , - ; - bias-disable; - }; - }; - - uart0_pins_default: uart0-pins-default { - pins_rx { - pinmux = ; - input-enable; - bias-pull-up; - }; - pins_tx { - pinmux = ; - }; - }; - - uart1_pins_default: uart1-pins-default { - pins_rx { - pinmux = ; - input-enable; - bias-pull-up; - }; - pins_tx { - pinmux = ; - }; - pins_rts { - pinmux = ; - output-enable; - }; - pins_cts { - pinmux = ; - input-enable; - }; - }; - - uart1_pins_sleep: uart1-pins-sleep { - pins_rx { - pinmux = ; - input-enable; - bias-pull-up; - }; - pins_tx { - pinmux = ; - }; - pins_rts { - pinmux = ; - output-enable; - }; - pins_cts { - pinmux = ; - input-enable; - }; - }; - - wifi_pins_pwrseq: wifi-pins-pwrseq { - pins_wifi_enable { - pinmux = ; - output-low; - }; - }; - - wifi_pins_wakeup: wifi-pins-wakeup { - pins_wifi_wakeup { - pinmux = ; - input-enable; - }; - }; -}; - -&scp { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&scp_pins>; - - cros_ec { - compatible = "google,cros-ec-rpmsg"; - mtk,rpmsg-name = "cros-ec-rpmsg"; - }; -}; - -&soc_data { - status = "okay"; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - mediatek,pad-select = <0>; - status = "okay"; - cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>; - - cr50@0 { - compatible = "google,cr50"; - reg = <0>; - spi-max-frequency = <1000000>; - pinctrl-names = "default"; - pinctrl-0 = <&h1_int_od_l>; - interrupt-parent = <&pio>; - interrupts = <153 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - mediatek,pad-select = <0>; - status = "okay"; - - w25q64dw: spi-flash@0 { - compatible = "winbond,w25q64dw", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <25000000>; - }; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins>; - mediatek,pad-select = <0>; - status = "okay"; - - cros_ec: cros-ec@0 { - compatible = "google,cros-ec-spi"; - reg = <0>; - spi-max-frequency = <3000000>; - interrupt-parent = <&pio>; - interrupts = <151 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_ap_int_odl>; - - i2c_tunnel: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - google,remote-bus = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - usbc_extcon: extcon0 { - compatible = "google,extcon-usbc-cros-ec"; - google,usb-port-id = <0>; - }; - }; -}; - -&spi3 { - pinctrl-names = "default"; - pinctrl-0 = <&spi3_pins>; - mediatek,pad-select = <0>; - status = "disabled"; -}; - -&spi4 { - pinctrl-names = "default"; - pinctrl-0 = <&spi4_pins>; - mediatek,pad-select = <0>; - status = "disabled"; -}; - -&spi5 { - pinctrl-names = "default"; - pinctrl-0 = <&spi5_pins>; - mediatek,pad-select = <0>; - status = "disabled"; -}; - -&ssusb { - dr_mode = "host"; - wakeup-source; - vusb33-supply = <&mt6358_vusb_reg>; - status = "okay"; -}; - -&u3phy { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_default>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&uart1_pins_default>; - pinctrl-1 = <&uart1_pins_sleep>; - status = "okay"; - interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>, - <&pio 121 IRQ_TYPE_EDGE_FALLING>; - - bluetooth: bluetooth { - pinctrl-names = "default"; - pinctrl-0 = <&bt_pins>; - status = "okay"; - compatible = "qcom,qca6174-bt"; - enable-gpios = <&pio 120 0>; - clocks = <&clk32k>; - firmware-name = "nvm_00440302_i2s.bin"; - }; -}; - -&usb_host { - #address-cells = <1>; - #size-cells = <0>; - vusb33-supply = <&mt6358_vusb_reg>; - status = "okay"; - - hub@1 { - compatible = "usb5e3,610"; - reg = <1>; - }; -}; - -#include -#include diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h deleted file mode 100644 index 6221cd712..000000000 --- a/arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h +++ /dev/null @@ -1,1120 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 MediaTek Inc. - * Author: Zhiyong Tao - * - */ - -#ifndef __MT8183_PINFUNC_H -#define __MT8183_PINFUNC_H - -#include - -#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) -#define PINMUX_GPIO0__FUNC_MRG_SYNC (MTK_PIN_NO(0) | 1) -#define PINMUX_GPIO0__FUNC_PCM0_SYNC (MTK_PIN_NO(0) | 2) -#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 3) -#define PINMUX_GPIO0__FUNC_SRCLKENAI0 (MTK_PIN_NO(0) | 4) -#define PINMUX_GPIO0__FUNC_SCP_SPI2_CS (MTK_PIN_NO(0) | 5) -#define PINMUX_GPIO0__FUNC_I2S3_MCK (MTK_PIN_NO(0) | 6) -#define PINMUX_GPIO0__FUNC_SPI2_CSB (MTK_PIN_NO(0) | 7) - -#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) -#define PINMUX_GPIO1__FUNC_MRG_CLK (MTK_PIN_NO(1) | 1) -#define PINMUX_GPIO1__FUNC_PCM0_CLK (MTK_PIN_NO(1) | 2) -#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 3) -#define PINMUX_GPIO1__FUNC_CLKM3 (MTK_PIN_NO(1) | 4) -#define PINMUX_GPIO1__FUNC_SCP_SPI2_MO (MTK_PIN_NO(1) | 5) -#define PINMUX_GPIO1__FUNC_I2S3_BCK (MTK_PIN_NO(1) | 6) -#define PINMUX_GPIO1__FUNC_SPI2_MO (MTK_PIN_NO(1) | 7) - -#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) -#define PINMUX_GPIO2__FUNC_MRG_DO (MTK_PIN_NO(2) | 1) -#define PINMUX_GPIO2__FUNC_PCM0_DO (MTK_PIN_NO(2) | 2) -#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 3) -#define PINMUX_GPIO2__FUNC_SCL6 (MTK_PIN_NO(2) | 4) -#define PINMUX_GPIO2__FUNC_SCP_SPI2_CK (MTK_PIN_NO(2) | 5) -#define PINMUX_GPIO2__FUNC_I2S3_LRCK (MTK_PIN_NO(2) | 6) -#define PINMUX_GPIO2__FUNC_SPI2_CLK (MTK_PIN_NO(2) | 7) - -#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) -#define PINMUX_GPIO3__FUNC_MRG_DI (MTK_PIN_NO(3) | 1) -#define PINMUX_GPIO3__FUNC_PCM0_DI (MTK_PIN_NO(3) | 2) -#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 3) -#define PINMUX_GPIO3__FUNC_SDA6 (MTK_PIN_NO(3) | 4) -#define PINMUX_GPIO3__FUNC_TDM_MCK (MTK_PIN_NO(3) | 5) -#define PINMUX_GPIO3__FUNC_I2S3_DO (MTK_PIN_NO(3) | 6) -#define PINMUX_GPIO3__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(3) | 7) - -#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) -#define PINMUX_GPIO4__FUNC_PWM_B (MTK_PIN_NO(4) | 1) -#define PINMUX_GPIO4__FUNC_I2S0_MCK (MTK_PIN_NO(4) | 2) -#define PINMUX_GPIO4__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(4) | 3) -#define PINMUX_GPIO4__FUNC_MD_URXD1 (MTK_PIN_NO(4) | 4) -#define PINMUX_GPIO4__FUNC_TDM_BCK (MTK_PIN_NO(4) | 5) -#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6) -#define PINMUX_GPIO4__FUNC_DAP_MD32_SWD (MTK_PIN_NO(4) | 7) - -#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) -#define PINMUX_GPIO5__FUNC_PWM_C (MTK_PIN_NO(5) | 1) -#define PINMUX_GPIO5__FUNC_I2S0_BCK (MTK_PIN_NO(5) | 2) -#define PINMUX_GPIO5__FUNC_SSPM_URXD_AO (MTK_PIN_NO(5) | 3) -#define PINMUX_GPIO5__FUNC_MD_UTXD1 (MTK_PIN_NO(5) | 4) -#define PINMUX_GPIO5__FUNC_TDM_LRCK (MTK_PIN_NO(5) | 5) -#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6) -#define PINMUX_GPIO5__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(5) | 7) - -#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) -#define PINMUX_GPIO6__FUNC_PWM_A (MTK_PIN_NO(6) | 1) -#define PINMUX_GPIO6__FUNC_I2S0_LRCK (MTK_PIN_NO(6) | 2) -#define PINMUX_GPIO6__FUNC_IDDIG (MTK_PIN_NO(6) | 3) -#define PINMUX_GPIO6__FUNC_MD_URXD0 (MTK_PIN_NO(6) | 4) -#define PINMUX_GPIO6__FUNC_TDM_DATA0 (MTK_PIN_NO(6) | 5) -#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6) -#define PINMUX_GPIO6__FUNC_CMFLASH (MTK_PIN_NO(6) | 7) - -#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) -#define PINMUX_GPIO7__FUNC_SPI1_B_MI (MTK_PIN_NO(7) | 1) -#define PINMUX_GPIO7__FUNC_I2S0_DI (MTK_PIN_NO(7) | 2) -#define PINMUX_GPIO7__FUNC_USB_DRVVBUS (MTK_PIN_NO(7) | 3) -#define PINMUX_GPIO7__FUNC_MD_UTXD0 (MTK_PIN_NO(7) | 4) -#define PINMUX_GPIO7__FUNC_TDM_DATA1 (MTK_PIN_NO(7) | 5) -#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6) -#define PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(7) | 7) - -#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) -#define PINMUX_GPIO8__FUNC_SPI1_B_CSB (MTK_PIN_NO(8) | 1) -#define PINMUX_GPIO8__FUNC_ANT_SEL3 (MTK_PIN_NO(8) | 2) -#define PINMUX_GPIO8__FUNC_SCL7 (MTK_PIN_NO(8) | 3) -#define PINMUX_GPIO8__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(8) | 4) -#define PINMUX_GPIO8__FUNC_TDM_DATA2 (MTK_PIN_NO(8) | 5) -#define PINMUX_GPIO8__FUNC_MD_INT0 (MTK_PIN_NO(8) | 6) -#define PINMUX_GPIO8__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(8) | 7) - -#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) -#define PINMUX_GPIO9__FUNC_SPI1_B_MO (MTK_PIN_NO(9) | 1) -#define PINMUX_GPIO9__FUNC_ANT_SEL4 (MTK_PIN_NO(9) | 2) -#define PINMUX_GPIO9__FUNC_CMMCLK2 (MTK_PIN_NO(9) | 3) -#define PINMUX_GPIO9__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(9) | 4) -#define PINMUX_GPIO9__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(9) | 5) -#define PINMUX_GPIO9__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(9) | 6) -#define PINMUX_GPIO9__FUNC_DBG_MON_B10 (MTK_PIN_NO(9) | 7) - -#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) -#define PINMUX_GPIO10__FUNC_SPI1_B_CLK (MTK_PIN_NO(10) | 1) -#define PINMUX_GPIO10__FUNC_ANT_SEL5 (MTK_PIN_NO(10) | 2) -#define PINMUX_GPIO10__FUNC_CMMCLK3 (MTK_PIN_NO(10) | 3) -#define PINMUX_GPIO10__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(10) | 4) -#define PINMUX_GPIO10__FUNC_TDM_DATA3 (MTK_PIN_NO(10) | 5) -#define PINMUX_GPIO10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 6) -#define PINMUX_GPIO10__FUNC_DBG_MON_B11 (MTK_PIN_NO(10) | 7) - -#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) -#define PINMUX_GPIO11__FUNC_TP_URXD1_AO (MTK_PIN_NO(11) | 1) -#define PINMUX_GPIO11__FUNC_IDDIG (MTK_PIN_NO(11) | 2) -#define PINMUX_GPIO11__FUNC_SCL6 (MTK_PIN_NO(11) | 3) -#define PINMUX_GPIO11__FUNC_UCTS1 (MTK_PIN_NO(11) | 4) -#define PINMUX_GPIO11__FUNC_UCTS0 (MTK_PIN_NO(11) | 5) -#define PINMUX_GPIO11__FUNC_SRCLKENAI1 (MTK_PIN_NO(11) | 6) -#define PINMUX_GPIO11__FUNC_I2S5_MCK (MTK_PIN_NO(11) | 7) - -#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) -#define PINMUX_GPIO12__FUNC_TP_UTXD1_AO (MTK_PIN_NO(12) | 1) -#define PINMUX_GPIO12__FUNC_USB_DRVVBUS (MTK_PIN_NO(12) | 2) -#define PINMUX_GPIO12__FUNC_SDA6 (MTK_PIN_NO(12) | 3) -#define PINMUX_GPIO12__FUNC_URTS1 (MTK_PIN_NO(12) | 4) -#define PINMUX_GPIO12__FUNC_URTS0 (MTK_PIN_NO(12) | 5) -#define PINMUX_GPIO12__FUNC_I2S2_DI2 (MTK_PIN_NO(12) | 6) -#define PINMUX_GPIO12__FUNC_I2S5_BCK (MTK_PIN_NO(12) | 7) - -#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) -#define PINMUX_GPIO13__FUNC_DBPI_D0 (MTK_PIN_NO(13) | 1) -#define PINMUX_GPIO13__FUNC_SPI5_MI (MTK_PIN_NO(13) | 2) -#define PINMUX_GPIO13__FUNC_PCM0_SYNC (MTK_PIN_NO(13) | 3) -#define PINMUX_GPIO13__FUNC_MD_URXD0 (MTK_PIN_NO(13) | 4) -#define PINMUX_GPIO13__FUNC_ANT_SEL3 (MTK_PIN_NO(13) | 5) -#define PINMUX_GPIO13__FUNC_I2S0_MCK (MTK_PIN_NO(13) | 6) -#define PINMUX_GPIO13__FUNC_DBG_MON_B15 (MTK_PIN_NO(13) | 7) - -#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) -#define PINMUX_GPIO14__FUNC_DBPI_D1 (MTK_PIN_NO(14) | 1) -#define PINMUX_GPIO14__FUNC_SPI5_CSB (MTK_PIN_NO(14) | 2) -#define PINMUX_GPIO14__FUNC_PCM0_CLK (MTK_PIN_NO(14) | 3) -#define PINMUX_GPIO14__FUNC_MD_UTXD0 (MTK_PIN_NO(14) | 4) -#define PINMUX_GPIO14__FUNC_ANT_SEL4 (MTK_PIN_NO(14) | 5) -#define PINMUX_GPIO14__FUNC_I2S0_BCK (MTK_PIN_NO(14) | 6) -#define PINMUX_GPIO14__FUNC_DBG_MON_B16 (MTK_PIN_NO(14) | 7) - -#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) -#define PINMUX_GPIO15__FUNC_DBPI_D2 (MTK_PIN_NO(15) | 1) -#define PINMUX_GPIO15__FUNC_SPI5_MO (MTK_PIN_NO(15) | 2) -#define PINMUX_GPIO15__FUNC_PCM0_DO (MTK_PIN_NO(15) | 3) -#define PINMUX_GPIO15__FUNC_MD_URXD1 (MTK_PIN_NO(15) | 4) -#define PINMUX_GPIO15__FUNC_ANT_SEL5 (MTK_PIN_NO(15) | 5) -#define PINMUX_GPIO15__FUNC_I2S0_LRCK (MTK_PIN_NO(15) | 6) -#define PINMUX_GPIO15__FUNC_DBG_MON_B17 (MTK_PIN_NO(15) | 7) - -#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) -#define PINMUX_GPIO16__FUNC_DBPI_D3 (MTK_PIN_NO(16) | 1) -#define PINMUX_GPIO16__FUNC_SPI5_CLK (MTK_PIN_NO(16) | 2) -#define PINMUX_GPIO16__FUNC_PCM0_DI (MTK_PIN_NO(16) | 3) -#define PINMUX_GPIO16__FUNC_MD_UTXD1 (MTK_PIN_NO(16) | 4) -#define PINMUX_GPIO16__FUNC_ANT_SEL6 (MTK_PIN_NO(16) | 5) -#define PINMUX_GPIO16__FUNC_I2S0_DI (MTK_PIN_NO(16) | 6) -#define PINMUX_GPIO16__FUNC_DBG_MON_B23 (MTK_PIN_NO(16) | 7) - -#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) -#define PINMUX_GPIO17__FUNC_DBPI_D4 (MTK_PIN_NO(17) | 1) -#define PINMUX_GPIO17__FUNC_SPI4_MI (MTK_PIN_NO(17) | 2) -#define PINMUX_GPIO17__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(17) | 3) -#define PINMUX_GPIO17__FUNC_MD_INT0 (MTK_PIN_NO(17) | 4) -#define PINMUX_GPIO17__FUNC_ANT_SEL7 (MTK_PIN_NO(17) | 5) -#define PINMUX_GPIO17__FUNC_I2S3_MCK (MTK_PIN_NO(17) | 6) -#define PINMUX_GPIO17__FUNC_DBG_MON_A1 (MTK_PIN_NO(17) | 7) - -#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) -#define PINMUX_GPIO18__FUNC_DBPI_D5 (MTK_PIN_NO(18) | 1) -#define PINMUX_GPIO18__FUNC_SPI4_CSB (MTK_PIN_NO(18) | 2) -#define PINMUX_GPIO18__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(18) | 3) -#define PINMUX_GPIO18__FUNC_MD_INT0 (MTK_PIN_NO(18) | 4) -#define PINMUX_GPIO18__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(18) | 5) -#define PINMUX_GPIO18__FUNC_I2S3_BCK (MTK_PIN_NO(18) | 6) -#define PINMUX_GPIO18__FUNC_DBG_MON_A2 (MTK_PIN_NO(18) | 7) - -#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) -#define PINMUX_GPIO19__FUNC_DBPI_D6 (MTK_PIN_NO(19) | 1) -#define PINMUX_GPIO19__FUNC_SPI4_MO (MTK_PIN_NO(19) | 2) -#define PINMUX_GPIO19__FUNC_CONN_MCU_TDO (MTK_PIN_NO(19) | 3) -#define PINMUX_GPIO19__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(19) | 4) -#define PINMUX_GPIO19__FUNC_URXD1 (MTK_PIN_NO(19) | 5) -#define PINMUX_GPIO19__FUNC_I2S3_LRCK (MTK_PIN_NO(19) | 6) -#define PINMUX_GPIO19__FUNC_DBG_MON_A3 (MTK_PIN_NO(19) | 7) - -#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) -#define PINMUX_GPIO20__FUNC_DBPI_D7 (MTK_PIN_NO(20) | 1) -#define PINMUX_GPIO20__FUNC_SPI4_CLK (MTK_PIN_NO(20) | 2) -#define PINMUX_GPIO20__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(20) | 3) -#define PINMUX_GPIO20__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(20) | 4) -#define PINMUX_GPIO20__FUNC_UTXD1 (MTK_PIN_NO(20) | 5) -#define PINMUX_GPIO20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 6) -#define PINMUX_GPIO20__FUNC_DBG_MON_A19 (MTK_PIN_NO(20) | 7) - -#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) -#define PINMUX_GPIO21__FUNC_DBPI_D8 (MTK_PIN_NO(21) | 1) -#define PINMUX_GPIO21__FUNC_SPI3_MI (MTK_PIN_NO(21) | 2) -#define PINMUX_GPIO21__FUNC_CONN_MCU_TMS (MTK_PIN_NO(21) | 3) -#define PINMUX_GPIO21__FUNC_DAP_MD32_SWD (MTK_PIN_NO(21) | 4) -#define PINMUX_GPIO21__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(21) | 5) -#define PINMUX_GPIO21__FUNC_I2S2_MCK (MTK_PIN_NO(21) | 6) -#define PINMUX_GPIO21__FUNC_DBG_MON_B5 (MTK_PIN_NO(21) | 7) - -#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) -#define PINMUX_GPIO22__FUNC_DBPI_D9 (MTK_PIN_NO(22) | 1) -#define PINMUX_GPIO22__FUNC_SPI3_CSB (MTK_PIN_NO(22) | 2) -#define PINMUX_GPIO22__FUNC_CONN_MCU_TCK (MTK_PIN_NO(22) | 3) -#define PINMUX_GPIO22__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(22) | 4) -#define PINMUX_GPIO22__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(22) | 5) -#define PINMUX_GPIO22__FUNC_I2S2_BCK (MTK_PIN_NO(22) | 6) -#define PINMUX_GPIO22__FUNC_DBG_MON_B6 (MTK_PIN_NO(22) | 7) - -#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) -#define PINMUX_GPIO23__FUNC_DBPI_D10 (MTK_PIN_NO(23) | 1) -#define PINMUX_GPIO23__FUNC_SPI3_MO (MTK_PIN_NO(23) | 2) -#define PINMUX_GPIO23__FUNC_CONN_MCU_TDI (MTK_PIN_NO(23) | 3) -#define PINMUX_GPIO23__FUNC_UCTS1 (MTK_PIN_NO(23) | 4) -#define PINMUX_GPIO23__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5) -#define PINMUX_GPIO23__FUNC_I2S2_LRCK (MTK_PIN_NO(23) | 6) -#define PINMUX_GPIO23__FUNC_DBG_MON_B7 (MTK_PIN_NO(23) | 7) - -#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) -#define PINMUX_GPIO24__FUNC_DBPI_D11 (MTK_PIN_NO(24) | 1) -#define PINMUX_GPIO24__FUNC_SPI3_CLK (MTK_PIN_NO(24) | 2) -#define PINMUX_GPIO24__FUNC_SRCLKENAI0 (MTK_PIN_NO(24) | 3) -#define PINMUX_GPIO24__FUNC_URTS1 (MTK_PIN_NO(24) | 4) -#define PINMUX_GPIO24__FUNC_IO_JTAG_TCK (MTK_PIN_NO(24) | 5) -#define PINMUX_GPIO24__FUNC_I2S2_DI (MTK_PIN_NO(24) | 6) -#define PINMUX_GPIO24__FUNC_DBG_MON_B31 (MTK_PIN_NO(24) | 7) - -#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) -#define PINMUX_GPIO25__FUNC_DBPI_HSYNC (MTK_PIN_NO(25) | 1) -#define PINMUX_GPIO25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 2) -#define PINMUX_GPIO25__FUNC_SCL6 (MTK_PIN_NO(25) | 3) -#define PINMUX_GPIO25__FUNC_KPCOL2 (MTK_PIN_NO(25) | 4) -#define PINMUX_GPIO25__FUNC_IO_JTAG_TMS (MTK_PIN_NO(25) | 5) -#define PINMUX_GPIO25__FUNC_I2S1_MCK (MTK_PIN_NO(25) | 6) -#define PINMUX_GPIO25__FUNC_DBG_MON_B0 (MTK_PIN_NO(25) | 7) - -#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) -#define PINMUX_GPIO26__FUNC_DBPI_VSYNC (MTK_PIN_NO(26) | 1) -#define PINMUX_GPIO26__FUNC_ANT_SEL1 (MTK_PIN_NO(26) | 2) -#define PINMUX_GPIO26__FUNC_SDA6 (MTK_PIN_NO(26) | 3) -#define PINMUX_GPIO26__FUNC_KPROW2 (MTK_PIN_NO(26) | 4) -#define PINMUX_GPIO26__FUNC_IO_JTAG_TDI (MTK_PIN_NO(26) | 5) -#define PINMUX_GPIO26__FUNC_I2S1_BCK (MTK_PIN_NO(26) | 6) -#define PINMUX_GPIO26__FUNC_DBG_MON_B1 (MTK_PIN_NO(26) | 7) - -#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) -#define PINMUX_GPIO27__FUNC_DBPI_DE (MTK_PIN_NO(27) | 1) -#define PINMUX_GPIO27__FUNC_ANT_SEL2 (MTK_PIN_NO(27) | 2) -#define PINMUX_GPIO27__FUNC_SCL7 (MTK_PIN_NO(27) | 3) -#define PINMUX_GPIO27__FUNC_DMIC_CLK (MTK_PIN_NO(27) | 4) -#define PINMUX_GPIO27__FUNC_IO_JTAG_TDO (MTK_PIN_NO(27) | 5) -#define PINMUX_GPIO27__FUNC_I2S1_LRCK (MTK_PIN_NO(27) | 6) -#define PINMUX_GPIO27__FUNC_DBG_MON_B9 (MTK_PIN_NO(27) | 7) - -#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) -#define PINMUX_GPIO28__FUNC_DBPI_CK (MTK_PIN_NO(28) | 1) -#define PINMUX_GPIO28__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(28) | 2) -#define PINMUX_GPIO28__FUNC_SDA7 (MTK_PIN_NO(28) | 3) -#define PINMUX_GPIO28__FUNC_DMIC_DAT (MTK_PIN_NO(28) | 4) -#define PINMUX_GPIO28__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(28) | 5) -#define PINMUX_GPIO28__FUNC_I2S1_DO (MTK_PIN_NO(28) | 6) -#define PINMUX_GPIO28__FUNC_DBG_MON_B32 (MTK_PIN_NO(28) | 7) - -#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) -#define PINMUX_GPIO29__FUNC_MSDC1_CLK (MTK_PIN_NO(29) | 1) -#define PINMUX_GPIO29__FUNC_IO_JTAG_TCK (MTK_PIN_NO(29) | 2) -#define PINMUX_GPIO29__FUNC_UDI_TCK (MTK_PIN_NO(29) | 3) -#define PINMUX_GPIO29__FUNC_CONN_DSP_JCK (MTK_PIN_NO(29) | 4) -#define PINMUX_GPIO29__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(29) | 5) -#define PINMUX_GPIO29__FUNC_PCM1_CLK (MTK_PIN_NO(29) | 6) -#define PINMUX_GPIO29__FUNC_DBG_MON_A6 (MTK_PIN_NO(29) | 7) - -#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) -#define PINMUX_GPIO30__FUNC_MSDC1_DAT3 (MTK_PIN_NO(30) | 1) -#define PINMUX_GPIO30__FUNC_DAP_MD32_SWD (MTK_PIN_NO(30) | 2) -#define PINMUX_GPIO30__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 3) -#define PINMUX_GPIO30__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(30) | 4) -#define PINMUX_GPIO30__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(30) | 5) -#define PINMUX_GPIO30__FUNC_PCM1_DI (MTK_PIN_NO(30) | 6) -#define PINMUX_GPIO30__FUNC_DBG_MON_A7 (MTK_PIN_NO(30) | 7) - -#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) -#define PINMUX_GPIO31__FUNC_MSDC1_CMD (MTK_PIN_NO(31) | 1) -#define PINMUX_GPIO31__FUNC_IO_JTAG_TMS (MTK_PIN_NO(31) | 2) -#define PINMUX_GPIO31__FUNC_UDI_TMS (MTK_PIN_NO(31) | 3) -#define PINMUX_GPIO31__FUNC_CONN_DSP_JMS (MTK_PIN_NO(31) | 4) -#define PINMUX_GPIO31__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(31) | 5) -#define PINMUX_GPIO31__FUNC_PCM1_SYNC (MTK_PIN_NO(31) | 6) -#define PINMUX_GPIO31__FUNC_DBG_MON_A8 (MTK_PIN_NO(31) | 7) - -#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) -#define PINMUX_GPIO32__FUNC_MSDC1_DAT0 (MTK_PIN_NO(32) | 1) -#define PINMUX_GPIO32__FUNC_IO_JTAG_TDI (MTK_PIN_NO(32) | 2) -#define PINMUX_GPIO32__FUNC_UDI_TDI (MTK_PIN_NO(32) | 3) -#define PINMUX_GPIO32__FUNC_CONN_DSP_JDI (MTK_PIN_NO(32) | 4) -#define PINMUX_GPIO32__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(32) | 5) -#define PINMUX_GPIO32__FUNC_PCM1_DO0 (MTK_PIN_NO(32) | 6) -#define PINMUX_GPIO32__FUNC_DBG_MON_A9 (MTK_PIN_NO(32) | 7) - -#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) -#define PINMUX_GPIO33__FUNC_MSDC1_DAT2 (MTK_PIN_NO(33) | 1) -#define PINMUX_GPIO33__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(33) | 2) -#define PINMUX_GPIO33__FUNC_UDI_NTRST (MTK_PIN_NO(33) | 3) -#define PINMUX_GPIO33__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(33) | 4) -#define PINMUX_GPIO33__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(33) | 5) -#define PINMUX_GPIO33__FUNC_PCM1_DO2 (MTK_PIN_NO(33) | 6) -#define PINMUX_GPIO33__FUNC_DBG_MON_A10 (MTK_PIN_NO(33) | 7) - -#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) -#define PINMUX_GPIO34__FUNC_MSDC1_DAT1 (MTK_PIN_NO(34) | 1) -#define PINMUX_GPIO34__FUNC_IO_JTAG_TDO (MTK_PIN_NO(34) | 2) -#define PINMUX_GPIO34__FUNC_UDI_TDO (MTK_PIN_NO(34) | 3) -#define PINMUX_GPIO34__FUNC_CONN_DSP_JDO (MTK_PIN_NO(34) | 4) -#define PINMUX_GPIO34__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(34) | 5) -#define PINMUX_GPIO34__FUNC_PCM1_DO1 (MTK_PIN_NO(34) | 6) -#define PINMUX_GPIO34__FUNC_DBG_MON_A11 (MTK_PIN_NO(34) | 7) - -#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) -#define PINMUX_GPIO35__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(35) | 1) -#define PINMUX_GPIO35__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(35) | 2) -#define PINMUX_GPIO35__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(35) | 3) -#define PINMUX_GPIO35__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(35) | 5) -#define PINMUX_GPIO35__FUNC_CONN_DSP_JMS (MTK_PIN_NO(35) | 6) -#define PINMUX_GPIO35__FUNC_DBG_MON_A28 (MTK_PIN_NO(35) | 7) - -#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) -#define PINMUX_GPIO36__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(36) | 1) -#define PINMUX_GPIO36__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(36) | 2) -#define PINMUX_GPIO36__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(36) | 3) -#define PINMUX_GPIO36__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(36) | 4) -#define PINMUX_GPIO36__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(36) | 5) -#define PINMUX_GPIO36__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(36) | 6) -#define PINMUX_GPIO36__FUNC_DBG_MON_A29 (MTK_PIN_NO(36) | 7) - -#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) -#define PINMUX_GPIO37__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(37) | 1) -#define PINMUX_GPIO37__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(37) | 2) -#define PINMUX_GPIO37__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(37) | 3) -#define PINMUX_GPIO37__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(37) | 5) -#define PINMUX_GPIO37__FUNC_CONN_DSP_JDO (MTK_PIN_NO(37) | 6) -#define PINMUX_GPIO37__FUNC_DBG_MON_A30 (MTK_PIN_NO(37) | 7) - -#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) -#define PINMUX_GPIO38__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(38) | 1) -#define PINMUX_GPIO38__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(38) | 3) -#define PINMUX_GPIO38__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(38) | 4) -#define PINMUX_GPIO38__FUNC_DBG_MON_A20 (MTK_PIN_NO(38) | 7) - -#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) -#define PINMUX_GPIO39__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(39) | 1) -#define PINMUX_GPIO39__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(39) | 2) -#define PINMUX_GPIO39__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(39) | 3) -#define PINMUX_GPIO39__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(39) | 5) -#define PINMUX_GPIO39__FUNC_CONN_DSP_JCK (MTK_PIN_NO(39) | 6) -#define PINMUX_GPIO39__FUNC_DBG_MON_A31 (MTK_PIN_NO(39) | 7) - -#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) -#define PINMUX_GPIO40__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(40) | 1) -#define PINMUX_GPIO40__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(40) | 2) -#define PINMUX_GPIO40__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(40) | 3) -#define PINMUX_GPIO40__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(40) | 5) -#define PINMUX_GPIO40__FUNC_CONN_DSP_JDI (MTK_PIN_NO(40) | 6) -#define PINMUX_GPIO40__FUNC_DBG_MON_A32 (MTK_PIN_NO(40) | 7) - -#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) -#define PINMUX_GPIO41__FUNC_IDDIG (MTK_PIN_NO(41) | 1) -#define PINMUX_GPIO41__FUNC_URXD1 (MTK_PIN_NO(41) | 2) -#define PINMUX_GPIO41__FUNC_UCTS0 (MTK_PIN_NO(41) | 3) -#define PINMUX_GPIO41__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(41) | 4) -#define PINMUX_GPIO41__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 5) -#define PINMUX_GPIO41__FUNC_DMIC_CLK (MTK_PIN_NO(41) | 6) - -#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) -#define PINMUX_GPIO42__FUNC_USB_DRVVBUS (MTK_PIN_NO(42) | 1) -#define PINMUX_GPIO42__FUNC_UTXD1 (MTK_PIN_NO(42) | 2) -#define PINMUX_GPIO42__FUNC_URTS0 (MTK_PIN_NO(42) | 3) -#define PINMUX_GPIO42__FUNC_SSPM_URXD_AO (MTK_PIN_NO(42) | 4) -#define PINMUX_GPIO42__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(42) | 5) -#define PINMUX_GPIO42__FUNC_DMIC_DAT (MTK_PIN_NO(42) | 6) - -#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) -#define PINMUX_GPIO43__FUNC_DISP_PWM (MTK_PIN_NO(43) | 1) - -#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) -#define PINMUX_GPIO44__FUNC_DSI_TE (MTK_PIN_NO(44) | 1) - -#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) -#define PINMUX_GPIO45__FUNC_LCM_RST (MTK_PIN_NO(45) | 1) - -#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) -#define PINMUX_GPIO46__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(46) | 1) -#define PINMUX_GPIO46__FUNC_URXD1 (MTK_PIN_NO(46) | 2) -#define PINMUX_GPIO46__FUNC_UCTS1 (MTK_PIN_NO(46) | 3) -#define PINMUX_GPIO46__FUNC_CCU_UTXD_AO (MTK_PIN_NO(46) | 4) -#define PINMUX_GPIO46__FUNC_TP_UCTS1_AO (MTK_PIN_NO(46) | 5) -#define PINMUX_GPIO46__FUNC_IDDIG (MTK_PIN_NO(46) | 6) -#define PINMUX_GPIO46__FUNC_I2S5_LRCK (MTK_PIN_NO(46) | 7) - -#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) -#define PINMUX_GPIO47__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(47) | 1) -#define PINMUX_GPIO47__FUNC_UTXD1 (MTK_PIN_NO(47) | 2) -#define PINMUX_GPIO47__FUNC_URTS1 (MTK_PIN_NO(47) | 3) -#define PINMUX_GPIO47__FUNC_CCU_URXD_AO (MTK_PIN_NO(47) | 4) -#define PINMUX_GPIO47__FUNC_TP_URTS1_AO (MTK_PIN_NO(47) | 5) -#define PINMUX_GPIO47__FUNC_USB_DRVVBUS (MTK_PIN_NO(47) | 6) -#define PINMUX_GPIO47__FUNC_I2S5_DO (MTK_PIN_NO(47) | 7) - -#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) -#define PINMUX_GPIO48__FUNC_SCL5 (MTK_PIN_NO(48) | 1) - -#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) -#define PINMUX_GPIO49__FUNC_SDA5 (MTK_PIN_NO(49) | 1) - -#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) -#define PINMUX_GPIO50__FUNC_SCL3 (MTK_PIN_NO(50) | 1) - -#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) -#define PINMUX_GPIO51__FUNC_SDA3 (MTK_PIN_NO(51) | 1) - -#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) -#define PINMUX_GPIO52__FUNC_BPI_ANT2 (MTK_PIN_NO(52) | 1) - -#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) -#define PINMUX_GPIO53__FUNC_BPI_ANT0 (MTK_PIN_NO(53) | 1) - -#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) -#define PINMUX_GPIO54__FUNC_BPI_OLAT1 (MTK_PIN_NO(54) | 1) - -#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) -#define PINMUX_GPIO55__FUNC_BPI_BUS8 (MTK_PIN_NO(55) | 1) - -#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) -#define PINMUX_GPIO56__FUNC_BPI_BUS9 (MTK_PIN_NO(56) | 1) -#define PINMUX_GPIO56__FUNC_SCL_6306 (MTK_PIN_NO(56) | 2) - -#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) -#define PINMUX_GPIO57__FUNC_BPI_BUS10 (MTK_PIN_NO(57) | 1) -#define PINMUX_GPIO57__FUNC_SDA_6306 (MTK_PIN_NO(57) | 2) - -#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) -#define PINMUX_GPIO58__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(58) | 1) -#define PINMUX_GPIO58__FUNC_SPM_BSI_D2 (MTK_PIN_NO(58) | 2) -#define PINMUX_GPIO58__FUNC_PWM_B (MTK_PIN_NO(58) | 3) - -#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) -#define PINMUX_GPIO59__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(59) | 1) -#define PINMUX_GPIO59__FUNC_SPM_BSI_D1 (MTK_PIN_NO(59) | 2) - -#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) -#define PINMUX_GPIO60__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(60) | 1) -#define PINMUX_GPIO60__FUNC_SPM_BSI_D0 (MTK_PIN_NO(60) | 2) - -#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) -#define PINMUX_GPIO61__FUNC_MIPI1_SDATA (MTK_PIN_NO(61) | 1) - -#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) -#define PINMUX_GPIO62__FUNC_MIPI1_SCLK (MTK_PIN_NO(62) | 1) - -#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) -#define PINMUX_GPIO63__FUNC_MIPI0_SDATA (MTK_PIN_NO(63) | 1) - -#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) -#define PINMUX_GPIO64__FUNC_MIPI0_SCLK (MTK_PIN_NO(64) | 1) - -#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) -#define PINMUX_GPIO65__FUNC_MIPI3_SDATA (MTK_PIN_NO(65) | 1) -#define PINMUX_GPIO65__FUNC_BPI_OLAT2 (MTK_PIN_NO(65) | 2) - -#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) -#define PINMUX_GPIO66__FUNC_MIPI3_SCLK (MTK_PIN_NO(66) | 1) -#define PINMUX_GPIO66__FUNC_BPI_OLAT3 (MTK_PIN_NO(66) | 2) - -#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) -#define PINMUX_GPIO67__FUNC_MIPI2_SDATA (MTK_PIN_NO(67) | 1) - -#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) -#define PINMUX_GPIO68__FUNC_MIPI2_SCLK (MTK_PIN_NO(68) | 1) - -#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) -#define PINMUX_GPIO69__FUNC_BPI_BUS7 (MTK_PIN_NO(69) | 1) - -#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) -#define PINMUX_GPIO70__FUNC_BPI_BUS6 (MTK_PIN_NO(70) | 1) - -#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) -#define PINMUX_GPIO71__FUNC_BPI_BUS5 (MTK_PIN_NO(71) | 1) - -#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) -#define PINMUX_GPIO72__FUNC_BPI_BUS4 (MTK_PIN_NO(72) | 1) - -#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) -#define PINMUX_GPIO73__FUNC_BPI_BUS3 (MTK_PIN_NO(73) | 1) - -#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) -#define PINMUX_GPIO74__FUNC_BPI_BUS2 (MTK_PIN_NO(74) | 1) - -#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) -#define PINMUX_GPIO75__FUNC_BPI_BUS1 (MTK_PIN_NO(75) | 1) - -#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) -#define PINMUX_GPIO76__FUNC_BPI_BUS0 (MTK_PIN_NO(76) | 1) - -#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) -#define PINMUX_GPIO77__FUNC_BPI_ANT1 (MTK_PIN_NO(77) | 1) - -#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) -#define PINMUX_GPIO78__FUNC_BPI_OLAT0 (MTK_PIN_NO(78) | 1) - -#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) -#define PINMUX_GPIO79__FUNC_BPI_PA_VM1 (MTK_PIN_NO(79) | 1) -#define PINMUX_GPIO79__FUNC_MIPI4_SDATA (MTK_PIN_NO(79) | 2) - -#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) -#define PINMUX_GPIO80__FUNC_BPI_PA_VM0 (MTK_PIN_NO(80) | 1) -#define PINMUX_GPIO80__FUNC_MIPI4_SCLK (MTK_PIN_NO(80) | 2) - -#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) -#define PINMUX_GPIO81__FUNC_SDA1 (MTK_PIN_NO(81) | 1) - -#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) -#define PINMUX_GPIO82__FUNC_SDA0 (MTK_PIN_NO(82) | 1) - -#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) -#define PINMUX_GPIO83__FUNC_SCL0 (MTK_PIN_NO(83) | 1) - -#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) -#define PINMUX_GPIO84__FUNC_SCL1 (MTK_PIN_NO(84) | 1) - -#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) -#define PINMUX_GPIO85__FUNC_SPI0_MI (MTK_PIN_NO(85) | 1) -#define PINMUX_GPIO85__FUNC_SCP_SPI0_MI (MTK_PIN_NO(85) | 2) -#define PINMUX_GPIO85__FUNC_CLKM3 (MTK_PIN_NO(85) | 3) -#define PINMUX_GPIO85__FUNC_I2S1_BCK (MTK_PIN_NO(85) | 4) -#define PINMUX_GPIO85__FUNC_MFG_DFD_JTAG_TDO (MTK_PIN_NO(85) | 5) -#define PINMUX_GPIO85__FUNC_DFD_TDO (MTK_PIN_NO(85) | 6) -#define PINMUX_GPIO85__FUNC_JTDO_SEL1 (MTK_PIN_NO(85) | 7) - -#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) -#define PINMUX_GPIO86__FUNC_SPI0_CSB (MTK_PIN_NO(86) | 1) -#define PINMUX_GPIO86__FUNC_SCP_SPI0_CS (MTK_PIN_NO(86) | 2) -#define PINMUX_GPIO86__FUNC_CLKM0 (MTK_PIN_NO(86) | 3) -#define PINMUX_GPIO86__FUNC_I2S1_LRCK (MTK_PIN_NO(86) | 4) -#define PINMUX_GPIO86__FUNC_MFG_DFD_JTAG_TMS (MTK_PIN_NO(86) | 5) -#define PINMUX_GPIO86__FUNC_DFD_TMS (MTK_PIN_NO(86) | 6) -#define PINMUX_GPIO86__FUNC_JTMS_SEL1 (MTK_PIN_NO(86) | 7) - -#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) -#define PINMUX_GPIO87__FUNC_SPI0_MO (MTK_PIN_NO(87) | 1) -#define PINMUX_GPIO87__FUNC_SCP_SPI0_MO (MTK_PIN_NO(87) | 2) -#define PINMUX_GPIO87__FUNC_SDA1 (MTK_PIN_NO(87) | 3) -#define PINMUX_GPIO87__FUNC_I2S1_DO (MTK_PIN_NO(87) | 4) -#define PINMUX_GPIO87__FUNC_MFG_DFD_JTAG_TDI (MTK_PIN_NO(87) | 5) -#define PINMUX_GPIO87__FUNC_DFD_TDI (MTK_PIN_NO(87) | 6) -#define PINMUX_GPIO87__FUNC_JTDI_SEL1 (MTK_PIN_NO(87) | 7) - -#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) -#define PINMUX_GPIO88__FUNC_SPI0_CLK (MTK_PIN_NO(88) | 1) -#define PINMUX_GPIO88__FUNC_SCP_SPI0_CK (MTK_PIN_NO(88) | 2) -#define PINMUX_GPIO88__FUNC_SCL1 (MTK_PIN_NO(88) | 3) -#define PINMUX_GPIO88__FUNC_I2S1_MCK (MTK_PIN_NO(88) | 4) -#define PINMUX_GPIO88__FUNC_MFG_DFD_JTAG_TCK (MTK_PIN_NO(88) | 5) -#define PINMUX_GPIO88__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 6) -#define PINMUX_GPIO88__FUNC_JTCK_SEL1 (MTK_PIN_NO(88) | 7) - -#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) -#define PINMUX_GPIO89__FUNC_SRCLKENAI0 (MTK_PIN_NO(89) | 1) -#define PINMUX_GPIO89__FUNC_PWM_C (MTK_PIN_NO(89) | 2) -#define PINMUX_GPIO89__FUNC_I2S5_BCK (MTK_PIN_NO(89) | 3) -#define PINMUX_GPIO89__FUNC_ANT_SEL6 (MTK_PIN_NO(89) | 4) -#define PINMUX_GPIO89__FUNC_SDA8 (MTK_PIN_NO(89) | 5) -#define PINMUX_GPIO89__FUNC_CMVREF0 (MTK_PIN_NO(89) | 6) -#define PINMUX_GPIO89__FUNC_DBG_MON_A21 (MTK_PIN_NO(89) | 7) - -#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) -#define PINMUX_GPIO90__FUNC_PWM_A (MTK_PIN_NO(90) | 1) -#define PINMUX_GPIO90__FUNC_CMMCLK2 (MTK_PIN_NO(90) | 2) -#define PINMUX_GPIO90__FUNC_I2S5_LRCK (MTK_PIN_NO(90) | 3) -#define PINMUX_GPIO90__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(90) | 4) -#define PINMUX_GPIO90__FUNC_SCL8 (MTK_PIN_NO(90) | 5) -#define PINMUX_GPIO90__FUNC_PTA_RXD (MTK_PIN_NO(90) | 6) -#define PINMUX_GPIO90__FUNC_DBG_MON_A22 (MTK_PIN_NO(90) | 7) - -#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) -#define PINMUX_GPIO91__FUNC_KPROW1 (MTK_PIN_NO(91) | 1) -#define PINMUX_GPIO91__FUNC_PWM_B (MTK_PIN_NO(91) | 2) -#define PINMUX_GPIO91__FUNC_I2S5_DO (MTK_PIN_NO(91) | 3) -#define PINMUX_GPIO91__FUNC_ANT_SEL7 (MTK_PIN_NO(91) | 4) -#define PINMUX_GPIO91__FUNC_CMMCLK3 (MTK_PIN_NO(91) | 5) -#define PINMUX_GPIO91__FUNC_PTA_TXD (MTK_PIN_NO(91) | 6) - -#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) -#define PINMUX_GPIO92__FUNC_KPROW0 (MTK_PIN_NO(92) | 1) - -#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) -#define PINMUX_GPIO93__FUNC_KPCOL0 (MTK_PIN_NO(93) | 1) -#define PINMUX_GPIO93__FUNC_DBG_MON_B27 (MTK_PIN_NO(93) | 7) - -#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) -#define PINMUX_GPIO94__FUNC_KPCOL1 (MTK_PIN_NO(94) | 1) -#define PINMUX_GPIO94__FUNC_I2S2_DI2 (MTK_PIN_NO(94) | 2) -#define PINMUX_GPIO94__FUNC_I2S5_MCK (MTK_PIN_NO(94) | 3) -#define PINMUX_GPIO94__FUNC_CMMCLK2 (MTK_PIN_NO(94) | 4) -#define PINMUX_GPIO94__FUNC_SCP_SPI2_MI (MTK_PIN_NO(94) | 5) -#define PINMUX_GPIO94__FUNC_SRCLKENAI1 (MTK_PIN_NO(94) | 6) -#define PINMUX_GPIO94__FUNC_SPI2_MI (MTK_PIN_NO(94) | 7) - -#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) -#define PINMUX_GPIO95__FUNC_URXD0 (MTK_PIN_NO(95) | 1) -#define PINMUX_GPIO95__FUNC_UTXD0 (MTK_PIN_NO(95) | 2) -#define PINMUX_GPIO95__FUNC_MD_URXD0 (MTK_PIN_NO(95) | 3) -#define PINMUX_GPIO95__FUNC_MD_URXD1 (MTK_PIN_NO(95) | 4) -#define PINMUX_GPIO95__FUNC_SSPM_URXD_AO (MTK_PIN_NO(95) | 5) -#define PINMUX_GPIO95__FUNC_CCU_URXD_AO (MTK_PIN_NO(95) | 6) - -#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) -#define PINMUX_GPIO96__FUNC_UTXD0 (MTK_PIN_NO(96) | 1) -#define PINMUX_GPIO96__FUNC_URXD0 (MTK_PIN_NO(96) | 2) -#define PINMUX_GPIO96__FUNC_MD_UTXD0 (MTK_PIN_NO(96) | 3) -#define PINMUX_GPIO96__FUNC_MD_UTXD1 (MTK_PIN_NO(96) | 4) -#define PINMUX_GPIO96__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(96) | 5) -#define PINMUX_GPIO96__FUNC_CCU_UTXD_AO (MTK_PIN_NO(96) | 6) -#define PINMUX_GPIO96__FUNC_DBG_MON_B2 (MTK_PIN_NO(96) | 7) - -#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) -#define PINMUX_GPIO97__FUNC_UCTS0 (MTK_PIN_NO(97) | 1) -#define PINMUX_GPIO97__FUNC_I2S2_MCK (MTK_PIN_NO(97) | 2) -#define PINMUX_GPIO97__FUNC_IDDIG (MTK_PIN_NO(97) | 3) -#define PINMUX_GPIO97__FUNC_CONN_MCU_TDO (MTK_PIN_NO(97) | 4) -#define PINMUX_GPIO97__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(97) | 5) -#define PINMUX_GPIO97__FUNC_IO_JTAG_TDO (MTK_PIN_NO(97) | 6) -#define PINMUX_GPIO97__FUNC_DBG_MON_B3 (MTK_PIN_NO(97) | 7) - -#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) -#define PINMUX_GPIO98__FUNC_URTS0 (MTK_PIN_NO(98) | 1) -#define PINMUX_GPIO98__FUNC_I2S2_BCK (MTK_PIN_NO(98) | 2) -#define PINMUX_GPIO98__FUNC_USB_DRVVBUS (MTK_PIN_NO(98) | 3) -#define PINMUX_GPIO98__FUNC_CONN_MCU_TMS (MTK_PIN_NO(98) | 4) -#define PINMUX_GPIO98__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(98) | 5) -#define PINMUX_GPIO98__FUNC_IO_JTAG_TMS (MTK_PIN_NO(98) | 6) -#define PINMUX_GPIO98__FUNC_DBG_MON_B4 (MTK_PIN_NO(98) | 7) - -#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) -#define PINMUX_GPIO99__FUNC_CMMCLK0 (MTK_PIN_NO(99) | 1) -#define PINMUX_GPIO99__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(99) | 4) -#define PINMUX_GPIO99__FUNC_DBG_MON_B28 (MTK_PIN_NO(99) | 7) - -#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) -#define PINMUX_GPIO100__FUNC_CMMCLK1 (MTK_PIN_NO(100) | 1) -#define PINMUX_GPIO100__FUNC_PWM_C (MTK_PIN_NO(100) | 2) -#define PINMUX_GPIO100__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(100) | 3) -#define PINMUX_GPIO100__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(100) | 4) -#define PINMUX_GPIO100__FUNC_DBG_MON_B29 (MTK_PIN_NO(100) | 7) - -#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) -#define PINMUX_GPIO101__FUNC_CLKM2 (MTK_PIN_NO(101) | 1) -#define PINMUX_GPIO101__FUNC_I2S2_LRCK (MTK_PIN_NO(101) | 2) -#define PINMUX_GPIO101__FUNC_CMVREF1 (MTK_PIN_NO(101) | 3) -#define PINMUX_GPIO101__FUNC_CONN_MCU_TCK (MTK_PIN_NO(101) | 4) -#define PINMUX_GPIO101__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(101) | 5) -#define PINMUX_GPIO101__FUNC_IO_JTAG_TCK (MTK_PIN_NO(101) | 6) - -#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) -#define PINMUX_GPIO102__FUNC_CLKM1 (MTK_PIN_NO(102) | 1) -#define PINMUX_GPIO102__FUNC_I2S2_DI (MTK_PIN_NO(102) | 2) -#define PINMUX_GPIO102__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(102) | 3) -#define PINMUX_GPIO102__FUNC_CONN_MCU_TDI (MTK_PIN_NO(102) | 4) -#define PINMUX_GPIO102__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(102) | 5) -#define PINMUX_GPIO102__FUNC_IO_JTAG_TDI (MTK_PIN_NO(102) | 6) -#define PINMUX_GPIO102__FUNC_DBG_MON_B8 (MTK_PIN_NO(102) | 7) - -#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) -#define PINMUX_GPIO103__FUNC_SCL2 (MTK_PIN_NO(103) | 1) - -#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) -#define PINMUX_GPIO104__FUNC_SDA2 (MTK_PIN_NO(104) | 1) - -#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) -#define PINMUX_GPIO105__FUNC_SCL4 (MTK_PIN_NO(105) | 1) - -#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) -#define PINMUX_GPIO106__FUNC_SDA4 (MTK_PIN_NO(106) | 1) - -#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) -#define PINMUX_GPIO107__FUNC_DMIC_CLK (MTK_PIN_NO(107) | 1) -#define PINMUX_GPIO107__FUNC_ANT_SEL0 (MTK_PIN_NO(107) | 2) -#define PINMUX_GPIO107__FUNC_CLKM0 (MTK_PIN_NO(107) | 3) -#define PINMUX_GPIO107__FUNC_SDA7 (MTK_PIN_NO(107) | 4) -#define PINMUX_GPIO107__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(107) | 5) -#define PINMUX_GPIO107__FUNC_PWM_A (MTK_PIN_NO(107) | 6) -#define PINMUX_GPIO107__FUNC_DBG_MON_B12 (MTK_PIN_NO(107) | 7) - -#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) -#define PINMUX_GPIO108__FUNC_CMMCLK2 (MTK_PIN_NO(108) | 1) -#define PINMUX_GPIO108__FUNC_ANT_SEL1 (MTK_PIN_NO(108) | 2) -#define PINMUX_GPIO108__FUNC_CLKM1 (MTK_PIN_NO(108) | 3) -#define PINMUX_GPIO108__FUNC_SCL8 (MTK_PIN_NO(108) | 4) -#define PINMUX_GPIO108__FUNC_DAP_MD32_SWD (MTK_PIN_NO(108) | 5) -#define PINMUX_GPIO108__FUNC_PWM_B (MTK_PIN_NO(108) | 6) -#define PINMUX_GPIO108__FUNC_DBG_MON_B13 (MTK_PIN_NO(108) | 7) - -#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) -#define PINMUX_GPIO109__FUNC_DMIC_DAT (MTK_PIN_NO(109) | 1) -#define PINMUX_GPIO109__FUNC_ANT_SEL2 (MTK_PIN_NO(109) | 2) -#define PINMUX_GPIO109__FUNC_CLKM2 (MTK_PIN_NO(109) | 3) -#define PINMUX_GPIO109__FUNC_SDA8 (MTK_PIN_NO(109) | 4) -#define PINMUX_GPIO109__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(109) | 5) -#define PINMUX_GPIO109__FUNC_PWM_C (MTK_PIN_NO(109) | 6) -#define PINMUX_GPIO109__FUNC_DBG_MON_B14 (MTK_PIN_NO(109) | 7) - -#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) -#define PINMUX_GPIO110__FUNC_SCL7 (MTK_PIN_NO(110) | 1) -#define PINMUX_GPIO110__FUNC_ANT_SEL0 (MTK_PIN_NO(110) | 2) -#define PINMUX_GPIO110__FUNC_TP_URXD1_AO (MTK_PIN_NO(110) | 3) -#define PINMUX_GPIO110__FUNC_USB_DRVVBUS (MTK_PIN_NO(110) | 4) -#define PINMUX_GPIO110__FUNC_SRCLKENAI1 (MTK_PIN_NO(110) | 5) -#define PINMUX_GPIO110__FUNC_KPCOL2 (MTK_PIN_NO(110) | 6) -#define PINMUX_GPIO110__FUNC_URXD1 (MTK_PIN_NO(110) | 7) - -#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) -#define PINMUX_GPIO111__FUNC_CMMCLK3 (MTK_PIN_NO(111) | 1) -#define PINMUX_GPIO111__FUNC_ANT_SEL1 (MTK_PIN_NO(111) | 2) -#define PINMUX_GPIO111__FUNC_SRCLKENAI0 (MTK_PIN_NO(111) | 3) -#define PINMUX_GPIO111__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(111) | 4) -#define PINMUX_GPIO111__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(111) | 5) -#define PINMUX_GPIO111__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(111) | 7) - -#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) -#define PINMUX_GPIO112__FUNC_SDA7 (MTK_PIN_NO(112) | 1) -#define PINMUX_GPIO112__FUNC_ANT_SEL2 (MTK_PIN_NO(112) | 2) -#define PINMUX_GPIO112__FUNC_TP_UTXD1_AO (MTK_PIN_NO(112) | 3) -#define PINMUX_GPIO112__FUNC_IDDIG (MTK_PIN_NO(112) | 4) -#define PINMUX_GPIO112__FUNC_AGPS_SYNC (MTK_PIN_NO(112) | 5) -#define PINMUX_GPIO112__FUNC_KPROW2 (MTK_PIN_NO(112) | 6) -#define PINMUX_GPIO112__FUNC_UTXD1 (MTK_PIN_NO(112) | 7) - -#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) -#define PINMUX_GPIO113__FUNC_CONN_TOP_CLK (MTK_PIN_NO(113) | 1) -#define PINMUX_GPIO113__FUNC_SCL6 (MTK_PIN_NO(113) | 3) -#define PINMUX_GPIO113__FUNC_AUXIF_CLK0 (MTK_PIN_NO(113) | 4) -#define PINMUX_GPIO113__FUNC_TP_UCTS1_AO (MTK_PIN_NO(113) | 6) - -#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) -#define PINMUX_GPIO114__FUNC_CONN_TOP_DATA (MTK_PIN_NO(114) | 1) -#define PINMUX_GPIO114__FUNC_SDA6 (MTK_PIN_NO(114) | 3) -#define PINMUX_GPIO114__FUNC_AUXIF_ST0 (MTK_PIN_NO(114) | 4) -#define PINMUX_GPIO114__FUNC_TP_URTS1_AO (MTK_PIN_NO(114) | 6) - -#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) -#define PINMUX_GPIO115__FUNC_CONN_BT_CLK (MTK_PIN_NO(115) | 1) -#define PINMUX_GPIO115__FUNC_UTXD1 (MTK_PIN_NO(115) | 2) -#define PINMUX_GPIO115__FUNC_PTA_TXD (MTK_PIN_NO(115) | 3) -#define PINMUX_GPIO115__FUNC_AUXIF_CLK1 (MTK_PIN_NO(115) | 4) -#define PINMUX_GPIO115__FUNC_DAP_MD32_SWD (MTK_PIN_NO(115) | 5) -#define PINMUX_GPIO115__FUNC_TP_UTXD1_AO (MTK_PIN_NO(115) | 6) - -#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) -#define PINMUX_GPIO116__FUNC_CONN_BT_DATA (MTK_PIN_NO(116) | 1) -#define PINMUX_GPIO116__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(116) | 2) -#define PINMUX_GPIO116__FUNC_AUXIF_ST1 (MTK_PIN_NO(116) | 4) -#define PINMUX_GPIO116__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(116) | 5) -#define PINMUX_GPIO116__FUNC_TP_URXD2_AO (MTK_PIN_NO(116) | 6) -#define PINMUX_GPIO116__FUNC_DBG_MON_A0 (MTK_PIN_NO(116) | 7) - -#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) -#define PINMUX_GPIO117__FUNC_CONN_WF_HB0 (MTK_PIN_NO(117) | 1) -#define PINMUX_GPIO117__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(117) | 2) -#define PINMUX_GPIO117__FUNC_TP_UTXD2_AO (MTK_PIN_NO(117) | 6) -#define PINMUX_GPIO117__FUNC_DBG_MON_A4 (MTK_PIN_NO(117) | 7) - -#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) -#define PINMUX_GPIO118__FUNC_CONN_WF_HB1 (MTK_PIN_NO(118) | 1) -#define PINMUX_GPIO118__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(118) | 2) -#define PINMUX_GPIO118__FUNC_SSPM_URXD_AO (MTK_PIN_NO(118) | 5) -#define PINMUX_GPIO118__FUNC_TP_UCTS2_AO (MTK_PIN_NO(118) | 6) -#define PINMUX_GPIO118__FUNC_DBG_MON_A5 (MTK_PIN_NO(118) | 7) - -#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) -#define PINMUX_GPIO119__FUNC_CONN_WF_HB2 (MTK_PIN_NO(119) | 1) -#define PINMUX_GPIO119__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(119) | 2) -#define PINMUX_GPIO119__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(119) | 5) -#define PINMUX_GPIO119__FUNC_TP_URTS2_AO (MTK_PIN_NO(119) | 6) - -#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) -#define PINMUX_GPIO120__FUNC_CONN_WB_PTA (MTK_PIN_NO(120) | 1) -#define PINMUX_GPIO120__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(120) | 2) -#define PINMUX_GPIO120__FUNC_CCU_URXD_AO (MTK_PIN_NO(120) | 5) - -#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) -#define PINMUX_GPIO121__FUNC_CONN_HRST_B (MTK_PIN_NO(121) | 1) -#define PINMUX_GPIO121__FUNC_URXD1 (MTK_PIN_NO(121) | 2) -#define PINMUX_GPIO121__FUNC_PTA_RXD (MTK_PIN_NO(121) | 3) -#define PINMUX_GPIO121__FUNC_CCU_UTXD_AO (MTK_PIN_NO(121) | 5) -#define PINMUX_GPIO121__FUNC_TP_URXD1_AO (MTK_PIN_NO(121) | 6) - -#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) -#define PINMUX_GPIO122__FUNC_MSDC0_CMD (MTK_PIN_NO(122) | 1) -#define PINMUX_GPIO122__FUNC_SSPM_URXD2_AO (MTK_PIN_NO(122) | 2) -#define PINMUX_GPIO122__FUNC_ANT_SEL1 (MTK_PIN_NO(122) | 3) -#define PINMUX_GPIO122__FUNC_DBG_MON_A12 (MTK_PIN_NO(122) | 7) - -#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) -#define PINMUX_GPIO123__FUNC_MSDC0_DAT0 (MTK_PIN_NO(123) | 1) -#define PINMUX_GPIO123__FUNC_ANT_SEL0 (MTK_PIN_NO(123) | 3) -#define PINMUX_GPIO123__FUNC_DBG_MON_A13 (MTK_PIN_NO(123) | 7) - -#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) -#define PINMUX_GPIO124__FUNC_MSDC0_CLK (MTK_PIN_NO(124) | 1) -#define PINMUX_GPIO124__FUNC_DBG_MON_A14 (MTK_PIN_NO(124) | 7) - -#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) -#define PINMUX_GPIO125__FUNC_MSDC0_DAT2 (MTK_PIN_NO(125) | 1) -#define PINMUX_GPIO125__FUNC_MRG_CLK (MTK_PIN_NO(125) | 3) -#define PINMUX_GPIO125__FUNC_DBG_MON_A15 (MTK_PIN_NO(125) | 7) - -#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) -#define PINMUX_GPIO126__FUNC_MSDC0_DAT4 (MTK_PIN_NO(126) | 1) -#define PINMUX_GPIO126__FUNC_ANT_SEL5 (MTK_PIN_NO(126) | 3) -#define PINMUX_GPIO126__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(126) | 6) -#define PINMUX_GPIO126__FUNC_DBG_MON_A16 (MTK_PIN_NO(126) | 7) - -#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) -#define PINMUX_GPIO127__FUNC_MSDC0_DAT6 (MTK_PIN_NO(127) | 1) -#define PINMUX_GPIO127__FUNC_ANT_SEL4 (MTK_PIN_NO(127) | 3) -#define PINMUX_GPIO127__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(127) | 6) -#define PINMUX_GPIO127__FUNC_DBG_MON_A17 (MTK_PIN_NO(127) | 7) - -#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) -#define PINMUX_GPIO128__FUNC_MSDC0_DAT1 (MTK_PIN_NO(128) | 1) -#define PINMUX_GPIO128__FUNC_ANT_SEL2 (MTK_PIN_NO(128) | 3) -#define PINMUX_GPIO128__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(128) | 6) -#define PINMUX_GPIO128__FUNC_DBG_MON_A18 (MTK_PIN_NO(128) | 7) - -#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) -#define PINMUX_GPIO129__FUNC_MSDC0_DAT5 (MTK_PIN_NO(129) | 1) -#define PINMUX_GPIO129__FUNC_ANT_SEL3 (MTK_PIN_NO(129) | 3) -#define PINMUX_GPIO129__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(129) | 6) -#define PINMUX_GPIO129__FUNC_DBG_MON_A23 (MTK_PIN_NO(129) | 7) - -#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) -#define PINMUX_GPIO130__FUNC_MSDC0_DAT7 (MTK_PIN_NO(130) | 1) -#define PINMUX_GPIO130__FUNC_MRG_DO (MTK_PIN_NO(130) | 3) -#define PINMUX_GPIO130__FUNC_DBG_MON_A24 (MTK_PIN_NO(130) | 7) - -#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) -#define PINMUX_GPIO131__FUNC_MSDC0_DSL (MTK_PIN_NO(131) | 1) -#define PINMUX_GPIO131__FUNC_MRG_SYNC (MTK_PIN_NO(131) | 3) -#define PINMUX_GPIO131__FUNC_DBG_MON_A25 (MTK_PIN_NO(131) | 7) - -#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) -#define PINMUX_GPIO132__FUNC_MSDC0_DAT3 (MTK_PIN_NO(132) | 1) -#define PINMUX_GPIO132__FUNC_MRG_DI (MTK_PIN_NO(132) | 3) -#define PINMUX_GPIO132__FUNC_DBG_MON_A26 (MTK_PIN_NO(132) | 7) - -#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) -#define PINMUX_GPIO133__FUNC_MSDC0_RSTB (MTK_PIN_NO(133) | 1) -#define PINMUX_GPIO133__FUNC_AGPS_SYNC (MTK_PIN_NO(133) | 3) -#define PINMUX_GPIO133__FUNC_DBG_MON_A27 (MTK_PIN_NO(133) | 7) - -#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) -#define PINMUX_GPIO134__FUNC_RTC32K_CK (MTK_PIN_NO(134) | 1) - -#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) -#define PINMUX_GPIO135__FUNC_WATCHDOG (MTK_PIN_NO(135) | 1) - -#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) -#define PINMUX_GPIO136__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(136) | 1) -#define PINMUX_GPIO136__FUNC_AUD_CLK_MISO (MTK_PIN_NO(136) | 2) -#define PINMUX_GPIO136__FUNC_I2S1_MCK (MTK_PIN_NO(136) | 3) -#define PINMUX_GPIO136__FUNC_UFS_UNIPRO_SCL (MTK_PIN_NO(136) | 6) - -#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) -#define PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(137) | 1) -#define PINMUX_GPIO137__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(137) | 2) -#define PINMUX_GPIO137__FUNC_I2S1_BCK (MTK_PIN_NO(137) | 3) - -#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) -#define PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(138) | 1) -#define PINMUX_GPIO138__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(138) | 2) -#define PINMUX_GPIO138__FUNC_I2S1_LRCK (MTK_PIN_NO(138) | 3) -#define PINMUX_GPIO138__FUNC_DBG_MON_B24 (MTK_PIN_NO(138) | 7) - -#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) -#define PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(139) | 1) -#define PINMUX_GPIO139__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(139) | 2) -#define PINMUX_GPIO139__FUNC_I2S1_DO (MTK_PIN_NO(139) | 3) -#define PINMUX_GPIO139__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(139) | 6) - -#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) -#define PINMUX_GPIO140__FUNC_AUD_CLK_MISO (MTK_PIN_NO(140) | 1) -#define PINMUX_GPIO140__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(140) | 2) -#define PINMUX_GPIO140__FUNC_I2S0_MCK (MTK_PIN_NO(140) | 3) -#define PINMUX_GPIO140__FUNC_UFS_UNIPRO_SDA (MTK_PIN_NO(140) | 6) - -#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) -#define PINMUX_GPIO141__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(141) | 1) -#define PINMUX_GPIO141__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(141) | 2) -#define PINMUX_GPIO141__FUNC_I2S0_BCK (MTK_PIN_NO(141) | 3) - -#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) -#define PINMUX_GPIO142__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(142) | 1) -#define PINMUX_GPIO142__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(142) | 2) -#define PINMUX_GPIO142__FUNC_I2S0_LRCK (MTK_PIN_NO(142) | 3) -#define PINMUX_GPIO142__FUNC_VOW_DAT_MISO (MTK_PIN_NO(142) | 4) -#define PINMUX_GPIO142__FUNC_DBG_MON_B25 (MTK_PIN_NO(142) | 7) - -#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) -#define PINMUX_GPIO143__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(143) | 1) -#define PINMUX_GPIO143__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(143) | 2) -#define PINMUX_GPIO143__FUNC_I2S0_DI (MTK_PIN_NO(143) | 3) -#define PINMUX_GPIO143__FUNC_VOW_CLK_MISO (MTK_PIN_NO(143) | 4) -#define PINMUX_GPIO143__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(143) | 6) -#define PINMUX_GPIO143__FUNC_DBG_MON_B26 (MTK_PIN_NO(143) | 7) - -#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) -#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(144) | 1) -#define PINMUX_GPIO144__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(144) | 2) - -#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) -#define PINMUX_GPIO145__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(145) | 1) - -#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) -#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(146) | 1) -#define PINMUX_GPIO146__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(146) | 2) - -#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) -#define PINMUX_GPIO147__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(147) | 1) - -#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) -#define PINMUX_GPIO148__FUNC_SRCLKENA0 (MTK_PIN_NO(148) | 1) - -#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) -#define PINMUX_GPIO149__FUNC_SRCLKENA1 (MTK_PIN_NO(149) | 1) - -#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) -#define PINMUX_GPIO150__FUNC_PWM_A (MTK_PIN_NO(150) | 1) -#define PINMUX_GPIO150__FUNC_CMFLASH (MTK_PIN_NO(150) | 2) -#define PINMUX_GPIO150__FUNC_CLKM0 (MTK_PIN_NO(150) | 3) -#define PINMUX_GPIO150__FUNC_DBG_MON_B30 (MTK_PIN_NO(150) | 7) - -#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) -#define PINMUX_GPIO151__FUNC_PWM_B (MTK_PIN_NO(151) | 1) -#define PINMUX_GPIO151__FUNC_CMVREF0 (MTK_PIN_NO(151) | 2) -#define PINMUX_GPIO151__FUNC_CLKM1 (MTK_PIN_NO(151) | 3) -#define PINMUX_GPIO151__FUNC_DBG_MON_B20 (MTK_PIN_NO(151) | 7) - -#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) -#define PINMUX_GPIO152__FUNC_PWM_C (MTK_PIN_NO(152) | 1) -#define PINMUX_GPIO152__FUNC_CMFLASH (MTK_PIN_NO(152) | 2) -#define PINMUX_GPIO152__FUNC_CLKM2 (MTK_PIN_NO(152) | 3) -#define PINMUX_GPIO152__FUNC_DBG_MON_B21 (MTK_PIN_NO(152) | 7) - -#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) -#define PINMUX_GPIO153__FUNC_PWM_A (MTK_PIN_NO(153) | 1) -#define PINMUX_GPIO153__FUNC_CMVREF0 (MTK_PIN_NO(153) | 2) -#define PINMUX_GPIO153__FUNC_CLKM3 (MTK_PIN_NO(153) | 3) -#define PINMUX_GPIO153__FUNC_DBG_MON_B22 (MTK_PIN_NO(153) | 7) - -#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) -#define PINMUX_GPIO154__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(154) | 1) -#define PINMUX_GPIO154__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(154) | 2) -#define PINMUX_GPIO154__FUNC_DBG_MON_B18 (MTK_PIN_NO(154) | 7) - -#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) -#define PINMUX_GPIO155__FUNC_ANT_SEL0 (MTK_PIN_NO(155) | 1) -#define PINMUX_GPIO155__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(155) | 2) -#define PINMUX_GPIO155__FUNC_CMVREF1 (MTK_PIN_NO(155) | 3) -#define PINMUX_GPIO155__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(155) | 7) - -#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) -#define PINMUX_GPIO156__FUNC_ANT_SEL1 (MTK_PIN_NO(156) | 1) -#define PINMUX_GPIO156__FUNC_SRCLKENAI0 (MTK_PIN_NO(156) | 2) -#define PINMUX_GPIO156__FUNC_SCL6 (MTK_PIN_NO(156) | 3) -#define PINMUX_GPIO156__FUNC_KPCOL2 (MTK_PIN_NO(156) | 4) -#define PINMUX_GPIO156__FUNC_IDDIG (MTK_PIN_NO(156) | 5) -#define PINMUX_GPIO156__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(156) | 7) - -#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) -#define PINMUX_GPIO157__FUNC_ANT_SEL2 (MTK_PIN_NO(157) | 1) -#define PINMUX_GPIO157__FUNC_SRCLKENAI1 (MTK_PIN_NO(157) | 2) -#define PINMUX_GPIO157__FUNC_SDA6 (MTK_PIN_NO(157) | 3) -#define PINMUX_GPIO157__FUNC_KPROW2 (MTK_PIN_NO(157) | 4) -#define PINMUX_GPIO157__FUNC_USB_DRVVBUS (MTK_PIN_NO(157) | 5) -#define PINMUX_GPIO157__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(157) | 7) - -#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) -#define PINMUX_GPIO158__FUNC_ANT_SEL3 (MTK_PIN_NO(158) | 1) - -#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) -#define PINMUX_GPIO159__FUNC_ANT_SEL4 (MTK_PIN_NO(159) | 1) - -#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) -#define PINMUX_GPIO160__FUNC_ANT_SEL5 (MTK_PIN_NO(160) | 1) - -#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) -#define PINMUX_GPIO161__FUNC_SPI1_A_MI (MTK_PIN_NO(161) | 1) -#define PINMUX_GPIO161__FUNC_SCP_SPI1_MI (MTK_PIN_NO(161) | 2) -#define PINMUX_GPIO161__FUNC_IDDIG (MTK_PIN_NO(161) | 3) -#define PINMUX_GPIO161__FUNC_ANT_SEL6 (MTK_PIN_NO(161) | 4) -#define PINMUX_GPIO161__FUNC_KPCOL2 (MTK_PIN_NO(161) | 5) -#define PINMUX_GPIO161__FUNC_PTA_RXD (MTK_PIN_NO(161) | 6) -#define PINMUX_GPIO161__FUNC_DBG_MON_B19 (MTK_PIN_NO(161) | 7) - -#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) -#define PINMUX_GPIO162__FUNC_SPI1_A_CSB (MTK_PIN_NO(162) | 1) -#define PINMUX_GPIO162__FUNC_SCP_SPI1_CS (MTK_PIN_NO(162) | 2) -#define PINMUX_GPIO162__FUNC_USB_DRVVBUS (MTK_PIN_NO(162) | 3) -#define PINMUX_GPIO162__FUNC_ANT_SEL5 (MTK_PIN_NO(162) | 4) -#define PINMUX_GPIO162__FUNC_KPROW2 (MTK_PIN_NO(162) | 5) -#define PINMUX_GPIO162__FUNC_PTA_TXD (MTK_PIN_NO(162) | 6) - -#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) -#define PINMUX_GPIO163__FUNC_SPI1_A_MO (MTK_PIN_NO(163) | 1) -#define PINMUX_GPIO163__FUNC_SCP_SPI1_MO (MTK_PIN_NO(163) | 2) -#define PINMUX_GPIO163__FUNC_SDA1 (MTK_PIN_NO(163) | 3) -#define PINMUX_GPIO163__FUNC_ANT_SEL4 (MTK_PIN_NO(163) | 4) -#define PINMUX_GPIO163__FUNC_CMMCLK2 (MTK_PIN_NO(163) | 5) -#define PINMUX_GPIO163__FUNC_DMIC_CLK (MTK_PIN_NO(163) | 6) - -#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) -#define PINMUX_GPIO164__FUNC_SPI1_A_CLK (MTK_PIN_NO(164) | 1) -#define PINMUX_GPIO164__FUNC_SCP_SPI1_CK (MTK_PIN_NO(164) | 2) -#define PINMUX_GPIO164__FUNC_SCL1 (MTK_PIN_NO(164) | 3) -#define PINMUX_GPIO164__FUNC_ANT_SEL3 (MTK_PIN_NO(164) | 4) -#define PINMUX_GPIO164__FUNC_CMMCLK3 (MTK_PIN_NO(164) | 5) -#define PINMUX_GPIO164__FUNC_DMIC_DAT (MTK_PIN_NO(164) | 6) - -#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) -#define PINMUX_GPIO165__FUNC_PWM_B (MTK_PIN_NO(165) | 1) -#define PINMUX_GPIO165__FUNC_CMMCLK2 (MTK_PIN_NO(165) | 2) -#define PINMUX_GPIO165__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(165) | 3) -#define PINMUX_GPIO165__FUNC_TDM_MCK_2ND (MTK_PIN_NO(165) | 6) -#define PINMUX_GPIO165__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(165) | 7) - -#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) -#define PINMUX_GPIO166__FUNC_ANT_SEL6 (MTK_PIN_NO(166) | 1) - -#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) -#define PINMUX_GPIO167__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(167) | 1) -#define PINMUX_GPIO167__FUNC_SPM_BSI_EN (MTK_PIN_NO(167) | 2) - -#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) -#define PINMUX_GPIO168__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(168) | 1) -#define PINMUX_GPIO168__FUNC_SPM_BSI_CK (MTK_PIN_NO(168) | 2) - -#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) -#define PINMUX_GPIO169__FUNC_PWM_C (MTK_PIN_NO(169) | 1) -#define PINMUX_GPIO169__FUNC_CMMCLK3 (MTK_PIN_NO(169) | 2) -#define PINMUX_GPIO169__FUNC_CMVREF1 (MTK_PIN_NO(169) | 3) -#define PINMUX_GPIO169__FUNC_ANT_SEL7 (MTK_PIN_NO(169) | 4) -#define PINMUX_GPIO169__FUNC_AGPS_SYNC (MTK_PIN_NO(169) | 5) -#define PINMUX_GPIO169__FUNC_TDM_BCK_2ND (MTK_PIN_NO(169) | 6) -#define PINMUX_GPIO169__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(169) | 7) - -#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) -#define PINMUX_GPIO170__FUNC_I2S1_BCK (MTK_PIN_NO(170) | 1) -#define PINMUX_GPIO170__FUNC_I2S3_BCK (MTK_PIN_NO(170) | 2) -#define PINMUX_GPIO170__FUNC_SCL7 (MTK_PIN_NO(170) | 3) -#define PINMUX_GPIO170__FUNC_I2S5_BCK (MTK_PIN_NO(170) | 4) -#define PINMUX_GPIO170__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(170) | 5) -#define PINMUX_GPIO170__FUNC_TDM_LRCK_2ND (MTK_PIN_NO(170) | 6) -#define PINMUX_GPIO170__FUNC_ANT_SEL3 (MTK_PIN_NO(170) | 7) - -#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) -#define PINMUX_GPIO171__FUNC_I2S1_LRCK (MTK_PIN_NO(171) | 1) -#define PINMUX_GPIO171__FUNC_I2S3_LRCK (MTK_PIN_NO(171) | 2) -#define PINMUX_GPIO171__FUNC_SDA7 (MTK_PIN_NO(171) | 3) -#define PINMUX_GPIO171__FUNC_I2S5_LRCK (MTK_PIN_NO(171) | 4) -#define PINMUX_GPIO171__FUNC_URXD1 (MTK_PIN_NO(171) | 5) -#define PINMUX_GPIO171__FUNC_TDM_DATA0_2ND (MTK_PIN_NO(171) | 6) -#define PINMUX_GPIO171__FUNC_ANT_SEL4 (MTK_PIN_NO(171) | 7) - -#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) -#define PINMUX_GPIO172__FUNC_I2S1_DO (MTK_PIN_NO(172) | 1) -#define PINMUX_GPIO172__FUNC_I2S3_DO (MTK_PIN_NO(172) | 2) -#define PINMUX_GPIO172__FUNC_SCL8 (MTK_PIN_NO(172) | 3) -#define PINMUX_GPIO172__FUNC_I2S5_DO (MTK_PIN_NO(172) | 4) -#define PINMUX_GPIO172__FUNC_UTXD1 (MTK_PIN_NO(172) | 5) -#define PINMUX_GPIO172__FUNC_TDM_DATA1_2ND (MTK_PIN_NO(172) | 6) -#define PINMUX_GPIO172__FUNC_ANT_SEL5 (MTK_PIN_NO(172) | 7) - -#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) -#define PINMUX_GPIO173__FUNC_I2S1_MCK (MTK_PIN_NO(173) | 1) -#define PINMUX_GPIO173__FUNC_I2S3_MCK (MTK_PIN_NO(173) | 2) -#define PINMUX_GPIO173__FUNC_SDA8 (MTK_PIN_NO(173) | 3) -#define PINMUX_GPIO173__FUNC_I2S5_MCK (MTK_PIN_NO(173) | 4) -#define PINMUX_GPIO173__FUNC_UCTS0 (MTK_PIN_NO(173) | 5) -#define PINMUX_GPIO173__FUNC_TDM_DATA2_2ND (MTK_PIN_NO(173) | 6) -#define PINMUX_GPIO173__FUNC_ANT_SEL6 (MTK_PIN_NO(173) | 7) - -#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) -#define PINMUX_GPIO174__FUNC_I2S2_DI (MTK_PIN_NO(174) | 1) -#define PINMUX_GPIO174__FUNC_I2S0_DI (MTK_PIN_NO(174) | 2) -#define PINMUX_GPIO174__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(174) | 3) -#define PINMUX_GPIO174__FUNC_I2S2_DI2 (MTK_PIN_NO(174) | 4) -#define PINMUX_GPIO174__FUNC_URTS0 (MTK_PIN_NO(174) | 5) -#define PINMUX_GPIO174__FUNC_TDM_DATA3_2ND (MTK_PIN_NO(174) | 6) -#define PINMUX_GPIO174__FUNC_ANT_SEL7 (MTK_PIN_NO(174) | 7) - -#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) -#define PINMUX_GPIO175__FUNC_ANT_SEL7 (MTK_PIN_NO(175) | 1) - -#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) - -#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) - -#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) - -#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) - -#endif /* __MT8183-PINFUNC_H */ diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi deleted file mode 100644 index 08a914d3a..000000000 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ /dev/null @@ -1,816 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (c) 2018 MediaTek Inc. - * Author: Ben Ho - * Erin Lo - */ - -#include -#include -#include -#include -#include -#include "mt8183-pinfunc.h" - -/ { - compatible = "mediatek,mt8183"; - interrupt-parent = <&sysirq>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - i2c9 = &i2c9; - i2c10 = &i2c10; - i2c11 = &i2c11; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x000>; - enable-method = "psci"; - capacity-dmips-mhz = <741>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; - dynamic-power-coefficient = <84>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x001>; - enable-method = "psci"; - capacity-dmips-mhz = <741>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; - dynamic-power-coefficient = <84>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x002>; - enable-method = "psci"; - capacity-dmips-mhz = <741>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; - dynamic-power-coefficient = <84>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x003>; - enable-method = "psci"; - capacity-dmips-mhz = <741>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; - dynamic-power-coefficient = <84>; - #cooling-cells = <2>; - }; - - cpu4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; - dynamic-power-coefficient = <211>; - #cooling-cells = <2>; - }; - - cpu5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x101>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; - dynamic-power-coefficient = <211>; - #cooling-cells = <2>; - }; - - cpu6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x102>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; - dynamic-power-coefficient = <211>; - #cooling-cells = <2>; - }; - - cpu7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - reg = <0x103>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; - dynamic-power-coefficient = <211>; - #cooling-cells = <2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x00010001>; - entry-latency-us = <200>; - exit-latency-us = <200>; - min-residency-us = <800>; - }; - - CLUSTER_SLEEP0: cluster-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x01010001>; - entry-latency-us = <250>; - exit-latency-us = <400>; - min-residency-us = <1000>; - }; - CLUSTER_SLEEP1: cluster-sleep-1 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x01010001>; - entry-latency-us = <250>; - exit-latency-us = <400>; - min-residency-us = <1300>; - }; - }; - }; - - pmu-a53 { - compatible = "arm,cortex-a53-pmu"; - interrupt-parent = <&gic>; - interrupts = ; - }; - - pmu-a73 { - compatible = "arm,cortex-a73-pmu"; - interrupt-parent = <&gic>; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - clk26m: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "clk26m"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - soc_data: soc_data@8000000 { - compatible = "mediatek,mt8183-efuse", - "mediatek,efuse"; - reg = <0 0x08000000 0 0x0010>; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - }; - - gic: interrupt-controller@c000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <4>; - interrupt-parent = <&gic>; - interrupt-controller; - reg = <0 0x0c000000 0 0x40000>, /* GICD */ - <0 0x0c100000 0 0x200000>, /* GICR */ - <0 0x0c400000 0 0x2000>, /* GICC */ - <0 0x0c410000 0 0x1000>, /* GICH */ - <0 0x0c420000 0 0x2000>; /* GICV */ - - interrupts = ; - ppi-partitions { - ppi_cluster0: interrupt-partition-0 { - affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; - }; - ppi_cluster1: interrupt-partition-1 { - affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; - }; - }; - }; - - mcucfg: syscon@c530000 { - compatible = "mediatek,mt8183-mcucfg", "syscon"; - reg = <0 0x0c530000 0 0x1000>; - #clock-cells = <1>; - }; - - sysirq: interrupt-controller@c530a80 { - compatible = "mediatek,mt8183-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x0c530a80 0 0x50>; - }; - - topckgen: syscon@10000000 { - compatible = "mediatek,mt8183-topckgen", "syscon"; - reg = <0 0x10000000 0 0x1000>; - #clock-cells = <1>; - }; - - infracfg: syscon@10001000 { - compatible = "mediatek,mt8183-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pericfg: syscon@10003000 { - compatible = "mediatek,mt8183-pericfg", "syscon"; - reg = <0 0x10003000 0 0x1000>; - #clock-cells = <1>; - }; - - pio: pinctrl@10005000 { - compatible = "mediatek,mt8183-pinctrl"; - reg = <0 0x10005000 0 0x1000>, - <0 0x11f20000 0 0x1000>, - <0 0x11e80000 0 0x1000>, - <0 0x11e70000 0 0x1000>, - <0 0x11e90000 0 0x1000>, - <0 0x11d30000 0 0x1000>, - <0 0x11d20000 0 0x1000>, - <0 0x11c50000 0 0x1000>, - <0 0x11f30000 0 0x1000>, - <0 0x1000b000 0 0x1000>; - reg-names = "iocfg0", "iocfg1", "iocfg2", - "iocfg3", "iocfg4", "iocfg5", - "iocfg6", "iocfg7", "iocfg8", - "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 192>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <2>; - }; - - watchdog: watchdog@10007000 { - compatible = "mediatek,mt8183-wdt"; - reg = <0 0x10007000 0 0x100>; - #reset-cells = <1>; - }; - - apmixedsys: syscon@1000c000 { - compatible = "mediatek,mt8183-apmixedsys", "syscon"; - reg = <0 0x1000c000 0 0x1000>; - #clock-cells = <1>; - }; - - pwrap: pwrap@1000d000 { - compatible = "mediatek,mt8183-pwrap"; - reg = <0 0x1000d000 0 0x1000>; - reg-names = "pwrap"; - interrupts = ; - clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, - <&infracfg CLK_INFRA_PMIC_AP>; - clock-names = "spi", "wrap"; - }; - - scp: scp@10500000 { - compatible = "mediatek,mt8183-scp"; - reg = <0 0x10500000 0 0x80000>, - <0 0x105c0000 0 0x19080>; - reg-names = "sram", "cfg"; - interrupts = ; - clocks = <&infracfg CLK_INFRA_SCPSYS>; - clock-names = "main"; - memory-region = <&scp_mem_reserved>; - status = "disabled"; - }; - - systimer: timer@10017000 { - compatible = "mediatek,mt8183-timer", - "mediatek,mt6765-timer"; - reg = <0 0x10017000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_CLK13M>; - clock-names = "clk13m"; - }; - - gce: mailbox@10238000 { - compatible = "mediatek,mt8183-gce"; - reg = <0 0x10238000 0 0x4000>; - interrupts = ; - #mbox-cells = <2>; - clocks = <&infracfg CLK_INFRA_GCE>; - clock-names = "gce"; - }; - - auxadc: auxadc@11001000 { - compatible = "mediatek,mt8183-auxadc", - "mediatek,mt8173-auxadc"; - reg = <0 0x11001000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_AUXADC>; - clock-names = "main"; - #io-channel-cells = <1>; - status = "disabled"; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt8183-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x1000>; - interrupts = ; - clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt8183-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x1000>; - interrupts = ; - clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt8183-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x1000>; - interrupts = ; - clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - i2c6: i2c@11005000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x11005000 0 0x1000>, - <0 0x11000600 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C6>, - <&infracfg CLK_INFRA_AP_DMA>; - clock-names = "main", "dma"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c0: i2c@11007000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x11007000 0 0x1000>, - <0 0x11000080 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C0>, - <&infracfg CLK_INFRA_AP_DMA>; - clock-names = "main", "dma"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@11008000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x11008000 0 0x1000>, - <0 0x11000100 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C1>, - <&infracfg CLK_INFRA_AP_DMA>, - <&infracfg CLK_INFRA_I2C1_ARBITER>; - clock-names = "main", "dma","arb"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@11009000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x11009000 0 0x1000>, - <0 0x11000280 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C2>, - <&infracfg CLK_INFRA_AP_DMA>, - <&infracfg CLK_INFRA_I2C2_ARBITER>; - clock-names = "main", "dma", "arb"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@1100a000 { - compatible = "mediatek,mt8183-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100a000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, - <&topckgen CLK_TOP_MUX_SPI>, - <&infracfg CLK_INFRA_SPI0>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - i2c3: i2c@1100f000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x1100f000 0 0x1000>, - <0 0x11000400 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C3>, - <&infracfg CLK_INFRA_AP_DMA>; - clock-names = "main", "dma"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@11010000 { - compatible = "mediatek,mt8183-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11010000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, - <&topckgen CLK_TOP_MUX_SPI>, - <&infracfg CLK_INFRA_SPI1>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - i2c1: i2c@11011000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x11011000 0 0x1000>, - <0 0x11000480 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C4>, - <&infracfg CLK_INFRA_AP_DMA>; - clock-names = "main", "dma"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@11012000 { - compatible = "mediatek,mt8183-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11012000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, - <&topckgen CLK_TOP_MUX_SPI>, - <&infracfg CLK_INFRA_SPI2>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - spi3: spi@11013000 { - compatible = "mediatek,mt8183-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11013000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, - <&topckgen CLK_TOP_MUX_SPI>, - <&infracfg CLK_INFRA_SPI3>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - i2c9: i2c@11014000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x11014000 0 0x1000>, - <0 0x11000180 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C1_IMM>, - <&infracfg CLK_INFRA_AP_DMA>, - <&infracfg CLK_INFRA_I2C1_ARBITER>; - clock-names = "main", "dma", "arb"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c10: i2c@11015000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x11015000 0 0x1000>, - <0 0x11000300 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C2_IMM>, - <&infracfg CLK_INFRA_AP_DMA>, - <&infracfg CLK_INFRA_I2C2_ARBITER>; - clock-names = "main", "dma", "arb"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@11016000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x11016000 0 0x1000>, - <0 0x11000500 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C5>, - <&infracfg CLK_INFRA_AP_DMA>, - <&infracfg CLK_INFRA_I2C5_ARBITER>; - clock-names = "main", "dma", "arb"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c11: i2c@11017000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x11017000 0 0x1000>, - <0 0x11000580 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C5_IMM>, - <&infracfg CLK_INFRA_AP_DMA>, - <&infracfg CLK_INFRA_I2C5_ARBITER>; - clock-names = "main", "dma", "arb"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@11018000 { - compatible = "mediatek,mt8183-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11018000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, - <&topckgen CLK_TOP_MUX_SPI>, - <&infracfg CLK_INFRA_SPI4>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - spi5: spi@11019000 { - compatible = "mediatek,mt8183-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11019000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, - <&topckgen CLK_TOP_MUX_SPI>, - <&infracfg CLK_INFRA_SPI5>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - i2c7: i2c@1101a000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x1101a000 0 0x1000>, - <0 0x11000680 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C7>, - <&infracfg CLK_INFRA_AP_DMA>; - clock-names = "main", "dma"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c8: i2c@1101b000 { - compatible = "mediatek,mt8183-i2c"; - reg = <0 0x1101b000 0 0x1000>, - <0 0x11000700 0 0x80>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_I2C8>, - <&infracfg CLK_INFRA_AP_DMA>; - clock-names = "main", "dma"; - clock-div = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ssusb: usb@11201000 { - compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3"; - reg = <0 0x11201000 0 0x2e00>, - <0 0x11203e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&u2port0 PHY_TYPE_USB2>, - <&u3port0 PHY_TYPE_USB3>; - clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, - <&infracfg CLK_INFRA_USB>; - clock-names = "sys_ck", "ref_ck"; - mediatek,syscon-wakeup = <&pericfg 0x400 0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - usb_host: xhci@11200000 { - compatible = "mediatek,mt8183-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11200000 0 0x1000>; - reg-names = "mac"; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, - <&infracfg CLK_INFRA_USB>; - clock-names = "sys_ck", "ref_ck"; - status = "disabled"; - }; - }; - - audiosys: syscon@11220000 { - compatible = "mediatek,mt8183-audiosys", "syscon"; - reg = <0 0x11220000 0 0x1000>; - #clock-cells = <1>; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt8183-mmc"; - reg = <0 0x11230000 0 0x1000>, - <0 0x11f50000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, - <&infracfg CLK_INFRA_MSDC0>, - <&infracfg CLK_INFRA_MSDC0_SCK>; - clock-names = "source", "hclk", "source_cg"; - status = "disabled"; - }; - - mmc1: mmc@11240000 { - compatible = "mediatek,mt8183-mmc"; - reg = <0 0x11240000 0 0x1000>, - <0 0x11e10000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, - <&infracfg CLK_INFRA_MSDC1>, - <&infracfg CLK_INFRA_MSDC1_SCK>; - clock-names = "source", "hclk", "source_cg"; - status = "disabled"; - }; - - efuse: efuse@11f10000 { - compatible = "mediatek,mt8183-efuse", - "mediatek,efuse"; - reg = <0 0x11f10000 0 0x1000>; - }; - - u3phy: usb-phy@11f40000 { - compatible = "mediatek,mt8183-tphy", - "mediatek,generic-tphy-v2"; - #address-cells = <1>; - #phy-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x11f40000 0x1000>; - status = "okay"; - - u2port0: usb-phy@0 { - reg = <0x0 0x700>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - mediatek,discth = <15>; - status = "okay"; - }; - - u3port0: usb-phy@0700 { - reg = <0x0700 0x900>; - clocks = <&clk26m>; - clock-names = "ref"; - #phy-cells = <1>; - status = "okay"; - }; - }; - - mfgcfg: syscon@13000000 { - compatible = "mediatek,mt8183-mfgcfg", "syscon"; - reg = <0 0x13000000 0 0x1000>; - #clock-cells = <1>; - }; - - mmsys: syscon@14000000 { - compatible = "mediatek,mt8183-mmsys", "syscon"; - reg = <0 0x14000000 0 0x1000>; - #clock-cells = <1>; - }; - - imgsys: syscon@15020000 { - compatible = "mediatek,mt8183-imgsys", "syscon"; - reg = <0 0x15020000 0 0x1000>; - #clock-cells = <1>; - }; - - vdecsys: syscon@16000000 { - compatible = "mediatek,mt8183-vdecsys", "syscon"; - reg = <0 0x16000000 0 0x1000>; - #clock-cells = <1>; - }; - - vencsys: syscon@17000000 { - compatible = "mediatek,mt8183-vencsys", "syscon"; - reg = <0 0x17000000 0 0x1000>; - #clock-cells = <1>; - }; - - ipu_conn: syscon@19000000 { - compatible = "mediatek,mt8183-ipu_conn", "syscon"; - reg = <0 0x19000000 0 0x1000>; - #clock-cells = <1>; - }; - - ipu_adl: syscon@19010000 { - compatible = "mediatek,mt8183-ipu_adl", "syscon"; - reg = <0 0x19010000 0 0x1000>; - #clock-cells = <1>; - }; - - ipu_core0: syscon@19180000 { - compatible = "mediatek,mt8183-ipu_core0", "syscon"; - reg = <0 0x19180000 0 0x1000>; - #clock-cells = <1>; - }; - - ipu_core1: syscon@19280000 { - compatible = "mediatek,mt8183-ipu_core1", "syscon"; - reg = <0 0x19280000 0 0x1000>; - #clock-cells = <1>; - }; - - camsys: syscon@1a000000 { - compatible = "mediatek,mt8183-camsys", "syscon"; - reg = <0 0x1a000000 0 0x1000>; - #clock-cells = <1>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt8516-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt8516-pinfunc.h deleted file mode 100644 index 73339bb48..000000000 --- a/arch/arm64/boot/dts/mediatek/mt8516-pinfunc.h +++ /dev/null @@ -1,663 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 MediaTek Inc. - */ -#ifndef __DTS_MT8516_PINFUNC_H -#define __DTS_MT8516_PINFUNC_H - -#include - -#define MT8516_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) -#define MT8516_PIN_0_EINT0__FUNC_PWM_B (MTK_PIN_NO(0) | 1) -#define MT8516_PIN_0_EINT0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3) -#define MT8516_PIN_0_EINT0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4) -#define MT8516_PIN_0_EINT0__FUNC_SQICS (MTK_PIN_NO(0) | 6) -#define MT8516_PIN_0_EINT0__FUNC_DBG_MON_A_6 (MTK_PIN_NO(0) | 7) - -#define MT8516_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) -#define MT8516_PIN_1_EINT1__FUNC_PWM_C (MTK_PIN_NO(1) | 1) -#define MT8516_PIN_1_EINT1__FUNC_I2S2_DI (MTK_PIN_NO(1) | 3) -#define MT8516_PIN_1_EINT1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4) -#define MT8516_PIN_1_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(1) | 5) -#define MT8516_PIN_1_EINT1__FUNC_SQISO (MTK_PIN_NO(1) | 6) -#define MT8516_PIN_1_EINT1__FUNC_DBG_MON_A_7 (MTK_PIN_NO(1) | 7) - -#define MT8516_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) -#define MT8516_PIN_2_EINT2__FUNC_CLKM0 (MTK_PIN_NO(2) | 1) -#define MT8516_PIN_2_EINT2__FUNC_I2S2_LRCK (MTK_PIN_NO(2) | 3) -#define MT8516_PIN_2_EINT2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4) -#define MT8516_PIN_2_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(2) | 5) -#define MT8516_PIN_2_EINT2__FUNC_SQISI (MTK_PIN_NO(2) | 6) -#define MT8516_PIN_2_EINT2__FUNC_DBG_MON_A_8 (MTK_PIN_NO(2) | 7) - -#define MT8516_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) -#define MT8516_PIN_3_EINT3__FUNC_CLKM1 (MTK_PIN_NO(3) | 1) -#define MT8516_PIN_3_EINT3__FUNC_SPI_MI (MTK_PIN_NO(3) | 3) -#define MT8516_PIN_3_EINT3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4) -#define MT8516_PIN_3_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(3) | 5) -#define MT8516_PIN_3_EINT3__FUNC_SQIWP (MTK_PIN_NO(3) | 6) -#define MT8516_PIN_3_EINT3__FUNC_DBG_MON_A_9 (MTK_PIN_NO(3) | 7) - -#define MT8516_PIN_4_EINT4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) -#define MT8516_PIN_4_EINT4__FUNC_CLKM2 (MTK_PIN_NO(4) | 1) -#define MT8516_PIN_4_EINT4__FUNC_SPI_MO (MTK_PIN_NO(4) | 3) -#define MT8516_PIN_4_EINT4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4) -#define MT8516_PIN_4_EINT4__FUNC_CONN_MCU_TCK (MTK_PIN_NO(4) | 5) -#define MT8516_PIN_4_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(4) | 6) -#define MT8516_PIN_4_EINT4__FUNC_DBG_MON_A_10 (MTK_PIN_NO(4) | 7) - -#define MT8516_PIN_5_EINT5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) -#define MT8516_PIN_5_EINT5__FUNC_UCTS2 (MTK_PIN_NO(5) | 1) -#define MT8516_PIN_5_EINT5__FUNC_SPI_CSB (MTK_PIN_NO(5) | 3) -#define MT8516_PIN_5_EINT5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4) -#define MT8516_PIN_5_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(5) | 5) -#define MT8516_PIN_5_EINT5__FUNC_CONN_TEST_CK (MTK_PIN_NO(5) | 6) -#define MT8516_PIN_5_EINT5__FUNC_DBG_MON_A_11 (MTK_PIN_NO(5) | 7) - -#define MT8516_PIN_6_EINT6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) -#define MT8516_PIN_6_EINT6__FUNC_URTS2 (MTK_PIN_NO(6) | 1) -#define MT8516_PIN_6_EINT6__FUNC_SPI_CLK (MTK_PIN_NO(6) | 3) -#define MT8516_PIN_6_EINT6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4) -#define MT8516_PIN_6_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(6) | 5) -#define MT8516_PIN_6_EINT6__FUNC_DBG_MON_A_12 (MTK_PIN_NO(6) | 7) - -#define MT8516_PIN_7_EINT7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) -#define MT8516_PIN_7_EINT7__FUNC_SQIRST (MTK_PIN_NO(7) | 1) -#define MT8516_PIN_7_EINT7__FUNC_SDA1_0 (MTK_PIN_NO(7) | 3) -#define MT8516_PIN_7_EINT7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4) -#define MT8516_PIN_7_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(7) | 5) -#define MT8516_PIN_7_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(7) | 6) -#define MT8516_PIN_7_EINT7__FUNC_DBG_MON_A_13 (MTK_PIN_NO(7) | 7) - -#define MT8516_PIN_8_EINT8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) -#define MT8516_PIN_8_EINT8__FUNC_SQICK (MTK_PIN_NO(8) | 1) -#define MT8516_PIN_8_EINT8__FUNC_CLKM3 (MTK_PIN_NO(8) | 2) -#define MT8516_PIN_8_EINT8__FUNC_SCL1_0 (MTK_PIN_NO(8) | 3) -#define MT8516_PIN_8_EINT8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4) -#define MT8516_PIN_8_EINT8__FUNC_ANT_SEL0 (MTK_PIN_NO(8) | 5) -#define MT8516_PIN_8_EINT8__FUNC_DBG_MON_A_14 (MTK_PIN_NO(8) | 7) - -#define MT8516_PIN_9_EINT9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) -#define MT8516_PIN_9_EINT9__FUNC_CLKM4 (MTK_PIN_NO(9) | 1) -#define MT8516_PIN_9_EINT9__FUNC_SDA2_0 (MTK_PIN_NO(9) | 2) -#define MT8516_PIN_9_EINT9__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3) -#define MT8516_PIN_9_EINT9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4) -#define MT8516_PIN_9_EINT9__FUNC_ANT_SEL1 (MTK_PIN_NO(9) | 5) -#define MT8516_PIN_9_EINT9__FUNC_DBG_MON_A_15 (MTK_PIN_NO(9) | 7) - -#define MT8516_PIN_10_EINT10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) -#define MT8516_PIN_10_EINT10__FUNC_CLKM5 (MTK_PIN_NO(10) | 1) -#define MT8516_PIN_10_EINT10__FUNC_SCL2_0 (MTK_PIN_NO(10) | 2) -#define MT8516_PIN_10_EINT10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 3) -#define MT8516_PIN_10_EINT10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4) -#define MT8516_PIN_10_EINT10__FUNC_ANT_SEL2 (MTK_PIN_NO(10) | 5) -#define MT8516_PIN_10_EINT10__FUNC_DBG_MON_A_16 (MTK_PIN_NO(10) | 7) - -#define MT8516_PIN_11_EINT11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) -#define MT8516_PIN_11_EINT11__FUNC_CLKM4 (MTK_PIN_NO(11) | 1) -#define MT8516_PIN_11_EINT11__FUNC_PWM_C (MTK_PIN_NO(11) | 2) -#define MT8516_PIN_11_EINT11__FUNC_CONN_TEST_CK (MTK_PIN_NO(11) | 3) -#define MT8516_PIN_11_EINT11__FUNC_ANT_SEL3 (MTK_PIN_NO(11) | 4) -#define MT8516_PIN_11_EINT11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 6) -#define MT8516_PIN_11_EINT11__FUNC_DBG_MON_A_17 (MTK_PIN_NO(11) | 7) - -#define MT8516_PIN_12_EINT12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) -#define MT8516_PIN_12_EINT12__FUNC_CLKM5 (MTK_PIN_NO(12) | 1) -#define MT8516_PIN_12_EINT12__FUNC_PWM_A (MTK_PIN_NO(12) | 2) -#define MT8516_PIN_12_EINT12__FUNC_SPDIF_OUT (MTK_PIN_NO(12) | 3) -#define MT8516_PIN_12_EINT12__FUNC_ANT_SEL4 (MTK_PIN_NO(12) | 4) -#define MT8516_PIN_12_EINT12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 6) -#define MT8516_PIN_12_EINT12__FUNC_DBG_MON_A_18 (MTK_PIN_NO(12) | 7) - -#define MT8516_PIN_13_EINT13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) -#define MT8516_PIN_13_EINT13__FUNC_TSF_IN (MTK_PIN_NO(13) | 3) -#define MT8516_PIN_13_EINT13__FUNC_ANT_SEL5 (MTK_PIN_NO(13) | 4) -#define MT8516_PIN_13_EINT13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 6) -#define MT8516_PIN_13_EINT13__FUNC_DBG_MON_A_19 (MTK_PIN_NO(13) | 7) - -#define MT8516_PIN_14_EINT14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) -#define MT8516_PIN_14_EINT14__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(14) | 2) -#define MT8516_PIN_14_EINT14__FUNC_TDM_RX_MCK (MTK_PIN_NO(14) | 3) -#define MT8516_PIN_14_EINT14__FUNC_ANT_SEL1 (MTK_PIN_NO(14) | 4) -#define MT8516_PIN_14_EINT14__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(14) | 5) -#define MT8516_PIN_14_EINT14__FUNC_NCLE (MTK_PIN_NO(14) | 6) -#define MT8516_PIN_14_EINT14__FUNC_DBG_MON_B_8 (MTK_PIN_NO(14) | 7) - -#define MT8516_PIN_15_EINT15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) -#define MT8516_PIN_15_EINT15__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(15) | 2) -#define MT8516_PIN_15_EINT15__FUNC_TDM_RX_BCK (MTK_PIN_NO(15) | 3) -#define MT8516_PIN_15_EINT15__FUNC_ANT_SEL2 (MTK_PIN_NO(15) | 4) -#define MT8516_PIN_15_EINT15__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(15) | 5) -#define MT8516_PIN_15_EINT15__FUNC_NCEB1 (MTK_PIN_NO(15) | 6) -#define MT8516_PIN_15_EINT15__FUNC_DBG_MON_B_9 (MTK_PIN_NO(15) | 7) - -#define MT8516_PIN_16_EINT16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) -#define MT8516_PIN_16_EINT16__FUNC_I2S_8CH_BCK (MTK_PIN_NO(16) | 2) -#define MT8516_PIN_16_EINT16__FUNC_TDM_RX_LRCK (MTK_PIN_NO(16) | 3) -#define MT8516_PIN_16_EINT16__FUNC_ANT_SEL3 (MTK_PIN_NO(16) | 4) -#define MT8516_PIN_16_EINT16__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(16) | 5) -#define MT8516_PIN_16_EINT16__FUNC_NCEB0 (MTK_PIN_NO(16) | 6) -#define MT8516_PIN_16_EINT16__FUNC_DBG_MON_B_10 (MTK_PIN_NO(16) | 7) - -#define MT8516_PIN_17_EINT17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) -#define MT8516_PIN_17_EINT17__FUNC_I2S_8CH_MCK (MTK_PIN_NO(17) | 2) -#define MT8516_PIN_17_EINT17__FUNC_TDM_RX_DI (MTK_PIN_NO(17) | 3) -#define MT8516_PIN_17_EINT17__FUNC_IDDIG (MTK_PIN_NO(17) | 4) -#define MT8516_PIN_17_EINT17__FUNC_ANT_SEL4 (MTK_PIN_NO(17) | 5) -#define MT8516_PIN_17_EINT17__FUNC_NREB (MTK_PIN_NO(17) | 6) -#define MT8516_PIN_17_EINT17__FUNC_DBG_MON_B_11 (MTK_PIN_NO(17) | 7) - -#define MT8516_PIN_18_EINT18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) -#define MT8516_PIN_18_EINT18__FUNC_USB_DRVVBUS (MTK_PIN_NO(18) | 2) -#define MT8516_PIN_18_EINT18__FUNC_I2S3_LRCK (MTK_PIN_NO(18) | 3) -#define MT8516_PIN_18_EINT18__FUNC_CLKM1 (MTK_PIN_NO(18) | 4) -#define MT8516_PIN_18_EINT18__FUNC_ANT_SEL3 (MTK_PIN_NO(18) | 5) -#define MT8516_PIN_18_EINT18__FUNC_I2S2_BCK (MTK_PIN_NO(18) | 6) -#define MT8516_PIN_18_EINT18__FUNC_DBG_MON_A_20 (MTK_PIN_NO(18) | 7) - -#define MT8516_PIN_19_EINT19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) -#define MT8516_PIN_19_EINT19__FUNC_UCTS1 (MTK_PIN_NO(19) | 1) -#define MT8516_PIN_19_EINT19__FUNC_IDDIG (MTK_PIN_NO(19) | 2) -#define MT8516_PIN_19_EINT19__FUNC_I2S3_BCK (MTK_PIN_NO(19) | 3) -#define MT8516_PIN_19_EINT19__FUNC_CLKM2 (MTK_PIN_NO(19) | 4) -#define MT8516_PIN_19_EINT19__FUNC_ANT_SEL4 (MTK_PIN_NO(19) | 5) -#define MT8516_PIN_19_EINT19__FUNC_I2S2_DI (MTK_PIN_NO(19) | 6) -#define MT8516_PIN_19_EINT19__FUNC_DBG_MON_A_21 (MTK_PIN_NO(19) | 7) - -#define MT8516_PIN_20_EINT20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) -#define MT8516_PIN_20_EINT20__FUNC_URTS1 (MTK_PIN_NO(20) | 1) -#define MT8516_PIN_20_EINT20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 3) -#define MT8516_PIN_20_EINT20__FUNC_CLKM3 (MTK_PIN_NO(20) | 4) -#define MT8516_PIN_20_EINT20__FUNC_ANT_SEL5 (MTK_PIN_NO(20) | 5) -#define MT8516_PIN_20_EINT20__FUNC_I2S2_LRCK (MTK_PIN_NO(20) | 6) -#define MT8516_PIN_20_EINT20__FUNC_DBG_MON_A_22 (MTK_PIN_NO(20) | 7) - -#define MT8516_PIN_21_EINT21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) -#define MT8516_PIN_21_EINT21__FUNC_NRNB (MTK_PIN_NO(21) | 1) -#define MT8516_PIN_21_EINT21__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 2) -#define MT8516_PIN_21_EINT21__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(21) | 3) -#define MT8516_PIN_21_EINT21__FUNC_DBG_MON_B_31 (MTK_PIN_NO(21) | 7) - -#define MT8516_PIN_22_EINT22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) -#define MT8516_PIN_22_EINT22__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(22) | 2) -#define MT8516_PIN_22_EINT22__FUNC_TSF_IN (MTK_PIN_NO(22) | 3) -#define MT8516_PIN_22_EINT22__FUNC_USB_DRVVBUS (MTK_PIN_NO(22) | 4) -#define MT8516_PIN_22_EINT22__FUNC_SPDIF_OUT (MTK_PIN_NO(22) | 5) -#define MT8516_PIN_22_EINT22__FUNC_NRE_C (MTK_PIN_NO(22) | 6) -#define MT8516_PIN_22_EINT22__FUNC_DBG_MON_B_12 (MTK_PIN_NO(22) | 7) - -#define MT8516_PIN_23_EINT23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) -#define MT8516_PIN_23_EINT23__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(23) | 2) -#define MT8516_PIN_23_EINT23__FUNC_CLKM0 (MTK_PIN_NO(23) | 3) -#define MT8516_PIN_23_EINT23__FUNC_IR (MTK_PIN_NO(23) | 4) -#define MT8516_PIN_23_EINT23__FUNC_SPDIF_IN (MTK_PIN_NO(23) | 5) -#define MT8516_PIN_23_EINT23__FUNC_NDQS_C (MTK_PIN_NO(23) | 6) -#define MT8516_PIN_23_EINT23__FUNC_DBG_MON_B_13 (MTK_PIN_NO(23) | 7) - -#define MT8516_PIN_24_EINT24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) -#define MT8516_PIN_24_EINT24__FUNC_ANT_SEL1 (MTK_PIN_NO(24) | 3) -#define MT8516_PIN_24_EINT24__FUNC_UCTS2 (MTK_PIN_NO(24) | 4) -#define MT8516_PIN_24_EINT24__FUNC_PWM_A (MTK_PIN_NO(24) | 5) -#define MT8516_PIN_24_EINT24__FUNC_I2S0_MCK (MTK_PIN_NO(24) | 6) -#define MT8516_PIN_24_EINT24__FUNC_DBG_MON_A_0 (MTK_PIN_NO(24) | 7) - -#define MT8516_PIN_25_EINT25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) -#define MT8516_PIN_25_EINT25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 3) -#define MT8516_PIN_25_EINT25__FUNC_URTS2 (MTK_PIN_NO(25) | 4) -#define MT8516_PIN_25_EINT25__FUNC_PWM_B (MTK_PIN_NO(25) | 5) -#define MT8516_PIN_25_EINT25__FUNC_I2S_8CH_MCK (MTK_PIN_NO(25) | 6) -#define MT8516_PIN_25_EINT25__FUNC_DBG_MON_A_1 (MTK_PIN_NO(25) | 7) - -#define MT8516_PIN_26_PWRAP_SPI0_MI__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) -#define MT8516_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(26) | 1) -#define MT8516_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(26) | 2) - -#define MT8516_PIN_27_PWRAP_SPI0_MO__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) -#define MT8516_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(27) | 1) -#define MT8516_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(27) | 2) - -#define MT8516_PIN_28_PWRAP_INT__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) -#define MT8516_PIN_28_PWRAP_INT__FUNC_I2S0_MCK (MTK_PIN_NO(28) | 1) -#define MT8516_PIN_28_PWRAP_INT__FUNC_I2S_8CH_MCK (MTK_PIN_NO(28) | 4) -#define MT8516_PIN_28_PWRAP_INT__FUNC_I2S2_MCK (MTK_PIN_NO(28) | 5) -#define MT8516_PIN_28_PWRAP_INT__FUNC_I2S3_MCK (MTK_PIN_NO(28) | 6) - -#define MT8516_PIN_29_PWRAP_SPI0_CK__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) -#define MT8516_PIN_29_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(29) | 1) - -#define MT8516_PIN_30_PWRAP_SPI0_CSN__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) -#define MT8516_PIN_30_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(30) | 1) - -#define MT8516_PIN_31_RTC32K_CK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) -#define MT8516_PIN_31_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(31) | 1) - -#define MT8516_PIN_32_WATCHDOG__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) -#define MT8516_PIN_32_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(32) | 1) - -#define MT8516_PIN_33_SRCLKENA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) -#define MT8516_PIN_33_SRCLKENA__FUNC_SRCLKENA0 (MTK_PIN_NO(33) | 1) - -#define MT8516_PIN_34_URXD2__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) -#define MT8516_PIN_34_URXD2__FUNC_URXD2 (MTK_PIN_NO(34) | 1) -#define MT8516_PIN_34_URXD2__FUNC_UTXD2 (MTK_PIN_NO(34) | 3) -#define MT8516_PIN_34_URXD2__FUNC_DBG_SCL (MTK_PIN_NO(34) | 4) -#define MT8516_PIN_34_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(34) | 6) -#define MT8516_PIN_34_URXD2__FUNC_DBG_MON_B_0 (MTK_PIN_NO(34) | 7) - -#define MT8516_PIN_35_UTXD2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) -#define MT8516_PIN_35_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(35) | 1) -#define MT8516_PIN_35_UTXD2__FUNC_URXD2 (MTK_PIN_NO(35) | 3) -#define MT8516_PIN_35_UTXD2__FUNC_DBG_SDA (MTK_PIN_NO(35) | 4) -#define MT8516_PIN_35_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(35) | 6) -#define MT8516_PIN_35_UTXD2__FUNC_DBG_MON_B_1 (MTK_PIN_NO(35) | 7) - -#define MT8516_PIN_36_MRG_CLK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) -#define MT8516_PIN_36_MRG_CLK__FUNC_MRG_CLK (MTK_PIN_NO(36) | 1) -#define MT8516_PIN_36_MRG_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(36) | 3) -#define MT8516_PIN_36_MRG_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(36) | 4) -#define MT8516_PIN_36_MRG_CLK__FUNC_PCM0_CLK (MTK_PIN_NO(36) | 5) -#define MT8516_PIN_36_MRG_CLK__FUNC_IR (MTK_PIN_NO(36) | 6) -#define MT8516_PIN_36_MRG_CLK__FUNC_DBG_MON_A_2 (MTK_PIN_NO(36) | 7) - -#define MT8516_PIN_37_MRG_SYNC__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) -#define MT8516_PIN_37_MRG_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(37) | 1) -#define MT8516_PIN_37_MRG_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(37) | 3) -#define MT8516_PIN_37_MRG_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(37) | 4) -#define MT8516_PIN_37_MRG_SYNC__FUNC_PCM0_SYNC (MTK_PIN_NO(37) | 5) -#define MT8516_PIN_37_MRG_SYNC__FUNC_EXT_COL (MTK_PIN_NO(37) | 6) -#define MT8516_PIN_37_MRG_SYNC__FUNC_DBG_MON_A_3 (MTK_PIN_NO(37) | 7) - -#define MT8516_PIN_38_MRG_DI__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) -#define MT8516_PIN_38_MRG_DI__FUNC_MRG_DI (MTK_PIN_NO(38) | 1) -#define MT8516_PIN_38_MRG_DI__FUNC_I2S0_DI (MTK_PIN_NO(38) | 3) -#define MT8516_PIN_38_MRG_DI__FUNC_I2S3_DO (MTK_PIN_NO(38) | 4) -#define MT8516_PIN_38_MRG_DI__FUNC_PCM0_DI (MTK_PIN_NO(38) | 5) -#define MT8516_PIN_38_MRG_DI__FUNC_EXT_MDIO (MTK_PIN_NO(38) | 6) -#define MT8516_PIN_38_MRG_DI__FUNC_DBG_MON_A_4 (MTK_PIN_NO(38) | 7) - -#define MT8516_PIN_39_MRG_DO__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) -#define MT8516_PIN_39_MRG_DO__FUNC_MRG_DO (MTK_PIN_NO(39) | 1) -#define MT8516_PIN_39_MRG_DO__FUNC_I2S0_MCK (MTK_PIN_NO(39) | 3) -#define MT8516_PIN_39_MRG_DO__FUNC_I2S3_MCK (MTK_PIN_NO(39) | 4) -#define MT8516_PIN_39_MRG_DO__FUNC_PCM0_DO (MTK_PIN_NO(39) | 5) -#define MT8516_PIN_39_MRG_DO__FUNC_EXT_MDC (MTK_PIN_NO(39) | 6) -#define MT8516_PIN_39_MRG_DO__FUNC_DBG_MON_A_5 (MTK_PIN_NO(39) | 7) - -#define MT8516_PIN_40_KPROW0__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) -#define MT8516_PIN_40_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(40) | 1) -#define MT8516_PIN_40_KPROW0__FUNC_DBG_MON_B_4 (MTK_PIN_NO(40) | 7) - -#define MT8516_PIN_41_KPROW1__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) -#define MT8516_PIN_41_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(41) | 1) -#define MT8516_PIN_41_KPROW1__FUNC_IDDIG (MTK_PIN_NO(41) | 2) -#define MT8516_PIN_41_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 3) -#define MT8516_PIN_41_KPROW1__FUNC_DBG_MON_B_5 (MTK_PIN_NO(41) | 7) - -#define MT8516_PIN_42_KPCOL0__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) -#define MT8516_PIN_42_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(42) | 1) -#define MT8516_PIN_42_KPCOL0__FUNC_DBG_MON_B_6 (MTK_PIN_NO(42) | 7) - -#define MT8516_PIN_43_KPCOL1__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) -#define MT8516_PIN_43_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(43) | 1) -#define MT8516_PIN_43_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(43) | 2) -#define MT8516_PIN_43_KPCOL1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(43) | 3) -#define MT8516_PIN_43_KPCOL1__FUNC_TSF_IN (MTK_PIN_NO(43) | 4) -#define MT8516_PIN_43_KPCOL1__FUNC_DBG_MON_B_7 (MTK_PIN_NO(43) | 7) - -#define MT8516_PIN_44_JTMS__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) -#define MT8516_PIN_44_JTMS__FUNC_JTMS (MTK_PIN_NO(44) | 1) -#define MT8516_PIN_44_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(44) | 2) -#define MT8516_PIN_44_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(44) | 3) -#define MT8516_PIN_44_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(44) | 5) -#define MT8516_PIN_44_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(44) | 6) - -#define MT8516_PIN_45_JTCK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) -#define MT8516_PIN_45_JTCK__FUNC_JTCK (MTK_PIN_NO(45) | 1) -#define MT8516_PIN_45_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(45) | 2) -#define MT8516_PIN_45_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(45) | 3) - -#define MT8516_PIN_46_JTDI__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) -#define MT8516_PIN_46_JTDI__FUNC_JTDI (MTK_PIN_NO(46) | 1) -#define MT8516_PIN_46_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(46) | 2) - -#define MT8516_PIN_47_JTDO__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) -#define MT8516_PIN_47_JTDO__FUNC_JTDO (MTK_PIN_NO(47) | 1) -#define MT8516_PIN_47_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(47) | 2) - -#define MT8516_PIN_48_SPI_CS__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) -#define MT8516_PIN_48_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(48) | 1) -#define MT8516_PIN_48_SPI_CS__FUNC_I2S0_DI (MTK_PIN_NO(48) | 3) -#define MT8516_PIN_48_SPI_CS__FUNC_I2S2_BCK (MTK_PIN_NO(48) | 4) -#define MT8516_PIN_48_SPI_CS__FUNC_DBG_MON_A_23 (MTK_PIN_NO(48) | 7) - -#define MT8516_PIN_49_SPI_CK__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) -#define MT8516_PIN_49_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(49) | 1) -#define MT8516_PIN_49_SPI_CK__FUNC_I2S0_LRCK (MTK_PIN_NO(49) | 3) -#define MT8516_PIN_49_SPI_CK__FUNC_I2S2_DI (MTK_PIN_NO(49) | 4) -#define MT8516_PIN_49_SPI_CK__FUNC_DBG_MON_A_24 (MTK_PIN_NO(49) | 7) - -#define MT8516_PIN_50_SPI_MI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) -#define MT8516_PIN_50_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(50) | 1) -#define MT8516_PIN_50_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(50) | 2) -#define MT8516_PIN_50_SPI_MI__FUNC_I2S0_BCK (MTK_PIN_NO(50) | 3) -#define MT8516_PIN_50_SPI_MI__FUNC_I2S2_LRCK (MTK_PIN_NO(50) | 4) -#define MT8516_PIN_50_SPI_MI__FUNC_DBG_MON_A_25 (MTK_PIN_NO(50) | 7) - -#define MT8516_PIN_51_SPI_MO__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) -#define MT8516_PIN_51_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(51) | 1) -#define MT8516_PIN_51_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(51) | 2) -#define MT8516_PIN_51_SPI_MO__FUNC_I2S0_MCK (MTK_PIN_NO(51) | 3) -#define MT8516_PIN_51_SPI_MO__FUNC_I2S2_MCK (MTK_PIN_NO(51) | 4) -#define MT8516_PIN_51_SPI_MO__FUNC_DBG_MON_A_26 (MTK_PIN_NO(51) | 7) - -#define MT8516_PIN_52_SDA1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) -#define MT8516_PIN_52_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(52) | 1) - -#define MT8516_PIN_53_SCL1__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) -#define MT8516_PIN_53_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(53) | 1) - -#define MT8516_PIN_54_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) -#define MT8516_PIN_54_GPIO54__FUNC_PWM_B (MTK_PIN_NO(54) | 2) -#define MT8516_PIN_54_GPIO54__FUNC_DBG_MON_B_2 (MTK_PIN_NO(54) | 7) - -#define MT8516_PIN_55_I2S_DATA_IN__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) -#define MT8516_PIN_55_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(55) | 1) -#define MT8516_PIN_55_I2S_DATA_IN__FUNC_UCTS0 (MTK_PIN_NO(55) | 2) -#define MT8516_PIN_55_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(55) | 3) -#define MT8516_PIN_55_I2S_DATA_IN__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(55) | 4) -#define MT8516_PIN_55_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(55) | 5) -#define MT8516_PIN_55_I2S_DATA_IN__FUNC_I2S2_BCK (MTK_PIN_NO(55) | 6) -#define MT8516_PIN_55_I2S_DATA_IN__FUNC_DBG_MON_A_28 (MTK_PIN_NO(55) | 7) - -#define MT8516_PIN_56_I2S_LRCK__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) -#define MT8516_PIN_56_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(56) | 1) -#define MT8516_PIN_56_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(56) | 3) -#define MT8516_PIN_56_I2S_LRCK__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(56) | 4) -#define MT8516_PIN_56_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(56) | 5) -#define MT8516_PIN_56_I2S_LRCK__FUNC_I2S2_DI (MTK_PIN_NO(56) | 6) -#define MT8516_PIN_56_I2S_LRCK__FUNC_DBG_MON_A_29 (MTK_PIN_NO(56) | 7) - -#define MT8516_PIN_57_I2S_BCK__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) -#define MT8516_PIN_57_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(57) | 1) -#define MT8516_PIN_57_I2S_BCK__FUNC_URTS0 (MTK_PIN_NO(57) | 2) -#define MT8516_PIN_57_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(57) | 3) -#define MT8516_PIN_57_I2S_BCK__FUNC_I2S_8CH_BCK (MTK_PIN_NO(57) | 4) -#define MT8516_PIN_57_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(57) | 5) -#define MT8516_PIN_57_I2S_BCK__FUNC_I2S2_LRCK (MTK_PIN_NO(57) | 6) -#define MT8516_PIN_57_I2S_BCK__FUNC_DBG_MON_A_30 (MTK_PIN_NO(57) | 7) - -#define MT8516_PIN_58_SDA0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) -#define MT8516_PIN_58_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(58) | 1) - -#define MT8516_PIN_59_SCL0__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) -#define MT8516_PIN_59_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(59) | 1) - -#define MT8516_PIN_60_SDA2__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) -#define MT8516_PIN_60_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(60) | 1) -#define MT8516_PIN_60_SDA2__FUNC_PWM_B (MTK_PIN_NO(60) | 2) - -#define MT8516_PIN_61_SCL2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) -#define MT8516_PIN_61_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(61) | 1) -#define MT8516_PIN_61_SCL2__FUNC_PWM_C (MTK_PIN_NO(61) | 2) - -#define MT8516_PIN_62_URXD0__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) -#define MT8516_PIN_62_URXD0__FUNC_URXD0 (MTK_PIN_NO(62) | 1) -#define MT8516_PIN_62_URXD0__FUNC_UTXD0 (MTK_PIN_NO(62) | 2) - -#define MT8516_PIN_63_UTXD0__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) -#define MT8516_PIN_63_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(63) | 1) -#define MT8516_PIN_63_UTXD0__FUNC_URXD0 (MTK_PIN_NO(63) | 2) - -#define MT8516_PIN_64_URXD1__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) -#define MT8516_PIN_64_URXD1__FUNC_URXD1 (MTK_PIN_NO(64) | 1) -#define MT8516_PIN_64_URXD1__FUNC_UTXD1 (MTK_PIN_NO(64) | 2) -#define MT8516_PIN_64_URXD1__FUNC_DBG_MON_A_27 (MTK_PIN_NO(64) | 7) - -#define MT8516_PIN_65_UTXD1__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) -#define MT8516_PIN_65_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(65) | 1) -#define MT8516_PIN_65_UTXD1__FUNC_URXD1 (MTK_PIN_NO(65) | 2) -#define MT8516_PIN_65_UTXD1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(65) | 7) - -#define MT8516_PIN_68_MSDC2_CMD__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) -#define MT8516_PIN_68_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(68) | 1) -#define MT8516_PIN_68_MSDC2_CMD__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(68) | 2) -#define MT8516_PIN_68_MSDC2_CMD__FUNC_SDA1_0 (MTK_PIN_NO(68) | 3) -#define MT8516_PIN_68_MSDC2_CMD__FUNC_USB_SDA (MTK_PIN_NO(68) | 5) -#define MT8516_PIN_68_MSDC2_CMD__FUNC_I2S3_BCK (MTK_PIN_NO(68) | 6) -#define MT8516_PIN_68_MSDC2_CMD__FUNC_DBG_MON_B_15 (MTK_PIN_NO(68) | 7) - -#define MT8516_PIN_69_MSDC2_CLK__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) -#define MT8516_PIN_69_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(69) | 1) -#define MT8516_PIN_69_MSDC2_CLK__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(69) | 2) -#define MT8516_PIN_69_MSDC2_CLK__FUNC_SCL1_0 (MTK_PIN_NO(69) | 3) -#define MT8516_PIN_69_MSDC2_CLK__FUNC_USB_SCL (MTK_PIN_NO(69) | 5) -#define MT8516_PIN_69_MSDC2_CLK__FUNC_I2S3_LRCK (MTK_PIN_NO(69) | 6) -#define MT8516_PIN_69_MSDC2_CLK__FUNC_DBG_MON_B_16 (MTK_PIN_NO(69) | 7) - -#define MT8516_PIN_70_MSDC2_DAT0__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) -#define MT8516_PIN_70_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(70) | 1) -#define MT8516_PIN_70_MSDC2_DAT0__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(70) | 2) -#define MT8516_PIN_70_MSDC2_DAT0__FUNC_UTXD0 (MTK_PIN_NO(70) | 5) -#define MT8516_PIN_70_MSDC2_DAT0__FUNC_I2S3_DO (MTK_PIN_NO(70) | 6) -#define MT8516_PIN_70_MSDC2_DAT0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(70) | 7) - -#define MT8516_PIN_71_MSDC2_DAT1__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) -#define MT8516_PIN_71_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(71) | 1) -#define MT8516_PIN_71_MSDC2_DAT1__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(71) | 2) -#define MT8516_PIN_71_MSDC2_DAT1__FUNC_PWM_A (MTK_PIN_NO(71) | 3) -#define MT8516_PIN_71_MSDC2_DAT1__FUNC_I2S3_MCK (MTK_PIN_NO(71) | 4) -#define MT8516_PIN_71_MSDC2_DAT1__FUNC_URXD0 (MTK_PIN_NO(71) | 5) -#define MT8516_PIN_71_MSDC2_DAT1__FUNC_PWM_B (MTK_PIN_NO(71) | 6) -#define MT8516_PIN_71_MSDC2_DAT1__FUNC_DBG_MON_B_18 (MTK_PIN_NO(71) | 7) - -#define MT8516_PIN_72_MSDC2_DAT2__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) -#define MT8516_PIN_72_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(72) | 1) -#define MT8516_PIN_72_MSDC2_DAT2__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(72) | 2) -#define MT8516_PIN_72_MSDC2_DAT2__FUNC_SDA2_0 (MTK_PIN_NO(72) | 3) -#define MT8516_PIN_72_MSDC2_DAT2__FUNC_UTXD1 (MTK_PIN_NO(72) | 5) -#define MT8516_PIN_72_MSDC2_DAT2__FUNC_PWM_C (MTK_PIN_NO(72) | 6) -#define MT8516_PIN_72_MSDC2_DAT2__FUNC_DBG_MON_B_19 (MTK_PIN_NO(72) | 7) - -#define MT8516_PIN_73_MSDC2_DAT3__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) -#define MT8516_PIN_73_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(73) | 1) -#define MT8516_PIN_73_MSDC2_DAT3__FUNC_I2S_8CH_BCK (MTK_PIN_NO(73) | 2) -#define MT8516_PIN_73_MSDC2_DAT3__FUNC_SCL2_0 (MTK_PIN_NO(73) | 3) -#define MT8516_PIN_73_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(73) | 4) -#define MT8516_PIN_73_MSDC2_DAT3__FUNC_URXD1 (MTK_PIN_NO(73) | 5) -#define MT8516_PIN_73_MSDC2_DAT3__FUNC_PWM_A (MTK_PIN_NO(73) | 6) -#define MT8516_PIN_73_MSDC2_DAT3__FUNC_DBG_MON_B_20 (MTK_PIN_NO(73) | 7) - -#define MT8516_PIN_74_TDN3__FUNC_GPI74 (MTK_PIN_NO(74) | 0) -#define MT8516_PIN_74_TDN3__FUNC_TDN3 (MTK_PIN_NO(74) | 1) - -#define MT8516_PIN_75_TDP3__FUNC_GPI75 (MTK_PIN_NO(75) | 0) -#define MT8516_PIN_75_TDP3__FUNC_TDP3 (MTK_PIN_NO(75) | 1) - -#define MT8516_PIN_76_TDN2__FUNC_GPI76 (MTK_PIN_NO(76) | 0) -#define MT8516_PIN_76_TDN2__FUNC_TDN2 (MTK_PIN_NO(76) | 1) - -#define MT8516_PIN_77_TDP2__FUNC_GPI77 (MTK_PIN_NO(77) | 0) -#define MT8516_PIN_77_TDP2__FUNC_TDP2 (MTK_PIN_NO(77) | 1) - -#define MT8516_PIN_78_TCN__FUNC_GPI78 (MTK_PIN_NO(78) | 0) -#define MT8516_PIN_78_TCN__FUNC_TCN (MTK_PIN_NO(78) | 1) - -#define MT8516_PIN_79_TCP__FUNC_GPI79 (MTK_PIN_NO(79) | 0) -#define MT8516_PIN_79_TCP__FUNC_TCP (MTK_PIN_NO(79) | 1) - -#define MT8516_PIN_80_TDN1__FUNC_GPI80 (MTK_PIN_NO(80) | 0) -#define MT8516_PIN_80_TDN1__FUNC_TDN1 (MTK_PIN_NO(80) | 1) - -#define MT8516_PIN_81_TDP1__FUNC_GPI81 (MTK_PIN_NO(81) | 0) -#define MT8516_PIN_81_TDP1__FUNC_TDP1 (MTK_PIN_NO(81) | 1) - -#define MT8516_PIN_82_TDN0__FUNC_GPI82 (MTK_PIN_NO(82) | 0) -#define MT8516_PIN_82_TDN0__FUNC_TDN0 (MTK_PIN_NO(82) | 1) - -#define MT8516_PIN_83_TDP0__FUNC_GPI83 (MTK_PIN_NO(83) | 0) -#define MT8516_PIN_83_TDP0__FUNC_TDP0 (MTK_PIN_NO(83) | 1) - -#define MT8516_PIN_84_RDN0__FUNC_GPI84 (MTK_PIN_NO(84) | 0) -#define MT8516_PIN_84_RDN0__FUNC_RDN0 (MTK_PIN_NO(84) | 1) - -#define MT8516_PIN_85_RDP0__FUNC_GPI85 (MTK_PIN_NO(85) | 0) -#define MT8516_PIN_85_RDP0__FUNC_RDP0 (MTK_PIN_NO(85) | 1) - -#define MT8516_PIN_86_RDN1__FUNC_GPI86 (MTK_PIN_NO(86) | 0) -#define MT8516_PIN_86_RDN1__FUNC_RDN1 (MTK_PIN_NO(86) | 1) - -#define MT8516_PIN_87_RDP1__FUNC_GPI87 (MTK_PIN_NO(87) | 0) -#define MT8516_PIN_87_RDP1__FUNC_RDP1 (MTK_PIN_NO(87) | 1) - -#define MT8516_PIN_88_RCN__FUNC_GPI88 (MTK_PIN_NO(88) | 0) -#define MT8516_PIN_88_RCN__FUNC_RCN (MTK_PIN_NO(88) | 1) - -#define MT8516_PIN_89_RCP__FUNC_GPI89 (MTK_PIN_NO(89) | 0) -#define MT8516_PIN_89_RCP__FUNC_RCP (MTK_PIN_NO(89) | 1) - -#define MT8516_PIN_90_RDN2__FUNC_GPI90 (MTK_PIN_NO(90) | 0) -#define MT8516_PIN_90_RDN2__FUNC_RDN2 (MTK_PIN_NO(90) | 1) -#define MT8516_PIN_90_RDN2__FUNC_CMDAT8 (MTK_PIN_NO(90) | 2) - -#define MT8516_PIN_91_RDP2__FUNC_GPI91 (MTK_PIN_NO(91) | 0) -#define MT8516_PIN_91_RDP2__FUNC_RDP2 (MTK_PIN_NO(91) | 1) -#define MT8516_PIN_91_RDP2__FUNC_CMDAT9 (MTK_PIN_NO(91) | 2) - -#define MT8516_PIN_92_RDN3__FUNC_GPI92 (MTK_PIN_NO(92) | 0) -#define MT8516_PIN_92_RDN3__FUNC_RDN3 (MTK_PIN_NO(92) | 1) -#define MT8516_PIN_92_RDN3__FUNC_CMDAT4 (MTK_PIN_NO(92) | 2) - -#define MT8516_PIN_93_RDP3__FUNC_GPI93 (MTK_PIN_NO(93) | 0) -#define MT8516_PIN_93_RDP3__FUNC_RDP3 (MTK_PIN_NO(93) | 1) -#define MT8516_PIN_93_RDP3__FUNC_CMDAT5 (MTK_PIN_NO(93) | 2) - -#define MT8516_PIN_94_RCN_A__FUNC_GPI94 (MTK_PIN_NO(94) | 0) -#define MT8516_PIN_94_RCN_A__FUNC_RCN_A (MTK_PIN_NO(94) | 1) -#define MT8516_PIN_94_RCN_A__FUNC_CMDAT6 (MTK_PIN_NO(94) | 2) - -#define MT8516_PIN_95_RCP_A__FUNC_GPI95 (MTK_PIN_NO(95) | 0) -#define MT8516_PIN_95_RCP_A__FUNC_RCP_A (MTK_PIN_NO(95) | 1) -#define MT8516_PIN_95_RCP_A__FUNC_CMDAT7 (MTK_PIN_NO(95) | 2) - -#define MT8516_PIN_96_RDN1_A__FUNC_GPI96 (MTK_PIN_NO(96) | 0) -#define MT8516_PIN_96_RDN1_A__FUNC_RDN1_A (MTK_PIN_NO(96) | 1) -#define MT8516_PIN_96_RDN1_A__FUNC_CMDAT2 (MTK_PIN_NO(96) | 2) -#define MT8516_PIN_96_RDN1_A__FUNC_CMCSD2 (MTK_PIN_NO(96) | 3) - -#define MT8516_PIN_97_RDP1_A__FUNC_GPI97 (MTK_PIN_NO(97) | 0) -#define MT8516_PIN_97_RDP1_A__FUNC_RDP1_A (MTK_PIN_NO(97) | 1) -#define MT8516_PIN_97_RDP1_A__FUNC_CMDAT3 (MTK_PIN_NO(97) | 2) -#define MT8516_PIN_97_RDP1_A__FUNC_CMCSD3 (MTK_PIN_NO(97) | 3) - -#define MT8516_PIN_98_RDN0_A__FUNC_GPI98 (MTK_PIN_NO(98) | 0) -#define MT8516_PIN_98_RDN0_A__FUNC_RDN0_A (MTK_PIN_NO(98) | 1) -#define MT8516_PIN_98_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(98) | 2) - -#define MT8516_PIN_99_RDP0_A__FUNC_GPI99 (MTK_PIN_NO(99) | 0) -#define MT8516_PIN_99_RDP0_A__FUNC_RDP0_A (MTK_PIN_NO(99) | 1) -#define MT8516_PIN_99_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(99) | 2) - -#define MT8516_PIN_100_CMDAT0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) -#define MT8516_PIN_100_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(100) | 1) -#define MT8516_PIN_100_CMDAT0__FUNC_CMCSD0 (MTK_PIN_NO(100) | 2) -#define MT8516_PIN_100_CMDAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(100) | 3) -#define MT8516_PIN_100_CMDAT0__FUNC_TDM_RX_MCK (MTK_PIN_NO(100) | 5) -#define MT8516_PIN_100_CMDAT0__FUNC_DBG_MON_B_21 (MTK_PIN_NO(100) | 7) - -#define MT8516_PIN_101_CMDAT1__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) -#define MT8516_PIN_101_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(101) | 1) -#define MT8516_PIN_101_CMDAT1__FUNC_CMCSD1 (MTK_PIN_NO(101) | 2) -#define MT8516_PIN_101_CMDAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(101) | 3) -#define MT8516_PIN_101_CMDAT1__FUNC_CMFLASH (MTK_PIN_NO(101) | 4) -#define MT8516_PIN_101_CMDAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(101) | 5) -#define MT8516_PIN_101_CMDAT1__FUNC_DBG_MON_B_22 (MTK_PIN_NO(101) | 7) - -#define MT8516_PIN_102_CMMCLK__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) -#define MT8516_PIN_102_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(102) | 1) -#define MT8516_PIN_102_CMMCLK__FUNC_ANT_SEL4 (MTK_PIN_NO(102) | 3) -#define MT8516_PIN_102_CMMCLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(102) | 5) -#define MT8516_PIN_102_CMMCLK__FUNC_DBG_MON_B_23 (MTK_PIN_NO(102) | 7) - -#define MT8516_PIN_103_CMPCLK__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) -#define MT8516_PIN_103_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(103) | 1) -#define MT8516_PIN_103_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(103) | 2) -#define MT8516_PIN_103_CMPCLK__FUNC_ANT_SEL5 (MTK_PIN_NO(103) | 3) -#define MT8516_PIN_103_CMPCLK__FUNC_TDM_RX_DI (MTK_PIN_NO(103) | 5) -#define MT8516_PIN_103_CMPCLK__FUNC_DBG_MON_B_24 (MTK_PIN_NO(103) | 7) - -#define MT8516_PIN_104_MSDC1_CMD__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) -#define MT8516_PIN_104_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(104) | 1) -#define MT8516_PIN_104_MSDC1_CMD__FUNC_SQICS (MTK_PIN_NO(104) | 4) -#define MT8516_PIN_104_MSDC1_CMD__FUNC_DBG_MON_B_25 (MTK_PIN_NO(104) | 7) - -#define MT8516_PIN_105_MSDC1_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) -#define MT8516_PIN_105_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(105) | 1) -#define MT8516_PIN_105_MSDC1_CLK__FUNC_SQISO (MTK_PIN_NO(105) | 4) -#define MT8516_PIN_105_MSDC1_CLK__FUNC_DBG_MON_B_26 (MTK_PIN_NO(105) | 7) - -#define MT8516_PIN_106_MSDC1_DAT0__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) -#define MT8516_PIN_106_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(106) | 1) -#define MT8516_PIN_106_MSDC1_DAT0__FUNC_SQISI (MTK_PIN_NO(106) | 4) -#define MT8516_PIN_106_MSDC1_DAT0__FUNC_DBG_MON_B_27 (MTK_PIN_NO(106) | 7) - -#define MT8516_PIN_107_MSDC1_DAT1__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) -#define MT8516_PIN_107_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(107) | 1) -#define MT8516_PIN_107_MSDC1_DAT1__FUNC_SQIWP (MTK_PIN_NO(107) | 4) -#define MT8516_PIN_107_MSDC1_DAT1__FUNC_DBG_MON_B_28 (MTK_PIN_NO(107) | 7) - -#define MT8516_PIN_108_MSDC1_DAT2__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) -#define MT8516_PIN_108_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(108) | 1) -#define MT8516_PIN_108_MSDC1_DAT2__FUNC_SQIRST (MTK_PIN_NO(108) | 4) -#define MT8516_PIN_108_MSDC1_DAT2__FUNC_DBG_MON_B_29 (MTK_PIN_NO(108) | 7) - -#define MT8516_PIN_109_MSDC1_DAT3__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) -#define MT8516_PIN_109_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(109) | 1) -#define MT8516_PIN_109_MSDC1_DAT3__FUNC_SQICK (MTK_PIN_NO(109) | 4) -#define MT8516_PIN_109_MSDC1_DAT3__FUNC_DBG_MON_B_30 (MTK_PIN_NO(109) | 7) - -#define MT8516_PIN_110_MSDC0_DAT7__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) -#define MT8516_PIN_110_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(110) | 1) -#define MT8516_PIN_110_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(110) | 4) - -#define MT8516_PIN_111_MSDC0_DAT6__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) -#define MT8516_PIN_111_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(111) | 1) -#define MT8516_PIN_111_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(111) | 4) - -#define MT8516_PIN_112_MSDC0_DAT5__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) -#define MT8516_PIN_112_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(112) | 1) -#define MT8516_PIN_112_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(112) | 4) - -#define MT8516_PIN_113_MSDC0_DAT4__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) -#define MT8516_PIN_113_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(113) | 1) -#define MT8516_PIN_113_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(113) | 4) - -#define MT8516_PIN_114_MSDC0_RSTB__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) -#define MT8516_PIN_114_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(114) | 1) -#define MT8516_PIN_114_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(114) | 4) - -#define MT8516_PIN_115_MSDC0_CMD__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) -#define MT8516_PIN_115_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(115) | 1) -#define MT8516_PIN_115_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(115) | 4) - -#define MT8516_PIN_116_MSDC0_CLK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) -#define MT8516_PIN_116_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(116) | 1) -#define MT8516_PIN_116_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(116) | 4) - -#define MT8516_PIN_117_MSDC0_DAT3__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) -#define MT8516_PIN_117_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(117) | 1) -#define MT8516_PIN_117_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(117) | 4) - -#define MT8516_PIN_118_MSDC0_DAT2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) -#define MT8516_PIN_118_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(118) | 1) -#define MT8516_PIN_118_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(118) | 4) - -#define MT8516_PIN_119_MSDC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) -#define MT8516_PIN_119_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(119) | 1) -#define MT8516_PIN_119_MSDC0_DAT1__FUNC_NLD8 (MTK_PIN_NO(119) | 4) - -#define MT8516_PIN_120_MSDC0_DAT0__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) -#define MT8516_PIN_120_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(120) | 1) -#define MT8516_PIN_120_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(120) | 4) -#define MT8516_PIN_120_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(120) | 5) - -#endif /* __DTS_MT8516_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts deleted file mode 100644 index cce642c53..000000000 --- a/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 BayLibre, SAS. - * Author: Fabien Parent - */ - -/dts-v1/; - -#include "mt8516.dtsi" -#include "pumpkin-common.dtsi" - -/ { - model = "Pumpkin MT8516"; - compatible = "mediatek,mt8516"; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi deleted file mode 100644 index 89af661e7..000000000 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ /dev/null @@ -1,474 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 MediaTek Inc. - * Copyright (c) 2019 BayLibre, SAS. - * Author: Fabien Parent - */ - -#include -#include -#include -#include - -#include "mt8516-pinfunc.h" - -/ { - compatible = "mediatek,mt8516"; - interrupt-parent = <&sysirq>; - #address-cells = <2>; - #size-cells = <2>; - - cluster0_opp: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - opp-598000000 { - opp-hz = /bits/ 64 <598000000>; - opp-microvolt = <1150000>; - }; - opp-747500000 { - opp-hz = /bits/ 64 <747500000>; - opp-microvolt = <1150000>; - }; - opp-1040000000 { - opp-hz = /bits/ 64 <1040000000>; - opp-microvolt = <1200000>; - }; - opp-1196000000 { - opp-hz = /bits/ 64 <1196000000>; - opp-microvolt = <1250000>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1300000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0>; - enable-method = "psci"; - cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, - <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; - clocks = <&infracfg CLK_IFR_MUX1_SEL>, - <&topckgen CLK_TOP_MAINPLL_D2>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x1>; - enable-method = "psci"; - cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, - <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; - clocks = <&infracfg CLK_IFR_MUX1_SEL>, - <&topckgen CLK_TOP_MAINPLL_D2>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x2>; - enable-method = "psci"; - cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, - <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; - clocks = <&infracfg CLK_IFR_MUX1_SEL>, - <&topckgen CLK_TOP_MAINPLL_D2>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x3>; - enable-method = "psci"; - cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, - <&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; - clocks = <&infracfg CLK_IFR_MUX1_SEL>, - <&topckgen CLK_TOP_MAINPLL_D2>; - clock-names = "cpu", "intermediate", "armpll"; - operating-points-v2 = <&cluster0_opp>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - entry-latency-us = <600>; - exit-latency-us = <600>; - min-residency-us = <1200>; - arm,psci-suspend-param = <0x0010000>; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - entry-latency-us = <800>; - exit-latency-us = <1000>; - min-residency-us = <2000>; - arm,psci-suspend-param = <0x2010000>; - }; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - clk26m: clk26m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "clk26m"; - }; - - clk32k: clk32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - clock-output-names = "clk32k"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ - bl31_secmon_reserved: secmon@43000000 { - no-map; - reg = <0 0x43000000 0 0x20000>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - topckgen: topckgen@10000000 { - compatible = "mediatek,mt8516-topckgen", "syscon"; - reg = <0 0x10000000 0 0x1000>; - #clock-cells = <1>; - }; - - infracfg: infracfg@10001000 { - compatible = "mediatek,mt8516-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - }; - - pericfg: pericfg@10003050 { - compatible = "mediatek,mt8516-pericfg", "syscon"; - reg = <0 0x10003050 0 0x1000>; - }; - - apmixedsys: apmixedsys@10018000 { - compatible = "mediatek,mt8516-apmixedsys", "syscon"; - reg = <0 0x10018000 0 0x710>; - #clock-cells = <1>; - }; - - toprgu: toprgu@10007000 { - compatible = "mediatek,mt8516-wdt", - "mediatek,mt6589-wdt"; - reg = <0 0x10007000 0 0x1000>; - interrupts = ; - #reset-cells = <1>; - }; - - timer: timer@10008000 { - compatible = "mediatek,mt8516-timer", - "mediatek,mt6577-timer"; - reg = <0 0x10008000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_CLK26M_D2>, - <&topckgen CLK_TOP_APXGPT>; - clock-names = "clk13m", "bus"; - }; - - syscfg_pctl: syscfg-pctl@10005000 { - compatible = "syscon"; - reg = <0 0x10005000 0 0x1000>; - }; - - pio: pinctrl@1000b000 { - compatible = "mediatek,mt8516-pinctrl"; - reg = <0 0x1000b000 0 0x1000>; - mediatek,pctl-regmap = <&syscfg_pctl>; - pins-are-numbered; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - pwrap: pwrap@1000f000 { - compatible = "mediatek,mt8516-pwrap"; - reg = <0 0x1000f000 0 0x1000>; - reg-names = "pwrap"; - interrupts = ; - clocks = <&topckgen CLK_TOP_PMICWRAP_26M>, - <&topckgen CLK_TOP_PMICWRAP_AP>; - clock-names = "spi", "wrap"; - }; - - sysirq: interrupt-controller@10200620 { - compatible = "mediatek,mt8516-sysirq", - "mediatek,mt6577-sysirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10200620 0 0x20>; - }; - - gic: interrupt-controller@10310000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; - reg = <0 0x10310000 0 0x1000>, - <0 0x10320000 0 0x1000>, - <0 0x10340000 0 0x2000>, - <0 0x10360000 0 0x2000>; - interrupts = ; - }; - - uart0: serial@11005000 { - compatible = "mediatek,mt8516-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11005000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UART0_SEL>, - <&topckgen CLK_TOP_UART0>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart1: serial@11006000 { - compatible = "mediatek,mt8516-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11006000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UART1_SEL>, - <&topckgen CLK_TOP_UART1>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - uart2: serial@11007000 { - compatible = "mediatek,mt8516-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11007000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UART2_SEL>, - <&topckgen CLK_TOP_UART2>; - clock-names = "baud", "bus"; - status = "disabled"; - }; - - i2c0: i2c@11009000 { - compatible = "mediatek,mt8516-i2c", - "mediatek,mt2712-i2c"; - reg = <0 0x11009000 0 0x90>, - <0 0x11000180 0 0x80>; - interrupts = ; - clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, - <&infracfg CLK_IFR_I2C0_SEL>, - <&topckgen CLK_TOP_I2C0>, - <&topckgen CLK_TOP_APDMA>; - clock-names = "main-source", - "main-sel", - "main", - "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@1100a000 { - compatible = "mediatek,mt8516-i2c", - "mediatek,mt2712-i2c"; - reg = <0 0x1100a000 0 0x90>, - <0 0x11000200 0 0x80>; - interrupts = ; - clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, - <&infracfg CLK_IFR_I2C1_SEL>, - <&topckgen CLK_TOP_I2C1>, - <&topckgen CLK_TOP_APDMA>; - clock-names = "main-source", - "main-sel", - "main", - "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@1100b000 { - compatible = "mediatek,mt8516-i2c", - "mediatek,mt2712-i2c"; - reg = <0 0x1100b000 0 0x90>, - <0 0x11000280 0 0x80>; - interrupts = ; - clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, - <&infracfg CLK_IFR_I2C2_SEL>, - <&topckgen CLK_TOP_I2C2>, - <&topckgen CLK_TOP_APDMA>; - clock-names = "main-source", - "main-sel", - "main", - "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi: spi@1100c000 { - compatible = "mediatek,mt8516-spi", - "mediatek,mt2712-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100c000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_UNIVPLL_D12>, - <&topckgen CLK_TOP_SPI_SEL>, - <&topckgen CLK_TOP_SPI>; - clock-names = "parent-clk", "sel-clk", "spi-clk"; - status = "disabled"; - }; - - mmc0: mmc@11120000 { - compatible = "mediatek,mt8516-mmc"; - reg = <0 0x11120000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_MSDC0>, - <&topckgen CLK_TOP_AHB_INFRA_SEL>, - <&topckgen CLK_TOP_MSDC0_INFRA>; - clock-names = "source", "hclk", "source_cg"; - status = "disabled"; - }; - - mmc1: mmc@11130000 { - compatible = "mediatek,mt8516-mmc"; - reg = <0 0x11130000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_MSDC1>, - <&topckgen CLK_TOP_AHB_INFRA_SEL>, - <&topckgen CLK_TOP_MSDC1_INFRA>; - clock-names = "source", "hclk", "source_cg"; - status = "disabled"; - }; - - mmc2: mmc@11170000 { - compatible = "mediatek,mt8516-mmc"; - reg = <0 0x11170000 0 0x1000>; - interrupts = ; - clocks = <&topckgen CLK_TOP_MSDC2>, - <&topckgen CLK_TOP_RG_MSDC2>, - <&topckgen CLK_TOP_MSDC2_INFRA>; - clock-names = "source", "hclk", "source_cg"; - status = "disabled"; - }; - - ethernet: ethernet@11180000 { - compatible = "mediatek,mt8516-eth"; - reg = <0 0x11180000 0 0x1000>; - mediatek,pericfg = <&pericfg>; - interrupts = ; - clocks = <&topckgen CLK_TOP_RG_ETH>, - <&topckgen CLK_TOP_66M_ETH>, - <&topckgen CLK_TOP_133M_ETH>; - clock-names = "core", "reg", "trans"; - status = "disabled"; - }; - - rng: rng@1020c000 { - compatible = "mediatek,mt8516-rng", - "mediatek,mt7623-rng"; - reg = <0 0x1020c000 0 0x100>; - clocks = <&topckgen CLK_TOP_TRNG>; - clock-names = "rng"; - }; - - pwm: pwm@11008000 { - compatible = "mediatek,mt8516-pwm"; - reg = <0 0x11008000 0 0x1000>; - #pwm-cells = <2>; - interrupts = ; - clocks = <&topckgen CLK_TOP_PWM>, - <&topckgen CLK_TOP_PWM_B>, - <&topckgen CLK_TOP_PWM1_FB>, - <&topckgen CLK_TOP_PWM2_FB>, - <&topckgen CLK_TOP_PWM3_FB>, - <&topckgen CLK_TOP_PWM4_FB>, - <&topckgen CLK_TOP_PWM5_FB>; - clock-names = "top", "main", "pwm1", "pwm2", "pwm3", - "pwm4", "pwm5"; - }; - - usb0: usb@11100000 { - compatible = "mediatek,mtk-musb"; - reg = <0 0x11100000 0 0x1000>; - interrupts = ; - interrupt-names = "mc"; - phys = <&usb0_port PHY_TYPE_USB2>; - clocks = <&topckgen CLK_TOP_USB>, - <&topckgen CLK_TOP_USBIF>, - <&topckgen CLK_TOP_USB_1P>; - clock-names = "main","mcu","univpll"; - status = "disabled"; - }; - - usb0_phy: usb@11110000 { - compatible = "mediatek,generic-tphy-v1"; - reg = <0 0x11110000 0 0x800>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - usb0_port: usb-phy@11110800 { - reg = <0 0x11110800 0 0x100>; - clocks = <&topckgen CLK_TOP_USB_PHY48M>; - clock-names = "ref"; - #phy-cells = <1>; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi deleted file mode 100644 index 99c2d6fd6..000000000 --- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi +++ /dev/null @@ -1,255 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 BayLibre, SAS. - * Author: Fabien Parent - */ - -#include - -/ { - aliases { - serial0 = &uart0; - ethernet0 = ðernet; - }; - - chosen { - stdout-path = "serial0:921600n8"; - }; - - firmware { - optee: optee@4fd00000 { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - input-name = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_default>; - - volume-up { - gpios = <&pio 42 GPIO_ACTIVE_LOW>; - label = "volume_up"; - linux,code = <115>; - wakeup-source; - debounce-interval = <15>; - }; - - volume-down { - gpios = <&pio 43 GPIO_ACTIVE_LOW>; - label = "volume_down"; - linux,code = <114>; - wakeup-source; - debounce-interval = <15>; - }; - }; -}; - -&i2c0 { - clock-div = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - tca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - reset-gpios = <&pio 65 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&tca6416_pins>; - - gpio-controller; - #gpio-cells = <2>; - - eint20_mux_sel0 { - gpio-hog; - gpios = <0 0>; - input; - line-name = "eint20_mux_sel0"; - }; - - expcon_mux_sel1 { - gpio-hog; - gpios = <1 0>; - input; - line-name = "expcon_mux_sel1"; - }; - - mrg_di_mux_sel2 { - gpio-hog; - gpios = <2 0>; - input; - line-name = "mrg_di_mux_sel2"; - }; - - sd_sdio_mux_sel3 { - gpio-hog; - gpios = <3 0>; - input; - line-name = "sd_sdio_mux_sel3"; - }; - - sd_sdio_mux_ctrl7 { - gpio-hog; - gpios = <7 0>; - output-low; - line-name = "sd_sdio_mux_ctrl7"; - }; - - hw_id0 { - gpio-hog; - gpios = <8 0>; - input; - line-name = "hw_id0"; - }; - - hw_id1 { - gpio-hog; - gpios = <9 0>; - input; - line-name = "hw_id1"; - }; - - hw_id2 { - gpio-hog; - gpios = <10 0>; - input; - line-name = "hw_id2"; - }; - - fg_int_n { - gpio-hog; - gpios = <11 0>; - input; - line-name = "fg_int_n"; - }; - - usba_pwr_en { - gpio-hog; - gpios = <12 0>; - output-high; - line-name = "usba_pwr_en"; - }; - - wifi_3v3_pg { - gpio-hog; - gpios = <13 0>; - input; - line-name = "wifi_3v3_pg"; - }; - - cam_rst { - gpio-hog; - gpios = <14 0>; - output-low; - line-name = "cam_rst"; - }; - - cam_pwdn { - gpio-hog; - gpios = <15 0>; - output-low; - line-name = "cam_pwdn"; - }; - }; -}; - -&i2c2 { - clock-div = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -ðernet { - pinctrl-names = "default"; - pinctrl-0 = <ðernet_pins_default>; - phy-handle = <ð_phy>; - phy-mode = "rmii"; - mac-address = [00 00 00 00 00 00]; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - eth_phy: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&usb0 { - status = "okay"; - dr_mode = "peripheral"; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - }; -}; - -&usb0_phy { - status = "okay"; -}; - -&pio { - gpio_keys_default: gpiodefault { - pins_cmd_dat { - pinmux = , - ; - bias-pull-up; - input-enable; - }; - }; - - i2c0_pins_a: i2c0@0 { - pins1 { - pinmux = , - ; - bias-disable; - }; - }; - - i2c2_pins_a: i2c2@0 { - pins1 { - pinmux = , - ; - bias-disable; - }; - }; - - tca6416_pins: pinmux_tca6416_pins { - gpio_mux_rst_n_pin { - pinmux = ; - output-high; - }; - - gpio_mux_int_n_pin { - pinmux = ; - input-enable; - bias-pull-up; - }; - }; - - ethernet_pins_default: ethernet { - pins_ethernet { - pinmux = , - , - , - , - , - , - , - , - , - ; - }; - }; -}; diff --git a/arch/arm64/boot/dts/microchip/Makefile b/arch/arm64/boot/dts/microchip/Makefile deleted file mode 100644 index c6e0313ee..000000000 --- a/arch/arm64/boot/dts/microchip/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb125.dtb -dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb134.dtb sparx5_pcb134_emmc.dtb -dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb135.dtb sparx5_pcb135_emmc.dtb diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi deleted file mode 100644 index 3cb01c39c..000000000 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ /dev/null @@ -1,294 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - */ - -#include -#include -#include - -/ { - compatible = "microchip,sparx5"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <1>; - - aliases { - spi0 = &spi0; - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - }; - }; - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - lcpll_clk: lcpll-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <2500000000>; - }; - - clks: clock-controller@61110000c { - compatible = "microchip,sparx5-dpll"; - #clock-cells = <1>; - clocks = <&lcpll_clk>; - reg = <0x6 0x1110000c 0x24>; - }; - - ahb_clk: ahb-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - }; - - sys_clk: sys-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <625000000>; - }; - - axi: axi@600000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges; - - gic: interrupt-controller@600300000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - interrupt-controller; - reg = <0x6 0x00300000 0x10000>, /* GIC Dist */ - <0x6 0x00340000 0xc0000>, /* GICR */ - <0x6 0x00200000 0x2000>, /* GICC */ - <0x6 0x00210000 0x2000>, /* GICV */ - <0x6 0x00220000 0x2000>; /* GICH */ - interrupts = ; - }; - - cpu_ctrl: syscon@600000000 { - compatible = "microchip,sparx5-cpu-syscon", "syscon", - "simple-mfd"; - reg = <0x6 0x00000000 0xd0>; - mux: mux-controller { - compatible = "mmio-mux"; - #mux-control-cells = <0>; - /* - * SI_OWNER and SI2_OWNER in GENERAL_CTRL - * SPI: value 9 - (SIMC,SIBM) = 0b1001 - * SPI2: value 6 - (SIBM,SIMC) = 0b0110 - */ - mux-reg-masks = <0x88 0xf0>; - }; - }; - - uart0: serial@600100000 { - pinctrl-0 = <&uart_pins>; - pinctrl-names = "default"; - compatible = "ns16550a"; - reg = <0x6 0x00100000 0x20>; - clocks = <&ahb_clk>; - reg-io-width = <4>; - reg-shift = <2>; - interrupts = ; - - status = "disabled"; - }; - - uart1: serial@600102000 { - pinctrl-0 = <&uart2_pins>; - pinctrl-names = "default"; - compatible = "ns16550a"; - reg = <0x6 0x00102000 0x20>; - clocks = <&ahb_clk>; - reg-io-width = <4>; - reg-shift = <2>; - interrupts = ; - - status = "disabled"; - }; - - spi0: spi@600104000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "microchip,sparx5-spi"; - reg = <0x6 0x00104000 0x40>; - num-cs = <16>; - reg-io-width = <4>; - reg-shift = <2>; - clocks = <&ahb_clk>; - interrupts = ; - status = "disabled"; - }; - - timer1: timer@600105000 { - compatible = "snps,dw-apb-timer"; - reg = <0x6 0x00105000 0x1000>; - clocks = <&ahb_clk>; - clock-names = "timer"; - interrupts = ; - }; - - sdhci0: mmc@600800000 { - compatible = "microchip,dw-sparx5-sdhci"; - status = "disabled"; - reg = <0x6 0x00800000 0x1000>; - pinctrl-0 = <&emmc_pins>; - pinctrl-names = "default"; - clocks = <&clks CLK_ID_AUX1>; - clock-names = "core"; - assigned-clocks = <&clks CLK_ID_AUX1>; - assigned-clock-rates = <800000000>; - interrupts = ; - bus-width = <8>; - }; - - gpio: pinctrl@6110101e0 { - compatible = "microchip,sparx5-pinctrl"; - reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&gpio 0 0 64>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <2>; - - cs1_pins: cs1-pins { - pins = "GPIO_16"; - function = "si"; - }; - - cs2_pins: cs2-pins { - pins = "GPIO_17"; - function = "si"; - }; - - cs3_pins: cs3-pins { - pins = "GPIO_18"; - function = "si"; - }; - - si2_pins: si2-pins { - pins = "GPIO_39", "GPIO_40", "GPIO_41"; - function = "si2"; - }; - - uart_pins: uart-pins { - pins = "GPIO_10", "GPIO_11"; - function = "uart"; - }; - - uart2_pins: uart2-pins { - pins = "GPIO_26", "GPIO_27"; - function = "uart2"; - }; - - i2c_pins: i2c-pins { - pins = "GPIO_14", "GPIO_15"; - function = "twi"; - }; - - i2c2_pins: i2c2-pins { - pins = "GPIO_28", "GPIO_29"; - function = "twi2"; - }; - - emmc_pins: emmc-pins { - pins = "GPIO_34", "GPIO_35", "GPIO_36", - "GPIO_37", "GPIO_38", "GPIO_39", - "GPIO_40", "GPIO_41", "GPIO_42", - "GPIO_43", "GPIO_44", "GPIO_45", - "GPIO_46", "GPIO_47"; - function = "emmc"; - }; - }; - - i2c0: i2c@600101000 { - compatible = "snps,designware-i2c"; - status = "disabled"; - pinctrl-0 = <&i2c_pins>; - pinctrl-names = "default"; - reg = <0x6 0x00101000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - i2c-sda-hold-time-ns = <300>; - clock-frequency = <100000>; - clocks = <&ahb_clk>; - }; - - i2c1: i2c@600103000 { - compatible = "snps,designware-i2c"; - status = "disabled"; - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - reg = <0x6 0x00103000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - i2c-sda-hold-time-ns = <300>; - clock-frequency = <100000>; - clocks = <&ahb_clk>; - }; - - tmon0: tmon@610508110 { - compatible = "microchip,sparx5-temp"; - reg = <0x6 0x10508110 0xc>; - #thermal-sensor-cells = <0>; - clocks = <&ahb_clk>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi b/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi deleted file mode 100644 index 03f107e42..000000000 --- a/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - */ - -&gpio { - cs14_pins: cs14-pins { - pins = "GPIO_44"; - function = "si"; - }; -}; - -&spi0 { - pinctrl-0 = <&si2_pins>; - pinctrl-names = "default"; - spi@e { - compatible = "spi-mux"; - mux-controls = <&mux>; - #address-cells = <1>; - #size-cells = <0>; - reg = <14>; /* CS14 */ - spi-flash@6 { - compatible = "spi-nand"; - pinctrl-0 = <&cs14_pins>; - pinctrl-names = "default"; - reg = <0x6>; /* SPI2 */ - spi-max-frequency = <42000000>; - rx-sample-delay-ns = <7>; /* Tune for speed */ - }; - }; -}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts deleted file mode 100644 index 6b2da7c75..000000000 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - */ - -/dts-v1/; -#include "sparx5_pcb_common.dtsi" - -/ { - model = "Sparx5 PCB125 Reference Board"; - compatible = "microchip,sparx5-pcb125", "microchip,sparx5"; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x10000000>; - }; -}; - -&gpio { - emmc_pins: emmc-pins { - /* NB: No "GPIO_35", "GPIO_36", "GPIO_37" - * (N/A: CARD_nDETECT, CARD_WP, CARD_LED) - */ - pins = "GPIO_34", "GPIO_38", "GPIO_39", - "GPIO_40", "GPIO_41", "GPIO_42", - "GPIO_43", "GPIO_44", "GPIO_45", - "GPIO_46", "GPIO_47"; - drive-strength = <3>; - function = "emmc"; - }; -}; - -&sdhci0 { - status = "okay"; - bus-width = <8>; - non-removable; - pinctrl-0 = <&emmc_pins>; - max-frequency = <8000000>; - microchip,clock-delay = <10>; -}; - -&spi0 { - status = "okay"; - spi@0 { - compatible = "spi-mux"; - mux-controls = <&mux>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; /* CS0 */ - spi-flash@9 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <8000000>; - reg = <0x9>; /* SPI */ - }; - }; - spi@1 { - compatible = "spi-mux"; - mux-controls = <&mux 0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; /* CS1 */ - spi-flash@9 { - compatible = "spi-nand"; - pinctrl-0 = <&cs1_pins>; - pinctrl-names = "default"; - spi-max-frequency = <8000000>; - reg = <0x9>; /* SPI */ - }; - }; -}; - -&i2c1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts deleted file mode 100644 index 45ca1af7e..000000000 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - */ - -/dts-v1/; -#include "sparx5_pcb134_board.dtsi" -#include "sparx5_nand.dtsi" - -/ { - model = "Sparx5 PCB134 Reference Board (NAND)"; - compatible = "microchip,sparx5-pcb134", "microchip,sparx5"; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x10000000>; - }; -}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi deleted file mode 100644 index f37b478d6..000000000 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ /dev/null @@ -1,284 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - */ - -/dts-v1/; -#include "sparx5_pcb_common.dtsi" - -/{ - aliases { - i2c0 = &i2c0; - i2c100 = &i2c100; - i2c101 = &i2c101; - i2c102 = &i2c102; - i2c103 = &i2c103; - i2c104 = &i2c104; - i2c105 = &i2c105; - i2c106 = &i2c106; - i2c107 = &i2c107; - i2c108 = &i2c108; - i2c109 = &i2c109; - i2c110 = &i2c110; - i2c111 = &i2c111; - i2c112 = &i2c112; - i2c113 = &i2c113; - i2c114 = &i2c114; - i2c115 = &i2c115; - i2c116 = &i2c116; - i2c117 = &i2c117; - i2c118 = &i2c118; - i2c119 = &i2c119; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio 37 GPIO_ACTIVE_LOW>; - priority = <200>; - }; -}; - -&spi0 { - status = "okay"; - spi@0 { - compatible = "spi-mux"; - mux-controls = <&mux>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; /* CS0 */ - spi-flash@9 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <8000000>; - reg = <0x9>; /* SPI */ - }; - }; -}; - -&spi0 { - status = "okay"; - spi@0 { - compatible = "spi-mux"; - mux-controls = <&mux>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; /* CS0 */ - spi-flash@9 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <8000000>; - reg = <0x9>; /* SPI */ - }; - }; -}; - -&gpio { - i2cmux_pins_i: i2cmux-pins-i { - pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19", - "GPIO_20", "GPIO_22", "GPIO_36", "GPIO_35", - "GPIO_50", "GPIO_51", "GPIO_56", "GPIO_57"; - function = "twi_scl_m"; - output-low; - }; - i2cmux_0: i2cmux-0 { - pins = "GPIO_16"; - function = "twi_scl_m"; - output-high; - }; - i2cmux_1: i2cmux-1 { - pins = "GPIO_17"; - function = "twi_scl_m"; - output-high; - }; - i2cmux_2: i2cmux-2 { - pins = "GPIO_18"; - function = "twi_scl_m"; - output-high; - }; - i2cmux_3: i2cmux-3 { - pins = "GPIO_19"; - function = "twi_scl_m"; - output-high; - }; - i2cmux_4: i2cmux-4 { - pins = "GPIO_20"; - function = "twi_scl_m"; - output-high; - }; - i2cmux_5: i2cmux-5 { - pins = "GPIO_22"; - function = "twi_scl_m"; - output-high; - }; - i2cmux_6: i2cmux-6 { - pins = "GPIO_36"; - function = "twi_scl_m"; - output-high; - }; - i2cmux_7: i2cmux-7 { - pins = "GPIO_35"; - function = "twi_scl_m"; - output-high; - }; - i2cmux_8: i2cmux-8 { - pins = "GPIO_50"; - function = "twi_scl_m"; - output-high; - }; - i2cmux_9: i2cmux-9 { - pins = "GPIO_51"; - function = "twi_scl_m"; - output-high; - }; - i2cmux_10: i2cmux-10 { - pins = "GPIO_56"; - function = "twi_scl_m"; - output-high; - }; - i2cmux_11: i2cmux-11 { - pins = "GPIO_57"; - function = "twi_scl_m"; - output-high; - }; -}; - -&axi { - i2c0_imux: i2c0-imux@0 { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - i2c-parent = <&i2c0>; - }; - i2c0_emux: i2c0-emux@0 { - compatible = "i2c-mux-gpio"; - #address-cells = <1>; - #size-cells = <0>; - i2c-parent = <&i2c0>; - }; -}; - -&i2c0_imux { - pinctrl-names = - "i2c100", "i2c101", "i2c102", "i2c103", - "i2c104", "i2c105", "i2c106", "i2c107", - "i2c108", "i2c109", "i2c110", "i2c111", "idle"; - pinctrl-0 = <&i2cmux_0>; - pinctrl-1 = <&i2cmux_1>; - pinctrl-2 = <&i2cmux_2>; - pinctrl-3 = <&i2cmux_3>; - pinctrl-4 = <&i2cmux_4>; - pinctrl-5 = <&i2cmux_5>; - pinctrl-6 = <&i2cmux_6>; - pinctrl-7 = <&i2cmux_7>; - pinctrl-8 = <&i2cmux_8>; - pinctrl-9 = <&i2cmux_9>; - pinctrl-10 = <&i2cmux_10>; - pinctrl-11 = <&i2cmux_11>; - pinctrl-12 = <&i2cmux_pins_i>; - i2c100: i2c_sfp1 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c101: i2c_sfp2 { - reg = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c102: i2c_sfp3 { - reg = <0x2>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c103: i2c_sfp4 { - reg = <0x3>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c104: i2c_sfp5 { - reg = <0x4>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c105: i2c_sfp6 { - reg = <0x5>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c106: i2c_sfp7 { - reg = <0x6>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c107: i2c_sfp8 { - reg = <0x7>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c108: i2c_sfp9 { - reg = <0x8>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c109: i2c_sfp10 { - reg = <0x9>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c110: i2c_sfp11 { - reg = <0xa>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c111: i2c_sfp12 { - reg = <0xb>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&i2c0_emux { - mux-gpios = <&gpio 55 GPIO_ACTIVE_HIGH - &gpio 60 GPIO_ACTIVE_HIGH - &gpio 61 GPIO_ACTIVE_HIGH - &gpio 54 GPIO_ACTIVE_HIGH>; - idle-state = <0x8>; - i2c112: i2c_sfp13 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c113: i2c_sfp14 { - reg = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c114: i2c_sfp15 { - reg = <0x2>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c115: i2c_sfp16 { - reg = <0x3>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c116: i2c_sfp17 { - reg = <0x4>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c117: i2c_sfp18 { - reg = <0x5>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c118: i2c_sfp19 { - reg = <0x6>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c119: i2c_sfp20 { - reg = <0x7>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts deleted file mode 100644 index bbb9852c1..000000000 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - */ - -/dts-v1/; -#include "sparx5_pcb134_board.dtsi" - -/ { - model = "Sparx5 PCB134 Reference Board (eMMC enabled)"; - compatible = "microchip,sparx5-pcb134", "microchip,sparx5"; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x10000000>; - }; -}; - -&gpio { - emmc_pins: emmc-pins { - /* NB: No "GPIO_35", "GPIO_36", "GPIO_37" - * (N/A: CARD_nDETECT, CARD_WP, CARD_LED) - */ - pins = "GPIO_34", "GPIO_38", "GPIO_39", - "GPIO_40", "GPIO_41", "GPIO_42", - "GPIO_43", "GPIO_44", "GPIO_45", - "GPIO_46", "GPIO_47"; - drive-strength = <3>; - function = "emmc"; - }; -}; - -&sdhci0 { - status = "okay"; - pinctrl-0 = <&emmc_pins>; - non-removable; - max-frequency = <52000000>; - bus-width = <8>; - microchip,clock-delay = <10>; -}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts deleted file mode 100644 index 647cdb38b..000000000 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - */ - -/dts-v1/; -#include "sparx5_pcb135_board.dtsi" -#include "sparx5_nand.dtsi" - -/ { - model = "Sparx5 PCB135 Reference Board (NAND)"; - compatible = "microchip,sparx5-pcb135", "microchip,sparx5"; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x10000000>; - }; -}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi deleted file mode 100644 index b02b8c8ce..000000000 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - */ - -/dts-v1/; -#include "sparx5_pcb_common.dtsi" - -/{ - aliases { - i2c0 = &i2c0; - i2c152 = &i2c152; - i2c153 = &i2c153; - i2c154 = &i2c154; - i2c155 = &i2c155; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio 37 GPIO_ACTIVE_LOW>; - priority = <200>; - }; -}; - -&gpio { - i2cmux_pins_i: i2cmux-pins-i { - pins = "GPIO_35", "GPIO_36", - "GPIO_50", "GPIO_51"; - function = "twi_scl_m"; - output-low; - }; - i2cmux_s29: i2cmux-0 { - pins = "GPIO_35"; - function = "twi_scl_m"; - output-high; - }; - i2cmux_s30: i2cmux-1 { - pins = "GPIO_36"; - function = "twi_scl_m"; - output-high; - }; - i2cmux_s31: i2cmux-2 { - pins = "GPIO_50"; - function = "twi_scl_m"; - output-high; - }; - i2cmux_s32: i2cmux-3 { - pins = "GPIO_51"; - function = "twi_scl_m"; - output-high; - }; -}; - -&spi0 { - status = "okay"; - spi@0 { - compatible = "spi-mux"; - mux-controls = <&mux>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; /* CS0 */ - spi-flash@9 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <8000000>; - reg = <0x9>; /* SPI */ - }; - }; -}; - -&spi0 { - status = "okay"; - spi@0 { - compatible = "spi-mux"; - mux-controls = <&mux>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; /* CS0 */ - spi-flash@9 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <8000000>; - reg = <0x9>; /* SPI */ - }; - }; -}; - -&axi { - i2c0_imux: i2c0-imux@0 { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - i2c-parent = <&i2c0>; - }; -}; - -&i2c0_imux { - pinctrl-names = - "i2c152", "i2c153", "i2c154", "i2c155", - "idle"; - pinctrl-0 = <&i2cmux_s29>; - pinctrl-1 = <&i2cmux_s30>; - pinctrl-2 = <&i2cmux_s31>; - pinctrl-3 = <&i2cmux_s32>; - pinctrl-4 = <&i2cmux_pins_i>; - i2c152: i2c_sfp1 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c153: i2c_sfp2 { - reg = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c154: i2c_sfp3 { - reg = <0x2>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c155: i2c_sfp4 { - reg = <0x3>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts deleted file mode 100644 index f82266fe2..000000000 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - */ - -/dts-v1/; -#include "sparx5_pcb135_board.dtsi" - -/ { - model = "Sparx5 PCB135 Reference Board (eMMC enabled)"; - compatible = "microchip,sparx5-pcb135", "microchip,sparx5"; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x10000000>; - }; -}; - -&gpio { - emmc_pins: emmc-pins { - /* NB: No "GPIO_35", "GPIO_36", "GPIO_37" - * (N/A: CARD_nDETECT, CARD_WP, CARD_LED) - */ - pins = "GPIO_34", "GPIO_38", "GPIO_39", - "GPIO_40", "GPIO_41", "GPIO_42", - "GPIO_43", "GPIO_44", "GPIO_45", - "GPIO_46", "GPIO_47"; - drive-strength = <3>; - function = "emmc"; - }; -}; - -&sdhci0 { - status = "okay"; - pinctrl-0 = <&emmc_pins>; - non-removable; - max-frequency = <52000000>; - bus-width = <8>; - microchip,clock-delay = <10>; -}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi deleted file mode 100644 index 9d1a082de..000000000 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - */ - -/dts-v1/; -#include "sparx5.dtsi" - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile deleted file mode 100644 index 9296d12d1..000000000 --- a/arch/arm64/boot/dts/nvidia/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb -dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb -dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb -dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb -dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p3450-0000.dtb -dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb -dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2894-0050-a08.dtb -dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb -dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb -dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0000.dtb -dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-sim-vdk.dtb diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts deleted file mode 100644 index 6e5f84656..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ /dev/null @@ -1,1197 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra132.dtsi" - -/ { - model = "NVIDIA Tegra132 Norrin"; - compatible = "nvidia,norrin", "nvidia,tegra132", "nvidia,tegra124"; - - aliases { - rtc0 = "/i2c@7000d000/as3722@40"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - host1x@50000000 { - hdmi@54280000 { - status = "disabled"; - - vdd-supply = <&vdd_3v3_hdmi>; - pll-supply = <&vdd_hdmi_pll>; - hdmi-supply = <&vdd_5v0_hdmi>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - }; - - sor@54540000 { - status = "okay"; - - avdd-io-hdmi-dp-supply = <&vdd_3v3_hdmi>; - vdd-hdmi-dp-pll-supply = <&vdd_hdmi_pll>; - - nvidia,dpaux = <&dpaux>; - nvidia,panel = <&panel>; - }; - - dpaux: dpaux@545c0000 { - vdd-supply = <&vdd_3v3_panel>; - status = "okay"; - }; - }; - - gpu@57000000 { - status = "okay"; - - vdd-supply = <&vdd_gpu>; - }; - - pinmux@70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_default>; - - pinmux_default: pinmux@0 { - dap_mclk1_pw4 { - nvidia,pins = "dap_mclk1_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5", - "dap2_fs_pa2", - "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0", - "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0", - "ulpi_nxt_py2", - "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1", - "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5", - "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - pj7 { - nvidia,pins = "pj7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "spdif"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk7 { - nvidia,pins = "pk7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg4 { - nvidia,pins = "pg4", - "pg5", - "pg6", - "pi3"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pg7 { - nvidia,pins = "pg7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph1 { - nvidia,pins = "ph1"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pk0 { - nvidia,pins = "pk0", - "kb_row15_ps7", - "clk_32k_out_pa0"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1", - "sdmmc1_dat0_py7", - "sdmmc1_dat1_py6", - "sdmmc1_dat2_py5", - "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7", - "sdmmc3_dat0_pb7", - "sdmmc3_dat1_pb6", - "sdmmc3_dat2_pb5", - "sdmmc3_dat3_pb4", - "kb_col4_pq4", - "sdmmc3_clk_lb_out_pee4", - "sdmmc3_clk_lb_in_pee5", - "sdmmc3_cd_n_pv2"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7", - "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - mic_det_l { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6", - "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - kb_col0_ap { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - en_vdd_sd { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lid_open { - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4", - "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4", - "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,rcv-sel = ; - }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4", - "usb_vbus_en1_pn5", - "usb_vbus_en2_pff1"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - drive_sdio1 { - nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <36>; - nvidia,pull-up-strength = <20>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <22>; - nvidia,pull-up-strength = <36>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - drive_gma { - nvidia,pins = "drive_gma"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <2>; - nvidia,pull-up-strength = <1>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - nvidia,drive-type = <1>; - }; - ac_ok { - nvidia,pins = "pj0"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - codec_irq_l { - nvidia,pins = "ph4"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - lcd_bl_en { - nvidia,pins = "ph2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - touch_irq_l { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - tpm_davint_l { - nvidia,pins = "ph6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ts_irq_l { - nvidia,pins = "pk2"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ts_reset_l { - nvidia,pins = "pk4"; - nvidia,function = "gmi"; - nvidia,pull = <1>; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ts_shdn_l { - nvidia,pins = "pk1"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - ph7 { - nvidia,pins = "ph7"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - sensor_irq_l { - nvidia,pins = "pi6"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - wifi_en { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - chromeos_write_protect { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "rsvd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - hp_det_l { - nvidia,pins = "pi7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - soc_warm_reset_l { - nvidia,pins = "pi5"; - nvidia,function = "gmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - }; - - serial@70006000 { - status = "okay"; - }; - - pwm: pwm@7000a000 { - status = "okay"; - }; - - /* HDMI DDC */ - hdmi_ddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - as3722: pmic@40 { - compatible = "ams,as3722"; - reg = <0x40>; - interrupts = ; - - ams,system-power-controller; - - #interrupt-cells = <2>; - interrupt-controller; - - #gpio-cells = <2>; - gpio-controller; - - pinctrl-names = "default"; - pinctrl-0 = <&as3722_default>; - - as3722_default: pinmux@0 { - gpio0 { - pins = "gpio0"; - function = "gpio"; - bias-pull-down; - }; - - gpio1 { - pins = "gpio1"; - function = "gpio"; - bias-pull-up; - }; - - gpio2_4_7 { - pins = "gpio2", "gpio4", "gpio7"; - function = "gpio"; - bias-pull-up; - }; - - gpio3 { - pins = "gpio3"; - function = "gpio"; - bias-high-impedance; - }; - - gpio5 { - pins = "gpio5"; - function = "clk32k-out"; - bias-pull-down; - }; - - gpio6 { - pins = "gpio6"; - function = "clk32k-out"; - bias-pull-down; - }; - }; - - regulators { - vsup-sd2-supply = <&vdd_5v0_sys>; - vsup-sd3-supply = <&vdd_5v0_sys>; - vsup-sd4-supply = <&vdd_5v0_sys>; - vsup-sd5-supply = <&vdd_5v0_sys>; - vin-ldo0-supply = <&vdd_1v35_lp0>; - vin-ldo1-6-supply = <&vdd_3v3_sys>; - vin-ldo2-5-7-supply = <&vddio_1v8>; - vin-ldo3-4-supply = <&vdd_3v3_sys>; - vin-ldo9-10-supply = <&vdd_5v0_sys>; - vin-ldo11-supply = <&vdd_3v3_run>; - - sd0 { - regulator-name = "+VDD_CPU_AP"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-max-microamp = <3500000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <2>; - }; - - sd1 { - regulator-name = "+VDD_CORE"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-max-microamp = <4000000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <1>; - }; - - vdd_1v35_lp0: sd2 { - regulator-name = "+1.35V_LP0(sd2)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - sd3 { - regulator-name = "+1.35V_LP0(sd3)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v05_run: sd4 { - regulator-name = "+1.05V_RUN"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - vddio_1v8: sd5 { - regulator-name = "+1.8V_VDDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_gpu: sd6 { - regulator-name = "+VDD_GPU_AP"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-always-on; - regulator-boot-on; - }; - - avdd_1v05_run: ldo0 { - regulator-name = "+1.05_RUN_AVDD"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - ams,ext-control = <1>; - }; - - ldo1 { - regulator-name = "+1.8V_RUN_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2 { - regulator-name = "+1.2V_GEN_AVDD"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo3 { - regulator-name = "+1.00V_LP0_VDD_RTC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - ams,enable-tracking; - }; - - vdd_run_cam: ldo4 { - regulator-name = "+2.8V_RUN_CAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo5 { - regulator-name = "+1.2V_RUN_CAM_FRONT"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vddio_sdmmc3: ldo6 { - regulator-name = "+VDDIO_SDMMC3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7 { - regulator-name = "+1.05V_RUN_CAM_REAR"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo9 { - regulator-name = "+2.8V_RUN_TOUCH"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo10 { - regulator-name = "+2.8V_RUN_CAM_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo11 { - regulator-name = "+1.8V_RUN_VPP_FUSE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - }; - - spi@7000d400 { - status = "okay"; - - ec: cros-ec@0 { - compatible = "google,cros-ec-spi"; - spi-max-frequency = <3000000>; - interrupt-parent = <&gpio>; - interrupts = ; - reg = <0>; - - google,cros-ec-spi-msg-delay = <2000>; - - i2c_20: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - #address-cells = <1>; - #size-cells = <0>; - - google,remote-bus = <0>; - - charger: bq24735 { - compatible = "ti,bq24735"; - reg = <0x9>; - interrupt-parent = <&gpio>; - interrupts = ; - ti,ac-detect-gpios = <&gpio - TEGRA_GPIO(J, 0) - GPIO_ACTIVE_HIGH>; - }; - - battery: smart-battery { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <10>; - /* power-supplies = <&charger>; */ - }; - }; - - keyboard-controller { - compatible = "google,cros-ec-keyb"; - keypad,num-rows = <8>; - keypad,num-columns = <13>; - google,needs-ghost-filter; - linux,keymap = - ; - }; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - #wake-cells = <3>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - nvidia,reset-gpio = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - }; - - usb@70090000 { - phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ - <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ - <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ - <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ - <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ - phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1"; - - avddio-pex-supply = <&vdd_1v05_run>; - dvddio-pex-supply = <&vdd_1v05_run>; - avdd-usb-supply = <&vdd_3v3_lp0>; - hvdd-usb-ss-supply = <&vdd_3v3_lp0>; - - status = "okay"; - }; - - padctl@7009f000 { - avdd-pll-utmip-supply = <&vddio_1v8>; - avdd-pll-erefe-supply = <&avdd_1v05_run>; - avdd-pex-pll-supply = <&vdd_1v05_run>; - hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-1 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "okay"; - mode = "otg"; - - vbus-supply = <&vdd_usb1_vbus>; - }; - - usb2-1 { - status = "okay"; - mode = "host"; - - vbus-supply = <&vdd_run_cam>; - }; - - usb2-2 { - status = "okay"; - mode = "host"; - - vbus-supply = <&vdd_usb3_vbus>; - }; - - usb3-0 { - nvidia,usb2-companion = <0>; - status = "okay"; - }; - - usb3-1 { - nvidia,usb2-companion = <2>; - status = "okay"; - }; - }; - }; - - /* WIFI/BT module */ - mmc@700b0000 { - status = "disabled"; - }; - - /* external SD/MMC */ - mmc@700b0400 { - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; - status = "okay"; - bus-width = <4>; - vqmmc-supply = <&vddio_sdmmc3>; - }; - - /* EMMC 4.51 */ - mmc@700b0600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_led>; - pwms = <&pwm 1 1000000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - - backlight-boot-off; - }; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - lid { - label = "Lid"; - gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; - linux,input-type = <5>; - linux,code = <0>; - debounce-interval = <1>; - wakeup-source; - }; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - - panel: panel { - compatible = "innolux,n116bge"; - power-supply = <&vdd_3v3_panel>; - backlight = <&backlight>; - ddc-i2c-bus = <&dpaux>; - }; - - vdd_mux: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "+VDD_MUX"; - regulator-min-microvolt = <19000000>; - regulator-max-microvolt = <19000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "+5V_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_sys: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "+3.3V_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_run: regulator@3 { - compatible = "regulator-fixed"; - regulator-name = "+3.3V_RUN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&as3722 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_3v3_hdmi: regulator@4 { - compatible = "regulator-fixed"; - regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_run>; - }; - - vdd_led: regulator@5 { - compatible = "regulator-fixed"; - regulator-name = "+VDD_LED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_mux>; - }; - - vdd_usb1_vbus: regulator@6 { - compatible = "regulator-fixed"; - regulator-name = "+5V_USB_HS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb3_vbus: regulator@7 { - compatible = "regulator-fixed"; - regulator-name = "+5V_USB_SS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_3v3_panel: regulator@8 { - compatible = "regulator-fixed"; - regulator-name = "+3.3V_PANEL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&as3722 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_hdmi_pll: regulator@9 { - compatible = "regulator-fixed"; - regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05_run>; - }; - - vdd_5v0_hdmi: regulator@10 { - compatible = "regulator-fixed"; - regulator-name = "+5V_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_5v0_ts: regulator@11 { - compatible = "regulator-fixed"; - regulator-name = "+5V_VDD_TS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_3v3_lp0: regulator@12 { - compatible = "regulator-fixed"; - regulator-name = "+3.3V_LP0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* - * TODO: find a way to wire this up with the USB EHCI - * controllers so that it can be enabled on demand. - */ - regulator-always-on; - gpio = <&as3722 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi deleted file mode 100644 index b14e9f3bf..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ /dev/null @@ -1,1241 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "nvidia,tegra132", "nvidia,tegra124"; - interrupt-parent = <&lic>; - #address-cells = <2>; - #size-cells = <2>; - - pcie@1003000 { - compatible = "nvidia,tegra124-pcie"; - device_type = "pci"; - reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ - <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ - <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ - reg-names = "pads", "afi", "cs"; - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - - bus-range = <0x00 0xff>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ - <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ - <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ - <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ - <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ - - clocks = <&tegra_car TEGRA124_CLK_PCIE>, - <&tegra_car TEGRA124_CLK_AFI>, - <&tegra_car TEGRA124_CLK_PLL_E>, - <&tegra_car TEGRA124_CLK_CML0>; - clock-names = "pex", "afi", "pll_e", "cml"; - resets = <&tegra_car 70>, - <&tegra_car 72>, - <&tegra_car 74>; - reset-names = "pex", "afi", "pcie_x"; - status = "disabled"; - - pci@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; - reg = <0x000800 0 0 0 0>; - bus-range = <0x00 0xff>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - - pci@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; - reg = <0x001000 0 0 0 0>; - bus-range = <0x00 0xff>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <1>; - }; - }; - - host1x@50000000 { - compatible = "nvidia,tegra132-host1x", - "nvidia,tegra124-host1x"; - reg = <0x0 0x50000000 0x0 0x00034000>; - interrupts = , /* syncpt */ - ; /* general */ - interrupt-names = "syncpt", "host1x"; - clocks = <&tegra_car TEGRA124_CLK_HOST1X>; - clock-names = "host1x"; - resets = <&tegra_car 28>; - reset-names = "host1x"; - - #address-cells = <2>; - #size-cells = <2>; - - ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; - - dc@54200000 { - compatible = "nvidia,tegra124-dc"; - reg = <0x0 0x54200000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DISP1>; - clock-names = "dc"; - resets = <&tegra_car 27>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DC>; - - nvidia,head = <0>; - }; - - dc@54240000 { - compatible = "nvidia,tegra124-dc"; - reg = <0x0 0x54240000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DISP2>; - clock-names = "dc"; - resets = <&tegra_car 26>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DCB>; - - nvidia,head = <1>; - }; - - hdmi@54280000 { - compatible = "nvidia,tegra124-hdmi"; - reg = <0x0 0x54280000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_HDMI>, - <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; - clock-names = "hdmi", "parent"; - resets = <&tegra_car 51>; - reset-names = "hdmi"; - status = "disabled"; - }; - - sor@54540000 { - compatible = "nvidia,tegra124-sor"; - reg = <0x0 0x54540000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SOR0>, - <&tegra_car TEGRA124_CLK_SOR0_OUT>, - <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, - <&tegra_car TEGRA124_CLK_PLL_DP>, - <&tegra_car TEGRA124_CLK_CLK_M>; - clock-names = "sor", "out", "parent", "dp", "safe"; - resets = <&tegra_car 182>; - reset-names = "sor"; - status = "disabled"; - }; - - dpaux: dpaux@545c0000 { - compatible = "nvidia,tegra124-dpaux"; - reg = <0x0 0x545c0000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_DPAUX>, - <&tegra_car TEGRA124_CLK_PLL_DP>; - clock-names = "dpaux", "parent"; - resets = <&tegra_car 181>; - reset-names = "dpaux"; - status = "disabled"; - - i2c-bus { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; - - gic: interrupt-controller@50041000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x50041000 0x0 0x1000>, - <0x0 0x50042000 0x0 0x2000>, - <0x0 0x50044000 0x0 0x2000>, - <0x0 0x50046000 0x0 0x2000>; - interrupts = ; - interrupt-parent = <&gic>; - }; - - gpu@57000000 { - compatible = "nvidia,gk20a"; - reg = <0x0 0x57000000 0x0 0x01000000>, - <0x0 0x58000000 0x0 0x01000000>; - interrupts = , - ; - interrupt-names = "stall", "nonstall"; - clocks = <&tegra_car TEGRA124_CLK_GPU>, - <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; - clock-names = "gpu", "pwr"; - resets = <&tegra_car 184>; - reset-names = "gpu"; - status = "disabled"; - }; - - lic: interrupt-controller@60004000 { - compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; - reg = <0x0 0x60004000 0x0 0x100>, - <0x0 0x60004100 0x0 0x100>, - <0x0 0x60004200 0x0 0x100>, - <0x0 0x60004300 0x0 0x100>, - <0x0 0x60004400 0x0 0x100>; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; - - timer@60005000 { - compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; - reg = <0x0 0x60005000 0x0 0x400>; - interrupts = , - , - , - , - , - ; - clocks = <&tegra_car TEGRA124_CLK_TIMER>; - clock-names = "timer"; - }; - - tegra_car: clock@60006000 { - compatible = "nvidia,tegra132-car"; - reg = <0x0 0x60006000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - nvidia,external-memory-controller = <&emc>; - }; - - flow-controller@60007000 { - compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl"; - reg = <0x0 0x60007000 0x0 0x1000>; - }; - - actmon@6000c800 { - compatible = "nvidia,tegra124-actmon"; - reg = <0x0 0x6000c800 0x0 0x400>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_ACTMON>, - <&tegra_car TEGRA124_CLK_EMC>; - clock-names = "actmon", "emc"; - resets = <&tegra_car 119>; - reset-names = "actmon"; - }; - - gpio: gpio@6000d000 { - compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; - reg = <0x0 0x6000d000 0x0 0x1000>; - interrupts = , - , - , - , - , - , - , - ; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - apbdma: dma@60020000 { - compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; - reg = <0x0 0x60020000 0x0 0x1400>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&tegra_car TEGRA124_CLK_APBDMA>; - clock-names = "dma"; - resets = <&tegra_car 34>; - reset-names = "dma"; - #dma-cells = <1>; - }; - - apbmisc@70000800 { - compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; - reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ - <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ - }; - - pinmux: pinmux@70000868 { - compatible = "nvidia,tegra124-pinmux"; - reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ - <0x0 0x70003000 0x0 0x434>, /* Mux registers */ - <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ - }; - - /* - * There are two serial driver i.e. 8250 based simple serial - * driver and APB DMA based serial driver for higher baudrate - * and performance. To enable the 8250 based driver, the compatible - * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable - * the APB DMA based serial driver, the compatible is - * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". - */ - uarta: serial@70006000 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006000 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_UARTA>; - clock-names = "serial"; - resets = <&tegra_car 6>; - reset-names = "serial"; - dmas = <&apbdma 8>, <&apbdma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartb: serial@70006040 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006040 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_UARTB>; - clock-names = "serial"; - resets = <&tegra_car 7>; - reset-names = "serial"; - dmas = <&apbdma 9>, <&apbdma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartc: serial@70006200 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006200 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_UARTC>; - clock-names = "serial"; - resets = <&tegra_car 55>; - reset-names = "serial"; - dmas = <&apbdma 10>, <&apbdma 10>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartd: serial@70006300 { - compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006300 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_UARTD>; - clock-names = "serial"; - resets = <&tegra_car 65>; - reset-names = "serial"; - dmas = <&apbdma 19>, <&apbdma 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - pwm: pwm@7000a000 { - compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; - reg = <0x0 0x7000a000 0x0 0x100>; - #pwm-cells = <2>; - clocks = <&tegra_car TEGRA124_CLK_PWM>; - clock-names = "pwm"; - resets = <&tegra_car 17>; - reset-names = "pwm"; - status = "disabled"; - }; - - i2c@7000c000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000c000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C1>; - clock-names = "div-clk"; - resets = <&tegra_car 12>; - reset-names = "i2c"; - dmas = <&apbdma 21>, <&apbdma 21>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c400 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000c400 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C2>; - clock-names = "div-clk"; - resets = <&tegra_car 54>; - reset-names = "i2c"; - dmas = <&apbdma 22>, <&apbdma 22>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c500 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000c500 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C3>; - clock-names = "div-clk"; - resets = <&tegra_car 67>; - reset-names = "i2c"; - dmas = <&apbdma 23>, <&apbdma 23>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c700 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000c700 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C4>; - clock-names = "div-clk"; - resets = <&tegra_car 103>; - reset-names = "i2c"; - dmas = <&apbdma 26>, <&apbdma 26>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000d000 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000d000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C5>; - clock-names = "div-clk"; - resets = <&tegra_car 47>; - reset-names = "i2c"; - dmas = <&apbdma 24>, <&apbdma 24>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000d100 { - compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x0 0x7000d100 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_I2C6>; - clock-names = "div-clk"; - resets = <&tegra_car 166>; - reset-names = "i2c"; - dmas = <&apbdma 30>, <&apbdma 30>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d400 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000d400 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC1>; - clock-names = "spi"; - resets = <&tegra_car 41>; - reset-names = "spi"; - dmas = <&apbdma 15>, <&apbdma 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d600 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000d600 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC2>; - clock-names = "spi"; - resets = <&tegra_car 44>; - reset-names = "spi"; - dmas = <&apbdma 16>, <&apbdma 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d800 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000d800 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC3>; - clock-names = "spi"; - resets = <&tegra_car 46>; - reset-names = "spi"; - dmas = <&apbdma 17>, <&apbdma 17>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000da00 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000da00 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC4>; - clock-names = "spi"; - resets = <&tegra_car 68>; - reset-names = "spi"; - dmas = <&apbdma 18>, <&apbdma 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000dc00 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000dc00 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC5>; - clock-names = "spi"; - resets = <&tegra_car 104>; - reset-names = "spi"; - dmas = <&apbdma 27>, <&apbdma 27>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000de00 { - compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000de00 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA124_CLK_SBC6>; - clock-names = "spi"; - resets = <&tegra_car 105>; - reset-names = "spi"; - dmas = <&apbdma 28>, <&apbdma 28>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - rtc@7000e000 { - compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; - reg = <0x0 0x7000e000 0x0 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_RTC>; - clock-names = "rtc"; - }; - - tegra_pmc: pmc@7000e400 { - compatible = "nvidia,tegra124-pmc"; - reg = <0x0 0x7000e400 0x0 0x400>; - clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - #clock-cells = <1>; - }; - - fuse@7000f800 { - compatible = "nvidia,tegra124-efuse"; - reg = <0x0 0x7000f800 0x0 0x400>; - clocks = <&tegra_car TEGRA124_CLK_FUSE>; - clock-names = "fuse"; - resets = <&tegra_car 39>; - reset-names = "fuse"; - }; - - mc: memory-controller@70019000 { - compatible = "nvidia,tegra132-mc"; - reg = <0x0 0x70019000 0x0 0x1000>; - clocks = <&tegra_car TEGRA124_CLK_MC>; - clock-names = "mc"; - - interrupts = ; - - #iommu-cells = <1>; - }; - - emc: external-memory-controller@7001b000 { - compatible = "nvidia,tegra132-emc"; - reg = <0x0 0x7001b000 0x0 0x1000>; - clocks = <&tegra_car TEGRA124_CLK_EMC>; - clock-names = "emc"; - - nvidia,memory-controller = <&mc>; - }; - - sata@70020000 { - compatible = "nvidia,tegra124-ahci"; - reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ - <0x0 0x70020000 0x0 0x7000>; /* SATA */ - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SATA>, - <&tegra_car TEGRA124_CLK_SATA_OOB>, - <&tegra_car TEGRA124_CLK_CML1>, - <&tegra_car TEGRA124_CLK_PLL_E>; - clock-names = "sata", "sata-oob", "cml1", "pll_e"; - resets = <&tegra_car 124>, - <&tegra_car 123>, - <&tegra_car 129>; - reset-names = "sata", "sata-oob", "sata-cold"; - status = "disabled"; - }; - - hda@70030000 { - compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda", - "nvidia,tegra30-hda"; - reg = <0x0 0x70030000 0x0 0x10000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_HDA>, - <&tegra_car TEGRA124_CLK_HDA2HDMI>, - <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; - clock-names = "hda", "hda2hdmi", "hda2codec_2x"; - resets = <&tegra_car 125>, /* hda */ - <&tegra_car 128>, /* hda2hdmi */ - <&tegra_car 111>; /* hda2codec_2x */ - reset-names = "hda", "hda2hdmi", "hda2codec_2x"; - status = "disabled"; - }; - - usb@70090000 { - compatible = "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"; - reg = <0x0 0x70090000 0x0 0x8000>, - <0x0 0x70098000 0x0 0x1000>, - <0x0 0x70099000 0x0 0x1000>; - reg-names = "hcd", "fpci", "ipfs"; - - interrupts = , - ; - - clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, - <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, - <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, - <&tegra_car TEGRA124_CLK_XUSB_SS>, - <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, - <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, - <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, - <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, - <&tegra_car TEGRA124_CLK_PLL_U_480M>, - <&tegra_car TEGRA124_CLK_CLK_M>, - <&tegra_car TEGRA124_CLK_PLL_E>; - clock-names = "xusb_host", "xusb_host_src", - "xusb_falcon_src", "xusb_ss", - "xusb_ss_src", "xusb_ss_div2", - "xusb_hs_src", "xusb_fs_src", - "pll_u_480m", "clk_m", "pll_e"; - resets = <&tegra_car 89>, <&tegra_car 156>, - <&tegra_car 143>; - reset-names = "xusb_host", "xusb_ss", "xusb_src"; - - nvidia,xusb-padctl = <&padctl>; - - status = "disabled"; - }; - - padctl: padctl@7009f000 { - compatible = "nvidia,tegra132-xusb-padctl", - "nvidia,tegra124-xusb-padctl"; - reg = <0x0 0x7009f000 0x0 0x1000>; - resets = <&tegra_car 142>; - reset-names = "padctl"; - - pads { - usb2 { - status = "disabled"; - - lanes { - usb2-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-2 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - ulpi { - status = "disabled"; - - lanes { - ulpi-0 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - hsic { - status = "disabled"; - - lanes { - hsic-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - hsic-1 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - pcie { - status = "disabled"; - - lanes { - pcie-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-2 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-3 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-4 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - sata { - status = "disabled"; - - lanes { - sata-0 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "disabled"; - }; - - usb2-1 { - status = "disabled"; - }; - - usb2-2 { - status = "disabled"; - }; - - hsic-0 { - status = "disabled"; - }; - - hsic-1 { - status = "disabled"; - }; - - usb3-0 { - status = "disabled"; - }; - - usb3-1 { - status = "disabled"; - }; - }; - }; - - mmc@700b0000 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0000 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; - clock-names = "sdhci"; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - status = "disabled"; - }; - - mmc@700b0200 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0200 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; - clock-names = "sdhci"; - resets = <&tegra_car 9>; - reset-names = "sdhci"; - status = "disabled"; - }; - - mmc@700b0400 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0400 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; - clock-names = "sdhci"; - resets = <&tegra_car 69>; - reset-names = "sdhci"; - status = "disabled"; - }; - - mmc@700b0600 { - compatible = "nvidia,tegra124-sdhci"; - reg = <0x0 0x700b0600 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; - clock-names = "sdhci"; - resets = <&tegra_car 15>; - reset-names = "sdhci"; - status = "disabled"; - }; - - soctherm: thermal-sensor@700e2000 { - compatible = "nvidia,tegra132-soctherm"; - reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */ - <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */ - reg-names = "soctherm-reg", "ccroc-reg"; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, - <&tegra_car TEGRA124_CLK_SOC_THERM>; - clock-names = "tsensor", "soctherm"; - resets = <&tegra_car 78>; - reset-names = "soctherm"; - #thermal-sensor-cells = <1>; - - throttle-cfgs { - throttle_heavy: heavy { - nvidia,priority = <100>; - nvidia,cpu-throt-level = ; - - #cooling-cells = <2>; - }; - }; - }; - - thermal-zones { - cpu { - polling-delay-passive = <1000>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; - - trips { - cpu_shutdown_trip { - temperature = <105000>; - hysteresis = <1000>; - type = "critical"; - }; - - cpu_throttle_trip: throttle-trip { - temperature = <102000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_throttle_trip>; - cooling-device = <&throttle_heavy 1 1>; - }; - }; - }; - mem { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; - - trips { - mem_shutdown_trip { - temperature = <101000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - /* - * There are currently no cooling maps, - * because there are no cooling devices. - */ - }; - }; - gpu { - polling-delay-passive = <1000>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; - - trips { - gpu_shutdown_trip { - temperature = <101000>; - hysteresis = <1000>; - type = "critical"; - }; - - gpu_throttle_trip: throttle-trip { - temperature = <99000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_throttle_trip>; - cooling-device = <&throttle_heavy 1 1>; - }; - }; - }; - pllx { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; - - trips { - pllx_shutdown_trip { - temperature = <105000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - /* - * There are currently no cooling maps, - * because there are no cooling devices. - */ - }; - }; - }; - - ahub@70300000 { - compatible = "nvidia,tegra124-ahub"; - reg = <0x0 0x70300000 0x0 0x200>, - <0x0 0x70300800 0x0 0x800>, - <0x0 0x70300200 0x0 0x600>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, - <&tegra_car TEGRA124_CLK_APBIF>; - clock-names = "d_audio", "apbif"; - resets = <&tegra_car 106>, /* d_audio */ - <&tegra_car 107>, /* apbif */ - <&tegra_car 30>, /* i2s0 */ - <&tegra_car 11>, /* i2s1 */ - <&tegra_car 18>, /* i2s2 */ - <&tegra_car 101>, /* i2s3 */ - <&tegra_car 102>, /* i2s4 */ - <&tegra_car 108>, /* dam0 */ - <&tegra_car 109>, /* dam1 */ - <&tegra_car 110>, /* dam2 */ - <&tegra_car 10>, /* spdif */ - <&tegra_car 153>, /* amx */ - <&tegra_car 185>, /* amx1 */ - <&tegra_car 154>, /* adx */ - <&tegra_car 180>, /* adx1 */ - <&tegra_car 186>, /* afc0 */ - <&tegra_car 187>, /* afc1 */ - <&tegra_car 188>, /* afc2 */ - <&tegra_car 189>, /* afc3 */ - <&tegra_car 190>, /* afc4 */ - <&tegra_car 191>; /* afc5 */ - reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", - "i2s3", "i2s4", "dam0", "dam1", "dam2", - "spdif", "amx", "amx1", "adx", "adx1", - "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; - dmas = <&apbdma 1>, <&apbdma 1>, - <&apbdma 2>, <&apbdma 2>, - <&apbdma 3>, <&apbdma 3>, - <&apbdma 4>, <&apbdma 4>, - <&apbdma 6>, <&apbdma 6>, - <&apbdma 7>, <&apbdma 7>, - <&apbdma 12>, <&apbdma 12>, - <&apbdma 13>, <&apbdma 13>, - <&apbdma 14>, <&apbdma 14>, - <&apbdma 29>, <&apbdma 29>; - dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", - "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", - "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", - "rx9", "tx9"; - ranges; - #address-cells = <2>; - #size-cells = <2>; - - tegra_i2s0: i2s@70301000 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301000 0x0 0x100>; - nvidia,ahub-cif-ids = <4 4>; - clocks = <&tegra_car TEGRA124_CLK_I2S0>; - clock-names = "i2s"; - resets = <&tegra_car 30>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s1: i2s@70301100 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301100 0x0 0x100>; - nvidia,ahub-cif-ids = <5 5>; - clocks = <&tegra_car TEGRA124_CLK_I2S1>; - clock-names = "i2s"; - resets = <&tegra_car 11>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s2: i2s@70301200 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301200 0x0 0x100>; - nvidia,ahub-cif-ids = <6 6>; - clocks = <&tegra_car TEGRA124_CLK_I2S2>; - clock-names = "i2s"; - resets = <&tegra_car 18>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s3: i2s@70301300 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301300 0x0 0x100>; - nvidia,ahub-cif-ids = <7 7>; - clocks = <&tegra_car TEGRA124_CLK_I2S3>; - clock-names = "i2s"; - resets = <&tegra_car 101>; - reset-names = "i2s"; - status = "disabled"; - }; - - tegra_i2s4: i2s@70301400 { - compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301400 0x0 0x100>; - nvidia,ahub-cif-ids = <8 8>; - clocks = <&tegra_car TEGRA124_CLK_I2S4>; - clock-names = "i2s"; - resets = <&tegra_car 102>; - reset-names = "i2s"; - status = "disabled"; - }; - }; - - usb@7d000000 { - compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x0 0x7d000000 0x0 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USBD>; - clock-names = "usb"; - resets = <&tegra_car 22>; - reset-names = "usb"; - nvidia,phy = <&phy1>; - status = "disabled"; - }; - - phy1: usb-phy@7d000000 { - compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x0 0x7d000000 0x0 0x4000>, - <0x0 0x7d000000 0x0 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USBD>, - <&tegra_car TEGRA124_CLK_PLL_U>, - <&tegra_car TEGRA124_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 22>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - #phy-cells = <0>; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - nvidia,has-utmi-pad-registers; - status = "disabled"; - }; - - usb@7d004000 { - compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x0 0x7d004000 0x0 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USB2>; - clock-names = "usb"; - resets = <&tegra_car 58>; - reset-names = "usb"; - nvidia,phy = <&phy2>; - status = "disabled"; - }; - - phy2: usb-phy@7d004000 { - compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x0 0x7d004000 0x0 0x4000>, - <0x0 0x7d000000 0x0 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USB2>, - <&tegra_car TEGRA124_CLK_PLL_U>, - <&tegra_car TEGRA124_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 58>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - #phy-cells = <0>; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - status = "disabled"; - }; - - usb@7d008000 { - compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x0 0x7d008000 0x0 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USB3>; - clock-names = "usb"; - resets = <&tegra_car 59>; - reset-names = "usb"; - nvidia,phy = <&phy3>; - status = "disabled"; - }; - - phy3: usb-phy@7d008000 { - compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x0 0x7d008000 0x0 0x4000>, - <0x0 0x7d000000 0x0 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA124_CLK_USB3>, - <&tegra_car TEGRA124_CLK_PLL_U>, - <&tegra_car TEGRA124_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 59>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - #phy-cells = <0>; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - status = "disabled"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "nvidia,tegra132-denver"; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "nvidia,tegra132-denver"; - reg = <1>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - interrupt-parent = <&gic>; - }; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts deleted file mode 100644 index c28d51cc5..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ /dev/null @@ -1,368 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include - -#include "tegra186-p3310.dtsi" - -/ { - model = "NVIDIA Jetson TX2 Developer Kit"; - compatible = "nvidia,p2771-0000", "nvidia,tegra186"; - - i2c@3160000 { - power-monitor@42 { - compatible = "ti,ina3221"; - reg = <0x42>; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - reg = <0x0>; - label = "VDD_MUX"; - shunt-resistor-micro-ohms = <20000>; - }; - - channel@1 { - reg = <0x1>; - label = "VDD_5V0_IO_SYS"; - shunt-resistor-micro-ohms = <5000>; - }; - - channel@2 { - reg = <0x2>; - label = "VDD_3V3_SYS"; - shunt-resistor-micro-ohms = <10000>; - }; - }; - - power-monitor@43 { - compatible = "ti,ina3221"; - reg = <0x43>; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - reg = <0x0>; - label = "VDD_3V3_IO_SLP"; - shunt-resistor-micro-ohms = <10000>; - }; - - channel@1 { - reg = <0x1>; - label = "VDD_1V8_IO"; - shunt-resistor-micro-ohms = <10000>; - }; - - channel@2 { - reg = <0x2>; - label = "VDD_M2_IN"; - shunt-resistor-micro-ohms = <10000>; - }; - }; - - exp1: gpio@74 { - compatible = "ti,tca9539"; - reg = <0x74>; - - interrupt-parent = <&gpio>; - interrupts = ; - - #gpio-cells = <2>; - gpio-controller; - - vcc-supply = <&vdd_3v3_sys>; - }; - - exp2: gpio@77 { - compatible = "ti,tca9539"; - reg = <0x77>; - - interrupt-parent = <&gpio>; - interrupts = ; - - #gpio-cells = <2>; - gpio-controller; - - vcc-supply = <&vdd_1v8>; - }; - }; - - /* SDMMC1 (SD/MMC) */ - mmc@3400000 { - status = "okay"; - - vmmc-supply = <&vdd_sd>; - }; - - hda@3510000 { - nvidia,model = "jetson-tx2-hda"; - status = "okay"; - }; - - padctl@3520000 { - status = "okay"; - - avdd-pll-erefeut-supply = <&vdd_1v8_pll>; - avdd-usb-supply = <&vdd_3v3_sys>; - vclamp-usb-supply = <&vdd_1v8>; - vddio-hsic-supply = <&gnd>; - - pads { - usb2 { - status = "okay"; - - lanes { - micro_b: usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - usb3 { - status = "okay"; - - lanes { - usb3-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb3-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb3-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "okay"; - mode = "otg"; - vbus-supply = <&vdd_usb0>; - usb-role-switch; - - connector { - compatible = "gpio-usb-b-connector", - "usb-b-connector"; - label = "micro-USB"; - type = "micro"; - vbus-gpios = <&gpio - TEGRA186_MAIN_GPIO(X, 7) - GPIO_ACTIVE_LOW>; - id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; - }; - - usb2-1 { - status = "okay"; - mode = "host"; - - vbus-supply = <&vdd_usb1>; - }; - - usb3-0 { - nvidia,usb2-companion = <1>; - vbus-supply = <&vdd_usb1>; - status = "okay"; - }; - }; - }; - - usb@3530000 { - status = "okay"; - - phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>, - <&{/padctl@3520000/pads/usb2/lanes/usb2-1}>, - <&{/padctl@3520000/pads/usb3/lanes/usb3-0}>; - phy-names = "usb2-0", "usb2-1", "usb3-0"; - }; - - usb@3550000 { - status = "okay"; - - phys = <µ_b>; - phy-names = "usb2-0"; - }; - - i2c@c250000 { - /* carrier board ID EEPROM */ - eeprom@57 { - compatible = "atmel,24c02"; - reg = <0x57>; - - label = "system"; - vcc-supply = <&vdd_1v8>; - address-width = <8>; - pagesize = <8>; - size = <256>; - read-only; - }; - }; - - pcie@10003000 { - status = "okay"; - - dvdd-pex-supply = <&vdd_pex>; - hvdd-pex-pll-supply = <&vdd_1v8>; - hvdd-pex-supply = <&vdd_1v8>; - vddio-pexctl-aud-supply = <&vdd_1v8>; - - pci@1,0 { - nvidia,num-lanes = <4>; - status = "okay"; - }; - - pci@2,0 { - nvidia,num-lanes = <0>; - status = "disabled"; - }; - - pci@3,0 { - nvidia,num-lanes = <1>; - status = "disabled"; - }; - }; - - host1x@13e00000 { - status = "okay"; - - dpaux@15040000 { - status = "okay"; - }; - - display-hub@15200000 { - status = "okay"; - }; - - dsi@15300000 { - status = "disabled"; - }; - - /* DP on E3320 */ - sor@15540000 { - status = "okay"; - - avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>; - vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>; - - nvidia,dpaux = <&dpaux>; - }; - - sor@15580000 { - status = "okay"; - - avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>; - vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>; - hdmi-supply = <&vdd_hdmi>; - - nvidia,ddc-i2c-bus = <&ddc>; - nvidia,hpd-gpio = <&gpio TEGRA186_MAIN_GPIO(P, 1) - GPIO_ACTIVE_LOW>; - }; - - dpaux@155c0000 { - status = "okay"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0) - GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - - volume-up { - label = "Volume Up"; - gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1) - GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <10>; - }; - - volume-down { - label = "Volume Down"; - gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2) - GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <10>; - }; - }; - - vdd_sd: regulator@100 { - compatible = "regulator-fixed"; - regulator-name = "SD_CARD_SW_PWR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio TEGRA186_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_hdmi: regulator@101 { - compatible = "regulator-fixed"; - regulator-name = "VDD_HDMI_5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&exp1 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb0: regulator@102 { - compatible = "regulator-fixed"; - regulator-name = "VDD_USB0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio TEGRA186_MAIN_GPIO(L, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb1: regulator@103 { - compatible = "regulator-fixed"; - regulator-name = "VDD_USB1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio TEGRA186_MAIN_GPIO(L, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&vdd_5v0_sys>; - }; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi deleted file mode 100644 index fd9177447..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ /dev/null @@ -1,425 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "tegra186.dtsi" - -#include - -/ { - model = "NVIDIA Jetson TX2"; - compatible = "nvidia,p3310", "nvidia,tegra186"; - - aliases { - ethernet0 = "/ethernet@2490000"; - i2c0 = "/bpmp/i2c"; - i2c1 = "/i2c@3160000"; - i2c2 = "/i2c@c240000"; - i2c3 = "/i2c@3180000"; - i2c4 = "/i2c@3190000"; - i2c5 = "/i2c@31c0000"; - i2c6 = "/i2c@c250000"; - i2c7 = "/i2c@31e0000"; - mmc0 = "/mmc@3460000"; - mmc1 = "/mmc@3400000"; - serial0 = &uarta; - }; - - chosen { - bootargs = "earlycon console=ttyS0,115200n8"; - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x2 0x00000000>; - }; - - ethernet@2490000 { - status = "okay"; - - phy-reset-gpios = <&gpio TEGRA186_MAIN_GPIO(M, 4) - GPIO_ACTIVE_LOW>; - phy-handle = <&phy>; - phy-mode = "rgmii"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - interrupt-parent = <&gpio>; - interrupts = ; - - #phy-cells = <0>; - }; - }; - }; - - memory-controller@2c00000 { - status = "okay"; - }; - - serial@3100000 { - status = "okay"; - }; - - i2c@3160000 { - status = "okay"; - - power-monitor@40 { - compatible = "ti,ina3221"; - reg = <0x40>; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - reg = <0x0>; - label = "VDD_SYS_GPU"; - shunt-resistor-micro-ohms = <10000>; - }; - - channel@1 { - reg = <0x1>; - label = "VDD_SYS_SOC"; - shunt-resistor-micro-ohms = <10000>; - }; - - channel@2 { - reg = <0x2>; - label = "VDD_3V8_WIFI"; - shunt-resistor-micro-ohms = <10000>; - }; - }; - - power-monitor@41 { - compatible = "ti,ina3221"; - reg = <0x41>; - #address-cells = <1>; - #size-cells = <0>; - - channel@0 { - reg = <0x0>; - label = "VDD_IN"; - shunt-resistor-micro-ohms = <5000>; - }; - - channel@1 { - reg = <0x1>; - label = "VDD_SYS_CPU"; - shunt-resistor-micro-ohms = <10000>; - }; - - channel@2 { - reg = <0x2>; - label = "VDD_5V0_DDR"; - shunt-resistor-micro-ohms = <10000>; - }; - }; - }; - - i2c@3180000 { - status = "okay"; - }; - - ddc: i2c@3190000 { - status = "okay"; - }; - - i2c@31c0000 { - status = "okay"; - }; - - i2c@31e0000 { - status = "okay"; - }; - - /* SDMMC1 (SD/MMC) */ - mmc@3400000 { - cd-gpios = <&gpio TEGRA186_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA186_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH>; - - vqmmc-supply = <&vddio_sdmmc1>; - }; - - /* SDMMC3 (SDIO) */ - mmc@3440000 { - status = "okay"; - }; - - /* SDMMC4 (eMMC) */ - mmc@3460000 { - status = "okay"; - bus-width = <8>; - non-removable; - - vqmmc-supply = <&vdd_1v8_ap>; - vmmc-supply = <&vdd_3v3_sys>; - }; - - hsp@3c00000 { - status = "okay"; - }; - - i2c@c240000 { - status = "okay"; - }; - - i2c@c250000 { - status = "okay"; - - /* module ID EEPROM */ - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - - label = "module"; - vcc-supply = <&vdd_1v8>; - address-width = <8>; - pagesize = <8>; - size = <256>; - read-only; - }; - }; - - rtc@c2a0000 { - status = "okay"; - }; - - pmc@c360000 { - nvidia,invert-interrupt; - }; - - cpus { - cpu@0 { - enable-method = "psci"; - }; - - cpu@1 { - enable-method = "psci"; - }; - - cpu@2 { - enable-method = "psci"; - }; - - cpu@3 { - enable-method = "psci"; - }; - - cpu@4 { - enable-method = "psci"; - }; - - cpu@5 { - enable-method = "psci"; - }; - }; - - bpmp { - i2c { - status = "okay"; - - pmic: pmic@3c { - compatible = "maxim,max77620"; - reg = <0x3c>; - - interrupt-parent = <&pmc>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - #interrupt-cells = <2>; - interrupt-controller; - - #gpio-cells = <2>; - gpio-controller; - - pinctrl-names = "default"; - pinctrl-0 = <&max77620_default>; - - max77620_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - }; - - gpio1 { - pins = "gpio1"; - function = "fps-out"; - maxim,active-fps-source = ; - }; - - gpio2 { - pins = "gpio2"; - function = "fps-out"; - maxim,active-fps-source = ; - }; - - gpio3 { - pins = "gpio3"; - function = "fps-out"; - maxim,active-fps-source = ; - }; - - gpio4 { - pins = "gpio4"; - function = "32k-out1"; - drive-push-pull = <1>; - }; - - gpio5 { - pins = "gpio5"; - function = "gpio"; - drive-push-pull = <0>; - }; - - gpio6 { - pins = "gpio6"; - function = "gpio"; - drive-push-pull = <1>; - }; - - gpio7 { - pins = "gpio7"; - function = "gpio"; - drive-push-pull = <0>; - }; - }; - - fps { - fps0 { - maxim,fps-event-source = ; - maxim,shutdown-fps-time-period-us = <640>; - }; - - fps1 { - maxim,fps-event-source = ; - maxim,shutdown-fps-time-period-us = <640>; - }; - - fps2 { - maxim,fps-event-source = ; - maxim,shutdown-fps-time-period-us = <640>; - }; - }; - - regulators { - in-sd0-supply = <&vdd_5v0_sys>; - in-sd1-supply = <&vdd_5v0_sys>; - in-sd2-supply = <&vdd_5v0_sys>; - in-sd3-supply = <&vdd_5v0_sys>; - - in-ldo0-1-supply = <&vdd_5v0_sys>; - in-ldo2-supply = <&vdd_5v0_sys>; - in-ldo3-5-supply = <&vdd_5v0_sys>; - in-ldo4-6-supply = <&vdd_1v8>; - in-ldo7-8-supply = <&avdd_dsi_csi>; - - sd0 { - regulator-name = "VDD_DDR_1V1_PMIC"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - }; - - avdd_dsi_csi: sd1 { - regulator-name = "AVDD_DSI_CSI_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vdd_1v8: sd2 { - regulator-name = "VDD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vdd_3v3_sys: sd3 { - regulator-name = "VDD_3V3_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_1v8_pll: ldo0 { - regulator-name = "VDD_1V8_AP_PLL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2 { - regulator-name = "VDDIO_3V3_AOHV"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vddio_sdmmc1: ldo3 { - regulator-name = "VDDIO_SDMMC1_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo4 { - regulator-name = "VDD_RTC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - vddio_sdmmc3: ldo5 { - regulator-name = "VDDIO_SDMMC3_AP"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - vdd_hdmi_1v05: ldo7 { - regulator-name = "VDD_HDMI_1V05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - vdd_pex: ldo8 { - regulator-name = "VDD_PEX_1V05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - }; - }; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - status = "okay"; - method = "smc"; - }; - - gnd: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "GND"; - regulator-min-microvolt = <0>; - regulator-max-microvolt = <0>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "VDD_5V0_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v8_ap: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "VDD_1V8_AP"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&vdd_1v8>; - }; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi deleted file mode 100644 index eec6418ec..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ /dev/null @@ -1,1744 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "nvidia,tegra186"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - misc@100000 { - compatible = "nvidia,tegra186-misc"; - reg = <0x0 0x00100000 0x0 0xf000>, - <0x0 0x0010f000 0x0 0x1000>; - }; - - gpio: gpio@2200000 { - compatible = "nvidia,tegra186-gpio"; - reg-names = "security", "gpio"; - reg = <0x0 0x2200000 0x0 0x10000>, - <0x0 0x2210000 0x0 0x10000>; - interrupts = , - , - , - , - , - ; - #interrupt-cells = <2>; - interrupt-controller; - #gpio-cells = <2>; - gpio-controller; - }; - - ethernet@2490000 { - compatible = "nvidia,tegra186-eqos", - "snps,dwc-qos-ethernet-4.10"; - reg = <0x0 0x02490000 0x0 0x10000>; - interrupts = , /* common */ - , /* power */ - , /* rx0 */ - , /* tx0 */ - , /* rx1 */ - , /* tx1 */ - , /* rx2 */ - , /* tx2 */ - , /* rx3 */ - ; /* tx3 */ - clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, - <&bpmp TEGRA186_CLK_EQOS_AXI>, - <&bpmp TEGRA186_CLK_EQOS_RX>, - <&bpmp TEGRA186_CLK_EQOS_TX>, - <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; - clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; - resets = <&bpmp TEGRA186_RESET_EQOS>; - reset-names = "eqos"; - interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, - <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; - interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA186_SID_EQOS>; - status = "disabled"; - - snps,write-requests = <1>; - snps,read-requests = <3>; - snps,burst-map = <0x7>; - snps,txpbl = <32>; - snps,rxpbl = <8>; - }; - - aconnect { - compatible = "nvidia,tegra186-aconnect", - "nvidia,tegra210-aconnect"; - clocks = <&bpmp TEGRA186_CLK_APE>, - <&bpmp TEGRA186_CLK_APB2APE>; - clock-names = "ape", "apb2ape"; - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x02900000 0x0 0x02900000 0x200000>; - status = "disabled"; - - adma: dma-controller@2930000 { - compatible = "nvidia,tegra186-adma"; - reg = <0x02930000 0x20000>; - interrupt-parent = <&agic>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - #dma-cells = <1>; - clocks = <&bpmp TEGRA186_CLK_AHUB>; - clock-names = "d_audio"; - status = "disabled"; - }; - - agic: interrupt-controller@2a40000 { - compatible = "nvidia,tegra186-agic", - "nvidia,tegra210-agic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x02a41000 0x1000>, - <0x02a42000 0x2000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_APE>; - clock-names = "clk"; - status = "disabled"; - }; - - tegra_ahub: ahub@2900800 { - compatible = "nvidia,tegra186-ahub"; - reg = <0x02900800 0x800>; - clocks = <&bpmp TEGRA186_CLK_AHUB>; - clock-names = "ahub"; - assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x02900800 0x02900800 0x11800>; - status = "disabled"; - - tegra_admaif: admaif@290f000 { - compatible = "nvidia,tegra186-admaif"; - reg = <0x0290f000 0x1000>; - dmas = <&adma 1>, <&adma 1>, - <&adma 2>, <&adma 2>, - <&adma 3>, <&adma 3>, - <&adma 4>, <&adma 4>, - <&adma 5>, <&adma 5>, - <&adma 6>, <&adma 6>, - <&adma 7>, <&adma 7>, - <&adma 8>, <&adma 8>, - <&adma 9>, <&adma 9>, - <&adma 10>, <&adma 10>, - <&adma 11>, <&adma 11>, - <&adma 12>, <&adma 12>, - <&adma 13>, <&adma 13>, - <&adma 14>, <&adma 14>, - <&adma 15>, <&adma 15>, - <&adma 16>, <&adma 16>, - <&adma 17>, <&adma 17>, - <&adma 18>, <&adma 18>, - <&adma 19>, <&adma 19>, - <&adma 20>, <&adma 20>; - dma-names = "rx1", "tx1", - "rx2", "tx2", - "rx3", "tx3", - "rx4", "tx4", - "rx5", "tx5", - "rx6", "tx6", - "rx7", "tx7", - "rx8", "tx8", - "rx9", "tx9", - "rx10", "tx10", - "rx11", "tx11", - "rx12", "tx12", - "rx13", "tx13", - "rx14", "tx14", - "rx15", "tx15", - "rx16", "tx16", - "rx17", "tx17", - "rx18", "tx18", - "rx19", "tx19", - "rx20", "tx20"; - status = "disabled"; - }; - - tegra_i2s1: i2s@2901000 { - compatible = "nvidia,tegra186-i2s", - "nvidia,tegra210-i2s"; - reg = <0x2901000 0x100>; - clocks = <&bpmp TEGRA186_CLK_I2S1>, - <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; - clock-names = "i2s", "sync_input"; - assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <1536000>; - sound-name-prefix = "I2S1"; - status = "disabled"; - }; - - tegra_i2s2: i2s@2901100 { - compatible = "nvidia,tegra186-i2s", - "nvidia,tegra210-i2s"; - reg = <0x2901100 0x100>; - clocks = <&bpmp TEGRA186_CLK_I2S2>, - <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; - clock-names = "i2s", "sync_input"; - assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <1536000>; - sound-name-prefix = "I2S2"; - status = "disabled"; - }; - - tegra_i2s3: i2s@2901200 { - compatible = "nvidia,tegra186-i2s", - "nvidia,tegra210-i2s"; - reg = <0x2901200 0x100>; - clocks = <&bpmp TEGRA186_CLK_I2S3>, - <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; - clock-names = "i2s", "sync_input"; - assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <1536000>; - sound-name-prefix = "I2S3"; - status = "disabled"; - }; - - tegra_i2s4: i2s@2901300 { - compatible = "nvidia,tegra186-i2s", - "nvidia,tegra210-i2s"; - reg = <0x2901300 0x100>; - clocks = <&bpmp TEGRA186_CLK_I2S4>, - <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; - clock-names = "i2s", "sync_input"; - assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <1536000>; - sound-name-prefix = "I2S4"; - status = "disabled"; - }; - - tegra_i2s5: i2s@2901400 { - compatible = "nvidia,tegra186-i2s", - "nvidia,tegra210-i2s"; - reg = <0x2901400 0x100>; - clocks = <&bpmp TEGRA186_CLK_I2S5>, - <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; - clock-names = "i2s", "sync_input"; - assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <1536000>; - sound-name-prefix = "I2S5"; - status = "disabled"; - }; - - tegra_i2s6: i2s@2901500 { - compatible = "nvidia,tegra186-i2s", - "nvidia,tegra210-i2s"; - reg = <0x2901500 0x100>; - clocks = <&bpmp TEGRA186_CLK_I2S6>, - <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; - clock-names = "i2s", "sync_input"; - assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <1536000>; - sound-name-prefix = "I2S6"; - status = "disabled"; - }; - - tegra_dmic1: dmic@2904000 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x2904000 0x100>; - clocks = <&bpmp TEGRA186_CLK_DMIC1>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC1"; - status = "disabled"; - }; - - tegra_dmic2: dmic@2904100 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x2904100 0x100>; - clocks = <&bpmp TEGRA186_CLK_DMIC2>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC2"; - status = "disabled"; - }; - - tegra_dmic3: dmic@2904200 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x2904200 0x100>; - clocks = <&bpmp TEGRA186_CLK_DMIC3>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC3"; - status = "disabled"; - }; - - tegra_dmic4: dmic@2904300 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x2904300 0x100>; - clocks = <&bpmp TEGRA186_CLK_DMIC4>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC4"; - status = "disabled"; - }; - - tegra_dspk1: dspk@2905000 { - compatible = "nvidia,tegra186-dspk"; - reg = <0x2905000 0x100>; - clocks = <&bpmp TEGRA186_CLK_DSPK1>; - clock-names = "dspk"; - assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <12288000>; - sound-name-prefix = "DSPK1"; - status = "disabled"; - }; - - tegra_dspk2: dspk@2905100 { - compatible = "nvidia,tegra186-dspk"; - reg = <0x2905100 0x100>; - clocks = <&bpmp TEGRA186_CLK_DSPK2>; - clock-names = "dspk"; - assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <12288000>; - sound-name-prefix = "DSPK2"; - status = "disabled"; - }; - }; - }; - - mc: memory-controller@2c00000 { - compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; - interrupts = ; - status = "disabled"; - - #interconnect-cells = <1>; - #address-cells = <2>; - #size-cells = <2>; - - ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; - - /* - * Memory clients have access to all 40 bits that the memory - * controller can address. - */ - dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; - - emc: external-memory-controller@2c60000 { - compatible = "nvidia,tegra186-emc"; - reg = <0x0 0x02c60000 0x0 0x50000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_EMC>; - clock-names = "emc"; - - #interconnect-cells = <0>; - - nvidia,bpmp = <&bpmp>; - }; - }; - - uarta: serial@3100000 { - compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x03100000 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_UARTA>; - clock-names = "serial"; - resets = <&bpmp TEGRA186_RESET_UARTA>; - reset-names = "serial"; - status = "disabled"; - }; - - uartb: serial@3110000 { - compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x03110000 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_UARTB>; - clock-names = "serial"; - resets = <&bpmp TEGRA186_RESET_UARTB>; - reset-names = "serial"; - status = "disabled"; - }; - - uartd: serial@3130000 { - compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x03130000 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_UARTD>; - clock-names = "serial"; - resets = <&bpmp TEGRA186_RESET_UARTD>; - reset-names = "serial"; - status = "disabled"; - }; - - uarte: serial@3140000 { - compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x03140000 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_UARTE>; - clock-names = "serial"; - resets = <&bpmp TEGRA186_RESET_UARTE>; - reset-names = "serial"; - status = "disabled"; - }; - - uartf: serial@3150000 { - compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x03150000 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_UARTF>; - clock-names = "serial"; - resets = <&bpmp TEGRA186_RESET_UARTF>; - reset-names = "serial"; - status = "disabled"; - }; - - gen1_i2c: i2c@3160000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; - reg = <0x0 0x03160000 0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA186_CLK_I2C1>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA186_RESET_I2C1>; - reset-names = "i2c"; - status = "disabled"; - }; - - cam_i2c: i2c@3180000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; - reg = <0x0 0x03180000 0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA186_CLK_I2C3>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA186_RESET_I2C3>; - reset-names = "i2c"; - status = "disabled"; - }; - - /* shares pads with dpaux1 */ - dp_aux_ch1_i2c: i2c@3190000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; - reg = <0x0 0x03190000 0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA186_CLK_I2C4>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA186_RESET_I2C4>; - reset-names = "i2c"; - pinctrl-names = "default", "idle"; - pinctrl-0 = <&state_dpaux1_i2c>; - pinctrl-1 = <&state_dpaux1_off>; - status = "disabled"; - }; - - /* controlled by BPMP, should not be enabled */ - pwr_i2c: i2c@31a0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; - reg = <0x0 0x031a0000 0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA186_CLK_I2C5>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA186_RESET_I2C5>; - reset-names = "i2c"; - status = "disabled"; - }; - - /* shares pads with dpaux0 */ - dp_aux_ch0_i2c: i2c@31b0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; - reg = <0x0 0x031b0000 0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA186_CLK_I2C6>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA186_RESET_I2C6>; - reset-names = "i2c"; - pinctrl-names = "default", "idle"; - pinctrl-0 = <&state_dpaux_i2c>; - pinctrl-1 = <&state_dpaux_off>; - status = "disabled"; - }; - - gen7_i2c: i2c@31c0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; - reg = <0x0 0x031c0000 0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA186_CLK_I2C7>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA186_RESET_I2C7>; - reset-names = "i2c"; - status = "disabled"; - }; - - gen9_i2c: i2c@31e0000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; - reg = <0x0 0x031e0000 0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA186_CLK_I2C9>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA186_RESET_I2C9>; - reset-names = "i2c"; - status = "disabled"; - }; - - sdmmc1: mmc@3400000 { - compatible = "nvidia,tegra186-sdhci"; - reg = <0x0 0x03400000 0x0 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SDMMC1>, - <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; - clock-names = "sdhci", "tmclk"; - resets = <&bpmp TEGRA186_RESET_SDMMC1>; - reset-names = "sdhci"; - interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, - <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; - interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA186_SID_SDMMC1>; - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; - pinctrl-0 = <&sdmmc1_3v3>; - pinctrl-1 = <&sdmmc1_1v8>; - nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; - nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; - nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; - nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; - nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; - nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; - nvidia,default-tap = <0x5>; - nvidia,default-trim = <0xb>; - assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, - <&bpmp TEGRA186_CLK_PLLP_OUT0>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; - status = "disabled"; - }; - - sdmmc2: mmc@3420000 { - compatible = "nvidia,tegra186-sdhci"; - reg = <0x0 0x03420000 0x0 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SDMMC2>, - <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; - clock-names = "sdhci", "tmclk"; - resets = <&bpmp TEGRA186_RESET_SDMMC2>; - reset-names = "sdhci"; - interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, - <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; - interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA186_SID_SDMMC2>; - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; - pinctrl-0 = <&sdmmc2_3v3>; - pinctrl-1 = <&sdmmc2_1v8>; - nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; - nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; - nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; - nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; - nvidia,default-tap = <0x5>; - nvidia,default-trim = <0xb>; - status = "disabled"; - }; - - sdmmc3: mmc@3440000 { - compatible = "nvidia,tegra186-sdhci"; - reg = <0x0 0x03440000 0x0 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SDMMC3>, - <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; - clock-names = "sdhci", "tmclk"; - resets = <&bpmp TEGRA186_RESET_SDMMC3>; - reset-names = "sdhci"; - interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, - <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; - interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA186_SID_SDMMC3>; - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; - pinctrl-0 = <&sdmmc3_3v3>; - pinctrl-1 = <&sdmmc3_1v8>; - nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; - nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; - nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; - nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; - nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; - nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; - nvidia,default-tap = <0x5>; - nvidia,default-trim = <0xb>; - status = "disabled"; - }; - - sdmmc4: mmc@3460000 { - compatible = "nvidia,tegra186-sdhci"; - reg = <0x0 0x03460000 0x0 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SDMMC4>, - <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; - clock-names = "sdhci", "tmclk"; - assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, - <&bpmp TEGRA186_CLK_PLLC4_VCO>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; - resets = <&bpmp TEGRA186_RESET_SDMMC4>; - reset-names = "sdhci"; - interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, - <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; - interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA186_SID_SDMMC4>; - nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; - nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; - nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; - nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; - nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; - nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; - nvidia,default-tap = <0x9>; - nvidia,default-trim = <0x5>; - nvidia,dqs-trim = <63>; - mmc-hs400-1_8v; - supports-cqe; - status = "disabled"; - }; - - hda@3510000 { - compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; - reg = <0x0 0x03510000 0x0 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_HDA>, - <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, - <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; - clock-names = "hda", "hda2hdmi", "hda2codec_2x"; - resets = <&bpmp TEGRA186_RESET_HDA>, - <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, - <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; - reset-names = "hda", "hda2hdmi", "hda2codec_2x"; - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; - interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, - <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; - interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA186_SID_HDA>; - status = "disabled"; - }; - - padctl: padctl@3520000 { - compatible = "nvidia,tegra186-xusb-padctl"; - reg = <0x0 0x03520000 0x0 0x1000>, - <0x0 0x03540000 0x0 0x1000>; - reg-names = "padctl", "ao"; - - resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; - reset-names = "padctl"; - - status = "disabled"; - - pads { - usb2 { - clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; - clock-names = "trk"; - status = "disabled"; - - lanes { - usb2-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-2 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - hsic { - clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; - clock-names = "trk"; - status = "disabled"; - - lanes { - hsic-0 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - usb3 { - status = "disabled"; - - lanes { - usb3-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb3-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb3-2 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "disabled"; - }; - - usb2-1 { - status = "disabled"; - }; - - usb2-2 { - status = "disabled"; - }; - - hsic-0 { - status = "disabled"; - }; - - usb3-0 { - status = "disabled"; - }; - - usb3-1 { - status = "disabled"; - }; - - usb3-2 { - status = "disabled"; - }; - }; - }; - - usb@3530000 { - compatible = "nvidia,tegra186-xusb"; - reg = <0x0 0x03530000 0x0 0x8000>, - <0x0 0x03538000 0x0 0x1000>; - reg-names = "hcd", "fpci"; - interrupts = , - ; - clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, - <&bpmp TEGRA186_CLK_XUSB_FALCON>, - <&bpmp TEGRA186_CLK_XUSB_SS>, - <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, - <&bpmp TEGRA186_CLK_CLK_M>, - <&bpmp TEGRA186_CLK_XUSB_FS>, - <&bpmp TEGRA186_CLK_PLLU>, - <&bpmp TEGRA186_CLK_CLK_M>, - <&bpmp TEGRA186_CLK_PLLE>; - clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", - "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", - "pll_u_480m", "clk_m", "pll_e"; - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, - <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; - power-domain-names = "xusb_host", "xusb_ss"; - interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, - <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; - interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA186_SID_XUSB_HOST>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - nvidia,xusb-padctl = <&padctl>; - }; - - usb@3550000 { - compatible = "nvidia,tegra186-xudc"; - reg = <0x0 0x03550000 0x0 0x8000>, - <0x0 0x03558000 0x0 0x1000>; - reg-names = "base", "fpci"; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, - <&bpmp TEGRA186_CLK_XUSB_SS>, - <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, - <&bpmp TEGRA186_CLK_XUSB_FS>; - clock-names = "dev", "ss", "ss_src", "fs_src"; - iommus = <&smmu TEGRA186_SID_XUSB_DEV>; - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, - <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; - power-domain-names = "dev", "ss"; - nvidia,xusb-padctl = <&padctl>; - status = "disabled"; - }; - - fuse@3820000 { - compatible = "nvidia,tegra186-efuse"; - reg = <0x0 0x03820000 0x0 0x10000>; - clocks = <&bpmp TEGRA186_CLK_FUSE>; - clock-names = "fuse"; - }; - - gic: interrupt-controller@3881000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x03881000 0x0 0x1000>, - <0x0 0x03882000 0x0 0x2000>; - interrupts = ; - interrupt-parent = <&gic>; - }; - - cec@3960000 { - compatible = "nvidia,tegra186-cec"; - reg = <0x0 0x03960000 0x0 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_CEC>; - clock-names = "cec"; - status = "disabled"; - }; - - hsp_top0: hsp@3c00000 { - compatible = "nvidia,tegra186-hsp"; - reg = <0x0 0x03c00000 0x0 0xa0000>; - interrupts = ; - interrupt-names = "doorbell"; - #mbox-cells = <2>; - status = "disabled"; - }; - - gen2_i2c: i2c@c240000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; - reg = <0x0 0x0c240000 0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA186_CLK_I2C2>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA186_RESET_I2C2>; - reset-names = "i2c"; - status = "disabled"; - }; - - gen8_i2c: i2c@c250000 { - compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; - reg = <0x0 0x0c250000 0x0 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA186_CLK_I2C8>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA186_RESET_I2C8>; - reset-names = "i2c"; - status = "disabled"; - }; - - uartc: serial@c280000 { - compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x0c280000 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_UARTC>; - clock-names = "serial"; - resets = <&bpmp TEGRA186_RESET_UARTC>; - reset-names = "serial"; - status = "disabled"; - }; - - uartg: serial@c290000 { - compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x0c290000 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_UARTG>; - clock-names = "serial"; - resets = <&bpmp TEGRA186_RESET_UARTG>; - reset-names = "serial"; - status = "disabled"; - }; - - rtc: rtc@c2a0000 { - compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; - reg = <0 0x0c2a0000 0 0x10000>; - interrupt-parent = <&pmc>; - interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&bpmp TEGRA186_CLK_CLK_32K>; - clock-names = "rtc"; - status = "disabled"; - }; - - gpio_aon: gpio@c2f0000 { - compatible = "nvidia,tegra186-gpio-aon"; - reg-names = "security", "gpio"; - reg = <0x0 0xc2f0000 0x0 0x1000>, - <0x0 0xc2f1000 0x0 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pmc: pmc@c360000 { - compatible = "nvidia,tegra186-pmc"; - reg = <0 0x0c360000 0 0x10000>, - <0 0x0c370000 0 0x10000>, - <0 0x0c380000 0 0x10000>, - <0 0x0c390000 0 0x10000>; - reg-names = "pmc", "wake", "aotag", "scratch"; - - #interrupt-cells = <2>; - interrupt-controller; - - sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1-hv"; - power-source = ; - }; - - sdmmc1_1v8: sdmmc1-1v8 { - pins = "sdmmc1-hv"; - power-source = ; - }; - - sdmmc2_3v3: sdmmc2-3v3 { - pins = "sdmmc2-hv"; - power-source = ; - }; - - sdmmc2_1v8: sdmmc2-1v8 { - pins = "sdmmc2-hv"; - power-source = ; - }; - - sdmmc3_3v3: sdmmc3-3v3 { - pins = "sdmmc3-hv"; - power-source = ; - }; - - sdmmc3_1v8: sdmmc3-1v8 { - pins = "sdmmc3-hv"; - power-source = ; - }; - }; - - ccplex@e000000 { - compatible = "nvidia,tegra186-ccplex-cluster"; - reg = <0x0 0x0e000000 0x0 0x400000>; - - nvidia,bpmp = <&bpmp>; - }; - - pcie@10003000 { - compatible = "nvidia,tegra186-pcie"; - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; - device_type = "pci"; - reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ - <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ - <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ - reg-names = "pads", "afi", "cs"; - - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - - bus-range = <0x00 0xff>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ - <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ - <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ - <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ - <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ - <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ - - clocks = <&bpmp TEGRA186_CLK_PCIE>, - <&bpmp TEGRA186_CLK_AFI>, - <&bpmp TEGRA186_CLK_PLLE>; - clock-names = "pex", "afi", "pll_e"; - - resets = <&bpmp TEGRA186_RESET_PCIE>, - <&bpmp TEGRA186_RESET_AFI>, - <&bpmp TEGRA186_RESET_PCIEXCLK>; - reset-names = "pex", "afi", "pcie_x"; - - interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, - <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; - interconnect-names = "dma-mem", "write"; - - iommus = <&smmu TEGRA186_SID_AFI>; - iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; - iommu-map-mask = <0x0>; - - status = "disabled"; - - pci@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; - reg = <0x000800 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <2>; - }; - - pci@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; - reg = <0x001000 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <1>; - }; - - pci@3,0 { - device_type = "pci"; - assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; - reg = <0x001800 0 0 0 0>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <1>; - }; - }; - - smmu: iommu@12000000 { - compatible = "arm,mmu-500"; - reg = <0 0x12000000 0 0x800000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - stream-match-mask = <0x7f80>; - #global-interrupts = <1>; - #iommu-cells = <1>; - }; - - host1x@13e00000 { - compatible = "nvidia,tegra186-host1x"; - reg = <0x0 0x13e00000 0x0 0x10000>, - <0x0 0x13e10000 0x0 0x10000>; - reg-names = "hypervisor", "vm"; - interrupts = , - ; - interrupt-names = "syncpt", "host1x"; - clocks = <&bpmp TEGRA186_CLK_HOST1X>; - clock-names = "host1x"; - resets = <&bpmp TEGRA186_RESET_HOST1X>; - reset-names = "host1x"; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x15000000 0x0 0x15000000 0x01000000>; - - interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; - interconnect-names = "dma-mem"; - - iommus = <&smmu TEGRA186_SID_HOST1X>; - - dpaux1: dpaux@15040000 { - compatible = "nvidia,tegra186-dpaux"; - reg = <0x15040000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_DPAUX1>, - <&bpmp TEGRA186_CLK_PLLDP>; - clock-names = "dpaux", "parent"; - resets = <&bpmp TEGRA186_RESET_DPAUX1>; - reset-names = "dpaux"; - status = "disabled"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; - - state_dpaux1_aux: pinmux-aux { - groups = "dpaux-io"; - function = "aux"; - }; - - state_dpaux1_i2c: pinmux-i2c { - groups = "dpaux-io"; - function = "i2c"; - }; - - state_dpaux1_off: pinmux-off { - groups = "dpaux-io"; - function = "off"; - }; - - i2c-bus { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - display-hub@15200000 { - compatible = "nvidia,tegra186-display"; - reg = <0x15200000 0x00040000>; - resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, - <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, - <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, - <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, - <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, - <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, - <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; - reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", - "wgrp3", "wgrp4", "wgrp5"; - clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, - <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, - <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; - clock-names = "disp", "dsc", "hub"; - status = "disabled"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x15200000 0x15200000 0x40000>; - - display@15200000 { - compatible = "nvidia,tegra186-dc"; - reg = <0x15200000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; - clock-names = "dc"; - resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; - reset-names = "dc"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; - interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, - <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; - interconnect-names = "dma-mem", "read-1"; - iommus = <&smmu TEGRA186_SID_NVDISPLAY>; - - nvidia,outputs = <&dsia &dsib &sor0 &sor1>; - nvidia,head = <0>; - }; - - display@15210000 { - compatible = "nvidia,tegra186-dc"; - reg = <0x15210000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; - clock-names = "dc"; - resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; - reset-names = "dc"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; - interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, - <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; - interconnect-names = "dma-mem", "read-1"; - iommus = <&smmu TEGRA186_SID_NVDISPLAY>; - - nvidia,outputs = <&dsia &dsib &sor0 &sor1>; - nvidia,head = <1>; - }; - - display@15220000 { - compatible = "nvidia,tegra186-dc"; - reg = <0x15220000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; - clock-names = "dc"; - resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; - reset-names = "dc"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; - interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, - <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; - interconnect-names = "dma-mem", "read-1"; - iommus = <&smmu TEGRA186_SID_NVDISPLAY>; - - nvidia,outputs = <&sor0 &sor1>; - nvidia,head = <2>; - }; - }; - - dsia: dsi@15300000 { - compatible = "nvidia,tegra186-dsi"; - reg = <0x15300000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_DSI>, - <&bpmp TEGRA186_CLK_DSIA_LP>, - <&bpmp TEGRA186_CLK_PLLD>; - clock-names = "dsi", "lp", "parent"; - resets = <&bpmp TEGRA186_RESET_DSI>; - reset-names = "dsi"; - status = "disabled"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; - }; - - vic@15340000 { - compatible = "nvidia,tegra186-vic"; - reg = <0x15340000 0x40000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_VIC>; - clock-names = "vic"; - resets = <&bpmp TEGRA186_RESET_VIC>; - reset-names = "vic"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; - interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, - <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; - interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA186_SID_VIC>; - }; - - dsib: dsi@15400000 { - compatible = "nvidia,tegra186-dsi"; - reg = <0x15400000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_DSIB>, - <&bpmp TEGRA186_CLK_DSIB_LP>, - <&bpmp TEGRA186_CLK_PLLD>; - clock-names = "dsi", "lp", "parent"; - resets = <&bpmp TEGRA186_RESET_DSIB>; - reset-names = "dsi"; - status = "disabled"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; - }; - - sor0: sor@15540000 { - compatible = "nvidia,tegra186-sor"; - reg = <0x15540000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SOR0>, - <&bpmp TEGRA186_CLK_SOR0_OUT>, - <&bpmp TEGRA186_CLK_PLLD2>, - <&bpmp TEGRA186_CLK_PLLDP>, - <&bpmp TEGRA186_CLK_SOR_SAFE>, - <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; - clock-names = "sor", "out", "parent", "dp", "safe", - "pad"; - resets = <&bpmp TEGRA186_RESET_SOR0>; - reset-names = "sor"; - pinctrl-0 = <&state_dpaux_aux>; - pinctrl-1 = <&state_dpaux_i2c>; - pinctrl-2 = <&state_dpaux_off>; - pinctrl-names = "aux", "i2c", "off"; - status = "disabled"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; - nvidia,interface = <0>; - }; - - sor1: sor@15580000 { - compatible = "nvidia,tegra186-sor"; - reg = <0x15580000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_SOR1>, - <&bpmp TEGRA186_CLK_SOR1_OUT>, - <&bpmp TEGRA186_CLK_PLLD3>, - <&bpmp TEGRA186_CLK_PLLDP>, - <&bpmp TEGRA186_CLK_SOR_SAFE>, - <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; - clock-names = "sor", "out", "parent", "dp", "safe", - "pad"; - resets = <&bpmp TEGRA186_RESET_SOR1>; - reset-names = "sor"; - pinctrl-0 = <&state_dpaux1_aux>; - pinctrl-1 = <&state_dpaux1_i2c>; - pinctrl-2 = <&state_dpaux1_off>; - pinctrl-names = "aux", "i2c", "off"; - status = "disabled"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; - nvidia,interface = <1>; - }; - - dpaux: dpaux@155c0000 { - compatible = "nvidia,tegra186-dpaux"; - reg = <0x155c0000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_DPAUX>, - <&bpmp TEGRA186_CLK_PLLDP>; - clock-names = "dpaux", "parent"; - resets = <&bpmp TEGRA186_RESET_DPAUX>; - reset-names = "dpaux"; - status = "disabled"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; - - state_dpaux_aux: pinmux-aux { - groups = "dpaux-io"; - function = "aux"; - }; - - state_dpaux_i2c: pinmux-i2c { - groups = "dpaux-io"; - function = "i2c"; - }; - - state_dpaux_off: pinmux-off { - groups = "dpaux-io"; - function = "off"; - }; - - i2c-bus { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - padctl@15880000 { - compatible = "nvidia,tegra186-dsi-padctl"; - reg = <0x15880000 0x10000>; - resets = <&bpmp TEGRA186_RESET_DSI>; - reset-names = "dsi"; - status = "disabled"; - }; - - dsic: dsi@15900000 { - compatible = "nvidia,tegra186-dsi"; - reg = <0x15900000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_DSIC>, - <&bpmp TEGRA186_CLK_DSIC_LP>, - <&bpmp TEGRA186_CLK_PLLD>; - clock-names = "dsi", "lp", "parent"; - resets = <&bpmp TEGRA186_RESET_DSIC>; - reset-names = "dsi"; - status = "disabled"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; - }; - - dsid: dsi@15940000 { - compatible = "nvidia,tegra186-dsi"; - reg = <0x15940000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA186_CLK_DSID>, - <&bpmp TEGRA186_CLK_DSID_LP>, - <&bpmp TEGRA186_CLK_PLLD>; - clock-names = "dsi", "lp", "parent"; - resets = <&bpmp TEGRA186_RESET_DSID>; - reset-names = "dsi"; - status = "disabled"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; - }; - }; - - gpu@17000000 { - compatible = "nvidia,gp10b"; - reg = <0x0 0x17000000 0x0 0x1000000>, - <0x0 0x18000000 0x0 0x1000000>; - interrupts = , - ; - interrupt-names = "stall", "nonstall"; - - clocks = <&bpmp TEGRA186_CLK_GPCCLK>, - <&bpmp TEGRA186_CLK_GPU>; - clock-names = "gpu", "pwr"; - resets = <&bpmp TEGRA186_RESET_GPU>; - reset-names = "gpu"; - status = "disabled"; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; - interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, - <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, - <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, - <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; - interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; - }; - - sram@30000000 { - compatible = "nvidia,tegra186-sysram", "mmio-sram"; - reg = <0x0 0x30000000 0x0 0x50000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x30000000 0x50000>; - - cpu_bpmp_tx: sram@4e000 { - reg = <0x4e000 0x1000>; - label = "cpu-bpmp-tx"; - pool; - }; - - cpu_bpmp_rx: sram@4f000 { - reg = <0x4f000 0x1000>; - label = "cpu-bpmp-rx"; - pool; - }; - }; - - bpmp: bpmp { - compatible = "nvidia,tegra186-bpmp"; - interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, - <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, - <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, - <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; - interconnect-names = "read", "write", "dma-mem", "dma-write"; - iommus = <&smmu TEGRA186_SID_BPMP>; - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB - TEGRA_HSP_DB_MASTER_BPMP>; - shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - - bpmp_i2c: i2c { - compatible = "nvidia,tegra186-bpmp-i2c"; - nvidia,bpmp-bus-id = <5>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - bpmp_thermal: thermal { - compatible = "nvidia,tegra186-bpmp-thermal"; - #thermal-sensor-cells = <1>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "nvidia,tegra186-denver"; - device_type = "cpu"; - i-cache-size = <0x20000>; - i-cache-line-size = <64>; - i-cache-sets = <512>; - d-cache-size = <0x10000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_DENVER>; - reg = <0x000>; - }; - - cpu@1 { - compatible = "nvidia,tegra186-denver"; - device_type = "cpu"; - i-cache-size = <0x20000>; - i-cache-line-size = <64>; - i-cache-sets = <512>; - d-cache-size = <0x10000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_DENVER>; - reg = <0x001>; - }; - - cpu@2 { - compatible = "arm,cortex-a57"; - device_type = "cpu"; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_A57>; - reg = <0x100>; - }; - - cpu@3 { - compatible = "arm,cortex-a57"; - device_type = "cpu"; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_A57>; - reg = <0x101>; - }; - - cpu@4 { - compatible = "arm,cortex-a57"; - device_type = "cpu"; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_A57>; - reg = <0x102>; - }; - - cpu@5 { - compatible = "arm,cortex-a57"; - device_type = "cpu"; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_A57>; - reg = <0x103>; - }; - - L2_DENVER: l2-cache0 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - cache-size = <0x200000>; - cache-line-size = <64>; - cache-sets = <2048>; - }; - - L2_A57: l2-cache1 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - cache-size = <0x200000>; - cache-line-size = <64>; - cache-sets = <2048>; - }; - }; - - thermal-zones { - a57 { - polling-delay = <0>; - polling-delay-passive = <1000>; - - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; - - trips { - critical { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - - denver { - polling-delay = <0>; - polling-delay-passive = <1000>; - - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; - - trips { - critical { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - - gpu { - polling-delay = <0>; - polling-delay-passive = <1000>; - - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; - - trips { - critical { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - - pll { - polling-delay = <0>; - polling-delay-passive = <1000>; - - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; - - trips { - critical { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - - always_on { - polling-delay = <0>; - polling-delay-passive = <1000>; - - thermal-sensors = - <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; - - trips { - critical { - temperature = <101000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - interrupt-parent = <&gic>; - always-on; - }; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi deleted file mode 100644 index d71b7a114..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ /dev/null @@ -1,357 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "tegra194.dtsi" - -#include - -/ { - model = "NVIDIA Jetson AGX Xavier"; - compatible = "nvidia,p2888", "nvidia,tegra194"; - - aliases { - ethernet0 = "/bus@0/ethernet@2490000"; - i2c0 = "/bpmp/i2c"; - i2c1 = "/bus@0/i2c@3160000"; - i2c2 = "/bus@0/i2c@c240000"; - i2c3 = "/bus@0/i2c@3180000"; - i2c4 = "/bus@0/i2c@3190000"; - i2c5 = "/bus@0/i2c@31c0000"; - i2c6 = "/bus@0/i2c@c250000"; - i2c7 = "/bus@0/i2c@31e0000"; - mmc0 = "/bus@0/mmc@3460000"; - mmc1 = "/bus@0/mmc@3400000"; - serial0 = &tcu; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = "serial0:115200n8"; - }; - - bus@0 { - ethernet@2490000 { - status = "okay"; - - phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(G, 5) GPIO_ACTIVE_LOW>; - phy-handle = <&phy>; - phy-mode = "rgmii-id"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - interrupt-parent = <&gpio>; - interrupts = ; - #phy-cells = <0>; - }; - }; - }; - - memory-controller@2c00000 { - status = "okay"; - }; - - serial@3110000 { - status = "okay"; - }; - - i2c@3160000 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - - label = "module"; - vcc-supply = <&vdd_1v8ls>; - address-width = <8>; - pagesize = <8>; - size = <256>; - read-only; - }; - }; - - /* SDMMC1 (SD/MMC) */ - mmc@3400000 { - cd-gpios = <&gpio TEGRA194_MAIN_GPIO(A, 0) GPIO_ACTIVE_LOW>; - }; - - /* SDMMC4 (eMMC) */ - mmc@3460000 { - status = "okay"; - bus-width = <8>; - non-removable; - - vqmmc-supply = <&vdd_1v8ls>; - vmmc-supply = <&vdd_emmc_3v3>; - }; - - padctl@3520000 { - avdd-usb-supply = <&vdd_usb_3v3>; - vclamp-usb-supply = <&vdd_1v8ao>; - - ports { - usb2-1 { - vbus-supply = <&vdd_5v0_sys>; - }; - - usb2-3 { - vbus-supply = <&vdd_5v_sata>; - }; - - usb3-0 { - vbus-supply = <&vdd_5v0_sys>; - }; - - usb3-3 { - vbus-supply = <&vdd_5v0_sys>; - }; - }; - }; - - rtc@c2a0000 { - status = "okay"; - }; - - pmc@c360000 { - nvidia,invert-interrupt; - }; - }; - - bpmp { - i2c { - status = "okay"; - - pmic: pmic@3c { - compatible = "maxim,max20024"; - reg = <0x3c>; - - interrupt-parent = <&pmc>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - #interrupt-cells = <2>; - interrupt-controller; - - #gpio-cells = <2>; - gpio-controller; - - pinctrl-names = "default"; - pinctrl-0 = <&max20024_default>; - - max20024_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - }; - - gpio1 { - pins = "gpio1"; - function = "fps-out"; - maxim,active-fps-source = ; - }; - - gpio2 { - pins = "gpio2"; - function = "fps-out"; - maxim,active-fps-source = ; - }; - - gpio3 { - pins = "gpio3"; - function = "fps-out"; - maxim,active-fps-source = ; - }; - - gpio4 { - pins = "gpio4"; - function = "32k-out1"; - drive-push-pull = <1>; - }; - - gpio6 { - pins = "gpio6"; - function = "gpio"; - drive-push-pull = <1>; - }; - - gpio7 { - pins = "gpio7"; - function = "gpio"; - drive-push-pull = <0>; - }; - }; - - fps { - fps0 { - maxim,fps-event-source = ; - maxim,shutdown-fps-time-period-us = <640>; - }; - - fps1 { - maxim,fps-event-source = ; - maxim,shutdown-fps-time-period-us = <640>; - maxim,device-state-on-disabled-event = ; - }; - - fps2 { - maxim,fps-event-source = ; - maxim,shutdown-fps-time-period-us = <640>; - }; - }; - - regulators { - in-sd0-supply = <&vdd_5v0_sys>; - in-sd1-supply = <&vdd_5v0_sys>; - in-sd2-supply = <&vdd_5v0_sys>; - in-sd3-supply = <&vdd_5v0_sys>; - in-sd4-supply = <&vdd_5v0_sys>; - - in-ldo0-1-supply = <&vdd_5v0_sys>; - in-ldo2-supply = <&vdd_5v0_sys>; - in-ldo3-5-supply = <&vdd_5v0_sys>; - in-ldo4-6-supply = <&vdd_5v0_sys>; - in-ldo7-8-supply = <&vdd_1v8ls>; - - vdd_1v0: sd0 { - regulator-name = "VDDIO_SYS_1V0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v8hs: sd1 { - regulator-name = "VDDIO_SYS_1V8HS"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v8ls: sd2 { - regulator-name = "VDDIO_SYS_1V8LS"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v8ao: sd3 { - regulator-name = "VDDIO_AO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - sd4 { - regulator-name = "VDD_DDR_1V1"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo0 { - regulator-name = "VDD_RTC"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo2 { - regulator-name = "VDDIO_AO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_emmc_3v3: ldo3 { - regulator-name = "VDD_EMMC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_usb_3v3: ldo5 { - regulator-name = "VDD_USB_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo6 { - regulator-name = "VDD_SDIO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7 { - regulator-name = "AVDD_CSI_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - }; - }; - - temperature-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - - interrupt-parent = <&gpio>; - interrupts = ; - vcc-supply = <&vdd_1v8ls>; - - #thermal-sensor-cells = <1>; - }; - }; - }; - - vdd_5v0_sys: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "VIN_SYS_5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_hdmi: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "VDD_5V0_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA194_MAIN_GPIO(A, 3) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_3v3_pcie: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "PEX_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - enable-active-high; - }; - - vdd_12v_pcie: regulator@3 { - compatible = "regulator-fixed"; - regulator-name = "VDD_12V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; - - vdd_5v_sata: regulator@4 { - compatible = "regulator-fixed"; - regulator-name = "VDD_5V_SATA"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts deleted file mode 100644 index 54d057bee..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ /dev/null @@ -1,349 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include - -#include "tegra194-p2888.dtsi" - -/ { - model = "NVIDIA Jetson AGX Xavier Developer Kit"; - compatible = "nvidia,p2972-0000", "nvidia,tegra194"; - - bus@0 { - aconnect@2900000 { - status = "okay"; - - dma-controller@2930000 { - status = "okay"; - }; - - interrupt-controller@2a40000 { - status = "okay"; - }; - }; - - i2c@3160000 { - eeprom@56 { - compatible = "atmel,24c02"; - reg = <0x56>; - - label = "system"; - vcc-supply = <&vdd_1v8ls>; - address-width = <8>; - pagesize = <8>; - size = <256>; - read-only; - }; - }; - - ddc: i2c@31c0000 { - status = "okay"; - }; - - /* SDMMC1 (SD/MMC) */ - mmc@3400000 { - status = "okay"; - }; - - hda@3510000 { - nvidia,model = "jetson-xavier-hda"; - status = "okay"; - }; - - padctl@3520000 { - status = "okay"; - - pads { - usb2 { - lanes { - usb2-1 { - status = "okay"; - }; - - usb2-3 { - status = "okay"; - }; - }; - }; - - usb3 { - lanes { - usb3-0 { - status = "okay"; - }; - - usb3-3 { - status = "okay"; - }; - }; - }; - }; - - ports { - usb2-1 { - mode = "host"; - status = "okay"; - }; - - usb2-3 { - mode = "host"; - status = "okay"; - }; - - usb3-0 { - nvidia,usb2-companion = <1>; - status = "okay"; - }; - - usb3-3 { - nvidia,usb2-companion = <3>; - maximum-speed = "super-speed"; - status = "okay"; - }; - }; - }; - - usb@3610000 { - status = "okay"; - - phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, - <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>, - <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>, - <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-3}>; - phy-names = "usb2-1", "usb2-3", "usb3-0", "usb3-3"; - }; - - pwm@c340000 { - status = "okay"; - }; - - host1x@13e00000 { - display-hub@15200000 { - status = "okay"; - }; - - dpaux@155c0000 { - status = "okay"; - }; - - dpaux@155d0000 { - status = "okay"; - }; - - dpaux@155e0000 { - status = "okay"; - }; - - /* DP0 */ - sor@15b00000 { - status = "okay"; - - avdd-io-hdmi-dp-supply = <&vdd_1v0>; - vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>; - - nvidia,dpaux = <&dpaux0>; - }; - - /* DP1 */ - sor@15b40000 { - status = "okay"; - - avdd-io-hdmi-dp-supply = <&vdd_1v0>; - vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>; - - nvidia,dpaux = <&dpaux1>; - }; - - /* HDMI */ - sor@15b80000 { - status = "okay"; - - avdd-io-hdmi-dp-supply = <&vdd_1v0>; - vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>; - hdmi-supply = <&vdd_hdmi>; - - nvidia,ddc-i2c-bus = <&ddc>; - nvidia,hpd-gpio = <&gpio TEGRA194_MAIN_GPIO(M, 2) - GPIO_ACTIVE_LOW>; - }; - }; - }; - - pcie@14100000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8ao>; - - phys = <&p2u_hsio_0>; - phy-names = "p2u-0"; - }; - - pcie@14140000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8ao>; - - phys = <&p2u_hsio_7>; - phy-names = "p2u-0"; - }; - - pcie@14180000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8ao>; - - phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>, - <&p2u_hsio_5>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; - }; - - pcie@141a0000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8ao>; - vpcie3v3-supply = <&vdd_3v3_pcie>; - vpcie12v-supply = <&vdd_12v_pcie>; - - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, - <&p2u_nvhs_6>, <&p2u_nvhs_7>; - - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", - "p2u-5", "p2u-6", "p2u-7"; - }; - - pcie_ep@141a0000 { - status = "disabled"; - - vddio-pex-ctl-supply = <&vdd_1v8ao>; - - reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; - - nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) - GPIO_ACTIVE_HIGH>; - - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, - <&p2u_nvhs_6>, <&p2u_nvhs_7>; - - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", - "p2u-5", "p2u-6", "p2u-7"; - }; - - fan: fan { - compatible = "pwm-fan"; - pwms = <&pwm4 0 45334>; - - cooling-levels = <0 64 128 255>; - #cooling-cells = <2>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - force-recovery { - label = "Force Recovery"; - gpios = <&gpio TEGRA194_MAIN_GPIO(G, 0) - GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <10>; - }; - - power { - label = "Power"; - gpios = <&gpio_aon TEGRA194_AON_GPIO(EE, 4) - GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - }; - - thermal-zones { - cpu { - polling-delay = <0>; - polling-delay-passive = <500>; - status = "okay"; - - trips { - cpu_trip_critical: critical { - temperature = <96500>; - hysteresis = <0>; - type = "critical"; - }; - - cpu_trip_hot: hot { - temperature = <70000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_trip_active: active { - temperature = <50000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_passive: passive { - temperature = <30000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu-critical { - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_critical>; - }; - - cpu-hot { - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_hot>; - }; - - cpu-active { - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active>; - }; - - cpu-passive { - cooling-device = <&fan 0 0>; - trip = <&cpu_trip_passive>; - }; - }; - }; - - gpu { - polling-delay = <0>; - polling-delay-passive = <500>; - status = "okay"; - - trips { - gpu_alert0: critical { - temperature = <99000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - aux { - polling-delay = <0>; - polling-delay-passive = <500>; - status = "okay"; - - trips { - aux_alert0: critical { - temperature = <90000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dts deleted file mode 100644 index 7f97b3421..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dts +++ /dev/null @@ -1,345 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include - -#include "tegra194-p3668-0000.dtsi" - -/ { - model = "NVIDIA Jetson Xavier NX Developer Kit"; - compatible = "nvidia,p3509-0000+p3668-0000", "nvidia,tegra194"; - - bus@0 { - aconnect@2900000 { - status = "okay"; - - dma-controller@2930000 { - status = "okay"; - }; - - interrupt-controller@2a40000 { - status = "okay"; - }; - }; - - ddc: i2c@3190000 { - status = "okay"; - }; - - i2c@3160000 { - eeprom@57 { - compatible = "atmel,24c02"; - reg = <0x57>; - - label = "system"; - vcc-supply = <&vdd_1v8>; - address-width = <8>; - pagesize = <8>; - size = <256>; - read-only; - }; - }; - - hda@3510000 { - nvidia,model = "jetson-xavier-nx-hda"; - status = "okay"; - }; - - padctl@3520000 { - status = "okay"; - - pads { - usb2 { - lanes { - usb2-1 { - status = "okay"; - }; - - usb2-2 { - status = "okay"; - }; - }; - }; - - usb3 { - lanes { - usb3-2 { - status = "okay"; - }; - }; - }; - }; - - ports { - usb2-1 { - mode = "host"; - status = "okay"; - }; - - usb2-2 { - mode = "host"; - vbus-supply = <&vdd_5v0_sys>; - status = "okay"; - }; - - usb3-2 { - nvidia,usb2-companion = <1>; - vbus-supply = <&vdd_5v0_sys>; - status = "okay"; - }; - }; - }; - - usb@3610000 { - status = "okay"; - - phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, - <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>, - <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>; - phy-names = "usb2-1", "usb2-2", "usb3-2"; - }; - - pwm@32d0000 { - status = "okay"; - }; - - host1x@13e00000 { - display-hub@15200000 { - status = "okay"; - }; - - dpaux@155c0000 { - status = "okay"; - }; - - dpaux@155d0000 { - status = "okay"; - }; - - /* DP0 */ - sor@15b00000 { - status = "okay"; - - avdd-io-hdmi-dp-supply = <&vdd_1v0>; - vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>; - - nvidia,dpaux = <&dpaux0>; - }; - - /* HDMI */ - sor@15b40000 { - status = "okay"; - - avdd-io-hdmi-dp-supply = <&vdd_1v0>; - vdd-hdmi-dp-pll-supply = <&vdd_1v8hs>; - hdmi-supply = <&vdd_hdmi>; - - nvidia,ddc-i2c-bus = <&ddc>; - nvidia,hpd-gpio = <&gpio TEGRA194_MAIN_GPIO(M, 1) - GPIO_ACTIVE_LOW>; - }; - }; - }; - - pcie@14160000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8ao>; - - phys = <&p2u_hsio_11>; - phy-names = "p2u-0"; - }; - - pcie@141a0000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8ao>; - - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, - <&p2u_nvhs_6>, <&p2u_nvhs_7>; - - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", - "p2u-5", "p2u-6", "p2u-7"; - }; - - pcie_ep@141a0000 { - status = "disabled"; - - vddio-pex-ctl-supply = <&vdd_1v8ao>; - - reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; - - nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) - GPIO_ACTIVE_HIGH>; - - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, - <&p2u_nvhs_6>, <&p2u_nvhs_7>; - - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", - "p2u-5", "p2u-6", "p2u-7"; - }; - - fan: fan { - compatible = "pwm-fan"; - pwms = <&pwm6 0 45334>; - - cooling-levels = <0 64 128 255>; - #cooling-cells = <2>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - force-recovery { - label = "Force Recovery"; - gpios = <&gpio TEGRA194_MAIN_GPIO(G, 0) - GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <10>; - }; - - power { - label = "Power"; - gpios = <&gpio_aon TEGRA194_AON_GPIO(EE, 4) - GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - }; - - vdd_5v0_sys: regulator@100 { - compatible = "regulator-fixed"; - regulator-name = "VDD_5V_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_3v3_sys: regulator@101 { - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_3v3_ao: regulator@102 { - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3_AO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v8: regulator@103 { - compatible = "regulator-fixed"; - regulator-name = "VDD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_hdmi: regulator@104 { - compatible = "regulator-fixed"; - regulator-name = "VDD_5V0_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - thermal-zones { - cpu { - polling-delay = <0>; - polling-delay-passive = <500>; - status = "okay"; - - trips { - cpu_trip_critical: critical { - temperature = <96500>; - hysteresis = <0>; - type = "critical"; - }; - - cpu_trip_hot: hot { - temperature = <70000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_trip_active: active { - temperature = <50000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_passive: passive { - temperature = <30000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu-critical { - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_critical>; - }; - - cpu-hot { - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_hot>; - }; - - cpu-active { - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active>; - }; - - cpu-passive { - cooling-device = <&fan 0 0>; - trip = <&cpu_trip_passive>; - }; - }; - }; - - gpu { - polling-delay = <0>; - polling-delay-passive = <500>; - status = "okay"; - - trips { - gpu_alert0: critical { - temperature = <99000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - aux { - polling-delay = <0>; - polling-delay-passive = <500>; - status = "okay"; - - trips { - aux_alert0: critical { - temperature = <90000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi deleted file mode 100644 index 0dc8304a2..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi +++ /dev/null @@ -1,306 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "tegra194.dtsi" - -#include - -/ { - model = "NVIDIA Jetson Xavier NX"; - compatible = "nvidia,p3668-0000", "nvidia,tegra194"; - - aliases { - ethernet0 = "/bus@0/ethernet@2490000"; - i2c0 = "/bpmp/i2c"; - i2c1 = "/bus@0/i2c@3160000"; - i2c2 = "/bus@0/i2c@c240000"; - i2c3 = "/bus@0/i2c@3180000"; - i2c4 = "/bus@0/i2c@3190000"; - i2c5 = "/bus@0/i2c@31c0000"; - i2c6 = "/bus@0/i2c@c250000"; - i2c7 = "/bus@0/i2c@31e0000"; - mmc0 = "/bus@0/mmc@3460000"; - rtc0 = "/bpmp/i2c/pmic@3c"; - rtc1 = "/bus@0/rtc@c2a0000"; - serial0 = &tcu; - }; - - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = "serial0:115200n8"; - }; - - bus@0 { - ethernet@2490000 { - status = "okay"; - - phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(R, 1) GPIO_ACTIVE_LOW>; - phy-handle = <&phy>; - phy-mode = "rgmii-id"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - interrupt-parent = <&gpio>; - interrupts = ; - #phy-cells = <0>; - }; - }; - }; - - memory-controller@2c00000 { - status = "okay"; - }; - - serial@3100000 { - status = "okay"; - }; - - i2c@3160000 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - - label = "module"; - vcc-supply = <&vdd_1v8ls>; - address-width = <8>; - pagesize = <8>; - size = <256>; - read-only; - }; - }; - - /* SDMMC1 (SD/MMC) */ - mmc@3400000 { - status = "okay"; - bus-width = <4>; - cd-gpios = <&gpio TEGRA194_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW>; - disable-wp; - vmmc-supply = <&vdd_3v3_sd>; - }; - - padctl@3520000 { - avdd-usb-supply = <&vdd_usb_3v3>; - vclamp-usb-supply = <&vdd_1v8ao>; - - ports { - usb2-1 { - vbus-supply = <&vdd_5v0_sys>; - }; - - usb2-3 { - vbus-supply = <&vdd_5v0_sys>; - }; - - usb3-0 { - vbus-supply = <&vdd_5v0_sys>; - }; - - usb3-3 { - vbus-supply = <&vdd_5v0_sys>; - }; - }; - }; - - rtc@c2a0000 { - status = "okay"; - }; - - pmc@c360000 { - nvidia,invert-interrupt; - }; - }; - - bpmp { - i2c { - status = "okay"; - - pmic: pmic@3c { - compatible = "maxim,max20024"; - reg = <0x3c>; - - interrupt-parent = <&pmc>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - #interrupt-cells = <2>; - interrupt-controller; - - #gpio-cells = <2>; - gpio-controller; - - pinctrl-names = "default"; - pinctrl-0 = <&max20024_default>; - - max20024_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - }; - - gpio1 { - pins = "gpio1"; - function = "fps-out"; - maxim,active-fps-source = ; - }; - - gpio2 { - pins = "gpio2"; - function = "fps-out"; - maxim,active-fps-source = ; - }; - - gpio3 { - pins = "gpio3"; - function = "fps-out"; - maxim,active-fps-source = ; - }; - - gpio4 { - pins = "gpio4"; - function = "32k-out1"; - drive-push-pull = <1>; - }; - - gpio6 { - pins = "gpio6"; - function = "gpio"; - drive-push-pull = <1>; - }; - - gpio7 { - pins = "gpio7"; - function = "gpio"; - drive-push-pull = <0>; - }; - }; - - fps { - fps0 { - maxim,fps-event-source = ; - maxim,shutdown-fps-time-period-us = <640>; - }; - - fps1 { - maxim,fps-event-source = ; - maxim,shutdown-fps-time-period-us = <640>; - maxim,device-state-on-disabled-event = ; - }; - - fps2 { - maxim,fps-event-source = ; - maxim,shutdown-fps-time-period-us = <640>; - }; - }; - - regulators { - in-sd0-supply = <&vdd_5v0_sys>; - in-sd1-supply = <&vdd_5v0_sys>; - in-sd2-supply = <&vdd_5v0_sys>; - in-sd3-supply = <&vdd_5v0_sys>; - in-sd4-supply = <&vdd_5v0_sys>; - - in-ldo0-1-supply = <&vdd_5v0_sys>; - in-ldo2-supply = <&vdd_5v0_sys>; - in-ldo3-5-supply = <&vdd_5v0_sys>; - in-ldo4-6-supply = <&vdd_5v0_sys>; - in-ldo7-8-supply = <&vdd_1v8ls>; - - vdd_1v0: sd0 { - regulator-name = "VDDIO_SYS_1V0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v8hs: sd1 { - regulator-name = "VDDIO_SYS_1V8HS"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v8ls: sd2 { - regulator-name = "VDDIO_SYS_1V8LS"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v8ao: sd3 { - regulator-name = "VDDIO_AO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - sd4 { - regulator-name = "VDD_DDR_1V1"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo0 { - regulator-name = "VDD_RTC"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo2 { - regulator-name = "VDDIO_AO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo3 { - regulator-name = "VDD_EMMC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_usb_3v3: ldo5 { - regulator-name = "VDD_USB_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo6 { - regulator-name = "VDD_SDIO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7 { - regulator-name = "AVDD_CSI_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - }; - }; - }; - }; - - vdd_3v3_sd: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3_SD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA194_MAIN_GPIO(G, 2) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - enable-active-high; - }; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi deleted file mode 100644 index 05cf606b8..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ /dev/null @@ -1,2382 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "nvidia,tegra194"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - /* control backbone */ - bus@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x40000000>; - - misc@100000 { - compatible = "nvidia,tegra194-misc"; - reg = <0x00100000 0xf000>, - <0x0010f000 0x1000>; - }; - - gpio: gpio@2200000 { - compatible = "nvidia,tegra194-gpio"; - reg-names = "security", "gpio"; - reg = <0x2200000 0x10000>, - <0x2210000 0x10000>; - interrupts = , - , - , - , - , - ; - #interrupt-cells = <2>; - interrupt-controller; - #gpio-cells = <2>; - gpio-controller; - }; - - ethernet@2490000 { - compatible = "nvidia,tegra194-eqos", - "nvidia,tegra186-eqos", - "snps,dwc-qos-ethernet-4.10"; - reg = <0x02490000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, - <&bpmp TEGRA194_CLK_EQOS_AXI>, - <&bpmp TEGRA194_CLK_EQOS_RX>, - <&bpmp TEGRA194_CLK_EQOS_TX>, - <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; - clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; - resets = <&bpmp TEGRA194_RESET_EQOS>; - reset-names = "eqos"; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, - <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; - interconnect-names = "dma-mem", "write"; - status = "disabled"; - - snps,write-requests = <1>; - snps,read-requests = <3>; - snps,burst-map = <0x7>; - snps,txpbl = <16>; - snps,rxpbl = <8>; - }; - - aconnect@2900000 { - compatible = "nvidia,tegra194-aconnect", - "nvidia,tegra210-aconnect"; - clocks = <&bpmp TEGRA194_CLK_APE>, - <&bpmp TEGRA194_CLK_APB2APE>; - clock-names = "ape", "apb2ape"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x02900000 0x02900000 0x200000>; - status = "disabled"; - - adma: dma-controller@2930000 { - compatible = "nvidia,tegra194-adma", - "nvidia,tegra186-adma"; - reg = <0x02930000 0x20000>; - interrupt-parent = <&agic>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - #dma-cells = <1>; - clocks = <&bpmp TEGRA194_CLK_AHUB>; - clock-names = "d_audio"; - status = "disabled"; - }; - - agic: interrupt-controller@2a40000 { - compatible = "nvidia,tegra194-agic", - "nvidia,tegra210-agic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x02a41000 0x1000>, - <0x02a42000 0x2000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_APE>; - clock-names = "clk"; - status = "disabled"; - }; - - tegra_ahub: ahub@2900800 { - compatible = "nvidia,tegra194-ahub", - "nvidia,tegra186-ahub"; - reg = <0x02900800 0x800>; - clocks = <&bpmp TEGRA194_CLK_AHUB>; - clock-names = "ahub"; - assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x02900800 0x02900800 0x11800>; - status = "disabled"; - - tegra_admaif: admaif@290f000 { - compatible = "nvidia,tegra194-admaif", - "nvidia,tegra186-admaif"; - reg = <0x0290f000 0x1000>; - dmas = <&adma 1>, <&adma 1>, - <&adma 2>, <&adma 2>, - <&adma 3>, <&adma 3>, - <&adma 4>, <&adma 4>, - <&adma 5>, <&adma 5>, - <&adma 6>, <&adma 6>, - <&adma 7>, <&adma 7>, - <&adma 8>, <&adma 8>, - <&adma 9>, <&adma 9>, - <&adma 10>, <&adma 10>, - <&adma 11>, <&adma 11>, - <&adma 12>, <&adma 12>, - <&adma 13>, <&adma 13>, - <&adma 14>, <&adma 14>, - <&adma 15>, <&adma 15>, - <&adma 16>, <&adma 16>, - <&adma 17>, <&adma 17>, - <&adma 18>, <&adma 18>, - <&adma 19>, <&adma 19>, - <&adma 20>, <&adma 20>; - dma-names = "rx1", "tx1", - "rx2", "tx2", - "rx3", "tx3", - "rx4", "tx4", - "rx5", "tx5", - "rx6", "tx6", - "rx7", "tx7", - "rx8", "tx8", - "rx9", "tx9", - "rx10", "tx10", - "rx11", "tx11", - "rx12", "tx12", - "rx13", "tx13", - "rx14", "tx14", - "rx15", "tx15", - "rx16", "tx16", - "rx17", "tx17", - "rx18", "tx18", - "rx19", "tx19", - "rx20", "tx20"; - status = "disabled"; - }; - - tegra_i2s1: i2s@2901000 { - compatible = "nvidia,tegra194-i2s", - "nvidia,tegra210-i2s"; - reg = <0x2901000 0x100>; - clocks = <&bpmp TEGRA194_CLK_I2S1>, - <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; - clock-names = "i2s", "sync_input"; - assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <1536000>; - sound-name-prefix = "I2S1"; - status = "disabled"; - }; - - tegra_i2s2: i2s@2901100 { - compatible = "nvidia,tegra194-i2s", - "nvidia,tegra210-i2s"; - reg = <0x2901100 0x100>; - clocks = <&bpmp TEGRA194_CLK_I2S2>, - <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; - clock-names = "i2s", "sync_input"; - assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <1536000>; - sound-name-prefix = "I2S2"; - status = "disabled"; - }; - - tegra_i2s3: i2s@2901200 { - compatible = "nvidia,tegra194-i2s", - "nvidia,tegra210-i2s"; - reg = <0x2901200 0x100>; - clocks = <&bpmp TEGRA194_CLK_I2S3>, - <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; - clock-names = "i2s", "sync_input"; - assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <1536000>; - sound-name-prefix = "I2S3"; - status = "disabled"; - }; - - tegra_i2s4: i2s@2901300 { - compatible = "nvidia,tegra194-i2s", - "nvidia,tegra210-i2s"; - reg = <0x2901300 0x100>; - clocks = <&bpmp TEGRA194_CLK_I2S4>, - <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; - clock-names = "i2s", "sync_input"; - assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <1536000>; - sound-name-prefix = "I2S4"; - status = "disabled"; - }; - - tegra_i2s5: i2s@2901400 { - compatible = "nvidia,tegra194-i2s", - "nvidia,tegra210-i2s"; - reg = <0x2901400 0x100>; - clocks = <&bpmp TEGRA194_CLK_I2S5>, - <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; - clock-names = "i2s", "sync_input"; - assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <1536000>; - sound-name-prefix = "I2S5"; - status = "disabled"; - }; - - tegra_i2s6: i2s@2901500 { - compatible = "nvidia,tegra194-i2s", - "nvidia,tegra210-i2s"; - reg = <0x2901500 0x100>; - clocks = <&bpmp TEGRA194_CLK_I2S6>, - <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; - clock-names = "i2s", "sync_input"; - assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <1536000>; - sound-name-prefix = "I2S6"; - status = "disabled"; - }; - - tegra_dmic1: dmic@2904000 { - compatible = "nvidia,tegra194-dmic", - "nvidia,tegra210-dmic"; - reg = <0x2904000 0x100>; - clocks = <&bpmp TEGRA194_CLK_DMIC1>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC1"; - status = "disabled"; - }; - - tegra_dmic2: dmic@2904100 { - compatible = "nvidia,tegra194-dmic", - "nvidia,tegra210-dmic"; - reg = <0x2904100 0x100>; - clocks = <&bpmp TEGRA194_CLK_DMIC2>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC2"; - status = "disabled"; - }; - - tegra_dmic3: dmic@2904200 { - compatible = "nvidia,tegra194-dmic", - "nvidia,tegra210-dmic"; - reg = <0x2904200 0x100>; - clocks = <&bpmp TEGRA194_CLK_DMIC3>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC3"; - status = "disabled"; - }; - - tegra_dmic4: dmic@2904300 { - compatible = "nvidia,tegra194-dmic", - "nvidia,tegra210-dmic"; - reg = <0x2904300 0x100>; - clocks = <&bpmp TEGRA194_CLK_DMIC4>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC4"; - status = "disabled"; - }; - - tegra_dspk1: dspk@2905000 { - compatible = "nvidia,tegra194-dspk", - "nvidia,tegra186-dspk"; - reg = <0x2905000 0x100>; - clocks = <&bpmp TEGRA194_CLK_DSPK1>; - clock-names = "dspk"; - assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <12288000>; - sound-name-prefix = "DSPK1"; - status = "disabled"; - }; - - tegra_dspk2: dspk@2905100 { - compatible = "nvidia,tegra194-dspk", - "nvidia,tegra186-dspk"; - reg = <0x2905100 0x100>; - clocks = <&bpmp TEGRA194_CLK_DSPK2>; - clock-names = "dspk"; - assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <12288000>; - sound-name-prefix = "DSPK2"; - status = "disabled"; - }; - }; - }; - - pinmux: pinmux@2430000 { - compatible = "nvidia,tegra194-pinmux"; - reg = <0x2430000 0x17000>, - <0xc300000 0x4000>; - - status = "okay"; - - pex_rst_c5_out_state: pex_rst_c5_out { - pex_rst { - nvidia,pins = "pex_l5_rst_n_pgg1"; - nvidia,schmitt = ; - nvidia,lpdr = ; - nvidia,enable-input = ; - nvidia,io-hv = ; - nvidia,tristate = ; - nvidia,pull = ; - }; - }; - - clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { - clkreq { - nvidia,pins = "pex_l5_clkreq_n_pgg0"; - nvidia,schmitt = ; - nvidia,lpdr = ; - nvidia,enable-input = ; - nvidia,io-hv = ; - nvidia,tristate = ; - nvidia,pull = ; - }; - }; - }; - - mc: memory-controller@2c00000 { - compatible = "nvidia,tegra194-mc"; - reg = <0x02c00000 0x100000>, - <0x02b80000 0x040000>, - <0x01700000 0x100000>; - interrupts = ; - #interconnect-cells = <1>; - status = "disabled"; - - #address-cells = <2>; - #size-cells = <2>; - - ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, - <0x02b80000 0x0 0x02b80000 0x0 0x040000>, - <0x02c00000 0x0 0x02c00000 0x0 0x100000>; - - /* - * Bit 39 of addresses passing through the memory - * controller selects the XBAR format used when memory - * is accessed. This is used to transparently access - * memory in the XBAR format used by the discrete GPU - * (bit 39 set) or Tegra (bit 39 clear). - * - * As a consequence, the operating system must ensure - * that bit 39 is never used implicitly, for example - * via an I/O virtual address mapping of an IOMMU. If - * devices require access to the XBAR switch, their - * drivers must set this bit explicitly. - * - * Limit the DMA range for memory clients to [38:0]. - */ - dma-ranges = <0x0 0x0 0x0 0x80 0x0>; - - emc: external-memory-controller@2c60000 { - compatible = "nvidia,tegra194-emc"; - reg = <0x0 0x02c60000 0x0 0x90000>, - <0x0 0x01780000 0x0 0x80000>; - clocks = <&bpmp TEGRA194_CLK_EMC>; - clock-names = "emc"; - - #interconnect-cells = <0>; - - nvidia,bpmp = <&bpmp>; - }; - }; - - uarta: serial@3100000 { - compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03100000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_UARTA>; - clock-names = "serial"; - resets = <&bpmp TEGRA194_RESET_UARTA>; - reset-names = "serial"; - status = "disabled"; - }; - - uartb: serial@3110000 { - compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03110000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_UARTB>; - clock-names = "serial"; - resets = <&bpmp TEGRA194_RESET_UARTB>; - reset-names = "serial"; - status = "disabled"; - }; - - uartd: serial@3130000 { - compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03130000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_UARTD>; - clock-names = "serial"; - resets = <&bpmp TEGRA194_RESET_UARTD>; - reset-names = "serial"; - status = "disabled"; - }; - - uarte: serial@3140000 { - compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03140000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_UARTE>; - clock-names = "serial"; - resets = <&bpmp TEGRA194_RESET_UARTE>; - reset-names = "serial"; - status = "disabled"; - }; - - uartf: serial@3150000 { - compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03150000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_UARTF>; - clock-names = "serial"; - resets = <&bpmp TEGRA194_RESET_UARTF>; - reset-names = "serial"; - status = "disabled"; - }; - - gen1_i2c: i2c@3160000 { - compatible = "nvidia,tegra194-i2c"; - reg = <0x03160000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA194_CLK_I2C1>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA194_RESET_I2C1>; - reset-names = "i2c"; - status = "disabled"; - }; - - uarth: serial@3170000 { - compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03170000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_UARTH>; - clock-names = "serial"; - resets = <&bpmp TEGRA194_RESET_UARTH>; - reset-names = "serial"; - status = "disabled"; - }; - - cam_i2c: i2c@3180000 { - compatible = "nvidia,tegra194-i2c"; - reg = <0x03180000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA194_CLK_I2C3>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA194_RESET_I2C3>; - reset-names = "i2c"; - status = "disabled"; - }; - - /* shares pads with dpaux1 */ - dp_aux_ch1_i2c: i2c@3190000 { - compatible = "nvidia,tegra194-i2c"; - reg = <0x03190000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA194_CLK_I2C4>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA194_RESET_I2C4>; - reset-names = "i2c"; - pinctrl-0 = <&state_dpaux1_i2c>; - pinctrl-1 = <&state_dpaux1_off>; - pinctrl-names = "default", "idle"; - status = "disabled"; - }; - - /* shares pads with dpaux0 */ - dp_aux_ch0_i2c: i2c@31b0000 { - compatible = "nvidia,tegra194-i2c"; - reg = <0x031b0000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA194_CLK_I2C6>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA194_RESET_I2C6>; - reset-names = "i2c"; - pinctrl-0 = <&state_dpaux0_i2c>; - pinctrl-1 = <&state_dpaux0_off>; - pinctrl-names = "default", "idle"; - status = "disabled"; - }; - - /* shares pads with dpaux2 */ - dp_aux_ch2_i2c: i2c@31c0000 { - compatible = "nvidia,tegra194-i2c"; - reg = <0x031c0000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA194_CLK_I2C7>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA194_RESET_I2C7>; - reset-names = "i2c"; - pinctrl-0 = <&state_dpaux2_i2c>; - pinctrl-1 = <&state_dpaux2_off>; - pinctrl-names = "default", "idle"; - status = "disabled"; - }; - - /* shares pads with dpaux3 */ - dp_aux_ch3_i2c: i2c@31e0000 { - compatible = "nvidia,tegra194-i2c"; - reg = <0x031e0000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA194_CLK_I2C9>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA194_RESET_I2C9>; - reset-names = "i2c"; - pinctrl-0 = <&state_dpaux3_i2c>; - pinctrl-1 = <&state_dpaux3_off>; - pinctrl-names = "default", "idle"; - status = "disabled"; - }; - - pwm1: pwm@3280000 { - compatible = "nvidia,tegra194-pwm", - "nvidia,tegra186-pwm"; - reg = <0x3280000 0x10000>; - clocks = <&bpmp TEGRA194_CLK_PWM1>; - clock-names = "pwm"; - resets = <&bpmp TEGRA194_RESET_PWM1>; - reset-names = "pwm"; - status = "disabled"; - #pwm-cells = <2>; - }; - - pwm2: pwm@3290000 { - compatible = "nvidia,tegra194-pwm", - "nvidia,tegra186-pwm"; - reg = <0x3290000 0x10000>; - clocks = <&bpmp TEGRA194_CLK_PWM2>; - clock-names = "pwm"; - resets = <&bpmp TEGRA194_RESET_PWM2>; - reset-names = "pwm"; - status = "disabled"; - #pwm-cells = <2>; - }; - - pwm3: pwm@32a0000 { - compatible = "nvidia,tegra194-pwm", - "nvidia,tegra186-pwm"; - reg = <0x32a0000 0x10000>; - clocks = <&bpmp TEGRA194_CLK_PWM3>; - clock-names = "pwm"; - resets = <&bpmp TEGRA194_RESET_PWM3>; - reset-names = "pwm"; - status = "disabled"; - #pwm-cells = <2>; - }; - - pwm5: pwm@32c0000 { - compatible = "nvidia,tegra194-pwm", - "nvidia,tegra186-pwm"; - reg = <0x32c0000 0x10000>; - clocks = <&bpmp TEGRA194_CLK_PWM5>; - clock-names = "pwm"; - resets = <&bpmp TEGRA194_RESET_PWM5>; - reset-names = "pwm"; - status = "disabled"; - #pwm-cells = <2>; - }; - - pwm6: pwm@32d0000 { - compatible = "nvidia,tegra194-pwm", - "nvidia,tegra186-pwm"; - reg = <0x32d0000 0x10000>; - clocks = <&bpmp TEGRA194_CLK_PWM6>; - clock-names = "pwm"; - resets = <&bpmp TEGRA194_RESET_PWM6>; - reset-names = "pwm"; - status = "disabled"; - #pwm-cells = <2>; - }; - - pwm7: pwm@32e0000 { - compatible = "nvidia,tegra194-pwm", - "nvidia,tegra186-pwm"; - reg = <0x32e0000 0x10000>; - clocks = <&bpmp TEGRA194_CLK_PWM7>; - clock-names = "pwm"; - resets = <&bpmp TEGRA194_RESET_PWM7>; - reset-names = "pwm"; - status = "disabled"; - #pwm-cells = <2>; - }; - - pwm8: pwm@32f0000 { - compatible = "nvidia,tegra194-pwm", - "nvidia,tegra186-pwm"; - reg = <0x32f0000 0x10000>; - clocks = <&bpmp TEGRA194_CLK_PWM8>; - clock-names = "pwm"; - resets = <&bpmp TEGRA194_RESET_PWM8>; - reset-names = "pwm"; - status = "disabled"; - #pwm-cells = <2>; - }; - - sdmmc1: mmc@3400000 { - compatible = "nvidia,tegra194-sdhci"; - reg = <0x03400000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_SDMMC1>, - <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; - clock-names = "sdhci", "tmclk"; - resets = <&bpmp TEGRA194_RESET_SDMMC1>; - reset-names = "sdhci"; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, - <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; - interconnect-names = "dma-mem", "write"; - nvidia,pad-autocal-pull-up-offset-3v3-timeout = - <0x07>; - nvidia,pad-autocal-pull-down-offset-3v3-timeout = - <0x07>; - nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; - nvidia,pad-autocal-pull-down-offset-1v8-timeout = - <0x07>; - nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; - nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; - nvidia,default-tap = <0x9>; - nvidia,default-trim = <0x5>; - status = "disabled"; - }; - - sdmmc3: mmc@3440000 { - compatible = "nvidia,tegra194-sdhci"; - reg = <0x03440000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_SDMMC3>, - <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; - clock-names = "sdhci", "tmclk"; - resets = <&bpmp TEGRA194_RESET_SDMMC3>; - reset-names = "sdhci"; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, - <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; - interconnect-names = "dma-mem", "write"; - nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; - nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; - nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; - nvidia,pad-autocal-pull-down-offset-3v3-timeout = - <0x07>; - nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; - nvidia,pad-autocal-pull-down-offset-1v8-timeout = - <0x07>; - nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; - nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; - nvidia,default-tap = <0x9>; - nvidia,default-trim = <0x5>; - status = "disabled"; - }; - - sdmmc4: mmc@3460000 { - compatible = "nvidia,tegra194-sdhci"; - reg = <0x03460000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_SDMMC4>, - <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; - clock-names = "sdhci", "tmclk"; - assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, - <&bpmp TEGRA194_CLK_PLLC4>; - assigned-clock-parents = - <&bpmp TEGRA194_CLK_PLLC4>; - resets = <&bpmp TEGRA194_RESET_SDMMC4>; - reset-names = "sdhci"; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, - <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; - interconnect-names = "dma-mem", "write"; - nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; - nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; - nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; - nvidia,pad-autocal-pull-down-offset-1v8-timeout = - <0x0a>; - nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; - nvidia,pad-autocal-pull-down-offset-3v3-timeout = - <0x0a>; - nvidia,default-tap = <0x8>; - nvidia,default-trim = <0x14>; - nvidia,dqs-trim = <40>; - supports-cqe; - status = "disabled"; - }; - - hda@3510000 { - compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; - reg = <0x3510000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_HDA>, - <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, - <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; - clock-names = "hda", "hda2hdmi", "hda2codec_2x"; - resets = <&bpmp TEGRA194_RESET_HDA>, - <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; - reset-names = "hda", "hda2hdmi"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, - <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; - interconnect-names = "dma-mem", "write"; - status = "disabled"; - }; - - xusb_padctl: padctl@3520000 { - compatible = "nvidia,tegra194-xusb-padctl"; - reg = <0x03520000 0x1000>, - <0x03540000 0x1000>; - reg-names = "padctl", "ao"; - - resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; - reset-names = "padctl"; - - status = "disabled"; - - pads { - usb2 { - clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; - clock-names = "trk"; - - lanes { - usb2-0 { - nvidia,function = "xusb"; - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-3 { - nvidia,function = "xusb"; - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - usb3 { - lanes { - usb3-0 { - nvidia,function = "xusb"; - status = "disabled"; - #phy-cells = <0>; - }; - - usb3-1 { - nvidia,function = "xusb"; - status = "disabled"; - #phy-cells = <0>; - }; - - usb3-2 { - nvidia,function = "xusb"; - status = "disabled"; - #phy-cells = <0>; - }; - - usb3-3 { - nvidia,function = "xusb"; - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "disabled"; - }; - - usb2-1 { - status = "disabled"; - }; - - usb2-2 { - status = "disabled"; - }; - - usb2-3 { - status = "disabled"; - }; - - usb3-0 { - status = "disabled"; - }; - - usb3-1 { - status = "disabled"; - }; - - usb3-2 { - status = "disabled"; - }; - - usb3-3 { - status = "disabled"; - }; - }; - }; - - usb@3550000 { - compatible = "nvidia,tegra194-xudc"; - reg = <0x03550000 0x8000>, - <0x03558000 0x1000>; - reg-names = "base", "fpci"; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, - <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, - <&bpmp TEGRA194_CLK_XUSB_SS>, - <&bpmp TEGRA194_CLK_XUSB_FS>; - clock-names = "dev", "ss", "ss_src", "fs_src"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, - <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; - power-domain-names = "dev", "ss"; - nvidia,xusb-padctl = <&xusb_padctl>; - status = "disabled"; - }; - - usb@3610000 { - compatible = "nvidia,tegra194-xusb"; - reg = <0x03610000 0x40000>, - <0x03600000 0x10000>; - reg-names = "hcd", "fpci"; - - interrupts = , - ; - - clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, - <&bpmp TEGRA194_CLK_XUSB_FALCON>, - <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, - <&bpmp TEGRA194_CLK_XUSB_SS>, - <&bpmp TEGRA194_CLK_CLK_M>, - <&bpmp TEGRA194_CLK_XUSB_FS>, - <&bpmp TEGRA194_CLK_UTMIPLL>, - <&bpmp TEGRA194_CLK_CLK_M>, - <&bpmp TEGRA194_CLK_PLLE>; - clock-names = "xusb_host", "xusb_falcon_src", - "xusb_ss", "xusb_ss_src", "xusb_hs_src", - "xusb_fs_src", "pll_u_480m", "clk_m", - "pll_e"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, - <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; - power-domain-names = "xusb_host", "xusb_ss"; - - nvidia,xusb-padctl = <&xusb_padctl>; - status = "disabled"; - }; - - fuse@3820000 { - compatible = "nvidia,tegra194-efuse"; - reg = <0x03820000 0x10000>; - clocks = <&bpmp TEGRA194_CLK_FUSE>; - clock-names = "fuse"; - }; - - gic: interrupt-controller@3881000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x03881000 0x1000>, - <0x03882000 0x2000>, - <0x03884000 0x2000>, - <0x03886000 0x2000>; - interrupts = ; - interrupt-parent = <&gic>; - }; - - cec@3960000 { - compatible = "nvidia,tegra194-cec"; - reg = <0x03960000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_CEC>; - clock-names = "cec"; - status = "disabled"; - }; - - hsp_top0: hsp@3c00000 { - compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; - reg = <0x03c00000 0xa0000>; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "doorbell", "shared0", "shared1", "shared2", - "shared3", "shared4", "shared5", "shared6", - "shared7"; - #mbox-cells = <2>; - }; - - p2u_hsio_0: phy@3e10000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03e10000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_1: phy@3e20000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03e20000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_2: phy@3e30000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03e30000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_3: phy@3e40000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03e40000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_4: phy@3e50000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03e50000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_5: phy@3e60000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03e60000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_6: phy@3e70000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03e70000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_7: phy@3e80000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03e80000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_8: phy@3e90000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03e90000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_9: phy@3ea0000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03ea0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_0: phy@3eb0000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03eb0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_1: phy@3ec0000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03ec0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_2: phy@3ed0000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03ed0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_3: phy@3ee0000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03ee0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_4: phy@3ef0000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03ef0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_5: phy@3f00000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03f00000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_6: phy@3f10000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03f10000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_7: phy@3f20000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03f20000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_10: phy@3f30000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03f30000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_11: phy@3f40000 { - compatible = "nvidia,tegra194-p2u"; - reg = <0x03f40000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - hsp_aon: hsp@c150000 { - compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; - reg = <0x0c150000 0x90000>; - interrupts = , - , - , - ; - /* - * Shared interrupt 0 is routed only to AON/SPE, so - * we only have 4 shared interrupts for the CCPLEX. - */ - interrupt-names = "shared1", "shared2", "shared3", "shared4"; - #mbox-cells = <2>; - }; - - gen2_i2c: i2c@c240000 { - compatible = "nvidia,tegra194-i2c"; - reg = <0x0c240000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA194_CLK_I2C2>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA194_RESET_I2C2>; - reset-names = "i2c"; - status = "disabled"; - }; - - gen8_i2c: i2c@c250000 { - compatible = "nvidia,tegra194-i2c"; - reg = <0x0c250000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA194_CLK_I2C8>; - clock-names = "div-clk"; - resets = <&bpmp TEGRA194_RESET_I2C8>; - reset-names = "i2c"; - status = "disabled"; - }; - - uartc: serial@c280000 { - compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x0c280000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_UARTC>; - clock-names = "serial"; - resets = <&bpmp TEGRA194_RESET_UARTC>; - reset-names = "serial"; - status = "disabled"; - }; - - uartg: serial@c290000 { - compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x0c290000 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_UARTG>; - clock-names = "serial"; - resets = <&bpmp TEGRA194_RESET_UARTG>; - reset-names = "serial"; - status = "disabled"; - }; - - rtc: rtc@c2a0000 { - compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; - reg = <0x0c2a0000 0x10000>; - interrupt-parent = <&pmc>; - interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&bpmp TEGRA194_CLK_CLK_32K>; - clock-names = "rtc"; - status = "disabled"; - }; - - gpio_aon: gpio@c2f0000 { - compatible = "nvidia,tegra194-gpio-aon"; - reg-names = "security", "gpio"; - reg = <0xc2f0000 0x1000>, - <0xc2f1000 0x1000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pwm4: pwm@c340000 { - compatible = "nvidia,tegra194-pwm", - "nvidia,tegra186-pwm"; - reg = <0xc340000 0x10000>; - clocks = <&bpmp TEGRA194_CLK_PWM4>; - clock-names = "pwm"; - resets = <&bpmp TEGRA194_RESET_PWM4>; - reset-names = "pwm"; - status = "disabled"; - #pwm-cells = <2>; - }; - - pmc: pmc@c360000 { - compatible = "nvidia,tegra194-pmc"; - reg = <0x0c360000 0x10000>, - <0x0c370000 0x10000>, - <0x0c380000 0x10000>, - <0x0c390000 0x10000>, - <0x0c3a0000 0x10000>; - reg-names = "pmc", "wake", "aotag", "scratch", "misc"; - - #interrupt-cells = <2>; - interrupt-controller; - }; - - host1x@13e00000 { - compatible = "nvidia,tegra194-host1x"; - reg = <0x13e00000 0x10000>, - <0x13e10000 0x10000>; - reg-names = "hypervisor", "vm"; - interrupts = , - ; - interrupt-names = "syncpt", "host1x"; - clocks = <&bpmp TEGRA194_CLK_HOST1X>; - clock-names = "host1x"; - resets = <&bpmp TEGRA194_RESET_HOST1X>; - reset-names = "host1x"; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x15000000 0x15000000 0x01000000>; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; - interconnect-names = "dma-mem"; - - display-hub@15200000 { - compatible = "nvidia,tegra194-display"; - reg = <0x15200000 0x00040000>; - resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, - <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, - <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, - <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, - <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, - <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, - <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; - reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", - "wgrp3", "wgrp4", "wgrp5"; - clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, - <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; - clock-names = "disp", "hub"; - status = "disabled"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x15200000 0x15200000 0x40000>; - - display@15200000 { - compatible = "nvidia,tegra194-dc"; - reg = <0x15200000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; - clock-names = "dc"; - resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; - reset-names = "dc"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; - interconnect-names = "dma-mem", "read-1"; - - nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; - nvidia,head = <0>; - }; - - display@15210000 { - compatible = "nvidia,tegra194-dc"; - reg = <0x15210000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; - clock-names = "dc"; - resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; - reset-names = "dc"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; - interconnect-names = "dma-mem", "read-1"; - - nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; - nvidia,head = <1>; - }; - - display@15220000 { - compatible = "nvidia,tegra194-dc"; - reg = <0x15220000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; - clock-names = "dc"; - resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; - reset-names = "dc"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; - interconnect-names = "dma-mem", "read-1"; - - nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; - nvidia,head = <2>; - }; - - display@15230000 { - compatible = "nvidia,tegra194-dc"; - reg = <0x15230000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; - clock-names = "dc"; - resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; - reset-names = "dc"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; - interconnect-names = "dma-mem", "read-1"; - - nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; - nvidia,head = <3>; - }; - }; - - vic@15340000 { - compatible = "nvidia,tegra194-vic"; - reg = <0x15340000 0x00040000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_VIC>; - clock-names = "vic"; - resets = <&bpmp TEGRA194_RESET_VIC>; - reset-names = "vic"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, - <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; - interconnect-names = "dma-mem", "write"; - }; - - dpaux0: dpaux@155c0000 { - compatible = "nvidia,tegra194-dpaux"; - reg = <0x155c0000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_DPAUX>, - <&bpmp TEGRA194_CLK_PLLDP>; - clock-names = "dpaux", "parent"; - resets = <&bpmp TEGRA194_RESET_DPAUX>; - reset-names = "dpaux"; - status = "disabled"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - - state_dpaux0_aux: pinmux-aux { - groups = "dpaux-io"; - function = "aux"; - }; - - state_dpaux0_i2c: pinmux-i2c { - groups = "dpaux-io"; - function = "i2c"; - }; - - state_dpaux0_off: pinmux-off { - groups = "dpaux-io"; - function = "off"; - }; - - i2c-bus { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - dpaux1: dpaux@155d0000 { - compatible = "nvidia,tegra194-dpaux"; - reg = <0x155d0000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_DPAUX1>, - <&bpmp TEGRA194_CLK_PLLDP>; - clock-names = "dpaux", "parent"; - resets = <&bpmp TEGRA194_RESET_DPAUX1>; - reset-names = "dpaux"; - status = "disabled"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - - state_dpaux1_aux: pinmux-aux { - groups = "dpaux-io"; - function = "aux"; - }; - - state_dpaux1_i2c: pinmux-i2c { - groups = "dpaux-io"; - function = "i2c"; - }; - - state_dpaux1_off: pinmux-off { - groups = "dpaux-io"; - function = "off"; - }; - - i2c-bus { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - dpaux2: dpaux@155e0000 { - compatible = "nvidia,tegra194-dpaux"; - reg = <0x155e0000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_DPAUX2>, - <&bpmp TEGRA194_CLK_PLLDP>; - clock-names = "dpaux", "parent"; - resets = <&bpmp TEGRA194_RESET_DPAUX2>; - reset-names = "dpaux"; - status = "disabled"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - - state_dpaux2_aux: pinmux-aux { - groups = "dpaux-io"; - function = "aux"; - }; - - state_dpaux2_i2c: pinmux-i2c { - groups = "dpaux-io"; - function = "i2c"; - }; - - state_dpaux2_off: pinmux-off { - groups = "dpaux-io"; - function = "off"; - }; - - i2c-bus { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - dpaux3: dpaux@155f0000 { - compatible = "nvidia,tegra194-dpaux"; - reg = <0x155f0000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_DPAUX3>, - <&bpmp TEGRA194_CLK_PLLDP>; - clock-names = "dpaux", "parent"; - resets = <&bpmp TEGRA194_RESET_DPAUX3>; - reset-names = "dpaux"; - status = "disabled"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - - state_dpaux3_aux: pinmux-aux { - groups = "dpaux-io"; - function = "aux"; - }; - - state_dpaux3_i2c: pinmux-i2c { - groups = "dpaux-io"; - function = "i2c"; - }; - - state_dpaux3_off: pinmux-off { - groups = "dpaux-io"; - function = "off"; - }; - - i2c-bus { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - sor0: sor@15b00000 { - compatible = "nvidia,tegra194-sor"; - reg = <0x15b00000 0x40000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, - <&bpmp TEGRA194_CLK_SOR0_OUT>, - <&bpmp TEGRA194_CLK_PLLD>, - <&bpmp TEGRA194_CLK_PLLDP>, - <&bpmp TEGRA194_CLK_SOR_SAFE>, - <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; - clock-names = "sor", "out", "parent", "dp", "safe", - "pad"; - resets = <&bpmp TEGRA194_RESET_SOR0>; - reset-names = "sor"; - pinctrl-0 = <&state_dpaux0_aux>; - pinctrl-1 = <&state_dpaux0_i2c>; - pinctrl-2 = <&state_dpaux0_off>; - pinctrl-names = "aux", "i2c", "off"; - status = "disabled"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - nvidia,interface = <0>; - }; - - sor1: sor@15b40000 { - compatible = "nvidia,tegra194-sor"; - reg = <0x15b40000 0x40000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, - <&bpmp TEGRA194_CLK_SOR1_OUT>, - <&bpmp TEGRA194_CLK_PLLD2>, - <&bpmp TEGRA194_CLK_PLLDP>, - <&bpmp TEGRA194_CLK_SOR_SAFE>, - <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; - clock-names = "sor", "out", "parent", "dp", "safe", - "pad"; - resets = <&bpmp TEGRA194_RESET_SOR1>; - reset-names = "sor"; - pinctrl-0 = <&state_dpaux1_aux>; - pinctrl-1 = <&state_dpaux1_i2c>; - pinctrl-2 = <&state_dpaux1_off>; - pinctrl-names = "aux", "i2c", "off"; - status = "disabled"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - nvidia,interface = <1>; - }; - - sor2: sor@15b80000 { - compatible = "nvidia,tegra194-sor"; - reg = <0x15b80000 0x40000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, - <&bpmp TEGRA194_CLK_SOR2_OUT>, - <&bpmp TEGRA194_CLK_PLLD3>, - <&bpmp TEGRA194_CLK_PLLDP>, - <&bpmp TEGRA194_CLK_SOR_SAFE>, - <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; - clock-names = "sor", "out", "parent", "dp", "safe", - "pad"; - resets = <&bpmp TEGRA194_RESET_SOR2>; - reset-names = "sor"; - pinctrl-0 = <&state_dpaux2_aux>; - pinctrl-1 = <&state_dpaux2_i2c>; - pinctrl-2 = <&state_dpaux2_off>; - pinctrl-names = "aux", "i2c", "off"; - status = "disabled"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - nvidia,interface = <2>; - }; - - sor3: sor@15bc0000 { - compatible = "nvidia,tegra194-sor"; - reg = <0x15bc0000 0x40000>; - interrupts = ; - clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, - <&bpmp TEGRA194_CLK_SOR3_OUT>, - <&bpmp TEGRA194_CLK_PLLD4>, - <&bpmp TEGRA194_CLK_PLLDP>, - <&bpmp TEGRA194_CLK_SOR_SAFE>, - <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; - clock-names = "sor", "out", "parent", "dp", "safe", - "pad"; - resets = <&bpmp TEGRA194_RESET_SOR3>; - reset-names = "sor"; - pinctrl-0 = <&state_dpaux3_aux>; - pinctrl-1 = <&state_dpaux3_i2c>; - pinctrl-2 = <&state_dpaux3_off>; - pinctrl-names = "aux", "i2c", "off"; - status = "disabled"; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - nvidia,interface = <3>; - }; - }; - - gpu@17000000 { - compatible = "nvidia,gv11b"; - reg = <0x17000000 0x1000000>, - <0x18000000 0x1000000>; - interrupts = , - ; - interrupt-names = "stall", "nonstall"; - clocks = <&bpmp TEGRA194_CLK_GPCCLK>, - <&bpmp TEGRA194_CLK_GPU_PWR>, - <&bpmp TEGRA194_CLK_FUSE>; - clock-names = "gpu", "pwr", "fuse"; - resets = <&bpmp TEGRA194_RESET_GPU>; - reset-names = "gpu"; - dma-coherent; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; - interconnect-names = "dma-mem", "read-0-hp", "write-0", - "read-1", "read-1-hp", "write-1", - "read-2", "read-2-hp", "write-2", - "read-3", "read-3-hp", "write-3"; - }; - }; - - pcie@14100000 { - compatible = "nvidia,tegra194-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; - reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; - - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <1>; - num-viewport = <8>; - linux,pci-domain = <1>; - - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; - clock-names = "core"; - - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_1>; - reset-names = "apb", "core"; - - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - - nvidia,bpmp = <&bpmp 1>; - - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; - - bus-range = <0x0 0xff>; - - ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ - <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ - <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ - - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; - interconnect-names = "read", "write"; - }; - - pcie@14120000 { - compatible = "nvidia,tegra194-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; - reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; - - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <1>; - num-viewport = <8>; - linux,pci-domain = <2>; - - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; - clock-names = "core"; - - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_2>; - reset-names = "apb", "core"; - - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; - - nvidia,bpmp = <&bpmp 2>; - - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; - - bus-range = <0x0 0xff>; - - ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ - <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ - <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ - - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; - interconnect-names = "read", "write"; - }; - - pcie@14140000 { - compatible = "nvidia,tegra194-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; - reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; - - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <1>; - num-viewport = <8>; - linux,pci-domain = <3>; - - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; - clock-names = "core"; - - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_3>; - reset-names = "apb", "core"; - - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - - nvidia,bpmp = <&bpmp 3>; - - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; - - bus-range = <0x0 0xff>; - - ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ - <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ - <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ - - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; - interconnect-names = "read", "write"; - }; - - pcie@14160000 { - compatible = "nvidia,tegra194-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; - reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; - - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - num-viewport = <8>; - linux,pci-domain = <4>; - - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; - clock-names = "core"; - - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_4>; - reset-names = "apb", "core"; - - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - - nvidia,bpmp = <&bpmp 4>; - - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; - - bus-range = <0x0 0xff>; - - ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ - <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ - <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ - - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; - interconnect-names = "read", "write"; - }; - - pcie@14180000 { - compatible = "nvidia,tegra194-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; - reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; - - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <8>; - num-viewport = <8>; - linux,pci-domain = <0>; - - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; - clock-names = "core"; - - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_0>; - reset-names = "apb", "core"; - - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - - nvidia,bpmp = <&bpmp 0>; - - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; - - bus-range = <0x0 0xff>; - - ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ - <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ - <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ - - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; - interconnect-names = "read", "write"; - }; - - pcie@141a0000 { - compatible = "nvidia,tegra194-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; - reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; - - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <8>; - num-viewport = <8>; - linux,pci-domain = <5>; - - pinctrl-names = "default"; - pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; - - clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, - <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; - clock-names = "core", "core_m"; - - resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, - <&bpmp TEGRA194_RESET_PEX1_CORE_5>; - reset-names = "apb", "core"; - - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - nvidia,bpmp = <&bpmp 5>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; - - bus-range = <0x0 0xff>; - - ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ - <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ - <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ - - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; - interconnect-names = "read", "write"; - }; - - pcie_ep@14160000 { - compatible = "nvidia,tegra194-pcie-ep"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; - reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ - reg-names = "appl", "atu_dma", "dbi", "addr_space"; - - status = "disabled"; - - num-lanes = <4>; - num-ib-windows = <2>; - num-ob-windows = <8>; - - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; - clock-names = "core"; - - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_4>; - reset-names = "apb", "core"; - - interrupts = ; /* controller interrupt */ - interrupt-names = "intr"; - - nvidia,bpmp = <&bpmp 4>; - - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; - }; - - pcie_ep@14180000 { - compatible = "nvidia,tegra194-pcie-ep"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; - reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ - reg-names = "appl", "atu_dma", "dbi", "addr_space"; - - status = "disabled"; - - num-lanes = <8>; - num-ib-windows = <2>; - num-ob-windows = <8>; - - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; - clock-names = "core"; - - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_0>; - reset-names = "apb", "core"; - - interrupts = ; /* controller interrupt */ - interrupt-names = "intr"; - - nvidia,bpmp = <&bpmp 0>; - - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; - }; - - pcie_ep@141a0000 { - compatible = "nvidia,tegra194-pcie-ep"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; - reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ - reg-names = "appl", "atu_dma", "dbi", "addr_space"; - - status = "disabled"; - - num-lanes = <8>; - num-ib-windows = <2>; - num-ob-windows = <8>; - - pinctrl-names = "default"; - pinctrl-0 = <&clkreq_c5_bi_dir_state>; - - clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; - clock-names = "core"; - - resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, - <&bpmp TEGRA194_RESET_PEX1_CORE_5>; - reset-names = "apb", "core"; - - interrupts = ; /* controller interrupt */ - interrupt-names = "intr"; - - nvidia,bpmp = <&bpmp 5>; - - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; - }; - - sram@40000000 { - compatible = "nvidia,tegra194-sysram", "mmio-sram"; - reg = <0x0 0x40000000 0x0 0x50000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x40000000 0x50000>; - - cpu_bpmp_tx: sram@4e000 { - reg = <0x4e000 0x1000>; - label = "cpu-bpmp-tx"; - pool; - }; - - cpu_bpmp_rx: sram@4f000 { - reg = <0x4f000 0x1000>; - label = "cpu-bpmp-rx"; - pool; - }; - }; - - bpmp: bpmp { - compatible = "nvidia,tegra186-bpmp"; - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB - TEGRA_HSP_DB_MASTER_BPMP>; - shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, - <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, - <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, - <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; - interconnect-names = "read", "write", "dma-mem", "dma-write"; - - bpmp_i2c: i2c { - compatible = "nvidia,tegra186-bpmp-i2c"; - nvidia,bpmp-bus-id = <5>; - #address-cells = <1>; - #size-cells = <0>; - }; - - bpmp_thermal: thermal { - compatible = "nvidia,tegra186-bpmp-thermal"; - #thermal-sensor-cells = <1>; - }; - }; - - cpus { - compatible = "nvidia,tegra194-ccplex"; - nvidia,bpmp = <&bpmp>; - #address-cells = <1>; - #size-cells = <0>; - - cpu0_0: cpu@0 { - compatible = "nvidia,tegra194-carmel"; - device_type = "cpu"; - reg = <0x000>; - enable-method = "psci"; - i-cache-size = <131072>; - i-cache-line-size = <64>; - i-cache-sets = <512>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2c_0>; - }; - - cpu0_1: cpu@1 { - compatible = "nvidia,tegra194-carmel"; - device_type = "cpu"; - reg = <0x001>; - enable-method = "psci"; - i-cache-size = <131072>; - i-cache-line-size = <64>; - i-cache-sets = <512>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2c_0>; - }; - - cpu1_0: cpu@100 { - compatible = "nvidia,tegra194-carmel"; - device_type = "cpu"; - reg = <0x100>; - enable-method = "psci"; - i-cache-size = <131072>; - i-cache-line-size = <64>; - i-cache-sets = <512>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2c_1>; - }; - - cpu1_1: cpu@101 { - compatible = "nvidia,tegra194-carmel"; - device_type = "cpu"; - reg = <0x101>; - enable-method = "psci"; - i-cache-size = <131072>; - i-cache-line-size = <64>; - i-cache-sets = <512>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2c_1>; - }; - - cpu2_0: cpu@200 { - compatible = "nvidia,tegra194-carmel"; - device_type = "cpu"; - reg = <0x200>; - enable-method = "psci"; - i-cache-size = <131072>; - i-cache-line-size = <64>; - i-cache-sets = <512>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2c_2>; - }; - - cpu2_1: cpu@201 { - compatible = "nvidia,tegra194-carmel"; - device_type = "cpu"; - reg = <0x201>; - enable-method = "psci"; - i-cache-size = <131072>; - i-cache-line-size = <64>; - i-cache-sets = <512>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2c_2>; - }; - - cpu3_0: cpu@300 { - compatible = "nvidia,tegra194-carmel"; - device_type = "cpu"; - reg = <0x300>; - enable-method = "psci"; - i-cache-size = <131072>; - i-cache-line-size = <64>; - i-cache-sets = <512>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2c_3>; - }; - - cpu3_1: cpu@301 { - compatible = "nvidia,tegra194-carmel"; - device_type = "cpu"; - reg = <0x301>; - enable-method = "psci"; - i-cache-size = <131072>; - i-cache-line-size = <64>; - i-cache-sets = <512>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2c_3>; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0_0>; - }; - - core1 { - cpu = <&cpu0_1>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu1_0>; - }; - - core1 { - cpu = <&cpu1_1>; - }; - }; - - cluster2 { - core0 { - cpu = <&cpu2_0>; - }; - - core1 { - cpu = <&cpu2_1>; - }; - }; - - cluster3 { - core0 { - cpu = <&cpu3_0>; - }; - - core1 { - cpu = <&cpu3_1>; - }; - }; - }; - - l2c_0: l2-cache0 { - cache-size = <2097152>; - cache-line-size = <64>; - cache-sets = <2048>; - next-level-cache = <&l3c>; - }; - - l2c_1: l2-cache1 { - cache-size = <2097152>; - cache-line-size = <64>; - cache-sets = <2048>; - next-level-cache = <&l3c>; - }; - - l2c_2: l2-cache2 { - cache-size = <2097152>; - cache-line-size = <64>; - cache-sets = <2048>; - next-level-cache = <&l3c>; - }; - - l2c_3: l2-cache3 { - cache-size = <2097152>; - cache-line-size = <64>; - cache-sets = <2048>; - next-level-cache = <&l3c>; - }; - - l3c: l3-cache { - cache-size = <4194304>; - cache-line-size = <64>; - cache-sets = <4096>; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - status = "okay"; - method = "smc"; - }; - - tcu: tcu { - compatible = "nvidia,tegra194-tcu"; - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, - <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; - mbox-names = "rx", "tx"; - }; - - thermal-zones { - cpu { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_CPU>; - status = "disabled"; - }; - - gpu { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_GPU>; - status = "disabled"; - }; - - aux { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_AUX>; - status = "disabled"; - }; - - pllx { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_PLLX>; - status = "disabled"; - }; - - ao { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_AO>; - status = "disabled"; - }; - - tj { - thermal-sensors = <&{/bpmp/thermal} - TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - interrupt-parent = <&gic>; - always-on; - }; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi deleted file mode 100644 index 6077d572d..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ /dev/null @@ -1,350 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -#include "tegra210.dtsi" - -/ { - model = "NVIDIA Jetson TX1"; - compatible = "nvidia,p2180", "nvidia,tegra210"; - - aliases { - rtc0 = "/i2c@7000d000/pmic@3c"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x1 0x0>; - }; - - gpu@57000000 { - vdd-supply = <&vdd_gpu>; - }; - - /* debug port */ - serial@70006000 { - status = "okay"; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: pmic@3c { - compatible = "maxim,max77620"; - reg = <0x3c>; - interrupt-parent = <&tegra_pmc>; - interrupts = <51 IRQ_TYPE_LEVEL_LOW>; - - #interrupt-cells = <2>; - interrupt-controller; - - #gpio-cells = <2>; - gpio-controller; - - pinctrl-names = "default"; - pinctrl-0 = <&max77620_default>; - - max77620_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - }; - - gpio1 { - pins = "gpio1"; - function = "fps-out"; - drive-push-pull = <1>; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <7>; - maxim,active-fps-power-down-slot = <0>; - }; - - gpio2_3 { - pins = "gpio2", "gpio3"; - function = "fps-out"; - drive-open-drain = <1>; - maxim,active-fps-source = ; - }; - - gpio4 { - pins = "gpio4"; - function = "32k-out1"; - }; - - gpio5_6_7 { - pins = "gpio5", "gpio6", "gpio7"; - function = "gpio"; - drive-push-pull = <1>; - }; - }; - - fps { - fps0 { - maxim,fps-event-source = ; - maxim,suspend-fps-time-period-us = <1280>; - }; - - fps1 { - maxim,fps-event-source = ; - maxim,suspend-fps-time-period-us = <1280>; - }; - - fps2 { - maxim,fps-event-source = ; - }; - }; - - regulators { - in-ldo0-1-supply = <&vdd_pre>; - in-ldo7-8-supply = <&vdd_pre>; - in-sd3-supply = <&vdd_5v0_sys>; - - vdd_soc: sd0 { - regulator-name = "VDD_SOC"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - - regulator-enable-ramp-delay = <146>; - regulator-ramp-delay = <27500>; - - maxim,active-fps-source = ; - }; - - vdd_ddr: sd1 { - regulator-name = "VDD_DDR_1V1_PMIC"; - regulator-always-on; - regulator-boot-on; - - regulator-enable-ramp-delay = <130>; - regulator-ramp-delay = <27500>; - - maxim,active-fps-source = ; - }; - - vdd_pre: sd2 { - regulator-name = "VDD_PRE_REG_1V35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - - regulator-enable-ramp-delay = <176>; - regulator-ramp-delay = <27500>; - - maxim,active-fps-source = ; - }; - - vdd_1v8: sd3 { - regulator-name = "VDD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-enable-ramp-delay = <242>; - regulator-ramp-delay = <27500>; - - maxim,active-fps-source = ; - }; - - vdd_sys_1v2: ldo0 { - regulator-name = "AVDD_SYS_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - - regulator-enable-ramp-delay = <26>; - regulator-ramp-delay = <100000>; - - maxim,active-fps-source = ; - }; - - vdd_pex_1v05: ldo1 { - regulator-name = "VDD_PEX_1V05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - - regulator-enable-ramp-delay = <22>; - regulator-ramp-delay = <100000>; - - maxim,active-fps-source = ; - }; - - vddio_sdmmc: ldo2 { - regulator-name = "VDDIO_SDMMC"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-enable-ramp-delay = <62>; - regulator-ramp-delay = <100000>; - - maxim,active-fps-source = ; - }; - - vdd_cam_hv: ldo3 { - regulator-name = "VDD_CAM_HV"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-enable-ramp-delay = <50>; - regulator-ramp-delay = <100000>; - - maxim,active-fps-source = ; - }; - - vdd_rtc: ldo4 { - regulator-name = "VDD_RTC"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-always-on; - regulator-boot-on; - - regulator-enable-ramp-delay = <22>; - regulator-ramp-delay = <100000>; - - maxim,active-fps-source = ; - }; - - vdd_ts_hv: ldo5 { - regulator-name = "VDD_TS_HV"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-enable-ramp-delay = <62>; - regulator-ramp-delay = <100000>; - - maxim,active-fps-source = ; - }; - - vdd_ts: ldo6 { - regulator-name = "VDD_TS_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-enable-ramp-delay = <36>; - regulator-ramp-delay = <100000>; - - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <7>; - maxim,active-fps-power-down-slot = <0>; - }; - - avdd_1v05_pll: ldo7 { - regulator-name = "AVDD_1V05_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - - regulator-enable-ramp-delay = <24>; - regulator-ramp-delay = <100000>; - - maxim,active-fps-source = ; - }; - - avdd_1v05: ldo8 { - regulator-name = "AVDD_SATA_HDMI_DP_1V05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - - regulator-enable-ramp-delay = <22>; - regulator-ramp-delay = <100000>; - - maxim,active-fps-source = ; - }; - }; - }; - }; - - i2c@7000c500 { - status = "okay"; - - /* module ID EEPROM */ - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - - label = "module"; - vcc-supply = <&vdd_1v8>; - address-width = <8>; - pagesize = <8>; - size = <256>; - read-only; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - nvidia,cpu-pwr-good-time = <0>; - nvidia,cpu-pwr-off-time = <0>; - nvidia,core-pwr-good-time = <4587 3876>; - nvidia,core-pwr-off-time = <39065>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - /* eMMC */ - mmc@700b0600 { - status = "okay"; - bus-width = <8>; - non-removable; - vqmmc-supply = <&vdd_1v8>; - }; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - cpus { - cpu@0 { - enable-method = "psci"; - }; - - cpu@1 { - enable-method = "psci"; - }; - - cpu@2 { - enable-method = "psci"; - }; - - cpu@3 { - enable-method = "psci"; - }; - - idle-states { - cpu-sleep { - status = "okay"; - }; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - vdd_gpu: regulator@100 { - compatible = "pwm-regulator"; - pwms = <&pwm 1 8000>; - regulator-name = "VDD_GPU"; - regulator-min-microvolt = <710000>; - regulator-max-microvolt = <1320000>; - enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; - regulator-ramp-delay = <80>; - regulator-enable-ramp-delay = <2000>; - regulator-settling-time-us = <160>; - }; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-0000.dts deleted file mode 100644 index 21c6d3749..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-0000.dts +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra210-p2530.dtsi" -#include "tegra210-p2595.dtsi" - -/ { - model = "NVIDIA Tegra210 P2371 (P2530/P2595) reference design"; - compatible = "nvidia,p2371-0000", "nvidia,tegra210"; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts deleted file mode 100644 index 4c9c2a054..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ /dev/null @@ -1,130 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra210-p2180.dtsi" -#include "tegra210-p2597.dtsi" - -/ { - model = "NVIDIA Jetson TX1 Developer Kit"; - compatible = "nvidia,p2371-2180", "nvidia,tegra210"; - - pcie@1003000 { - status = "okay"; - - avdd-pll-uerefe-supply = <&avdd_1v05_pll>; - hvddio-pex-supply = <&vdd_1v8>; - dvddio-pex-supply = <&vdd_pex_1v05>; - dvdd-pex-pll-supply = <&vdd_pex_1v05>; - hvdd-pex-pll-e-supply = <&vdd_1v8>; - vddio-pex-ctl-supply = <&vdd_1v8>; - - pci@1,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; - phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3"; - status = "okay"; - }; - - pci@2,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; - phy-names = "pcie-0"; - status = "okay"; - }; - }; - - host1x@50000000 { - dsi@54300000 { - status = "okay"; - - avdd-dsi-csi-supply = <&vdd_dsi_csi>; - - panel@0 { - compatible = "auo,b080uan01"; - reg = <0>; - - enable-gpios = <&gpio TEGRA_GPIO(V, 2) - GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_5v0_io>; - backlight = <&backlight>; - }; - }; - }; - - i2c@7000c400 { - backlight: backlight@2c { - compatible = "ti,lp8557"; - reg = <0x2c>; - power-supply = <&vdd_3v3_sys>; - - dev-ctrl = /bits/ 8 <0x80>; - init-brt = /bits/ 8 <0xff>; - - pwm-period = <29334>; - - pwms = <&pwm 0 29334>; - pwm-names = "lp8557"; - - /* 3 LED string */ - rom_14h { - rom-addr = /bits/ 8 <0x14>; - rom-val = /bits/ 8 <0x87>; - }; - - /* boost frequency 1 MHz */ - rom_13h { - rom-addr = /bits/ 8 <0x13>; - rom-val = /bits/ 8 <0x01>; - }; - }; - }; - - i2c@7000c500 { - /* carrier board ID EEPROM */ - eeprom@57 { - compatible = "atmel,24c02"; - reg = <0x57>; - - label = "system"; - vcc-supply = <&vdd_1v8>; - address-width = <8>; - pagesize = <8>; - size = <256>; - read-only; - }; - }; - - clock@70110000 { - status = "okay"; - - nvidia,cf = <6>; - nvidia,ci = <0>; - nvidia,cg = <2>; - nvidia,droop-ctrl = <0x00000f00>; - nvidia,force-mode = <1>; - nvidia,sample-rate = <25000>; - - nvidia,pwm-min-microvolts = <708000>; - nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ - nvidia,pwm-to-pmic; - nvidia,pwm-tristate-microvolts = <1000000>; - nvidia,pwm-voltage-step-microvolts = <19200>; - - pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; - pinctrl-0 = <&dvfs_pwm_active_state>; - pinctrl-1 = <&dvfs_pwm_inactive_state>; - }; - - aconnect@702c0000 { - status = "okay"; - - dma@702e2000 { - status = "okay"; - }; - - interrupt-controller@702f9000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi deleted file mode 100644 index 58aa05189..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "tegra210.dtsi" - -/ { - model = "NVIDIA Tegra210 P2530 main board"; - compatible = "nvidia,p2530", "nvidia,tegra210"; - - aliases { - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0xc0000000>; - }; - - /* debug port */ - serial@70006000 { - status = "okay"; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - }; - - /* eMMC */ - mmc@700b0600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - cpus { - cpu@0 { - enable-method = "psci"; - }; - - cpu@1 { - enable-method = "psci"; - }; - - cpu@2 { - enable-method = "psci"; - }; - - cpu@3 { - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2571.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2571.dts deleted file mode 100644 index e2a347e57..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2571.dts +++ /dev/null @@ -1,1303 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include "tegra210-p2530.dtsi" - -/ { - model = "NVIDIA Tegra210 P2571 reference design"; - compatible = "nvidia,p2571", "nvidia,tegra210"; - - pinmux: pinmux@700008d4 { - pinctrl-names = "boot"; - pinctrl-0 = <&state_boot>; - - state_boot: pinmux { - pex_l0_rst_n_pa0 { - nvidia,pins = "pex_l0_rst_n_pa0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l0_clkreq_n_pa1 { - nvidia,pins = "pex_l0_clkreq_n_pa1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_wake_n_pa2 { - nvidia,pins = "pex_wake_n_pa2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l1_rst_n_pa3 { - nvidia,pins = "pex_l1_rst_n_pa3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l1_clkreq_n_pa4 { - nvidia,pins = "pex_l1_clkreq_n_pa4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - sata_led_active_pa5 { - nvidia,pins = "sata_led_active_pa5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pa6 { - nvidia,pins = "pa6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_fs_pb0 { - nvidia,pins = "dap1_fs_pb0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_din_pb1 { - nvidia,pins = "dap1_din_pb1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_dout_pb2 { - nvidia,pins = "dap1_dout_pb2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_sclk_pb3 { - nvidia,pins = "dap1_sclk_pb3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_mosi_pb4 { - nvidia,pins = "spi2_mosi_pb4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_miso_pb5 { - nvidia,pins = "spi2_miso_pb5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_sck_pb6 { - nvidia,pins = "spi2_sck_pb6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_cs0_pb7 { - nvidia,pins = "spi2_cs0_pb7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_mosi_pc0 { - nvidia,pins = "spi1_mosi_pc0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_miso_pc1 { - nvidia,pins = "spi1_miso_pc1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_sck_pc2 { - nvidia,pins = "spi1_sck_pc2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_cs0_pc3 { - nvidia,pins = "spi1_cs0_pc3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_cs1_pc4 { - nvidia,pins = "spi1_cs1_pc4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_sck_pc5 { - nvidia,pins = "spi4_sck_pc5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_cs0_pc6 { - nvidia,pins = "spi4_cs0_pc6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_mosi_pc7 { - nvidia,pins = "spi4_mosi_pc7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_miso_pd0 { - nvidia,pins = "spi4_miso_pd0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_tx_pd1 { - nvidia,pins = "uart3_tx_pd1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_rx_pd2 { - nvidia,pins = "uart3_rx_pd2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_rts_pd3 { - nvidia,pins = "uart3_rts_pd3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_cts_pd4 { - nvidia,pins = "uart3_cts_pd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic1_clk_pe0 { - nvidia,pins = "dmic1_clk_pe0"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic1_dat_pe1 { - nvidia,pins = "dmic1_dat_pe1"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic2_clk_pe2 { - nvidia,pins = "dmic2_clk_pe2"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic2_dat_pe3 { - nvidia,pins = "dmic2_dat_pe3"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic3_clk_pe4 { - nvidia,pins = "dmic3_clk_pe4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic3_dat_pe5 { - nvidia,pins = "dmic3_dat_pe5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pe6 { - nvidia,pins = "pe6"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pe7 { - nvidia,pins = "pe7"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen3_i2c_scl_pf0 { - nvidia,pins = "gen3_i2c_scl_pf0"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen3_i2c_sda_pf1 { - nvidia,pins = "gen3_i2c_sda_pf1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - uart2_tx_pg0 { - nvidia,pins = "uart2_tx_pg0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_rx_pg1 { - nvidia,pins = "uart2_rx_pg1"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_rts_pg2 { - nvidia,pins = "uart2_rts_pg2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_cts_pg3 { - nvidia,pins = "uart2_cts_pg3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_en_ph0 { - nvidia,pins = "wifi_en_ph0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_rst_ph1 { - nvidia,pins = "wifi_rst_ph1"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_wake_ap_ph2 { - nvidia,pins = "wifi_wake_ap_ph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_wake_bt_ph3 { - nvidia,pins = "ap_wake_bt_ph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - bt_rst_ph4 { - nvidia,pins = "bt_rst_ph4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - bt_wake_ap_ph5 { - nvidia,pins = "bt_wake_ap_ph5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ph6 { - nvidia,pins = "ph6"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_wake_nfc_ph7 { - nvidia,pins = "ap_wake_nfc_ph7"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - nfc_en_pi0 { - nvidia,pins = "nfc_en_pi0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - nfc_int_pi1 { - nvidia,pins = "nfc_int_pi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gps_en_pi2 { - nvidia,pins = "gps_en_pi2"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gps_rst_pi3 { - nvidia,pins = "gps_rst_pi3"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_tx_pi4 { - nvidia,pins = "uart4_tx_pi4"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_rx_pi5 { - nvidia,pins = "uart4_rx_pi5"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_rts_pi6 { - nvidia,pins = "uart4_rts_pi6"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_cts_pi7 { - nvidia,pins = "uart4_cts_pi7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pj0 { - nvidia,pins = "gen1_i2c_sda_pj0"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen1_i2c_scl_pj1 { - nvidia,pins = "gen1_i2c_scl_pj1"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen2_i2c_scl_pj2 { - nvidia,pins = "gen2_i2c_scl_pj2"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen2_i2c_sda_pj3 { - nvidia,pins = "gen2_i2c_sda_pj3"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - dap4_fs_pj4 { - nvidia,pins = "dap4_fs_pj4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_din_pj5 { - nvidia,pins = "dap4_din_pj5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_dout_pj6 { - nvidia,pins = "dap4_dout_pj6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_sclk_pj7 { - nvidia,pins = "dap4_sclk_pj7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk0 { - nvidia,pins = "pk0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk1 { - nvidia,pins = "pk1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk2 { - nvidia,pins = "pk2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk3 { - nvidia,pins = "pk3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk4 { - nvidia,pins = "pk4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk5 { - nvidia,pins = "pk5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk6 { - nvidia,pins = "pk6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk7 { - nvidia,pins = "pk7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pl0 { - nvidia,pins = "pl0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pl1 { - nvidia,pins = "pl1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_clk_pm0 { - nvidia,pins = "sdmmc1_clk_pm0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_cmd_pm1 { - nvidia,pins = "sdmmc1_cmd_pm1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat3_pm2 { - nvidia,pins = "sdmmc1_dat3_pm2"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat2_pm3 { - nvidia,pins = "sdmmc1_dat2_pm3"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat1_pm4 { - nvidia,pins = "sdmmc1_dat1_pm4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat0_pm5 { - nvidia,pins = "sdmmc1_dat0_pm5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_clk_pp0 { - nvidia,pins = "sdmmc3_clk_pp0"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_cmd_pp1 { - nvidia,pins = "sdmmc3_cmd_pp1"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat3_pp2 { - nvidia,pins = "sdmmc3_dat3_pp2"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat2_pp3 { - nvidia,pins = "sdmmc3_dat2_pp3"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat1_pp4 { - nvidia,pins = "sdmmc3_dat1_pp4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat0_pp5 { - nvidia,pins = "sdmmc3_dat0_pp5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_mclk_ps0 { - nvidia,pins = "cam1_mclk_ps0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam2_mclk_ps1 { - nvidia,pins = "cam2_mclk_ps1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_scl_ps2 { - nvidia,pins = "cam_i2c_scl_ps2"; - nvidia,function = "i2cvi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - cam_i2c_sda_ps3 { - nvidia,pins = "cam_i2c_sda_ps3"; - nvidia,function = "i2cvi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - cam_rst_ps4 { - nvidia,pins = "cam_rst_ps4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_af_en_ps5 { - nvidia,pins = "cam_af_en_ps5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_flash_en_ps6 { - nvidia,pins = "cam_flash_en_ps6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_pwdn_ps7 { - nvidia,pins = "cam1_pwdn_ps7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam2_pwdn_pt0 { - nvidia,pins = "cam2_pwdn_pt0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_strobe_pt1 { - nvidia,pins = "cam1_strobe_pt1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_tx_pu0 { - nvidia,pins = "uart1_tx_pu0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_rx_pu1 { - nvidia,pins = "uart1_rx_pu1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_rts_pu2 { - nvidia,pins = "uart1_rts_pu2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_cts_pu3 { - nvidia,pins = "uart1_cts_pu3"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_bl_pwm_pv0 { - nvidia,pins = "lcd_bl_pwm_pv0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_bl_en_pv1 { - nvidia,pins = "lcd_bl_en_pv1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_rst_pv2 { - nvidia,pins = "lcd_rst_pv2"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_gpio1_pv3 { - nvidia,pins = "lcd_gpio1_pv3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_gpio2_pv4 { - nvidia,pins = "lcd_gpio2_pv4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_ready_pv5 { - nvidia,pins = "ap_ready_pv5"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_rst_pv6 { - nvidia,pins = "touch_rst_pv6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_clk_pv7 { - nvidia,pins = "touch_clk_pv7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - modem_wake_ap_px0 { - nvidia,pins = "modem_wake_ap_px0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_int_px1 { - nvidia,pins = "touch_int_px1"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - motion_int_px2 { - nvidia,pins = "motion_int_px2"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - als_prox_int_px3 { - nvidia,pins = "als_prox_int_px3"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - temp_alert_px4 { - nvidia,pins = "temp_alert_px4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_power_on_px5 { - nvidia,pins = "button_power_on_px5"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_vol_up_px6 { - nvidia,pins = "button_vol_up_px6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_vol_down_px7 { - nvidia,pins = "button_vol_down_px7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_slide_sw_py0 { - nvidia,pins = "button_slide_sw_py0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_home_py1 { - nvidia,pins = "button_home_py1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_te_py2 { - nvidia,pins = "lcd_te_py2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_scl_py3 { - nvidia,pins = "pwr_i2c_scl_py3"; - nvidia,function = "i2cpmu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pwr_i2c_sda_py4 { - nvidia,pins = "pwr_i2c_sda_py4"; - nvidia,function = "i2cpmu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - clk_32k_out_py5 { - nvidia,pins = "clk_32k_out_py5"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz0 { - nvidia,pins = "pz0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz1 { - nvidia,pins = "pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz2 { - nvidia,pins = "pz2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz3 { - nvidia,pins = "pz3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz4 { - nvidia,pins = "pz4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz5 { - nvidia,pins = "pz5"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_fs_paa0 { - nvidia,pins = "dap2_fs_paa0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_sclk_paa1 { - nvidia,pins = "dap2_sclk_paa1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_din_paa2 { - nvidia,pins = "dap2_din_paa2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_dout_paa3 { - nvidia,pins = "dap2_dout_paa3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - aud_mclk_pbb0 { - nvidia,pins = "aud_mclk_pbb0"; - nvidia,function = "aud"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dvfs_pwm_pbb1 { - nvidia,pins = "dvfs_pwm_pbb1"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dvfs_clk_pbb2 { - nvidia,pins = "dvfs_clk_pbb2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gpio_x1_aud_pbb3 { - nvidia,pins = "gpio_x1_aud_pbb3"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gpio_x3_aud_pbb4 { - nvidia,pins = "gpio_x3_aud_pbb4"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi_cec_pcc0 { - nvidia,pins = "hdmi_cec_pcc0"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - hdmi_int_dp_hpd_pcc1 { - nvidia,pins = "hdmi_int_dp_hpd_pcc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - spdif_out_pcc2 { - nvidia,pins = "spdif_out_pcc2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spdif_in_pcc3 { - nvidia,pins = "spdif_in_pcc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - usb_vbus_en0_pcc4 { - nvidia,pins = "usb_vbus_en0_pcc4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - usb_vbus_en1_pcc5 { - nvidia,pins = "usb_vbus_en1_pcc5"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - dp_hpd0_pcc6 { - nvidia,pins = "dp_hpd0_pcc6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pcc7 { - nvidia,pins = "pcc7"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - spi2_cs1_pdd0 { - nvidia,pins = "spi2_cs1_pdd0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_sck_pee0 { - nvidia,pins = "qspi_sck_pee0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_cs_n_pee1 { - nvidia,pins = "qspi_cs_n_pee1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io0_pee2 { - nvidia,pins = "qspi_io0_pee2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io1_pee3 { - nvidia,pins = "qspi_io1_pee3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io2_pee4 { - nvidia,pins = "qspi_io2_pee4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io3_pee5 { - nvidia,pins = "qspi_io3_pee5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "core"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "jtag"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - clk_req { - nvidia,pins = "clk_req"; - nvidia,function = "sys"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - shutdown { - nvidia,pins = "shutdown"; - nvidia,function = "shutdown"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2595.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2595.dtsi deleted file mode 100644 index 6ae292da7..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2595.dtsi +++ /dev/null @@ -1,1273 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - model = "NVIDIA Tegra210 P2595 I/O board"; - compatible = "nvidia,p2595", "nvidia,tegra210"; - - pinmux: pinmux@700008d4 { - pinctrl-names = "boot"; - pinctrl-0 = <&state_boot>; - - state_boot: pinmux { - pex_l0_rst_n_pa0 { - nvidia,pins = "pex_l0_rst_n_pa0"; - nvidia,function = "pe0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l0_clkreq_n_pa1 { - nvidia,pins = "pex_l0_clkreq_n_pa1"; - nvidia,function = "pe0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_wake_n_pa2 { - nvidia,pins = "pex_wake_n_pa2"; - nvidia,function = "pe"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l1_rst_n_pa3 { - nvidia,pins = "pex_l1_rst_n_pa3"; - nvidia,function = "pe1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l1_clkreq_n_pa4 { - nvidia,pins = "pex_l1_clkreq_n_pa4"; - nvidia,function = "pe1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - sata_led_active_pa5 { - nvidia,pins = "sata_led_active_pa5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pa6 { - nvidia,pins = "pa6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_fs_pb0 { - nvidia,pins = "dap1_fs_pb0"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_din_pb1 { - nvidia,pins = "dap1_din_pb1"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_dout_pb2 { - nvidia,pins = "dap1_dout_pb2"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_sclk_pb3 { - nvidia,pins = "dap1_sclk_pb3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_mosi_pb4 { - nvidia,pins = "spi2_mosi_pb4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_miso_pb5 { - nvidia,pins = "spi2_miso_pb5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_sck_pb6 { - nvidia,pins = "spi2_sck_pb6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_cs0_pb7 { - nvidia,pins = "spi2_cs0_pb7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_mosi_pc0 { - nvidia,pins = "spi1_mosi_pc0"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_miso_pc1 { - nvidia,pins = "spi1_miso_pc1"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_sck_pc2 { - nvidia,pins = "spi1_sck_pc2"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_cs0_pc3 { - nvidia,pins = "spi1_cs0_pc3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_cs1_pc4 { - nvidia,pins = "spi1_cs1_pc4"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_sck_pc5 { - nvidia,pins = "spi4_sck_pc5"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_cs0_pc6 { - nvidia,pins = "spi4_cs0_pc6"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_mosi_pc7 { - nvidia,pins = "spi4_mosi_pc7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_miso_pd0 { - nvidia,pins = "spi4_miso_pd0"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_tx_pd1 { - nvidia,pins = "uart3_tx_pd1"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_rx_pd2 { - nvidia,pins = "uart3_rx_pd2"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_rts_pd3 { - nvidia,pins = "uart3_rts_pd3"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_cts_pd4 { - nvidia,pins = "uart3_cts_pd4"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic1_clk_pe0 { - nvidia,pins = "dmic1_clk_pe0"; - nvidia,function = "dmic1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic1_dat_pe1 { - nvidia,pins = "dmic1_dat_pe1"; - nvidia,function = "dmic1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic2_clk_pe2 { - nvidia,pins = "dmic2_clk_pe2"; - nvidia,function = "dmic2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic2_dat_pe3 { - nvidia,pins = "dmic2_dat_pe3"; - nvidia,function = "dmic2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic3_clk_pe4 { - nvidia,pins = "dmic3_clk_pe4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic3_dat_pe5 { - nvidia,pins = "dmic3_dat_pe5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pe6 { - nvidia,pins = "pe6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pe7 { - nvidia,pins = "pe7"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen3_i2c_scl_pf0 { - nvidia,pins = "gen3_i2c_scl_pf0"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen3_i2c_sda_pf1 { - nvidia,pins = "gen3_i2c_sda_pf1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - uart2_tx_pg0 { - nvidia,pins = "uart2_tx_pg0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_rx_pg1 { - nvidia,pins = "uart2_rx_pg1"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_rts_pg2 { - nvidia,pins = "uart2_rts_pg2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_cts_pg3 { - nvidia,pins = "uart2_cts_pg3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_en_ph0 { - nvidia,pins = "wifi_en_ph0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_rst_ph1 { - nvidia,pins = "wifi_rst_ph1"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_wake_ap_ph2 { - nvidia,pins = "wifi_wake_ap_ph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_wake_bt_ph3 { - nvidia,pins = "ap_wake_bt_ph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - bt_rst_ph4 { - nvidia,pins = "bt_rst_ph4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - bt_wake_ap_ph5 { - nvidia,pins = "bt_wake_ap_ph5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ph6 { - nvidia,pins = "ph6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_wake_nfc_ph7 { - nvidia,pins = "ap_wake_nfc_ph7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - nfc_en_pi0 { - nvidia,pins = "nfc_en_pi0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - nfc_int_pi1 { - nvidia,pins = "nfc_int_pi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gps_en_pi2 { - nvidia,pins = "gps_en_pi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gps_rst_pi3 { - nvidia,pins = "gps_rst_pi3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_tx_pi4 { - nvidia,pins = "uart4_tx_pi4"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_rx_pi5 { - nvidia,pins = "uart4_rx_pi5"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_rts_pi6 { - nvidia,pins = "uart4_rts_pi6"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_cts_pi7 { - nvidia,pins = "uart4_cts_pi7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pj0 { - nvidia,pins = "gen1_i2c_sda_pj0"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen1_i2c_scl_pj1 { - nvidia,pins = "gen1_i2c_scl_pj1"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen2_i2c_scl_pj2 { - nvidia,pins = "gen2_i2c_scl_pj2"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen2_i2c_sda_pj3 { - nvidia,pins = "gen2_i2c_sda_pj3"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - dap4_fs_pj4 { - nvidia,pins = "dap4_fs_pj4"; - nvidia,function = "i2s4b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_din_pj5 { - nvidia,pins = "dap4_din_pj5"; - nvidia,function = "i2s4b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_dout_pj6 { - nvidia,pins = "dap4_dout_pj6"; - nvidia,function = "i2s4b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_sclk_pj7 { - nvidia,pins = "dap4_sclk_pj7"; - nvidia,function = "i2s4b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk0 { - nvidia,pins = "pk0"; - nvidia,function = "i2s5b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk1 { - nvidia,pins = "pk1"; - nvidia,function = "i2s5b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk2 { - nvidia,pins = "pk2"; - nvidia,function = "i2s5b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk3 { - nvidia,pins = "pk3"; - nvidia,function = "i2s5b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk4 { - nvidia,pins = "pk4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk5 { - nvidia,pins = "pk5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk6 { - nvidia,pins = "pk6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk7 { - nvidia,pins = "pk7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pl0 { - nvidia,pins = "pl0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pl1 { - nvidia,pins = "pl1"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_clk_pm0 { - nvidia,pins = "sdmmc1_clk_pm0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_cmd_pm1 { - nvidia,pins = "sdmmc1_cmd_pm1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat3_pm2 { - nvidia,pins = "sdmmc1_dat3_pm2"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat2_pm3 { - nvidia,pins = "sdmmc1_dat2_pm3"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat1_pm4 { - nvidia,pins = "sdmmc1_dat1_pm4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat0_pm5 { - nvidia,pins = "sdmmc1_dat0_pm5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_clk_pp0 { - nvidia,pins = "sdmmc3_clk_pp0"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_cmd_pp1 { - nvidia,pins = "sdmmc3_cmd_pp1"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat3_pp2 { - nvidia,pins = "sdmmc3_dat3_pp2"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat2_pp3 { - nvidia,pins = "sdmmc3_dat2_pp3"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat1_pp4 { - nvidia,pins = "sdmmc3_dat1_pp4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat0_pp5 { - nvidia,pins = "sdmmc3_dat0_pp5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_mclk_ps0 { - nvidia,pins = "cam1_mclk_ps0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam2_mclk_ps1 { - nvidia,pins = "cam2_mclk_ps1"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_scl_ps2 { - nvidia,pins = "cam_i2c_scl_ps2"; - nvidia,function = "i2cvi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - cam_i2c_sda_ps3 { - nvidia,pins = "cam_i2c_sda_ps3"; - nvidia,function = "i2cvi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - cam_rst_ps4 { - nvidia,pins = "cam_rst_ps4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_af_en_ps5 { - nvidia,pins = "cam_af_en_ps5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_flash_en_ps6 { - nvidia,pins = "cam_flash_en_ps6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_pwdn_ps7 { - nvidia,pins = "cam1_pwdn_ps7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam2_pwdn_pt0 { - nvidia,pins = "cam2_pwdn_pt0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_strobe_pt1 { - nvidia,pins = "cam1_strobe_pt1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_tx_pu0 { - nvidia,pins = "uart1_tx_pu0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_rx_pu1 { - nvidia,pins = "uart1_rx_pu1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_rts_pu2 { - nvidia,pins = "uart1_rts_pu2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_cts_pu3 { - nvidia,pins = "uart1_cts_pu3"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_bl_pwm_pv0 { - nvidia,pins = "lcd_bl_pwm_pv0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_bl_en_pv1 { - nvidia,pins = "lcd_bl_en_pv1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_rst_pv2 { - nvidia,pins = "lcd_rst_pv2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_gpio1_pv3 { - nvidia,pins = "lcd_gpio1_pv3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_gpio2_pv4 { - nvidia,pins = "lcd_gpio2_pv4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_ready_pv5 { - nvidia,pins = "ap_ready_pv5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_rst_pv6 { - nvidia,pins = "touch_rst_pv6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_clk_pv7 { - nvidia,pins = "touch_clk_pv7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - modem_wake_ap_px0 { - nvidia,pins = "modem_wake_ap_px0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_int_px1 { - nvidia,pins = "touch_int_px1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - motion_int_px2 { - nvidia,pins = "motion_int_px2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - als_prox_int_px3 { - nvidia,pins = "als_prox_int_px3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - temp_alert_px4 { - nvidia,pins = "temp_alert_px4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_power_on_px5 { - nvidia,pins = "button_power_on_px5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_vol_up_px6 { - nvidia,pins = "button_vol_up_px6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_vol_down_px7 { - nvidia,pins = "button_vol_down_px7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_slide_sw_py0 { - nvidia,pins = "button_slide_sw_py0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_home_py1 { - nvidia,pins = "button_home_py1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_te_py2 { - nvidia,pins = "lcd_te_py2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_scl_py3 { - nvidia,pins = "pwr_i2c_scl_py3"; - nvidia,function = "i2cpmu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pwr_i2c_sda_py4 { - nvidia,pins = "pwr_i2c_sda_py4"; - nvidia,function = "i2cpmu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - clk_32k_out_py5 { - nvidia,pins = "clk_32k_out_py5"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz0 { - nvidia,pins = "pz0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz1 { - nvidia,pins = "pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz2 { - nvidia,pins = "pz2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz3 { - nvidia,pins = "pz3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz4 { - nvidia,pins = "pz4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz5 { - nvidia,pins = "pz5"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_fs_paa0 { - nvidia,pins = "dap2_fs_paa0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_sclk_paa1 { - nvidia,pins = "dap2_sclk_paa1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_din_paa2 { - nvidia,pins = "dap2_din_paa2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_dout_paa3 { - nvidia,pins = "dap2_dout_paa3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - aud_mclk_pbb0 { - nvidia,pins = "aud_mclk_pbb0"; - nvidia,function = "aud"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dvfs_pwm_pbb1 { - nvidia,pins = "dvfs_pwm_pbb1"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dvfs_clk_pbb2 { - nvidia,pins = "dvfs_clk_pbb2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gpio_x1_aud_pbb3 { - nvidia,pins = "gpio_x1_aud_pbb3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gpio_x3_aud_pbb4 { - nvidia,pins = "gpio_x3_aud_pbb4"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi_cec_pcc0 { - nvidia,pins = "hdmi_cec_pcc0"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - hdmi_int_dp_hpd_pcc1 { - nvidia,pins = "hdmi_int_dp_hpd_pcc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - spdif_out_pcc2 { - nvidia,pins = "spdif_out_pcc2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spdif_in_pcc3 { - nvidia,pins = "spdif_in_pcc3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - usb_vbus_en0_pcc4 { - nvidia,pins = "usb_vbus_en0_pcc4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - usb_vbus_en1_pcc5 { - nvidia,pins = "usb_vbus_en1_pcc5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - dp_hpd0_pcc6 { - nvidia,pins = "dp_hpd0_pcc6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pcc7 { - nvidia,pins = "pcc7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - spi2_cs1_pdd0 { - nvidia,pins = "spi2_cs1_pdd0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_sck_pee0 { - nvidia,pins = "qspi_sck_pee0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_cs_n_pee1 { - nvidia,pins = "qspi_cs_n_pee1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io0_pee2 { - nvidia,pins = "qspi_io0_pee2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io1_pee3 { - nvidia,pins = "qspi_io1_pee3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io2_pee4 { - nvidia,pins = "qspi_io2_pee4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io3_pee5 { - nvidia,pins = "qspi_io3_pee5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "core"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "jtag"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - clk_req { - nvidia,pins = "clk_req"; - nvidia,function = "sys"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - shutdown { - nvidia,pins = "shutdown"; - nvidia,function = "shutdown"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi deleted file mode 100644 index a9caaf7c0..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ /dev/null @@ -1,1715 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -/ { - model = "NVIDIA Tegra210 P2597 I/O board"; - compatible = "nvidia,p2597", "nvidia,tegra210"; - - aliases { - ethernet = "/usb@70090000/ethernet@1"; - }; - - host1x@50000000 { - dpaux@54040000 { - status = "okay"; - }; - - vi@54080000 { - status = "okay"; - - avdd-dsi-csi-supply = <&vdd_dsi_csi>; - - csi@838 { - status = "okay"; - }; - }; - - sor@54580000 { - status = "okay"; - - avdd-io-hdmi-dp-supply = <&avdd_1v05>; - vdd-hdmi-dp-pll-supply = <&vdd_1v8>; - hdmi-supply = <&vdd_hdmi>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) - GPIO_ACTIVE_LOW>; - }; - }; - - pinmux: pinmux@700008d4 { - pinctrl-names = "boot"; - pinctrl-0 = <&state_boot>; - - state_boot: pinmux { - pex_l0_rst_n_pa0 { - nvidia,pins = "pex_l0_rst_n_pa0"; - nvidia,function = "pe0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l0_clkreq_n_pa1 { - nvidia,pins = "pex_l0_clkreq_n_pa1"; - nvidia,function = "pe0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_wake_n_pa2 { - nvidia,pins = "pex_wake_n_pa2"; - nvidia,function = "pe"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l1_rst_n_pa3 { - nvidia,pins = "pex_l1_rst_n_pa3"; - nvidia,function = "pe1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l1_clkreq_n_pa4 { - nvidia,pins = "pex_l1_clkreq_n_pa4"; - nvidia,function = "pe1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - sata_led_active_pa5 { - nvidia,pins = "sata_led_active_pa5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pa6 { - nvidia,pins = "pa6"; - nvidia,function = "sata"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_fs_pb0 { - nvidia,pins = "dap1_fs_pb0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_din_pb1 { - nvidia,pins = "dap1_din_pb1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_dout_pb2 { - nvidia,pins = "dap1_dout_pb2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_sclk_pb3 { - nvidia,pins = "dap1_sclk_pb3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_mosi_pb4 { - nvidia,pins = "spi2_mosi_pb4"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_miso_pb5 { - nvidia,pins = "spi2_miso_pb5"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_sck_pb6 { - nvidia,pins = "spi2_sck_pb6"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_cs0_pb7 { - nvidia,pins = "spi2_cs0_pb7"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_mosi_pc0 { - nvidia,pins = "spi1_mosi_pc0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_miso_pc1 { - nvidia,pins = "spi1_miso_pc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_sck_pc2 { - nvidia,pins = "spi1_sck_pc2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_cs0_pc3 { - nvidia,pins = "spi1_cs0_pc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_cs1_pc4 { - nvidia,pins = "spi1_cs1_pc4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_sck_pc5 { - nvidia,pins = "spi4_sck_pc5"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_cs0_pc6 { - nvidia,pins = "spi4_cs0_pc6"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_mosi_pc7 { - nvidia,pins = "spi4_mosi_pc7"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_miso_pd0 { - nvidia,pins = "spi4_miso_pd0"; - nvidia,function = "spi4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_tx_pd1 { - nvidia,pins = "uart3_tx_pd1"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_rx_pd2 { - nvidia,pins = "uart3_rx_pd2"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_rts_pd3 { - nvidia,pins = "uart3_rts_pd3"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_cts_pd4 { - nvidia,pins = "uart3_cts_pd4"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic1_clk_pe0 { - nvidia,pins = "dmic1_clk_pe0"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic1_dat_pe1 { - nvidia,pins = "dmic1_dat_pe1"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic2_clk_pe2 { - nvidia,pins = "dmic2_clk_pe2"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic2_dat_pe3 { - nvidia,pins = "dmic2_dat_pe3"; - nvidia,function = "i2s3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic3_clk_pe4 { - nvidia,pins = "dmic3_clk_pe4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic3_dat_pe5 { - nvidia,pins = "dmic3_dat_pe5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pe6 { - nvidia,pins = "pe6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pe7 { - nvidia,pins = "pe7"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen3_i2c_scl_pf0 { - nvidia,pins = "gen3_i2c_scl_pf0"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen3_i2c_sda_pf1 { - nvidia,pins = "gen3_i2c_sda_pf1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - uart2_tx_pg0 { - nvidia,pins = "uart2_tx_pg0"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_rx_pg1 { - nvidia,pins = "uart2_rx_pg1"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_rts_pg2 { - nvidia,pins = "uart2_rts_pg2"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_cts_pg3 { - nvidia,pins = "uart2_cts_pg3"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_en_ph0 { - nvidia,pins = "wifi_en_ph0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_rst_ph1 { - nvidia,pins = "wifi_rst_ph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_wake_ap_ph2 { - nvidia,pins = "wifi_wake_ap_ph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_wake_bt_ph3 { - nvidia,pins = "ap_wake_bt_ph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - bt_rst_ph4 { - nvidia,pins = "bt_rst_ph4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - bt_wake_ap_ph5 { - nvidia,pins = "bt_wake_ap_ph5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ph6 { - nvidia,pins = "ph6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_wake_nfc_ph7 { - nvidia,pins = "ap_wake_nfc_ph7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - nfc_en_pi0 { - nvidia,pins = "nfc_en_pi0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - nfc_int_pi1 { - nvidia,pins = "nfc_int_pi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gps_en_pi2 { - nvidia,pins = "gps_en_pi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gps_rst_pi3 { - nvidia,pins = "gps_rst_pi3"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_tx_pi4 { - nvidia,pins = "uart4_tx_pi4"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_rx_pi5 { - nvidia,pins = "uart4_rx_pi5"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_rts_pi6 { - nvidia,pins = "uart4_rts_pi6"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_cts_pi7 { - nvidia,pins = "uart4_cts_pi7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pj0 { - nvidia,pins = "gen1_i2c_sda_pj0"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen1_i2c_scl_pj1 { - nvidia,pins = "gen1_i2c_scl_pj1"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen2_i2c_scl_pj2 { - nvidia,pins = "gen2_i2c_scl_pj2"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen2_i2c_sda_pj3 { - nvidia,pins = "gen2_i2c_sda_pj3"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - dap4_fs_pj4 { - nvidia,pins = "dap4_fs_pj4"; - nvidia,function = "i2s4b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_din_pj5 { - nvidia,pins = "dap4_din_pj5"; - nvidia,function = "i2s4b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_dout_pj6 { - nvidia,pins = "dap4_dout_pj6"; - nvidia,function = "i2s4b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_sclk_pj7 { - nvidia,pins = "dap4_sclk_pj7"; - nvidia,function = "i2s4b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk0 { - nvidia,pins = "pk0"; - nvidia,function = "i2s5b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk1 { - nvidia,pins = "pk1"; - nvidia,function = "i2s5b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk2 { - nvidia,pins = "pk2"; - nvidia,function = "i2s5b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk3 { - nvidia,pins = "pk3"; - nvidia,function = "i2s5b"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk4 { - nvidia,pins = "pk4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk5 { - nvidia,pins = "pk5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk6 { - nvidia,pins = "pk6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk7 { - nvidia,pins = "pk7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pl0 { - nvidia,pins = "pl0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pl1 { - nvidia,pins = "pl1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_clk_pm0 { - nvidia,pins = "sdmmc1_clk_pm0"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_cmd_pm1 { - nvidia,pins = "sdmmc1_cmd_pm1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat3_pm2 { - nvidia,pins = "sdmmc1_dat3_pm2"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat2_pm3 { - nvidia,pins = "sdmmc1_dat2_pm3"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat1_pm4 { - nvidia,pins = "sdmmc1_dat1_pm4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat0_pm5 { - nvidia,pins = "sdmmc1_dat0_pm5"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_clk_pp0 { - nvidia,pins = "sdmmc3_clk_pp0"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_cmd_pp1 { - nvidia,pins = "sdmmc3_cmd_pp1"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat3_pp2 { - nvidia,pins = "sdmmc3_dat3_pp2"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat2_pp3 { - nvidia,pins = "sdmmc3_dat2_pp3"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat1_pp4 { - nvidia,pins = "sdmmc3_dat1_pp4"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat0_pp5 { - nvidia,pins = "sdmmc3_dat0_pp5"; - nvidia,function = "sdmmc3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_mclk_ps0 { - nvidia,pins = "cam1_mclk_ps0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam2_mclk_ps1 { - nvidia,pins = "cam2_mclk_ps1"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_scl_ps2 { - nvidia,pins = "cam_i2c_scl_ps2"; - nvidia,function = "i2cvi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - cam_i2c_sda_ps3 { - nvidia,pins = "cam_i2c_sda_ps3"; - nvidia,function = "i2cvi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - cam_rst_ps4 { - nvidia,pins = "cam_rst_ps4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_af_en_ps5 { - nvidia,pins = "cam_af_en_ps5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_flash_en_ps6 { - nvidia,pins = "cam_flash_en_ps6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_pwdn_ps7 { - nvidia,pins = "cam1_pwdn_ps7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam2_pwdn_pt0 { - nvidia,pins = "cam2_pwdn_pt0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_strobe_pt1 { - nvidia,pins = "cam1_strobe_pt1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_tx_pu0 { - nvidia,pins = "uart1_tx_pu0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_rx_pu1 { - nvidia,pins = "uart1_rx_pu1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_rts_pu2 { - nvidia,pins = "uart1_rts_pu2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_cts_pu3 { - nvidia,pins = "uart1_cts_pu3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_bl_pwm_pv0 { - nvidia,pins = "lcd_bl_pwm_pv0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_bl_en_pv1 { - nvidia,pins = "lcd_bl_en_pv1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_rst_pv2 { - nvidia,pins = "lcd_rst_pv2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_gpio1_pv3 { - nvidia,pins = "lcd_gpio1_pv3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_gpio2_pv4 { - nvidia,pins = "lcd_gpio2_pv4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_ready_pv5 { - nvidia,pins = "ap_ready_pv5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_rst_pv6 { - nvidia,pins = "touch_rst_pv6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_clk_pv7 { - nvidia,pins = "touch_clk_pv7"; - nvidia,function = "touch"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - modem_wake_ap_px0 { - nvidia,pins = "modem_wake_ap_px0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_int_px1 { - nvidia,pins = "touch_int_px1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - motion_int_px2 { - nvidia,pins = "motion_int_px2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - als_prox_int_px3 { - nvidia,pins = "als_prox_int_px3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - temp_alert_px4 { - nvidia,pins = "temp_alert_px4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_power_on_px5 { - nvidia,pins = "button_power_on_px5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_vol_up_px6 { - nvidia,pins = "button_vol_up_px6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_vol_down_px7 { - nvidia,pins = "button_vol_down_px7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_slide_sw_py0 { - nvidia,pins = "button_slide_sw_py0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_home_py1 { - nvidia,pins = "button_home_py1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_te_py2 { - nvidia,pins = "lcd_te_py2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_scl_py3 { - nvidia,pins = "pwr_i2c_scl_py3"; - nvidia,function = "i2cpmu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pwr_i2c_sda_py4 { - nvidia,pins = "pwr_i2c_sda_py4"; - nvidia,function = "i2cpmu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - clk_32k_out_py5 { - nvidia,pins = "clk_32k_out_py5"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz0 { - nvidia,pins = "pz0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz1 { - nvidia,pins = "pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz2 { - nvidia,pins = "pz2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz3 { - nvidia,pins = "pz3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz4 { - nvidia,pins = "pz4"; - nvidia,function = "sdmmc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz5 { - nvidia,pins = "pz5"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_fs_paa0 { - nvidia,pins = "dap2_fs_paa0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_sclk_paa1 { - nvidia,pins = "dap2_sclk_paa1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_din_paa2 { - nvidia,pins = "dap2_din_paa2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_dout_paa3 { - nvidia,pins = "dap2_dout_paa3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - aud_mclk_pbb0 { - nvidia,pins = "aud_mclk_pbb0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dvfs_pwm_pbb1 { - nvidia,pins = "dvfs_pwm_pbb1"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dvfs_clk_pbb2 { - nvidia,pins = "dvfs_clk_pbb2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gpio_x1_aud_pbb3 { - nvidia,pins = "gpio_x1_aud_pbb3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gpio_x3_aud_pbb4 { - nvidia,pins = "gpio_x3_aud_pbb4"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi_cec_pcc0 { - nvidia,pins = "hdmi_cec_pcc0"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - hdmi_int_dp_hpd_pcc1 { - nvidia,pins = "hdmi_int_dp_hpd_pcc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - spdif_out_pcc2 { - nvidia,pins = "spdif_out_pcc2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spdif_in_pcc3 { - nvidia,pins = "spdif_in_pcc3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - usb_vbus_en0_pcc4 { - nvidia,pins = "usb_vbus_en0_pcc4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - usb_vbus_en1_pcc5 { - nvidia,pins = "usb_vbus_en1_pcc5"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - dp_hpd0_pcc6 { - nvidia,pins = "dp_hpd0_pcc6"; - nvidia,function = "dp"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pcc7 { - nvidia,pins = "pcc7"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - spi2_cs1_pdd0 { - nvidia,pins = "spi2_cs1_pdd0"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_sck_pee0 { - nvidia,pins = "qspi_sck_pee0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_cs_n_pee1 { - nvidia,pins = "qspi_cs_n_pee1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io0_pee2 { - nvidia,pins = "qspi_io0_pee2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io1_pee3 { - nvidia,pins = "qspi_io1_pee3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io2_pee4 { - nvidia,pins = "qspi_io2_pee4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io3_pee5 { - nvidia,pins = "qspi_io3_pee5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "core"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "jtag"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - clk_req { - nvidia,pins = "clk_req"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - shutdown { - nvidia,pins = "shutdown"; - nvidia,function = "shutdown"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - }; - - dvfs_pwm_active_state: dvfs_pwm_active { - dvfs_pwm_pbb1 { - nvidia,pins = "dvfs_pwm_pbb1"; - nvidia,tristate = ; - }; - }; - - dvfs_pwm_inactive_state: dvfs_pwm_inactive { - dvfs_pwm_pbb1 { - nvidia,pins = "dvfs_pwm_pbb1"; - nvidia,tristate = ; - }; - }; - }; - - pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - - exp1: gpio@74 { - compatible = "ti,tca9539"; - reg = <0x74>; - - #gpio-cells = <2>; - gpio-controller; - }; - - exp2: gpio@77 { - compatible = "ti,tca9539"; - reg = <0x77>; - - #gpio-cells = <2>; - gpio-controller; - }; - }; - - /* HDMI DDC */ - hdmi_ddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - sata@70020000 { - status = "okay"; - phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; - }; - - hda@70030000 { - nvidia,model = "jetson-tx1-hda"; - status = "okay"; - }; - - usb@70090000 { - phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, - <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, - <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, - <&{/padctl@7009f000/pads/usb2/lanes/usb2-3}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-5}>; - phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", "usb3-0", - "usb3-1"; - dvddio-pex-supply = <&vdd_pex_1v05>; - hvddio-pex-supply = <&vdd_1v8>; - avdd-usb-supply = <&vdd_3v3_sys>; - /* XXX what are these? */ - avdd-pll-utmip-supply = <&vdd_1v8>; - avdd-pll-uerefe-supply = <&vdd_pex_1v05>; - dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>; - hvdd-usb-ss-pll-e-supply = <&vdd_1v8>; - - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - ethernet@1 { - reg = <1>; - }; - }; - - padctl@7009f000 { - status = "okay"; - - avdd-pll-utmip-supply = <&vdd_1v8>; - avdd-pll-uerefe-supply = <&avdd_1v05_pll>; - dvdd-pex-pll-supply = <&vdd_pex_1v05>; - hvdd-pex-pll-e-supply = <&vdd_1v8>; - - pads { - usb2 { - status = "okay"; - - lanes { - micro_b: usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-3 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - nvidia,function = "pcie-x1"; - status = "okay"; - }; - - pcie-1 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-2 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-3 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-4 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-5 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-6 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - }; - }; - - sata { - status = "okay"; - - lanes { - sata-0 { - nvidia,function = "sata"; - status = "okay"; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "okay"; - vbus-supply = <&vdd_usb_vbus_otg>; - usb-role-switch; - mode = "otg"; - - connector { - compatible = "gpio-usb-b-connector", - "usb-b-connector"; - label = "micro-USB"; - type = "micro"; - vbus-gpios = <&gpio TEGRA_GPIO(Z, 0) - GPIO_ACTIVE_LOW>; - id-gpios = <&pmic 0 GPIO_ACTIVE_HIGH>; - }; - }; - - usb2-1 { - status = "okay"; - vbus-supply = <&vdd_5v0_rtl>; - mode = "host"; - }; - - usb2-2 { - status = "okay"; - vbus-supply = <&vdd_usb_vbus>; - mode = "host"; - }; - - usb2-3 { - status = "okay"; - mode = "host"; - }; - - usb3-0 { - nvidia,usb2-companion = <1>; - status = "okay"; - }; - - usb3-1 { - nvidia,usb2-companion = <2>; - status = "okay"; - }; - }; - }; - - /* MMC/SD */ - mmc@700b0000 { - status = "okay"; - bus-width = <4>; - - cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; - - vqmmc-supply = <&vddio_sdmmc>; - vmmc-supply = <&vdd_3v3_sd>; - }; - - usb@700d0000 { - status = "okay"; - phys = <µ_b>; - phy-names = "usb2-0"; - avddio-usb-supply = <&vdd_3v3_sys>; - hvdd-usb-supply = <&vdd_1v8>; - }; - - gpio-keys { - compatible = "gpio-keys"; - label = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - - volume_down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume_up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - vdd_sys_mux: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "VDD_SYS_MUX"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "VDD_5V0_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_sys_mux>; - }; - - vdd_3v3_sys: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_sys_mux>; - - regulator-enable-ramp-delay = <160>; - regulator-disable-ramp-delay = <10000>; - }; - - vdd_5v0_io: regulator@3 { - compatible = "regulator-fixed"; - regulator-name = "VDD_5V0_IO_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_3v3_sd: regulator@4 { - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3_SD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - - regulator-enable-ramp-delay = <472>; - regulator-disable-ramp-delay = <4880>; - }; - - vdd_dsi_csi: regulator@5 { - compatible = "regulator-fixed"; - regulator-name = "AVDD_DSI_CSI_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - vin-supply = <&vdd_sys_1v2>; - }; - - vdd_3v3_dis: regulator@6 { - compatible = "regulator-fixed"; - regulator-name = "VDD_DIS_3V3_LCD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_1v8_dis: regulator@7 { - compatible = "regulator-fixed"; - regulator-name = "VDD_LCD_1V8_DIS"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - gpio = <&exp1 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_1v8>; - }; - - vdd_5v0_rtl: regulator@8 { - compatible = "regulator-fixed"; - regulator-name = "RTL_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb_vbus: regulator@9 { - compatible = "regulator-fixed"; - regulator-name = "USB_VBUS_EN1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_hdmi: regulator@10 { - compatible = "regulator-fixed"; - regulator-name = "VDD_HDMI_5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&exp1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_cam_1v2: regulator@11 { - compatible = "regulator-fixed"; - regulator-name = "vdd-cam-1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&exp2 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_cam_2v8: regulator@12 { - compatible = "regulator-fixed"; - regulator-name = "vdd-cam-2v8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&exp1 13 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_cam_1v8: regulator@13 { - compatible = "regulator-fixed"; - regulator-name = "vdd-cam-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&exp2 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_usb_vbus_otg: regulator@14 { - compatible = "regulator-fixed"; - regulator-name = "USB_VBUS_EN0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894-0050-a08.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2894-0050-a08.dts deleted file mode 100644 index 7ffb351b5..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894-0050-a08.dts +++ /dev/null @@ -1,9 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra210-p2894.dtsi" - -/ { - model = "NVIDIA Shield TV"; - compatible = "nvidia,p2894-0050-a08", "nvidia,darcy", "nvidia,tegra210"; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi deleted file mode 100644 index 41beab626..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ /dev/null @@ -1,1832 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include -#include -#include -#include -#include "tegra210.dtsi" - -/ { - aliases { - serial0 = &uarta; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0xc0000000>; - }; - - pinmux: pinmux@700008d4 { - status = "okay"; - pinctrl-names = "boot"; - pinctrl-0 = <&state_boot>; - - state_boot: pinmux { - pex_l0_rst_n_pa0 { - nvidia,pins = "pex_l0_rst_n_pa0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l0_clkreq_n_pa1 { - nvidia,pins = "pex_l0_clkreq_n_pa1"; - nvidia,function = "pe0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_wake_n_pa2 { - nvidia,pins = "pex_wake_n_pa2"; - nvidia,function = "pe"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l1_rst_n_pa3 { - nvidia,pins = "pex_l1_rst_n_pa3"; - nvidia,function = "pe1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l1_clkreq_n_pa4 { - nvidia,pins = "pex_l1_clkreq_n_pa4"; - nvidia,function = "pe1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - sata_led_active_pa5 { - nvidia,pins = "sata_led_active_pa5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pa6 { - nvidia,pins = "pa6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_fs_pb0 { - nvidia,pins = "dap1_fs_pb0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_din_pb1 { - nvidia,pins = "dap1_din_pb1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_dout_pb2 { - nvidia,pins = "dap1_dout_pb2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_sclk_pb3 { - nvidia,pins = "dap1_sclk_pb3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_mosi_pb4 { - nvidia,pins = "spi2_mosi_pb4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_miso_pb5 { - nvidia,pins = "spi2_miso_pb5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_sck_pb6 { - nvidia,pins = "spi2_sck_pb6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_cs0_pb7 { - nvidia,pins = "spi2_cs0_pb7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_mosi_pc0 { - nvidia,pins = "spi1_mosi_pc0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_miso_pc1 { - nvidia,pins = "spi1_miso_pc1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_sck_pc2 { - nvidia,pins = "spi1_sck_pc2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_cs0_pc3 { - nvidia,pins = "spi1_cs0_pc3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_cs1_pc4 { - nvidia,pins = "spi1_cs1_pc4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_sck_pc5 { - nvidia,pins = "spi4_sck_pc5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_cs0_pc6 { - nvidia,pins = "spi4_cs0_pc6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_mosi_pc7 { - nvidia,pins = "spi4_mosi_pc7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_miso_pd0 { - nvidia,pins = "spi4_miso_pd0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_tx_pd1 { - nvidia,pins = "uart3_tx_pd1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_rx_pd2 { - nvidia,pins = "uart3_rx_pd2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_rts_pd3 { - nvidia,pins = "uart3_rts_pd3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_cts_pd4 { - nvidia,pins = "uart3_cts_pd4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic1_clk_pe0 { - nvidia,pins = "dmic1_clk_pe0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic1_dat_pe1 { - nvidia,pins = "dmic1_dat_pe1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic2_clk_pe2 { - nvidia,pins = "dmic2_clk_pe2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic2_dat_pe3 { - nvidia,pins = "dmic2_dat_pe3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic3_clk_pe4 { - nvidia,pins = "dmic3_clk_pe4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic3_dat_pe5 { - nvidia,pins = "dmic3_dat_pe5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pe6 { - nvidia,pins = "pe6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pe7 { - nvidia,pins = "pe7"; - nvidia,function = "pwm3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen3_i2c_scl_pf0 { - nvidia,pins = "gen3_i2c_scl_pf0"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen3_i2c_sda_pf1 { - nvidia,pins = "gen3_i2c_sda_pf1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - uart2_tx_pg0 { - nvidia,pins = "uart2_tx_pg0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_rx_pg1 { - nvidia,pins = "uart2_rx_pg1"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_rts_pg2 { - nvidia,pins = "uart2_rts_pg2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_cts_pg3 { - nvidia,pins = "uart2_cts_pg3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_en_ph0 { - nvidia,pins = "wifi_en_ph0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_rst_ph1 { - nvidia,pins = "wifi_rst_ph1"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_wake_ap_ph2 { - nvidia,pins = "wifi_wake_ap_ph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_wake_bt_ph3 { - nvidia,pins = "ap_wake_bt_ph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - bt_rst_ph4 { - nvidia,pins = "bt_rst_ph4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - bt_wake_ap_ph5 { - nvidia,pins = "bt_wake_ap_ph5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ph6 { - nvidia,pins = "ph6"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_wake_nfc_ph7 { - nvidia,pins = "ap_wake_nfc_ph7"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - nfc_en_pi0 { - nvidia,pins = "nfc_en_pi0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - nfc_int_pi1 { - nvidia,pins = "nfc_int_pi1"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gps_en_pi2 { - nvidia,pins = "gps_en_pi2"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gps_rst_pi3 { - nvidia,pins = "gps_rst_pi3"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_tx_pi4 { - nvidia,pins = "uart4_tx_pi4"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_rx_pi5 { - nvidia,pins = "uart4_rx_pi5"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_rts_pi6 { - nvidia,pins = "uart4_rts_pi6"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_cts_pi7 { - nvidia,pins = "uart4_cts_pi7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pj0 { - nvidia,pins = "gen1_i2c_sda_pj0"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen1_i2c_scl_pj1 { - nvidia,pins = "gen1_i2c_scl_pj1"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen2_i2c_scl_pj2 { - nvidia,pins = "gen2_i2c_scl_pj2"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen2_i2c_sda_pj3 { - nvidia,pins = "gen2_i2c_sda_pj3"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - dap4_fs_pj4 { - nvidia,pins = "dap4_fs_pj4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_din_pj5 { - nvidia,pins = "dap4_din_pj5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_dout_pj6 { - nvidia,pins = "dap4_dout_pj6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_sclk_pj7 { - nvidia,pins = "dap4_sclk_pj7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk0 { - nvidia,pins = "pk0"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk1 { - nvidia,pins = "pk1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk2 { - nvidia,pins = "pk2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk3 { - nvidia,pins = "pk3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk4 { - nvidia,pins = "pk4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk5 { - nvidia,pins = "pk5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk6 { - nvidia,pins = "pk6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk7 { - nvidia,pins = "pk7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pl0 { - nvidia,pins = "pl0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pl1 { - nvidia,pins = "pl1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_clk_pm0 { - nvidia,pins = "sdmmc1_clk_pm0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_cmd_pm1 { - nvidia,pins = "sdmmc1_cmd_pm1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat3_pm2 { - nvidia,pins = "sdmmc1_dat3_pm2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat2_pm3 { - nvidia,pins = "sdmmc1_dat2_pm3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat1_pm4 { - nvidia,pins = "sdmmc1_dat1_pm4"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat0_pm5 { - nvidia,pins = "sdmmc1_dat0_pm5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_clk_pp0 { - nvidia,pins = "sdmmc3_clk_pp0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_cmd_pp1 { - nvidia,pins = "sdmmc3_cmd_pp1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat3_pp2 { - nvidia,pins = "sdmmc3_dat3_pp2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat2_pp3 { - nvidia,pins = "sdmmc3_dat2_pp3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat1_pp4 { - nvidia,pins = "sdmmc3_dat1_pp4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat0_pp5 { - nvidia,pins = "sdmmc3_dat0_pp5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_mclk_ps0 { - nvidia,pins = "cam1_mclk_ps0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam2_mclk_ps1 { - nvidia,pins = "cam2_mclk_ps1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_scl_ps2 { - nvidia,pins = "cam_i2c_scl_ps2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - cam_i2c_sda_ps3 { - nvidia,pins = "cam_i2c_sda_ps3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - cam_rst_ps4 { - nvidia,pins = "cam_rst_ps4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_af_en_ps5 { - nvidia,pins = "cam_af_en_ps5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_flash_en_ps6 { - nvidia,pins = "cam_flash_en_ps6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_pwdn_ps7 { - nvidia,pins = "cam1_pwdn_ps7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam2_pwdn_pt0 { - nvidia,pins = "cam2_pwdn_pt0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_strobe_pt1 { - nvidia,pins = "cam1_strobe_pt1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_tx_pu0 { - nvidia,pins = "uart1_tx_pu0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_rx_pu1 { - nvidia,pins = "uart1_rx_pu1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_rts_pu2 { - nvidia,pins = "uart1_rts_pu2"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_cts_pu3 { - nvidia,pins = "uart1_cts_pu3"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_bl_pwm_pv0 { - nvidia,pins = "lcd_bl_pwm_pv0"; - nvidia,function = "pwm0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_bl_en_pv1 { - nvidia,pins = "lcd_bl_en_pv1"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_rst_pv2 { - nvidia,pins = "lcd_rst_pv2"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_gpio1_pv3 { - nvidia,pins = "lcd_gpio1_pv3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_gpio2_pv4 { - nvidia,pins = "lcd_gpio2_pv4"; - nvidia,function = "pwm1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_ready_pv5 { - nvidia,pins = "ap_ready_pv5"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_rst_pv6 { - nvidia,pins = "touch_rst_pv6"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_clk_pv7 { - nvidia,pins = "touch_clk_pv7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - modem_wake_ap_px0 { - nvidia,pins = "modem_wake_ap_px0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_int_px1 { - nvidia,pins = "touch_int_px1"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - motion_int_px2 { - nvidia,pins = "motion_int_px2"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - als_prox_int_px3 { - nvidia,pins = "als_prox_int_px3"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - temp_alert_px4 { - nvidia,pins = "temp_alert_px4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_power_on_px5 { - nvidia,pins = "button_power_on_px5"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_vol_up_px6 { - nvidia,pins = "button_vol_up_px6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_vol_down_px7 { - nvidia,pins = "button_vol_down_px7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_slide_sw_py0 { - nvidia,pins = "button_slide_sw_py0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_home_py1 { - nvidia,pins = "button_home_py1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_te_py2 { - nvidia,pins = "lcd_te_py2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_scl_py3 { - nvidia,pins = "pwr_i2c_scl_py3"; - nvidia,function = "i2cpmu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pwr_i2c_sda_py4 { - nvidia,pins = "pwr_i2c_sda_py4"; - nvidia,function = "i2cpmu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - clk_32k_out_py5 { - nvidia,pins = "clk_32k_out_py5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz0 { - nvidia,pins = "pz0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz1 { - nvidia,pins = "pz1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz2 { - nvidia,pins = "pz2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz3 { - nvidia,pins = "pz3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz4 { - nvidia,pins = "pz4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz5 { - nvidia,pins = "pz5"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_fs_paa0 { - nvidia,pins = "dap2_fs_paa0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_sclk_paa1 { - nvidia,pins = "dap2_sclk_paa1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_din_paa2 { - nvidia,pins = "dap2_din_paa2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_dout_paa3 { - nvidia,pins = "dap2_dout_paa3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - aud_mclk_pbb0 { - nvidia,pins = "aud_mclk_pbb0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dvfs_pwm_pbb1 { - nvidia,pins = "dvfs_pwm_pbb1"; - nvidia,function = "cldvfs"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dvfs_clk_pbb2 { - nvidia,pins = "dvfs_clk_pbb2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gpio_x1_aud_pbb3 { - nvidia,pins = "gpio_x1_aud_pbb3"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gpio_x3_aud_pbb4 { - nvidia,pins = "gpio_x3_aud_pbb4"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi_cec_pcc0 { - nvidia,pins = "hdmi_cec_pcc0"; - nvidia,function = "cec"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - hdmi_int_dp_hpd_pcc1 { - nvidia,pins = "hdmi_int_dp_hpd_pcc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - spdif_out_pcc2 { - nvidia,pins = "spdif_out_pcc2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spdif_in_pcc3 { - nvidia,pins = "spdif_in_pcc3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - usb_vbus_en0_pcc4 { - nvidia,pins = "usb_vbus_en0_pcc4"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - usb_vbus_en1_pcc5 { - nvidia,pins = "usb_vbus_en1_pcc5"; - nvidia,function = "usb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - dp_hpd0_pcc6 { - nvidia,pins = "dp_hpd0_pcc6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pcc7 { - nvidia,pins = "pcc7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - spi2_cs1_pdd0 { - nvidia,pins = "spi2_cs1_pdd0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_sck_pee0 { - nvidia,pins = "qspi_sck_pee0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_cs_n_pee1 { - nvidia,pins = "qspi_cs_n_pee1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io0_pee2 { - nvidia,pins = "qspi_io0_pee2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io1_pee3 { - nvidia,pins = "qspi_io1_pee3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io2_pee4 { - nvidia,pins = "qspi_io2_pee4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io3_pee5 { - nvidia,pins = "qspi_io3_pee5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "core"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "jtag"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - clk_req { - nvidia,pins = "clk_req"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - shutdown { - nvidia,pins = "shutdown"; - nvidia,function = "shutdown"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - }; - }; - - serial@70006000 { - status = "okay"; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: pmic@3c { - compatible = "maxim,max77620"; - reg = <0x3c>; - interrupts = ; - - #interrupt-cells = <2>; - interrupt-controller; - - gpio-controller; - #gpio-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&max77620_default>; - - max77620_default: pinmux@0 { - gpio0 { - pins = "gpio0"; - function = "gpio"; - }; - - gpio1 { - pins = "gpio1"; - function = "fps-out"; - drive-push-pull = <1>; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <7>; - maxim,active-fps-power-down-slot = <0>; - }; - - gpio2 { - pins = "gpio2"; - function = "fps-out"; - drive-open-drain = <1>; - maxim,active-fps-source = ; - }; - - gpio3 { - pins = "gpio3"; - function = "fps-out"; - drive-open-drain = <1>; - maxim,active-fps-source = ; - }; - - gpio4 { - pins = "gpio4"; - function = "32k-out1"; - }; - - gpio5_6_7 { - pins = "gpio5", "gpio6", "gpio7"; - function = "gpio"; - drive-push-pull = <1>; - }; - }; - - gpio@0 { - gpio-hog; - output-high; - gpios = <2 GPIO_ACTIVE_HIGH>, - <7 GPIO_ACTIVE_HIGH>; - }; - - fps { - #address-cells = <1>; - #size-cells = <0>; - - fps0 { - reg = <0>; - maxim,fps-event-source = ; - }; - - fps1 { - reg = <1>; - maxim,fps-event-source = ; - maxim,device-state-on-disabled-event = ; - }; - - fps2 { - reg = <2>; - maxim,fps-event-source = ; - }; - }; - - regulators { - in-ldo0-1-supply = <&max77620_sd2>; - in-ldo7-8-supply = <&max77620_sd2>; - - max77620_sd0: sd0 { - regulator-name = "vdd-core"; - regulator-enable-ramp-delay = <146>; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-ramp-delay = <27500>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-source = ; - }; - - max77620_sd1: sd1 { - regulator-name = "vddio-ddr"; - regulator-enable-ramp-delay = <130>; - regulator-ramp-delay = <27500>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - }; - - max77620_sd2: sd2 { - regulator-name = "vdd-pre-reg"; - regulator-enable-ramp-delay = <176>; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-ramp-delay = <27500>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - maxim,suspend-fps-source = ; - }; - - max77620_sd3: sd3 { - regulator-name = "vdd-1v8"; - regulator-enable-ramp-delay = <242>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <27500>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - }; - - max77620_ldo0: ldo0 { - regulator-name = "avdd-sys"; - regulator-enable-ramp-delay = <26>; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-ramp-delay = <100000>; - regulator-boot-on; - - maxim,active-fps-source = ; - }; - - max77620_ldo1: ldo1 { - regulator-name = "vdd-pex"; - regulator-enable-ramp-delay = <22>; - regulator-min-microvolt = <1075000>; - regulator-max-microvolt = <1075000>; - regulator-ramp-delay = <100000>; - regulator-always-on; - - maxim,active-fps-source = ; - }; - - max77620_ldo2: ldo2 { - regulator-name = "vddio-sdmmc3"; - regulator-enable-ramp-delay = <62>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <100000>; - - maxim,active-fps-source = ; - }; - - max77620_ldo3: ldo3 { - regulator-name = "vdd-3v3-eth"; - regulator-enable-ramp-delay = <50>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <100000>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - }; - - max77620_ldo4: ldo4 { - regulator-name = "vdd-rtc"; - regulator-enable-ramp-delay = <22>; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-ramp-delay = <100000>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - }; - - max77620_ldo5: ldo5 { - regulator-name = "avdd-ts-hv"; - regulator-enable-ramp-delay = <62>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <100000>; - - maxim,active-fps-source = ; - }; - - max77620_ldo6: ldo6 { - regulator-name = "vdd-ts"; - regulator-enable-ramp-delay = <36>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <100000>; - regulator-boot-on; - - maxim,active-fps-source = ; - }; - - max77620_ldo7: ldo7 { - regulator-name = "vdd-gen-pll-edp"; - regulator-enable-ramp-delay = <24>; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <100000>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - maxim,suspend-fps-source = ; - }; - - max77620_ldo8: ldo8 { - regulator-name = "vdd-hdmi-dp"; - regulator-enable-ramp-delay = <22>; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <100000>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - }; - }; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - nvidia,cpu-pwr-good-time = <0>; - nvidia,cpu-pwr-off-time = <0>; - nvidia,core-pwr-good-time = <4587 3876>; - nvidia,core-pwr-off-time = <39065>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - status = "okay"; - }; - - mmc@700b0600 { - bus-width = <8>; - non-removable; - status = "okay"; - }; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - status = "okay"; - - power { - debounce-interval = <30>; - gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; - label = "Power"; - linux,code = ; - wakeup-event-action = ; - wakeup-source; - }; - }; - - cpus { - cpu@0 { - enable-method = "psci"; - }; - - cpu@1 { - enable-method = "psci"; - }; - - cpu@2 { - enable-method = "psci"; - }; - - cpu@3 { - enable-method = "psci"; - }; - - idle-states { - cpu-sleep { - status = "okay"; - }; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - battery_reg: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vdd-ac-bat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vdd_3v3: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "vdd-3v3"; - regulator-enable-ramp-delay = <160>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - - gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - max77620_gpio7: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "max77620-gpio7"; - regulator-enable-ramp-delay = <240>; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - vin-supply = <&max77620_ldo0>; - regulator-always-on; - regulator-boot-on; - - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - lcd_bl_en: regulator@3 { - compatible = "regulator-fixed"; - regulator-name = "lcd-bl-en"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - - gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - en_vdd_sd: regulator@4 { - compatible = "regulator-fixed"; - regulator-name = "en-vdd-sd"; - regulator-enable-ramp-delay = <472>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3>; - - gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - en_vdd_cam: regulator@5 { - compatible = "regulator-fixed"; - regulator-name = "en-vdd-cam"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_sys_boost: regulator@6 { - compatible = "regulator-fixed"; - regulator-name = "vdd-sys-boost"; - regulator-enable-ramp-delay = <3090>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_hdmi: regulator@7 { - compatible = "regulator-fixed"; - regulator-name = "vdd-hdmi"; - regulator-enable-ramp-delay = <468>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vdd_sys_boost>; - regulator-boot-on; - - gpio = <&gpio TEGRA_GPIO(CC, 7) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - en_vdd_cpu_fixed: regulator@8 { - compatible = "regulator-fixed"; - regulator-name = "vdd-cpu-fixed"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - vdd_aux_3v3: regulator@9 { - compatible = "regulator-fixed"; - regulator-name = "aux-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_snsr_pm: regulator@10 { - compatible = "regulator-fixed"; - regulator-name = "snsr_pm"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - enable-active-high; - }; - - vdd_usb_5v0: regulator@11 { - compatible = "regulator-fixed"; - status = "disabled"; - regulator-name = "vdd-usb-5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vdd_3v3>; - - enable-active-high; - }; - - vdd_cdc_1v2_aud: regulator@101 { - compatible = "regulator-fixed"; - status = "disabled"; - regulator-name = "vdd_cdc_1v2_aud"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - startup-delay-us = <250000>; - - enable-active-high; - }; - - vdd_disp_3v0: regulator@12 { - compatible = "regulator-fixed"; - regulator-name = "vdd-disp-3v0"; - regulator-enable-ramp-delay = <232>; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - - gpio = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_fan: regulator@13 { - compatible = "regulator-fixed"; - regulator-name = "vdd-fan"; - regulator-enable-ramp-delay = <284>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio TEGRA_GPIO(E, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usb_vbus1: regulator@14 { - compatible = "regulator-fixed"; - regulator-name = "usb-vbus1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - }; - - usb_vbus2: regulator@15 { - compatible = "regulator-fixed"; - regulator-name = "usb-vbus2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - }; - - vdd_3v3_eth: regulator@16 { - compatible = "regulator-fixed"; - regulator-name = "vdd-3v3-eth-a02"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - }; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts deleted file mode 100644 index 859241db4..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ /dev/null @@ -1,873 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include -#include - -#include "tegra210.dtsi" - -/ { - model = "NVIDIA Jetson Nano Developer Kit"; - compatible = "nvidia,p3450-0000", "nvidia,tegra210"; - - aliases { - ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0"; - rtc0 = "/i2c@7000d000/pmic@3c"; - rtc1 = "/rtc@7000e000"; - serial0 = &uarta; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x1 0x0>; - }; - - pcie@1003000 { - status = "okay"; - - avdd-pll-uerefe-supply = <&vdd_pex_1v05>; - hvddio-pex-supply = <&vdd_1v8>; - dvddio-pex-supply = <&vdd_pex_1v05>; - dvdd-pex-pll-supply = <&vdd_pex_1v05>; - hvdd-pex-pll-e-supply = <&vdd_1v8>; - vddio-pex-ctl-supply = <&vdd_1v8>; - - pci@1,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; - phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3"; - nvidia,num-lanes = <4>; - status = "okay"; - }; - - pci@2,0 { - phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; - phy-names = "pcie-0"; - status = "okay"; - - ethernet@0,0 { - reg = <0x000000 0 0 0 0>; - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - }; - }; - - host1x@50000000 { - dpaux@54040000 { - status = "okay"; - }; - - vi@54080000 { - status = "okay"; - - avdd-dsi-csi-supply = <&vdd_sys_1v2>; - - csi@838 { - status = "okay"; - }; - }; - - sor@54540000 { - status = "okay"; - - avdd-io-hdmi-dp-supply = <&avdd_io_edp_1v05>; - vdd-hdmi-dp-pll-supply = <&vdd_1v8>; - - nvidia,xbar-cfg = <2 1 0 3 4>; - nvidia,dpaux = <&dpaux>; - }; - - sor@54580000 { - status = "okay"; - - avdd-io-hdmi-dp-supply = <&avdd_1v05>; - vdd-hdmi-dp-pll-supply = <&vdd_1v8>; - hdmi-supply = <&vdd_hdmi>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) - GPIO_ACTIVE_LOW>; - nvidia,xbar-cfg = <0 1 2 3 4>; - }; - - dpaux@545c0000 { - status = "okay"; - }; - - i2c@546c0000 { - status = "okay"; - }; - }; - - gpu@57000000 { - vdd-supply = <&vdd_gpu>; - status = "okay"; - }; - - pinmux@700008d4 { - dvfs_pwm_active_state: dvfs_pwm_active { - dvfs_pwm_pbb1 { - nvidia,pins = "dvfs_pwm_pbb1"; - nvidia,tristate = ; - }; - }; - - dvfs_pwm_inactive_state: dvfs_pwm_inactive { - dvfs_pwm_pbb1 { - nvidia,pins = "dvfs_pwm_pbb1"; - nvidia,tristate = ; - }; - }; - }; - - /* debug port */ - serial@70006000 { - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <100000>; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - - label = "module"; - vcc-supply = <&vdd_1v8>; - address-width = <8>; - pagesize = <8>; - size = <256>; - read-only; - }; - - eeprom@57 { - compatible = "atmel,24c02"; - reg = <0x57>; - - label = "system"; - vcc-supply = <&vdd_1v8>; - address-width = <8>; - pagesize = <8>; - size = <256>; - read-only; - }; - }; - - hdmi_ddc: i2c@7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: pmic@3c { - compatible = "maxim,max77620"; - reg = <0x3c>; - interrupt-parent = <&tegra_pmc>; - interrupts = <51 IRQ_TYPE_LEVEL_LOW>; - - #interrupt-cells = <2>; - interrupt-controller; - - #gpio-cells = <2>; - gpio-controller; - - pinctrl-names = "default"; - pinctrl-0 = <&max77620_default>; - - max77620_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - }; - - gpio1 { - pins = "gpio1"; - function = "fps-out"; - drive-push-pull = <1>; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - - gpio2 { - pins = "gpio2"; - function = "fps-out"; - drive-open-drain = <1>; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - - gpio3 { - pins = "gpio3"; - function = "fps-out"; - drive-open-drain = <1>; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <4>; - maxim,active-fps-power-down-slot = <3>; - }; - - gpio4 { - pins = "gpio4"; - function = "32k-out1"; - }; - - gpio5_6_7 { - pins = "gpio5", "gpio6", "gpio7"; - function = "gpio"; - drive-push-pull = <1>; - }; - }; - - fps { - fps0 { - maxim,fps-event-source = ; - maxim,suspend-fps-time-period-us = <5120>; - }; - - fps1 { - maxim,fps-event-source = ; - maxim,suspend-fps-time-period-us = <5120>; - }; - - fps2 { - maxim,fps-event-source = ; - }; - }; - - regulators { - in-ldo0-1-supply = <&vdd_pre>; - in-ldo2-supply = <&vdd_3v3_sys>; - in-ldo3-5-supply = <&vdd_1v8>; - in-ldo4-6-supply = <&vdd_5v0_sys>; - in-ldo7-8-supply = <&vdd_pre>; - in-sd0-supply = <&vdd_5v0_sys>; - in-sd1-supply = <&vdd_5v0_sys>; - in-sd2-supply = <&vdd_5v0_sys>; - in-sd3-supply = <&vdd_5v0_sys>; - - vdd_soc: sd0 { - regulator-name = "VDD_SOC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1170000>; - regulator-enable-ramp-delay = <146>; - regulator-disable-ramp-delay = <4080>; - regulator-ramp-delay = <27500>; - regulator-ramp-delay-scale = <300>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <1>; - maxim,active-fps-power-down-slot = <6>; - }; - - vdd_ddr: sd1 { - regulator-name = "VDD_DDR_1V1_PMIC"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - regulator-enable-ramp-delay = <176>; - regulator-disable-ramp-delay = <145800>; - regulator-ramp-delay = <27500>; - regulator-ramp-delay-scale = <300>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <5>; - maxim,active-fps-power-down-slot = <2>; - }; - - vdd_pre: sd2 { - regulator-name = "VDD_PRE_REG_1V35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-enable-ramp-delay = <176>; - regulator-disable-ramp-delay = <32000>; - regulator-ramp-delay = <27500>; - regulator-ramp-delay-scale = <350>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <2>; - maxim,active-fps-power-down-slot = <5>; - }; - - vdd_1v8: sd3 { - regulator-name = "VDD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <242>; - regulator-disable-ramp-delay = <118000>; - regulator-ramp-delay = <27500>; - regulator-ramp-delay-scale = <360>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <3>; - maxim,active-fps-power-down-slot = <4>; - }; - - vdd_sys_1v2: ldo0 { - regulator-name = "AVDD_SYS_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-enable-ramp-delay = <26>; - regulator-disable-ramp-delay = <626>; - regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - - vdd_pex_1v05: ldo1 { - regulator-name = "VDD_PEX_1V05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-enable-ramp-delay = <22>; - regulator-disable-ramp-delay = <650>; - regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; - - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - - vddio_sdmmc: ldo2 { - regulator-name = "VDDIO_SDMMC"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <62>; - regulator-disable-ramp-delay = <650>; - regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; - - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - - ldo3 { - status = "disabled"; - }; - - vdd_rtc: ldo4 { - regulator-name = "VDD_RTC"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1100000>; - regulator-enable-ramp-delay = <22>; - regulator-disable-ramp-delay = <610>; - regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; - regulator-disable-active-discharge; - regulator-always-on; - regulator-boot-on; - - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <1>; - maxim,active-fps-power-down-slot = <6>; - }; - - ldo5 { - status = "disabled"; - }; - - ldo6 { - status = "disabled"; - }; - - avdd_1v05_pll: ldo7 { - regulator-name = "AVDD_1V05_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-enable-ramp-delay = <24>; - regulator-disable-ramp-delay = <2768>; - regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; - - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <3>; - maxim,active-fps-power-down-slot = <4>; - }; - - avdd_1v05: ldo8 { - regulator-name = "AVDD_SATA_HDMI_DP_1V05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-enable-ramp-delay = <22>; - regulator-disable-ramp-delay = <1160>; - regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; - - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <6>; - maxim,active-fps-power-down-slot = <1>; - }; - }; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - nvidia,cpu-pwr-good-time = <0>; - nvidia,cpu-pwr-off-time = <0>; - nvidia,core-pwr-good-time = <4587 3876>; - nvidia,core-pwr-off-time = <39065>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - hda@70030000 { - nvidia,model = "jetson-nano-hda"; - - status = "okay"; - }; - - usb@70090000 { - phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, - <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, - <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>; - phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; - - avdd-usb-supply = <&vdd_3v3_sys>; - dvddio-pex-supply = <&vdd_pex_1v05>; - hvddio-pex-supply = <&vdd_1v8>; - /* these really belong to the XUSB pad controller */ - avdd-pll-utmip-supply = <&vdd_1v8>; - avdd-pll-uerefe-supply = <&vdd_pex_1v05>; - dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>; - hvdd-usb-ss-pll-e-supply = <&vdd_1v8>; - - status = "okay"; - }; - - padctl@7009f000 { - status = "okay"; - - avdd-pll-utmip-supply = <&vdd_1v8>; - avdd-pll-uerefe-supply = <&vdd_pex_1v05>; - dvdd-pex-pll-supply = <&vdd_pex_1v05>; - hvdd-pex-pll-e-supply = <&vdd_1v8>; - - pads { - usb2 { - status = "okay"; - - lanes { - micro_b: usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-1 { - nvidia,function = "xusb"; - status = "okay"; - }; - - usb2-2 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-0 { - nvidia,function = "pcie-x1"; - status = "okay"; - }; - - pcie-1 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-2 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-3 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-4 { - nvidia,function = "pcie-x4"; - status = "okay"; - }; - - pcie-5 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - - pcie-6 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "okay"; - mode = "peripheral"; - usb-role-switch; - - vbus-supply = <&vdd_5v0_usb>; - - connector { - compatible = "gpio-usb-b-connector", - "usb-b-connector"; - label = "micro-USB"; - type = "micro"; - vbus-gpios = <&gpio TEGRA_GPIO(CC, 4) - GPIO_ACTIVE_LOW>; - }; - }; - - usb2-1 { - status = "okay"; - mode = "host"; - }; - - usb2-2 { - status = "okay"; - mode = "host"; - }; - - usb3-0 { - status = "okay"; - nvidia,usb2-companion = <1>; - vbus-supply = <&vdd_hub_3v3>; - }; - }; - }; - - mmc@700b0000 { - status = "okay"; - bus-width = <4>; - - cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; - disable-wp; - - vqmmc-supply = <&vddio_sdmmc>; - vmmc-supply = <&vdd_3v3_sd>; - }; - - mmc@700b0400 { - status = "okay"; - bus-width = <4>; - - vqmmc-supply = <&vdd_1v8>; - vmmc-supply = <&vdd_3v3_sys>; - - non-removable; - cap-sdio-irq; - keep-power-in-suspend; - wakeup-source; - }; - - usb@700d0000 { - status = "okay"; - phys = <µ_b>; - phy-names = "usb2-0"; - avddio-usb-supply = <&vdd_3v3_sys>; - hvdd-usb-supply = <&vdd_1v8>; - }; - - clock@70110000 { - status = "okay"; - - nvidia,cf = <6>; - nvidia,ci = <0>; - nvidia,cg = <2>; - nvidia,droop-ctrl = <0x00000f00>; - nvidia,force-mode = <1>; - nvidia,sample-rate = <25000>; - - nvidia,pwm-min-microvolts = <708000>; - nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ - nvidia,pwm-to-pmic; - nvidia,pwm-tristate-microvolts = <1000000>; - nvidia,pwm-voltage-step-microvolts = <19200>; - - pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; - pinctrl-0 = <&dvfs_pwm_active_state>; - pinctrl-1 = <&dvfs_pwm_inactive_state>; - }; - - aconnect@702c0000 { - status = "okay"; - - dma@702e2000 { - status = "okay"; - }; - - interrupt-controller@702f9000 { - status = "okay"; - }; - }; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - cpus { - cpu@0 { - enable-method = "psci"; - }; - - cpu@1 { - enable-method = "psci"; - }; - - cpu@2 { - enable-method = "psci"; - }; - - cpu@3 { - enable-method = "psci"; - }; - - idle-states { - cpu-sleep { - status = "okay"; - }; - }; - }; - - fan: fan { - compatible = "pwm-fan"; - pwms = <&pwm 3 45334>; - - cooling-levels = <0 64 128 255>; - #cooling-cells = <2>; - }; - - thermal-zones { - cpu { - trips { - cpu_trip_critical: critical { - temperature = <96500>; - hysteresis = <0>; - type = "critical"; - }; - - cpu_trip_hot: hot { - temperature = <70000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_trip_active: active { - temperature = <50000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_passive: passive { - temperature = <30000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu-critical { - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_critical>; - }; - - cpu-hot { - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_hot>; - }; - - cpu-active { - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active>; - }; - - cpu-passive { - cooling-device = <&fan 0 0>; - trip = <&cpu_trip_passive>; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <30>; - wakeup-event-action = ; - wakeup-source; - }; - - force-recovery { - label = "Force Recovery"; - gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <30>; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - vdd_5v0_sys: regulator@0 { - compatible = "regulator-fixed"; - - regulator-name = "VDD_5V0_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_3v3_sys: regulator@1 { - compatible = "regulator-fixed"; - - regulator-name = "VDD_3V3_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <240>; - regulator-disable-ramp-delay = <11340>; - regulator-always-on; - regulator-boot-on; - - gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_3v3_sd: regulator@2 { - compatible = "regulator-fixed"; - - regulator-name = "VDD_3V3_SD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_hdmi: regulator@3 { - compatible = "regulator-fixed"; - - regulator-name = "VDD_HDMI_5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_hub_3v3: regulator@4 { - compatible = "regulator-fixed"; - - regulator-name = "VDD_HUB_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_cpu: regulator@5 { - compatible = "regulator-fixed"; - - regulator-name = "VDD_CPU"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - - gpio = <&pmic 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_gpu: regulator@6 { - compatible = "pwm-regulator"; - pwms = <&pwm 1 8000>; - - regulator-name = "VDD_GPU"; - regulator-min-microvolt = <710000>; - regulator-max-microvolt = <1320000>; - regulator-ramp-delay = <80>; - regulator-enable-ramp-delay = <2000>; - regulator-settling-time-us = <160>; - - enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>; - vin-supply = <&vdd_5v0_sys>; - }; - - avdd_io_edp_1v05: regulator@7 { - compatible = "regulator-fixed"; - - regulator-name = "AVDD_IO_EDP_1V05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - - gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - - vin-supply = <&avdd_1v05_pll>; - }; - - vdd_5v0_usb: regulator@8 { - compatible = "regulator-fixed"; - - regulator-name = "VDD_5V_USB"; - regulator-min-microvolt = <50000000>; - regulator-max-microvolt = <50000000>; - - vin-supply = <&vdd_5v0_sys>; - }; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts deleted file mode 100644 index bd7837824..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ /dev/null @@ -1,1879 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include -#include - -#include "tegra210.dtsi" - -/ { - model = "Google Pixel C"; - compatible = "google,smaug-rev8", "google,smaug-rev7", - "google,smaug-rev6", "google,smaug-rev5", - "google,smaug-rev4", "google,smaug-rev3", - "google,smaug-rev2", "google,smaug-rev1", - "google,smaug", "nvidia,tegra210"; - - aliases { - serial0 = &uarta; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0xc0000000>; - }; - - host1x@50000000 { - dpaux: dpaux@545c0000 { - status = "okay"; - }; - }; - - pinmux: pinmux@700008d4 { - pinctrl-names = "boot"; - pinctrl-0 = <&state_boot>; - - state_boot: pinmux { - pex_l0_rst_n_pa0 { - nvidia,pins = "pex_l0_rst_n_pa0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l0_clkreq_n_pa1 { - nvidia,pins = "pex_l0_clkreq_n_pa1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_wake_n_pa2 { - nvidia,pins = "pex_wake_n_pa2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l1_rst_n_pa3 { - nvidia,pins = "pex_l1_rst_n_pa3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pex_l1_clkreq_n_pa4 { - nvidia,pins = "pex_l1_clkreq_n_pa4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - sata_led_active_pa5 { - nvidia,pins = "sata_led_active_pa5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pa6 { - nvidia,pins = "pa6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_fs_pb0 { - nvidia,pins = "dap1_fs_pb0"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_din_pb1 { - nvidia,pins = "dap1_din_pb1"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_dout_pb2 { - nvidia,pins = "dap1_dout_pb2"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap1_sclk_pb3 { - nvidia,pins = "dap1_sclk_pb3"; - nvidia,function = "i2s1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_mosi_pb4 { - nvidia,pins = "spi2_mosi_pb4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_miso_pb5 { - nvidia,pins = "spi2_miso_pb5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_sck_pb6 { - nvidia,pins = "spi2_sck_pb6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi2_cs0_pb7 { - nvidia,pins = "spi2_cs0_pb7"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_mosi_pc0 { - nvidia,pins = "spi1_mosi_pc0"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_miso_pc1 { - nvidia,pins = "spi1_miso_pc1"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_sck_pc2 { - nvidia,pins = "spi1_sck_pc2"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_cs0_pc3 { - nvidia,pins = "spi1_cs0_pc3"; - nvidia,function = "spi1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi1_cs1_pc4 { - nvidia,pins = "spi1_cs1_pc4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_sck_pc5 { - nvidia,pins = "spi4_sck_pc5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_cs0_pc6 { - nvidia,pins = "spi4_cs0_pc6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_mosi_pc7 { - nvidia,pins = "spi4_mosi_pc7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spi4_miso_pd0 { - nvidia,pins = "spi4_miso_pd0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_tx_pd1 { - nvidia,pins = "uart3_tx_pd1"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_rx_pd2 { - nvidia,pins = "uart3_rx_pd2"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_rts_pd3 { - nvidia,pins = "uart3_rts_pd3"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart3_cts_pd4 { - nvidia,pins = "uart3_cts_pd4"; - nvidia,function = "uartc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic1_clk_pe0 { - nvidia,pins = "dmic1_clk_pe0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic1_dat_pe1 { - nvidia,pins = "dmic1_dat_pe1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic2_clk_pe2 { - nvidia,pins = "dmic2_clk_pe2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic2_dat_pe3 { - nvidia,pins = "dmic2_dat_pe3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic3_clk_pe4 { - nvidia,pins = "dmic3_clk_pe4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dmic3_dat_pe5 { - nvidia,pins = "dmic3_dat_pe5"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pe6 { - nvidia,pins = "pe6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pe7 { - nvidia,pins = "pe7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen3_i2c_scl_pf0 { - nvidia,pins = "gen3_i2c_scl_pf0"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen3_i2c_sda_pf1 { - nvidia,pins = "gen3_i2c_sda_pf1"; - nvidia,function = "i2c3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - uart2_tx_pg0 { - nvidia,pins = "uart2_tx_pg0"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_rx_pg1 { - nvidia,pins = "uart2_rx_pg1"; - nvidia,function = "uartb"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_rts_pg2 { - nvidia,pins = "uart2_rts_pg2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart2_cts_pg3 { - nvidia,pins = "uart2_cts_pg3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_en_ph0 { - nvidia,pins = "wifi_en_ph0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_rst_ph1 { - nvidia,pins = "wifi_rst_ph1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - wifi_wake_ap_ph2 { - nvidia,pins = "wifi_wake_ap_ph2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_wake_bt_ph3 { - nvidia,pins = "ap_wake_bt_ph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - bt_rst_ph4 { - nvidia,pins = "bt_rst_ph4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - bt_wake_ap_ph5 { - nvidia,pins = "bt_wake_ap_ph5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ph6 { - nvidia,pins = "ph6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_wake_nfc_ph7 { - nvidia,pins = "ap_wake_nfc_ph7"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - nfc_en_pi0 { - nvidia,pins = "nfc_en_pi0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - nfc_int_pi1 { - nvidia,pins = "nfc_int_pi1"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gps_en_pi2 { - nvidia,pins = "gps_en_pi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gps_rst_pi3 { - nvidia,pins = "gps_rst_pi3"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_tx_pi4 { - nvidia,pins = "uart4_tx_pi4"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_rx_pi5 { - nvidia,pins = "uart4_rx_pi5"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_rts_pi6 { - nvidia,pins = "uart4_rts_pi6"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart4_cts_pi7 { - nvidia,pins = "uart4_cts_pi7"; - nvidia,function = "uartd"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gen1_i2c_sda_pj0 { - nvidia,pins = "gen1_i2c_sda_pj0"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen1_i2c_scl_pj1 { - nvidia,pins = "gen1_i2c_scl_pj1"; - nvidia,function = "i2c1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen2_i2c_scl_pj2 { - nvidia,pins = "gen2_i2c_scl_pj2"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - gen2_i2c_sda_pj3 { - nvidia,pins = "gen2_i2c_sda_pj3"; - nvidia,function = "i2c2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - dap4_fs_pj4 { - nvidia,pins = "dap4_fs_pj4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_din_pj5 { - nvidia,pins = "dap4_din_pj5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_dout_pj6 { - nvidia,pins = "dap4_dout_pj6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap4_sclk_pj7 { - nvidia,pins = "dap4_sclk_pj7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk0 { - nvidia,pins = "pk0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk1 { - nvidia,pins = "pk1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk2 { - nvidia,pins = "pk2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk3 { - nvidia,pins = "pk3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk4 { - nvidia,pins = "pk4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk5 { - nvidia,pins = "pk5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk6 { - nvidia,pins = "pk6"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pk7 { - nvidia,pins = "pk7"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pl0 { - nvidia,pins = "pl0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pl1 { - nvidia,pins = "pl1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_clk_pm0 { - nvidia,pins = "sdmmc1_clk_pm0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_cmd_pm1 { - nvidia,pins = "sdmmc1_cmd_pm1"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat3_pm2 { - nvidia,pins = "sdmmc1_dat3_pm2"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat2_pm3 { - nvidia,pins = "sdmmc1_dat2_pm3"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat1_pm4 { - nvidia,pins = "sdmmc1_dat1_pm4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc1_dat0_pm5 { - nvidia,pins = "sdmmc1_dat0_pm5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_clk_pp0 { - nvidia,pins = "sdmmc3_clk_pp0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_cmd_pp1 { - nvidia,pins = "sdmmc3_cmd_pp1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat3_pp2 { - nvidia,pins = "sdmmc3_dat3_pp2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat2_pp3 { - nvidia,pins = "sdmmc3_dat2_pp3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat1_pp4 { - nvidia,pins = "sdmmc3_dat1_pp4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - sdmmc3_dat0_pp5 { - nvidia,pins = "sdmmc3_dat0_pp5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_mclk_ps0 { - nvidia,pins = "cam1_mclk_ps0"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam2_mclk_ps1 { - nvidia,pins = "cam2_mclk_ps1"; - nvidia,function = "extperiph3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_i2c_scl_ps2 { - nvidia,pins = "cam_i2c_scl_ps2"; - nvidia,function = "i2cvi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - cam_i2c_sda_ps3 { - nvidia,pins = "cam_i2c_sda_ps3"; - nvidia,function = "i2cvi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - cam_rst_ps4 { - nvidia,pins = "cam_rst_ps4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_af_en_ps5 { - nvidia,pins = "cam_af_en_ps5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam_flash_en_ps6 { - nvidia,pins = "cam_flash_en_ps6"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_pwdn_ps7 { - nvidia,pins = "cam1_pwdn_ps7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam2_pwdn_pt0 { - nvidia,pins = "cam2_pwdn_pt0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cam1_strobe_pt1 { - nvidia,pins = "cam1_strobe_pt1"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_tx_pu0 { - nvidia,pins = "uart1_tx_pu0"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_rx_pu1 { - nvidia,pins = "uart1_rx_pu1"; - nvidia,function = "uarta"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_rts_pu2 { - nvidia,pins = "uart1_rts_pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - uart1_cts_pu3 { - nvidia,pins = "uart1_cts_pu3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_bl_pwm_pv0 { - nvidia,pins = "lcd_bl_pwm_pv0"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_bl_en_pv1 { - nvidia,pins = "lcd_bl_en_pv1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_rst_pv2 { - nvidia,pins = "lcd_rst_pv2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_gpio1_pv3 { - nvidia,pins = "lcd_gpio1_pv3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_gpio2_pv4 { - nvidia,pins = "lcd_gpio2_pv4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - ap_ready_pv5 { - nvidia,pins = "ap_ready_pv5"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_rst_pv6 { - nvidia,pins = "touch_rst_pv6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_clk_pv7 { - nvidia,pins = "touch_clk_pv7"; - nvidia,function = "touch"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - modem_wake_ap_px0 { - nvidia,pins = "modem_wake_ap_px0"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - touch_int_px1 { - nvidia,pins = "touch_int_px1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - motion_int_px2 { - nvidia,pins = "motion_int_px2"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - als_prox_int_px3 { - nvidia,pins = "als_prox_int_px3"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - temp_alert_px4 { - nvidia,pins = "temp_alert_px4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_power_on_px5 { - nvidia,pins = "button_power_on_px5"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_vol_up_px6 { - nvidia,pins = "button_vol_up_px6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_vol_down_px7 { - nvidia,pins = "button_vol_down_px7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_slide_sw_py0 { - nvidia,pins = "button_slide_sw_py0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - button_home_py1 { - nvidia,pins = "button_home_py1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - lcd_te_py2 { - nvidia,pins = "lcd_te_py2"; - nvidia,function = "displaya"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_i2c_scl_py3 { - nvidia,pins = "pwr_i2c_scl_py3"; - nvidia,function = "i2cpmu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - pwr_i2c_sda_py4 { - nvidia,pins = "pwr_i2c_sda_py4"; - nvidia,function = "i2cpmu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - clk_32k_out_py5 { - nvidia,pins = "clk_32k_out_py5"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz0 { - nvidia,pins = "pz0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz1 { - nvidia,pins = "pz1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz2 { - nvidia,pins = "pz2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz3 { - nvidia,pins = "pz3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz4 { - nvidia,pins = "pz4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pz5 { - nvidia,pins = "pz5"; - nvidia,function = "soc"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_fs_paa0 { - nvidia,pins = "dap2_fs_paa0"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_sclk_paa1 { - nvidia,pins = "dap2_sclk_paa1"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_din_paa2 { - nvidia,pins = "dap2_din_paa2"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dap2_dout_paa3 { - nvidia,pins = "dap2_dout_paa3"; - nvidia,function = "i2s2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - aud_mclk_pbb0 { - nvidia,pins = "aud_mclk_pbb0"; - nvidia,function = "aud"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dvfs_pwm_pbb1 { - nvidia,pins = "dvfs_pwm_pbb1"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - dvfs_clk_pbb2 { - nvidia,pins = "dvfs_clk_pbb2"; - nvidia,function = "rsvd0"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gpio_x1_aud_pbb3 { - nvidia,pins = "gpio_x1_aud_pbb3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - gpio_x3_aud_pbb4 { - nvidia,pins = "gpio_x3_aud_pbb4"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - hdmi_cec_pcc0 { - nvidia,pins = "hdmi_cec_pcc0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - hdmi_int_dp_hpd_pcc1 { - nvidia,pins = "hdmi_int_dp_hpd_pcc1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - spdif_out_pcc2 { - nvidia,pins = "spdif_out_pcc2"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - spdif_in_pcc3 { - nvidia,pins = "spdif_in_pcc3"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - usb_vbus_en0_pcc4 { - nvidia,pins = "usb_vbus_en0_pcc4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - usb_vbus_en1_pcc5 { - nvidia,pins = "usb_vbus_en1_pcc5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - dp_hpd0_pcc6 { - nvidia,pins = "dp_hpd0_pcc6"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pcc7 { - nvidia,pins = "pcc7"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - nvidia,io-hv = ; - }; - spi2_cs1_pdd0 { - nvidia,pins = "spi2_cs1_pdd0"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_sck_pee0 { - nvidia,pins = "qspi_sck_pee0"; - nvidia,function = "qspi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_cs_n_pee1 { - nvidia,pins = "qspi_cs_n_pee1"; - nvidia,function = "qspi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io0_pee2 { - nvidia,pins = "qspi_io0_pee2"; - nvidia,function = "qspi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io1_pee3 { - nvidia,pins = "qspi_io1_pee3"; - nvidia,function = "qspi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io2_pee4 { - nvidia,pins = "qspi_io2_pee4"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - qspi_io3_pee5 { - nvidia,pins = "qspi_io3_pee5"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "core"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "cpu"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "clk"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "jtag"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - clk_req { - nvidia,pins = "clk_req"; - nvidia,function = "rsvd1"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - shutdown { - nvidia,pins = "shutdown"; - nvidia,function = "shutdown"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; - }; - }; - }; - - serial@70006000 { - status = "okay"; - }; - - i2c@7000c400 { - status = "okay"; - clock-frequency = <1000000>; - - ec@1e { - compatible = "google,cros-ec-i2c"; - reg = <0x1e>; - interrupt-parent = <&gpio>; - interrupts = ; - wakeup-source; - - ec_i2c_0: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - #address-cells = <1>; - #size-cells = <0>; - - google,remote-bus = <0>; - - battery: bq27742@55 { - compatible = "ti,bq27742"; - reg = <0x55>; - }; - }; - }; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <1000000>; - - max77621_cpu: max77621@1b { - compatible = "maxim,max77621"; - reg = <0x1b>; - interrupt-parent = <&gpio>; - interrupts = ; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1231250>; - regulator-name = "PPVAR_CPU"; - regulator-ramp-delay = <12500>; - maxim,dvs-default-state = <1>; - maxim,enable-active-discharge; - maxim,enable-bias-control; - maxim,enable-etr; - maxim,enable-gpio = <&pmic 5 0>; - maxim,externally-enable; - }; - - pmic: pmic@3c { - compatible = "maxim,max77620"; - reg = <0x3c>; - interrupts = ; - - #interrupt-cells = <2>; - interrupt-controller; - - gpio-controller; - #gpio-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&max77620_default>; - - max77620_default: pinmux { - gpio0_1_2_7 { - pins = "gpio0", "gpio1", "gpio2", "gpio7"; - function = "gpio"; - }; - - /* - * GPIO3 is used to en_pp3300, and it is part of power - * sequence, So it must be sequenced up (automatically - * set by OTP) and down properly. - */ - gpio3 { - pins = "gpio3"; - function = "fps-out"; - drive-open-drain = <1>; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <4>; - maxim,active-fps-power-down-slot = <2>; - }; - - gpio5_6 { - pins = "gpio5", "gpio6"; - function = "gpio"; - drive-push-pull = <1>; - }; - - gpio4 { - pins = "gpio4"; - function = "32k-out1"; - }; - }; - - fps { - fps0 { - maxim,shutdown-fps-time-period-us = <5120>; - maxim,fps-event-source = ; - }; - - fps1 { - maxim,shutdown-fps-time-period-us = <5120>; - maxim,fps-event-source = ; - maxim,device-state-on-disabled-event = ; - }; - - fps2 { - maxim,fps-event-source = ; - }; - }; - - regulators { - in-ldo0-1-supply = <&pp1350>; - in-ldo2-supply = <&pp3300>; - in-ldo3-5-supply = <&pp3300>; - in-ldo7-8-supply = <&pp1350>; - - ppvar_soc: sd0 { - regulator-name = "PPVAR_SOC"; - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1125000>; - regulator-always-on; - regulator-boot-on; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <1>; - maxim,active-fps-power-down-slot = <7>; - }; - - pp1100_sd1: sd1 { - regulator-name = "PP1100"; - regulator-min-microvolt = <1125000>; - regulator-max-microvolt = <1125000>; - regulator-always-on; - regulator-boot-on; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <5>; - maxim,active-fps-power-down-slot = <1>; - }; - - pp1350: sd2 { - regulator-name = "PP1350"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <2>; - maxim,active-fps-power-down-slot = <5>; - }; - - pp1800: sd3 { - regulator-name = "PP1800"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <3>; - maxim,active-fps-power-down-slot = <3>; - }; - - pp1200_avdd: ldo0 { - regulator-name = "PP1200_AVDD"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-enable-ramp-delay = <26>; - regulator-ramp-delay = <100000>; - regulator-boot-on; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - - pp1200_rcam: ldo1 { - regulator-name = "PP1200_RCAM"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-enable-ramp-delay = <22>; - regulator-ramp-delay = <100000>; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - - pp_ldo2: ldo2 { - regulator-name = "PP_LDO2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <62>; - regulator-ramp-delay = <11000>; - regulator-always-on; - regulator-boot-on; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - - pp2800l_rcam: ldo3 { - regulator-name = "PP2800L_RCAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <50>; - regulator-ramp-delay = <100000>; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - - pp100_soc_rtc: ldo4 { - regulator-name = "PP1100_SOC_RTC"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-enable-ramp-delay = <22>; - regulator-ramp-delay = <100000>; - regulator-always-on; /* Check this */ - regulator-boot-on; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <1>; - maxim,active-fps-power-down-slot = <7>; - }; - - pp2800l_fcam: ldo5 { - regulator-name = "PP2800L_FCAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-enable-ramp-delay = <62>; - regulator-ramp-delay = <100000>; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - - ldo6 { - /* Unused. */ - regulator-name = "PP_LDO6"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <36>; - regulator-ramp-delay = <100000>; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - - pp1050_avdd: ldo7 { - regulator-name = "PP1050_AVDD"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-enable-ramp-delay = <24>; - regulator-ramp-delay = <100000>; - regulator-always-on; - regulator-boot-on; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <3>; - maxim,active-fps-power-down-slot = <4>; - }; - - avddio_1v05: ldo8 { - regulator-name = "AVDDIO_1V05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-enable-ramp-delay = <22>; - regulator-ramp-delay = <100000>; - regulator-boot-on; - maxim,active-fps-source = ; - maxim,active-fps-power-up-slot = <0>; - maxim,active-fps-power-down-slot = <7>; - }; - }; - }; - }; - - i2c@7000d100 { - status = "okay"; - clock-frequency = <400000>; - - nau8825@1a { - compatible = "nuvoton,nau8825"; - reg = <0x1a>; - interrupt-parent = <&gpio>; - interrupts = ; - clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_2>; - clock-names = "mclk"; - - nuvoton,jkdet-enable; - nuvoton,jkdet-polarity = ; - nuvoton,vref-impedance = <2>; - nuvoton,micbias-voltage = <6>; - nuvoton,sar-threshold-num = <4>; - nuvoton,sar-threshold = <0xc 0x1e 0x38 0x60>; - nuvoton,sar-hysteresis = <1>; - nuvoton,sar-voltage = <0>; - nuvoton,sar-compare-time = <0>; - nuvoton,sar-sampling-time = <0>; - nuvoton,short-key-debounce = <2>; - nuvoton,jack-insert-debounce = <7>; - nuvoton,jack-eject-debounce = <7>; - status = "okay"; - }; - - audio-codec@2d { - compatible = "realtek,rt5677"; - reg = <0x2d>; - interrupt-parent = <&gpio>; - interrupts = ; - realtek,reset-gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_LOW>; - gpio-controller; - #gpio-cells = <2>; - status = "okay"; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - nvidia,cpu-pwr-good-time = <0>; - nvidia,cpu-pwr-off-time = <0>; - nvidia,core-pwr-good-time = <12000 6000>; - nvidia,core-pwr-off-time = <39053>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - status = "okay"; - }; - - usb@70090000 { - phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>; - phy-names = "usb2-0", "usb3-0"; - - dvddio-pex-supply = <&avddio_1v05>; - hvddio-pex-supply = <&pp1800>; - avdd-usb-supply = <&pp3300>; - avdd-pll-utmip-supply = <&pp1800>; - avdd-pll-uerefe-supply = <&pp1050_avdd>; - dvdd-pex-pll-supply = <&avddio_1v05>; - hvdd-pex-pll-e-supply = <&pp1800>; - - status = "okay"; - }; - - padctl@7009f000 { - status = "okay"; - - avdd-pll-utmip-supply = <&pp1800>; - avdd-pll-uerefe-supply = <&pp1050_avdd>; - dvdd-pex-pll-supply = <&avddio_1v05>; - hvdd-pex-pll-e-supply = <&pp1800>; - - pads { - usb2 { - status = "okay"; - - lanes { - usb2-0 { - nvidia,function = "xusb"; - status = "okay"; - }; - }; - }; - - pcie { - status = "okay"; - - lanes { - pcie-6 { - nvidia,function = "usb3-ss"; - status = "okay"; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "okay"; - vbus-supply = <&usbc_vbus>; - mode = "otg"; - }; - - usb3-0 { - nvidia,usb2-companion = <0>; - status = "okay"; - }; - }; - }; - - mmc@700b0600 { - bus-width = <8>; - non-removable; - status = "okay"; - }; - - clock@70110000 { - status = "okay"; - nvidia,cf = <6>; - nvidia,ci = <0>; - nvidia,cg = <2>; - nvidia,droop-ctrl = <0x00000f00>; - nvidia,force-mode = <1>; - nvidia,i2c-fs-rate = <400000>; - nvidia,sample-rate = <12500>; - vdd-cpu-supply = <&max77621_cpu>; - }; - - aconnect@702c0000 { - status = "okay"; - - dma@702e2000 { - status = "okay"; - }; - - interrupt-controller@702f9000 { - status = "okay"; - }; - }; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - cpus { - cpu@0 { - enable-method = "psci"; - }; - - cpu@1 { - enable-method = "psci"; - }; - - cpu@2 { - enable-method = "psci"; - }; - - cpu@3 { - enable-method = "psci"; - }; - - idle-states { - cpu-sleep { - arm,psci-suspend-param = <0x00010007>; - status = "okay"; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <30>; - wakeup-source; - }; - - lid { - label = "Lid"; - gpios = <&gpio TEGRA_GPIO(B, 4) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - wakeup-source; - }; - - tablet_mode { - label = "Tablet Mode"; - gpios = <&gpio TEGRA_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; - linux,input-type = ; - linux,code = ; - wakeup-source; - }; - - volume_down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - volume_up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(M, 4) GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - max98357a { - compatible = "maxim,max98357a"; - status = "okay"; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - ppvar_sys: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "PPVAR_SYS"; - regulator-min-microvolt = <4400000>; - regulator-max-microvolt = <4400000>; - regulator-always-on; - }; - - pplcd_vdd: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "PPLCD_VDD"; - regulator-min-microvolt = <4400000>; - regulator-max-microvolt = <4400000>; - gpio = <&gpio TEGRA_GPIO(V, 4) 0>; - enable-active-high; - regulator-boot-on; - }; - - pp3000_always: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "PP3000_ALWAYS"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - pp3300: regulator@3 { - compatible = "regulator-fixed"; - regulator-name = "PP3300"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - enable-active-high; - }; - - pp5000: regulator@4 { - compatible = "regulator-fixed"; - regulator-name = "PP5000"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - pp1800_lcdio: regulator@5 { - compatible = "regulator-fixed"; - regulator-name = "PP1800_LCDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio TEGRA_GPIO(V, 3) 0>; - enable-active-high; - regulator-boot-on; - }; - - pp1800_cam: regulator@6 { - compatible = "regulator-fixed"; - regulator-name = "PP1800_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio TEGRA_GPIO(K, 3) 0>; - enable-active-high; - }; - - usbc_vbus: regulator@7 { - compatible = "regulator-fixed"; - regulator-name = "USBC_VBUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi deleted file mode 100644 index 7fd47d8f1..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ /dev/null @@ -1,1856 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "nvidia,tegra210"; - interrupt-parent = <&lic>; - #address-cells = <2>; - #size-cells = <2>; - - pcie@1003000 { - compatible = "nvidia,tegra210-pcie"; - device_type = "pci"; - reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ - <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ - <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ - reg-names = "pads", "afi", "cs"; - interrupts = , /* controller interrupt */ - ; /* MSI interrupt */ - interrupt-names = "intr", "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - - bus-range = <0x00 0xff>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ - <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ - <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ - <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ - <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ - - clocks = <&tegra_car TEGRA210_CLK_PCIE>, - <&tegra_car TEGRA210_CLK_AFI>, - <&tegra_car TEGRA210_CLK_PLL_E>, - <&tegra_car TEGRA210_CLK_CML0>; - clock-names = "pex", "afi", "pll_e", "cml"; - resets = <&tegra_car 70>, - <&tegra_car 72>, - <&tegra_car 74>; - reset-names = "pex", "afi", "pcie_x"; - - pinctrl-names = "default", "idle"; - pinctrl-0 = <&pex_dpd_disable>; - pinctrl-1 = <&pex_dpd_enable>; - - status = "disabled"; - - pci@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; - reg = <0x000800 0 0 0 0>; - bus-range = <0x00 0xff>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <4>; - }; - - pci@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; - reg = <0x001000 0 0 0 0>; - bus-range = <0x00 0xff>; - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - nvidia,num-lanes = <1>; - }; - }; - - host1x@50000000 { - compatible = "nvidia,tegra210-host1x"; - reg = <0x0 0x50000000 0x0 0x00034000>; - interrupts = , /* syncpt */ - ; /* general */ - interrupt-names = "syncpt", "host1x"; - clocks = <&tegra_car TEGRA210_CLK_HOST1X>; - clock-names = "host1x"; - resets = <&tegra_car 28>; - reset-names = "host1x"; - - #address-cells = <2>; - #size-cells = <2>; - - ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; - - iommus = <&mc TEGRA_SWGROUP_HC>; - - dpaux1: dpaux@54040000 { - compatible = "nvidia,tegra210-dpaux"; - reg = <0x0 0x54040000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, - <&tegra_car TEGRA210_CLK_PLL_DP>; - clock-names = "dpaux", "parent"; - resets = <&tegra_car 207>; - reset-names = "dpaux"; - power-domains = <&pd_sor>; - status = "disabled"; - - state_dpaux1_aux: pinmux-aux { - groups = "dpaux-io"; - function = "aux"; - }; - - state_dpaux1_i2c: pinmux-i2c { - groups = "dpaux-io"; - function = "i2c"; - }; - - state_dpaux1_off: pinmux-off { - groups = "dpaux-io"; - function = "off"; - }; - - i2c-bus { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - vi@54080000 { - compatible = "nvidia,tegra210-vi"; - reg = <0x0 0x54080000 0x0 0x700>; - interrupts = ; - status = "disabled"; - assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; - - clocks = <&tegra_car TEGRA210_CLK_VI>; - power-domains = <&pd_venc>; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x0 0x0 0x54080000 0x2000>; - - csi@838 { - compatible = "nvidia,tegra210-csi"; - reg = <0x838 0x1300>; - status = "disabled"; - assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, - <&tegra_car TEGRA210_CLK_CILCD>, - <&tegra_car TEGRA210_CLK_CILE>, - <&tegra_car TEGRA210_CLK_CSI_TPG>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, - <&tegra_car TEGRA210_CLK_PLL_P>, - <&tegra_car TEGRA210_CLK_PLL_P>; - assigned-clock-rates = <102000000>, - <102000000>, - <102000000>, - <972000000>; - - clocks = <&tegra_car TEGRA210_CLK_CSI>, - <&tegra_car TEGRA210_CLK_CILAB>, - <&tegra_car TEGRA210_CLK_CILCD>, - <&tegra_car TEGRA210_CLK_CILE>, - <&tegra_car TEGRA210_CLK_CSI_TPG>; - clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; - power-domains = <&pd_sor>; - }; - }; - - tsec@54100000 { - compatible = "nvidia,tegra210-tsec"; - reg = <0x0 0x54100000 0x0 0x00040000>; - }; - - dc@54200000 { - compatible = "nvidia,tegra210-dc"; - reg = <0x0 0x54200000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_DISP1>; - clock-names = "dc"; - resets = <&tegra_car 27>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DC>; - - nvidia,outputs = <&dsia &dsib &sor0 &sor1>; - nvidia,head = <0>; - }; - - dc@54240000 { - compatible = "nvidia,tegra210-dc"; - reg = <0x0 0x54240000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_DISP2>; - clock-names = "dc"; - resets = <&tegra_car 26>; - reset-names = "dc"; - - iommus = <&mc TEGRA_SWGROUP_DCB>; - - nvidia,outputs = <&dsia &dsib &sor0 &sor1>; - nvidia,head = <1>; - }; - - dsia: dsi@54300000 { - compatible = "nvidia,tegra210-dsi"; - reg = <0x0 0x54300000 0x0 0x00040000>; - clocks = <&tegra_car TEGRA210_CLK_DSIA>, - <&tegra_car TEGRA210_CLK_DSIALP>, - <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; - clock-names = "dsi", "lp", "parent"; - resets = <&tegra_car 48>; - reset-names = "dsi"; - power-domains = <&pd_sor>; - nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ - - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - vic@54340000 { - compatible = "nvidia,tegra210-vic"; - reg = <0x0 0x54340000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_VIC03>; - clock-names = "vic"; - resets = <&tegra_car 178>; - reset-names = "vic"; - - iommus = <&mc TEGRA_SWGROUP_VIC>; - power-domains = <&pd_vic>; - }; - - nvjpg@54380000 { - compatible = "nvidia,tegra210-nvjpg"; - reg = <0x0 0x54380000 0x0 0x00040000>; - status = "disabled"; - }; - - dsib: dsi@54400000 { - compatible = "nvidia,tegra210-dsi"; - reg = <0x0 0x54400000 0x0 0x00040000>; - clocks = <&tegra_car TEGRA210_CLK_DSIB>, - <&tegra_car TEGRA210_CLK_DSIBLP>, - <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; - clock-names = "dsi", "lp", "parent"; - resets = <&tegra_car 82>; - reset-names = "dsi"; - power-domains = <&pd_sor>; - nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ - - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - nvdec@54480000 { - compatible = "nvidia,tegra210-nvdec"; - reg = <0x0 0x54480000 0x0 0x00040000>; - status = "disabled"; - }; - - nvenc@544c0000 { - compatible = "nvidia,tegra210-nvenc"; - reg = <0x0 0x544c0000 0x0 0x00040000>; - status = "disabled"; - }; - - tsec@54500000 { - compatible = "nvidia,tegra210-tsec"; - reg = <0x0 0x54500000 0x0 0x00040000>; - status = "disabled"; - }; - - sor0: sor@54540000 { - compatible = "nvidia,tegra210-sor"; - reg = <0x0 0x54540000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SOR0>, - <&tegra_car TEGRA210_CLK_SOR0_OUT>, - <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, - <&tegra_car TEGRA210_CLK_PLL_DP>, - <&tegra_car TEGRA210_CLK_SOR_SAFE>; - clock-names = "sor", "out", "parent", "dp", "safe"; - resets = <&tegra_car 182>; - reset-names = "sor"; - pinctrl-0 = <&state_dpaux_aux>; - pinctrl-1 = <&state_dpaux_i2c>; - pinctrl-2 = <&state_dpaux_off>; - pinctrl-names = "aux", "i2c", "off"; - power-domains = <&pd_sor>; - status = "disabled"; - }; - - sor1: sor@54580000 { - compatible = "nvidia,tegra210-sor1"; - reg = <0x0 0x54580000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SOR1>, - <&tegra_car TEGRA210_CLK_SOR1_OUT>, - <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, - <&tegra_car TEGRA210_CLK_PLL_DP>, - <&tegra_car TEGRA210_CLK_SOR_SAFE>; - clock-names = "sor", "out", "parent", "dp", "safe"; - resets = <&tegra_car 183>; - reset-names = "sor"; - pinctrl-0 = <&state_dpaux1_aux>; - pinctrl-1 = <&state_dpaux1_i2c>; - pinctrl-2 = <&state_dpaux1_off>; - pinctrl-names = "aux", "i2c", "off"; - power-domains = <&pd_sor>; - status = "disabled"; - }; - - dpaux: dpaux@545c0000 { - compatible = "nvidia,tegra210-dpaux"; - reg = <0x0 0x545c0000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_DPAUX>, - <&tegra_car TEGRA210_CLK_PLL_DP>; - clock-names = "dpaux", "parent"; - resets = <&tegra_car 181>; - reset-names = "dpaux"; - power-domains = <&pd_sor>; - status = "disabled"; - - state_dpaux_aux: pinmux-aux { - groups = "dpaux-io"; - function = "aux"; - }; - - state_dpaux_i2c: pinmux-i2c { - groups = "dpaux-io"; - function = "i2c"; - }; - - state_dpaux_off: pinmux-off { - groups = "dpaux-io"; - function = "off"; - }; - - i2c-bus { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - isp@54600000 { - compatible = "nvidia,tegra210-isp"; - reg = <0x0 0x54600000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_ISPA>; - resets = <&tegra_car 23>; - reset-names = "isp"; - status = "disabled"; - }; - - isp@54680000 { - compatible = "nvidia,tegra210-isp"; - reg = <0x0 0x54680000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_ISPB>; - resets = <&tegra_car 3>; - reset-names = "isp"; - status = "disabled"; - }; - - i2c@546c0000 { - compatible = "nvidia,tegra210-i2c-vi"; - reg = <0x0 0x546c0000 0x0 0x00040000>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, - <&tegra_car TEGRA210_CLK_I2CSLOW>; - clock-names = "div-clk", "slow"; - resets = <&tegra_car 208>; - reset-names = "i2c"; - power-domains = <&pd_venc>; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gic: interrupt-controller@50041000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x50041000 0x0 0x1000>, - <0x0 0x50042000 0x0 0x2000>, - <0x0 0x50044000 0x0 0x2000>, - <0x0 0x50046000 0x0 0x2000>; - interrupts = ; - interrupt-parent = <&gic>; - }; - - gpu@57000000 { - compatible = "nvidia,gm20b"; - reg = <0x0 0x57000000 0x0 0x01000000>, - <0x0 0x58000000 0x0 0x01000000>; - interrupts = , - ; - interrupt-names = "stall", "nonstall"; - clocks = <&tegra_car TEGRA210_CLK_GPU>, - <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, - <&tegra_car TEGRA210_CLK_PLL_G_REF>; - clock-names = "gpu", "pwr", "ref"; - resets = <&tegra_car 184>; - reset-names = "gpu"; - - iommus = <&mc TEGRA_SWGROUP_GPU>; - - status = "disabled"; - }; - - lic: interrupt-controller@60004000 { - compatible = "nvidia,tegra210-ictlr"; - reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ - <0x0 0x60004100 0x0 0x40>, /* secondary controller */ - <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ - <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ - <0x0 0x60004400 0x0 0x40>, /* quinary controller */ - <0x0 0x60004500 0x0 0x40>; /* senary controller */ - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - }; - - timer@60005000 { - compatible = "nvidia,tegra210-timer"; - reg = <0x0 0x60005000 0x0 0x400>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&tegra_car TEGRA210_CLK_TIMER>; - clock-names = "timer"; - }; - - tegra_car: clock@60006000 { - compatible = "nvidia,tegra210-car"; - reg = <0x0 0x60006000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - flow-controller@60007000 { - compatible = "nvidia,tegra210-flowctrl"; - reg = <0x0 0x60007000 0x0 0x1000>; - }; - - gpio: gpio@6000d000 { - compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; - reg = <0x0 0x6000d000 0x0 0x1000>; - interrupts = , - , - , - , - , - , - , - ; - #gpio-cells = <2>; - gpio-controller; - #interrupt-cells = <2>; - interrupt-controller; - }; - - apbdma: dma@60020000 { - compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; - reg = <0x0 0x60020000 0x0 0x1400>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&tegra_car TEGRA210_CLK_APBDMA>; - clock-names = "dma"; - resets = <&tegra_car 34>; - reset-names = "dma"; - #dma-cells = <1>; - }; - - apbmisc@70000800 { - compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; - reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ - <0x0 0x70000008 0x0 0x04>; /* Strapping options */ - }; - - pinmux: pinmux@700008d4 { - compatible = "nvidia,tegra210-pinmux"; - reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ - <0x0 0x70003000 0x0 0x294>; /* Mux registers */ - sdmmc1_3v3_drv: sdmmc1-3v3-drv { - sdmmc1 { - nvidia,pins = "drive_sdmmc1"; - nvidia,pull-down-strength = <0x8>; - nvidia,pull-up-strength = <0x8>; - }; - }; - sdmmc1_1v8_drv: sdmmc1-1v8-drv { - sdmmc1 { - nvidia,pins = "drive_sdmmc1"; - nvidia,pull-down-strength = <0x4>; - nvidia,pull-up-strength = <0x3>; - }; - }; - sdmmc2_1v8_drv: sdmmc2-1v8-drv { - sdmmc2 { - nvidia,pins = "drive_sdmmc2"; - nvidia,pull-down-strength = <0x10>; - nvidia,pull-up-strength = <0x10>; - }; - }; - sdmmc3_3v3_drv: sdmmc3-3v3-drv { - sdmmc3 { - nvidia,pins = "drive_sdmmc3"; - nvidia,pull-down-strength = <0x8>; - nvidia,pull-up-strength = <0x8>; - }; - }; - sdmmc3_1v8_drv: sdmmc3-1v8-drv { - sdmmc3 { - nvidia,pins = "drive_sdmmc3"; - nvidia,pull-down-strength = <0x4>; - nvidia,pull-up-strength = <0x3>; - }; - }; - sdmmc4_1v8_drv: sdmmc4-1v8-drv { - sdmmc4 { - nvidia,pins = "drive_sdmmc4"; - nvidia,pull-down-strength = <0x10>; - nvidia,pull-up-strength = <0x10>; - }; - }; - }; - - /* - * There are two serial driver i.e. 8250 based simple serial - * driver and APB DMA based serial driver for higher baudrate - * and performance. To enable the 8250 based driver, the compatible - * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable - * the APB DMA based serial driver, the compatible is - * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". - */ - uarta: serial@70006000 { - compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006000 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_UARTA>; - clock-names = "serial"; - resets = <&tegra_car 6>; - reset-names = "serial"; - dmas = <&apbdma 8>, <&apbdma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartb: serial@70006040 { - compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006040 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_UARTB>; - clock-names = "serial"; - resets = <&tegra_car 7>; - reset-names = "serial"; - dmas = <&apbdma 9>, <&apbdma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartc: serial@70006200 { - compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006200 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_UARTC>; - clock-names = "serial"; - resets = <&tegra_car 55>; - reset-names = "serial"; - dmas = <&apbdma 10>, <&apbdma 10>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uartd: serial@70006300 { - compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; - reg = <0x0 0x70006300 0x0 0x40>; - reg-shift = <2>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_UARTD>; - clock-names = "serial"; - resets = <&tegra_car 65>; - reset-names = "serial"; - dmas = <&apbdma 19>, <&apbdma 19>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - pwm: pwm@7000a000 { - compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; - reg = <0x0 0x7000a000 0x0 0x100>; - #pwm-cells = <2>; - clocks = <&tegra_car TEGRA210_CLK_PWM>; - clock-names = "pwm"; - resets = <&tegra_car 17>; - reset-names = "pwm"; - status = "disabled"; - }; - - i2c@7000c000 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; - reg = <0x0 0x7000c000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_I2C1>; - clock-names = "div-clk"; - resets = <&tegra_car 12>; - reset-names = "i2c"; - dmas = <&apbdma 21>, <&apbdma 21>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c400 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; - reg = <0x0 0x7000c400 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_I2C2>; - clock-names = "div-clk"; - resets = <&tegra_car 54>; - reset-names = "i2c"; - dmas = <&apbdma 22>, <&apbdma 22>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c500 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; - reg = <0x0 0x7000c500 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_I2C3>; - clock-names = "div-clk"; - resets = <&tegra_car 67>; - reset-names = "i2c"; - dmas = <&apbdma 23>, <&apbdma 23>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000c700 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; - reg = <0x0 0x7000c700 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_I2C4>; - clock-names = "div-clk"; - resets = <&tegra_car 103>; - reset-names = "i2c"; - dmas = <&apbdma 26>, <&apbdma 26>; - dma-names = "rx", "tx"; - pinctrl-0 = <&state_dpaux1_i2c>; - pinctrl-1 = <&state_dpaux1_off>; - pinctrl-names = "default", "idle"; - status = "disabled"; - }; - - i2c@7000d000 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; - reg = <0x0 0x7000d000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_I2C5>; - clock-names = "div-clk"; - resets = <&tegra_car 47>; - reset-names = "i2c"; - dmas = <&apbdma 24>, <&apbdma 24>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c@7000d100 { - compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; - reg = <0x0 0x7000d100 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_I2C6>; - clock-names = "div-clk"; - resets = <&tegra_car 166>; - reset-names = "i2c"; - dmas = <&apbdma 30>, <&apbdma 30>; - dma-names = "rx", "tx"; - pinctrl-0 = <&state_dpaux_i2c>; - pinctrl-1 = <&state_dpaux_off>; - pinctrl-names = "default", "idle"; - status = "disabled"; - }; - - spi@7000d400 { - compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000d400 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_SBC1>; - clock-names = "spi"; - resets = <&tegra_car 41>; - reset-names = "spi"; - dmas = <&apbdma 15>, <&apbdma 15>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d600 { - compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000d600 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_SBC2>; - clock-names = "spi"; - resets = <&tegra_car 44>; - reset-names = "spi"; - dmas = <&apbdma 16>, <&apbdma 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000d800 { - compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000d800 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_SBC3>; - clock-names = "spi"; - resets = <&tegra_car 46>; - reset-names = "spi"; - dmas = <&apbdma 17>, <&apbdma 17>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi@7000da00 { - compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; - reg = <0x0 0x7000da00 0x0 0x200>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_SBC4>; - clock-names = "spi"; - resets = <&tegra_car 68>; - reset-names = "spi"; - dmas = <&apbdma 18>, <&apbdma 18>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - rtc@7000e000 { - compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; - reg = <0x0 0x7000e000 0x0 0x100>; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&tegra_pmc>; - clocks = <&tegra_car TEGRA210_CLK_RTC>; - clock-names = "rtc"; - }; - - tegra_pmc: pmc@7000e400 { - compatible = "nvidia,tegra210-pmc"; - reg = <0x0 0x7000e400 0x0 0x400>; - clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - #clock-cells = <1>; - #interrupt-cells = <2>; - interrupt-controller; - - powergates { - pd_audio: aud { - clocks = <&tegra_car TEGRA210_CLK_APE>, - <&tegra_car TEGRA210_CLK_APB2APE>; - resets = <&tegra_car 198>; - #power-domain-cells = <0>; - }; - - pd_sor: sor { - clocks = <&tegra_car TEGRA210_CLK_SOR0>, - <&tegra_car TEGRA210_CLK_SOR1>, - <&tegra_car TEGRA210_CLK_CILAB>, - <&tegra_car TEGRA210_CLK_CILCD>, - <&tegra_car TEGRA210_CLK_CILE>, - <&tegra_car TEGRA210_CLK_DSIA>, - <&tegra_car TEGRA210_CLK_DSIB>, - <&tegra_car TEGRA210_CLK_DPAUX>, - <&tegra_car TEGRA210_CLK_DPAUX1>, - <&tegra_car TEGRA210_CLK_MIPI_CAL>; - resets = <&tegra_car TEGRA210_CLK_SOR0>, - <&tegra_car TEGRA210_CLK_SOR1>, - <&tegra_car TEGRA210_CLK_DSIA>, - <&tegra_car TEGRA210_CLK_DSIB>, - <&tegra_car TEGRA210_CLK_DPAUX>, - <&tegra_car TEGRA210_CLK_DPAUX1>, - <&tegra_car TEGRA210_CLK_MIPI_CAL>; - #power-domain-cells = <0>; - }; - - pd_xusbss: xusba { - clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; - resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; - #power-domain-cells = <0>; - }; - - pd_xusbdev: xusbb { - clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; - resets = <&tegra_car 95>; - #power-domain-cells = <0>; - }; - - pd_xusbhost: xusbc { - clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; - resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; - #power-domain-cells = <0>; - }; - - pd_vic: vic { - clocks = <&tegra_car TEGRA210_CLK_VIC03>; - clock-names = "vic"; - resets = <&tegra_car 178>; - reset-names = "vic"; - #power-domain-cells = <0>; - }; - - pd_venc: venc { - clocks = <&tegra_car TEGRA210_CLK_VI>, - <&tegra_car TEGRA210_CLK_CSI>; - resets = <&mc TEGRA210_MC_RESET_VI>, - <&tegra_car 20>, - <&tegra_car 52>; - #power-domain-cells = <0>; - }; - }; - - sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1"; - power-source = ; - }; - - sdmmc1_1v8: sdmmc1-1v8 { - pins = "sdmmc1"; - power-source = ; - }; - - sdmmc3_3v3: sdmmc3-3v3 { - pins = "sdmmc3"; - power-source = ; - }; - - sdmmc3_1v8: sdmmc3-1v8 { - pins = "sdmmc3"; - power-source = ; - }; - - pex_dpd_disable: pex_en { - pex-dpd-disable { - pins = "pex-bias", "pex-clk1", "pex-clk2"; - low-power-disable; - }; - }; - - pex_dpd_enable: pex_dis { - pex-dpd-enable { - pins = "pex-bias", "pex-clk1", "pex-clk2"; - low-power-enable; - }; - }; - }; - - fuse@7000f800 { - compatible = "nvidia,tegra210-efuse"; - reg = <0x0 0x7000f800 0x0 0x400>; - clocks = <&tegra_car TEGRA210_CLK_FUSE>; - clock-names = "fuse"; - resets = <&tegra_car 39>; - reset-names = "fuse"; - }; - - mc: memory-controller@70019000 { - compatible = "nvidia,tegra210-mc"; - reg = <0x0 0x70019000 0x0 0x1000>; - clocks = <&tegra_car TEGRA210_CLK_MC>; - clock-names = "mc"; - - interrupts = ; - - #iommu-cells = <1>; - #reset-cells = <1>; - }; - - emc: external-memory-controller@7001b000 { - compatible = "nvidia,tegra210-emc"; - reg = <0x0 0x7001b000 0x0 0x1000>, - <0x0 0x7001e000 0x0 0x1000>, - <0x0 0x7001f000 0x0 0x1000>; - clocks = <&tegra_car TEGRA210_CLK_EMC>; - clock-names = "emc"; - interrupts = ; - nvidia,memory-controller = <&mc>; - #cooling-cells = <2>; - }; - - sata@70020000 { - compatible = "nvidia,tegra210-ahci"; - reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ - <0x0 0x70020000 0x0 0x7000>, /* SATA */ - <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SATA>, - <&tegra_car TEGRA210_CLK_SATA_OOB>; - clock-names = "sata", "sata-oob"; - resets = <&tegra_car 124>, - <&tegra_car 123>, - <&tegra_car 129>; - reset-names = "sata", "sata-oob", "sata-cold"; - status = "disabled"; - }; - - hda@70030000 { - compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; - reg = <0x0 0x70030000 0x0 0x10000>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_HDA>, - <&tegra_car TEGRA210_CLK_HDA2HDMI>, - <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; - clock-names = "hda", "hda2hdmi", "hda2codec_2x"; - resets = <&tegra_car 125>, /* hda */ - <&tegra_car 128>, /* hda2hdmi */ - <&tegra_car 111>; /* hda2codec_2x */ - reset-names = "hda", "hda2hdmi", "hda2codec_2x"; - power-domains = <&pd_sor>; - status = "disabled"; - }; - - usb@70090000 { - compatible = "nvidia,tegra210-xusb"; - reg = <0x0 0x70090000 0x0 0x8000>, - <0x0 0x70098000 0x0 0x1000>, - <0x0 0x70099000 0x0 0x1000>; - reg-names = "hcd", "fpci", "ipfs"; - - interrupts = , - ; - - clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, - <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, - <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, - <&tegra_car TEGRA210_CLK_XUSB_SS>, - <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, - <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, - <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, - <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, - <&tegra_car TEGRA210_CLK_PLL_U_480M>, - <&tegra_car TEGRA210_CLK_CLK_M>, - <&tegra_car TEGRA210_CLK_PLL_E>; - clock-names = "xusb_host", "xusb_host_src", - "xusb_falcon_src", "xusb_ss", - "xusb_ss_src", "xusb_ss_div2", - "xusb_hs_src", "xusb_fs_src", - "pll_u_480m", "clk_m", "pll_e"; - resets = <&tegra_car 89>, <&tegra_car 156>, - <&tegra_car 143>; - reset-names = "xusb_host", "xusb_ss", "xusb_src"; - power-domains = <&pd_xusbhost>, <&pd_xusbss>; - power-domain-names = "xusb_host", "xusb_ss"; - - nvidia,xusb-padctl = <&padctl>; - - status = "disabled"; - }; - - padctl: padctl@7009f000 { - compatible = "nvidia,tegra210-xusb-padctl"; - reg = <0x0 0x7009f000 0x0 0x1000>; - resets = <&tegra_car 142>; - reset-names = "padctl"; - - status = "disabled"; - - pads { - usb2 { - clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; - clock-names = "trk"; - status = "disabled"; - - lanes { - usb2-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-2 { - status = "disabled"; - #phy-cells = <0>; - }; - - usb2-3 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - hsic { - clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; - clock-names = "trk"; - status = "disabled"; - - lanes { - hsic-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - hsic-1 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - pcie { - clocks = <&tegra_car TEGRA210_CLK_PLL_E>; - clock-names = "pll"; - resets = <&tegra_car 205>; - reset-names = "phy"; - status = "disabled"; - - lanes { - pcie-0 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-1 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-2 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-3 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-4 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-5 { - status = "disabled"; - #phy-cells = <0>; - }; - - pcie-6 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - - sata { - clocks = <&tegra_car TEGRA210_CLK_PLL_E>; - clock-names = "pll"; - resets = <&tegra_car 204>; - reset-names = "phy"; - status = "disabled"; - - lanes { - sata-0 { - status = "disabled"; - #phy-cells = <0>; - }; - }; - }; - }; - - ports { - usb2-0 { - status = "disabled"; - }; - - usb2-1 { - status = "disabled"; - }; - - usb2-2 { - status = "disabled"; - }; - - usb2-3 { - status = "disabled"; - }; - - hsic-0 { - status = "disabled"; - }; - - usb3-0 { - status = "disabled"; - }; - - usb3-1 { - status = "disabled"; - }; - - usb3-2 { - status = "disabled"; - }; - - usb3-3 { - status = "disabled"; - }; - }; - }; - - mmc@700b0000 { - compatible = "nvidia,tegra210-sdhci"; - reg = <0x0 0x700b0000 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, - <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; - clock-names = "sdhci", "tmclk"; - resets = <&tegra_car 14>; - reset-names = "sdhci"; - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", - "sdmmc-3v3-drv", "sdmmc-1v8-drv"; - pinctrl-0 = <&sdmmc1_3v3>; - pinctrl-1 = <&sdmmc1_1v8>; - pinctrl-2 = <&sdmmc1_3v3_drv>; - pinctrl-3 = <&sdmmc1_1v8_drv>; - nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; - nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; - nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; - nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; - nvidia,default-tap = <0x2>; - nvidia,default-trim = <0x4>; - assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, - <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, - <&tegra_car TEGRA210_CLK_PLL_C4>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; - assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; - status = "disabled"; - }; - - mmc@700b0200 { - compatible = "nvidia,tegra210-sdhci"; - reg = <0x0 0x700b0200 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SDMMC2>, - <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; - clock-names = "sdhci", "tmclk"; - resets = <&tegra_car 9>; - reset-names = "sdhci"; - pinctrl-names = "sdmmc-1v8-drv"; - pinctrl-0 = <&sdmmc2_1v8_drv>; - nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; - nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; - nvidia,default-tap = <0x8>; - nvidia,default-trim = <0x0>; - status = "disabled"; - }; - - mmc@700b0400 { - compatible = "nvidia,tegra210-sdhci"; - reg = <0x0 0x700b0400 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SDMMC3>, - <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; - clock-names = "sdhci", "tmclk"; - resets = <&tegra_car 69>; - reset-names = "sdhci"; - pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", - "sdmmc-3v3-drv", "sdmmc-1v8-drv"; - pinctrl-0 = <&sdmmc3_3v3>; - pinctrl-1 = <&sdmmc3_1v8>; - pinctrl-2 = <&sdmmc3_3v3_drv>; - pinctrl-3 = <&sdmmc3_1v8_drv>; - nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; - nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; - nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; - nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; - nvidia,default-tap = <0x3>; - nvidia,default-trim = <0x3>; - status = "disabled"; - }; - - mmc@700b0600 { - compatible = "nvidia,tegra210-sdhci"; - reg = <0x0 0x700b0600 0x0 0x200>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, - <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; - clock-names = "sdhci", "tmclk"; - resets = <&tegra_car 15>; - reset-names = "sdhci"; - pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; - pinctrl-0 = <&sdmmc4_1v8_drv>; - pinctrl-1 = <&sdmmc4_1v8_drv>; - nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; - nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; - nvidia,default-tap = <0x8>; - nvidia,default-trim = <0x0>; - assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, - <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; - nvidia,dqs-trim = <40>; - mmc-hs400-1_8v; - status = "disabled"; - }; - - usb@700d0000 { - compatible = "nvidia,tegra210-xudc"; - reg = <0x0 0x700d0000 0x0 0x8000>, - <0x0 0x700d8000 0x0 0x1000>, - <0x0 0x700d9000 0x0 0x1000>; - reg-names = "base", "fpci", "ipfs"; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, - <&tegra_car TEGRA210_CLK_XUSB_SS>, - <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, - <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, - <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; - clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; - power-domains = <&pd_xusbdev>, <&pd_xusbss>; - power-domain-names = "dev", "ss"; - nvidia,xusb-padctl = <&padctl>; - status = "disabled"; - }; - - mipi: mipi@700e3000 { - compatible = "nvidia,tegra210-mipi"; - reg = <0x0 0x700e3000 0x0 0x100>; - clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; - clock-names = "mipi-cal"; - power-domains = <&pd_sor>; - #nvidia,mipi-calibrate-cells = <1>; - }; - - dfll: clock@70110000 { - compatible = "nvidia,tegra210-dfll"; - reg = <0 0x70110000 0 0x100>, /* DFLL control */ - <0 0x70110000 0 0x100>, /* I2C output control */ - <0 0x70110100 0 0x100>, /* Integrated I2C controller */ - <0 0x70110200 0 0x100>; /* Look-up table RAM */ - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, - <&tegra_car TEGRA210_CLK_DFLL_REF>, - <&tegra_car TEGRA210_CLK_I2C5>; - clock-names = "soc", "ref", "i2c"; - resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; - reset-names = "dvco"; - #clock-cells = <0>; - clock-output-names = "dfllCPU_out"; - status = "disabled"; - }; - - aconnect@702c0000 { - compatible = "nvidia,tegra210-aconnect"; - clocks = <&tegra_car TEGRA210_CLK_APE>, - <&tegra_car TEGRA210_CLK_APB2APE>; - clock-names = "ape", "apb2ape"; - power-domains = <&pd_audio>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; - status = "disabled"; - - adma: dma@702e2000 { - compatible = "nvidia,tegra210-adma"; - reg = <0x702e2000 0x2000>; - interrupt-parent = <&agic>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - #dma-cells = <1>; - clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; - clock-names = "d_audio"; - status = "disabled"; - }; - - agic: interrupt-controller@702f9000 { - compatible = "nvidia,tegra210-agic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x702f9000 0x1000>, - <0x702fa000 0x2000>; - interrupts = ; - clocks = <&tegra_car TEGRA210_CLK_APE>; - clock-names = "clk"; - status = "disabled"; - }; - - tegra_ahub: ahub@702d0800 { - compatible = "nvidia,tegra210-ahub"; - reg = <0x702d0800 0x800>; - clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; - clock-names = "ahub"; - assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x702d0000 0x702d0000 0x0000e400>; - status = "disabled"; - - tegra_admaif: admaif@702d0000 { - compatible = "nvidia,tegra210-admaif"; - reg = <0x702d0000 0x800>; - dmas = <&adma 1>, <&adma 1>, - <&adma 2>, <&adma 2>, - <&adma 3>, <&adma 3>, - <&adma 4>, <&adma 4>, - <&adma 5>, <&adma 5>, - <&adma 6>, <&adma 6>, - <&adma 7>, <&adma 7>, - <&adma 8>, <&adma 8>, - <&adma 9>, <&adma 9>, - <&adma 10>, <&adma 10>; - dma-names = "rx1", "tx1", - "rx2", "tx2", - "rx3", "tx3", - "rx4", "tx4", - "rx5", "tx5", - "rx6", "tx6", - "rx7", "tx7", - "rx8", "tx8", - "rx9", "tx9", - "rx10", "tx10"; - status = "disabled"; - }; - - tegra_i2s1: i2s@702d1000 { - compatible = "nvidia,tegra210-i2s"; - reg = <0x702d1000 0x100>; - clocks = <&tegra_car TEGRA210_CLK_I2S0>, - <&tegra_car TEGRA210_CLK_I2S0_SYNC>; - clock-names = "i2s", "sync_input"; - assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; - assigned-clock-rates = <1536000>; - sound-name-prefix = "I2S1"; - status = "disabled"; - }; - - tegra_i2s2: i2s@702d1100 { - compatible = "nvidia,tegra210-i2s"; - reg = <0x702d1100 0x100>; - clocks = <&tegra_car TEGRA210_CLK_I2S1>, - <&tegra_car TEGRA210_CLK_I2S1_SYNC>; - clock-names = "i2s", "sync_input"; - assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; - assigned-clock-rates = <1536000>; - sound-name-prefix = "I2S2"; - status = "disabled"; - }; - - tegra_i2s3: i2s@702d1200 { - compatible = "nvidia,tegra210-i2s"; - reg = <0x702d1200 0x100>; - clocks = <&tegra_car TEGRA210_CLK_I2S2>, - <&tegra_car TEGRA210_CLK_I2S2_SYNC>; - clock-names = "i2s", "sync_input"; - assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; - assigned-clock-rates = <1536000>; - sound-name-prefix = "I2S3"; - status = "disabled"; - }; - - tegra_i2s4: i2s@702d1300 { - compatible = "nvidia,tegra210-i2s"; - reg = <0x702d1300 0x100>; - clocks = <&tegra_car TEGRA210_CLK_I2S3>, - <&tegra_car TEGRA210_CLK_I2S3_SYNC>; - clock-names = "i2s", "sync_input"; - assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; - assigned-clock-rates = <1536000>; - sound-name-prefix = "I2S4"; - status = "disabled"; - }; - - tegra_i2s5: i2s@702d1400 { - compatible = "nvidia,tegra210-i2s"; - reg = <0x702d1400 0x100>; - clocks = <&tegra_car TEGRA210_CLK_I2S4>, - <&tegra_car TEGRA210_CLK_I2S4_SYNC>; - clock-names = "i2s", "sync_input"; - assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; - assigned-clock-rates = <1536000>; - sound-name-prefix = "I2S5"; - status = "disabled"; - }; - - tegra_dmic1: dmic@702d4000 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x702d4000 0x100>; - clocks = <&tegra_car TEGRA210_CLK_DMIC1>; - clock-names = "dmic"; - assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC1"; - status = "disabled"; - }; - - tegra_dmic2: dmic@702d4100 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x702d4100 0x100>; - clocks = <&tegra_car TEGRA210_CLK_DMIC2>; - clock-names = "dmic"; - assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC2"; - status = "disabled"; - }; - - tegra_dmic3: dmic@702d4200 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x702d4200 0x100>; - clocks = <&tegra_car TEGRA210_CLK_DMIC3>; - clock-names = "dmic"; - assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC3"; - status = "disabled"; - }; - }; - }; - - spi@70410000 { - compatible = "nvidia,tegra210-qspi"; - reg = <0x0 0x70410000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_QSPI>; - clock-names = "qspi"; - resets = <&tegra_car 211>; - reset-names = "qspi"; - dmas = <&apbdma 5>, <&apbdma 5>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - usb@7d000000 { - compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x0 0x7d000000 0x0 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA210_CLK_USBD>; - clock-names = "usb"; - resets = <&tegra_car 22>; - reset-names = "usb"; - nvidia,phy = <&phy1>; - status = "disabled"; - }; - - phy1: usb-phy@7d000000 { - compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x0 0x7d000000 0x0 0x4000>, - <0x0 0x7d000000 0x0 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA210_CLK_USBD>, - <&tegra_car TEGRA210_CLK_PLL_U>, - <&tegra_car TEGRA210_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 22>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - nvidia,has-utmi-pad-registers; - status = "disabled"; - }; - - usb@7d004000 { - compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x0 0x7d004000 0x0 0x4000>; - interrupts = ; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA210_CLK_USB2>; - clock-names = "usb"; - resets = <&tegra_car 58>; - reset-names = "usb"; - nvidia,phy = <&phy2>; - status = "disabled"; - }; - - phy2: usb-phy@7d004000 { - compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x0 0x7d004000 0x0 0x4000>, - <0x0 0x7d000000 0x0 0x4000>; - phy_type = "utmi"; - clocks = <&tegra_car TEGRA210_CLK_USB2>, - <&tegra_car TEGRA210_CLK_PLL_U>, - <&tegra_car TEGRA210_CLK_USBD>; - clock-names = "reg", "pll_u", "utmi-pads"; - resets = <&tegra_car 58>, <&tegra_car 22>; - reset-names = "usb", "utmi-pads"; - nvidia,hssync-start-delay = <0>; - nvidia,idle-wait-delay = <17>; - nvidia,elastic-limit = <16>; - nvidia,term-range-adj = <6>; - nvidia,xcvr-setup = <9>; - nvidia,xcvr-lsfslew = <0>; - nvidia,xcvr-lsrslew = <3>; - nvidia,hssquelch-level = <2>; - nvidia,hsdiscon-level = <5>; - nvidia,xcvr-hsslew = <12>; - status = "disabled"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0>; - clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, - <&tegra_car TEGRA210_CLK_PLL_X>, - <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, - <&dfll>; - clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; - clock-latency = <300000>; - cpu-idle-states = <&CPU_SLEEP>; - next-level-cache = <&L2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <1>; - cpu-idle-states = <&CPU_SLEEP>; - next-level-cache = <&L2>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <2>; - cpu-idle-states = <&CPU_SLEEP>; - next-level-cache = <&L2>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <3>; - cpu-idle-states = <&CPU_SLEEP>; - next-level-cache = <&L2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x40000007>; - entry-latency-us = <100>; - exit-latency-us = <30>; - min-residency-us = <1000>; - wakeup-latency-us = <130>; - idle-state-name = "cpu-sleep"; - status = "disabled"; - }; - }; - - L2: l2-cache { - compatible = "cache"; - }; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} - &{/cpus/cpu@2} &{/cpus/cpu@3}>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - interrupt-parent = <&gic>; - arm,no-tick-in-suspend; - }; - - soctherm: thermal-sensor@700e2000 { - compatible = "nvidia,tegra210-soctherm"; - reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ - <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ - reg-names = "soctherm-reg", "car-reg"; - interrupts = , - ; - interrupt-names = "thermal", "edp"; - clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, - <&tegra_car TEGRA210_CLK_SOC_THERM>; - clock-names = "tsensor", "soctherm"; - resets = <&tegra_car 78>; - reset-names = "soctherm"; - #thermal-sensor-cells = <1>; - - throttle-cfgs { - throttle_heavy: heavy { - nvidia,priority = <100>; - nvidia,cpu-throt-percent = <85>; - - #cooling-cells = <2>; - }; - }; - }; - - thermal-zones { - cpu { - polling-delay-passive = <1000>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; - - trips { - cpu-shutdown-trip { - temperature = <102500>; - hysteresis = <0>; - type = "critical"; - }; - - cpu_throttle_trip: throttle-trip { - temperature = <98500>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_throttle_trip>; - cooling-device = <&throttle_heavy 1 1>; - }; - }; - }; - - mem { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; - - trips { - dram_nominal: mem-nominal-trip { - temperature = <50000>; - hysteresis = <1000>; - type = "passive"; - }; - - dram_throttle: mem-throttle-trip { - temperature = <70000>; - hysteresis = <1000>; - type = "active"; - }; - - mem-shutdown-trip { - temperature = <103000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - dram-passive { - cooling-device = <&emc 0 0>; - trip = <&dram_nominal>; - }; - - dram-active { - cooling-device = <&emc 1 1>; - trip = <&dram_throttle>; - }; - }; - }; - - gpu { - polling-delay-passive = <1000>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; - - trips { - gpu-shutdown-trip { - temperature = <103000>; - hysteresis = <0>; - type = "critical"; - }; - - gpu_throttle_trip: throttle-trip { - temperature = <100000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_throttle_trip>; - cooling-device = <&throttle_heavy 1 1>; - }; - }; - }; - - pllx { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; - - trips { - pllx-shutdown-trip { - temperature = <103000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - /* - * There are currently no cooling maps, - * because there are no cooling devices. - */ - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts b/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts deleted file mode 100644 index b5d9a5526..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "tegra234.dtsi" - -/ { - model = "NVIDIA Tegra234 VDK"; - compatible = "nvidia,tegra234-vdk", "nvidia,tegra234"; - - aliases { - mmc3 = "/bus@0/mmc@3460000"; - serial0 = &uarta; - }; - - chosen { - bootargs = "console=ttyS0,115200n8 earlycon=uart8250,mmio32,0x03100000"; - stdout-path = "serial0:115200n8"; - }; - - bus@0 { - serial@3100000 { - status = "okay"; - }; - - mmc@3460000 { - status = "okay"; - bus-width = <8>; - non-removable; - only-1-8-v; - }; - - rtc@c2a0000 { - status = "okay"; - }; - - pmc@c360000 { - nvidia,invert-interrupt; - }; - }; -}; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi deleted file mode 100644 index f0efb3a62..000000000 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ /dev/null @@ -1,189 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include -#include -#include -#include - -/ { - compatible = "nvidia,tegra234"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - bus@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x0 0x0 0x0 0x40000000>; - - misc@100000 { - compatible = "nvidia,tegra234-misc"; - reg = <0x00100000 0xf000>, - <0x0010f000 0x1000>; - status = "okay"; - }; - - uarta: serial@3100000 { - compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; - reg = <0x03100000 0x10000>; - interrupts = ; - clocks = <&bpmp TEGRA234_CLK_UARTA>; - clock-names = "serial"; - resets = <&bpmp TEGRA234_RESET_UARTA>; - reset-names = "serial"; - status = "disabled"; - }; - - mmc@3460000 { - compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; - reg = <0x03460000 0x20000>; - interrupts = ; - clocks = <&bpmp TEGRA234_CLK_SDMMC4>; - clock-names = "sdhci"; - resets = <&bpmp TEGRA234_RESET_SDMMC4>; - reset-names = "sdhci"; - dma-coherent; - status = "disabled"; - }; - - fuse@3810000 { - compatible = "nvidia,tegra234-efuse"; - reg = <0x03810000 0x10000>; - clocks = <&bpmp TEGRA234_CLK_FUSE>; - clock-names = "fuse"; - }; - - hsp_top0: hsp@3c00000 { - compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; - reg = <0x03c00000 0xa0000>; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "doorbell", "shared0", "shared1", "shared2", - "shared3", "shared4", "shared5", "shared6", - "shared7"; - #mbox-cells = <2>; - }; - - hsp_aon: hsp@c150000 { - compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; - reg = <0x0c150000 0x90000>; - interrupts = , - , - , - ; - /* - * Shared interrupt 0 is routed only to AON/SPE, so - * we only have 4 shared interrupts for the CCPLEX. - */ - interrupt-names = "shared1", "shared2", "shared3", "shared4"; - #mbox-cells = <2>; - }; - - rtc@c2a0000 { - compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; - reg = <0x0c2a0000 0x10000>; - interrupt-parent = <&pmc>; - interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - pmc: pmc@c360000 { - compatible = "nvidia,tegra234-pmc"; - reg = <0x0c360000 0x10000>, - <0x0c370000 0x10000>, - <0x0c380000 0x10000>, - <0x0c390000 0x10000>, - <0x0c3a0000 0x10000>; - reg-names = "pmc", "wake", "aotag", "scratch", "misc"; - - #interrupt-cells = <2>; - interrupt-controller; - }; - - gic: interrupt-controller@f400000 { - compatible = "arm,gic-v3"; - reg = <0x0f400000 0x010000>, /* GICD */ - <0x0f440000 0x200000>; /* GICR */ - interrupt-parent = <&gic>; - interrupts = ; - - #redistributor-regions = <1>; - #interrupt-cells = <3>; - interrupt-controller; - }; - }; - - sysram@40000000 { - compatible = "nvidia,tegra234-sysram", "mmio-sram"; - reg = <0x0 0x40000000 0x0 0x50000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x40000000 0x50000>; - - cpu_bpmp_tx: shmem@4e000 { - reg = <0x4e000 0x1000>; - label = "cpu-bpmp-tx"; - pool; - }; - - cpu_bpmp_rx: shmem@4f000 { - reg = <0x4f000 0x1000>; - label = "cpu-bpmp-rx"; - pool; - }; - }; - - bpmp: bpmp { - compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB - TEGRA_HSP_DB_MASTER_BPMP>; - shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - - bpmp_i2c: i2c { - compatible = "nvidia,tegra186-bpmp-i2c"; - nvidia,bpmp-bus-id = <5>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - reg = <0x000>; - - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - status = "okay"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - interrupt-parent = <&gic>; - always-on; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile deleted file mode 100644 index fb4631f89..000000000 --- a/arch/arm64/boot/dts/qcom/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb -dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb -dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-talkman.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8992-xiaomi-libra.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-sumire.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb -dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb -dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts deleted file mode 100644 index 48bd1c287..000000000 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include "apq8016-sbc.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. APQ 8016 SBC"; - compatible = "qcom,apq8016-sbc", "qcom,apq8016", "qcom,sbc"; -}; diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi deleted file mode 100644 index 3c7f97539..000000000 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ /dev/null @@ -1,831 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - */ - -#include "msm8916-pm8916.dtsi" -#include -#include -#include -#include -#include - -/ { - aliases { - serial0 = &blsp1_uart2; - serial1 = &blsp1_uart1; - usid0 = &pm8916_0; - i2c0 = &blsp_i2c2; - i2c1 = &blsp_i2c6; - i2c3 = &blsp_i2c4; - spi0 = &blsp_spi5; - spi1 = &blsp_spi3; - }; - - chosen { - stdout-path = "serial0"; - }; - - camera_vdddo_1v8: camera-vdddo-1v8 { - compatible = "regulator-fixed"; - regulator-name = "camera_vdddo"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - camera_vdda_2v8: camera-vdda-2v8 { - compatible = "regulator-fixed"; - regulator-name = "camera_vdda"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - camera_vddd_1v5: camera-vddd-1v5 { - compatible = "regulator-fixed"; - regulator-name = "camera_vddd"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - reserved-memory { - ramoops@bff00000 { - compatible = "ramoops"; - reg = <0x0 0xbff00000 0x0 0x100000>; - - record-size = <0x20000>; - console-size = <0x20000>; - ftrace-size = <0x20000>; - }; - }; - - usb2513 { - compatible = "smsc,usb3503"; - reset-gpios = <&pm8916_gpios 3 GPIO_ACTIVE_LOW>; - initial-mode = <1>; - }; - - usb_id: usb-id { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_id_default>; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7533_out>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&msm_key_volp_n_default>; - - button@0 { - label = "Volume Up"; - linux,code = ; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&msmgpio_leds>, - <&pm8916_gpios_leds>, - <&pm8916_mpps_leds>; - - compatible = "gpio-leds"; - - led@1 { - label = "apq8016-sbc:green:user1"; - gpios = <&msmgpio 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led@2 { - label = "apq8016-sbc:green:user2"; - gpios = <&msmgpio 120 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led@3 { - label = "apq8016-sbc:green:user3"; - gpios = <&pm8916_gpios 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led@4 { - label = "apq8016-sbc:green:user4"; - gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - panic-indicator; - default-state = "off"; - }; - - led@5 { - label = "apq8016-sbc:yellow:wlan"; - gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - led@6 { - label = "apq8016-sbc:blue:bt"; - gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "bluetooth-power"; - default-state = "off"; - }; - }; -}; - -&blsp_dma { - status = "okay"; -}; - -&blsp_i2c2 { - /* On Low speed expansion */ - status = "okay"; - label = "LS-I2C0"; -}; - -&blsp_i2c4 { - /* On High speed expansion */ - status = "okay"; - label = "HS-I2C2"; - - adv_bridge: bridge@39 { - status = "okay"; - - compatible = "adi,adv7533"; - reg = <0x39>; - - interrupt-parent = <&msmgpio>; - interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - - adi,dsi-lanes = <4>; - clocks = <&rpmcc RPM_SMD_BB_CLK2>; - clock-names = "cec"; - - pd-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; - - avdd-supply = <&pm8916_l6>; - v1p2-supply = <&pm8916_l6>; - v3p3-supply = <&pm8916_l17>; - - pinctrl-names = "default","sleep"; - pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>; - pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>; - #sound-dai-cells = <1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7533_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - adv7533_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&blsp_i2c6 { - /* On Low speed expansion */ - status = "okay"; - label = "LS-I2C1"; -}; - -&blsp_spi3 { - /* On High speed expansion */ - status = "okay"; - label = "HS-SPI1"; -}; - -&blsp_spi5 { - /* On Low speed expansion */ - status = "okay"; - label = "LS-SPI0"; -}; - -&blsp1_uart1 { - status = "okay"; - label = "LS-UART0"; -}; - -&blsp1_uart2 { - status = "okay"; - label = "LS-UART1"; -}; - -&camss { - status = "okay"; - ports { - port@0 { - reg = <0>; - csiphy0_ep: endpoint { - clock-lanes = <1>; - data-lanes = <0 2>; - remote-endpoint = <&ov5640_ep>; - status = "okay"; - }; - }; - }; -}; - -&cci { - status = "okay"; -}; - -&cci_i2c0 { - camera_rear@3b { - compatible = "ovti,ov5640"; - reg = <0x3b>; - - enable-gpios = <&msmgpio 34 GPIO_ACTIVE_HIGH>; - reset-gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&camera_rear_default>; - - clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; - clock-names = "xclk"; - clock-frequency = <23880000>; - - vdddo-supply = <&camera_vdddo_1v8>; - vdda-supply = <&camera_vdda_2v8>; - vddd-supply = <&camera_vddd_1v5>; - - /* No camera mezzanine by default */ - status = "disabled"; - - port { - ov5640_ep: endpoint { - clock-lanes = <1>; - data-lanes = <0 2>; - remote-endpoint = <&csiphy0_ep>; - }; - }; - }; -}; - -&dsi0_out { - data-lanes = <0 1 2 3>; - remote-endpoint = <&adv7533_in>; -}; - -&lpass { - status = "okay"; -}; - -&pm8916_resin { - status = "okay"; - linux,code = ; -}; - -&pronto { - status = "okay"; -}; - -&sdhc_1 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; -}; - -&sdhc_2 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; -}; - -&sound { - status = "okay"; - - pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>; - pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>; - pinctrl-names = "default", "sleep"; - qcom,model = "DB410c"; - qcom,audio-routing = - "AMIC2", "MIC BIAS Internal2", - "AMIC3", "MIC BIAS External1"; - - external-dai-link@0 { - link-name = "ADV7533"; - cpu { - sound-dai = <&lpass MI2S_QUATERNARY>; - }; - codec { - sound-dai = <&adv_bridge 0>; - }; - }; - - internal-codec-playback-dai-link@0 { - link-name = "WCD"; - cpu { - sound-dai = <&lpass MI2S_PRIMARY>; - }; - codec { - sound-dai = <&lpass_codec 0>, <&wcd_codec 0>; - }; - }; - - internal-codec-capture-dai-link@0 { - link-name = "WCD-Capture"; - cpu { - sound-dai = <&lpass MI2S_TERTIARY>; - }; - codec { - sound-dai = <&lpass_codec 1>, <&wcd_codec 1>; - }; - }; -}; - -&usb { - status = "okay"; - extcon = <&usb_id>, <&usb_id>; - - pinctrl-names = "default", "device"; - pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>; - pinctrl-1 = <&usb_sw_sel_pm_device &usb_hub_reset_pm_device>; -}; - -&usb_hs_phy { - extcon = <&usb_id>; -}; - -&wcd_codec { - clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; - clock-names = "mclk"; - qcom,mbhc-vthreshold-low = <75 150 237 450 500>; - qcom,mbhc-vthreshold-high = <75 150 237 450 500>; -}; - -/* Enable CoreSight */ -&cti0 { status = "okay"; }; -&cti1 { status = "okay"; }; -&cti12 { status = "okay"; }; -&cti13 { status = "okay"; }; -&cti14 { status = "okay"; }; -&cti15 { status = "okay"; }; -&debug0 { status = "okay"; }; -&debug1 { status = "okay"; }; -&debug2 { status = "okay"; }; -&debug3 { status = "okay"; }; -&etf { status = "okay"; }; -&etm0 { status = "okay"; }; -&etm1 { status = "okay"; }; -&etm2 { status = "okay"; }; -&etm3 { status = "okay"; }; -&etr { status = "okay"; }; -&funnel0 { status = "okay"; }; -&funnel1 { status = "okay"; }; -&replicator { status = "okay"; }; -&tpiu { status = "okay"; }; - -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s1 { - regulator-min-microvolt = <375000>; - regulator-max-microvolt = <1562000>; - }; - - s3 { - regulator-min-microvolt = <375000>; - regulator-max-microvolt = <1562000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - }; - - l1 { - regulator-min-microvolt = <375000>; - regulator-max-microvolt = <1525000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <375000>; - regulator-max-microvolt = <1525000>; - }; - - l4 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l5 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l8 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l9 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l10 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l11 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l13 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l14 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - /** - * 1.8v required on LS expansion - * for mezzanine boards - */ - l15 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - regulator-always-on; - }; - - l16 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; - - l17 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l18 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <3337000>; - }; -}; - -/* - * 2mA drive strength is not enough when connecting multiple - * I2C devices with different pull up resistors. - */ -&i2c2_default { - drive-strength = <16>; -}; - -&i2c4_default { - drive-strength = <16>; -}; - -&i2c6_default { - drive-strength = <16>; -}; - -/* - * GPIO name legend: proper name = the GPIO line is used as GPIO - * NC = not connected (pin out but not routed from the chip to - * anything the board) - * "[PER]" = pin is muxed for [peripheral] (not GPIO) - * LSEC = Low Speed External Connector - * HSEC = High Speed External Connector - * - * Line names are taken from the schematic "DragonBoard410c" - * dated monday, august 31, 2015. Page 5 in particular. - * - * For the lines routed to the external connectors the - * lines are named after the 96Boards CE Specification 1.0, - * Appendix "Expansion Connector Signal Description". - * - * When the 96Board naming of a line and the schematic name of - * the same line are in conflict, the 96Board specification - * takes precedence, which means that the external UART on the - * LSEC is named UART0 while the schematic and SoC names this - * UART3. This is only for the informational lines i.e. "[FOO]", - * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only - * ones actually used for GPIO. - */ - -&msmgpio { - gpio-line-names = - "[UART0_TX]", /* GPIO_0, LSEC pin 5 */ - "[UART0_RX]", /* GPIO_1, LSEC pin 7 */ - "[UART0_CTS_N]", /* GPIO_2, LSEC pin 3 */ - "[UART0_RTS_N]", /* GPIO_3, LSEC pin 9 */ - "[UART1_TX]", /* GPIO_4, LSEC pin 11 */ - "[UART1_RX]", /* GPIO_5, LSEC pin 13 */ - "[I2C0_SDA]", /* GPIO_8, LSEC pin 17 */ - "[I2C0_SCL]", /* GPIO_7, LSEC pin 15 */ - "[SPI1_DOUT]", /* SPI1_MOSI, HSEC pin 1 */ - "[SPI1_DIN]", /* SPI1_MISO, HSEC pin 11 */ - "[SPI1_CS]", /* SPI1_CS_N, HSEC pin 7 */ - "[SPI1_SCLK]", /* SPI1_CLK, HSEC pin 9 */ - "GPIO-B", /* LS_EXP_GPIO_B, LSEC pin 24 */ - "GPIO-C", /* LS_EXP_GPIO_C, LSEC pin 25 */ - "[I2C3_SDA]", /* HSEC pin 38 */ - "[I2C3_SCL]", /* HSEC pin 36 */ - "[SPI0_MOSI]", /* LSEC pin 14 */ - "[SPI0_MISO]", /* LSEC pin 10 */ - "[SPI0_CS_N]", /* LSEC pin 12 */ - "[SPI0_CLK]", /* LSEC pin 8 */ - "HDMI_HPD_N", /* GPIO 20 */ - "USR_LED_1_CTRL", - "[I2C1_SDA]", /* GPIO_22, LSEC pin 21 */ - "[I2C1_SCL]", /* GPIO_23, LSEC pin 19 */ - "GPIO-G", /* LS_EXP_GPIO_G, LSEC pin 29 */ - "GPIO-H", /* LS_EXP_GPIO_H, LSEC pin 30 */ - "[CSI0_MCLK]", /* HSEC pin 15 */ - "[CSI1_MCLK]", /* HSEC pin 17 */ - "GPIO-K", /* LS_EXP_GPIO_K, LSEC pin 33 */ - "[I2C2_SDA]", /* HSEC pin 34 */ - "[I2C2_SCL]", /* HSEC pin 32 */ - "DSI2HDMI_INT_N", - "DSI_SW_SEL_APQ", - "GPIO-L", /* LS_EXP_GPIO_L, LSEC pin 34 */ - "GPIO-J", /* LS_EXP_GPIO_J, LSEC pin 32 */ - "GPIO-I", /* LS_EXP_GPIO_I, LSEC pin 31 */ - "GPIO-A", /* LS_EXP_GPIO_A, LSEC pin 23 */ - "FORCED_USB_BOOT", - "SD_CARD_DET_N", - "[WCSS_BT_SSBI]", - "[WCSS_WLAN_DATA_2]", /* GPIO 40 */ - "[WCSS_WLAN_DATA_1]", - "[WCSS_WLAN_DATA_0]", - "[WCSS_WLAN_SET]", - "[WCSS_WLAN_CLK]", - "[WCSS_FM_SSBI]", - "[WCSS_FM_SDI]", - "[WCSS_BT_DAT_CTL]", - "[WCSS_BT_DAT_STB]", - "NC", - "NC", /* GPIO 50 */ - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", /* GPIO 60 */ - "NC", - "NC", - "[CDC_PDM0_CLK]", - "[CDC_PDM0_SYNC]", - "[CDC_PDM0_TX0]", - "[CDC_PDM0_RX0]", - "[CDC_PDM0_RX1]", - "[CDC_PDM0_RX2]", - "GPIO-D", /* LS_EXP_GPIO_D, LSEC pin 26 */ - "NC", /* GPIO 70 */ - "NC", - "NC", - "NC", - "NC", /* GPIO 74 */ - "NC", - "NC", - "NC", - "NC", - "NC", - "BOOT_CONFIG_0", /* GPIO 80 */ - "BOOT_CONFIG_1", - "BOOT_CONFIG_2", - "BOOT_CONFIG_3", - "NC", - "NC", - "BOOT_CONFIG_5", - "NC", - "NC", - "NC", - "NC", /* GPIO 90 */ - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", /* GPIO 100 */ - "NC", - "NC", - "NC", - "SSBI_GPS", - "NC", - "NC", - "KEY_VOLP_N", - "NC", - "NC", - "[LS_EXP_MI2S_WS]", /* GPIO 110 */ - "NC", - "NC", - "[LS_EXP_MI2S_SCK]", - "[LS_EXP_MI2S_DATA0]", - "GPIO-E", /* LS_EXP_GPIO_E, LSEC pin 27 */ - "NC", - "[DSI2HDMI_MI2S_WS]", - "[DSI2HDMI_MI2S_SCK]", - "[DSI2HDMI_MI2S_DATA0]", - "USR_LED_2_CTRL", /* GPIO 120 */ - "SB_HS_ID"; - - msmgpio_leds: msmgpio-leds { - pins = "gpio21", "gpio120"; - function = "gpio"; - - output-low; - }; - - usb_id_default: usb-id-default { - pins = "gpio121"; - function = "gpio"; - - drive-strength = <8>; - input-enable; - bias-pull-up; - }; - - adv7533_int_active: adv533-int-active { - pins = "gpio31"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - }; - - adv7533_int_suspend: adv7533-int-suspend { - pins = "gpio31"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - adv7533_switch_active: adv7533-switch-active { - pins = "gpio32"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - }; - - adv7533_switch_suspend: adv7533-switch-suspend { - pins = "gpio32"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - msm_key_volp_n_default: msm-key-volp-n-default { - pins = "gpio107"; - function = "gpio"; - - drive-strength = <8>; - input-enable; - bias-pull-up; - }; -}; - -&pm8916_gpios { - gpio-line-names = - "USR_LED_3_CTRL", - "USR_LED_4_CTRL", - "USB_HUB_RESET_N_PM", - "USB_SW_SEL_PM"; - - usb_hub_reset_pm: usb-hub-reset-pm { - pins = "gpio3"; - function = PMIC_GPIO_FUNC_NORMAL; - - input-disable; - output-high; - }; - - usb_hub_reset_pm_device: usb-hub-reset-pm-device { - pins = "gpio3"; - function = PMIC_GPIO_FUNC_NORMAL; - - output-low; - }; - - usb_sw_sel_pm: usb-sw-sel-pm { - pins = "gpio4"; - function = PMIC_GPIO_FUNC_NORMAL; - - power-source = ; - input-disable; - output-high; - }; - - usb_sw_sel_pm_device: usb-sw-sel-pm-device { - pins = "gpio4"; - function = PMIC_GPIO_FUNC_NORMAL; - - power-source = ; - input-disable; - output-low; - }; - - pm8916_gpios_leds: pm8916-gpios-leds { - pins = "gpio1", "gpio2"; - function = PMIC_GPIO_FUNC_NORMAL; - - output-low; - }; -}; - -&pm8916_mpps { - gpio-line-names = - "VDD_PX_BIAS", - "WLAN_LED_CTRL", - "BT_LED_CTRL", - "GPIO-F"; /* LS_EXP_GPIO_F, LSEC pin 28 */ - - pinctrl-names = "default"; - pinctrl-0 = <&ls_exp_gpio_f>; - - ls_exp_gpio_f: pm8916-mpp4 { - pins = "mpp4"; - function = "digital"; - - output-low; - power-source = ; // 1.8V - }; - - pm8916_mpps_leds: pm8916-mpps-leds { - pins = "mpp2", "mpp3"; - function = "digital"; - - output-low; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts deleted file mode 100644 index 757afa274..000000000 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include "apq8096-db820c.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. DB820c"; - compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096"; -}; diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi deleted file mode 100644 index defcbd15e..000000000 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ /dev/null @@ -1,1102 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. - */ - -#include "msm8996.dtsi" -#include "pm8994.dtsi" -#include "pmi8994.dtsi" -#include -#include -#include -#include -#include - -/* - * GPIO name legend: proper name = the GPIO line is used as GPIO - * NC = not connected (pin out but not routed from the chip to - * anything the board) - * "[PER]" = pin is muxed for [peripheral] (not GPIO) - * LSEC = Low Speed External Connector - * P HSEC = Primary High Speed External Connector - * S HSEC = Secondary High Speed External Connector - * J14 = Camera Connector - * TP = Test Points - * - * Line names are taken from the schematic "DragonBoard 820c", - * drawing no: LM25-P2751-1 - * - * For the lines routed to the external connectors the - * lines are named after the 96Boards CE Specification 1.0, - * Appendix "Expansion Connector Signal Description". - * - * When the 96Board naming of a line and the schematic name of - * the same line are in conflict, the 96Board specification - * takes precedence, which means that the external UART on the - * LSEC is named UART0 while the schematic and SoC names this - * UART3. This is only for the informational lines i.e. "[FOO]", - * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only - * ones actually used for GPIO. - */ - -/ { - aliases { - serial0 = &blsp2_uart1; - serial1 = &blsp2_uart2; - serial2 = &blsp1_uart1; - i2c0 = &blsp1_i2c2; - i2c1 = &blsp2_i2c1; - i2c2 = &blsp2_i2c0; - spi0 = &blsp1_spi0; - spi1 = &blsp2_spi5; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - clocks { - compatible = "simple-bus"; - divclk4: divclk4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "divclk4"; - - pinctrl-names = "default"; - pinctrl-0 = <&divclk4_pin_a>; - }; - - div1_mclk: divclk1 { - compatible = "gpio-gate-clock"; - pinctrl-0 = <&audio_mclk>; - pinctrl-names = "default"; - clocks = <&rpmcc RPM_SMD_DIV_CLK1>; - #clock-cells = <0>; - enable-gpios = <&pm8994_gpios 15 0>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&volume_up_gpio>; - - button@0 { - label = "Volume Up"; - linux,code = ; - gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; - }; - }; - - usb2_id: usb2-id { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_vbus_det_gpio>; - }; - - usb3_id: usb3-id { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb3_vbus_det_gpio>; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-always-on; - regulator-boot-on; - - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - - wlan_en: wlan-en-1-8v { - pinctrl-names = "default"; - pinctrl-0 = <&wlan_en_gpios>; - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&pm8994_gpios 8 0>; - - /* WLAN card specific delay */ - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&blsp1_i2c2 { - /* On Low speed expansion */ - label = "LS-I2C0"; - status = "okay"; -}; - -&blsp1_spi0 { - /* On Low speed expansion */ - label = "LS-SPI0"; - status = "okay"; -}; - -&blsp1_uart1 { - label = "BT-UART"; - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart1_default>; - pinctrl-1 = <&blsp1_uart1_sleep>; - - bluetooth { - compatible = "qcom,qca6174-bt"; - - /* bt_disable_n gpio */ - enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>; - - clocks = <&divclk4>; - }; -}; - -&blsp2_i2c0 { - /* On High speed expansion */ - label = "HS-I2C2"; - status = "okay"; -}; - -&blsp2_i2c1 { - /* On Low speed expansion */ - label = "LS-I2C1"; - status = "okay"; -}; - -&blsp2_spi5 { - /* On High speed expansion */ - label = "HS-SPI1"; - status = "okay"; -}; - -&blsp2_uart1 { - label = "LS-UART1"; - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart1_2pins_default>; - pinctrl-1 = <&blsp2_uart1_2pins_sleep>; -}; - -&blsp2_uart2 { - label = "LS-UART0"; - status = "disabled"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart2_4pins_default>; - pinctrl-1 = <&blsp2_uart2_4pins_sleep>; -}; - -&camss { - vdda-supply = <&vreg_l2a_1p25>; -}; - -&hdmi { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>; - pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>; - - core-vdda-supply = <&vreg_l12a_1p8>; - core-vcc-supply = <&vreg_s4a_1p8>; -}; - -&hdmi_phy { - status = "okay"; - - vddio-supply = <&vreg_l12a_1p8>; - vcca-supply = <&vreg_l28a_0p925>; - #phy-cells = <0>; -}; - -&hsusb_phy1 { - status = "okay"; - - vdda-pll-supply = <&vreg_l12a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; -}; - -&hsusb_phy2 { - status = "okay"; - - vdda-pll-supply = <&vreg_l12a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; -}; - -&mdp { - status = "okay"; -}; - -&mdss { - status = "okay"; -}; - -&mmcc { - vdd-gfx-supply = <&vdd_gfx>; -}; - -&msmgpio { - gpio-line-names = - "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */ - "[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */ - "[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC pin 12 */ - "[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC pin 8 */ - "[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC pin 11 */ - "[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC pin 13 */ - "[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC pin 21 */ - "[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC pin 19 */ - "GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 */ - "TP93", /* GPIO_9 */ - "GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 */ - "[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */ - "NC", /* GPIO_12 */ - "[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC pin 15 */ - "[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */ - "[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC pin 17 */ - "TP99", /* GPIO_16 */ - "[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC pin 34 */ - "[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC pin 32 */ - "[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */ - "[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */ - "FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */ - "FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */ - "GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */ - "GPIO-D", /* GPIO_24, LSEC pin 26 */ - "GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */ - "GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 32 */ - "BLSP6_I2C_SDA", /* GPIO_27 */ - "BLSP6_I2C_SCL", /* GPIO_28 */ - "GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 */ - "GPIO30", /* GPIO_30, S HSEC pin 4 */ - "HDMI_CEC", /* GPIO_31 */ - "HDMI_DDC_CLOCK", /* GPIO_32 */ - "HDMI_DDC_DATA", /* GPIO_33 */ - "HDMI_HOT_PLUG_DETECT", /* GPIO_34 */ - "PCIE0_RST_N", /* GPIO_35 */ - "PCIE0_CLKREQ_N", /* GPIO_36 */ - "PCIE0_WAKE", /* GPIO_37 */ - "SD_CARD_DET_N", /* GPIO_38 */ - "TSIF1_SYNC", /* GPIO_39, S HSEC pin 48 */ - "W_DISABLE_N", /* GPIO_40 */ - "[BLSP9_UART_TX]", /* GPIO_41 */ - "[BLSP9_UART_RX]", /* GPIO_42 */ - "[BLSP2_UART_CTS_N]", /* GPIO_43 */ - "[BLSP2_UART_RFR_N]", /* GPIO_44 */ - "[BLSP3_UART_TX]", /* GPIO_45 */ - "[BLSP3_UART_RX]", /* GPIO_46 */ - "[I2C0_SDA]", /* GPIO_47, LS_I2C0_SDA, LSEC pin 17 */ - "[I2C0_SCL]", /* GPIO_48, LS_I2C0_SCL, LSEC pin 15 */ - "[UART0_TxD]", /* GPIO_49, BLSP9_UART_TX, LSEC pin 5 */ - "[UART0_RxD]", /* GPIO_50, BLSP9_UART_RX, LSEC pin 7 */ - "[UART0_CTS]", /* GPIO_51, BLSP9_UART_CTS_N, LSEC pin 3 */ - "[UART0_RTS]", /* GPIO_52, BLSP9_UART_RFR_N, LSEC pin 9 */ - "[CODEC_INT1_N]", /* GPIO_53 */ - "[CODEC_INT2_N]", /* GPIO_54 */ - "[BLSP7_I2C_SDA]", /* GPIO_55 */ - "[BLSP7_I2C_SCL]", /* GPIO_56 */ - "MI2S_MCLK", /* GPIO_57, S HSEC pin 3 */ - "[PCM_CLK]", /* GPIO_58, QUA_MI2S_SCK, LSEC pin 18 */ - "[PCM_FS]", /* GPIO_59, QUA_MI2S_WS, LSEC pin 16 */ - "[PCM_DO]", /* GPIO_60, QUA_MI2S_DATA0, LSEC pin 20 */ - "[PCM_DI]", /* GPIO_61, QUA_MI2S_DATA1, LSEC pin 22 */ - "GPIO-E", /* GPIO_62, LSEC pin 27 */ - "TP87", /* GPIO_63 */ - "[CODEC_RST_N]", /* GPIO_64 */ - "[PCM1_CLK]", /* GPIO_65 */ - "[PCM1_SYNC]", /* GPIO_66 */ - "[PCM1_DIN]", /* GPIO_67 */ - "[PCM1_DOUT]", /* GPIO_68 */ - "AUDIO_REF_CLK", /* GPIO_69 */ - "SLIMBUS_CLK", /* GPIO_70 */ - "SLIMBUS_DATA0", /* GPIO_71 */ - "SLIMBUS_DATA1", /* GPIO_72 */ - "NC", /* GPIO_73 */ - "NC", /* GPIO_74 */ - "NC", /* GPIO_75 */ - "NC", /* GPIO_76 */ - "TP94", /* GPIO_77 */ - "NC", /* GPIO_78 */ - "TP95", /* GPIO_79 */ - "GPIO-A", /* GPIO_80, MEMS_RESET_N, LSEC pin 23 */ - "TP88", /* GPIO_81 */ - "TP89", /* GPIO_82 */ - "TP90", /* GPIO_83 */ - "TP91", /* GPIO_84 */ - "[SD_DAT0]", /* GPIO_85, BLSP12_SPI_MOSI, P HSEC pin 1 */ - "[SD_CMD]", /* GPIO_86, BLSP12_SPI_MISO, P HSEC pin 11 */ - "[SD_DAT3]", /* GPIO_87, BLSP12_SPI_CS_N, P HSEC pin 7 */ - "[SD_SCLK]", /* GPIO_88, BLSP12_SPI_CLK, P HSEC pin 9 */ - "TSIF1_CLK", /* GPIO_89, S HSEC pin 42 */ - "TSIF1_EN", /* GPIO_90, S HSEC pin 46 */ - "TSIF1_DATA", /* GPIO_91, S HSEC pin 44 */ - "NC", /* GPIO_92 */ - "TSIF2_CLK", /* GPIO_93, S HSEC pin 52 */ - "TSIF2_EN", /* GPIO_94, S HSEC pin 56 */ - "TSIF2_DATA", /* GPIO_95, S HSEC pin 54 */ - "TSIF2_SYNC", /* GPIO_96, S HSEC pin 58 */ - "NC", /* GPIO_97 */ - "CAM1_STANDBY_N", /* GPIO_98 */ - "NC", /* GPIO_99 */ - "NC", /* GPIO_100 */ - "[LCD1_RESET_N]", /* GPIO_101, S HSEC pin 51 */ - "BOOT_CONFIG1", /* GPIO_102 */ - "USB_HUB_RESET", /* GPIO_103 */ - "CAM1_RST_N", /* GPIO_104 */ - "NC", /* GPIO_105 */ - "NC", /* GPIO_106 */ - "NC", /* GPIO_107 */ - "NC", /* GPIO_108 */ - "NC", /* GPIO_109 */ - "NC", /* GPIO_110 */ - "NC", /* GPIO_111 */ - "NC", /* GPIO_112 */ - "PMI8994_BUA", /* GPIO_113 */ - "PCIE2_RST_N", /* GPIO_114 */ - "PCIE2_CLKREQ_N", /* GPIO_115 */ - "PCIE2_WAKE", /* GPIO_116 */ - "SSC_IRQ_0", /* GPIO_117 */ - "SSC_IRQ_1", /* GPIO_118 */ - "SSC_IRQ_2", /* GPIO_119 */ - "NC", /* GPIO_120 */ - "GPIO121", /* GPIO_121, S HSEC pin 2 */ - "NC", /* GPIO_122 */ - "SSC_IRQ_6", /* GPIO_123 */ - "SSC_IRQ_7", /* GPIO_124 */ - "GPIO-C", /* GPIO_125, TS_INT0, LSEC pin 25 */ - "BOOT_CONFIG5", /* GPIO_126 */ - "NC", /* GPIO_127 */ - "NC", /* GPIO_128 */ - "BOOT_CONFIG7", /* GPIO_129 */ - "PCIE1_RST_N", /* GPIO_130 */ - "PCIE1_CLKREQ_N", /* GPIO_131 */ - "PCIE1_WAKE", /* GPIO_132 */ - "GPIO-L", /* GPIO_133, CAM2_STANDBY_N, LSEC pin 34 */ - "NC", /* GPIO_134 */ - "NC", /* GPIO_135 */ - "BOOT_CONFIG8", /* GPIO_136 */ - "NC", /* GPIO_137 */ - "NC", /* GPIO_138 */ - "GPS_SSBI2", /* GPIO_139 */ - "GPS_SSBI1", /* GPIO_140 */ - "NC", /* GPIO_141 */ - "NC", /* GPIO_142 */ - "NC", /* GPIO_143 */ - "BOOT_CONFIG6", /* GPIO_144 */ - "NC", /* GPIO_145 */ - "NC", /* GPIO_146 */ - "NC", /* GPIO_147 */ - "NC", /* GPIO_148 */ - "NC"; /* GPIO_149 */ - - sdc2_cd_on: sdc2_cd_on { - mux { - pins = "gpio38"; - function = "gpio"; - }; - - config { - pins = "gpio38"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_cd_off: sdc2_cd_off { - mux { - pins = "gpio38"; - function = "gpio"; - }; - - config { - pins = "gpio38"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - blsp1_uart1_default: blsp1_uart1_default { - mux { - pins = "gpio41", "gpio42", "gpio43", "gpio44"; - function = "blsp_uart2"; - }; - - config { - pins = "gpio41", "gpio42", "gpio43", "gpio44"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp1_uart1_sleep: blsp1_uart1_sleep { - mux { - pins = "gpio41", "gpio42", "gpio43", "gpio44"; - function = "gpio"; - }; - - config { - pins = "gpio41", "gpio42", "gpio43", "gpio44"; - drive-strength = <2>; - bias-disable; - }; - }; - - hdmi_hpd_active: hdmi_hpd_active { - mux { - pins = "gpio34"; - function = "hdmi_hot"; - }; - - config { - pins = "gpio34"; - bias-pull-down; - drive-strength = <16>; - }; - }; - - hdmi_hpd_suspend: hdmi_hpd_suspend { - mux { - pins = "gpio34"; - function = "hdmi_hot"; - }; - - config { - pins = "gpio34"; - bias-pull-down; - drive-strength = <2>; - }; - }; - - hdmi_ddc_active: hdmi_ddc_active { - mux { - pins = "gpio32", "gpio33"; - function = "hdmi_ddc"; - }; - - config { - pins = "gpio32", "gpio33"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - hdmi_ddc_suspend: hdmi_ddc_suspend { - mux { - pins = "gpio32", "gpio33"; - function = "hdmi_ddc"; - }; - - config { - pins = "gpio32", "gpio33"; - drive-strength = <2>; - bias-pull-down; - }; - }; -}; - -&pcie0 { - status = "okay"; - perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&wlan_en>; - vdda-supply = <&vreg_l28a_0p925>; -}; - -&pcie1 { - status = "okay"; - perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>; - vdda-supply = <&vreg_l28a_0p925>; -}; - -&pcie2 { - status = "okay"; - perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>; - vdda-supply = <&vreg_l28a_0p925>; -}; - -&pcie_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l28a_0p925>; - vdda-pll-supply = <&vreg_l12a_1p8>; -}; - -&pm8994_gpios { - gpio-line-names = - "NC", - "KEY_VOLP_N", - "NC", - "BL1_PWM", - "GPIO-F", /* BL0_PWM, LSEC pin 28 */ - "BL1_EN", - "NC", - "WLAN_EN", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "DIVCLK1", - "DIVCLK2", - "DIVCLK3", - "DIVCLK4", - "BT_EN", - "PMIC_SLB", - "PMIC_BUA", - "USB_VBUS_DET"; - - pinctrl-names = "default"; - pinctrl-0 = <&ls_exp_gpio_f &bt_en_gpios>; - - ls_exp_gpio_f: pm8994_gpio5 { - pinconf { - pins = "gpio5"; - output-low; - power-source = <2>; // PM8994_GPIO_S4, 1.8V - }; - }; - - bt_en_gpios: bt_en_gpios { - pinconf { - pins = "gpio19"; - function = PMIC_GPIO_FUNC_NORMAL; - output-low; - power-source = ; // 1.8V - qcom,drive-strength = ; - bias-pull-down; - }; - }; - - wlan_en_gpios: wlan_en_gpios { - pinconf { - pins = "gpio8"; - function = PMIC_GPIO_FUNC_NORMAL; - output-low; - power-source = ; // 1.8V - qcom,drive-strength = ; - bias-pull-down; - }; - }; - - audio_mclk: clk_div1 { - pinconf { - pins = "gpio15"; - function = "func1"; - power-source = ; // 1.8V - }; - }; - - volume_up_gpio: pm8996_gpio2 { - pinconf { - pins = "gpio2"; - function = "normal"; - input-enable; - drive-push-pull; - bias-pull-up; - qcom,drive-strength = ; - power-source = ; // 1.8V - }; - }; - - divclk4_pin_a: divclk4 { - pinconf { - pins = "gpio18"; - function = PMIC_GPIO_FUNC_FUNC2; - - bias-disable; - power-source = ; - }; - }; - - usb3_vbus_det_gpio: pm8996_gpio22 { - pinconf { - pins = "gpio22"; - function = PMIC_GPIO_FUNC_NORMAL; - input-enable; - bias-pull-down; - qcom,drive-strength = ; - power-source = ; // 1.8V - }; - }; -}; - -&pm8994_mpps { - gpio-line-names = - "VDDPX_BIAS", - "WIFI_LED", - "NC", - "BT_LED", - "PM_MPP05", - "PM_MPP06", - "PM_MPP07", - "NC"; -}; - -&pm8994_spmi_regulators { - qcom,saw-reg = <&saw3>; - s9 { - qcom,saw-slave; - }; - s10 { - qcom,saw-slave; - }; - s11 { - qcom,saw-leader; - regulator-always-on; - regulator-min-microvolt = <980000>; - regulator-max-microvolt = <980000>; - }; -}; - -&pmi8994_gpios { - gpio-line-names = - "NC", - "SPKR_AMP_EN1", - "SPKR_AMP_EN2", - "TP61", - "NC", - "USB2_VBUS_DET", - "NC", - "NC", - "NC", - "NC"; - - usb2_vbus_det_gpio: pmi8996_gpio6 { - pinconf { - pins = "gpio6"; - function = PMIC_GPIO_FUNC_NORMAL; - input-enable; - bias-pull-down; - qcom,drive-strength = ; - power-source = ; // 1.8V - }; - }; -}; - -&pmi8994_spmi_regulators { - vdd_gfx: s2@1700 { - reg = <0x1700 0x100>; - regulator-name = "VDD_GFX"; - regulator-min-microvolt = <980000>; - regulator-max-microvolt = <980000>; - }; -}; - -&rpm_requests { - pm8994-regulators { - compatible = "qcom,rpm-pm8994-regulators"; - - vdd_s1-supply = <&vph_pwr>; - vdd_s2-supply = <&vph_pwr>; - vdd_s3-supply = <&vph_pwr>; - vdd_s4-supply = <&vph_pwr>; - vdd_s5-supply = <&vph_pwr>; - vdd_s6-supply = <&vph_pwr>; - vdd_s7-supply = <&vph_pwr>; - vdd_s8-supply = <&vph_pwr>; - vdd_s9-supply = <&vph_pwr>; - vdd_s10-supply = <&vph_pwr>; - vdd_s11-supply = <&vph_pwr>; - vdd_s12-supply = <&vph_pwr>; - vdd_l1-supply = <&vreg_s1b_1p025>; - vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>; - vdd_l3_l11-supply = <&vreg_s3a_1p3>; - vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>; - vdd_l5_l7-supply = <&vreg_s5a_2p15>; - vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>; - vdd_l8_l16_l30-supply = <&vph_pwr>; - vdd_l9_l10_l18_l22-supply = <&vph_pwr_bbyp>; - vdd_l13_l19_l23_l24-supply = <&vph_pwr_bbyp>; - vdd_l14_l15-supply = <&vreg_s5a_2p15>; - vdd_l17_l29-supply = <&vph_pwr_bbyp>; - vdd_l20_l21-supply = <&vph_pwr_bbyp>; - vdd_l25-supply = <&vreg_s3a_1p3>; - vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; - - vreg_s3a_1p3: s3 { - regulator-name = "vreg_s3a_1p3"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - /** - * 1.8v required on LS expansion - * for mezzanine boards - */ - vreg_s4a_1p8: s4 { - regulator-name = "vreg_s4a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - vreg_s5a_2p15: s5 { - regulator-name = "vreg_s5a_2p15"; - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - }; - vreg_s7a_1p0: s7 { - regulator-name = "vreg_s7a_1p0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - }; - - vreg_l1a_1p0: l1 { - regulator-name = "vreg_l1a_1p0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l2a_1p25: l2 { - regulator-name = "vreg_l2a_1p25"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - }; - vreg_l3a_0p875: l3 { - regulator-name = "vreg_l3a_0p875"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - }; - vreg_l4a_1p225: l4 { - regulator-name = "vreg_l4a_1p225"; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - vreg_l6a_1p2: l6 { - regulator-name = "vreg_l6a_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - vreg_l8a_1p8: l8 { - regulator-name = "vreg_l8a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l9a_1p8: l9 { - regulator-name = "vreg_l9a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l10a_1p8: l10 { - regulator-name = "vreg_l10a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l11a_1p15: l11 { - regulator-name = "vreg_l11a_1p15"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - }; - vreg_l12a_1p8: l12 { - regulator-name = "vreg_l12a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l13a_2p95: l13 { - regulator-name = "vreg_l13a_2p95"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - vreg_l14a_1p8: l14 { - regulator-name = "vreg_l14a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l15a_1p8: l15 { - regulator-name = "vreg_l15a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l16a_2p7: l16 { - regulator-name = "vreg_l16a_2p7"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - vreg_l17a_2p8: l17 { - regulator-name = "vreg_l17a_2p8"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - vreg_l18a_2p85: l18 { - regulator-name = "vreg_l18a_2p85"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2900000>; - }; - vreg_l19a_2p8: l19 { - regulator-name = "vreg_l19a_2p8"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - vreg_l20a_2p95: l20 { - regulator-name = "vreg_l20a_2p95"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - }; - vreg_l21a_2p95: l21 { - regulator-name = "vreg_l21a_2p95"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - vreg_l22a_3p0: l22 { - regulator-name = "vreg_l22a_3p0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - vreg_l23a_2p8: l23 { - regulator-name = "vreg_l23a_2p8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - vreg_l24a_3p075: l24 { - regulator-name = "vreg_l24a_3p075"; - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - vreg_l25a_1p2: l25 { - regulator-name = "vreg_l25a_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-allow-set-load; - }; - vreg_l26a_0p8: l27 { - regulator-name = "vreg_l26a_0p8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l28a_0p925: l28 { - regulator-name = "vreg_l28a_0p925"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <925000>; - regulator-allow-set-load; - }; - vreg_l29a_2p8: l29 { - regulator-name = "vreg_l29a_2p8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - vreg_l30a_1p8: l30 { - regulator-name = "vreg_l30a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l32a_1p8: l32 { - regulator-name = "vreg_l32a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vreg_lvs1a_1p8: lvs1 { - regulator-name = "vreg_lvs1a_1p8"; - }; - - vreg_lvs2a_1p8: lvs2 { - regulator-name = "vreg_lvs2a_1p8"; - }; - }; - - pmi8994-regulators { - compatible = "qcom,rpm-pmi8994-regulators"; - - vdd_s1-supply = <&vph_pwr>; - vdd_s2-supply = <&vph_pwr>; - vdd_s3-supply = <&vph_pwr>; - vdd_bst_byp-supply = <&vph_pwr>; - - vph_pwr_bbyp: boost-bypass { - regulator-name = "vph_pwr_bbyp"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vreg_s1b_1p025: s1 { - regulator-name = "vreg_s1b_1p025"; - regulator-min-microvolt = <1025000>; - regulator-max-microvolt = <1025000>; - }; - }; -}; - -&sdhc2 { - /* External SD card */ - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - cd-gpios = <&msmgpio 38 0x1>; - vmmc-supply = <&vreg_l21a_2p95>; - vqmmc-supply = <&vreg_l13a_2p95>; - status = "okay"; -}; - -&q6asmdai { - dai@0 { - reg = <0>; - }; - - dai@1 { - reg = <1>; - }; - - dai@2 { - reg = <2>; - }; -}; - -&sound { - compatible = "qcom,apq8096-sndcard"; - model = "DB820c"; - audio-routing = "RX_BIAS", "MCLK", - "MM_DL1", "MultiMedia1 Playback", - "MM_DL2", "MultiMedia2 Playback", - "MultiMedia3 Capture", "MM_UL3"; - - mm1-dai-link { - link-name = "MultiMedia1"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; - }; - }; - - mm2-dai-link { - link-name = "MultiMedia2"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; - }; - }; - - mm3-dai-link { - link-name = "MultiMedia3"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; - }; - }; - - hdmi-dai-link { - link-name = "HDMI"; - cpu { - sound-dai = <&q6afedai HDMI_RX>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&hdmi 0>; - }; - }; - - slim-dai-link { - link-name = "SLIM Playback"; - cpu { - sound-dai = <&q6afedai SLIMBUS_6_RX>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&wcd9335 6>; - }; - }; - - slimcap-dai-link { - link-name = "SLIM Capture"; - cpu { - sound-dai = <&q6afedai SLIMBUS_0_TX>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&wcd9335 1>; - }; - }; -}; - -&spmi_bus { - pmic@0 { - pon@800 { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; - }; - }; -}; - -&ufsphy { - status = "okay"; - - vdda-phy-supply = <&vreg_l28a_0p925>; - vdda-pll-supply = <&vreg_l12a_1p8>; - vddp-ref-clk-supply = <&vreg_l25a_1p2>; -}; - -&ufshc { - status = "okay"; - - vcc-supply = <&vreg_l20a_2p95>; - vccq-supply = <&vreg_l25a_1p2>; - vccq2-supply = <&vreg_s4a_1p8>; - - vcc-max-microamp = <600000>; - vccq-max-microamp = <450000>; - vccq2-max-microamp = <450000>; -}; - -&usb2 { - status = "okay"; - extcon = <&usb2_id>; - - dwc3@7600000 { - extcon = <&usb2_id>; - dr_mode = "otg"; - maximum-speed = "high-speed"; - }; -}; - -&usb3 { - status = "okay"; - extcon = <&usb3_id>; - - dwc3@6a00000 { - extcon = <&usb3_id>; - dr_mode = "otg"; - }; -}; - -&usb3phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l28a_0p925>; - vdda-pll-supply = <&vreg_l12a_1p8>; - -}; - -&wcd9335 { - clock-names = "mclk", "slimbus"; - clocks = <&div1_mclk>, - <&rpmcc RPM_SMD_BB_CLK1>; - - vdd-buck-supply = <&vreg_s4a_1p8>; - vdd-buck-sido-supply = <&vreg_s4a_1p8>; - vdd-tx-supply = <&vreg_s4a_1p8>; - vdd-rx-supply = <&vreg_s4a_1p8>; - vdd-io-supply = <&vreg_s4a_1p8>; -}; diff --git a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts deleted file mode 100644 index f6ddf17ad..000000000 --- a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts +++ /dev/null @@ -1,385 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause - -/dts-v1/; - -#include "msm8996.dtsi" -#include "pm8994.dtsi" -#include "pmi8994.dtsi" -#include -#include -#include - -/ { - model = "Inforce 6640 Single Board Computer"; - compatible = "inforce,ifc6640", "qcom,apq8096-sbc", "qcom,apq8096"; - - qcom,msm-id = <291 0x00030001>; - qcom,board-id = <0x00010018 0>; - - aliases { - serial0 = &blsp2_uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - v1p05: v1p05-regulator { - compatible = "regulator-fixed"; - reglator-name = "v1p05"; - regulator-always-on; - regulator-boot-on; - - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - - vin-supply = <&v5p0>; - }; - - v12_poe: v12-poe-regulator { - compatible = "regulator-fixed"; - reglator-name = "v12_poe"; - regulator-always-on; - regulator-boot-on; - - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - v3p3: v3p3-regulator { - compatible = "regulator-fixed"; - regulator-name = "v3p3"; - regulator-always-on; - regulator-boot-on; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - vin-supply = <&v12_poe>; - }; - - v5p0: v5p0-regulator { - compatible = "regulator-fixed"; - regulator-name = "v5p0"; - regulator-always-on; - regulator-boot-on; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - vin-supply = <&v12_poe>; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-always-on; - regulator-boot-on; - - regulator-min-microvolt = <3800000>; - regulator-max-microvolt = <3800000>; - }; -}; - -&blsp2_uart1 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart1_2pins_default>; - pinctrl-1 = <&blsp2_uart1_2pins_sleep>; -}; - -&msmgpio { - sdc2_pins_default: sdc2-pins-default { - clk { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <16>; - }; - - cmd { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - data { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <10>; - }; - - cd { - pins = "gpio38"; - function = "gpio"; - - bias-pull-up; - drive-strength = <16>; - }; - }; - - sdc2_pins_sleep: sdc2-pins-sleep { - clk { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <2>; - }; - - cmd { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - data { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <2>; - }; - - cd { - pins = "gpio38"; - function = "gpio"; - bias-pull-up; - drive-strength = <2>; - }; - }; -}; - -&rpm_requests { - pm8994-regulators { - compatible = "qcom,rpm-pm8994-regulators"; - - vdd_s1-supply = <&vph_pwr>; - vdd_s2-supply = <&vph_pwr>; - vdd_s3-supply = <&vph_pwr>; - vdd_s4-supply = <&vph_pwr>; - vdd_s5-supply = <&vph_pwr>; - vdd_s6-supply = <&vph_pwr>; - vdd_s7-supply = <&vph_pwr>; - vdd_s8-supply = <&vph_pwr>; - vdd_s9-supply = <&vph_pwr>; - vdd_s10-supply = <&vph_pwr>; - vdd_s11-supply = <&vph_pwr>; - vdd_s12-supply = <&vph_pwr>; - vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>; - vdd_l3_l11-supply = <&vreg_s3a_1p3>; - vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>; - vdd_l5_l7-supply = <&vreg_s5a_2p15>; - vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>; - vdd_l8_l16_l30-supply = <&vph_pwr>; - vdd_l25-supply = <&vreg_s3a_1p3>; - vdd_lvs1_2-supply = <&vreg_s4a_1p8>; - - vreg_s3a_1p3: s3 { - regulator-name = "vreg_s3a_1p3"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - vreg_s4a_1p8: s4 { - regulator-name = "vreg_s4a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - vreg_s5a_2p15: s5 { - regulator-name = "vreg_s5a_2p15"; - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - }; - vreg_s7a_1p0: s7 { - regulator-name = "vreg_s7a_1p0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - }; - - vreg_l1a_1p0: l1 { - regulator-name = "vreg_l1a_1p0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l2a_1p25: l2 { - regulator-name = "vreg_l2a_1p25"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - }; - vreg_l3a_0p875: l3 { - regulator-name = "vreg_l3a_0p875"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - }; - vreg_l4a_1p225: l4 { - regulator-name = "vreg_l4a_1p225"; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - vreg_l6a_1p2: l6 { - regulator-name = "vreg_l6a_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - vreg_l8a_1p8: l8 { - regulator-name = "vreg_l8a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l9a_1p8: l9 { - regulator-name = "vreg_l9a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l10a_1p8: l10 { - regulator-name = "vreg_l10a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l11a_1p15: l11 { - regulator-name = "vreg_l11a_1p15"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - }; - vreg_l12a_1p8: l12 { - regulator-name = "vreg_l12a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l13a_2p95: l13 { - regulator-name = "vreg_l13a_2p95"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - vreg_l14a_1p8: l14 { - regulator-name = "vreg_l14a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l15a_1p8: l15 { - regulator-name = "vreg_l15a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l16a_2p7: l16 { - regulator-name = "vreg_l16a_2p7"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - vreg_l17a_2p8: l17 { - regulator-name = "vreg_l17a_2p8"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - vreg_l18a_2p85: l18 { - regulator-name = "vreg_l18a_2p85"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2900000>; - }; - vreg_l19a_2p8: l19 { - regulator-name = "vreg_l19a_2p8"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - vreg_l20a_2p95: l20 { - regulator-name = "vreg_l20a_2p95"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - }; - vreg_l21a_2p95: l21 { - regulator-name = "vreg_l21a_2p95"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - }; - vreg_l22a_3p0: l22 { - regulator-name = "vreg_l22a_3p0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - vreg_l23a_2p8: l23 { - regulator-name = "vreg_l23a_2p8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - vreg_l24a_3p075: l24 { - regulator-name = "vreg_l24a_3p075"; - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - vreg_l25a_1p2: l25 { - regulator-name = "vreg_l25a_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-allow-set-load; - }; - vreg_l26a_0p8: l27 { - regulator-name = "vreg_l26a_0p8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l28a_0p925: l28 { - regulator-name = "vreg_l28a_0p925"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <925000>; - regulator-allow-set-load; - }; - vreg_l29a_2p8: l29 { - regulator-name = "vreg_l29a_2p8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - vreg_l30a_1p8: l30 { - regulator-name = "vreg_l30a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l32a_1p8: l32 { - regulator-name = "vreg_l32a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vreg_lvs1a_1p8: lvs1 { - regulator-name = "vreg_lvs1a_1p8"; - }; - - vreg_lvs2a_1p8: lvs2 { - regulator-name = "vreg_lvs2a_1p8"; - }; - }; -}; - -&sdhc2 { - status = "okay"; - - bus-width = <4>; - - cd-gpios = <&msmgpio 38 0x1>; - - vmmc-supply = <&vreg_l21a_2p95>; - vqmmc-supply = <&vreg_l13a_2p95>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_pins_default>; - pinctrl-1 = <&sdc2_pins_sleep>; -}; - -&ufshc { - status = "okay"; - - vcc-supply = <&vreg_l20a_2p95>; - vccq-supply = <&vreg_l25a_1p2>; - vccq2-supply = <&vreg_s4a_1p8>; - - vcc-max-microamp = <600000>; - vccq-max-microamp = <450000>; - vccq2-max-microamp = <450000>; -}; - -&ufsphy { - status = "okay"; - - vdda-phy-supply = <&vreg_l28a_0p925>; - vdda-pll-supply = <&vreg_l12a_1p8>; - - vdda-phy-max-microamp = <18380>; - vdda-pll-max-microamp = <9440>; -}; diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts deleted file mode 100644 index e8eaa958c..000000000 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * IPQ6018 CP01 board device tree source - * - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include "ipq6018.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1"; - compatible = "qcom,ipq6018-cp01", "qcom,ipq6018"; - - aliases { - serial0 = &blsp1_uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - bootargs-append = " swiotlb=1"; - }; -}; - -&blsp1_uart3 { - pinctrl-0 = <&serial_3_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c_1 { - pinctrl-0 = <&i2c_1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&spi_0 { - cs-select = <0>; - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - compatible = "n25q128a11"; - spi-max-frequency = <50000000>; - }; -}; - -&tlmm { - i2c_1_pins: i2c-1-pins { - pins = "gpio42", "gpio43"; - function = "blsp2_i2c"; - drive-strength = <8>; - }; - - spi_0_pins: spi-0-pins { - pins = "gpio38", "gpio39", "gpio40", "gpio41"; - function = "blsp0_spi"; - drive-strength = <8>; - bias-pull-down; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi deleted file mode 100644 index 2a1f03cdb..000000000 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ /dev/null @@ -1,533 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * IPQ6018 SoC device tree source - * - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - */ - -#include -#include -#include -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&intc>; - - clocks { - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - xo: xo { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - }; - - cpus: cpus { - #address-cells = <1>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x1>; - next-level-cache = <&L2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x2>; - next-level-cache = <&L2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x3>; - next-level-cache = <&L2_0>; - clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; - clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; - }; - - L2_0: l2-cache { - compatible = "cache"; - cache-level = <0x2>; - }; - }; - - cpu_opp_table: cpu_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - opp-864000000 { - opp-hz = /bits/ 64 <864000000>; - opp-microvolt = <725000>; - clock-latency-ns = <200000>; - }; - opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-microvolt = <787500>; - clock-latency-ns = <200000>; - }; - opp-1320000000 { - opp-hz = /bits/ 64 <1320000000>; - opp-microvolt = <862500>; - clock-latency-ns = <200000>; - }; - opp-1440000000 { - opp-hz = /bits/ 64 <1440000000>; - opp-microvolt = <925000>; - clock-latency-ns = <200000>; - }; - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <987500>; - clock-latency-ns = <200000>; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1062500>; - clock-latency-ns = <200000>; - }; - }; - - firmware { - scm { - compatible = "qcom,scm"; - }; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x80>; - #hwlock-cells = <1>; - }; - - pmuv8: pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - }; - - psci: psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rpm_msg_ram: memory@60000 { - reg = <0x0 0x60000 0x0 0x6000>; - no-map; - }; - - tz: memory@4a600000 { - reg = <0x0 0x4a600000 0x0 0x00400000>; - no-map; - }; - - smem_region: memory@4aa00000 { - reg = <0x0 0x4aa00000 0x0 0x00100000>; - no-map; - }; - - q6_region: memory@4ab00000 { - reg = <0x0 0x4ab00000 0x0 0x05500000>; - no-map; - }; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_region>; - hwlocks = <&tcsr_mutex 0>; - }; - - soc: soc { - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0 0 0 0x0 0xffffffff>; - dma-ranges; - compatible = "simple-bus"; - - prng: qrng@e1000 { - compatible = "qcom,prng-ee"; - reg = <0x0 0xe3000 0x0 0x1000>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; - - cryptobam: dma@704000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x0 0x00704000 0x0 0x20000>; - interrupts = ; - clocks = <&gcc GCC_CRYPTO_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <1>; - qcom,controlled-remotely; - qcom,config-pipe-trust-reg = <0>; - }; - - crypto: crypto@73a000 { - compatible = "qcom,crypto-v5.1"; - reg = <0x0 0x0073a000 0x0 0x6000>; - clocks = <&gcc GCC_CRYPTO_AHB_CLK>, - <&gcc GCC_CRYPTO_AXI_CLK>, - <&gcc GCC_CRYPTO_CLK>; - clock-names = "iface", "bus", "core"; - dmas = <&cryptobam 2>, <&cryptobam 3>; - dma-names = "rx", "tx"; - }; - - tlmm: pinctrl@1000000 { - compatible = "qcom,ipq6018-pinctrl"; - reg = <0x0 0x01000000 0x0 0x300000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 0 80>; - interrupt-controller; - #interrupt-cells = <2>; - - serial_3_pins: serial3-pinmux { - pins = "gpio44", "gpio45"; - function = "blsp2_uart"; - drive-strength = <8>; - bias-pull-down; - }; - }; - - gcc: gcc@1800000 { - compatible = "qcom,gcc-ipq6018"; - reg = <0x0 0x01800000 0x0 0x80000>; - clocks = <&xo>, <&sleep_clk>; - clock-names = "xo", "sleep_clk"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - tcsr_mutex_regs: syscon@1905000 { - compatible = "syscon"; - reg = <0x0 0x01905000 0x0 0x8000>; - }; - - tcsr_q6: syscon@1945000 { - compatible = "syscon"; - reg = <0x0 0x01945000 0x0 0xe000>; - }; - - blsp_dma: dma@7884000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x0 0x07884000 0x0 0x2b000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - blsp1_uart3: serial@78b1000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x0 0x078b1000 0x0 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - spi_0: spi@78b5000 { - compatible = "qcom,spi-qup-v2.2.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x078b5000 0x0 0x600>; - interrupts = ; - spi-max-frequency = <50000000>; - clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 12>, <&blsp_dma 13>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spi_1: spi@78b6000 { - compatible = "qcom,spi-qup-v2.2.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x078b6000 0x0 0x600>; - interrupts = ; - spi-max-frequency = <50000000>; - clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 14>, <&blsp_dma 15>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - i2c_0: i2c@78b6000 { - compatible = "qcom,i2c-qup-v2.2.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x078b6000 0x0 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <400000>; - dmas = <&blsp_dma 15>, <&blsp_dma 14>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */ - compatible = "qcom,i2c-qup-v2.2.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x078b7000 0x0 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <400000>; - dmas = <&blsp_dma 17>, <&blsp_dma 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - intc: interrupt-controller@b000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <0x3>; - reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ - <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ - <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ - <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ - interrupts = ; - }; - - watchdog@b017000 { - compatible = "qcom,kpss-wdt"; - interrupts = ; - reg = <0x0 0x0b017000 0x0 0x40>; - clocks = <&sleep_clk>; - timeout-sec = <10>; - }; - - apcs_glb: mailbox@b111000 { - compatible = "qcom,ipq6018-apcs-apps-global"; - reg = <0x0 0x0b111000 0x0 0x1000>; - #clock-cells = <1>; - clocks = <&a53pll>, <&xo>; - clock-names = "pll", "xo"; - #mbox-cells = <1>; - }; - - a53pll: clock@b116000 { - compatible = "qcom,ipq6018-a53pll"; - reg = <0x0 0x0b116000 0x0 0x40>; - #clock-cells = <0>; - clocks = <&xo>; - clock-names = "xo"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - timer@b120000 { - #address-cells = <2>; - #size-cells = <2>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x0b120000 0x0 0x1000>; - clock-frequency = <19200000>; - - frame@b120000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x0 0x0b121000 0x0 0x1000>, - <0x0 0x0b122000 0x0 0x1000>; - }; - - frame@b123000 { - frame-number = <1>; - interrupts = ; - reg = <0x0 0xb123000 0x0 0x1000>; - status = "disabled"; - }; - - frame@b124000 { - frame-number = <2>; - interrupts = ; - reg = <0x0 0x0b124000 0x0 0x1000>; - status = "disabled"; - }; - - frame@b125000 { - frame-number = <3>; - interrupts = ; - reg = <0x0 0x0b125000 0x0 0x1000>; - status = "disabled"; - }; - - frame@b126000 { - frame-number = <4>; - interrupts = ; - reg = <0x0 0x0b126000 0x0 0x1000>; - status = "disabled"; - }; - - frame@b127000 { - frame-number = <5>; - interrupts = ; - reg = <0x0 0x0b127000 0x0 0x1000>; - status = "disabled"; - }; - - frame@b128000 { - frame-number = <6>; - interrupts = ; - reg = <0x0 0x0b128000 0x0 0x1000>; - status = "disabled"; - }; - }; - - q6v5_wcss: remoteproc@cd00000 { - compatible = "qcom,ipq8074-wcss-pil"; - reg = <0x0 0x0cd00000 0x0 0x4040>, - <0x0 0x004ab000 0x0 0x20>; - reg-names = "qdsp6", - "rmb"; - interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, - <&wcss_smp2p_in 0 0>, - <&wcss_smp2p_in 1 0>, - <&wcss_smp2p_in 2 0>, - <&wcss_smp2p_in 3 0>; - interrupt-names = "wdog", - "fatal", - "ready", - "handover", - "stop-ack"; - - resets = <&gcc GCC_WCSSAON_RESET>, - <&gcc GCC_WCSS_BCR>, - <&gcc GCC_WCSS_Q6_BCR>; - - reset-names = "wcss_aon_reset", - "wcss_reset", - "wcss_q6_reset"; - - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "prng"; - - qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>; - - qcom,smem-states = <&wcss_smp2p_out 0>, - <&wcss_smp2p_out 1>; - qcom,smem-state-names = "shutdown", - "stop"; - - memory-region = <&q6_region>; - - glink-edge { - interrupts = ; - qcom,remote-pid = <1>; - mboxes = <&apcs_glb 8>; - - qrtr_requests { - qcom,glink-channels = "IPCRTR"; - }; - }; - }; - - }; - - wcss: wcss-smp2p { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - - interrupt-parent = <&intc>; - interrupts = ; - - mboxes = <&apcs_glb 9>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - wcss_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - wcss_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - rpm-glink { - compatible = "qcom,glink-rpm"; - interrupts = ; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: glink-channel { - compatible = "qcom,rpm-ipq6018"; - qcom,glink-channels = "rpm_requests"; - - regulators { - compatible = "qcom,rpm-mp5496-regulators"; - - ipq6018_s2: s2 { - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1062500>; - regulator-always-on; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts deleted file mode 100644 index cc08dc4eb..000000000 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/dts-v1/; -/* Copyright (c) 2017, The Linux Foundation. All rights reserved. - */ -#include "ipq8074.dtsi" - -/ { - #address-cells = <0x2>; - #size-cells = <0x2>; - model = "Qualcomm Technologies, Inc. IPQ8074-HK01"; - compatible = "qcom,ipq8074-hk01", "qcom,ipq8074"; - interrupt-parent = <&intc>; - - aliases { - serial0 = &blsp1_uart5; - serial1 = &blsp1_uart3; - }; - - chosen { - stdout-path = "serial0"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0x0 0x20000000>; - }; -}; - -&blsp1_i2c2 { - status = "okay"; -}; - -&blsp1_spi1 { - status = "okay"; - - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - }; -}; - -&blsp1_uart3 { - status = "okay"; -}; - -&blsp1_uart5 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - perst-gpio = <&tlmm 61 0x1>; -}; - -&pcie1 { - status = "okay"; - perst-gpio = <&tlmm 58 0x1>; -}; - -&pcie_phy0 { - status = "okay"; -}; - -&pcie_phy1 { - status = "okay"; -}; - -&qpic_bam { - status = "okay"; -}; - -&qpic_nand { - status = "okay"; - - nand@0 { - reg = <0>; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-bus-width = <8>; - }; -}; - -&sdhc_1 { - status = "okay"; -}; - -&qusb_phy_0 { - status = "okay"; -}; - -&qusb_phy_1 { - status = "okay"; -}; - -&ssphy_0 { - status = "okay"; -}; - -&ssphy_1 { - status = "okay"; -}; - -&usb_0 { - status = "okay"; -}; - -&usb_1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi deleted file mode 100644 index dca040f66..000000000 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ /dev/null @@ -1,693 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2017, The Linux Foundation. All rights reserved. - */ - -#include -#include - -/ { - model = "Qualcomm Technologies, Inc. IPQ8074"; - compatible = "qcom,ipq8074"; - - clocks { - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - xo: xo { - compatible = "fixed-clock"; - clock-frequency = <19200000>; - #clock-cells = <0>; - }; - }; - - cpus { - #address-cells = <0x1>; - #size-cells = <0x0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x1>; - next-level-cache = <&L2_0>; - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x2>; - next-level-cache = <&L2_0>; - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x3>; - next-level-cache = <&L2_0>; - }; - - L2_0: l2-cache { - compatible = "cache"; - cache-level = <0x2>; - }; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - soc: soc { - #address-cells = <0x1>; - #size-cells = <0x1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - ssphy_1: phy@58000 { - compatible = "qcom,ipq8074-qmp-usb3-phy"; - reg = <0x00058000 0x1c4>; - #clock-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_USB1_AUX_CLK>, - <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, - <&xo>; - clock-names = "aux", "cfg_ahb", "ref"; - - resets = <&gcc GCC_USB1_PHY_BCR>, - <&gcc GCC_USB3PHY_1_PHY_BCR>; - reset-names = "phy","common"; - status = "disabled"; - - usb1_ssphy: lane@58200 { - reg = <0x00058200 0x130>, /* Tx */ - <0x00058400 0x200>, /* Rx */ - <0x00058800 0x1f8>, /* PCS */ - <0x00058600 0x044>; /* PCS misc*/ - #phy-cells = <0>; - clocks = <&gcc GCC_USB1_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "gcc_usb1_pipe_clk_src"; - }; - }; - - qusb_phy_1: phy@59000 { - compatible = "qcom,ipq8074-qusb2-phy"; - reg = <0x00059000 0x180>; - #phy-cells = <0>; - - clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, - <&xo>; - clock-names = "cfg_ahb", "ref"; - - resets = <&gcc GCC_QUSB2_1_PHY_BCR>; - status = "disabled"; - }; - - ssphy_0: phy@78000 { - compatible = "qcom,ipq8074-qmp-usb3-phy"; - reg = <0x00078000 0x1c4>; - #clock-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_USB0_AUX_CLK>, - <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, - <&xo>; - clock-names = "aux", "cfg_ahb", "ref"; - - resets = <&gcc GCC_USB0_PHY_BCR>, - <&gcc GCC_USB3PHY_0_PHY_BCR>; - reset-names = "phy","common"; - status = "disabled"; - - usb0_ssphy: lane@78200 { - reg = <0x00078200 0x130>, /* Tx */ - <0x00078400 0x200>, /* Rx */ - <0x00078800 0x1f8>, /* PCS */ - <0x00078600 0x044>; /* PCS misc*/ - #phy-cells = <0>; - clocks = <&gcc GCC_USB0_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "gcc_usb0_pipe_clk_src"; - }; - }; - - qusb_phy_0: phy@79000 { - compatible = "qcom,ipq8074-qusb2-phy"; - reg = <0x00079000 0x180>; - #phy-cells = <0>; - - clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, - <&xo>; - clock-names = "cfg_ahb", "ref"; - - resets = <&gcc GCC_QUSB2_0_PHY_BCR>; - }; - - pcie_phy0: phy@86000 { - compatible = "qcom,ipq8074-qmp-pcie-phy"; - reg = <0x00086000 0x1000>; - #phy-cells = <0>; - clocks = <&gcc GCC_PCIE0_PIPE_CLK>; - clock-names = "pipe_clk"; - clock-output-names = "pcie20_phy0_pipe_clk"; - - resets = <&gcc GCC_PCIE0_PHY_BCR>, - <&gcc GCC_PCIE0PHY_PHY_BCR>; - reset-names = "phy", - "common"; - status = "disabled"; - }; - - pcie_phy1: phy@8e000 { - compatible = "qcom,ipq8074-qmp-pcie-phy"; - reg = <0x0008e000 0x1000>; - #phy-cells = <0>; - clocks = <&gcc GCC_PCIE1_PIPE_CLK>; - clock-names = "pipe_clk"; - clock-output-names = "pcie20_phy1_pipe_clk"; - - resets = <&gcc GCC_PCIE1_PHY_BCR>, - <&gcc GCC_PCIE1PHY_PHY_BCR>; - reset-names = "phy", - "common"; - status = "disabled"; - }; - - tlmm: pinctrl@1000000 { - compatible = "qcom,ipq8074-pinctrl"; - reg = <0x01000000 0x300000>; - interrupts = ; - gpio-controller; - gpio-ranges = <&tlmm 0 0 70>; - #gpio-cells = <0x2>; - interrupt-controller; - #interrupt-cells = <0x2>; - - serial_4_pins: serial4-pinmux { - pins = "gpio23", "gpio24"; - function = "blsp4_uart1"; - drive-strength = <8>; - bias-disable; - }; - - i2c_0_pins: i2c-0-pinmux { - pins = "gpio42", "gpio43"; - function = "blsp1_i2c"; - drive-strength = <8>; - bias-disable; - }; - - spi_0_pins: spi-0-pins { - pins = "gpio38", "gpio39", "gpio40", "gpio41"; - function = "blsp0_spi"; - drive-strength = <8>; - bias-disable; - }; - - hsuart_pins: hsuart-pins { - pins = "gpio46", "gpio47", "gpio48", "gpio49"; - function = "blsp2_uart"; - drive-strength = <8>; - bias-disable; - }; - - qpic_pins: qpic-pins { - pins = "gpio1", "gpio3", "gpio4", - "gpio5", "gpio6", "gpio7", - "gpio8", "gpio10", "gpio11", - "gpio12", "gpio13", "gpio14", - "gpio15", "gpio16", "gpio17"; - function = "qpic"; - drive-strength = <8>; - bias-disable; - }; - }; - - gcc: gcc@1800000 { - compatible = "qcom,gcc-ipq8074"; - reg = <0x01800000 0x80000>; - #clock-cells = <0x1>; - #reset-cells = <0x1>; - }; - - sdhc_1: sdhci@7824900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0x7824900 0x500>, <0x7824000 0x800>; - reg-names = "hc_mem", "core_mem"; - - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - - clocks = <&xo>, - <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>; - clock-names = "xo", "iface", "core"; - max-frequency = <384000000>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - - status = "disabled"; - }; - - blsp_dma: dma@7884000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x07884000 0x2b000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - blsp1_uart1: serial@78af000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078af000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp1_uart3: serial@78b1000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078b1000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 4>, - <&blsp_dma 5>; - dma-names = "tx", "rx"; - pinctrl-0 = <&hsuart_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - blsp1_uart5: serial@78b3000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078b3000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-0 = <&serial_4_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - blsp1_spi1: spi@78b5000 { - compatible = "qcom,spi-qup-v2.2.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x078b5000 0x600>; - interrupts = ; - spi-max-frequency = <50000000>; - clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 12>, <&blsp_dma 13>; - dma-names = "tx", "rx"; - pinctrl-0 = <&spi_0_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - blsp1_i2c2: i2c@78b6000 { - compatible = "qcom,i2c-qup-v2.2.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x078b6000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <400000>; - dmas = <&blsp_dma 15>, <&blsp_dma 14>; - dma-names = "rx", "tx"; - pinctrl-0 = <&i2c_0_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - blsp1_i2c3: i2c@78b7000 { - compatible = "qcom,i2c-qup-v2.2.1"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x078b7000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <100000>; - dmas = <&blsp_dma 17>, <&blsp_dma 16>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - qpic_bam: dma@7984000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x07984000 0x1a000>; - interrupts = ; - clocks = <&gcc GCC_QPIC_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - status = "disabled"; - }; - - qpic_nand: nand@79b0000 { - compatible = "qcom,ipq8074-nand"; - reg = <0x079b0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&gcc GCC_QPIC_CLK>, - <&gcc GCC_QPIC_AHB_CLK>; - clock-names = "core", "aon"; - - dmas = <&qpic_bam 0>, - <&qpic_bam 1>, - <&qpic_bam 2>; - dma-names = "tx", "rx", "cmd"; - pinctrl-0 = <&qpic_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - usb_0: usb@8af8800 { - compatible = "qcom,dwc3"; - reg = <0x08af8800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, - <&gcc GCC_USB0_MASTER_CLK>, - <&gcc GCC_USB0_SLEEP_CLK>, - <&gcc GCC_USB0_MOCK_UTMI_CLK>; - clock-names = "sys_noc_axi", - "master", - "sleep", - "mock_utmi"; - - assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, - <&gcc GCC_USB0_MASTER_CLK>, - <&gcc GCC_USB0_MOCK_UTMI_CLK>; - assigned-clock-rates = <133330000>, - <133330000>, - <19200000>; - - resets = <&gcc GCC_USB0_BCR>; - status = "disabled"; - - dwc_0: dwc3@8a00000 { - compatible = "snps,dwc3"; - reg = <0x8a00000 0xcd00>; - interrupts = ; - phys = <&qusb_phy_0>, <&usb0_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - tx-fifo-resize; - snps,is-utmi-l1-suspend; - snps,hird-threshold = /bits/ 8 <0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - dr_mode = "host"; - }; - }; - - usb_1: usb@8cf8800 { - compatible = "qcom,dwc3"; - reg = <0x08cf8800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, - <&gcc GCC_USB1_MASTER_CLK>, - <&gcc GCC_USB1_SLEEP_CLK>, - <&gcc GCC_USB1_MOCK_UTMI_CLK>; - clock-names = "sys_noc_axi", - "master", - "sleep", - "mock_utmi"; - - assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, - <&gcc GCC_USB1_MASTER_CLK>, - <&gcc GCC_USB1_MOCK_UTMI_CLK>; - assigned-clock-rates = <133330000>, - <133330000>, - <19200000>; - - resets = <&gcc GCC_USB1_BCR>; - status = "disabled"; - - dwc_1: dwc3@8c00000 { - compatible = "snps,dwc3"; - reg = <0x8c00000 0xcd00>; - interrupts = ; - phys = <&qusb_phy_1>, <&usb1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - tx-fifo-resize; - snps,is-utmi-l1-suspend; - snps,hird-threshold = /bits/ 8 <0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - dr_mode = "host"; - }; - }; - - intc: interrupt-controller@b000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <0x3>; - reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - watchdog: watchdog@b017000 { - compatible = "qcom,kpss-wdt"; - reg = <0xb017000 0x1000>; - interrupts = ; - clocks = <&sleep_clk>; - timeout-sec = <30>; - }; - - timer@b120000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x0b120000 0x1000>; - clock-frequency = <19200000>; - - frame@b120000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x0b121000 0x1000>, - <0x0b122000 0x1000>; - }; - - frame@b123000 { - frame-number = <1>; - interrupts = ; - reg = <0x0b123000 0x1000>; - status = "disabled"; - }; - - frame@b124000 { - frame-number = <2>; - interrupts = ; - reg = <0x0b124000 0x1000>; - status = "disabled"; - }; - - frame@b125000 { - frame-number = <3>; - interrupts = ; - reg = <0x0b125000 0x1000>; - status = "disabled"; - }; - - frame@b126000 { - frame-number = <4>; - interrupts = ; - reg = <0x0b126000 0x1000>; - status = "disabled"; - }; - - frame@b127000 { - frame-number = <5>; - interrupts = ; - reg = <0x0b127000 0x1000>; - status = "disabled"; - }; - - frame@b128000 { - frame-number = <6>; - interrupts = ; - reg = <0x0b128000 0x1000>; - status = "disabled"; - }; - }; - - pcie1: pci@10000000 { - compatible = "qcom,pcie-ipq8074"; - reg = <0x10000000 0xf1d>, - <0x10000f20 0xa8>, - <0x00088000 0x2000>, - <0x10100000 0x1000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <1>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - - phys = <&pcie_phy1>; - phy-names = "pciephy"; - - ranges = <0x81000000 0 0x10200000 0x10200000 - 0 0x100000 /* downstream I/O */ - 0x82000000 0 0x10300000 0x10300000 - 0 0xd00000>; /* non-prefetchable memory */ - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 142 - IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 143 - IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 144 - IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 145 - IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, - <&gcc GCC_PCIE1_AXI_M_CLK>, - <&gcc GCC_PCIE1_AXI_S_CLK>, - <&gcc GCC_PCIE1_AHB_CLK>, - <&gcc GCC_PCIE1_AUX_CLK>; - clock-names = "iface", - "axi_m", - "axi_s", - "ahb", - "aux"; - resets = <&gcc GCC_PCIE1_PIPE_ARES>, - <&gcc GCC_PCIE1_SLEEP_ARES>, - <&gcc GCC_PCIE1_CORE_STICKY_ARES>, - <&gcc GCC_PCIE1_AXI_MASTER_ARES>, - <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, - <&gcc GCC_PCIE1_AHB_ARES>, - <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; - reset-names = "pipe", - "sleep", - "sticky", - "axi_m", - "axi_s", - "ahb", - "axi_m_sticky"; - status = "disabled"; - }; - - pcie0: pci@20000000 { - compatible = "qcom,pcie-ipq8074"; - reg = <0x20000000 0xf1d>, - <0x20000f20 0xa8>, - <0x00080000 0x2000>, - <0x20100000 0x1000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - - phys = <&pcie_phy0>; - phy-names = "pciephy"; - - ranges = <0x81000000 0 0x20200000 0x20200000 - 0 0x100000 /* downstream I/O */ - 0x82000000 0 0x20300000 0x20300000 - 0 0xd00000>; /* non-prefetchable memory */ - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 75 - IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 78 - IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 79 - IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 83 - IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, - <&gcc GCC_PCIE0_AXI_M_CLK>, - <&gcc GCC_PCIE0_AXI_S_CLK>, - <&gcc GCC_PCIE0_AHB_CLK>, - <&gcc GCC_PCIE0_AUX_CLK>; - - clock-names = "iface", - "axi_m", - "axi_s", - "ahb", - "aux"; - resets = <&gcc GCC_PCIE0_PIPE_ARES>, - <&gcc GCC_PCIE0_SLEEP_ARES>, - <&gcc GCC_PCIE0_CORE_STICKY_ARES>, - <&gcc GCC_PCIE0_AXI_MASTER_ARES>, - <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, - <&gcc GCC_PCIE0_AHB_ARES>, - <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; - reset-names = "pipe", - "sleep", - "sticky", - "axi_m", - "axi_s", - "ahb", - "axi_m_sticky"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts deleted file mode 100644 index b9d3c5d98..000000000 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ /dev/null @@ -1,224 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/dts-v1/; - -#include "msm8916-pm8916.dtsi" -#include -#include - -/ { - model = "Longcheer L8150"; - compatible = "longcheer,l8150", "qcom,msm8916-v1-qrd/9-v1", "qcom,msm8916"; - - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0"; - }; - - reserved-memory { - // wcnss.mdt is not relocatable, so it must be loaded at 0x8b600000 - /delete-node/ wcnss@89300000; - - wcnss_mem: wcnss@8b600000 { - reg = <0x0 0x8b600000 0x0 0x600000>; - no-map; - }; - }; - - // FIXME: Use extcon device provided by charger driver when available - usb_vbus: usb-vbus { - compatible = "linux,extcon-usb-gpio"; - vbus-gpio = <&msmgpio 62 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_vbus_default>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_default>; - - label = "GPIO Buttons"; - - volume-up { - label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; -}; - -&blsp1_uart2 { - status = "okay"; -}; - -&pm8916_resin { - status = "okay"; - linux,code = ; -}; - -&pronto { - status = "okay"; -}; - -&sdhc_1 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; -}; - -&sdhc_2 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; - - non-removable; -}; - -&usb { - status = "okay"; - dr_mode = "peripheral"; - extcon = <&usb_vbus>; -}; - -&usb_hs_phy { - extcon = <&usb_vbus>; -}; - -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1300000>; - }; - - s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1287500>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - -&msmgpio { - gpio_keys_default: gpio-keys-default { - pins = "gpio107"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; - - usb_vbus_default: usb-vbus-default { - pins = "gpio62"; - function = "gpio"; - - bias-pull-up; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts deleted file mode 100644 index c3f885923..000000000 --- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include "msm8916-mtp.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM 8916 MTP"; - compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp/1", - "qcom,msm8916", "qcom,mtp"; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi deleted file mode 100644 index 1bd05046c..000000000 --- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. - */ - -#include "msm8916-pm8916.dtsi" - -/ { - aliases { - serial0 = &blsp1_uart2; - usid0 = &pm8916_0; - }; - - chosen { - stdout-path = "serial0"; - }; -}; - -&blsp1_uart2 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi deleted file mode 100644 index 4dc437f13..000000000 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ /dev/null @@ -1,562 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. - */ - -&msmgpio { - - blsp1_uart1_default: blsp1-uart1-default { - // TX, RX, CTS_N, RTS_N - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "blsp_uart1"; - - drive-strength = <16>; - bias-disable; - }; - - blsp1_uart1_sleep: blsp1-uart1-sleep { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - blsp1_uart2_default: blsp1-uart2-default { - pins = "gpio4", "gpio5"; - function = "blsp_uart2"; - - drive-strength = <16>; - bias-disable; - }; - - blsp1_uart2_sleep: blsp1-uart2-sleep { - pins = "gpio4", "gpio5"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - spi1_default: spi1-default { - pins = "gpio0", "gpio1", "gpio3"; - function = "blsp_spi1"; - - drive-strength = <12>; - bias-disable; - - cs { - pins = "gpio2"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi1_sleep: spi1-sleep { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - spi2_default: spi2-default { - pins = "gpio4", "gpio5", "gpio7"; - function = "blsp_spi2"; - - drive-strength = <12>; - bias-disable; - - cs { - pins = "gpio6"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi2_sleep: spi2-sleep { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - spi3_default: spi3-default { - pins = "gpio8", "gpio9", "gpio11"; - function = "blsp_spi3"; - - drive-strength = <12>; - bias-disable; - - cs { - pins = "gpio10"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi3_sleep: spi3-sleep { - pins = "gpio8", "gpio9", "gpio10", "gpio11"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - spi4_default: spi4-default { - pins = "gpio12", "gpio13", "gpio15"; - function = "blsp_spi4"; - - drive-strength = <12>; - bias-disable; - - cs { - pins = "gpio14"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi4_sleep: spi4-sleep { - pins = "gpio12", "gpio13", "gpio14", "gpio15"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - spi5_default: spi5-default { - pins = "gpio16", "gpio17", "gpio19"; - function = "blsp_spi5"; - - drive-strength = <12>; - bias-disable; - - cs { - pins = "gpio18"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi5_sleep: spi5-sleep { - pins = "gpio16", "gpio17", "gpio18", "gpio19"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - spi6_default: spi6-default { - pins = "gpio20", "gpio21", "gpio23"; - function = "blsp_spi6"; - - drive-strength = <12>; - bias-disable; - - cs { - pins = "gpio22"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi6_sleep: spi6-sleep { - pins = "gpio20", "gpio21", "gpio22", "gpio23"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - - i2c1_default: i2c1-default { - pins = "gpio2", "gpio3"; - function = "blsp_i2c1"; - - drive-strength = <2>; - bias-disable; - }; - - i2c1_sleep: i2c1-sleep { - pins = "gpio2", "gpio3"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - i2c2_default: i2c2-default { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - - drive-strength = <2>; - bias-disable; - }; - - i2c2_sleep: i2c2-sleep { - pins = "gpio6", "gpio7"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - i2c4_default: i2c4-default { - pins = "gpio14", "gpio15"; - function = "blsp_i2c4"; - - drive-strength = <2>; - bias-disable; - }; - - i2c4_sleep: i2c4-sleep { - pins = "gpio14", "gpio15"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - i2c5_default: i2c5-default { - pins = "gpio18", "gpio19"; - function = "blsp_i2c5"; - - drive-strength = <2>; - bias-disable; - }; - - i2c5_sleep: i2c5-sleep { - pins = "gpio18", "gpio19"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - i2c6_default: i2c6-default { - pins = "gpio22", "gpio23"; - function = "blsp_i2c6"; - - drive-strength = <2>; - bias-disable; - }; - - i2c6_sleep: i2c6-sleep { - pins = "gpio22", "gpio23"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - pmx-sdc1-clk { - sdc1_clk_on: clk-on { - pins = "sdc1_clk"; - - bias-disable; - drive-strength = <16>; - }; - sdc1_clk_off: clk-off { - pins = "sdc1_clk"; - - bias-disable; - drive-strength = <2>; - }; - }; - - pmx-sdc1-cmd { - sdc1_cmd_on: cmd-on { - pins = "sdc1_cmd"; - - bias-pull-up; - drive-strength = <10>; - }; - sdc1_cmd_off: cmd-off { - pins = "sdc1_cmd"; - - bias-pull-up; - drive-strength = <2>; - }; - }; - - pmx-sdc1-data { - sdc1_data_on: data-on { - pins = "sdc1_data"; - - bias-pull-up; - drive-strength = <10>; - }; - sdc1_data_off: data-off { - pins = "sdc1_data"; - - bias-pull-up; - drive-strength = <2>; - }; - }; - - pmx-sdc2-clk { - sdc2_clk_on: clk-on { - pins = "sdc2_clk"; - - bias-disable; - drive-strength = <16>; - }; - sdc2_clk_off: clk-off { - pins = "sdc2_clk"; - - bias-disable; - drive-strength = <2>; - }; - }; - - pmx-sdc2-cmd { - sdc2_cmd_on: cmd-on { - pins = "sdc2_cmd"; - - bias-pull-up; - drive-strength = <10>; - }; - sdc2_cmd_off: cmd-off { - pins = "sdc2_cmd"; - - bias-pull-up; - drive-strength = <2>; - }; - }; - - pmx-sdc2-data { - sdc2_data_on: data-on { - pins = "sdc2_data"; - - bias-pull-up; - drive-strength = <10>; - }; - sdc2_data_off: data-off { - pins = "sdc2_data"; - - bias-pull-up; - drive-strength = <2>; - }; - }; - - pmx-sdc2-cd-pin { - sdc2_cd_on: cd-on { - pins = "gpio38"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; - sdc2_cd_off: cd-off { - pins = "gpio38"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - }; - - cdc-pdm-lines { - cdc_pdm_lines_act: pdm-lines-on { - pins = "gpio63", "gpio64", "gpio65", "gpio66", - "gpio67", "gpio68"; - function = "cdc_pdm0"; - - drive-strength = <8>; - bias-disable; - }; - cdc_pdm_lines_sus: pdm-lines-off { - pins = "gpio63", "gpio64", "gpio65", "gpio66", - "gpio67", "gpio68"; - function = "cdc_pdm0"; - - drive-strength = <2>; - bias-pull-down; - }; - }; - - ext-pri-tlmm-lines { - ext_pri_tlmm_lines_act: ext-pa-on { - pins = "gpio113", "gpio114", "gpio115", "gpio116"; - function = "pri_mi2s"; - - drive-strength = <8>; - bias-disable; - }; - ext_pri_tlmm_lines_sus: ext-pa-off { - pins = "gpio113", "gpio114", "gpio115", "gpio116"; - function = "pri_mi2s"; - - drive-strength = <2>; - bias-disable; - }; - }; - - ext-pri-ws-line { - ext_pri_ws_act: ext-pa-on { - pins = "gpio110"; - function = "pri_mi2s_ws"; - - drive-strength = <8>; - bias-disable; - }; - ext_pri_ws_sus: ext-pa-off { - pins = "gpio110"; - function = "pri_mi2s_ws"; - - drive-strength = <2>; - bias-disable; - }; - }; - - ext-mclk-tlmm-lines { - ext_mclk_tlmm_lines_act: mclk-lines-on { - pins = "gpio116"; - function = "pri_mi2s"; - - drive-strength = <8>; - bias-disable; - }; - ext_mclk_tlmm_lines_sus: mclk-lines-off { - pins = "gpio116"; - function = "pri_mi2s"; - - drive-strength = <2>; - bias-disable; - }; - }; - - /* secondary Mi2S */ - ext-sec-tlmm-lines { - ext_sec_tlmm_lines_act: tlmm-lines-on { - pins = "gpio112", "gpio117", "gpio118", "gpio119"; - function = "sec_mi2s"; - - drive-strength = <8>; - bias-disable; - }; - ext_sec_tlmm_lines_sus: tlmm-lines-off { - pins = "gpio112", "gpio117", "gpio118", "gpio119"; - function = "sec_mi2s"; - - drive-strength = <2>; - bias-disable; - }; - }; - - cdc-dmic-lines { - cdc_dmic_lines_act: dmic-lines-on { - clk { - pins = "gpio0"; - function = "dmic0_clk"; - - drive-strength = <8>; - }; - data { - pins = "gpio1"; - function = "dmic0_data"; - - drive-strength = <8>; - }; - }; - cdc_dmic_lines_sus: dmic-lines-off { - clk { - pins = "gpio0"; - function = "dmic0_clk"; - - drive-strength = <2>; - bias-disable; - }; - data { - pins = "gpio1"; - function = "dmic0_data"; - - drive-strength = <2>; - bias-disable; - }; - }; - }; - - wcnss_pin_a: wcnss-active { - pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; - function = "wcss_wlan"; - - drive-strength = <6>; - bias-pull-up; - }; - - cci0_default: cci0-default { - pins = "gpio29", "gpio30"; - function = "cci_i2c"; - - drive-strength = <16>; - bias-disable; - }; - - camera_front_default: camera-front-default { - pwdn { - pins = "gpio33"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - }; - rst { - pins = "gpio28"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - }; - mclk1 { - pins = "gpio27"; - function = "cam_mclk1"; - - drive-strength = <16>; - bias-disable; - }; - }; - - camera_rear_default: camera-rear-default { - pwdn { - pins = "gpio34"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - }; - rst { - pins = "gpio35"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - }; - mclk0 { - pins = "gpio26"; - function = "cam_mclk0"; - - drive-strength = <16>; - bias-disable; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi deleted file mode 100644 index cd626e7db..000000000 --- a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include "msm8916.dtsi" -#include "pm8916.dtsi" - -&camss { - vdda-supply = <&pm8916_l2>; -}; - -&dsi0 { - vdda-supply = <&pm8916_l2>; - vddio-supply = <&pm8916_l6>; -}; - -&dsi_phy0 { - vddio-supply = <&pm8916_l6>; -}; - -&mpss { - cx-supply = <&pm8916_s1>; - mx-supply = <&pm8916_l3>; - pll-supply = <&pm8916_l7>; -}; - -&pronto { - vddmx-supply = <&pm8916_l3>; - vddpx-supply = <&pm8916_l7>; - - iris { - vddxo-supply = <&pm8916_l7>; - vddrfa-supply = <&pm8916_s3>; - vddpa-supply = <&pm8916_l9>; - vdddig-supply = <&pm8916_l5>; - }; -}; - -&sdhc_1 { - vmmc-supply = <&pm8916_l8>; - vqmmc-supply = <&pm8916_l5>; -}; - -&sdhc_2 { - vmmc-supply = <&pm8916_l11>; - vqmmc-supply = <&pm8916_l12>; -}; - -&usb_hs_phy { - v1p8-supply = <&pm8916_l7>; - v3p3-supply = <&pm8916_l13>; -}; - -&rpm_requests { - smd_rpm_regulators: pm8916-regulators { - compatible = "qcom,rpm-pm8916-regulators"; - - pm8916_s1: s1 {}; - pm8916_s3: s3 {}; - pm8916_s4: s4 {}; - - pm8916_l1: l1 {}; - pm8916_l2: l2 {}; - pm8916_l3: l3 {}; - pm8916_l4: l4 {}; - pm8916_l5: l5 {}; - pm8916_l6: l6 {}; - pm8916_l7: l7 {}; - pm8916_l8: l8 {}; - pm8916_l9: l9 {}; - pm8916_l10: l10 {}; - pm8916_l11: l11 {}; - pm8916_l12: l12 {}; - pm8916_l13: l13 {}; - pm8916_l14: l14 {}; - pm8916_l15: l15 {}; - pm8916_l16: l16 {}; - pm8916_l17: l17 {}; - pm8916_l18: l18 {}; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi deleted file mode 100644 index 7bf2cb015..000000000 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ /dev/null @@ -1,349 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include "msm8916-pm8916.dtsi" -#include -#include -#include - -/ { - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0"; - }; - - reserved-memory { - /* Additional memory used by Samsung firmware modifications */ - tz-apps@85500000 { - reg = <0x0 0x85500000 0x0 0xb00000>; - no-map; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_default>; - - label = "GPIO Buttons"; - - volume-up { - label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - home { - label = "Home"; - gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-hall-sensor { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_hall_sensor_default>; - - label = "GPIO Hall Effect Sensor"; - - hall-sensor { - label = "Hall Effect Sensor"; - gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - linux,can-disable; - }; - }; - - reg_vdd_tsp: regulator-vdd-tsp { - compatible = "regulator-fixed"; - regulator-name = "vdd_tsp"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&msmgpio 73 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&tsp_en_default>; - }; - - i2c-muic { - compatible = "i2c-gpio"; - sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - scl-gpios = <&msmgpio 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; - - pinctrl-names = "default"; - pinctrl-0 = <&muic_i2c_default>; - - #address-cells = <1>; - #size-cells = <0>; - - muic: extcon@25 { - compatible = "siliconmitus,sm5502-muic"; - - reg = <0x25>; - interrupt-parent = <&msmgpio>; - interrupts = <12 IRQ_TYPE_EDGE_FALLING>; - - pinctrl-names = "default"; - pinctrl-0 = <&muic_int_default>; - }; - }; -}; - -&blsp_i2c2 { - status = "okay"; - - accelerometer: accelerometer@10 { - compatible = "bosch,bmc150_accel"; - reg = <0x10>; - interrupt-parent = <&msmgpio>; - interrupts = <115 IRQ_TYPE_EDGE_RISING>; - - vdd-supply = <&pm8916_l17>; - vddio-supply = <&pm8916_l5>; - - pinctrl-names = "default"; - pinctrl-0 = <&accel_int_default>; - }; - - magnetometer@12 { - compatible = "bosch,bmc150_magn"; - reg = <0x12>; - - vdd-supply = <&pm8916_l17>; - vddio-supply = <&pm8916_l5>; - }; -}; - -&blsp1_uart2 { - status = "okay"; -}; - -&dsi0 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mdss_default>; - pinctrl-1 = <&mdss_sleep>; -}; - -&pm8916_resin { - status = "okay"; - linux,code = ; -}; - -&pronto { - status = "okay"; -}; - -&sdhc_1 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; -}; - -&sdhc_2 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; -}; - -&usb { - status = "okay"; - extcon = <&muic>, <&muic>; -}; - -&usb_hs_phy { - extcon = <&muic>; -}; - -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1300000>; - }; - - s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1287500>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - -&msmgpio { - accel_int_default: accel-int-default { - pins = "gpio115"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - gpio_keys_default: gpio-keys-default { - pins = "gpio107", "gpio109"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; - - gpio_hall_sensor_default: gpio-hall-sensor-default { - pins = "gpio52"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - mdss { - mdss_default: mdss-default { - pins = "gpio25"; - function = "gpio"; - - drive-strength = <8>; - bias-disable; - }; - mdss_sleep: mdss-sleep { - pins = "gpio25"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-down; - }; - }; - - muic_i2c_default: muic-i2c-default { - pins = "gpio105", "gpio106"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - muic_int_default: muic-int-default { - pins = "gpio12"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - tsp_en_default: tsp-en-default { - pins = "gpio73"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts deleted file mode 100644 index 086f07ead..000000000 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts +++ /dev/null @@ -1,62 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/dts-v1/; - -#include "msm8916-samsung-a2015-common.dtsi" - -/ { - model = "Samsung Galaxy A3U (EUR)"; - compatible = "samsung,a3u-eur", "qcom,msm8916"; - - reg_panel_vdd3: regulator-panel-vdd3 { - compatible = "regulator-fixed"; - regulator-name = "panel_vdd3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&msmgpio 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&panel_vdd3_default>; - }; -}; - -&accelerometer { - mount-matrix = "0", "1", "0", - "1", "0", "0", - "0", "0", "1"; -}; - -&dsi0 { - panel@0 { - reg = <0>; - - compatible = "samsung,s6e88a0-ams452ef01"; - - vdd3-supply = <®_panel_vdd3>; - vci-supply = <&pm8916_l17>; - reset-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; -}; - -&dsi0_out { - data-lanes = <0 1>; - remote-endpoint = <&panel_in>; -}; - -&msmgpio { - panel_vdd3_default: panel-vdd3-default { - pins = "gpio9"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts deleted file mode 100644 index dd35c3344..000000000 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/dts-v1/; - -#include "msm8916-samsung-a2015-common.dtsi" - -/ { - model = "Samsung Galaxy A5U (EUR)"; - compatible = "samsung,a5u-eur", "qcom,msm8916"; -}; - -&accelerometer { - mount-matrix = "-1", "0", "0", - "0", "1", "0", - "0", "0", "1"; -}; - -&blsp_i2c5 { - status = "okay"; - - touchscreen@48 { - compatible = "melfas,mms345l"; - - reg = <0x48>; - interrupt-parent = <&msmgpio>; - interrupts = <13 IRQ_TYPE_EDGE_FALLING>; - - touchscreen-size-x = <720>; - touchscreen-size-y = <1280>; - - avdd-supply = <®_vdd_tsp>; - vdd-supply = <&pm8916_l6>; - - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_default>; - }; -}; - -&pronto { - iris { - compatible = "qcom,wcn3660b"; - }; -}; - -&msmgpio { - ts_int_default: ts-int-default { - pins = "gpio13"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi deleted file mode 100644 index 291276a38..000000000 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ /dev/null @@ -1,1921 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - aliases { - mmc0 = &sdhc_1; /* SDC1 eMMC slot */ - mmc1 = &sdhc_2; /* SDC2 SD card slot */ - }; - - chosen { }; - - memory { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - tz-apps@86000000 { - reg = <0x0 0x86000000 0x0 0x300000>; - no-map; - }; - - smem_mem: smem_region@86300000 { - reg = <0x0 0x86300000 0x0 0x100000>; - no-map; - }; - - hypervisor@86400000 { - reg = <0x0 0x86400000 0x0 0x100000>; - no-map; - }; - - tz@86500000 { - reg = <0x0 0x86500000 0x0 0x180000>; - no-map; - }; - - reserved@86680000 { - reg = <0x0 0x86680000 0x0 0x80000>; - no-map; - }; - - rmtfs@86700000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x86700000 0x0 0xe0000>; - no-map; - - qcom,client-id = <1>; - }; - - rfsa@867e0000 { - reg = <0x0 0x867e0000 0x0 0x20000>; - no-map; - }; - - mpss_mem: mpss@86800000 { - reg = <0x0 0x86800000 0x0 0x2b00000>; - no-map; - }; - - wcnss_mem: wcnss@89300000 { - reg = <0x0 0x89300000 0x0 0x600000>; - no-map; - }; - - venus_mem: venus@89900000 { - reg = <0x0 0x89900000 0x0 0x600000>; - no-map; - }; - - mba_mem: mba@8ea00000 { - no-map; - reg = <0 0x8ea00000 0 0x100000>; - }; - }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - clocks = <&apcs>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - power-domains = <&CPU_PD0>; - power-domain-names = "psci"; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - clocks = <&apcs>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - power-domains = <&CPU_PD1>; - power-domain-names = "psci"; - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - clocks = <&apcs>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - power-domains = <&CPU_PD2>; - power-domain-names = "psci"; - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x3>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - clocks = <&apcs>; - operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; - power-domains = <&CPU_PD3>; - power-domain-names = "psci"; - }; - - L2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - idle-state-name = "standalone-power-collapse"; - arm,psci-suspend-param = <0x40000002>; - entry-latency-us = <130>; - exit-latency-us = <150>; - min-residency-us = <2000>; - local-timer-stop; - }; - }; - - domain-idle-states { - - CLUSTER_RET: cluster-retention { - compatible = "domain-idle-state"; - arm,psci-suspend-param = <0x41000012>; - entry-latency-us = <500>; - exit-latency-us = <500>; - min-residency-us = <2000>; - }; - - CLUSTER_PWRDN: cluster-gdhs { - compatible = "domain-idle-state"; - arm,psci-suspend-param = <0x41000032>; - entry-latency-us = <2000>; - exit-latency-us = <2000>; - min-residency-us = <6000>; - }; - }; - }; - - cpu_opp_table: cpu-opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - }; - opp-998400000 { - opp-hz = /bits/ 64 <998400000>; - }; - }; - - firmware { - scm: scm { - compatible = "qcom,scm-msm8916", "qcom,scm"; - clocks = <&gcc GCC_CRYPTO_CLK>, - <&gcc GCC_CRYPTO_AXI_CLK>, - <&gcc GCC_CRYPTO_AHB_CLK>; - clock-names = "core", "bus", "iface"; - #reset-cells = <1>; - - qcom,dload-mode = <&tcsr 0x6100>; - }; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - - CPU_PD0: power-domain-cpu0 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&CPU_SLEEP_0>; - }; - - CPU_PD1: power-domain-cpu1 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&CPU_SLEEP_0>; - }; - - CPU_PD2: power-domain-cpu2 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&CPU_SLEEP_0>; - }; - - CPU_PD3: power-domain-cpu3 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&CPU_SLEEP_0>; - }; - - CLUSTER_PD: power-domain-cluster { - #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; - }; - }; - - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = ; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8916"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8916"; - #clock-cells = <1>; - }; - }; - }; - }; - - smem { - compatible = "qcom,smem"; - - memory-region = <&smem_mem>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-hexagon { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - - interrupts = ; - - qcom,ipc = <&apcs 8 14>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - hexagon_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - - #qcom,smem-state-cells = <1>; - }; - - hexagon_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-wcnss { - compatible = "qcom,smp2p"; - qcom,smem = <451>, <431>; - - interrupts = ; - - qcom,ipc = <&apcs 8 18>; - - qcom,local-pid = <0>; - qcom,remote-pid = <4>; - - wcnss_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - - #qcom,smem-state-cells = <1>; - }; - - wcnss_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smsm { - compatible = "qcom,smsm"; - - #address-cells = <1>; - #size-cells = <0>; - - qcom,ipc-1 = <&apcs 8 13>; - qcom,ipc-3 = <&apcs 8 19>; - - apps_smsm: apps@0 { - reg = <0>; - - #qcom,smem-state-cells = <1>; - }; - - hexagon_smsm: hexagon@1 { - reg = <1>; - interrupts = ; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - wcnss_smsm: wcnss@6 { - reg = <6>; - interrupts = ; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - rng@22000 { - compatible = "qcom,prng"; - reg = <0x00022000 0x200>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; - - restart@4ab000 { - compatible = "qcom,pshold"; - reg = <0x004ab000 0x4>; - }; - - qfprom: qfprom@5c000 { - compatible = "qcom,qfprom"; - reg = <0x0005c000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - tsens_caldata: caldata@d0 { - reg = <0xd0 0x8>; - }; - tsens_calsel: calsel@ec { - reg = <0xec 0x4>; - }; - }; - - rpm_msg_ram: memory@60000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0x00060000 0x8000>; - }; - - bimc: interconnect@400000 { - compatible = "qcom,msm8916-bimc"; - reg = <0x00400000 0x62000>; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_BIMC_CLK>, - <&rpmcc RPM_SMD_BIMC_A_CLK>; - }; - - tsens: thermal-sensor@4a9000 { - compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; - reg = <0x004a9000 0x1000>, /* TM */ - <0x004a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; - nvmem-cell-names = "calib", "calib_sel"; - #qcom,sensors = <5>; - interrupts = ; - interrupt-names = "uplow"; - #thermal-sensor-cells = <1>; - }; - - pcnoc: interconnect@500000 { - compatible = "qcom,msm8916-pcnoc"; - reg = <0x00500000 0x11000>; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, - <&rpmcc RPM_SMD_PCNOC_A_CLK>; - }; - - snoc: interconnect@580000 { - compatible = "qcom,msm8916-snoc"; - reg = <0x00580000 0x14000>; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_SNOC_CLK>, - <&rpmcc RPM_SMD_SNOC_A_CLK>; - }; - - /* System CTIs */ - /* CTI 0 - TMC connections */ - cti0: cti@810000 { - compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x00810000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - status = "disabled"; - }; - - /* CTI 1 - TPIU connections */ - cti1: cti@811000 { - compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x00811000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - status = "disabled"; - }; - - /* CTIs 2-11 - no information - not instantiated */ - - tpiu: tpiu@820000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0x00820000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - status = "disabled"; - - in-ports { - port { - tpiu_in: endpoint { - remote-endpoint = <&replicator_out1>; - }; - }; - }; - }; - - funnel0: funnel@821000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x00821000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - status = "disabled"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* - * Not described input ports: - * 0 - connected to Resource and Power Manger CPU ETM - * 1 - not-connected - * 2 - connected to Modem CPU ETM - * 3 - not-connected - * 5 - not-connected - * 6 - connected trought funnel to Wireless CPU ETM - * 7 - connected to STM component - */ - - port@4 { - reg = <4>; - funnel0_in4: endpoint { - remote-endpoint = <&funnel1_out>; - }; - }; - }; - - out-ports { - port { - funnel0_out: endpoint { - remote-endpoint = <&etf_in>; - }; - }; - }; - }; - - replicator: replicator@824000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0x00824000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - status = "disabled"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = <&etr_in>; - }; - }; - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = <&tpiu_in>; - }; - }; - }; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = <&etf_out>; - }; - }; - }; - }; - - etf: etf@825000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x00825000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - status = "disabled"; - - in-ports { - port { - etf_in: endpoint { - remote-endpoint = <&funnel0_out>; - }; - }; - }; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = <&replicator_in>; - }; - }; - }; - }; - - etr: etr@826000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x00826000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - status = "disabled"; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = <&replicator_out0>; - }; - }; - }; - }; - - funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x00841000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - status = "disabled"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel1_in0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - port@1 { - reg = <1>; - funnel1_in1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - port@2 { - reg = <2>; - funnel1_in2: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - port@3 { - reg = <3>; - funnel1_in3: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - }; - - out-ports { - port { - funnel1_out: endpoint { - remote-endpoint = <&funnel0_in4>; - }; - }; - }; - }; - - debug0: debug@850000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x00850000 0x1000>; - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - cpu = <&CPU0>; - status = "disabled"; - }; - - debug1: debug@852000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x00852000 0x1000>; - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - cpu = <&CPU1>; - status = "disabled"; - }; - - debug2: debug@854000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x00854000 0x1000>; - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - cpu = <&CPU2>; - status = "disabled"; - }; - - debug3: debug@856000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x00856000 0x1000>; - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - cpu = <&CPU3>; - status = "disabled"; - }; - - /* Core CTIs; CTIs 12-15 */ - /* CTI - CPU-0 */ - cti12: cti@858000 { - compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", - "arm,primecell"; - reg = <0x00858000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU0>; - arm,cs-dev-assoc = <&etm0>; - - status = "disabled"; - }; - - /* CTI - CPU-1 */ - cti13: cti@859000 { - compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", - "arm,primecell"; - reg = <0x00859000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU1>; - arm,cs-dev-assoc = <&etm1>; - - status = "disabled"; - }; - - /* CTI - CPU-2 */ - cti14: cti@85a000 { - compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", - "arm,primecell"; - reg = <0x0085a000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU2>; - arm,cs-dev-assoc = <&etm2>; - - status = "disabled"; - }; - - /* CTI - CPU-3 */ - cti15: cti@85b000 { - compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", - "arm,primecell"; - reg = <0x0085b000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU3>; - arm,cs-dev-assoc = <&etm3>; - - status = "disabled"; - }; - - etm0: etm@85c000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x0085c000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - arm,coresight-loses-context-with-cpu; - - cpu = <&CPU0>; - - status = "disabled"; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = <&funnel1_in0>; - }; - }; - }; - }; - - etm1: etm@85d000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x0085d000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - arm,coresight-loses-context-with-cpu; - - cpu = <&CPU1>; - - status = "disabled"; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = <&funnel1_in1>; - }; - }; - }; - }; - - etm2: etm@85e000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x0085e000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - arm,coresight-loses-context-with-cpu; - - cpu = <&CPU2>; - - status = "disabled"; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = <&funnel1_in2>; - }; - }; - }; - }; - - etm3: etm@85f000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x0085f000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - arm,coresight-loses-context-with-cpu; - - cpu = <&CPU3>; - - status = "disabled"; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = <&funnel1_in3>; - }; - }; - }; - }; - - msmgpio: pinctrl@1000000 { - compatible = "qcom,msm8916-pinctrl"; - reg = <0x01000000 0x300000>; - interrupts = ; - gpio-controller; - gpio-ranges = <&msmgpio 0 0 122>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gcc: clock-controller@1800000 { - compatible = "qcom,gcc-msm8916"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0x01800000 0x80000>; - }; - - tcsr_mutex: hwlock@1905000 { - compatible = "qcom,tcsr-mutex"; - reg = <0x01905000 0x20000>; - #hwlock-cells = <1>; - }; - - tcsr: syscon@1937000 { - compatible = "qcom,tcsr-msm8916", "syscon"; - reg = <0x01937000 0x30000>; - }; - - mdss: mdss@1a00000 { - compatible = "qcom,mdss"; - reg = <0x01a00000 0x1000>, - <0x01ac8000 0x3000>; - reg-names = "mdss_phys", "vbif_phys"; - - power-domains = <&gcc MDSS_GDSC>; - - clocks = <&gcc GCC_MDSS_AHB_CLK>, - <&gcc GCC_MDSS_AXI_CLK>, - <&gcc GCC_MDSS_VSYNC_CLK>; - clock-names = "iface", - "bus", - "vsync"; - - interrupts = ; - - interrupt-controller; - #interrupt-cells = <1>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mdp: mdp@1a01000 { - compatible = "qcom,mdp5"; - reg = <0x01a01000 0x89000>; - reg-names = "mdp_phys"; - - interrupt-parent = <&mdss>; - interrupts = <0>; - - clocks = <&gcc GCC_MDSS_AHB_CLK>, - <&gcc GCC_MDSS_AXI_CLK>, - <&gcc GCC_MDSS_MDP_CLK>, - <&gcc GCC_MDSS_VSYNC_CLK>; - clock-names = "iface", - "bus", - "core", - "vsync"; - - iommus = <&apps_iommu 4>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdp5_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; - }; - - dsi0: dsi@1a98000 { - compatible = "qcom,mdss-dsi-ctrl"; - reg = <0x01a98000 0x25c>; - reg-names = "dsi_ctrl"; - - interrupt-parent = <&mdss>; - interrupts = <4>; - - assigned-clocks = <&gcc BYTE0_CLK_SRC>, - <&gcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi_phy0 0>, - <&dsi_phy0 1>; - - clocks = <&gcc GCC_MDSS_MDP_CLK>, - <&gcc GCC_MDSS_AHB_CLK>, - <&gcc GCC_MDSS_AXI_CLK>, - <&gcc GCC_MDSS_BYTE0_CLK>, - <&gcc GCC_MDSS_PCLK0_CLK>, - <&gcc GCC_MDSS_ESC0_CLK>; - clock-names = "mdp_core", - "iface", - "bus", - "byte", - "pixel", - "core"; - phys = <&dsi_phy0>; - phy-names = "dsi-phy"; - - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - remote-endpoint = <&mdp5_intf1_out>; - }; - }; - - port@1 { - reg = <1>; - dsi0_out: endpoint { - }; - }; - }; - }; - - dsi_phy0: dsi-phy@1a98300 { - compatible = "qcom,dsi-phy-28nm-lp"; - reg = <0x01a98300 0xd4>, - <0x01a98500 0x280>, - <0x01a98780 0x30>; - reg-names = "dsi_pll", - "dsi_phy", - "dsi_phy_regulator"; - - #clock-cells = <1>; - #phy-cells = <0>; - - clocks = <&gcc GCC_MDSS_AHB_CLK>, - <&xo_board>; - clock-names = "iface", "ref"; - }; - }; - - camss: camss@1b00000 { - compatible = "qcom,msm8916-camss"; - reg = <0x01b0ac00 0x200>, - <0x01b00030 0x4>, - <0x01b0b000 0x200>, - <0x01b00038 0x4>, - <0x01b08000 0x100>, - <0x01b08400 0x100>, - <0x01b0a000 0x500>, - <0x01b00020 0x10>, - <0x01b10000 0x1000>; - reg-names = "csiphy0", - "csiphy0_clk_mux", - "csiphy1", - "csiphy1_clk_mux", - "csid0", - "csid1", - "ispif", - "csi_clk_mux", - "vfe0"; - interrupts = , - , - , - , - , - ; - interrupt-names = "csiphy0", - "csiphy1", - "csid0", - "csid1", - "ispif", - "vfe0"; - power-domains = <&gcc VFE_GDSC>; - clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, - <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, - <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, - <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, - <&gcc GCC_CAMSS_CSI0_AHB_CLK>, - <&gcc GCC_CAMSS_CSI0_CLK>, - <&gcc GCC_CAMSS_CSI0PHY_CLK>, - <&gcc GCC_CAMSS_CSI0PIX_CLK>, - <&gcc GCC_CAMSS_CSI0RDI_CLK>, - <&gcc GCC_CAMSS_CSI1_AHB_CLK>, - <&gcc GCC_CAMSS_CSI1_CLK>, - <&gcc GCC_CAMSS_CSI1PHY_CLK>, - <&gcc GCC_CAMSS_CSI1PIX_CLK>, - <&gcc GCC_CAMSS_CSI1RDI_CLK>, - <&gcc GCC_CAMSS_AHB_CLK>, - <&gcc GCC_CAMSS_VFE0_CLK>, - <&gcc GCC_CAMSS_CSI_VFE0_CLK>, - <&gcc GCC_CAMSS_VFE_AHB_CLK>, - <&gcc GCC_CAMSS_VFE_AXI_CLK>; - clock-names = "top_ahb", - "ispif_ahb", - "csiphy0_timer", - "csiphy1_timer", - "csi0_ahb", - "csi0", - "csi0_phy", - "csi0_pix", - "csi0_rdi", - "csi1_ahb", - "csi1", - "csi1_phy", - "csi1_pix", - "csi1_rdi", - "ahb", - "vfe0", - "csi_vfe0", - "vfe_ahb", - "vfe_axi"; - iommus = <&apps_iommu 3>; - status = "disabled"; - ports { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - cci: cci@1b0c000 { - compatible = "qcom,msm8916-cci"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x01b0c000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, - <&gcc GCC_CAMSS_CCI_AHB_CLK>, - <&gcc GCC_CAMSS_CCI_CLK>, - <&gcc GCC_CAMSS_AHB_CLK>; - clock-names = "camss_top_ahb", "cci_ahb", - "cci", "camss_ahb"; - assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, - <&gcc GCC_CAMSS_CCI_CLK>; - assigned-clock-rates = <80000000>, <19200000>; - pinctrl-names = "default"; - pinctrl-0 = <&cci0_default>; - status = "disabled"; - - cci_i2c0: i2c-bus@0 { - reg = <0>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gpu@1c00000 { - compatible = "qcom,adreno-306.0", "qcom,adreno"; - reg = <0x01c00000 0x20000>; - reg-names = "kgsl_3d0_reg_memory"; - interrupts = ; - interrupt-names = "kgsl_3d0_irq"; - clock-names = - "core", - "iface", - "mem", - "mem_iface", - "alt_mem_iface", - "gfx3d"; - clocks = - <&gcc GCC_OXILI_GFX3D_CLK>, - <&gcc GCC_OXILI_AHB_CLK>, - <&gcc GCC_OXILI_GMEM_CLK>, - <&gcc GCC_BIMC_GFX_CLK>, - <&gcc GCC_BIMC_GPU_CLK>, - <&gcc GFX3D_CLK_SRC>; - power-domains = <&gcc OXILI_GDSC>; - operating-points-v2 = <&gpu_opp_table>; - iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - }; - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - }; - }; - }; - - venus: video-codec@1d00000 { - compatible = "qcom,msm8916-venus"; - reg = <0x01d00000 0xff000>; - interrupts = ; - power-domains = <&gcc VENUS_GDSC>; - clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, - <&gcc GCC_VENUS0_AHB_CLK>, - <&gcc GCC_VENUS0_AXI_CLK>; - clock-names = "core", "iface", "bus"; - iommus = <&apps_iommu 5>; - memory-region = <&venus_mem>; - status = "okay"; - - video-decoder { - compatible = "venus-decoder"; - }; - - video-encoder { - compatible = "venus-encoder"; - }; - }; - - apps_iommu: iommu@1ef0000 { - #address-cells = <1>; - #size-cells = <1>; - #iommu-cells = <1>; - compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; - ranges = <0 0x01e20000 0x40000>; - reg = <0x01ef0000 0x3000>; - clocks = <&gcc GCC_SMMU_CFG_CLK>, - <&gcc GCC_APSS_TCU_CLK>; - clock-names = "iface", "bus"; - qcom,iommu-secure-id = <17>; - - // vfe: - iommu-ctx@3000 { - compatible = "qcom,msm-iommu-v1-sec"; - reg = <0x3000 0x1000>; - interrupts = ; - }; - - // mdp_0: - iommu-ctx@4000 { - compatible = "qcom,msm-iommu-v1-ns"; - reg = <0x4000 0x1000>; - interrupts = ; - }; - - // venus_ns: - iommu-ctx@5000 { - compatible = "qcom,msm-iommu-v1-sec"; - reg = <0x5000 0x1000>; - interrupts = ; - }; - }; - - gpu_iommu: iommu@1f08000 { - #address-cells = <1>; - #size-cells = <1>; - #iommu-cells = <1>; - compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; - ranges = <0 0x01f08000 0x10000>; - clocks = <&gcc GCC_SMMU_CFG_CLK>, - <&gcc GCC_GFX_TCU_CLK>; - clock-names = "iface", "bus"; - qcom,iommu-secure-id = <18>; - - // gfx3d_user: - iommu-ctx@1000 { - compatible = "qcom,msm-iommu-v1-ns"; - reg = <0x1000 0x1000>; - interrupts = ; - }; - - // gfx3d_priv: - iommu-ctx@2000 { - compatible = "qcom,msm-iommu-v1-ns"; - reg = <0x2000 0x1000>; - interrupts = ; - }; - }; - - spmi_bus: spmi@200f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0200f000 0x001000>, - <0x02400000 0x400000>, - <0x02c00000 0x400000>, - <0x03800000 0x200000>, - <0x0200a000 0x002100>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - mpss: remoteproc@4080000 { - compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil"; - reg = <0x04080000 0x100>, - <0x04020000 0x040>; - - reg-names = "qdsp6", "rmb"; - - interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, - <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, - <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, - <&gcc GCC_BOOT_ROM_AHB_CLK>, - <&xo_board>; - clock-names = "iface", "bus", "mem", "xo"; - - qcom,smem-states = <&hexagon_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - resets = <&scm 0>; - reset-names = "mss_restart"; - - qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; - - status = "disabled"; - - mba { - memory-region = <&mba_mem>; - }; - - mpss { - memory-region = <&mpss_mem>; - }; - - smd-edge { - interrupts = ; - - qcom,smd-edge = <0>; - qcom,ipc = <&apcs 8 12>; - qcom,remote-pid = <1>; - - label = "hexagon"; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,smd-channels = "fastrpcsmd-apps-dsp"; - label = "adsp"; - - #address-cells = <1>; - #size-cells = <0>; - - cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - }; - }; - }; - }; - - sound: sound@7702000 { - status = "disabled"; - compatible = "qcom,apq8016-sbc-sndcard"; - reg = <0x07702000 0x4>, <0x07702004 0x4>; - reg-names = "mic-iomux", "spkr-iomux"; - }; - - lpass: audio-controller@7708000 { - status = "disabled"; - compatible = "qcom,lpass-cpu-apq8016"; - - /* - * Note: Unlike the name would suggest, the SEC_I2S_CLK - * is actually only used by Tertiary MI2S while - * Primary/Secondary MI2S both use the PRI_I2S_CLK. - */ - clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, - <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, - <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>, - <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, - <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, - <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, - <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>; - - clock-names = "ahbix-clk", - "pcnoc-mport-clk", - "pcnoc-sway-clk", - "mi2s-bit-clk0", - "mi2s-bit-clk1", - "mi2s-bit-clk2", - "mi2s-bit-clk3"; - #sound-dai-cells = <1>; - - interrupts = ; - interrupt-names = "lpass-irq-lpaif"; - reg = <0x07708000 0x10000>; - reg-names = "lpass-lpaif"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - lpass_codec: audio-codec@771c000 { - compatible = "qcom,msm8916-wcd-digital-codec"; - reg = <0x0771c000 0x400>; - clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, - <&gcc GCC_CODEC_DIGCODEC_CLK>; - clock-names = "ahbix-clk", "mclk"; - #sound-dai-cells = <1>; - }; - - sdhc_1: sdhci@7824000 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0x07824900 0x11c>, <0x07824000 0x800>; - reg-names = "hc_mem", "core_mem"; - - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; - mmc-ddr-1_8v; - bus-width = <8>; - non-removable; - status = "disabled"; - }; - - sdhc_2: sdhci@7864000 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0x07864900 0x11c>, <0x07864000 0x800>; - reg-names = "hc_mem", "core_mem"; - - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; - bus-width = <4>; - status = "disabled"; - }; - - blsp_dma: dma@7884000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x07884000 0x23000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - status = "disabled"; - }; - - blsp1_uart1: serial@78af000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078af000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 1>, <&blsp_dma 0>; - dma-names = "rx", "tx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart1_default>; - pinctrl-1 = <&blsp1_uart1_sleep>; - status = "disabled"; - }; - - blsp1_uart2: serial@78b0000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078b0000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 3>, <&blsp_dma 2>; - dma-names = "rx", "tx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; - status = "disabled"; - }; - - blsp_i2c1: i2c@78b5000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b5000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c1_default>; - pinctrl-1 = <&i2c1_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_spi1: spi@78b5000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b5000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 5>, <&blsp_dma 4>; - dma-names = "rx", "tx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi1_default>; - pinctrl-1 = <&spi1_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c2: i2c@78b6000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b6000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_default>; - pinctrl-1 = <&i2c2_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_spi2: spi@78b6000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b6000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 7>, <&blsp_dma 6>; - dma-names = "rx", "tx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi2_default>; - pinctrl-1 = <&spi2_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_spi3: spi@78b7000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b7000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 9>, <&blsp_dma 8>; - dma-names = "rx", "tx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi3_default>; - pinctrl-1 = <&spi3_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c4: i2c@78b8000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b8000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c4_default>; - pinctrl-1 = <&i2c4_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_spi4: spi@78b8000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b8000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 11>, <&blsp_dma 10>; - dma-names = "rx", "tx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi4_default>; - pinctrl-1 = <&spi4_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c5: i2c@78b9000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b9000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c5_default>; - pinctrl-1 = <&i2c5_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_spi5: spi@78b9000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b9000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 13>, <&blsp_dma 12>; - dma-names = "rx", "tx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi5_default>; - pinctrl-1 = <&spi5_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c6: i2c@78ba000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078ba000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c6_default>; - pinctrl-1 = <&i2c6_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_spi6: spi@78ba000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078ba000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 15>, <&blsp_dma 14>; - dma-names = "rx", "tx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi6_default>; - pinctrl-1 = <&spi6_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - usb: usb@78d9000 { - compatible = "qcom,ci-hdrc"; - reg = <0x078d9000 0x200>, - <0x078d9200 0x200>; - interrupts = , - ; - clocks = <&gcc GCC_USB_HS_AHB_CLK>, - <&gcc GCC_USB_HS_SYSTEM_CLK>; - clock-names = "iface", "core"; - assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; - assigned-clock-rates = <80000000>; - resets = <&gcc GCC_USB_HS_BCR>; - reset-names = "core"; - phy_type = "ulpi"; - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - ahb-burst-config = <0>; - phy-names = "usb-phy"; - phys = <&usb_hs_phy>; - status = "disabled"; - #reset-cells = <1>; - - ulpi { - usb_hs_phy: phy { - compatible = "qcom,usb-hs-phy-msm8916", - "qcom,usb-hs-phy"; - #phy-cells = <0>; - clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; - clock-names = "ref", "sleep"; - resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; - reset-names = "phy", "por"; - qcom,init-seq = /bits/ 8 <0x0 0x44 - 0x1 0x6b 0x2 0x24 0x3 0x13>; - }; - }; - }; - - pronto: remoteproc@a21b000 { - compatible = "qcom,pronto-v2-pil", "qcom,pronto"; - reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; - reg-names = "ccu", "dxe", "pmu"; - - memory-region = <&wcnss_mem>; - - interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - qcom,state = <&wcnss_smp2p_out 0>; - qcom,state-names = "stop"; - - pinctrl-names = "default"; - pinctrl-0 = <&wcnss_pin_a>; - - status = "disabled"; - - iris { - compatible = "qcom,wcn3620"; - - clocks = <&rpmcc RPM_SMD_RF_CLK2>; - clock-names = "xo"; - }; - - smd-edge { - interrupts = ; - - qcom,ipc = <&apcs 8 17>; - qcom,smd-edge = <6>; - qcom,remote-pid = <4>; - - label = "pronto"; - - wcnss { - compatible = "qcom,wcnss"; - qcom,smd-channels = "WCNSS_CTRL"; - - qcom,mmio = <&pronto>; - - bt { - compatible = "qcom,wcnss-bt"; - }; - - wifi { - compatible = "qcom,wcnss-wlan"; - - interrupts = , - ; - interrupt-names = "tx", "rx"; - - qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; - qcom,smem-state-names = "tx-enable", "tx-rings-empty"; - }; - }; - }; - }; - - intc: interrupt-controller@b000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; - }; - - apcs: mailbox@b011000 { - compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; - reg = <0x0b011000 0x1000>; - #mbox-cells = <1>; - clocks = <&a53pll>, <&gcc GPLL0_VOTE>; - clock-names = "pll", "aux"; - #clock-cells = <0>; - }; - - a53pll: clock@b016000 { - compatible = "qcom,msm8916-a53pll"; - reg = <0x0b016000 0x40>; - #clock-cells = <0>; - }; - - timer@b020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x0b020000 0x1000>; - clock-frequency = <19200000>; - - frame@b021000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x0b021000 0x1000>, - <0x0b022000 0x1000>; - }; - - frame@b023000 { - frame-number = <1>; - interrupts = ; - reg = <0x0b023000 0x1000>; - status = "disabled"; - }; - - frame@b024000 { - frame-number = <2>; - interrupts = ; - reg = <0x0b024000 0x1000>; - status = "disabled"; - }; - - frame@b025000 { - frame-number = <3>; - interrupts = ; - reg = <0x0b025000 0x1000>; - status = "disabled"; - }; - - frame@b026000 { - frame-number = <4>; - interrupts = ; - reg = <0x0b026000 0x1000>; - status = "disabled"; - }; - - frame@b027000 { - frame-number = <5>; - interrupts = ; - reg = <0x0b027000 0x1000>; - status = "disabled"; - }; - - frame@b028000 { - frame-number = <6>; - interrupts = ; - reg = <0x0b028000 0x1000>; - status = "disabled"; - }; - }; - }; - - thermal-zones { - cpu0-1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 5>; - - trips { - cpu0_1_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu0_1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu0_1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 4>; - - trips { - cpu2_3_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu2_3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 2>; - - trips { - gpu_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - gpu_crit: gpu_crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 1>; - - trips { - cam_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 0>; - - trips { - modem_alert0: trip-point0 { - temperature = <85000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; - -#include "msm8916-pins.dtsi" diff --git a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts deleted file mode 100644 index cb82864a9..000000000 --- a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts +++ /dev/null @@ -1,279 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2015, LGE Inc. All rights reserved. - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * Copyright (c) 2021, Petr Vorel - */ - -/dts-v1/; - -#include "msm8992.dtsi" - -/ { - model = "LG Nexus 5X"; - compatible = "lg,bullhead", "qcom,msm8992"; - /* required for bootloader to select correct board */ - qcom,msm-id = <251 0>, <252 0>; - qcom,board-id = <0xb64 0>; - qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>; - - /* Bullhead firmware doesn't support PSCI */ - /delete-node/ psci; - - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ramoops@1ff00000 { - compatible = "ramoops"; - reg = <0x0 0x1ff00000 0x0 0x40000>; - console-size = <0x10000>; - record-size = <0x10000>; - ftrace-size = <0x10000>; - pmsg-size = <0x20000>; - }; - }; -}; - -&blsp1_uart2 { - status = "okay"; -}; - -&rpm_requests { - pm8994-regulators { - compatible = "qcom,rpm-pm8994-regulators"; - - vdd_l1-supply = <&pm8994_s1>; - vdd_l2_26_28-supply = <&pm8994_s3>; - vdd_l3_11-supply = <&pm8994_s3>; - vdd_l4_27_31-supply = <&pm8994_s3>; - vdd_l5_7-supply = <&pm8994_s3>; - vdd_l6_12_32-supply = <&pm8994_s5>; - vdd_l8_16_30-supply = <&vreg_vph_pwr>; - vdd_l9_10_18_22-supply = <&vreg_vph_pwr>; - vdd_l13_19_23_24-supply = <&vreg_vph_pwr>; - vdd_l14_15-supply = <&pm8994_s5>; - vdd_l17_29-supply = <&vreg_vph_pwr>; - vdd_l20_21-supply = <&vreg_vph_pwr>; - vdd_l25-supply = <&pm8994_s5>; - vdd_lvs1_2 = <&pm8994_s4>; - - pm8994_s1: s1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - }; - - pm8994_s2: s2 { - /* TODO */ - }; - - pm8994_s3: s3 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - pm8994_s4: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-allow-set-load; - regulator-system-load = <325000>; - }; - - pm8994_s5: s5 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - }; - - pm8994_s7: s7 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - pm8994_l1: l1 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - pm8994_l2: l2 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - }; - - pm8994_l3: l3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8994_l4: l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pm8994_l5: l5 { - /* TODO */ - }; - - pm8994_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l7: l7 { - /* TODO */ - }; - - pm8994_l8: l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l9: l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l10: l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l11: l11 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8994_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l13: l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8994_l14: l14 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8994_l15: l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l16: l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - pm8994_l17: l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - pm8994_l18: l18 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - pm8994_l19: l19 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l20: l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-always-on; - regulator-boot-on; - regulator-allow-set-load; - regulator-system-load = <570000>; - }; - - pm8994_l21: l21 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - pm8994_l22: l22 { - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - }; - - pm8994_l23: l23 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - pm8994_l24: l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3150000>; - }; - - pm8994_l25: l25 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l26: l26 { - /* TODO: value from downstream - regulator-min-microvolt = <987500>; - fails to apply */ - }; - - pm8994_l27: l27 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - pm8994_l28: l28 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - pm8994_l29: l29 { - /* TODO: Unsupported voltage range. - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - qcom,init-voltage = <2800000>; - */ - }; - - pm8994_l30: l30 { - /* TODO: get this verified - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,init-voltage = <1800000>; - */ - }; - - pm8994_l31: l31 { - regulator-min-microvolt = <1262500>; - regulator-max-microvolt = <1262500>; - }; - - pm8994_l32: l32 { - /* TODO: get this verified - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,init-voltage = <1800000>; - */ - }; - }; -}; - -&sdhc_1 { - status = "okay"; - - mmc-hs400-1_8v; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts b/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts deleted file mode 100644 index 3cc01f022..000000000 --- a/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, Konrad Dybcio - */ - -/dts-v1/; - -#include "msm8992.dtsi" -#include "pm8994.dtsi" -#include "pmi8994.dtsi" -#include -#include - -/ { - model = "Microsoft Lumia 950"; - compatible = "microsoft,talkman", "qcom,msm8992"; - - /* Most Lumia 950 users use GRUB to load their kernels, - * hence there is no need for msm-id and friends. - */ - - /* This enables graphical output via bootloader-enabled display. - * acpi=no is required due to WP platforms having ACPI support, but - * only for Windows-based OSes. - */ - chosen { - bootargs = "earlycon=efifb console=efifb acpi=no"; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - }; -}; - -&sdhc_1 { - status = "okay"; - - mmc-hs200-1_8v; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts deleted file mode 100644 index 4f64ca3ea..000000000 --- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +++ /dev/null @@ -1,364 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, Konrad Dybcio - */ - -/dts-v1/; - -#include "msm8992.dtsi" -#include "pm8994.dtsi" -#include "pmi8994.dtsi" -#include -#include - -/ { - model = "Xiaomi Mi 4C"; - compatible = "xiaomi,libra", "qcom,msm8992"; - /* required for bootloader to select correct board */ - qcom,msm-id = <251 0 252 0>; - qcom,pmic-id = <65545 65546 0 0>; - qcom,board-id = <12 0>; - - /* This enables graphical output via bootloader-enabled display */ - chosen { - bootargs = "earlycon=tty0 console=tty0"; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - framebuffer0: framebuffer@3404000 { - status= "okay"; - compatible = "simple-framebuffer"; - reg = <0 0x3404000 0 (1080 * 1920 * 3)>; - width = <1080>; - height = <1920>; - stride = <(1080 * 3)>; - format = "r8g8b8"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - input-name = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - button@0 { - label = "Volume Up"; - gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - wakeup-source; - debounce-interval = <15>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* This is for getting crash logs using Android downstream kernels */ - ramoops@dfc00000 { - compatible = "ramoops"; - reg = <0x0 0xdfc00000 0x0 0x40000>; - console-size = <0x10000>; - record-size = <0x10000>; - ftrace-size = <0x10000>; - pmsg-size = <0x20000>; - }; - - continuous_splash: framebuffer@3401000{ - reg = <0x0 0x3401000 0x0 0x2200000>; - no-map; - }; - - dfps_data_mem: dfps_data_mem@3400000 { - reg = <0x0 0x3400000 0x0 0x1000>; - no-map; - }; - - peripheral_region: peripheral_region@7400000 { - reg = <0x0 0x7400000 0x0 0x1c00000>; - no-map; - }; - - modem_region: modem_region@9000000 { - reg = <0x0 0x9000000 0x0 0x5a00000>; - no-map; - }; - - tzapp: modem_region@ea00000 { - reg = <0x0 0xea00000 0x0 0x1900000>; - no-map; - }; - }; -}; - -&blsp_i2c2 { - status = "okay"; - - /* Atmel or Synaptics touchscreen */ -}; - -&blsp_i2c5 { - status = "okay"; - - /* Silabs si4705 FM transmitter */ -}; - -&blsp_i2c6 { - status = "okay"; - - /* NCI NFC, - * TI USB320 Type-C controller, - * Pericom 30216a USB (de)mux switch - */ -}; - -&blsp_i2c7 { - status = "okay"; - - /* cm36686 proximity and ambient light sensor */ -}; - -&blsp_i2c13 { - status = "okay"; - - /* ST lsm6db0 gyro/accelerometer */ -}; - -&blsp2_uart2 { - status = "okay"; -}; - -&rpm_requests { - pm8994-regulators { - compatible = "qcom,rpm-pm8994-regulators"; - - vdd_l1-supply = <&pm8994_s7>; - vdd_l2_26_28-supply = <&pm8994_s3>; - vdd_l3_11-supply = <&pm8994_s3>; - vdd_l4_27_31-supply = <&pm8994_s3>; - vdd_l5_7-supply = <&pm8994_s3>; - vdd_l6_12_32-supply = <&pm8994_s5>; - vdd_l8_16_30-supply = <&vreg_vph_pwr>; - vdd_l9_10_18_22-supply = <&vreg_vph_pwr>; - vdd_l13_19_23_24-supply = <&vreg_vph_pwr>; - vdd_l14_15-supply = <&pm8994_s5>; - vdd_l17_29-supply = <&vreg_vph_pwr>; - vdd_l20_21-supply = <&vreg_vph_pwr>; - vdd_l25-supply = <&pm8994_s5>; - vdd_lvs1_2 = <&pm8994_s4>; - - pm8994_s1: s1 { - /* unused */ - status = "disabled"; - }; - - pm8994_s2: s2 { - /* unused */ - status = "disabled"; - }; - - pm8994_s3: s3 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - pm8994_s4: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-allow-set-load; - regulator-always-on; - regulator-system-load = <325000>; - }; - - pm8994_s5: s5 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - }; - - pm8994_s7: s7 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - pm8994_l1: l1 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - pm8994_l2: l2 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - }; - - pm8994_l3: l3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8994_l4: l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pm8994_l5: l5 { - /* unused */ - status = "disabled"; - }; - - pm8994_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l7: l7 { - /* unused */ - status = "disabled"; - }; - - pm8994_l8: l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l9: l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l10: l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l11: l11 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8994_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l13: l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8994_l14: l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l15: l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l16: l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - pm8994_l17: l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - pm8994_l18: l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - pm8994_l19: l19 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - pm8994_l20: l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-always-on; - regulator-boot-on; - regulator-allow-set-load; - regulator-system-load = <570000>; - }; - - pm8994_l21: l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-always-on; - }; - - pm8994_l22: l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - pm8994_l23: l23 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - pm8994_l24: l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3150000>; - }; - - pm8994_l25: l25 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - pm8994_l26: l26 { - regulator-min-microvolt = <987500>; - regulator-max-microvolt = <987500>; - - }; - - pm8994_l27: l27 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - pm8994_l28: l28 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - pm8994_l29: l29 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - pm8994_l30: l30 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8994_l31: l31 { - regulator-min-microvolt = <1262500>; - regulator-max-microvolt = <1262500>; - }; - - pm8994_l32: l32 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; -}; - -&sdhc_1 { - status = "okay"; - - mmc-hs400-1_8v; - vmmc-supply = <&pm8994_l20>; - vqmmc-supply = <&pm8994_s4>; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi deleted file mode 100644 index 8626b3a50..000000000 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ /dev/null @@ -1,619 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. - */ - -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - L2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CPU4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x100>; - next-level-cache = <&L2_1>; - enable-method = "psci"; - L2_1: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - CPU5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; - next-level-cache = <&L2_1>; - enable-method = "psci"; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU4>; - }; - - core1 { - cpu = <&CPU5>; - }; - }; - }; - }; - - clocks { - xo_board: xo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-msm8994", "qcom,scm"; - }; - }; - - memory { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "hvc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - smem_region: smem@6a00000 { - reg = <0x0 0x6a00000 0x0 0x200000>; - no-map; - }; - }; - - sfpb_mutex: hwmutex { - compatible = "qcom,sfpb-mutex"; - syscon = <&sfpb_mutex_regs 0x0 0x100>; - #hwlock-cells = <1>; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_region>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - hwlocks = <&sfpb_mutex 3>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - intc: interrupt-controller@f9000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xf9000000 0x1000>, - <0xf9002000 0x1000>; - }; - - apcs: mailbox@f900d000 { - compatible = "qcom,msm8994-apcs-kpss-global", "syscon"; - reg = <0xf900d000 0x2000>; - #mbox-cells = <1>; - }; - - timer@f9020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0xf9020000 0x1000>; - - frame@f9021000 { - frame-number = <0>; - interrupts = , - ; - reg = <0xf9021000 0x1000>, - <0xf9022000 0x1000>; - }; - - frame@f9023000 { - frame-number = <1>; - interrupts = ; - reg = <0xf9023000 0x1000>; - status = "disabled"; - }; - - frame@f9024000 { - frame-number = <2>; - interrupts = ; - reg = <0xf9024000 0x1000>; - status = "disabled"; - }; - - frame@f9025000 { - frame-number = <3>; - interrupts = ; - reg = <0xf9025000 0x1000>; - status = "disabled"; - }; - - frame@f9026000 { - frame-number = <4>; - interrupts = ; - reg = <0xf9026000 0x1000>; - status = "disabled"; - }; - - frame@f9027000 { - frame-number = <5>; - interrupts = ; - reg = <0xf9027000 0x1000>; - status = "disabled"; - }; - - frame@f9028000 { - frame-number = <6>; - interrupts = ; - reg = <0xf9028000 0x1000>; - status = "disabled"; - }; - }; - - sdhc_1: sdhci@f9824900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; - - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on - &sdc1_rclk_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off - &sdc1_rclk_off>; - - regulator-always-on; - bus-width = <8>; - non-removable; - - status = "disabled"; - }; - - blsp1_uart2: serial@f991e000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf991e000 0x1000>; - interrupts = ; - clock-names = "core", "iface"; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; - status = "disabled"; - }; - - blsp_i2c2: i2c@f9924000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0xf9924000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <400000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_default>; - pinctrl-1 = <&i2c2_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - /* Somebody was very creative with their numbering scheme downstream... */ - - blsp_i2c13: i2c@f9927000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0xf9927000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <400000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c13_default>; - pinctrl-1 = <&i2c13_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c6: i2c@f9928000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0xf9928000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <400000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c6_default>; - pinctrl-1 = <&i2c6_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_uart2: serial@f995e000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf995e000 0x1000>; - interrupts = ; - clock-names = "core", "iface"; - clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart2_default>; - pinctrl-1 = <&blsp2_uart2_sleep>; - status = "disabled"; - }; - - blsp_i2c7: i2c@f9963000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0xf9963000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <400000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c7_default>; - pinctrl-1 = <&i2c7_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c5: i2c@f9967000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0xf9967000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <100000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c5_default>; - pinctrl-1 = <&i2c5_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gcc: clock-controller@fc400000 { - compatible = "qcom,gcc-msm8994"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0xfc400000 0x2000>; - }; - - rpm_msg_ram: memory@fc428000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0xfc428000 0x4000>; - }; - - restart@fc4ab000 { - compatible = "qcom,pshold"; - reg = <0xfc4ab000 0x4>; - }; - - spmi_bus: spmi@fc4c0000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0xfc4cf000 0x1000>, - <0xfc4cb000 0x1000>, - <0xfc4ca000 0x1000>; - reg-names = "core", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - sfpb_mutex_regs: syscon@fd484000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "syscon"; - reg = <0xfd484000 0x400>; - }; - - tlmm: pinctrl@fd510000 { - compatible = "qcom,msm8994-pinctrl"; - reg = <0xfd510000 0x4000>; - interrupts = ; - gpio-controller; - gpio-ranges = <&tlmm 0 0 146>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - - blsp1_uart2_default: blsp1-uart2-default { - function = "blsp_uart2"; - pins = "gpio4", "gpio5"; - drive-strength = <16>; - bias-disable; - }; - - blsp1_uart2_sleep: blsp1-uart2-sleep { - function = "gpio"; - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-pull-down; - }; - - blsp2_uart2_default: blsp2-uart2-default { - function = "blsp_uart8"; - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - drive-strength = <16>; - bias-disable; - }; - - blsp2_uart2_sleep: blsp2-uart2-sleep { - function = "gpio"; - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - drive-strength = <2>; - bias-pull-down; - }; - - sdc1_clk_on: clk-on { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <6>; - }; - - sdc1_clk_off: clk-off { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <2>; - }; - - sdc1_cmd_on: cmd-on { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <6>; - }; - - sdc1_cmd_off: cmd-off { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - sdc1_data_on: data-on { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <6>; - }; - - sdc1_data_off: data-off { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <2>; - }; - - sdc1_rclk_on: rclk-on { - pins = "sdc1_rclk"; - bias-pull-down; - }; - - sdc1_rclk_off: rclk-off { - pins = "sdc1_rclk"; - bias-pull-down; - }; - - i2c2_default: i2c2-default { - function = "blsp_i2c2"; - pins = "gpio6", "gpio7"; - drive-strength = <2>; - bias-disable; - }; - - i2c2_sleep: i2c2-sleep { - function = "gpio"; - pins = "gpio6", "gpio7"; - drive-strength = <2>; - bias-disable; - }; - - i2c5_default: i2c5-default { - /* Don't be fooled! Nobody knows the reason why though... */ - function = "blsp_i2c11"; - pins = "gpio83", "gpio84"; - drive-strength = <2>; - bias-disable; - }; - - i2c5_sleep: i2c5-sleep { - function = "gpio"; - pins = "gpio83", "gpio84"; - drive-strength = <2>; - bias-disable; - }; - - i2c6_default: i2c6-default { - function = "blsp_i2c6"; - pins = "gpio28", "gpio27"; - drive-strength = <2>; - bias-disable; - }; - - i2c6_sleep: i2c6-sleep { - function = "gpio"; - pins = "gpio28", "gpio27"; - drive-strength = <2>; - bias-disable; - }; - - i2c7_default: i2c7-default { - function = "blsp_i2c7"; - pins = "gpio43", "gpio44"; - drive-strength = <2>; - bias-disable; - }; - - i2c7_sleep: i2c7-sleep { - function = "gpio"; - pins = "gpio43", "gpio44"; - drive-strength = <2>; - bias-disable; - }; - - i2c13_default: i2c13-default { - /* Not a typo either. */ - function = "blsp_i2c5"; - pins = "gpio23", "gpio24"; - drive-strength = <2>; - bias-disable; - }; - - i2c13_sleep: i2c13-sleep { - function = "gpio"; - pins = "gpio23", "gpio24"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - - smd_rpm: smd { - compatible = "qcom,smd"; - rpm { - interrupts = ; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - qcom,local-pid = <0>; - qcom,remote-pid = <6>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8994"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: rpmcc { - compatible = "qcom,rpmcc-msm8992"; - #clock-cells = <1>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - vreg_vph_pwr: vreg-vph-pwr { - compatible = "regulator-fixed"; - status = "okay"; - regulator-name = "vph-pwr"; - - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - - regulator-always-on; - }; -}; - diff --git a/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts deleted file mode 100644 index ffe1a9bd8..000000000 --- a/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2015, Huawei Inc. All rights reserved. - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include "msm8994.dtsi" - -/ { - model = "Huawei Nexus 6P"; - compatible = "huawei,angler", "qcom,msm8994"; - /* required for bootloader to select correct board */ - qcom,msm-id = <207 0x20000>; - qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>; - qcom,board-id = <8026 0>; - - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - serial@f991e000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; - }; - }; -}; - -&tlmm { - gpio-reserved-ranges = <85 4>; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dts b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dts deleted file mode 100644 index 5d6bbbf6c..000000000 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, Konrad Dybcio - */ - -/dts-v1/; - -#include "msm8994-sony-xperia-kitakami.dtsi" - -/ { - model = "Sony Xperia Z5"; - compatible = "sony,sumire-row", "qcom,msm8994"; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi deleted file mode 100644 index 791f254ac..000000000 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ /dev/null @@ -1,240 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, Konrad Dybcio - */ - -#include "msm8994.dtsi" -#include "pm8994.dtsi" -#include "pmi8994.dtsi" -#include -#include - -/ { - /* required for bootloader to select correct board */ - qcom,msm-id = <0xcf 0x20001>; - qcom,pmic-id = <0x10009 0x1000a 0x00 0x00>; - qcom,board-id = <8 0>; - - /* Kitakami firmware doesn't support PSCI */ - /delete-node/ psci; - - gpio_keys { - compatible = "gpio-keys"; - input-name = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - button@0 { - label = "Volume Down"; - gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - wakeup-source; - debounce-interval = <15>; - }; - - button@1 { - label = "Volume Up"; - gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - wakeup-source; - debounce-interval = <15>; - }; - - button@2 { - label = "Camera Snapshot"; - gpios = <&pm8994_gpios 4 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - wakeup-source; - debounce-interval = <15>; - }; - - button@3 { - label = "Camera Focus"; - gpios = <&pm8994_gpios 5 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - wakeup-source; - debounce-interval = <15>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* This is for getting crash logs using Android downstream kernels */ - ramoops@1fe00000 { - compatible = "ramoops"; - reg = <0x0 0x1fe00000 0x0 0x200000>; - console-size = <0x100000>; - record-size = <0x10000>; - ftrace-size = <0x10000>; - pmsg-size = <0x80000>; - }; - - continuous_splash: framebuffer@3401000{ - reg = <0x0 0x3401000 0x0 0x2200000>; - no-map; - }; - - dfps_data_mem: dfps_data_mem@3400000 { - reg = <0x0 0x3400000 0x0 0x1000>; - no-map; - }; - - peripheral_region: peripheral_region@7400000 { - reg = <0x0 0x7400000 0x0 0x1c00000>; - no-map; - }; - - modem_region: modem_region@9000000 { - reg = <0x0 0x9000000 0x0 0x5a00000>; - no-map; - }; - - tzapp: modem_region@ea00000 { - reg = <0x0 0xea00000 0x0 0x1900000>; - no-map; - }; - - fb_region: fb_region@40000000 { - reg = <0x00 0x40000000 0x00 0x1000000>; - no-map; - }; - }; -}; - -&blsp_spi0 { - status = "okay"; - - /* FPC fingerprint reader */ -}; - -/* I2C1 is disabled on this board */ - -&blsp_i2c2 { - status = "okay"; - - /* NXP NFC */ -}; - -&blsp_i2c4 { - status = "okay"; - - /* Empty but active */ -}; - -&blsp_i2c5 { - status = "okay"; - - /* SMB1357 charger and sii8620 HDMI/MHL bridge */ -}; - -&blsp_i2c6 { - status = "okay"; - - /* Synaptics touchscreen */ -}; - -&blsp1_uart2 { - status = "okay"; -}; - -&blsp2_uart2 { - status = "okay"; -}; - -&rpm_requests { - pm8994_regulators: pm8994-regulators { - compatible = "qcom,rpm-pm8994-regulators"; - vdd_l1-supply = <&pm8994_s1>; - vdd_l2_26_28-supply = <&pm8994_s3>; - vdd_l3_11-supply = <&pm8994_s3>; - vdd_l4_27_31-supply = <&pm8994_s3>; - vdd_l5_7-supply = <&pm8994_s3>; - vdd_l6_12_32-supply = <&pm8994_s5>; - vdd_l8_16_30-supply = <&vreg_vph_pwr>; - vdd_l9_10_18_22-supply = <&vreg_vph_pwr>; - vdd_l13_19_23_24-supply = <&vreg_vph_pwr>; - vdd_l14_15-supply = <&pm8994_s5>; - vdd_l17_29-supply = <&vreg_vph_pwr>; - vdd_l20_21-supply = <&vreg_vph_pwr>; - vdd_l25-supply = <&pm8994_s5>; - vdd_lvs1_2 = <&pm8994_s4>; - - pm8994_s1: s1 {}; - pm8994_s2: s2 {}; - pm8994_s3: s3 {}; - pm8994_s4: s4 {}; - pm8994_s5: s5 {}; - pm8994_s6: s6 {}; - pm8994_s7: s7 {}; - - pm8994_l1: l1 {}; - pm8994_l2: l2 {}; - pm8994_l3: l3 {}; - pm8994_l4: l4 {}; - pm8994_l6: l6 {}; - pm8994_l8: l8 {}; - pm8994_l9: l9 {}; - pm8994_l10: l10 {}; - pm8994_l11: l11 {}; - pm8994_l12: l12 {}; - pm8994_l13: l13 {}; - pm8994_l14: l14 {}; - pm8994_l15: l15 {}; - pm8994_l16: l16 {}; - pm8994_l17: l17 {}; - pm8994_l18: l18 {}; - pm8994_l19: l19 {}; - pm8994_l20: l20 {}; - pm8994_l21: l21 {}; - pm8994_l22: l22 {}; - pm8994_l23: l23 {}; - pm8994_l24: l24 {}; - pm8994_l25: l25 {}; - pm8994_l26: l26 {}; - pm8994_l27: l27 {}; - pm8994_l28: l28 {}; - pm8994_l29: l29 {}; - pm8994_l30: l30 {}; - pm8994_l31: l31 {}; - pm8994_l32: l32 {}; - - pm8994_lvs1: lvs1 {}; - pm8994_lvs2: lvs2 {}; - }; - - pmi8994_regulators: pmi8994-regulators { - compatible = "qcom,rpm-pmi8994-regulators"; - - pmi8994_s1: s1 {}; - pmi8994_s2: s2 {}; - pmi8994_s3: s3 {}; - pmi8994_bby: boost-bypass {}; - }; -}; - -&sdhc1 { - /* There is an issue with the eMMC causing permanent - * damage to the card if a quirk isn't addressed. - * Until it's fixed, disable the MMC so as not to brick - * devices. - */ - status = "disabled"; - - /* Downstream pushes 2.95V to the sdhci device, - * but upstream driver REALLY wants to make vmmc 1.8v - * cause of the hs400-1_8v mode. MMC works fine without - * that regulator, so let's not use it for now. - * vqmmc is also disabled cause driver stll complains. - * - * vmmc-supply = <&pm8994_l20>; - * vqmmc-supply = <&pm8994_s4>; - */ -}; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi deleted file mode 100644 index 297408b94..000000000 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ /dev/null @@ -1,715 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. - */ - -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "xo_board"; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "sleep_clk"; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - L2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; - - CPU4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&L2_1>; - L2_1: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - CPU5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; - enable-method = "psci"; - next-level-cache = <&L2_1>; - }; - - CPU6: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; - enable-method = "psci"; - next-level-cache = <&L2_1>; - }; - - CPU7: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; - enable-method = "psci"; - next-level-cache = <&L2_1>; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU4>; - }; - - core1 { - cpu = <&CPU5>; - }; - - core2 { - cpu = <&CPU6>; - }; - - core3 { - cpu = <&CPU7>; - }; - }; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-msm8994", "qcom,scm"; - }; - }; - - memory { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "hvc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - smem_mem: smem_region@6a00000 { - reg = <0x0 0x6a00000 0x0 0x200000>; - no-map; - }; - }; - - smd { - compatible = "qcom,smd"; - rpm { - interrupts = ; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - qcom,local-pid = <0>; - qcom,remote-pid = <6>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8994"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: rpmcc { - compatible = "qcom,rpmcc-msm8994"; - #clock-cells = <1>; - }; - }; - }; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - hwlocks = <&tcsr_mutex 3>; - }; - - soc: soc { - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - intc: interrupt-controller@f9000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xf9000000 0x1000>, - <0xf9002000 0x1000>; - }; - - apcs: mailbox@f900d000 { - compatible = "qcom,msm8994-apcs-kpss-global", "syscon"; - reg = <0xf900d000 0x2000>; - #mbox-cells = <1>; - }; - - timer@f9020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0xf9020000 0x1000>; - - frame@f9021000 { - frame-number = <0>; - interrupts = , - ; - reg = <0xf9021000 0x1000>, - <0xf9022000 0x1000>; - }; - - frame@f9023000 { - frame-number = <1>; - interrupts = ; - reg = <0xf9023000 0x1000>; - status = "disabled"; - }; - - frame@f9024000 { - frame-number = <2>; - interrupts = ; - reg = <0xf9024000 0x1000>; - status = "disabled"; - }; - - frame@f9025000 { - frame-number = <3>; - interrupts = ; - reg = <0xf9025000 0x1000>; - status = "disabled"; - }; - - frame@f9026000 { - frame-number = <4>; - interrupts = ; - reg = <0xf9026000 0x1000>; - status = "disabled"; - }; - - frame@f9027000 { - frame-number = <5>; - interrupts = ; - reg = <0xf9027000 0x1000>; - status = "disabled"; - }; - - frame@f9028000 { - frame-number = <6>; - interrupts = ; - reg = <0xf9028000 0x1000>; - status = "disabled"; - }; - }; - - sdhc1: sdhci@f9824900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; - - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; - - bus-width = <8>; - non-removable; - status = "disabled"; - }; - - blsp1_dma: dma@f9904000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0xf9904000 0x19000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - qcom,controlled-remotely; - num-channels = <24>; - qcom,num-ees = <4>; - }; - - blsp1_uart2: serial@f991e000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf991e000 0x1000>; - interrupts = ; - clock-names = "core", "iface"; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; - status = "disabled"; - }; - - blsp_i2c1: i2c@f9923000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0xf9923000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <400000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c1_default>; - pinctrl-1 = <&i2c1_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_spi0: spi@f9923000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0xf9923000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - spi-max-frequency = <19200000>; - dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_spi0_default>; - pinctrl-1 = <&blsp1_spi0_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c2: i2c@f9924000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0xf9924000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <355000>; - dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_default>; - pinctrl-1 = <&i2c2_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - /* I2C3 doesn't exist */ - - blsp_i2c4: i2c@f9926000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0xf9926000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <355000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c4_default>; - pinctrl-1 = <&i2c4_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_dma: dma@f9944000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0xf9944000 0x19000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - qcom,controlled-remotely; - num-channels = <24>; - qcom,num-ees = <4>; - }; - - /* According to downstream kernels, i2c6 - * comes before i2c5 address-wise... - */ - - blsp_i2c6: i2c@f9928000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0xf9928000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <355000>; - dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c6_default>; - pinctrl-1 = <&i2c6_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_uart2: serial@f995e000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf995e000 0x1000>; - interrupts = ; - clock-names = "core", "iface"; - clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - dmas = <&blsp2_dma 2>, <&blsp2_dma 3>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart2_default>; - pinctrl-1 = <&blsp2_uart2_sleep>; - status = "disabled"; - }; - - blsp_i2c5: i2c@f9967000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0xf9967000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <355000>; - dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c5_default>; - pinctrl-1 = <&i2c5_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gcc: clock-controller@fc400000 { - compatible = "qcom,gcc-msm8994"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0xfc400000 0x2000>; - }; - - rpm_msg_ram: memory@fc428000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0xfc428000 0x4000>; - }; - - restart@fc4ab000 { - compatible = "qcom,pshold"; - reg = <0xfc4ab000 0x4>; - }; - - spmi_bus: spmi@fc4c0000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0xfc4cf000 0x1000>, - <0xfc4cb000 0x1000>, - <0xfc4ca000 0x1000>; - reg-names = "core", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - tcsr_mutex_regs: syscon@fd484000 { - compatible = "syscon"; - reg = <0xfd484000 0x2000>; - }; - - tlmm: pinctrl@fd510000 { - compatible = "qcom,msm8994-pinctrl"; - reg = <0xfd510000 0x4000>; - interrupts = ; - gpio-controller; - gpio-ranges = <&tlmm 0 0 146>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - - blsp1_uart2_default: blsp1-uart2-default { - function = "blsp_uart2"; - pins = "gpio4", "gpio5"; - drive-strength = <16>; - bias-disable; - }; - - blsp1_uart2_sleep: blsp1-uart2-sleep { - function = "gpio"; - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-pull-down; - }; - - blsp2_uart2_default: blsp2-uart2-default { - function = "blsp_uart8"; - pins = "gpio45", "gpio46"; - drive-strength = <2>; - bias-disable; - }; - - blsp2_uart2_sleep: blsp2-uart2-sleep { - function = "gpio"; - pins = "gpio45", "gpio46"; - drive-strength = <2>; - bias-pull-down; - }; - - i2c1_default: i2c1-default { - function = "blsp_i2c1"; - pins = "gpio2", "gpio3"; - drive-strength = <2>; - bias-disable; - }; - - i2c1_sleep: i2c1-sleep { - function = "gpio"; - pins = "gpio2", "gpio3"; - drive-strength = <2>; - bias-disable; - }; - - i2c2_default: i2c2-default { - function = "blsp_i2c2"; - pins = "gpio6", "gpio7"; - drive-strength = <2>; - bias-disable; - }; - - i2c2_sleep: i2c2-sleep { - function = "gpio"; - pins = "gpio6", "gpio7"; - drive-strength = <2>; - bias-disable; - }; - - i2c4_default: i2c4-default { - function = "blsp_i2c4"; - pins = "gpio19", "gpio20"; - drive-strength = <2>; - bias-disable; - }; - - i2c4_sleep: i2c4-sleep { - function = "gpio"; - pins = "gpio19", "gpio20"; - drive-strength = <2>; - bias-pull-down; - input-enable; - }; - - i2c5_default: i2c5-default { - function = "blsp_i2c5"; - pins = "gpio23", "gpio24"; - drive-strength = <2>; - bias-disable; - }; - - i2c5_sleep: i2c5-sleep { - function = "gpio"; - pins = "gpio23", "gpio24"; - drive-strength = <2>; - bias-disable; - }; - - i2c6_default: i2c6-default { - function = "blsp_i2c6"; - pins = "gpio28", "gpio27"; - drive-strength = <2>; - bias-disable; - }; - - i2c6_sleep: i2c6-sleep { - function = "gpio"; - pins = "gpio28", "gpio27"; - drive-strength = <2>; - bias-disable; - }; - - blsp1_spi0_default: blsp1-spi0-default { - default { - function = "blsp_spi1"; - pins = "gpio0", "gpio1", "gpio3"; - drive-strength = <10>; - bias-pull-down; - }; - cs { - function = "gpio"; - pins = "gpio8"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp1_spi0_sleep: blsp1-spi0-sleep { - pins = "gpio0", "gpio1", "gpio3"; - drive-strength = <2>; - bias-disable; - }; - - sdc1_clk_on: clk-on { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <16>; - }; - - sdc1_clk_off: clk-off { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <2>; - }; - - sdc1_cmd_on: cmd-on { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <8>; - }; - - sdc1_cmd_off: cmd-off { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - sdc1_data_on: data-on { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <8>; - }; - - sdc1_data_off: data-off { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <2>; - }; - - sdc1_rclk_on: rclk-on { - pins = "sdc1_rclk"; - bias-pull-down; - }; - - sdc1_rclk_off: rclk-off { - pins = "sdc1_rclk"; - bias-pull-down; - }; - }; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x80>; - #hwlock-cells = <1>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - vreg_vph_pwr: vreg-vph-pwr { - compatible = "regulator-fixed"; - regulator-name = "vph-pwr"; - - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - - regulator-always-on; - }; -}; - diff --git a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts deleted file mode 100644 index 45ed594c1..000000000 --- a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include "msm8996-mtp.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM 8996 MTP"; - compatible = "qcom,msm8996-mtp"; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi deleted file mode 100644 index 5f46a1427..000000000 --- a/arch/arm64/boot/dts/qcom/msm8996-mtp.dtsi +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. - */ - -#include "msm8996.dtsi" - -/ { - aliases { - serial0 = &blsp2_uart1; - }; - - chosen { - stdout-path = "serial0"; - }; - - soc { - serial@75b0000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi deleted file mode 100644 index ac1ede579..000000000 --- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi +++ /dev/null @@ -1,653 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. - */ - -&msmgpio { - - wcd9xxx_intr { - wcd_intr_default: wcd_intr_default{ - mux { - pins = "gpio54"; - function = "gpio"; - }; - - config { - pins = "gpio54"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* pull down */ - input-enable; - }; - }; - }; - - cdc_reset_ctrl { - cdc_reset_sleep: cdc_reset_sleep { - mux { - pins = "gpio64"; - function = "gpio"; - }; - config { - pins = "gpio64"; - drive-strength = <16>; - bias-disable; - output-low; - }; - }; - cdc_reset_active:cdc_reset_active { - mux { - pins = "gpio64"; - function = "gpio"; - }; - config { - pins = "gpio64"; - drive-strength = <16>; - bias-pull-down; - output-high; - }; - }; - }; - - blsp1_spi0_default: blsp1_spi0_default { - pinmux { - function = "blsp_spi1"; - pins = "gpio0", "gpio1", "gpio3"; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio2"; - }; - pinconf { - pins = "gpio0", "gpio1", "gpio3"; - drive-strength = <12>; - bias-disable; - }; - pinconf_cs { - pins = "gpio2"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - blsp1_spi0_sleep: blsp1_spi0_sleep { - pinmux { - function = "gpio"; - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - }; - pinconf { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - blsp1_i2c2_default: blsp1_i2c2_default { - pinmux { - function = "blsp_i2c3"; - pins = "gpio47", "gpio48"; - }; - pinconf { - pins = "gpio47", "gpio48"; - drive-strength = <16>; - bias-disable = <0>; - }; - }; - - blsp1_i2c2_sleep: blsp1_i2c2_sleep { - pinmux { - function = "gpio"; - pins = "gpio47", "gpio48"; - }; - pinconf { - pins = "gpio47", "gpio48"; - drive-strength = <2>; - bias-disable = <0>; - }; - }; - - blsp2_i2c0_default: blsp2_i2c0 { - pinmux { - function = "blsp_i2c7"; - pins = "gpio55", "gpio56"; - }; - pinconf { - pins = "gpio55", "gpio56"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_i2c0_sleep: blsp2_i2c0_sleep { - pinmux { - function = "gpio"; - pins = "gpio55", "gpio56"; - }; - pinconf { - pins = "gpio55", "gpio56"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_uart1_2pins_default: blsp2_uart1_2pins { - pinmux { - function = "blsp_uart8"; - pins = "gpio4", "gpio5"; - }; - pinconf { - pins = "gpio4", "gpio5"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_uart1_2pins_sleep: blsp2_uart1_2pins_sleep { - pinmux { - function = "gpio"; - pins = "gpio4", "gpio5"; - }; - pinconf { - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_uart1_4pins_default: blsp2_uart1_4pins { - pinmux { - function = "blsp_uart8"; - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - }; - - pinconf { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_uart1_4pins_sleep: blsp2_uart1_4pins_sleep { - pinmux { - function = "gpio"; - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - }; - - pinconf { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_i2c1_default: blsp2_i2c1 { - pinmux { - function = "blsp_i2c8"; - pins = "gpio6", "gpio7"; - }; - pinconf { - pins = "gpio6", "gpio7"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_i2c1_sleep: blsp2_i2c1_sleep { - pinmux { - function = "gpio"; - pins = "gpio6", "gpio7"; - }; - pinconf { - pins = "gpio6", "gpio7"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_uart2_2pins_default: blsp2_uart2_2pins { - pinmux { - function = "blsp_uart9"; - pins = "gpio49", "gpio50"; - }; - pinconf { - pins = "gpio49", "gpio50"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_uart2_2pins_sleep: blsp2_uart2_2pins_sleep { - pinmux { - function = "gpio"; - pins = "gpio49", "gpio50"; - }; - pinconf { - pins = "gpio49", "gpio50"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_uart2_4pins_default: blsp2_uart2_4pins { - pinmux { - function = "blsp_uart9"; - pins = "gpio49", "gpio50", "gpio51", "gpio52"; - }; - - pinconf { - pins = "gpio49", "gpio50", "gpio51", "gpio52"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp2_uart2_4pins_sleep: blsp2_uart2_4pins_sleep { - pinmux { - function = "gpio"; - pins = "gpio49", "gpio50", "gpio51", "gpio52"; - }; - - pinconf { - pins = "gpio49", "gpio50", "gpio51", "gpio52"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_spi5_default: blsp2_spi5_default { - pinmux { - function = "blsp_spi12"; - pins = "gpio85", "gpio86", "gpio88"; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio87"; - }; - pinconf { - pins = "gpio85", "gpio86", "gpio88"; - drive-strength = <12>; - bias-disable; - }; - pinconf_cs { - pins = "gpio87"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - blsp2_spi5_sleep: blsp2_spi5_sleep { - pinmux { - function = "gpio"; - pins = "gpio85", "gpio86", "gpio87", "gpio88"; - }; - pinconf { - pins = "gpio85", "gpio86", "gpio87", "gpio88"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - sdc2_clk_on: sdc2_clk_on { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_clk_off: sdc2_clk_off { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc2_cmd_on: sdc2_cmd_on { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <10>; /* 10 MA */ - }; - }; - - sdc2_cmd_off: sdc2_cmd_off { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc2_data_on: sdc2_data_on { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <10>; /* 10 MA */ - }; - }; - - sdc2_data_off: sdc2_data_off { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - pcie0_clkreq_default: pcie0_clkreq_default { - mux { - pins = "gpio36"; - function = "pci_e0"; - }; - - config { - pins = "gpio36"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie0_perst_default: pcie0_perst_default { - mux { - pins = "gpio35"; - function = "gpio"; - }; - - config { - pins = "gpio35"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - pcie0_wake_default: pcie0_wake_default { - mux { - pins = "gpio37"; - function = "gpio"; - }; - - config { - pins = "gpio37"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie0_clkreq_sleep: pcie0_clkreq_sleep { - mux { - pins = "gpio36"; - function = "gpio"; - }; - - config { - pins = "gpio36"; - drive-strength = <2>; - bias-disable; - }; - }; - - pcie0_wake_sleep: pcie0_wake_sleep { - mux { - pins = "gpio37"; - function = "gpio"; - }; - - config { - pins = "gpio37"; - drive-strength = <2>; - bias-disable; - }; - }; - - pcie1_clkreq_default: pcie1_clkreq_default { - mux { - pins = "gpio131"; - function = "pci_e1"; - }; - - config { - pins = "gpio131"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie1_perst_default: pcie1_perst_default { - mux { - pins = "gpio130"; - function = "gpio"; - }; - - config { - pins = "gpio130"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - pcie1_wake_default: pcie1_wake_default { - mux { - pins = "gpio132"; - function = "gpio"; - }; - - config { - pins = "gpio132"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - pcie1_clkreq_sleep: pcie1_clkreq_sleep { - mux { - pins = "gpio131"; - function = "gpio"; - }; - - config { - pins = "gpio131"; - drive-strength = <2>; - bias-disable; - }; - }; - - pcie1_wake_sleep: pcie1_wake_sleep { - mux { - pins = "gpio132"; - function = "gpio"; - }; - - config { - pins = "gpio132"; - drive-strength = <2>; - bias-disable; - }; - }; - - pcie2_clkreq_default: pcie2_clkreq_default { - mux { - pins = "gpio115"; - function = "pci_e2"; - }; - - config { - pins = "gpio115"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie2_perst_default: pcie2_perst_default { - mux { - pins = "gpio114"; - function = "gpio"; - }; - - config { - pins = "gpio114"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - pcie2_wake_default: pcie2_wake_default { - mux { - pins = "gpio116"; - function = "gpio"; - }; - - config { - pins = "gpio116"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - pcie2_clkreq_sleep: pcie2_clkreq_sleep { - mux { - pins = "gpio115"; - function = "gpio"; - }; - - config { - pins = "gpio115"; - drive-strength = <2>; - bias-disable; - }; - }; - - pcie2_wake_sleep: pcie2_wake_sleep { - mux { - pins = "gpio116"; - function = "gpio"; - }; - - config { - pins = "gpio116"; - drive-strength = <2>; - bias-disable; - }; - }; - - cci0_default: cci0_default { - pinmux { - function = "cci_i2c"; - pins = "gpio17", "gpio18"; - }; - pinconf { - pins = "gpio17", "gpio18"; - drive-strength = <16>; - bias-disable; - }; - }; - - cci1_default: cci1_default { - pinmux { - function = "cci_i2c"; - pins = "gpio19", "gpio20"; - }; - pinconf { - pins = "gpio19", "gpio20"; - drive-strength = <16>; - bias-disable; - }; - }; - - camera_board_default: camera_board_default { - mux_pwdn { - function = "gpio"; - pins = "gpio98"; - }; - config_pwdn { - pins = "gpio98"; - drive-strength = <16>; - bias-disable; - }; - - mux_rst { - function = "gpio"; - pins = "gpio104"; - }; - config_rst { - pins = "gpio104"; - drive-strength = <16>; - bias-disable; - }; - - mux_mclk1 { - function = "cam_mclk"; - pins = "gpio14"; - }; - config_mclk1 { - pins = "gpio14"; - drive-strength = <16>; - bias-disable; - }; - }; - - camera_front_default: camera_front_default { - mux_pwdn { - function = "gpio"; - pins = "gpio133"; - }; - config_pwdn { - pins = "gpio133"; - drive-strength = <16>; - bias-disable; - }; - - mux_rst { - function = "gpio"; - pins = "gpio23"; - }; - config_rst { - pins = "gpio23"; - drive-strength = <16>; - bias-disable; - }; - - mux_mclk2 { - function = "cam_mclk"; - pins = "gpio15"; - }; - config_mclk2 { - pins = "gpio15"; - drive-strength = <16>; - bias-disable; - }; - }; - - camera_rear_default: camera_rear_default { - mux_pwdn { - function = "gpio"; - pins = "gpio26"; - }; - config_pwdn { - pins = "gpio26"; - drive-strength = <16>; - bias-disable; - }; - - mux_rst { - function = "gpio"; - pins = "gpio25"; - }; - config_rst { - pins = "gpio25"; - drive-strength = <16>; - bias-disable; - }; - - mux_mclk0 { - function = "cam_mclk"; - pins = "gpio13"; - }; - config_mclk0 { - pins = "gpio13"; - drive-strength = <16>; - bias-disable; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi deleted file mode 100644 index ef5d03a15..000000000 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ /dev/null @@ -1,2454 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. - */ - -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "xo_board"; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; - clock-output-names = "sleep_clk"; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo"; - reg = <0x0 0x0>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - capacity-dmips-mhz = <1024>; - next-level-cache = <&L2_0>; - L2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "qcom,kryo"; - reg = <0x0 0x1>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - capacity-dmips-mhz = <1024>; - next-level-cache = <&L2_0>; - }; - - CPU2: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo"; - reg = <0x0 0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - capacity-dmips-mhz = <1024>; - next-level-cache = <&L2_1>; - L2_1: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - CPU3: cpu@101 { - device_type = "cpu"; - compatible = "qcom,kryo"; - reg = <0x0 0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - capacity-dmips-mhz = <1024>; - next-level-cache = <&L2_1>; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU2>; - }; - - core1 { - cpu = <&CPU3>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - idle-state-name = "standalone-power-collapse"; - arm,psci-suspend-param = <0x00000004>; - entry-latency-us = <130>; - exit-latency-us = <80>; - min-residency-us = <300>; - }; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-msm8996"; - qcom,dload-mode = <&tcsr 0x13000>; - }; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - - memory { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - mba_region: mba@91500000 { - reg = <0x0 0x91500000 0x0 0x200000>; - no-map; - }; - - slpi_region: slpi@90b00000 { - reg = <0x0 0x90b00000 0x0 0xa00000>; - no-map; - }; - - venus_region: venus@90400000 { - reg = <0x0 0x90400000 0x0 0x700000>; - no-map; - }; - - adsp_region: adsp@8ea00000 { - reg = <0x0 0x8ea00000 0x0 0x1a00000>; - no-map; - }; - - mpss_region: mpss@88800000 { - reg = <0x0 0x88800000 0x0 0x6200000>; - no-map; - }; - - smem_mem: smem-mem@86000000 { - reg = <0x0 0x86000000 0x0 0x200000>; - no-map; - }; - - memory@85800000 { - reg = <0x0 0x85800000 0x0 0x800000>; - no-map; - }; - - memory@86200000 { - reg = <0x0 0x86200000 0x0 0x2600000>; - no-map; - }; - - rmtfs@86700000 { - compatible = "qcom,rmtfs-mem"; - - size = <0x0 0x200000>; - alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - zap_shader_region: gpu@8f200000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x90b00000 0x0 0xa00000>; - no-map; - }; - }; - - rpm-glink { - compatible = "qcom,glink-rpm"; - - interrupts = ; - - qcom,rpm-msg-ram = <&rpm_msg_ram>; - - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8996"; - qcom,glink-channels = "rpm_requests"; - - rpmcc: qcom,rpmcc { - compatible = "qcom,rpmcc-msm8996"; - #clock-cells = <1>; - }; - - rpmpd: power-controller { - compatible = "qcom,msm8996-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp1: opp1 { - opp-level = <1>; - }; - - rpmpd_opp2: opp2 { - opp-level = <2>; - }; - - rpmpd_opp3: opp3 { - opp-level = <3>; - }; - - rpmpd_opp4: opp4 { - opp-level = <4>; - }; - - rpmpd_opp5: opp5 { - opp-level = <5>; - }; - - rpmpd_opp6: opp6 { - opp-level = <6>; - }; - }; - }; - }; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-adsp { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - - interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; - - mboxes = <&apcs_glb 10>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - smp2p_adsp_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_adsp_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-modem { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - - interrupts = ; - - mboxes = <&apcs_glb 14>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - - interrupts = ; - - mboxes = <&apcs_glb 26>; - - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - smp2p_slpi_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - smp2p_slpi_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - pcie_phy: phy@34000 { - compatible = "qcom,msm8996-qmp-pcie-phy"; - reg = <0x00034000 0x488>; - #clock-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, - <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, - <&gcc GCC_PCIE_CLKREF_CLK>; - clock-names = "aux", "cfg_ahb", "ref"; - - resets = <&gcc GCC_PCIE_PHY_BCR>, - <&gcc GCC_PCIE_PHY_COM_BCR>, - <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; - reset-names = "phy", "common", "cfg"; - status = "disabled"; - - pciephy_0: lane@35000 { - reg = <0x00035000 0x130>, - <0x00035200 0x200>, - <0x00035400 0x1dc>; - #phy-cells = <0>; - - clock-output-names = "pcie_0_pipe_clk_src"; - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "pipe0"; - resets = <&gcc GCC_PCIE_0_PHY_BCR>; - reset-names = "lane0"; - }; - - pciephy_1: lane@36000 { - reg = <0x00036000 0x130>, - <0x00036200 0x200>, - <0x00036400 0x1dc>; - #phy-cells = <0>; - - clock-output-names = "pcie_1_pipe_clk_src"; - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; - clock-names = "pipe1"; - resets = <&gcc GCC_PCIE_1_PHY_BCR>; - reset-names = "lane1"; - }; - - pciephy_2: lane@37000 { - reg = <0x00037000 0x130>, - <0x00037200 0x200>, - <0x00037400 0x1dc>; - #phy-cells = <0>; - - clock-output-names = "pcie_2_pipe_clk_src"; - clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; - clock-names = "pipe2"; - resets = <&gcc GCC_PCIE_2_PHY_BCR>; - reset-names = "lane2"; - }; - }; - - rpm_msg_ram: memory@68000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0x00068000 0x6000>; - }; - - qfprom@74000 { - compatible = "qcom,qfprom"; - reg = <0x00074000 0x8ff>; - #address-cells = <1>; - #size-cells = <1>; - - qusb2p_hstx_trim: hstx_trim@24e { - reg = <0x24e 0x2>; - bits = <5 4>; - }; - - qusb2s_hstx_trim: hstx_trim@24f { - reg = <0x24f 0x1>; - bits = <1 4>; - }; - - gpu_speed_bin: gpu_speed_bin@133 { - reg = <0x133 0x1>; - bits = <5 3>; - }; - }; - - rng: rng@83000 { - compatible = "qcom,prng-ee"; - reg = <0x00083000 0x1000>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; - - gcc: clock-controller@300000 { - compatible = "qcom,gcc-msm8996"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0x00300000 0x90000>; - - clocks = <&rpmcc RPM_SMD_LN_BB_CLK>; - clock-names = "cxo2"; - }; - - tsens0: thermal-sensor@4a9000 { - compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; - reg = <0x004a9000 0x1000>, /* TM */ - <0x004a8000 0x1000>; /* SROT */ - #qcom,sensors = <13>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@4ad000 { - compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; - reg = <0x004ad000 0x1000>, /* TM */ - <0x004ac000 0x1000>; /* SROT */ - #qcom,sensors = <8>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tcsr_mutex_regs: syscon@740000 { - compatible = "syscon"; - reg = <0x00740000 0x20000>; - }; - - tcsr: syscon@7a0000 { - compatible = "qcom,tcsr-msm8996", "syscon"; - reg = <0x007a0000 0x18000>; - }; - - mmcc: clock-controller@8c0000 { - compatible = "qcom,mmcc-msm8996"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0x008c0000 0x40000>; - assigned-clocks = <&mmcc MMPLL9_PLL>, - <&mmcc MMPLL1_PLL>, - <&mmcc MMPLL3_PLL>, - <&mmcc MMPLL4_PLL>, - <&mmcc MMPLL5_PLL>; - assigned-clock-rates = <624000000>, - <810000000>, - <980000000>, - <960000000>, - <825000000>; - }; - - mdss: mdss@900000 { - compatible = "qcom,mdss"; - - reg = <0x00900000 0x1000>, - <0x009b0000 0x1040>, - <0x009b8000 0x1040>; - reg-names = "mdss_phys", - "vbif_phys", - "vbif_nrt_phys"; - - power-domains = <&mmcc MDSS_GDSC>; - interrupts = ; - - interrupt-controller; - #interrupt-cells = <1>; - - clocks = <&mmcc MDSS_AHB_CLK>; - clock-names = "iface"; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mdp: mdp@901000 { - compatible = "qcom,mdp5"; - reg = <0x00901000 0x90000>; - reg-names = "mdp_phys"; - - interrupt-parent = <&mdss>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_MDP_CLK>, - <&mmcc SMMU_MDP_AXI_CLK>, - <&mmcc MDSS_VSYNC_CLK>; - clock-names = "iface", - "bus", - "core", - "iommu", - "vsync"; - - iommus = <&mdp_smmu 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdp5_intf3_out: endpoint { - remote-endpoint = <&hdmi_in>; - }; - }; - }; - }; - - hdmi: hdmi-tx@9a0000 { - compatible = "qcom,hdmi-tx-8996"; - reg = <0x009a0000 0x50c>, - <0x00070000 0x6158>, - <0x009e0000 0xfff>; - reg-names = "core_physical", - "qfprom_physical", - "hdcp_physical"; - - interrupt-parent = <&mdss>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&mmcc MDSS_MDP_CLK>, - <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_HDMI_CLK>, - <&mmcc MDSS_HDMI_AHB_CLK>, - <&mmcc MDSS_EXTPCLK_CLK>; - clock-names = - "mdp_core", - "iface", - "core", - "alt_iface", - "extp"; - - phys = <&hdmi_phy>; - phy-names = "hdmi_phy"; - #sound-dai-cells = <1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - hdmi_in: endpoint { - remote-endpoint = <&mdp5_intf3_out>; - }; - }; - }; - }; - - hdmi_phy: hdmi-phy@9a0600 { - #phy-cells = <0>; - compatible = "qcom,hdmi-phy-8996"; - reg = <0x009a0600 0x1c4>, - <0x009a0a00 0x124>, - <0x009a0c00 0x124>, - <0x009a0e00 0x124>, - <0x009a1000 0x124>, - <0x009a1200 0x0c8>; - reg-names = "hdmi_pll", - "hdmi_tx_l0", - "hdmi_tx_l1", - "hdmi_tx_l2", - "hdmi_tx_l3", - "hdmi_phy"; - - clocks = <&mmcc MDSS_AHB_CLK>, - <&gcc GCC_HDMI_CLKREF_CLK>; - clock-names = "iface", - "ref"; - }; - }; - gpu@b00000 { - compatible = "qcom,adreno-530.2", "qcom,adreno"; - #stream-id-cells = <16>; - - reg = <0x00b00000 0x3f000>; - reg-names = "kgsl_3d0_reg_memory"; - - interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&mmcc GPU_GX_GFX3D_CLK>, - <&mmcc GPU_AHB_CLK>, - <&mmcc GPU_GX_RBBMTIMER_CLK>, - <&gcc GCC_BIMC_GFX_CLK>, - <&gcc GCC_MMSS_BIMC_GFX_CLK>; - - clock-names = "core", - "iface", - "rbbmtimer", - "mem", - "mem_iface"; - - power-domains = <&mmcc GPU_GX_GDSC>; - iommus = <&adreno_smmu 0>; - - nvmem-cells = <&gpu_speed_bin>; - nvmem-cell-names = "speed_bin"; - - operating-points-v2 = <&gpu_opp_table>; - - gpu_opp_table: opp-table { - compatible ="operating-points-v2"; - - /* - * 624Mhz and 560Mhz are only available on speed - * bin (1 << 0). All the rest are available on - * all bins of the hardware - */ - opp-624000000 { - opp-hz = /bits/ 64 <624000000>; - opp-supported-hw = <0x01>; - }; - opp-560000000 { - opp-hz = /bits/ 64 <560000000>; - opp-supported-hw = <0x01>; - }; - opp-510000000 { - opp-hz = /bits/ 64 <510000000>; - opp-supported-hw = <0xFF>; - }; - opp-401800000 { - opp-hz = /bits/ 64 <401800000>; - opp-supported-hw = <0xFF>; - }; - opp-315000000 { - opp-hz = /bits/ 64 <315000000>; - opp-supported-hw = <0xFF>; - }; - opp-214000000 { - opp-hz = /bits/ 64 <214000000>; - opp-supported-hw = <0xFF>; - }; - opp-133000000 { - opp-hz = /bits/ 64 <133000000>; - opp-supported-hw = <0xFF>; - }; - }; - - zap-shader { - memory-region = <&zap_shader_region>; - }; - }; - - msmgpio: pinctrl@1010000 { - compatible = "qcom,msm8996-pinctrl"; - reg = <0x01010000 0x300000>; - interrupts = ; - gpio-controller; - gpio-ranges = <&msmgpio 0 0 150>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - spmi_bus: qcom,spmi@400f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0400f000 0x1000>, - <0x04400000 0x800000>, - <0x04c00000 0x800000>, - <0x05800000 0x200000>, - <0x0400a000 0x002100>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - agnoc@0 { - power-domains = <&gcc AGGRE0_NOC_GDSC>; - compatible = "simple-pm-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pcie0: pcie@600000 { - compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; - status = "disabled"; - power-domains = <&gcc PCIE0_GDSC>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - - reg = <0x00600000 0x2000>, - <0x0c000000 0xf1d>, - <0x0c000f20 0xa8>, - <0x0c100000 0x100000>; - reg-names = "parf", "dbi", "elbi","config"; - - phys = <&pciephy_0>; - phy-names = "pciephy"; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, - <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>; - pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>; - - linux,pci-domain = <0>; - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>; - - clock-names = "pipe", - "aux", - "cfg", - "bus_master", - "bus_slave"; - - }; - - pcie1: pcie@608000 { - compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; - power-domains = <&gcc PCIE1_GDSC>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - - status = "disabled"; - - reg = <0x00608000 0x2000>, - <0x0d000000 0xf1d>, - <0x0d000f20 0xa8>, - <0x0d100000 0x100000>; - - reg-names = "parf", "dbi", "elbi","config"; - - phys = <&pciephy_1>; - phy-names = "pciephy"; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>, - <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>; - pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>; - - linux,pci-domain = <1>; - - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_AXI_CLK>; - - clock-names = "pipe", - "aux", - "cfg", - "bus_master", - "bus_slave"; - }; - - pcie2: pcie@610000 { - compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; - power-domains = <&gcc PCIE2_GDSC>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - status = "disabled"; - reg = <0x00610000 0x2000>, - <0x0e000000 0xf1d>, - <0x0e000f20 0xa8>, - <0x0e100000 0x100000>; - - reg-names = "parf", "dbi", "elbi","config"; - - phys = <&pciephy_2>; - phy-names = "pciephy"; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>, - <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; - - device_type = "pci"; - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>; - pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >; - - linux,pci-domain = <2>; - clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, - <&gcc GCC_PCIE_2_AUX_CLK>, - <&gcc GCC_PCIE_2_CFG_AHB_CLK>, - <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_2_SLV_AXI_CLK>; - - clock-names = "pipe", - "aux", - "cfg", - "bus_master", - "bus_slave"; - }; - }; - - ufshc: ufshc@624000 { - compatible = "qcom,ufshc"; - reg = <0x00624000 0x2500>; - interrupts = ; - - phys = <&ufsphy_lane>; - phy-names = "ufsphy"; - - power-domains = <&gcc UFS_GDSC>; - - clock-names = - "core_clk_src", - "core_clk", - "bus_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro_src", - "core_clk_unipro", - "core_clk_ice", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk"; - clocks = - <&gcc UFS_AXI_CLK_SRC>, - <&gcc GCC_UFS_AXI_CLK>, - <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, - <&gcc GCC_AGGRE2_UFS_AXI_CLK>, - <&gcc GCC_UFS_AHB_CLK>, - <&gcc UFS_ICE_CORE_CLK_SRC>, - <&gcc GCC_UFS_UNIPRO_CORE_CLK>, - <&gcc GCC_UFS_ICE_CORE_CLK>, - <&rpmcc RPM_SMD_LN_BB_CLK>, - <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; - freq-table-hz = - <100000000 200000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>, - <150000000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; - - lanes-per-direction = <1>; - #reset-cells = <1>; - status = "disabled"; - - ufs_variant { - compatible = "qcom,ufs_variant"; - }; - }; - - ufsphy: phy@627000 { - compatible = "qcom,msm8996-qmp-ufs-phy"; - reg = <0x00627000 0x1c4>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_UFS_CLKREF_CLK>; - clock-names = "ref"; - - resets = <&ufshc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufsphy_lane: lanes@627400 { - reg = <0x627400 0x12c>, - <0x627600 0x200>, - <0x627c00 0x1b4>; - #phy-cells = <0>; - }; - }; - - camss: camss@a00000 { - compatible = "qcom,msm8996-camss"; - reg = <0x00a34000 0x1000>, - <0x00a00030 0x4>, - <0x00a35000 0x1000>, - <0x00a00038 0x4>, - <0x00a36000 0x1000>, - <0x00a00040 0x4>, - <0x00a30000 0x100>, - <0x00a30400 0x100>, - <0x00a30800 0x100>, - <0x00a30c00 0x100>, - <0x00a31000 0x500>, - <0x00a00020 0x10>, - <0x00a10000 0x1000>, - <0x00a14000 0x1000>; - reg-names = "csiphy0", - "csiphy0_clk_mux", - "csiphy1", - "csiphy1_clk_mux", - "csiphy2", - "csiphy2_clk_mux", - "csid0", - "csid1", - "csid2", - "csid3", - "ispif", - "csi_clk_mux", - "vfe0", - "vfe1"; - interrupts = , - , - , - , - , - , - , - , - , - ; - interrupt-names = "csiphy0", - "csiphy1", - "csiphy2", - "csid0", - "csid1", - "csid2", - "csid3", - "ispif", - "vfe0", - "vfe1"; - power-domains = <&mmcc VFE0_GDSC>, - <&mmcc VFE1_GDSC>; - clocks = <&mmcc CAMSS_TOP_AHB_CLK>, - <&mmcc CAMSS_ISPIF_AHB_CLK>, - <&mmcc CAMSS_CSI0PHYTIMER_CLK>, - <&mmcc CAMSS_CSI1PHYTIMER_CLK>, - <&mmcc CAMSS_CSI2PHYTIMER_CLK>, - <&mmcc CAMSS_CSI0_AHB_CLK>, - <&mmcc CAMSS_CSI0_CLK>, - <&mmcc CAMSS_CSI0PHY_CLK>, - <&mmcc CAMSS_CSI0PIX_CLK>, - <&mmcc CAMSS_CSI0RDI_CLK>, - <&mmcc CAMSS_CSI1_AHB_CLK>, - <&mmcc CAMSS_CSI1_CLK>, - <&mmcc CAMSS_CSI1PHY_CLK>, - <&mmcc CAMSS_CSI1PIX_CLK>, - <&mmcc CAMSS_CSI1RDI_CLK>, - <&mmcc CAMSS_CSI2_AHB_CLK>, - <&mmcc CAMSS_CSI2_CLK>, - <&mmcc CAMSS_CSI2PHY_CLK>, - <&mmcc CAMSS_CSI2PIX_CLK>, - <&mmcc CAMSS_CSI2RDI_CLK>, - <&mmcc CAMSS_CSI3_AHB_CLK>, - <&mmcc CAMSS_CSI3_CLK>, - <&mmcc CAMSS_CSI3PHY_CLK>, - <&mmcc CAMSS_CSI3PIX_CLK>, - <&mmcc CAMSS_CSI3RDI_CLK>, - <&mmcc CAMSS_AHB_CLK>, - <&mmcc CAMSS_VFE0_CLK>, - <&mmcc CAMSS_CSI_VFE0_CLK>, - <&mmcc CAMSS_VFE0_AHB_CLK>, - <&mmcc CAMSS_VFE0_STREAM_CLK>, - <&mmcc CAMSS_VFE1_CLK>, - <&mmcc CAMSS_CSI_VFE1_CLK>, - <&mmcc CAMSS_VFE1_AHB_CLK>, - <&mmcc CAMSS_VFE1_STREAM_CLK>, - <&mmcc CAMSS_VFE_AHB_CLK>, - <&mmcc CAMSS_VFE_AXI_CLK>; - clock-names = "top_ahb", - "ispif_ahb", - "csiphy0_timer", - "csiphy1_timer", - "csiphy2_timer", - "csi0_ahb", - "csi0", - "csi0_phy", - "csi0_pix", - "csi0_rdi", - "csi1_ahb", - "csi1", - "csi1_phy", - "csi1_pix", - "csi1_rdi", - "csi2_ahb", - "csi2", - "csi2_phy", - "csi2_pix", - "csi2_rdi", - "csi3_ahb", - "csi3", - "csi3_phy", - "csi3_pix", - "csi3_rdi", - "ahb", - "vfe0", - "csi_vfe0", - "vfe0_ahb", - "vfe0_stream", - "vfe1", - "csi_vfe1", - "vfe1_ahb", - "vfe1_stream", - "vfe_ahb", - "vfe_axi"; - iommus = <&vfe_smmu 0>, - <&vfe_smmu 1>, - <&vfe_smmu 2>, - <&vfe_smmu 3>; - status = "disabled"; - ports { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - cci: cci@a0c000 { - compatible = "qcom,msm8996-cci"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xa0c000 0x1000>; - interrupts = ; - power-domains = <&mmcc CAMSS_GDSC>; - clocks = <&mmcc CAMSS_TOP_AHB_CLK>, - <&mmcc CAMSS_CCI_AHB_CLK>, - <&mmcc CAMSS_CCI_CLK>, - <&mmcc CAMSS_AHB_CLK>; - clock-names = "camss_top_ahb", - "cci_ahb", - "cci", - "camss_ahb"; - assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, - <&mmcc CAMSS_CCI_CLK>; - assigned-clock-rates = <80000000>, <37500000>; - pinctrl-names = "default"; - pinctrl-0 = <&cci0_default &cci1_default>; - status = "disabled"; - - cci_i2c0: i2c-bus@0 { - reg = <0>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - cci_i2c1: i2c-bus@1 { - reg = <1>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - adreno_smmu: iommu@b40000 { - compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; - reg = <0x00b40000 0x10000>; - - #global-interrupts = <1>; - interrupts = , - , - ; - #iommu-cells = <1>; - - clocks = <&mmcc GPU_AHB_CLK>, - <&gcc GCC_MMSS_BIMC_GFX_CLK>; - clock-names = "iface", "bus"; - - power-domains = <&mmcc GPU_GDSC>; - }; - - video-codec@c00000 { - compatible = "qcom,msm8996-venus"; - reg = <0x00c00000 0xff000>; - interrupts = ; - power-domains = <&mmcc VENUS_GDSC>; - clocks = <&mmcc VIDEO_CORE_CLK>, - <&mmcc VIDEO_AHB_CLK>, - <&mmcc VIDEO_AXI_CLK>, - <&mmcc VIDEO_MAXI_CLK>; - clock-names = "core", "iface", "bus", "mbus"; - iommus = <&venus_smmu 0x00>, - <&venus_smmu 0x01>, - <&venus_smmu 0x0a>, - <&venus_smmu 0x07>, - <&venus_smmu 0x0e>, - <&venus_smmu 0x0f>, - <&venus_smmu 0x08>, - <&venus_smmu 0x09>, - <&venus_smmu 0x0b>, - <&venus_smmu 0x0c>, - <&venus_smmu 0x0d>, - <&venus_smmu 0x10>, - <&venus_smmu 0x11>, - <&venus_smmu 0x21>, - <&venus_smmu 0x28>, - <&venus_smmu 0x29>, - <&venus_smmu 0x2b>, - <&venus_smmu 0x2c>, - <&venus_smmu 0x2d>, - <&venus_smmu 0x31>; - memory-region = <&venus_region>; - status = "okay"; - - video-decoder { - compatible = "venus-decoder"; - clocks = <&mmcc VIDEO_SUBCORE0_CLK>; - clock-names = "core"; - power-domains = <&mmcc VENUS_CORE0_GDSC>; - }; - - video-encoder { - compatible = "venus-encoder"; - clocks = <&mmcc VIDEO_SUBCORE1_CLK>; - clock-names = "core"; - power-domains = <&mmcc VENUS_CORE1_GDSC>; - }; - }; - - mdp_smmu: iommu@d00000 { - compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; - reg = <0x00d00000 0x10000>; - - #global-interrupts = <1>; - interrupts = , - , - ; - #iommu-cells = <1>; - clocks = <&mmcc SMMU_MDP_AHB_CLK>, - <&mmcc SMMU_MDP_AXI_CLK>; - clock-names = "iface", "bus"; - - power-domains = <&mmcc MDSS_GDSC>; - }; - - venus_smmu: iommu@d40000 { - compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; - reg = <0x00d40000 0x20000>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - ; - power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; - clocks = <&mmcc SMMU_VIDEO_AHB_CLK>, - <&mmcc SMMU_VIDEO_AXI_CLK>; - clock-names = "iface", "bus"; - #iommu-cells = <1>; - status = "okay"; - }; - - vfe_smmu: iommu@da0000 { - compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; - reg = <0x00da0000 0x10000>; - - #global-interrupts = <1>; - interrupts = , - , - ; - power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; - clocks = <&mmcc SMMU_VFE_AHB_CLK>, - <&mmcc SMMU_VFE_AXI_CLK>; - clock-names = "iface", - "bus"; - #iommu-cells = <1>; - }; - - lpass_q6_smmu: iommu@1600000 { - compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; - reg = <0x01600000 0x20000>; - #iommu-cells = <1>; - power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; - - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - ; - - clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>, - <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; - clock-names = "iface", "bus"; - }; - - stm@3002000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0x3002000 0x1000>, - <0x8280000 0x180000>; - reg-names = "stm-base", "stm-stimulus-base"; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - port { - stm_out: endpoint { - remote-endpoint = - <&funnel0_in>; - }; - }; - }; - }; - - tpiu@3020000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0x3020000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - port { - tpiu_in: endpoint { - remote-endpoint = - <&replicator_out1>; - }; - }; - }; - }; - - funnel@3021000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x3021000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@7 { - reg = <7>; - funnel0_in: endpoint { - remote-endpoint = - <&stm_out>; - }; - }; - }; - - out-ports { - port { - funnel0_out: endpoint { - remote-endpoint = - <&merge_funnel_in0>; - }; - }; - }; - }; - - funnel@3022000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x3022000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@6 { - reg = <6>; - funnel1_in: endpoint { - remote-endpoint = - <&apss_merge_funnel_out>; - }; - }; - }; - - out-ports { - port { - funnel1_out: endpoint { - remote-endpoint = - <&merge_funnel_in1>; - }; - }; - }; - }; - - funnel@3023000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x3023000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - - out-ports { - port { - funnel2_out: endpoint { - remote-endpoint = - <&merge_funnel_in2>; - }; - }; - }; - }; - - funnel@3025000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x3025000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - merge_funnel_in0: endpoint { - remote-endpoint = - <&funnel0_out>; - }; - }; - - port@1 { - reg = <1>; - merge_funnel_in1: endpoint { - remote-endpoint = - <&funnel1_out>; - }; - }; - - port@2 { - reg = <2>; - merge_funnel_in2: endpoint { - remote-endpoint = - <&funnel2_out>; - }; - }; - }; - - out-ports { - port { - merge_funnel_out: endpoint { - remote-endpoint = - <&etf_in>; - }; - }; - }; - }; - - replicator@3026000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0x3026000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = - <&etf_out>; - }; - }; - }; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = - <&etr_in>; - }; - }; - - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = - <&tpiu_in>; - }; - }; - }; - }; - - etf@3027000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x3027000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - port { - etf_in: endpoint { - remote-endpoint = - <&merge_funnel_out>; - }; - }; - }; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = - <&replicator_in>; - }; - }; - }; - }; - - etr@3028000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x3028000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - arm,scatter-gather; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = - <&replicator_out0>; - }; - }; - }; - }; - - debug@3810000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x3810000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU0>; - }; - - etm@3840000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x3840000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU0>; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = - <&apss_funnel0_in0>; - }; - }; - }; - }; - - debug@3910000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x3910000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU1>; - }; - - etm@3940000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x3940000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU1>; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = - <&apss_funnel0_in1>; - }; - }; - }; - }; - - funnel@39b0000 { /* APSS Funnel 0 */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x39b0000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - apss_funnel0_in0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - apss_funnel0_in1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - }; - - out-ports { - port { - apss_funnel0_out: endpoint { - remote-endpoint = - <&apss_merge_funnel_in0>; - }; - }; - }; - }; - - debug@3a10000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x3a10000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU2>; - }; - - etm@3a40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x3a40000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU2>; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = - <&apss_funnel1_in0>; - }; - }; - }; - }; - - debug@3b10000 { - compatible = "arm,coresight-cpu-debug", "arm,primecell"; - reg = <0x3b10000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - cpu = <&CPU3>; - }; - - etm@3b40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x3b40000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU3>; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = - <&apss_funnel1_in1>; - }; - }; - }; - }; - - funnel@3bb0000 { /* APSS Funnel 1 */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x3bb0000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - apss_funnel1_in0: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - - port@1 { - reg = <1>; - apss_funnel1_in1: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - }; - - out-ports { - port { - apss_funnel1_out: endpoint { - remote-endpoint = - <&apss_merge_funnel_in1>; - }; - }; - }; - }; - - funnel@3bc0000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x3bc0000 0x1000>; - - clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - apss_merge_funnel_in0: endpoint { - remote-endpoint = - <&apss_funnel0_out>; - }; - }; - - port@1 { - reg = <1>; - apss_merge_funnel_in1: endpoint { - remote-endpoint = - <&apss_funnel1_out>; - }; - }; - }; - - out-ports { - port { - apss_merge_funnel_out: endpoint { - remote-endpoint = - <&funnel1_in>; - }; - }; - }; - }; - kryocc: clock-controller@6400000 { - compatible = "qcom,apcc-msm8996"; - reg = <0x06400000 0x90000>; - #clock-cells = <1>; - }; - - usb3: usb@6af8800 { - compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; - reg = <0x06af8800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, - <&gcc GCC_USB30_MASTER_CLK>, - <&gcc GCC_AGGRE2_USB3_AXI_CLK>, - <&gcc GCC_USB30_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SLEEP_CLK>, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; - - assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_MASTER_CLK>; - assigned-clock-rates = <19200000>, <120000000>; - - power-domains = <&gcc USB30_GDSC>; - status = "disabled"; - - dwc3@6a00000 { - compatible = "snps,dwc3"; - reg = <0x06a00000 0xcc00>; - interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; - phys = <&hsusb_phy1>, <&ssusb_phy_0>; - phy-names = "usb2-phy", "usb3-phy"; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - }; - }; - - usb3phy: phy@7410000 { - compatible = "qcom,msm8996-qmp-usb3-phy"; - reg = <0x07410000 0x1c4>; - #clock-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_USB3_CLKREF_CLK>; - clock-names = "aux", "cfg_ahb", "ref"; - - resets = <&gcc GCC_USB3_PHY_BCR>, - <&gcc GCC_USB3PHY_PHY_BCR>; - reset-names = "phy", "common"; - status = "disabled"; - - ssusb_phy_0: lane@7410200 { - reg = <0x07410200 0x200>, - <0x07410400 0x130>, - <0x07410600 0x1a8>; - #phy-cells = <0>; - - clock-output-names = "usb3_phy_pipe_clk_src"; - clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; - clock-names = "pipe0"; - }; - }; - - hsusb_phy1: phy@7411000 { - compatible = "qcom,msm8996-qusb2-phy"; - reg = <0x07411000 0x180>; - #phy-cells = <0>; - - clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_RX1_USB2_CLKREF_CLK>; - clock-names = "cfg_ahb", "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - nvmem-cells = <&qusb2p_hstx_trim>; - status = "disabled"; - }; - - hsusb_phy2: phy@7412000 { - compatible = "qcom,msm8996-qusb2-phy"; - reg = <0x07412000 0x180>; - #phy-cells = <0>; - - clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_RX2_USB2_CLKREF_CLK>; - clock-names = "cfg_ahb", "ref"; - - resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; - nvmem-cells = <&qusb2s_hstx_trim>; - status = "disabled"; - }; - - sdhc2: sdhci@74a4900 { - status = "disabled"; - compatible = "qcom,sdhci-msm-v4"; - reg = <0x074a4900 0x314>, <0x074a4000 0x800>; - reg-names = "hc_mem", "core_mem"; - - interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, - <0 221 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hc_irq", "pwr_irq"; - - clock-names = "iface", "core", "xo"; - clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, - <&xo_board>; - bus-width = <4>; - }; - - blsp1_uart1: serial@7570000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x07570000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp1_spi0: spi@7575000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x07575000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_spi0_default>; - pinctrl-1 = <&blsp1_spi0_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_i2c2: i2c@7577000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x07577000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_i2c2_default>; - pinctrl-1 = <&blsp1_i2c2_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_uart1: serial@75b0000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x075b0000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp2_uart2: serial@75b1000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x075b1000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp2_i2c0: i2c@75b5000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x075b5000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_i2c0_default>; - pinctrl-1 = <&blsp2_i2c0_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_i2c1: i2c@75b6000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x075b6000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_i2c1_default>; - pinctrl-1 = <&blsp2_i2c1_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_spi5: spi@75ba000{ - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x075ba000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_spi5_default>; - pinctrl-1 = <&blsp2_spi5_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - usb2: usb@76f8800 { - compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; - reg = <0x076f8800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, - <&gcc GCC_USB20_MASTER_CLK>, - <&gcc GCC_USB20_MOCK_UTMI_CLK>, - <&gcc GCC_USB20_SLEEP_CLK>, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; - - assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, - <&gcc GCC_USB20_MASTER_CLK>; - assigned-clock-rates = <19200000>, <60000000>; - - power-domains = <&gcc USB30_GDSC>; - status = "disabled"; - - dwc3@7600000 { - compatible = "snps,dwc3"; - reg = <0x07600000 0xcc00>; - interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; - phys = <&hsusb_phy2>; - phy-names = "usb2-phy"; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - }; - }; - - slimbam: dma@9184000 { - compatible = "qcom,bam-v1.7.0"; - qcom,controlled-remotely; - reg = <0x09184000 0x32000>; - num-channels = <31>; - interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - qcom,ee = <1>; - qcom,num-ees = <2>; - }; - - slim_msm: slim@91c0000 { - compatible = "qcom,slim-ngd-v1.5.0"; - reg = <0x091c0000 0x2C000>; - reg-names = "ctrl"; - interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&slimbam 3>, <&slimbam 4>, - <&slimbam 5>, <&slimbam 6>; - dma-names = "rx", "tx", "tx2", "rx2"; - #address-cells = <1>; - #size-cells = <0>; - ngd@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <1>; - - tasha_ifd: tas-ifd { - compatible = "slim217,1a0"; - reg = <0 0>; - }; - - wcd9335: codec@1{ - pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; - pinctrl-names = "default"; - - compatible = "slim217,1a0"; - reg = <1 0>; - - interrupt-parent = <&msmgpio>; - interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, - <53 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "intr1", "intr2"; - interrupt-controller; - #interrupt-cells = <1>; - reset-gpios = <&msmgpio 64 0>; - - slim-ifc-dev = <&tasha_ifd>; - - #sound-dai-cells = <1>; - }; - }; - }; - - adsp_pil: remoteproc@9300000 { - compatible = "qcom,msm8996-adsp-pil"; - reg = <0x09300000 0x80000>; - - interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&xo_board>; - clock-names = "xo"; - - memory-region = <&adsp_region>; - - qcom,smem-states = <&smp2p_adsp_out 0>; - qcom,smem-state-names = "stop"; - - smd-edge { - interrupts = ; - - label = "lpass"; - mboxes = <&apcs_glb 8>; - qcom,smd-edge = <1>; - qcom,remote-pid = <2>; - #address-cells = <1>; - #size-cells = <0>; - apr { - power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; - compatible = "qcom,apr-v2"; - qcom,smd-channels = "apr_audio_svc"; - qcom,apr-domain = ; - #address-cells = <1>; - #size-cells = <0>; - - q6core { - reg = ; - compatible = "qcom,q6core"; - }; - - q6afe: q6afe { - compatible = "qcom,q6afe"; - reg = ; - q6afedai: dais { - compatible = "qcom,q6afe-dais"; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <1>; - hdmi@1 { - reg = <1>; - }; - }; - }; - - q6asm: q6asm { - compatible = "qcom,q6asm"; - reg = ; - q6asmdai: dais { - compatible = "qcom,q6asm-dais"; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <1>; - iommus = <&lpass_q6_smmu 1>; - }; - }; - - q6adm: q6adm { - compatible = "qcom,q6adm"; - reg = ; - q6routing: routing { - compatible = "qcom,q6adm-routing"; - #sound-dai-cells = <0>; - }; - }; - }; - - }; - }; - - apcs_glb: mailbox@9820000 { - compatible = "qcom,msm8996-apcs-hmss-global"; - reg = <0x09820000 0x1000>; - - #mbox-cells = <1>; - }; - - timer@9840000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x09840000 0x1000>; - clock-frequency = <19200000>; - - frame@9850000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x09850000 0x1000>, - <0x09860000 0x1000>; - }; - - frame@9870000 { - frame-number = <1>; - interrupts = ; - reg = <0x09870000 0x1000>; - status = "disabled"; - }; - - frame@9880000 { - frame-number = <2>; - interrupts = ; - reg = <0x09880000 0x1000>; - status = "disabled"; - }; - - frame@9890000 { - frame-number = <3>; - interrupts = ; - reg = <0x09890000 0x1000>; - status = "disabled"; - }; - - frame@98a0000 { - frame-number = <4>; - interrupts = ; - reg = <0x098a0000 0x1000>; - status = "disabled"; - }; - - frame@98b0000 { - frame-number = <5>; - interrupts = ; - reg = <0x098b0000 0x1000>; - status = "disabled"; - }; - - frame@98c0000 { - frame-number = <6>; - interrupts = ; - reg = <0x098c0000 0x1000>; - status = "disabled"; - }; - }; - - saw3: syscon@9a10000 { - compatible = "syscon"; - reg = <0x09a10000 0x1000>; - }; - - intc: interrupt-controller@9bc0000 { - compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x40000>; - reg = <0x09bc0000 0x10000>, - <0x09c00000 0x100000>; - interrupts = ; - }; - }; - - sound: sound { - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 3>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 5>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 8>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 10>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - gpu-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 6>; - - trips { - gpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - gpu-thermal-bottom { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 7>; - - trips { - gpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - m4m-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 1>; - - trips { - m4m_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - l3-or-venus-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 2>; - - trips { - l3_or_venus_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster0-l2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 7>; - - trips { - cluster0_l2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster1-l2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 12>; - - trips { - cluster1_l2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 1>; - - trips { - camera_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-dsp-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 2>; - - trips { - q6_dsp_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 3>; - - trips { - mem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modemtx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 4>; - - trips { - modemtx_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; -#include "msm8996-pins.dtsi" diff --git a/arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dts b/arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dts deleted file mode 100644 index db5821be1..000000000 --- a/arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dts +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2019, Jeffrey Hugo. All rights reserved. */ - -/dts-v1/; - -#include "msm8998-clamshell.dtsi" - -/ { - model = "Asus NovaGo TP370QL"; - compatible = "asus,novago-tp370ql", "qcom,msm8998"; -}; - -&blsp1_i2c6 { - status = "okay"; - - touchpad@15 { - compatible = "hid-over-i2c"; - interrupt-parent = <&tlmm>; - interrupts = <0x7b IRQ_TYPE_LEVEL_LOW>; - reg = <0x15>; - hid-descr-addr = <0x0001>; - - pinctrl-names = "default"; - pinctrl-0 = <&touchpad>; - }; - - keyboard@3a { - compatible = "hid-over-i2c"; - interrupt-parent = <&tlmm>; - interrupts = <0x25 IRQ_TYPE_LEVEL_LOW>; - reg = <0x3a>; - hid-descr-addr = <0x0001>; - }; -}; - -&sdhc2 { - cd-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; -}; - -&tlmm { - touchpad: touchpad { - config { - pins = "gpio123"; - bias-pull-up; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi b/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi deleted file mode 100644 index 00d84fb21..000000000 --- a/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi +++ /dev/null @@ -1,343 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2019, Jeffrey Hugo. All rights reserved. */ - -/* - * Common include for MSM8998 clamshell devices, ie the Lenovo Miix 630, - * Asus NovaGo TP370QL, and HP Envy x2. All three devices are basically the - * same, with differences in peripherals. - */ - -#include "msm8998.dtsi" -#include "pm8998.dtsi" -#include "pm8005.dtsi" - -/ { - chosen { - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&blsp1_uart3 { - status = "okay"; - - bluetooth { - compatible = "qcom,wcn3990-bt"; - - vddio-supply = <&vreg_s4a_1p8>; - vddxo-supply = <&vreg_l7a_1p8>; - vddrf-supply = <&vreg_l17a_1p3>; - vddch0-supply = <&vreg_l25a_3p3>; - max-speed = <3200000>; - }; -}; - -/* - * The laptop FW does not appear to support the retention state as it is - * not advertised as enabled in ACPI, and enabling it in DT can cause boot - * hangs. - */ -&CPU0 { - cpu-idle-states = <&LITTLE_CPU_SLEEP_1>; -}; - -&CPU1 { - cpu-idle-states = <&LITTLE_CPU_SLEEP_1>; -}; - -&CPU2 { - cpu-idle-states = <&LITTLE_CPU_SLEEP_1>; -}; - -&CPU3 { - cpu-idle-states = <&LITTLE_CPU_SLEEP_1>; -}; - -&CPU4 { - cpu-idle-states = <&BIG_CPU_SLEEP_1>; -}; - -&CPU5 { - cpu-idle-states = <&BIG_CPU_SLEEP_1>; -}; - -&CPU6 { - cpu-idle-states = <&BIG_CPU_SLEEP_1>; -}; - -&CPU7 { - cpu-idle-states = <&BIG_CPU_SLEEP_1>; -}; - -&pm8005_lsid1 { - pm8005-regulators { - compatible = "qcom,pm8005-regulators"; - - vdd_s1-supply = <&vph_pwr>; - - pm8005_s1: s1 { /* VDD_GFX supply */ - regulator-min-microvolt = <524000>; - regulator-max-microvolt = <1100000>; - regulator-enable-ramp-delay = <500>; - - /* hack until we rig up the gpu consumer */ - regulator-always-on; - }; - }; -}; - -&qusb2phy { - status = "okay"; - - vdda-pll-supply = <&vreg_l12a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; -}; - -&rpm_requests { - pm8998-regulators { - compatible = "qcom,rpm-pm8998-regulators"; - - vdd_s1-supply = <&vph_pwr>; - vdd_s2-supply = <&vph_pwr>; - vdd_s3-supply = <&vph_pwr>; - vdd_s4-supply = <&vph_pwr>; - vdd_s5-supply = <&vph_pwr>; - vdd_s6-supply = <&vph_pwr>; - vdd_s7-supply = <&vph_pwr>; - vdd_s8-supply = <&vph_pwr>; - vdd_s9-supply = <&vph_pwr>; - vdd_s10-supply = <&vph_pwr>; - vdd_s11-supply = <&vph_pwr>; - vdd_s12-supply = <&vph_pwr>; - vdd_s13-supply = <&vph_pwr>; - vdd_l1_l27-supply = <&vreg_s7a_1p025>; - vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>; - vdd_l3_l11-supply = <&vreg_s7a_1p025>; - vdd_l4_l5-supply = <&vreg_s7a_1p025>; - vdd_l6-supply = <&vreg_s5a_2p04>; - vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>; - vdd_l9-supply = <&vph_pwr>; - vdd_l10_l23_l25-supply = <&vph_pwr>; - vdd_l13_l19_l21-supply = <&vph_pwr>; - vdd_l16_l28-supply = <&vph_pwr>; - vdd_l18_l22-supply = <&vph_pwr>; - vdd_l20_l24-supply = <&vph_pwr>; - vdd_l26-supply = <&vreg_s3a_1p35>; - vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; - - vreg_s3a_1p35: s3 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - vreg_s4a_1p8: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-allow-set-load; - }; - vreg_s5a_2p04: s5 { - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2040000>; - }; - vreg_s7a_1p025: s7 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1028000>; - }; - vreg_l1a_0p875: l1 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-allow-set-load; - }; - vreg_l2a_1p2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-allow-set-load; - }; - vreg_l3a_1p0: l3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l5a_0p8: l5 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - }; - vreg_l6a_1p8: l6 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <1808000>; - }; - vreg_l7a_1p8: l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-allow-set-load; - }; - vreg_l8a_1p2: l8 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - vreg_l9a_1p8: l9 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <2960000>; - }; - vreg_l10a_1p8: l10 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <2960000>; - }; - vreg_l11a_1p0: l11 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l12a_1p8: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l13a_2p95: l13 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <2960000>; - }; - vreg_l14a_1p88: l14 { - regulator-min-microvolt = <1880000>; - regulator-max-microvolt = <1880000>; - }; - vreg_l15a_1p8: l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l16a_2p7: l16 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - }; - vreg_l17a_1p3: l17 { - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-allow-set-load; - }; - vreg_l18a_2p7: l18 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - }; - vreg_l19a_3p0: l19 { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - }; - vreg_l20a_2p95: l20 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-allow-set-load; - }; - vreg_l21a_2p95: l21 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-allow-set-load; - regulator-system-load = <800000>; - }; - vreg_l22a_2p85: l22 { - regulator-min-microvolt = <2864000>; - regulator-max-microvolt = <2864000>; - }; - vreg_l23a_3p3: l23 { - regulator-min-microvolt = <3312000>; - regulator-max-microvolt = <3312000>; - }; - vreg_l24a_3p075: l24 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3088000>; - }; - vreg_l25a_3p3: l25 { - regulator-min-microvolt = <3104000>; - regulator-max-microvolt = <3312000>; - regulator-allow-set-load; - }; - vreg_l26a_1p2: l26 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - vreg_l28_3p0: l28 { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - }; - - vreg_lvs1a_1p8: lvs1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vreg_lvs2a_1p8: lvs2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - }; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; - - touchpad: touchpad { - config { - pins = "gpio123"; - bias-pull-up; /* pull up */ - }; - }; -}; - -&sdhc2 { - status = "okay"; - - vmmc-supply = <&vreg_l21a_2p95>; - vqmmc-supply = <&vreg_l13a_2p95>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; -}; - -&usb3 { - status = "okay"; -}; - -&usb3_dwc3 { - dr_mode = "host"; /* Force to host until we have Type-C hooked up */ -}; - -&usb3phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l2a_1p2>; -}; - -&wifi { - status = "okay"; - - vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; - vdd-1.8-xo-supply = <&vreg_l7a_1p8>; - vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; - vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; -}; - -/* PINCTRL - board-specific pinctrl */ -&blsp1_uart3_on { - rx { - /delete-property/ bias-disable; - /* - * Configure a pull-up on 45 (RX). This is needed to - * avoid garbage data when the TX pin of the Bluetooth - * module is in tri-state (module powered off or not - * driving the signal yet). - */ - bias-pull-up; - }; - - cts { - /delete-property/ bias-disable; - /* - * Configure a pull-down on 47 (CTS) to match the pull - * of the Bluetooth module. - */ - bias-pull-down; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dts b/arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dts deleted file mode 100644 index 240731270..000000000 --- a/arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2019, Jeffrey Hugo. All rights reserved. */ - -/dts-v1/; - -#include "msm8998-clamshell.dtsi" - -/ { - model = "HP Envy x2"; - compatible = "hp,envy-x2", "qcom,msm8998"; -}; - -&blsp1_i2c6 { - status = "okay"; - - keyboard@3a { - compatible = "hid-over-i2c"; - interrupt-parent = <&tlmm>; - interrupts = <0x79 IRQ_TYPE_LEVEL_LOW>; - reg = <0x3a>; - hid-descr-addr = <0x0001>; - - pinctrl-names = "default"; - pinctrl-0 = <&touchpad>; - }; -}; - -&sdhc2 { - cd-gpios = <&tlmm 95 GPIO_ACTIVE_LOW>; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts b/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts deleted file mode 100644 index 89492ed51..000000000 --- a/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2019, Jeffrey Hugo. All rights reserved. */ - -/dts-v1/; - -#include "msm8998-clamshell.dtsi" - -/ { - model = "Lenovo Miix 630"; - compatible = "lenovo,miix-630", "qcom,msm8998"; -}; - -&blsp1_i2c6 { - status = "okay"; - - keyboard@3a { - compatible = "hid-over-i2c"; - interrupt-parent = <&tlmm>; - interrupts = <0x79 IRQ_TYPE_LEVEL_LOW>; - reg = <0x3a>; - hid-descr-addr = <0x0001>; - - pinctrl-names = "default"; - pinctrl-0 = <&touchpad>; - }; -}; - -&remoteproc_mss { - firmware-name = "qcom/LENOVO/81F1/qcdsp1v28998.mbn", - "qcom/LENOVO/81F1/qcdsp28998.mbn"; -}; - -&sdhc2 { - cd-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts deleted file mode 100644 index 66540d2ca..000000000 --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ - -/dts-v1/; - -#include "msm8998-mtp.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM8998 v1 MTP"; - compatible = "qcom,msm8998-mtp"; - - qcom,board-id = <8 0>; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi deleted file mode 100644 index cec42437b..000000000 --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi +++ /dev/null @@ -1,411 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ - -#include "msm8998.dtsi" -#include "pm8998.dtsi" -#include "pmi8998.dtsi" -#include "pm8005.dtsi" - -/ { - aliases { - serial0 = &blsp2_uart1; - serial1 = &blsp1_uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-always-on; - regulator-boot-on; - }; -}; - -&blsp1_uart3 { - status = "okay"; - - bluetooth { - compatible = "qcom,wcn3990-bt"; - - vddio-supply = <&vreg_s4a_1p8>; - vddxo-supply = <&vreg_l7a_1p8>; - vddrf-supply = <&vreg_l17a_1p3>; - vddch0-supply = <&vreg_l25a_3p3>; - max-speed = <3200000>; - }; -}; - -&blsp2_uart1 { - status = "okay"; -}; - -&etf { - status = "okay"; -}; - -&etm1 { - status = "okay"; -}; - -&etm2 { - status = "okay"; -}; - -&etm3 { - status = "okay"; -}; - -&etm4 { - status = "okay"; -}; - -&etm5 { - status = "okay"; -}; - -&etm6 { - status = "okay"; -}; - -&etm7 { - status = "okay"; -}; - -&etm8 { - status = "okay"; -}; - -&etr { - status = "okay"; -}; - -&funnel1 { - status = "okay"; -}; - -&funnel2 { - status = "okay"; -}; - -&funnel3 { - status = "okay"; -}; - -&funnel4 { - // FIXME: Figure out why clock late_initcall crashes the board with - // this enabled. - // status = "okay"; -}; - -&funnel5 { - // FIXME: Figure out why clock late_initcall crashes the board with - // this enabled. - // status = "okay"; -}; - -&pm8005_lsid1 { - pm8005-regulators { - compatible = "qcom,pm8005-regulators"; - - vdd_s1-supply = <&vph_pwr>; - - pm8005_s1: s1 { /* VDD_GFX supply */ - regulator-min-microvolt = <524000>; - regulator-max-microvolt = <1100000>; - regulator-enable-ramp-delay = <500>; - - /* hack until we rig up the gpu consumer */ - regulator-always-on; - }; - }; -}; - -&qusb2phy { - status = "okay"; - - vdda-pll-supply = <&vreg_l12a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; -}; - -&replicator1 { - status = "okay"; -}; - -&rpm_requests { - pm8998-regulators { - compatible = "qcom,rpm-pm8998-regulators"; - - vdd_s1-supply = <&vph_pwr>; - vdd_s2-supply = <&vph_pwr>; - vdd_s3-supply = <&vph_pwr>; - vdd_s4-supply = <&vph_pwr>; - vdd_s5-supply = <&vph_pwr>; - vdd_s6-supply = <&vph_pwr>; - vdd_s7-supply = <&vph_pwr>; - vdd_s8-supply = <&vph_pwr>; - vdd_s9-supply = <&vph_pwr>; - vdd_s10-supply = <&vph_pwr>; - vdd_s11-supply = <&vph_pwr>; - vdd_s12-supply = <&vph_pwr>; - vdd_s13-supply = <&vph_pwr>; - vdd_l1_l27-supply = <&vreg_s7a_1p025>; - vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>; - vdd_l3_l11-supply = <&vreg_s7a_1p025>; - vdd_l4_l5-supply = <&vreg_s7a_1p025>; - vdd_l6-supply = <&vreg_s5a_2p04>; - vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>; - vdd_l9-supply = <&vreg_bob>; - vdd_l10_l23_l25-supply = <&vreg_bob>; - vdd_l13_l19_l21-supply = <&vreg_bob>; - vdd_l16_l28-supply = <&vreg_bob>; - vdd_l18_l22-supply = <&vreg_bob>; - vdd_l20_l24-supply = <&vreg_bob>; - vdd_l26-supply = <&vreg_s3a_1p35>; - vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; - - vreg_s3a_1p35: s3 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - vreg_s4a_1p8: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-allow-set-load; - }; - vreg_s5a_2p04: s5 { - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2040000>; - }; - vreg_s7a_1p025: s7 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1028000>; - }; - vreg_l1a_0p875: l1 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - }; - vreg_l2a_1p2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - vreg_l3a_1p0: l3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l5a_0p8: l5 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - }; - vreg_l6a_1p8: l6 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <1808000>; - }; - vreg_l7a_1p8: l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l8a_1p2: l8 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - vreg_l9a_1p8: l9 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <2960000>; - }; - vreg_l10a_1p8: l10 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <2960000>; - }; - vreg_l11a_1p0: l11 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l12a_1p8: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l13a_2p95: l13 { - regulator-min-microvolt = <1808000>; - regulator-max-microvolt = <2960000>; - }; - vreg_l14a_1p88: l14 { - regulator-min-microvolt = <1880000>; - regulator-max-microvolt = <1880000>; - }; - vreg_l15a_1p8: l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l16a_2p7: l16 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - }; - vreg_l17a_1p3: l17 { - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - }; - vreg_l18a_2p7: l18 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - }; - vreg_l19a_3p0: l19 { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - }; - vreg_l20a_2p95: l20 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-allow-set-load; - }; - vreg_l21a_2p95: l21 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-allow-set-load; - regulator-system-load = <800000>; - }; - vreg_l22a_2p85: l22 { - regulator-min-microvolt = <2864000>; - regulator-max-microvolt = <2864000>; - }; - vreg_l23a_3p3: l23 { - regulator-min-microvolt = <3312000>; - regulator-max-microvolt = <3312000>; - }; - vreg_l24a_3p075: l24 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3088000>; - }; - vreg_l25a_3p3: l25 { - regulator-min-microvolt = <3104000>; - regulator-max-microvolt = <3312000>; - }; - vreg_l26a_1p2: l26 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-allow-set-load; - }; - vreg_l28_3p0: l28 { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - }; - - vreg_lvs1a_1p8: lvs1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vreg_lvs2a_1p8: lvs2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - }; - - pmi8998-regulators { - compatible = "qcom,rpm-pmi8998-regulators"; - - vdd_bob-supply = <&vph_pwr>; - - vreg_bob: bob { - regulator-min-microvolt = <3312000>; - regulator-max-microvolt = <3600000>; - }; - }; -}; - -&remoteproc_adsp { - status = "okay"; -}; - -&remoteproc_slpi { - status = "okay"; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; -}; - -&sdhc2 { - status = "okay"; - cd-gpios = <&tlmm 95 GPIO_ACTIVE_LOW>; - - vmmc-supply = <&vreg_l21a_2p95>; - vqmmc-supply = <&vreg_l13a_2p95>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; -}; - -&stm { - status = "okay"; -}; - -&ufshc { - vcc-supply = <&vreg_l20a_2p95>; - vccq-supply = <&vreg_l26a_1p2>; - vccq2-supply = <&vreg_s4a_1p8>; - vcc-max-microamp = <750000>; - vccq-max-microamp = <560000>; - vccq2-max-microamp = <750000>; -}; - -&ufsphy { - vdda-phy-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l2a_1p2>; - vddp-ref-clk-supply = <&vreg_l26a_1p2>; - vdda-phy-max-microamp = <51400>; - vdda-pll-max-microamp = <14600>; - vddp-ref-clk-max-microamp = <100>; - vddp-ref-clk-always-on; -}; - -&usb3 { - status = "okay"; -}; - -&usb3_dwc3 { - dr_mode = "host"; /* Force to host until we have Type-C hooked up */ -}; - -&usb3phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l2a_1p2>; -}; - -&wifi { - status = "okay"; - - vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; - vdd-1.8-xo-supply = <&vreg_l7a_1p8>; - vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; - vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; -}; - -/* PINCTRL - board-specific pinctrl */ -&blsp1_uart3_on { - rx { - /delete-property/ bias-disable; - /* - * Configure a pull-up on 45 (RX). This is needed to - * avoid garbage data when the TX pin of the Bluetooth - * module is in tri-state (module powered off or not - * driving the signal yet). - */ - bias-pull-up; - }; - - cts { - /delete-property/ bias-disable; - /* - * Configure a pull-down on 47 (CTS) to match the pull - * of the Bluetooth module. - */ - bias-pull-down; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8998-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8998-pins.dtsi deleted file mode 100644 index 7c222cbf1..000000000 --- a/arch/arm64/boot/dts/qcom/msm8998-pins.dtsi +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ - -&tlmm { - sdc2_clk_on: sdc2_clk_on { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 mA */ - }; - }; - - sdc2_clk_off: sdc2_clk_off { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <2>; /* 2 mA */ - }; - }; - - sdc2_cmd_on: sdc2_cmd_on { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <10>; /* 10 mA */ - }; - }; - - sdc2_cmd_off: sdc2_cmd_off { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 mA */ - }; - }; - - sdc2_data_on: sdc2_data_on { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <10>; /* 10 mA */ - }; - }; - - sdc2_data_off: sdc2_data_off { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 mA */ - }; - }; - - sdc2_cd_on: sdc2_cd_on { - mux { - pins = "gpio95"; - function = "gpio"; - }; - - config { - pins = "gpio95"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 mA */ - }; - }; - - sdc2_cd_off: sdc2_cd_off { - mux { - pins = "gpio95"; - function = "gpio"; - }; - - config { - pins = "gpio95"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 mA */ - }; - }; - - blsp1_uart3_on: blsp1_uart3_on { - tx { - pins = "gpio45"; - function = "blsp_uart3_a"; - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio46"; - function = "blsp_uart3_a"; - drive-strength = <2>; - bias-disable; - }; - - cts { - pins = "gpio47"; - function = "blsp_uart3_a"; - drive-strength = <2>; - bias-disable; - }; - - rfr { - pins = "gpio48"; - function = "blsp_uart3_a"; - drive-strength = <2>; - bias-disable; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi deleted file mode 100644 index 9e04ac3f5..000000000 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ /dev/null @@ -1,2118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ - -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - qcom,msm-id = <292 0x0>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - memory { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@85800000 { - reg = <0x0 0x85800000 0x0 0x600000>; - no-map; - }; - - xbl_mem: memory@85e00000 { - reg = <0x0 0x85e00000 0x0 0x100000>; - no-map; - }; - - smem_mem: smem-mem@86000000 { - reg = <0x0 0x86000000 0x0 0x200000>; - no-map; - }; - - tz_mem: memory@86200000 { - reg = <0x0 0x86200000 0x0 0x2d00000>; - no-map; - }; - - rmtfs_mem: memory@88f00000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x88f00000 0x0 0x200000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - spss_mem: memory@8ab00000 { - reg = <0x0 0x8ab00000 0x0 0x700000>; - no-map; - }; - - adsp_mem: memory@8b200000 { - reg = <0x0 0x8b200000 0x0 0x1a00000>; - no-map; - }; - - mpss_mem: memory@8cc00000 { - reg = <0x0 0x8cc00000 0x0 0x7000000>; - no-map; - }; - - venus_mem: memory@93c00000 { - reg = <0x0 0x93c00000 0x0 0x500000>; - no-map; - }; - - mba_mem: memory@94100000 { - reg = <0x0 0x94100000 0x0 0x200000>; - no-map; - }; - - slpi_mem: memory@94300000 { - reg = <0x0 0x94300000 0x0 0xf00000>; - no-map; - }; - - ipa_fw_mem: memory@95200000 { - reg = <0x0 0x95200000 0x0 0x10000>; - no-map; - }; - - ipa_gsi_mem: memory@95210000 { - reg = <0x0 0x95210000 0x0 0x5000>; - no-map; - }; - - gpu_mem: memory@95600000 { - reg = <0x0 0x95600000 0x0 0x100000>; - no-map; - }; - - wlan_msa_mem: memory@95700000 { - reg = <0x0 0x95700000 0x0 0x100000>; - no-map; - }; - }; - - clocks { - xo: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "xo_board"; - }; - - sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo280"; - reg = <0x0 0x0>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; - next-level-cache = <&L2_0>; - L2_0: l2-cache { - compatible = "arm,arch-cache"; - cache-level = <2>; - }; - L1_I_0: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_0: l1-dcache { - compatible = "arm,arch-cache"; - }; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "qcom,kryo280"; - reg = <0x0 0x1>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; - next-level-cache = <&L2_0>; - L1_I_1: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_1: l1-dcache { - compatible = "arm,arch-cache"; - }; - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "qcom,kryo280"; - reg = <0x0 0x2>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; - next-level-cache = <&L2_0>; - L1_I_2: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_2: l1-dcache { - compatible = "arm,arch-cache"; - }; - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "qcom,kryo280"; - reg = <0x0 0x3>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; - next-level-cache = <&L2_0>; - L1_I_3: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_3: l1-dcache { - compatible = "arm,arch-cache"; - }; - }; - - CPU4: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo280"; - reg = <0x0 0x100>; - enable-method = "psci"; - cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; - next-level-cache = <&L2_1>; - L2_1: l2-cache { - compatible = "arm,arch-cache"; - cache-level = <2>; - }; - L1_I_100: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_100: l1-dcache { - compatible = "arm,arch-cache"; - }; - }; - - CPU5: cpu@101 { - device_type = "cpu"; - compatible = "qcom,kryo280"; - reg = <0x0 0x101>; - enable-method = "psci"; - cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; - next-level-cache = <&L2_1>; - L1_I_101: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_101: l1-dcache { - compatible = "arm,arch-cache"; - }; - }; - - CPU6: cpu@102 { - device_type = "cpu"; - compatible = "qcom,kryo280"; - reg = <0x0 0x102>; - enable-method = "psci"; - cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; - next-level-cache = <&L2_1>; - L1_I_102: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_102: l1-dcache { - compatible = "arm,arch-cache"; - }; - }; - - CPU7: cpu@103 { - device_type = "cpu"; - compatible = "qcom,kryo280"; - reg = <0x0 0x103>; - enable-method = "psci"; - cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; - next-level-cache = <&L2_1>; - L1_I_103: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_103: l1-dcache { - compatible = "arm,arch-cache"; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU4>; - }; - - core1 { - cpu = <&CPU5>; - }; - - core2 { - cpu = <&CPU6>; - }; - - core3 { - cpu = <&CPU7>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "little-retention"; - /* CPU Retention (C2D), L2 Active */ - arm,psci-suspend-param = <0x00000002>; - entry-latency-us = <81>; - exit-latency-us = <86>; - min-residency-us = <504>; - }; - - LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { - compatible = "arm,idle-state"; - idle-state-name = "little-power-collapse"; - /* CPU + L2 Power Collapse (C3, D4) */ - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <814>; - exit-latency-us = <4562>; - min-residency-us = <9183>; - local-timer-stop; - }; - - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "big-retention"; - /* CPU Retention (C2D), L2 Active */ - arm,psci-suspend-param = <0x00000002>; - entry-latency-us = <79>; - exit-latency-us = <82>; - min-residency-us = <1302>; - }; - - BIG_CPU_SLEEP_1: cpu-sleep-1-1 { - compatible = "arm,idle-state"; - idle-state-name = "big-power-collapse"; - /* CPU + L2 Power Collapse (C3, D4) */ - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <724>; - exit-latency-us = <2027>; - min-residency-us = <9419>; - local-timer-stop; - }; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-msm8998", "qcom,scm"; - }; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - rpm-glink { - compatible = "qcom,glink-rpm"; - - interrupts = ; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8998"; - qcom,glink-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; - #clock-cells = <1>; - }; - - rpmpd: power-controller { - compatible = "qcom,msm8998-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = <16>; - }; - - rpmpd_opp_ret_plus: opp2 { - opp-level = <32>; - }; - - rpmpd_opp_min_svs: opp3 { - opp-level = <48>; - }; - - rpmpd_opp_low_svs: opp4 { - opp-level = <64>; - }; - - rpmpd_opp_svs: opp5 { - opp-level = <128>; - }; - - rpmpd_opp_svs_plus: opp6 { - opp-level = <192>; - }; - - rpmpd_opp_nom: opp7 { - opp-level = <256>; - }; - - rpmpd_opp_nom_plus: opp8 { - opp-level = <320>; - }; - - rpmpd_opp_turbo: opp9 { - opp-level = <384>; - }; - - rpmpd_opp_turbo_plus: opp10 { - opp-level = <512>; - }; - }; - }; - }; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-lpass { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - - interrupts = ; - - mboxes = <&apcs_glb 10>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - adsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - adsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-mpss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - interrupts = ; - mboxes = <&apcs_glb 14>; - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - interrupts = ; - mboxes = <&apcs_glb 26>; - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - slpi_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - slpi_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 1>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 2>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 3>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 4>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu4-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 7>; - - trips { - cpu4_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu5-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 8>; - - trips { - cpu5_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu6-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 9>; - - trips { - cpu6_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu7-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 10>; - - trips { - cpu7_alert0: trip-point0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_crit: cpu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - gpu-thermal-bottom { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 12>; - - trips { - gpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - gpu-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 13>; - - trips { - gpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - clust0-mhm-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 5>; - - trips { - cluster0_mhm_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - clust1-mhm-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 6>; - - trips { - cluster1_mhm_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster1-l2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 11>; - - trips { - cluster1_l2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 1>; - - trips { - modem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 2>; - - trips { - mem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - wlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 3>; - - trips { - wlan_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-dsp-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 4>; - - trips { - q6_dsp_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 5>; - - trips { - camera_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - multimedia-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 6>; - - trips { - multimedia_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-msm8998"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0x00100000 0xb0000>; - }; - - rpm_msg_ram: memory@778000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0x00778000 0x7000>; - }; - - qfprom: qfprom@780000 { - compatible = "qcom,qfprom"; - reg = <0x00780000 0x621c>; - #address-cells = <1>; - #size-cells = <1>; - - qusb2_hstx_trim: hstx-trim@423a { - reg = <0x423a 0x1>; - bits = <0 4>; - }; - }; - - tsens0: thermal@10ab000 { - compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; - reg = <0x010ab000 0x1000>, /* TM */ - <0x010aa000 0x1000>; /* SROT */ - #qcom,sensors = <14>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal@10ae000 { - compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; - reg = <0x010ae000 0x1000>, /* TM */ - <0x010ad000 0x1000>; /* SROT */ - #qcom,sensors = <8>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - anoc1_smmu: iommu@1680000 { - compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; - reg = <0x01680000 0x10000>; - #iommu-cells = <1>; - - #global-interrupts = <0>; - interrupts = - , - , - , - , - , - ; - }; - - anoc2_smmu: iommu@16c0000 { - compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; - reg = <0x016c0000 0x40000>; - #iommu-cells = <1>; - - #global-interrupts = <0>; - interrupts = - , - , - , - , - , - , - , - , - , - ; - }; - - pcie0: pci@1c00000 { - compatible = "qcom,pcie-msm8996"; - reg = <0x01c00000 0x2000>, - <0x1b000000 0xf1d>, - <0x1b000f20 0xa8>, - <0x1b100000 0x100000>; - reg-names = "parf", "dbi", "elbi", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - #address-cells = <3>; - #size-cells = <2>; - num-lanes = <1>; - phys = <&pciephy>; - phy-names = "pciephy"; - - ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>, - <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; - - #interrupt-cells = <1>; - interrupts = ; - interrupt-names = "msi"; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>; - clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux"; - - power-domains = <&gcc PCIE_0_GDSC>; - iommu-map = <0x100 &anoc1_smmu 0x1480 1>; - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - }; - - phy@1c06000 { - compatible = "qcom,msm8998-qmp-pcie-phy"; - reg = <0x01c06000 0x18c>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_CLKREF_CLK>; - clock-names = "aux", "cfg_ahb", "ref"; - - resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; - reset-names = "phy", "common"; - - vdda-phy-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l2a_1p2>; - - pciephy: lane@1c06800 { - reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; - #phy-cells = <0>; - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "pcie_0_pipe_clk_src"; - #clock-cells = <0>; - }; - }; - - ufshc: ufshc@1da4000 { - compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0x01da4000 0x2500>; - interrupts = ; - phys = <&ufsphy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - power-domains = <&gcc UFS_GDSC>; - #reset-cells = <1>; - - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - clocks = - <&gcc GCC_UFS_AXI_CLK>, - <&gcc GCC_AGGRE1_UFS_AXI_CLK>, - <&gcc GCC_UFS_AHB_CLK>, - <&gcc GCC_UFS_UNIPRO_CORE_CLK>, - <&rpmcc RPM_SMD_LN_BB_CLK1>, - <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; - freq-table-hz = - <50000000 200000000>, - <0 0>, - <0 0>, - <37500000 150000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; - - resets = <&gcc GCC_UFS_BCR>; - reset-names = "rst"; - }; - - ufsphy: phy@1da7000 { - compatible = "qcom,msm8998-qmp-ufs-phy"; - reg = <0x01da7000 0x18c>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clock-names = - "ref", - "ref_aux"; - clocks = - <&gcc GCC_UFS_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_AUX_CLK>; - - reset-names = "ufsphy"; - resets = <&ufshc 0>; - - ufsphy_lanes: lanes@1da7400 { - reg = <0x01da7400 0x128>, - <0x01da7600 0x1fc>, - <0x01da7c00 0x1dc>, - <0x01da7800 0x128>, - <0x01da7a00 0x1fc>; - #phy-cells = <0>; - }; - }; - - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0x01f40000 0x40000>; - }; - - tlmm: pinctrl@3400000 { - compatible = "qcom,msm8998-pinctrl"; - reg = <0x03400000 0xc00000>; - interrupts = ; - gpio-controller; - #gpio-cells = <0x2>; - interrupt-controller; - #interrupt-cells = <0x2>; - }; - - remoteproc_mss: remoteproc@4080000 { - compatible = "qcom,msm8998-mss-pil"; - reg = <0x04080000 0x100>, <0x04180000 0x20>; - reg-names = "qdsp6", "rmb"; - - interrupts-extended = - <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack", - "shutdown-ack"; - - clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, - <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, - <&gcc GCC_BOOT_ROM_AHB_CLK>, - <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, - <&gcc GCC_MSS_SNOC_AXI_CLK>, - <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, - <&rpmcc RPM_SMD_QDSS_CLK>, - <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "iface", "bus", "mem", "gpll0_mss", - "snoc_axi", "mnoc_axi", "qdss", "xo"; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - resets = <&gcc GCC_MSS_RESTART>; - reset-names = "mss_restart"; - - qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; - - power-domains = <&rpmpd MSM8998_VDDCX>, - <&rpmpd MSM8998_VDDMX>; - power-domain-names = "cx", "mx"; - - mba { - memory-region = <&mba_mem>; - }; - - mpss { - memory-region = <&mpss_mem>; - }; - - glink-edge { - interrupts = ; - label = "modem"; - qcom,remote-pid = <1>; - mboxes = <&apcs_glb 15>; - }; - }; - - gpucc: clock-controller@5065000 { - compatible = "qcom,msm8998-gpucc"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0x05065000 0x9000>; - - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&gcc GPLL0_OUT_MAIN>; - clock-names = "xo", - "gpll0"; - }; - - remoteproc_slpi: remoteproc@5800000 { - compatible = "qcom,msm8998-slpi-pas"; - reg = <0x05800000 0x4040>; - - interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - px-supply = <&vreg_lvs2a_1p8>; - - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; - clock-names = "xo", "aggre2"; - - memory-region = <&slpi_mem>; - - qcom,smem-states = <&slpi_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - power-domains = <&rpmpd MSM8998_SSCCX>; - power-domain-names = "ssc_cx"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "dsps"; - qcom,remote-pid = <3>; - mboxes = <&apcs_glb 27>; - }; - }; - - stm: stm@6002000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0x06002000 0x1000>, - <0x16280000 0x180000>; - reg-names = "stm-base", "stm-data-base"; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - port { - stm_out: endpoint { - remote-endpoint = <&funnel0_in7>; - }; - }; - }; - }; - - funnel1: funnel@6041000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x06041000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - port { - funnel0_out: endpoint { - remote-endpoint = - <&merge_funnel_in0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@7 { - reg = <7>; - funnel0_in7: endpoint { - remote-endpoint = <&stm_out>; - }; - }; - }; - }; - - funnel2: funnel@6042000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x06042000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - port { - funnel1_out: endpoint { - remote-endpoint = - <&merge_funnel_in1>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@6 { - reg = <6>; - funnel1_in6: endpoint { - remote-endpoint = - <&apss_merge_funnel_out>; - }; - }; - }; - }; - - funnel3: funnel@6045000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x06045000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - port { - merge_funnel_out: endpoint { - remote-endpoint = - <&etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - merge_funnel_in0: endpoint { - remote-endpoint = - <&funnel0_out>; - }; - }; - - port@1 { - reg = <1>; - merge_funnel_in1: endpoint { - remote-endpoint = - <&funnel1_out>; - }; - }; - }; - }; - - replicator1: replicator@6046000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0x06046000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - port { - replicator_out: endpoint { - remote-endpoint = <&etr_in>; - }; - }; - }; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = <&etf_out>; - }; - }; - }; - }; - - etf: etf@6047000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x06047000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = - <&replicator_in>; - }; - }; - }; - - in-ports { - port { - etf_in: endpoint { - remote-endpoint = - <&merge_funnel_out>; - }; - }; - }; - }; - - etr: etr@6048000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x06048000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - arm,scatter-gather; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = - <&replicator_out>; - }; - }; - }; - }; - - etm1: etm@7840000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x07840000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU0>; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = - <&apss_funnel_in0>; - }; - }; - }; - }; - - etm2: etm@7940000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x07940000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU1>; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = - <&apss_funnel_in1>; - }; - }; - }; - }; - - etm3: etm@7a40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x07a40000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU2>; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = - <&apss_funnel_in2>; - }; - }; - }; - }; - - etm4: etm@7b40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x07b40000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU3>; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = - <&apss_funnel_in3>; - }; - }; - }; - }; - - funnel4: funnel@7b60000 { /* APSS Funnel */ - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x07b60000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - port { - apss_funnel_out: endpoint { - remote-endpoint = - <&apss_merge_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - apss_funnel_in0: endpoint { - remote-endpoint = - <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - apss_funnel_in1: endpoint { - remote-endpoint = - <&etm1_out>; - }; - }; - - port@2 { - reg = <2>; - apss_funnel_in2: endpoint { - remote-endpoint = - <&etm2_out>; - }; - }; - - port@3 { - reg = <3>; - apss_funnel_in3: endpoint { - remote-endpoint = - <&etm3_out>; - }; - }; - - port@4 { - reg = <4>; - apss_funnel_in4: endpoint { - remote-endpoint = - <&etm4_out>; - }; - }; - - port@5 { - reg = <5>; - apss_funnel_in5: endpoint { - remote-endpoint = - <&etm5_out>; - }; - }; - - port@6 { - reg = <6>; - apss_funnel_in6: endpoint { - remote-endpoint = - <&etm6_out>; - }; - }; - - port@7 { - reg = <7>; - apss_funnel_in7: endpoint { - remote-endpoint = - <&etm7_out>; - }; - }; - }; - }; - - funnel5: funnel@7b70000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x07b70000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - out-ports { - port { - apss_merge_funnel_out: endpoint { - remote-endpoint = - <&funnel1_in6>; - }; - }; - }; - - in-ports { - port { - apss_merge_funnel_in: endpoint { - remote-endpoint = - <&apss_funnel_out>; - }; - }; - }; - }; - - etm5: etm@7c40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x07c40000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU4>; - - port{ - etm4_out: endpoint { - remote-endpoint = <&apss_funnel_in4>; - }; - }; - }; - - etm6: etm@7d40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x07d40000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU5>; - - port{ - etm5_out: endpoint { - remote-endpoint = <&apss_funnel_in5>; - }; - }; - }; - - etm7: etm@7e40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x07e40000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU6>; - - port{ - etm6_out: endpoint { - remote-endpoint = <&apss_funnel_in6>; - }; - }; - }; - - etm8: etm@7f40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x07f40000 0x1000>; - status = "disabled"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; - clock-names = "apb_pclk", "atclk"; - - cpu = <&CPU7>; - - port{ - etm7_out: endpoint { - remote-endpoint = <&apss_funnel_in7>; - }; - }; - }; - - spmi_bus: spmi@800f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0800f000 0x1000>, - <0x08400000 0x1000000>, - <0x09400000 0x1000000>, - <0x0a400000 0x220000>, - <0x0800a000 0x3000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - usb3: usb@a8f8800 { - compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; - reg = <0x0a8f8800 0x400>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, - <&gcc GCC_USB30_MASTER_CLK>, - <&gcc GCC_AGGRE1_USB3_AXI_CLK>, - <&gcc GCC_USB30_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SLEEP_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep"; - - assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_MASTER_CLK>; - assigned-clock-rates = <19200000>, <120000000>; - - interrupts = , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq"; - - power-domains = <&gcc USB_30_GDSC>; - - resets = <&gcc GCC_USB_30_BCR>; - - usb3_dwc3: dwc3@a800000 { - compatible = "snps,dwc3"; - reg = <0x0a800000 0xcd00>; - interrupts = ; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&qusb2phy>, <&usb1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - }; - }; - - usb3phy: phy@c010000 { - compatible = "qcom,msm8998-qmp-usb3-phy"; - reg = <0x0c010000 0x18c>; - status = "disabled"; - #clock-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_USB3_CLKREF_CLK>; - clock-names = "aux", "cfg_ahb", "ref"; - - resets = <&gcc GCC_USB3_PHY_BCR>, - <&gcc GCC_USB3PHY_PHY_BCR>; - reset-names = "phy", "common"; - - usb1_ssphy: lane@c010200 { - reg = <0xc010200 0x128>, - <0xc010400 0x200>, - <0xc010c00 0x20c>, - <0xc010600 0x128>, - <0xc010800 0x200>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; - }; - - qusb2phy: phy@c012000 { - compatible = "qcom,msm8998-qusb2-phy"; - reg = <0x0c012000 0x2a8>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_RX1_USB2_CLKREF_CLK>; - clock-names = "cfg_ahb", "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - - nvmem-cells = <&qusb2_hstx_trim>; - }; - - sdhc2: sdhci@c0a4900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; - reg-names = "hc_mem", "core_mem"; - - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - - clock-names = "iface", "core", "xo"; - clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, - <&xo>; - bus-width = <4>; - status = "disabled"; - }; - - blsp1_dma: dma@c144000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x0c144000 0x25000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - qcom,controlled-remotely; - num-channels = <18>; - qcom,num-ees = <4>; - }; - - blsp1_uart3: serial@c171000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x0c171000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart3_on>; - status = "disabled"; - }; - - blsp1_i2c1: i2c@c175000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c175000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c2: i2c@c176000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c176000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c3: i2c@c177000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c177000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c4: i2c@c178000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c178000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c5: i2c@c179000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c179000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp1_i2c6: i2c@c17a000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c17a000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp2_uart1: serial@c1b0000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x0c1b0000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - blsp2_i2c0: i2c@c1b5000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c1b5000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp2_i2c1: i2c@c1b6000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c1b6000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp2_i2c2: i2c@c1b7000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c1b7000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp2_i2c3: i2c@c1b8000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c1b8000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp2_i2c4: i2c@c1b9000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c1b9000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - blsp2_i2c5: i2c@c1ba000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c1ba000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - remoteproc_adsp: remoteproc@17300000 { - compatible = "qcom,msm8998-adsp-pas"; - reg = <0x17300000 0x4040>; - - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "xo"; - - memory-region = <&adsp_mem>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - power-domains = <&rpmpd MSM8998_VDDCX>; - power-domain-names = "cx"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "lpass"; - qcom,remote-pid = <2>; - mboxes = <&apcs_glb 9>; - }; - }; - - apcs_glb: mailbox@17911000 { - compatible = "qcom,msm8998-apcs-hmss-global"; - reg = <0x17911000 0x1000>; - - #mbox-cells = <1>; - }; - - timer@17920000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x17920000 0x1000>; - - frame@17921000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x17921000 0x1000>, - <0x17922000 0x1000>; - }; - - frame@17923000 { - frame-number = <1>; - interrupts = ; - reg = <0x17923000 0x1000>; - status = "disabled"; - }; - - frame@17924000 { - frame-number = <2>; - interrupts = ; - reg = <0x17924000 0x1000>; - status = "disabled"; - }; - - frame@17925000 { - frame-number = <3>; - interrupts = ; - reg = <0x17925000 0x1000>; - status = "disabled"; - }; - - frame@17926000 { - frame-number = <4>; - interrupts = ; - reg = <0x17926000 0x1000>; - status = "disabled"; - }; - - frame@17927000 { - frame-number = <5>; - interrupts = ; - reg = <0x17927000 0x1000>; - status = "disabled"; - }; - - frame@17928000 { - frame-number = <6>; - interrupts = ; - reg = <0x17928000 0x1000>; - status = "disabled"; - }; - }; - - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - reg = <0x17a00000 0x10000>, /* GICD */ - <0x17b00000 0x100000>; /* GICR * 8 */ - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x20000>; - interrupts = ; - }; - - wifi: wifi@18800000 { - compatible = "qcom,wcn3990-wifi"; - status = "disabled"; - reg = <0x18800000 0x800000>; - reg-names = "membase"; - memory-region = <&wlan_msa_mem>; - clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>; - clock-names = "cxo_ref_clk_pin"; - interrupts = - , - , - , - , - , - , - , - , - , - , - , - ; - iommus = <&anoc2_smmu 0x1900>, - <&anoc2_smmu 0x1901>; - qcom,snoc-host-cap-8bit-quirk; - }; - }; -}; - -#include "msm8998-pins.dtsi" diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi deleted file mode 100644 index 57af0b4a3..000000000 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// Copyright (c) 2019, The Linux Foundation. All rights reserved. - -#include -#include -#include -#include -#include - -&spmi_bus { - pm6150_lsid0: pmic@0 { - compatible = "qcom,pm6150", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm6150_pon: pon@800 { - compatible = "qcom,pm8998-pon"; - reg = <0x800>; - mode-bootloader = <0x2>; - mode-recovery = <0x1>; - - pm6150_pwrkey: pwrkey { - compatible = "qcom,pm8941-pwrkey"; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; - }; - - pm6150_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; - io-channels = <&pm6150_adc ADC5_DIE_TEMP>; - io-channel-names = "thermal"; - #thermal-sensor-cells = <0>; - }; - - pm6150_adc: adc@3100 { - compatible = "qcom,spmi-adc5"; - reg = <0x3100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - - adc-chan@6 { - reg = ; - label = "die_temp"; - }; - }; - - pm6150_gpio: gpios@c000 { - compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm6150_gpio 0 0 10>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pm6150_lsid1: pmic@1 { - compatible = "qcom,pm6150", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi deleted file mode 100644 index f84027b50..000000000 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// Copyright (c) 2019, The Linux Foundation. All rights reserved. - -#include -#include - -&spmi_bus { - pm6150l_lsid4: pmic@4 { - compatible = "qcom,pm6150l", "qcom,spmi-pmic"; - reg = <0x4 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm6150l_gpio: gpios@c000 { - compatible = "qcom,pm6150l-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm6150l_gpio 0 0 12>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pm6150l_lsid5: pmic@5 { - compatible = "qcom,pm6150l", "qcom,spmi-pmic"; - reg = <0x5 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi deleted file mode 100644 index 2e6a6f6c3..000000000 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, Konrad Dybcio - */ - -#include -#include -#include - -&spmi_bus { - - pmic@0 { - compatible = "qcom,pm660", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>, <0x6100>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - }; - - pon: pon@800 { - compatible = "qcom,pm8916-pon"; - - reg = <0x800>; - - pwrkey { - compatible = "qcom,pm8941-pwrkey"; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; - - }; - - pm660_gpios: gpios@c000 { - compatible = "qcom,pm660-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm660_gpios 0 0 13>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/pm660l.dtsi b/arch/arm64/boot/dts/qcom/pm660l.dtsi deleted file mode 100644 index edba6de02..000000000 --- a/arch/arm64/boot/dts/qcom/pm660l.dtsi +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, Konrad Dybcio - */ - -#include -#include -#include - -&spmi_bus { - - pmic@2 { - compatible = "qcom,pm660l", "qcom,spmi-pmic"; - reg = <0x2 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm660l_gpios: gpios@c000 { - compatible = "qcom,pm660l-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm660l_gpios 0 0 12>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pmic@3 { - compatible = "qcom,pm660l", "qcom,spmi-pmic"; - reg = <0x3 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; - diff --git a/arch/arm64/boot/dts/qcom/pm8004.dtsi b/arch/arm64/boot/dts/qcom/pm8004.dtsi deleted file mode 100644 index 0abd1abe1..000000000 --- a/arch/arm64/boot/dts/qcom/pm8004.dtsi +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include - -&spmi_bus { - - pm8004_lsid4: pmic@4 { - compatible = "qcom,pm8004", "qcom,spmi-pmic"; - reg = <0x4 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pm8004_lsid5: pmic@5 { - compatible = "qcom,pm8004", "qcom,spmi-pmic"; - reg = <0x5 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - pm8004_spmi_regulators: regulators { - compatible = "qcom,pm8004-regulators"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/pm8005.dtsi b/arch/arm64/boot/dts/qcom/pm8005.dtsi deleted file mode 100644 index 3f97607d8..000000000 --- a/arch/arm64/boot/dts/qcom/pm8005.dtsi +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* Copyright 2018 Google LLC. */ - -#include -#include - -&spmi_bus { - pm8005_lsid0: pmic@4 { - compatible = "qcom,pm8005", "qcom,spmi-pmic"; - reg = <0x4 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8005_gpio: gpios@c000 { - compatible = "qcom,pm8005-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm8005_gpio 0 0 4>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - }; - - pm8005_lsid1: pmic@5 { - compatible = "qcom,pm8005", "qcom,spmi-pmic"; - reg = <0x5 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/pm8009.dtsi b/arch/arm64/boot/dts/qcom/pm8009.dtsi deleted file mode 100644 index b126d7e7e..000000000 --- a/arch/arm64/boot/dts/qcom/pm8009.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2020, Linaro Limited - */ - -#include - -&spmi_bus { - pmic@a { - compatible = "qcom,pm8009", "qcom,spmi-pmic"; - reg = <0xa SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8009_pon: pon@800 { - compatible = "qcom,pm8916-pon"; - reg = <0x0800>; - }; - - pm8009_gpios: gpio@c000 { - compatible = "qcom,pm8005-gpio"; - reg = <0xc000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pmic@b { - compatible = "qcom,pm8009", "qcom,spmi-pmic"; - reg = <0xb SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi deleted file mode 100644 index 82edcd74c..000000000 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2019, Linaro Limited - */ - -#include -#include -#include -#include - -/ { - thermal-zones { - pm8150 { - polling-delay-passive = <100>; - polling-delay = <0>; - - thermal-sensors = <&pm8150_temp>; - - trips { - trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - trip1 { - temperature = <115000>; - hysteresis = <0>; - type = "hot"; - }; - - trip2 { - temperature = <145000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - }; -}; - -&spmi_bus { - pm8150_0: pmic@0 { - compatible = "qcom,pm8150", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pon: power-on@800 { - compatible = "qcom,pm8998-pon"; - reg = <0x0800>; - pwrkey { - compatible = "qcom,pm8941-pwrkey"; - interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - - status = "disabled"; - }; - }; - - pm8150_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; - io-channels = <&pm8150_adc ADC5_DIE_TEMP>; - io-channel-names = "thermal"; - #thermal-sensor-cells = <0>; - }; - - pm8150_adc: adc@3100 { - compatible = "qcom,spmi-adc5"; - reg = <0x3100>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - - ref-gnd@0 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "ref_gnd"; - }; - - vref-1p25@1 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "vref_1p25"; - }; - - die-temp@6 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "die_temp"; - }; - }; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; - - status = "disabled"; - }; - - pm8150_gpios: gpio@c000 { - compatible = "qcom,pm8150-gpio"; - reg = <0xc000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pmic@1 { - compatible = "qcom,pm8150", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi deleted file mode 100644 index e112e8876..000000000 --- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2019, Linaro Limited - */ - -#include -#include -#include - -/ { - thermal-zones { - pm8150b { - polling-delay-passive = <100>; - polling-delay = <0>; - - thermal-sensors = <&pm8150b_temp>; - - trips { - trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - trip1 { - temperature = <115000>; - hysteresis = <0>; - type = "hot"; - }; - - trip2 { - temperature = <145000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - }; -}; - -&spmi_bus { - pmic@2 { - compatible = "qcom,pm8150b", "qcom,spmi-pmic"; - reg = <0x2 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - power-on@800 { - compatible = "qcom,pm8916-pon"; - reg = <0x0800>; - - status = "disabled"; - }; - - pm8150b_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; - io-channels = <&pm8150b_adc ADC5_DIE_TEMP>; - io-channel-names = "thermal"; - #thermal-sensor-cells = <0>; - }; - - pm8150b_adc: adc@3100 { - compatible = "qcom,spmi-adc5"; - reg = <0x3100>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - - ref-gnd@0 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "ref_gnd"; - }; - - vref-1p25@1 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "vref_1p25"; - }; - - die-temp@6 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "die_temp"; - }; - - chg-temp@9 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "chg_temp"; - }; - }; - - pm8150b_gpios: gpio@c000 { - compatible = "qcom,pm8150b-gpio"; - reg = <0xc000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pmic@3 { - compatible = "qcom,pm8150b", "qcom,spmi-pmic"; - reg = <0x3 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi deleted file mode 100644 index 62139538b..000000000 --- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2019, Linaro Limited - */ - -#include -#include -#include - -/ { - thermal-zones { - pm8150l { - polling-delay-passive = <100>; - polling-delay = <0>; - - thermal-sensors = <&pm8150l_temp>; - - trips { - trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - trip1 { - temperature = <115000>; - hysteresis = <0>; - type = "hot"; - }; - - trip2 { - temperature = <145000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - }; -}; - -&spmi_bus { - pmic@4 { - compatible = "qcom,pm8150l", "qcom,spmi-pmic"; - reg = <0x4 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - power-on@800 { - compatible = "qcom,pm8916-pon"; - reg = <0x0800>; - - status = "disabled"; - }; - - pm8150l_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; - io-channels = <&pm8150l_adc ADC5_DIE_TEMP>; - io-channel-names = "thermal"; - #thermal-sensor-cells = <0>; - }; - - pm8150l_adc: adc@3100 { - compatible = "qcom,spmi-adc5"; - reg = <0x3100>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - - ref-gnd@0 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "ref_gnd"; - }; - - vref-1p25@1 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "vref_1p25"; - }; - - die-temp@6 { - reg = ; - qcom,pre-scaling = <1 1>; - label = "die_temp"; - }; - }; - - pm8150l_gpios: gpio@c000 { - compatible = "qcom,pm8150l-gpio"; - reg = <0xc000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pmic@5 { - compatible = "qcom,pm8150l", "qcom,spmi-pmic"; - reg = <0x5 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi deleted file mode 100644 index 42180f1b5..000000000 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ /dev/null @@ -1,168 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include - -&spmi_bus { - - pm8916_0: pmic@0 { - compatible = "qcom,pm8916", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pon@800 { - compatible = "qcom,pm8916-pon"; - reg = <0x800>; - mode-bootloader = <0x2>; - mode-recovery = <0x1>; - - pwrkey { - compatible = "qcom,pm8941-pwrkey"; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; - - pm8916_resin: resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - status = "disabled"; - }; - - watchdog { - compatible = "qcom,pm8916-wdt"; - interrupts = <0x0 0x8 6 IRQ_TYPE_EDGE_RISING>; - timeout-sec = <60>; - }; - }; - - pm8916_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; - io-channels = <&pm8916_vadc VADC_DIE_TEMP>; - io-channel-names = "thermal"; - #thermal-sensor-cells = <0>; - }; - - pm8916_vadc: adc@3100 { - compatible = "qcom,spmi-vadc"; - reg = <0x3100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - - adc-chan@0 { - reg = ; - qcom,pre-scaling = <1 10>; - }; - adc-chan@7 { - reg = ; - qcom,pre-scaling = <1 3>; - }; - adc-chan@8 { - reg = ; - }; - adc-chan@9 { - reg = ; - }; - adc-chan@a { - reg = ; - }; - adc-chan@e { - reg = ; - }; - adc-chan@f { - reg = ; - }; - }; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - }; - - pm8916_mpps: mpps@a000 { - compatible = "qcom,pm8916-mpp"; - reg = <0xa000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, - <0 0xa1 0 IRQ_TYPE_NONE>, - <0 0xa2 0 IRQ_TYPE_NONE>, - <0 0xa3 0 IRQ_TYPE_NONE>; - }; - - pm8916_gpios: gpios@c000 { - compatible = "qcom,pm8916-gpio"; - reg = <0xc000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, - <0 0xc1 0 IRQ_TYPE_NONE>, - <0 0xc2 0 IRQ_TYPE_NONE>, - <0 0xc3 0 IRQ_TYPE_NONE>; - }; - }; - - pm8916_1: pmic@1 { - compatible = "qcom,pm8916", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8916_vib: vibrator@c000 { - compatible = "qcom,pm8916-vib"; - reg = <0xc000>; - status = "disabled"; - }; - - wcd_codec: audio-codec@f000 { - compatible = "qcom,pm8916-wcd-analog-codec"; - reg = <0xf000>; - reg-names = "pmic-codec-core"; - clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; - clock-names = "mclk"; - interrupt-parent = <&spmi_bus>; - interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>, - <0x1 0xf0 0x1 IRQ_TYPE_NONE>, - <0x1 0xf0 0x2 IRQ_TYPE_NONE>, - <0x1 0xf0 0x3 IRQ_TYPE_NONE>, - <0x1 0xf0 0x4 IRQ_TYPE_NONE>, - <0x1 0xf0 0x5 IRQ_TYPE_NONE>, - <0x1 0xf0 0x6 IRQ_TYPE_NONE>, - <0x1 0xf0 0x7 IRQ_TYPE_NONE>, - <0x1 0xf1 0x0 IRQ_TYPE_NONE>, - <0x1 0xf1 0x1 IRQ_TYPE_NONE>, - <0x1 0xf1 0x2 IRQ_TYPE_NONE>, - <0x1 0xf1 0x3 IRQ_TYPE_NONE>, - <0x1 0xf1 0x4 IRQ_TYPE_NONE>, - <0x1 0xf1 0x5 IRQ_TYPE_NONE>; - interrupt-names = "cdc_spk_cnp_int", - "cdc_spk_clip_int", - "cdc_spk_ocp_int", - "mbhc_ins_rem_det1", - "mbhc_but_rel_det", - "mbhc_but_press_det", - "mbhc_ins_rem_det", - "mbhc_switch_int", - "cdc_ear_ocp_int", - "cdc_hphr_ocp_int", - "cdc_hphl_ocp_det", - "cdc_ear_cnp_int", - "cdc_hphr_cnp_int", - "cdc_hphl_cnp_int"; - vdd-cdc-io-supply = <&pm8916_l5>; - vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>; - vdd-micbias-supply = <&pm8916_l13>; - #sound-dai-cells = <1>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi deleted file mode 100644 index 7e4f77774..000000000 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include - -&spmi_bus { - - pmic@0 { - compatible = "qcom,pm8994", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>, <0x6100>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - }; - - pon@800 { - compatible = "qcom,pm8916-pon"; - - reg = <0x800>; - mode-bootloader = <0x2>; - mode-recovery = <0x1>; - - pwrkey { - compatible = "qcom,pm8941-pwrkey"; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; - - }; - - pm8994_gpios: gpios@c000 { - compatible = "qcom,pm8994-gpio"; - reg = <0xc000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, - <0 0xc1 0 IRQ_TYPE_NONE>, - <0 0xc2 0 IRQ_TYPE_NONE>, - <0 0xc3 0 IRQ_TYPE_NONE>, - <0 0xc4 0 IRQ_TYPE_NONE>, - <0 0xc5 0 IRQ_TYPE_NONE>, - <0 0xc6 0 IRQ_TYPE_NONE>, - <0 0xc7 0 IRQ_TYPE_NONE>, - <0 0xc8 0 IRQ_TYPE_NONE>, - <0 0xc9 0 IRQ_TYPE_NONE>, - <0 0xca 0 IRQ_TYPE_NONE>, - <0 0xcb 0 IRQ_TYPE_NONE>, - <0 0xcc 0 IRQ_TYPE_NONE>, - <0 0xcd 0 IRQ_TYPE_NONE>, - <0 0xce 0 IRQ_TYPE_NONE>, - <0 0xcf 0 IRQ_TYPE_NONE>, - <0 0xd0 0 IRQ_TYPE_NONE>, - <0 0xd1 0 IRQ_TYPE_NONE>, - <0 0xd2 0 IRQ_TYPE_NONE>, - <0 0xd3 0 IRQ_TYPE_NONE>, - <0 0xd4 0 IRQ_TYPE_NONE>, - <0 0xd5 0 IRQ_TYPE_NONE>; - }; - - pm8994_mpps: mpps@a000 { - compatible = "qcom,pm8994-mpp"; - reg = <0xa000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, - <0 0xa1 0 IRQ_TYPE_NONE>, - <0 0xa2 0 IRQ_TYPE_NONE>, - <0 0xa3 0 IRQ_TYPE_NONE>, - <0 0xa4 0 IRQ_TYPE_NONE>, - <0 0xa5 0 IRQ_TYPE_NONE>, - <0 0xa6 0 IRQ_TYPE_NONE>, - <0 0xa7 0 IRQ_TYPE_NONE>; - }; - }; - - pmic@1 { - compatible = "qcom,pm8994", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8994_spmi_regulators: regulators { - compatible = "qcom,pm8994-regulators"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi deleted file mode 100644 index 67283d60e..000000000 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* Copyright 2018 Google LLC. */ - -#include -#include -#include -#include -#include - -/ { - thermal-zones { - pm8998 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&pm8998_temp>; - - trips { - pm8998_alert0: pm8998-alert0 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - pm8998_crit: pm8998-crit { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; -}; - -&spmi_bus { - pm8998_lsid0: pmic@0 { - compatible = "qcom,pm8998", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8998_pon: pon@800 { - compatible = "qcom,pm8998-pon"; - - reg = <0x800>; - mode-bootloader = <0x2>; - mode-recovery = <0x1>; - - pm8998_pwrkey: pwrkey { - compatible = "qcom,pm8941-pwrkey"; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; - }; - - pm8998_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; - io-channels = <&pm8998_adc ADC5_DIE_TEMP>; - io-channel-names = "thermal"; - #thermal-sensor-cells = <0>; - }; - - pm8998_coincell: coincell@2800 { - compatible = "qcom,pm8941-coincell"; - reg = <0x2800>; - - status = "disabled"; - }; - - pm8998_adc: adc@3100 { - compatible = "qcom,spmi-adc-rev2"; - reg = <0x3100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - - adc-chan@6 { - reg = ; - label = "die_temp"; - }; - }; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>, <0x6100>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - }; - - pm8998_gpio: gpios@c000 { - compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm8998_gpio 0 0 26>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - }; - - pm8998_lsid1: pmic@1 { - compatible = "qcom,pm8998", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi deleted file mode 100644 index e5ed28ab9..000000000 --- a/arch/arm64/boot/dts/qcom/pmi8994.dtsi +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include - -&spmi_bus { - - pmic@2 { - compatible = "qcom,pmi8994", "qcom,spmi-pmic"; - reg = <0x2 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pmi8994_gpios: gpios@c000 { - compatible = "qcom,pmi8994-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pmi8994_gpios 0 0 10>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pmic@3 { - compatible = "qcom,pmi8994", "qcom,spmi-pmic"; - reg = <0x3 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pmi8994_spmi_regulators: regulators { - compatible = "qcom,pmi8994-regulators"; - #address-cells = <1>; - #size-cells = <1>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi deleted file mode 100644 index d016b1296..000000000 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include - -&spmi_bus { - pmi8998_lsid0: pmic@2 { - compatible = "qcom,pmi8998", "qcom,spmi-pmic"; - reg = <0x2 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pmi8998_gpio: gpios@c000 { - compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pmi8998_gpio 0 0 14>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pmi8998_lsid1: pmic@3 { - compatible = "qcom,pmi8998", "qcom,spmi-pmic"; - reg = <0x3 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - labibb { - compatible = "qcom,pmi8998-lab-ibb"; - - ibb: ibb { - interrupts = <0x3 0xdc 0x2 IRQ_TYPE_EDGE_RISING>; - }; - - lab: lab { - interrupts = <0x3 0xde 0x0 IRQ_TYPE_EDGE_RISING>; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi deleted file mode 100644 index ff4005186..000000000 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, Linaro Limited - -#include -#include -#include -#include - -/ { - thermal-zones { - pms405 { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&pms405_temp>; - - trips { - pms405_alert0: pms405-alert0 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - pms405_crit: pms405-crit { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; -}; - -&spmi_bus { - pms405_0: pms405@0 { - compatible = "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pms405_gpios: gpio@c000 { - compatible = "qcom,pms405-gpio"; - reg = <0xc000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, - <0 0xc1 0 IRQ_TYPE_NONE>, - <0 0xc2 0 IRQ_TYPE_NONE>, - <0 0xc3 0 IRQ_TYPE_NONE>, - <0 0xc4 0 IRQ_TYPE_NONE>, - <0 0xc5 0 IRQ_TYPE_NONE>, - <0 0xc6 0 IRQ_TYPE_NONE>, - <0 0xc7 0 IRQ_TYPE_NONE>, - <0 0xc8 0 IRQ_TYPE_NONE>, - <0 0xc9 0 IRQ_TYPE_NONE>, - <0 0xca 0 IRQ_TYPE_NONE>, - <0 0xcb 0 IRQ_TYPE_NONE>; - }; - - pon@800 { - compatible = "qcom,pms405-pon"; - reg = <0x0800>; - mode-bootloader = <0x2>; - mode-recovery = <0x1>; - - pwrkey { - compatible = "qcom,pm8941-pwrkey"; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; - }; - - pms405_temp: temp-alarm@2400 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0x2400>; - interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; - io-channels = <&pms405_adc ADC5_DIE_TEMP>; - io-channel-names = "thermal"; - #thermal-sensor-cells = <0>; - }; - - pms405_adc: adc@3100 { - compatible = "qcom,pms405-adc", "qcom,spmi-adc-rev2"; - reg = <0x3100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - - ref_gnd@0 { - reg = ; - qcom,pre-scaling = <1 1>; - }; - - vref_1p25@1 { - reg = ; - qcom,pre-scaling = <1 1>; - }; - - pon_1: vph_pwr@131 { - reg = ; - qcom,pre-scaling = <1 3>; - }; - - die_temp@6 { - reg = ; - qcom,pre-scaling = <1 1>; - }; - - pa_therm1: thermistor1@77 { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - qcom,pre-scaling = <1 1>; - }; - - pa_therm3: thermistor3@79 { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - qcom,pre-scaling = <1 1>; - }; - - xo_therm: xo_temp@76 { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - qcom,pre-scaling = <1 1>; - }; - }; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; - }; - }; - - pms405_1: pms405@1 { - compatible = "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - - pms405_spmi_regulators: regulators { - compatible = "qcom,pms405-regulators"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts b/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts deleted file mode 100644 index 937eb4555..000000000 --- a/arch/arm64/boot/dts/qcom/qcs404-evb-1000.dts +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, Linaro Limited - -/dts-v1/; - -#include "qcs404-evb.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. QCS404 EVB 1000"; - compatible = "qcom,qcs404-evb-1000", "qcom,qcs404-evb", - "qcom,qcs404"; -}; diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts b/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts deleted file mode 100644 index 08d5d5122..000000000 --- a/arch/arm64/boot/dts/qcom/qcs404-evb-4000.dts +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, Linaro Limited - -/dts-v1/; - -#include -#include "qcs404-evb.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. QCS404 EVB 4000"; - compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb", - "qcom,qcs404"; -}; - -ðernet { - status = "okay"; - - snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 10000>; - - pinctrl-names = "default"; - pinctrl-0 = <ðernet_defaults>; - - phy-handle = <&phy1>; - phy-mode = "rgmii"; - mdio { - #address-cells = <0x1>; - #size-cells = <0x0>; - compatible = "snps,dwmac-mdio"; - phy1: phy@4 { - compatible = "ethernet-phy-ieee802.3-c22"; - device_type = "ethernet-phy"; - reg = <0x4>; - }; - }; -}; - -&tlmm { - ethernet_defaults: ethernet-defaults { - int { - pins = "gpio61"; - function = "rgmii_int"; - bias-disable; - drive-strength = <2>; - }; - mdc { - pins = "gpio76"; - function = "rgmii_mdc"; - bias-pull-up; - }; - mdio { - pins = "gpio75"; - function = "rgmii_mdio"; - bias-pull-up; - }; - tx { - pins = "gpio67", "gpio66", "gpio65", "gpio64"; - function = "rgmii_tx"; - bias-pull-up; - drive-strength = <16>; - }; - rx { - pins = "gpio73", "gpio72", "gpio71", "gpio70"; - function = "rgmii_rx"; - bias-disable; - drive-strength = <2>; - }; - tx-ctl { - pins = "gpio68"; - function = "rgmii_ctl"; - bias-pull-up; - drive-strength = <16>; - }; - rx-ctl { - pins = "gpio74"; - function = "rgmii_ctl"; - bias-disable; - drive-strength = <2>; - }; - tx-ck { - pins = "gpio63"; - function = "rgmii_ck"; - bias-pull-up; - drive-strength = <16>; - }; - rx-ck { - pins = "gpio69"; - function = "rgmii_ck"; - bias-disable; - drive-strength = <2>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi deleted file mode 100644 index a80c57848..000000000 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ /dev/null @@ -1,395 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, Linaro Limited - -#include -#include "qcs404.dtsi" -#include "pms405.dtsi" -#include -#include - -/ { - aliases { - serial0 = &blsp1_uart2; - serial1 = &blsp1_uart3; - }; - - chosen { - stdout-path = "serial0"; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-always-on; - regulator-boot-on; - }; - - vdd_ch0_3p3: - vdd_esmps3_3p3: vdd-esmps3-3p3-regulator { - compatible = "regulator-fixed"; - regulator-name = "eSMPS3_3P3"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - usb3_vbus_reg: regulator-usb3-vbus { - compatible = "regulator-fixed"; - regulator-name = "VBUS_BOOST_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_vbus_boost_pin>; - vin-supply = <&vph_pwr>; - enable-active-high; - - /* TODO: Drop this when introducing role switching */ - regulator-always-on; - }; -}; - -&blsp1_uart3 { - status = "okay"; - - bluetooth { - compatible = "qcom,wcn3990-bt"; - vddio-supply = <&vreg_l6_1p8>; - vddxo-supply = <&vreg_l5_1p8>; - vddrf-supply = <&vreg_l1_1p3>; - vddch0-supply = <&vdd_ch0_3p3>; - - local-bd-address = [ 02 00 00 00 5a ad ]; - - max-speed = <3200000>; - }; -}; - -&blsp1_dma { - qcom,controlled-remotely; -}; - -&blsp2_dma { - qcom,controlled-remotely; -}; - -&gcc { - protected-clocks = , - , - , - , - <141>, /* GCC_WCSS_Q6_AHB_CLK */ - <142>; /* GCC_WCSS_Q6_AXIM_CLK */ -}; - -&pms405_spmi_regulators { - vdd_s3-supply = <&vph_pwr>; - - pms405_s3: s3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd_apc"; - regulator-initial-mode = <1>; - regulator-min-microvolt = <1048000>; - regulator-max-microvolt = <1384000>; - }; -}; - -&pcie { - status = "okay"; - - perst-gpio = <&tlmm 43 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&perst_state>; -}; - -&pcie_phy { - status = "okay"; - - vdda-vp-supply = <&vreg_l3_1p05>; - vdda-vph-supply = <&vreg_l5_1p8>; -}; - -&remoteproc_adsp { - status = "okay"; -}; - -&remoteproc_cdsp { - status = "okay"; -}; - -&remoteproc_wcss { - status = "okay"; -}; - -&rpm_requests { - pms405-regulators { - compatible = "qcom,rpm-pms405-regulators"; - - vdd_s1-supply = <&vph_pwr>; - vdd_s2-supply = <&vph_pwr>; - vdd_s3-supply = <&vph_pwr>; - vdd_s4-supply = <&vph_pwr>; - vdd_s5-supply = <&vph_pwr>; - vdd_l1_l2-supply = <&vreg_s5_1p35>; - vdd_l3_l8-supply = <&vreg_s5_1p35>; - vdd_l4-supply = <&vreg_s5_1p35>; - vdd_l5_l6-supply = <&vreg_s4_1p8>; - vdd_l7-supply = <&vph_pwr>; - vdd_l9-supply = <&vreg_s5_1p35>; - vdd_l10_l11_l12_l13-supply = <&vph_pwr>; - - vreg_s4_1p8: s4 { - regulator-min-microvolt = <1728000>; - regulator-max-microvolt = <1920000>; - }; - - vreg_s5_1p35: s5 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_l1_1p3: l1 { - regulator-min-microvolt = <1240000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_l2_1p275: l2 { - regulator-min-microvolt = <1048000>; - regulator-max-microvolt = <1280000>; - }; - - vreg_l3_1p05: l3 { - regulator-min-microvolt = <1048000>; - regulator-max-microvolt = <1160000>; - }; - - vreg_l4_1p2: l4 { - regulator-min-microvolt = <1144000>; - regulator-max-microvolt = <1256000>; - }; - - vreg_l5_1p8: l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vreg_l6_1p8: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vreg_l7_1p8: l7 { - regulator-min-microvolt = <1616000>; - regulator-max-microvolt = <3000000>; - }; - - vreg_l8_1p2: l8 { - regulator-min-microvolt = <1136000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_l10_3p3: l10 { - regulator-min-microvolt = <2936000>; - regulator-max-microvolt = <3088000>; - }; - - vreg_l11_sdc2: l11 { - regulator-min-microvolt = <2696000>; - regulator-max-microvolt = <3304000>; - }; - - vreg_l12_3p3: l12 { - regulator-min-microvolt = <3050000>; - regulator-max-microvolt = <3300000>; - }; - - vreg_l13_3p3: l13 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - }; -}; - -&sdcc1 { - status = "okay"; - - supports-cqe; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - non-removable; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; -}; - -&tlmm { - perst_state: perst { - pins = "gpio43"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - output-low; - }; - - sdc1_on: sdc1-on { - clk { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <16>; - }; - - cmd { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - data { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <10>; - }; - - rclk { - pins = "sdc1_rclk"; - bias-pull-down; - }; - }; - - sdc1_off: sdc1-off { - clk { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <2>; - }; - - cmd { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - data { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <2>; - }; - - rclk { - pins = "sdc1_rclk"; - bias-pull-down; - }; - }; - - usb3_id_pin: usb3-id-pin { - pinmux { - pins = "gpio116"; - function = "gpio"; - }; - - pinconf { - pins = "gpio116"; - drive-strength = <2>; - bias-pull-up; - input-enable; - }; - }; -}; - -&pms405_gpios { - usb_vbus_boost_pin: usb-vbus-boost-pin { - pinconf { - pins = "gpio3"; - function = PMIC_GPIO_FUNC_NORMAL; - output-low; - power-source = <1>; - }; - }; - usb3_vbus_pin: usb3-vbus-pin { - pinconf { - pins = "gpio12"; - function = PMIC_GPIO_FUNC_NORMAL; - input-enable; - bias-pull-down; - power-source = <1>; - }; - }; -}; - -&usb2 { - status = "okay"; -}; - -&usb2_phy_sec { - vdd-supply = <&vreg_l4_1p2>; - vdda1p8-supply = <&vreg_l5_1p8>; - vdda3p3-supply = <&vreg_l12_3p3>; - status = "okay"; -}; - -&usb3 { - status = "okay"; - - dwc3@7580000 { - dr_mode = "host"; - }; -}; - -&usb2_phy_prim { - vdd-supply = <&vreg_l4_1p2>; - vdda1p8-supply = <&vreg_l5_1p8>; - vdda3p3-supply = <&vreg_l12_3p3>; - status = "okay"; -}; - -&usb3_phy { - vdd-supply = <&vreg_l3_1p05>; - vdda1p8-supply = <&vreg_l5_1p8>; - status = "okay"; -}; - -&wifi { - status = "okay"; - vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>; - vdd-1.8-xo-supply = <&vreg_l5_1p8>; - vdd-1.3-rfa-supply = <&vreg_l1_1p3>; -}; - -/* PINCTRL - additions to nodes defined in qcs404.dtsi */ - -&blsp1_uart2_default { - rx { - drive-strength = <2>; - bias-disable; - }; - - tx { - drive-strength = <2>; - bias-disable; - }; -}; - -&blsp1_uart3_default { - cts { - pins = "gpio84"; - bias-disable; - }; - - rts-tx { - pins = "gpio85", "gpio82"; - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio83"; - bias-pull-up; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi deleted file mode 100644 index b654b802e..000000000 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ /dev/null @@ -1,1642 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2018, Linaro Limited - -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CPU0: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x100>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - next-level-cache = <&L2_0>; - #cooling-cells = <2>; - clocks = <&apcs_glb>; - operating-points-v2 = <&cpu_opp_table>; - power-domains = <&cpr>; - power-domain-names = "cpr"; - }; - - CPU1: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x101>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - next-level-cache = <&L2_0>; - #cooling-cells = <2>; - clocks = <&apcs_glb>; - operating-points-v2 = <&cpu_opp_table>; - power-domains = <&cpr>; - power-domain-names = "cpr"; - }; - - CPU2: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x102>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - next-level-cache = <&L2_0>; - #cooling-cells = <2>; - clocks = <&apcs_glb>; - operating-points-v2 = <&cpu_opp_table>; - power-domains = <&cpr>; - power-domain-names = "cpr"; - }; - - CPU3: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x103>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - next-level-cache = <&L2_0>; - #cooling-cells = <2>; - clocks = <&apcs_glb>; - operating-points-v2 = <&cpu_opp_table>; - power-domains = <&cpr>; - power-domain-names = "cpr"; - }; - - L2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - idle-state-name = "standalone-power-collapse"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <125>; - exit-latency-us = <180>; - min-residency-us = <595>; - local-timer-stop; - }; - }; - }; - - cpu_opp_table: cpu-opp-table { - compatible = "operating-points-v2-kryo-cpu"; - opp-shared; - - opp-1094400000 { - opp-hz = /bits/ 64 <1094400000>; - required-opps = <&cpr_opp1>; - }; - opp-1248000000 { - opp-hz = /bits/ 64 <1248000000>; - required-opps = <&cpr_opp2>; - }; - opp-1401600000 { - opp-hz = /bits/ 64 <1401600000>; - required-opps = <&cpr_opp3>; - }; - }; - - cpr_opp_table: cpr-opp-table { - compatible = "operating-points-v2-qcom-level"; - - cpr_opp1: opp1 { - opp-level = <1>; - qcom,opp-fuse-level = <1>; - }; - cpr_opp2: opp2 { - opp-level = <2>; - qcom,opp-fuse-level = <2>; - }; - cpr_opp3: opp3 { - opp-level = <3>; - qcom,opp-fuse-level = <3>; - }; - }; - - firmware { - scm: scm { - compatible = "qcom,scm-qcs404", "qcom,scm"; - #reset-cells = <1>; - }; - }; - - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0 0x80000000 0 0>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - tz_apps_mem: memory@85900000 { - reg = <0 0x85900000 0 0x500000>; - no-map; - }; - - xbl_mem: memory@85e00000 { - reg = <0 0x85e00000 0 0x100000>; - no-map; - }; - - smem_region: memory@85f00000 { - reg = <0 0x85f00000 0 0x200000>; - no-map; - }; - - tz_mem: memory@86100000 { - reg = <0 0x86100000 0 0x300000>; - no-map; - }; - - wlan_fw_mem: memory@86400000 { - reg = <0 0x86400000 0 0x1100000>; - no-map; - }; - - adsp_fw_mem: memory@87500000 { - reg = <0 0x87500000 0 0x1a00000>; - no-map; - }; - - cdsp_fw_mem: memory@88f00000 { - reg = <0 0x88f00000 0 0x600000>; - no-map; - }; - - wlan_msa_mem: memory@89500000 { - reg = <0 0x89500000 0 0x100000>; - no-map; - }; - - uefi_mem: memory@9f800000 { - reg = <0 0x9f800000 0 0x800000>; - no-map; - }; - }; - - rpm-glink { - compatible = "qcom,glink-rpm"; - - interrupts = ; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: glink-channel { - compatible = "qcom,rpm-qcs404"; - qcom,glink-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-qcs404"; - #clock-cells = <1>; - }; - - rpmpd: power-controller { - compatible = "qcom,qcs404-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = <16>; - }; - - rpmpd_opp_ret_plus: opp2 { - opp-level = <32>; - }; - - rpmpd_opp_min_svs: opp3 { - opp-level = <48>; - }; - - rpmpd_opp_low_svs: opp4 { - opp-level = <64>; - }; - - rpmpd_opp_svs: opp5 { - opp-level = <128>; - }; - - rpmpd_opp_svs_plus: opp6 { - opp-level = <192>; - }; - - rpmpd_opp_nom: opp7 { - opp-level = <256>; - }; - - rpmpd_opp_nom_plus: opp8 { - opp-level = <320>; - }; - - rpmpd_opp_turbo: opp9 { - opp-level = <384>; - }; - - rpmpd_opp_turbo_no_cpr: opp10 { - opp-level = <416>; - }; - - rpmpd_opp_turbo_plus: opp11 { - opp-level = <512>; - }; - }; - }; - }; - }; - - smem { - compatible = "qcom,smem"; - - memory-region = <&smem_region>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - - hwlocks = <&tcsr_mutex 3>; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - - soc: soc@0 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - turingcc: clock-controller@800000 { - compatible = "qcom,qcs404-turingcc"; - reg = <0x00800000 0x30000>; - clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>; - - #clock-cells = <1>; - #reset-cells = <1>; - - status = "disabled"; - }; - - rpm_msg_ram: memory@60000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0x00060000 0x6000>; - }; - - usb3_phy: phy@78000 { - compatible = "qcom,usb-ss-28nm-phy"; - reg = <0x00078000 0x400>; - #phy-cells = <0>; - clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, - <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, - <&gcc GCC_USB3_PHY_PIPE_CLK>; - clock-names = "ref", "ahb", "pipe"; - resets = <&gcc GCC_USB3_PHY_BCR>, - <&gcc GCC_USB3PHY_PHY_BCR>; - reset-names = "com", "phy"; - status = "disabled"; - }; - - usb2_phy_prim: phy@7a000 { - compatible = "qcom,usb-hs-28nm-femtophy"; - reg = <0x0007a000 0x200>; - #phy-cells = <0>; - clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, - <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, - <&gcc GCC_USB2A_PHY_SLEEP_CLK>; - clock-names = "ref", "ahb", "sleep"; - resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, - <&gcc GCC_USB2A_PHY_BCR>; - reset-names = "phy", "por"; - status = "disabled"; - }; - - usb2_phy_sec: phy@7c000 { - compatible = "qcom,usb-hs-28nm-femtophy"; - reg = <0x0007c000 0x200>; - #phy-cells = <0>; - clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, - <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, - <&gcc GCC_USB2A_PHY_SLEEP_CLK>; - clock-names = "ref", "ahb", "sleep"; - resets = <&gcc GCC_QUSB2_PHY_BCR>, - <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; - reset-names = "phy", "por"; - status = "disabled"; - }; - - qfprom: qfprom@a4000 { - compatible = "qcom,qfprom"; - reg = <0x000a4000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - tsens_caldata: caldata@d0 { - reg = <0x1f8 0x14>; - }; - cpr_efuse_speedbin: speedbin@13c { - reg = <0x13c 0x4>; - bits = <2 3>; - }; - cpr_efuse_quot_offset1: qoffset1@231 { - reg = <0x231 0x4>; - bits = <4 7>; - }; - cpr_efuse_quot_offset2: qoffset2@232 { - reg = <0x232 0x4>; - bits = <3 7>; - }; - cpr_efuse_quot_offset3: qoffset3@233 { - reg = <0x233 0x4>; - bits = <2 7>; - }; - cpr_efuse_init_voltage1: ivoltage1@229 { - reg = <0x229 0x4>; - bits = <4 6>; - }; - cpr_efuse_init_voltage2: ivoltage2@22a { - reg = <0x22a 0x4>; - bits = <2 6>; - }; - cpr_efuse_init_voltage3: ivoltage3@22b { - reg = <0x22b 0x4>; - bits = <0 6>; - }; - cpr_efuse_quot1: quot1@22b { - reg = <0x22b 0x4>; - bits = <6 12>; - }; - cpr_efuse_quot2: quot2@22d { - reg = <0x22d 0x4>; - bits = <2 12>; - }; - cpr_efuse_quot3: quot3@230 { - reg = <0x230 0x4>; - bits = <0 12>; - }; - cpr_efuse_ring1: ring1@228 { - reg = <0x228 0x4>; - bits = <0 3>; - }; - cpr_efuse_ring2: ring2@228 { - reg = <0x228 0x4>; - bits = <4 3>; - }; - cpr_efuse_ring3: ring3@229 { - reg = <0x229 0x4>; - bits = <0 3>; - }; - cpr_efuse_revision: revision@218 { - reg = <0x218 0x4>; - bits = <3 3>; - }; - }; - - rng: rng@e3000 { - compatible = "qcom,prng-ee"; - reg = <0x000e3000 0x1000>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; - - bimc: interconnect@400000 { - reg = <0x00400000 0x80000>; - compatible = "qcom,qcs404-bimc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_BIMC_CLK>, - <&rpmcc RPM_SMD_BIMC_A_CLK>; - }; - - tsens: thermal-sensor@4a9000 { - compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; - reg = <0x004a9000 0x1000>, /* TM */ - <0x004a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>; - nvmem-cell-names = "calib"; - #qcom,sensors = <10>; - interrupts = ; - interrupt-names = "uplow"; - #thermal-sensor-cells = <1>; - }; - - pcnoc: interconnect@500000 { - reg = <0x00500000 0x15080>; - compatible = "qcom,qcs404-pcnoc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_PNOC_CLK>, - <&rpmcc RPM_SMD_PNOC_A_CLK>; - }; - - snoc: interconnect@580000 { - reg = <0x00580000 0x23080>; - compatible = "qcom,qcs404-snoc"; - #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_SNOC_CLK>, - <&rpmcc RPM_SMD_SNOC_A_CLK>; - }; - - remoteproc_cdsp: remoteproc@b00000 { - compatible = "qcom,qcs404-cdsp-pas"; - reg = <0x00b00000 0x4040>; - - interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&xo_board>, - <&gcc GCC_CDSP_CFG_AHB_CLK>, - <&gcc GCC_CDSP_TBU_CLK>, - <&gcc GCC_BIMC_CDSP_CLK>, - <&turingcc TURING_WRAPPER_AON_CLK>, - <&turingcc TURING_Q6SS_AHBS_AON_CLK>, - <&turingcc TURING_Q6SS_AHBM_AON_CLK>, - <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; - clock-names = "xo", - "sway", - "tbu", - "bimc", - "ahb_aon", - "q6ss_slave", - "q6ss_master", - "q6_axim"; - - resets = <&gcc GCC_CDSP_RESTART>; - reset-names = "restart"; - - qcom,halt-regs = <&tcsr 0x19004>; - - memory-region = <&cdsp_fw_mem>; - - qcom,smem-states = <&cdsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - - qcom,remote-pid = <5>; - mboxes = <&apcs_glb 12>; - - label = "cdsp"; - }; - }; - - usb3: usb@7678800 { - compatible = "qcom,dwc3"; - reg = <0x07678800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - clocks = <&gcc GCC_USB30_MASTER_CLK>, - <&gcc GCC_SYS_NOC_USB3_CLK>, - <&gcc GCC_USB30_SLEEP_CLK>, - <&gcc GCC_USB30_MOCK_UTMI_CLK>; - clock-names = "core", "iface", "sleep", "mock_utmi"; - assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - status = "disabled"; - - dwc3@7580000 { - compatible = "snps,dwc3"; - reg = <0x07580000 0xcd00>; - interrupts = ; - phys = <&usb2_phy_sec>, <&usb3_phy>; - phy-names = "usb2-phy", "usb3-phy"; - snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - snps,usb3_lpm_capable; - dr_mode = "otg"; - }; - }; - - usb2: usb@79b8800 { - compatible = "qcom,dwc3"; - reg = <0x079b8800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, - <&gcc GCC_PCNOC_USB2_CLK>, - <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, - <&gcc GCC_USB20_MOCK_UTMI_CLK>; - clock-names = "core", "iface", "sleep", "mock_utmi"; - assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, - <&gcc GCC_USB_HS_SYSTEM_CLK>; - assigned-clock-rates = <19200000>, <133333333>; - status = "disabled"; - - dwc3@78c0000 { - compatible = "snps,dwc3"; - reg = <0x078c0000 0xcc00>; - interrupts = ; - phys = <&usb2_phy_prim>; - phy-names = "usb2-phy"; - snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - snps,usb3_lpm_capable; - dr_mode = "peripheral"; - }; - }; - - tlmm: pinctrl@1000000 { - compatible = "qcom,qcs404-pinctrl"; - reg = <0x01000000 0x200000>, - <0x01300000 0x200000>, - <0x07b00000 0x200000>; - reg-names = "south", "north", "east"; - interrupts = ; - gpio-ranges = <&tlmm 0 0 120>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - - blsp1_i2c0_default: blsp1-i2c0-default { - pins = "gpio32", "gpio33"; - function = "blsp_i2c0"; - }; - - blsp1_i2c1_default: blsp1-i2c1-default { - pins = "gpio24", "gpio25"; - function = "blsp_i2c1"; - }; - - blsp1_i2c2_default: blsp1-i2c2-default { - sda { - pins = "gpio19"; - function = "blsp_i2c_sda_a2"; - }; - - scl { - pins = "gpio20"; - function = "blsp_i2c_scl_a2"; - }; - }; - - blsp1_i2c3_default: blsp1-i2c3-default { - pins = "gpio84", "gpio85"; - function = "blsp_i2c3"; - }; - - blsp1_i2c4_default: blsp1-i2c4-default { - pins = "gpio117", "gpio118"; - function = "blsp_i2c4"; - }; - - blsp1_uart0_default: blsp1-uart0-default { - pins = "gpio30", "gpio31", "gpio32", "gpio33"; - function = "blsp_uart0"; - }; - - blsp1_uart1_default: blsp1-uart1-default { - pins = "gpio22", "gpio23"; - function = "blsp_uart1"; - }; - - blsp1_uart2_default: blsp1-uart2-default { - rx { - pins = "gpio18"; - function = "blsp_uart_rx_a2"; - }; - - tx { - pins = "gpio17"; - function = "blsp_uart_tx_a2"; - }; - }; - - blsp1_uart3_default: blsp1-uart3-default { - pins = "gpio82", "gpio83", "gpio84", "gpio85"; - function = "blsp_uart3"; - }; - - blsp2_i2c0_default: blsp2-i2c0-default { - pins = "gpio28", "gpio29"; - function = "blsp_i2c5"; - }; - - blsp1_spi0_default: blsp1-spi0-default { - pins = "gpio30", "gpio31", "gpio32", "gpio33"; - function = "blsp_spi0"; - }; - - blsp1_spi1_default: blsp1-spi1-default { - pins = "gpio22", "gpio23", "gpio24", "gpio25"; - function = "blsp_spi1"; - }; - - blsp1_spi2_default: blsp1-spi2-default { - pins = "gpio17", "gpio18", "gpio19", "gpio20"; - function = "blsp_spi2"; - }; - - blsp1_spi3_default: blsp1-spi3-default { - pins = "gpio82", "gpio83", "gpio84", "gpio85"; - function = "blsp_spi3"; - }; - - blsp1_spi4_default: blsp1-spi4-default { - pins = "gpio37", "gpio38", "gpio117", "gpio118"; - function = "blsp_spi4"; - }; - - blsp2_spi0_default: blsp2-spi0-default { - pins = "gpio26", "gpio27", "gpio28", "gpio29"; - function = "blsp_spi5"; - }; - - blsp2_uart0_default: blsp2-uart0-default { - pins = "gpio26", "gpio27", "gpio28", "gpio29"; - function = "blsp_uart5"; - }; - }; - - gcc: clock-controller@1800000 { - compatible = "qcom,gcc-qcs404"; - reg = <0x01800000 0x80000>; - #clock-cells = <1>; - #reset-cells = <1>; - - assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; - assigned-clock-rates = <19200000>; - }; - - tcsr_mutex_regs: syscon@1905000 { - compatible = "syscon"; - reg = <0x01905000 0x20000>; - }; - - tcsr: syscon@1937000 { - compatible = "syscon"; - reg = <0x01937000 0x25000>; - }; - - spmi_bus: spmi@200f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0200f000 0x001000>, - <0x02400000 0x800000>, - <0x02c00000 0x800000>, - <0x03800000 0x200000>, - <0x0200a000 0x002100>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - remoteproc_wcss: remoteproc@7400000 { - compatible = "qcom,qcs404-wcss-pas"; - reg = <0x07400000 0x4040>; - - interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, - <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&xo_board>; - clock-names = "xo"; - - memory-region = <&wlan_fw_mem>; - - qcom,smem-states = <&wcss_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - - qcom,remote-pid = <1>; - mboxes = <&apcs_glb 16>; - - label = "wcss"; - }; - }; - - pcie_phy: phy@7786000 { - compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; - reg = <0x07786000 0xb8>; - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, - <&gcc 21>; - reset-names = "phy", "pipe"; - - clock-output-names = "pcie_0_pipe_clk"; - #phy-cells = <0>; - - status = "disabled"; - }; - - sdcc1: sdcc@7804000 { - compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x07804000 0x1000>, <0x7805000 0x1000>; - reg-names = "hc", "cqhci"; - - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; - - status = "disabled"; - }; - - blsp1_dma: dma@7884000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x07884000 0x25000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - status = "okay"; - }; - - blsp1_uart0: serial@78af000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078af000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp1_dma 1>, <&blsp1_dma 0>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart0_default>; - status = "disabled"; - }; - - blsp1_uart1: serial@78b0000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078b0000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp1_dma 3>, <&blsp1_dma 2>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart1_default>; - status = "disabled"; - }; - - blsp1_uart2: serial@78b1000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078b1000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp1_dma 5>, <&blsp1_dma 4>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart2_default>; - status = "okay"; - }; - - ethernet: ethernet@7a80000 { - compatible = "qcom,qcs404-ethqos"; - reg = <0x07a80000 0x10000>, - <0x07a96000 0x100>; - reg-names = "stmmaceth", "rgmii"; - clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; - clocks = <&gcc GCC_ETH_AXI_CLK>, - <&gcc GCC_ETH_SLAVE_AHB_CLK>, - <&gcc GCC_ETH_PTP_CLK>, - <&gcc GCC_ETH_RGMII_CLK>; - interrupts = , - ; - interrupt-names = "macirq", "eth_lpi"; - - snps,tso; - rx-fifo-depth = <4096>; - tx-fifo-depth = <4096>; - - status = "disabled"; - }; - - wifi: wifi@a000000 { - compatible = "qcom,wcn3990-wifi"; - reg = <0xa000000 0x800000>; - reg-names = "membase"; - memory-region = <&wlan_msa_mem>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; - status = "disabled"; - }; - - blsp1_uart3: serial@78b2000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078b2000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp1_dma 7>, <&blsp1_dma 6>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart3_default>; - status = "disabled"; - }; - - blsp1_i2c0: i2c@78b5000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b5000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c0_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_spi0: spi@78b5000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b5000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_spi0_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_i2c1: i2c@78b6000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b6000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c1_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_spi1: spi@78b6000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b6000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_spi1_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_i2c2: i2c@78b7000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b7000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c2_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_spi2: spi@78b7000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b7000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_spi2_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_i2c3: i2c@78b8000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b8000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c3_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_spi3: spi@78b8000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b8000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_spi3_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_i2c4: i2c@78b9000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x078b9000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_i2c4_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp1_spi4: spi@78b9000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x078b9000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_spi4_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_dma: dma@7ac4000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x07ac4000 0x17000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - status = "disabled"; - }; - - blsp2_uart0: serial@7aef000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x07aef000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp2_dma 1>, <&blsp2_dma 0>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp2_uart0_default>; - status = "disabled"; - }; - - blsp2_i2c0: i2c@7af5000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x07af5000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp2_i2c0_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_spi0: spi@7af5000 { - compatible = "qcom,spi-qup-v2.2.1"; - reg = <0x07af5000 0x600>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>; - clock-names = "iface", "core"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp2_spi0_default>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - imem@8600000 { - compatible = "simple-mfd"; - reg = <0x08600000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0x08600000 0x1000>; - - pil-reloc@94c { - compatible = "qcom,pil-reloc-info"; - reg = <0x94c 0xc8>; - }; - }; - - intc: interrupt-controller@b000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0b000000 0x1000>, - <0x0b002000 0x1000>; - }; - - apcs_glb: mailbox@b011000 { - compatible = "qcom,qcs404-apcs-apps-global", "syscon"; - reg = <0x0b011000 0x1000>; - #mbox-cells = <1>; - clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; - clock-names = "pll", "aux"; - #clock-cells = <0>; - }; - - apcs_hfpll: clock-controller@b016000 { - compatible = "qcom,hfpll"; - reg = <0x0b016000 0x30>; - #clock-cells = <0>; - clock-output-names = "apcs_hfpll"; - clocks = <&xo_board>; - clock-names = "xo"; - }; - - watchdog@b017000 { - compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; - reg = <0x0b017000 0x1000>; - clocks = <&sleep_clk>; - }; - - cpr: power-controller@b018000 { - compatible = "qcom,qcs404-cpr", "qcom,cpr"; - reg = <0x0b018000 0x1000>; - interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; - clocks = <&xo_board>; - clock-names = "ref"; - vdd-apc-supply = <&pms405_s3>; - #power-domain-cells = <0>; - operating-points-v2 = <&cpr_opp_table>; - acc-syscon = <&tcsr>; - - nvmem-cells = <&cpr_efuse_quot_offset1>, - <&cpr_efuse_quot_offset2>, - <&cpr_efuse_quot_offset3>, - <&cpr_efuse_init_voltage1>, - <&cpr_efuse_init_voltage2>, - <&cpr_efuse_init_voltage3>, - <&cpr_efuse_quot1>, - <&cpr_efuse_quot2>, - <&cpr_efuse_quot3>, - <&cpr_efuse_ring1>, - <&cpr_efuse_ring2>, - <&cpr_efuse_ring3>, - <&cpr_efuse_revision>; - nvmem-cell-names = "cpr_quotient_offset1", - "cpr_quotient_offset2", - "cpr_quotient_offset3", - "cpr_init_voltage1", - "cpr_init_voltage2", - "cpr_init_voltage3", - "cpr_quotient1", - "cpr_quotient2", - "cpr_quotient3", - "cpr_ring_osc1", - "cpr_ring_osc2", - "cpr_ring_osc3", - "cpr_fuse_revision"; - }; - - timer@b120000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x0b120000 0x1000>; - clock-frequency = <19200000>; - - frame@b121000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x0b121000 0x1000>, - <0x0b122000 0x1000>; - }; - - frame@b123000 { - frame-number = <1>; - interrupts = ; - reg = <0x0b123000 0x1000>; - status = "disabled"; - }; - - frame@b124000 { - frame-number = <2>; - interrupts = ; - reg = <0x0b124000 0x1000>; - status = "disabled"; - }; - - frame@b125000 { - frame-number = <3>; - interrupts = ; - reg = <0x0b125000 0x1000>; - status = "disabled"; - }; - - frame@b126000 { - frame-number = <4>; - interrupts = ; - reg = <0x0b126000 0x1000>; - status = "disabled"; - }; - - frame@b127000 { - frame-number = <5>; - interrupts = ; - reg = <0xb127000 0x1000>; - status = "disabled"; - }; - - frame@b128000 { - frame-number = <6>; - interrupts = ; - reg = <0x0b128000 0x1000>; - status = "disabled"; - }; - }; - - remoteproc_adsp: remoteproc@c700000 { - compatible = "qcom,qcs404-adsp-pas"; - reg = <0x0c700000 0x4040>; - - interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&xo_board>; - clock-names = "xo"; - - memory-region = <&adsp_fw_mem>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - - qcom,remote-pid = <2>; - mboxes = <&apcs_glb 8>; - - label = "adsp"; - }; - }; - - pcie: pci@10000000 { - compatible = "qcom,pcie-qcs404", "snps,dw-pcie"; - reg = <0x10000000 0xf1d>, - <0x10000f20 0xa8>, - <0x07780000 0x2000>, - <0x10001000 0x2000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */ - <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */ - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>; - clock-names = "iface", "aux", "master_bus", "slave_bus"; - - resets = <&gcc 18>, - <&gcc 17>, - <&gcc 15>, - <&gcc 19>, - <&gcc GCC_PCIE_0_BCR>, - <&gcc 16>; - reset-names = "axi_m", - "axi_s", - "axi_m_sticky", - "pipe_sticky", - "pwr", - "ahb"; - - phys = <&pcie_phy>; - phy-names = "pciephy"; - - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - smp2p-adsp { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - interrupts = ; - mboxes = <&apcs_glb 10>; - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - adsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - adsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - interrupts = ; - mboxes = <&apcs_glb 14>; - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - cdsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - cdsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-wcss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - interrupts = ; - mboxes = <&apcs_glb 18>; - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - wcss_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - wcss_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - thermal-zones { - aoss-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 0>; - - trips { - aoss_alert0: trip-point0 { - temperature = <105000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-hvx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 1>; - - trips { - q6_hvx_alert0: trip-point0 { - temperature = <105000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - lpass-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 2>; - - trips { - lpass_alert0: trip-point0 { - temperature = <105000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - wlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 3>; - - trips { - wlan_alert0: trip-point0 { - temperature = <105000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 4>; - - trips { - cluster_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster_alert1: trip-point1 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - cluster_crit: cluster_crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cluster_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 5>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - cpu0_alert1: trip-point1 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu0_crit: cpu_crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 6>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - cpu1_alert1: trip-point1 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu1_crit: cpu_crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 7>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - cpu2_alert1: trip-point1 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu2_crit: cpu_crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 8>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - cpu3_alert1: trip-point1 { - temperature = <105000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu3_crit: cpu_crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 9>; - - trips { - gpu_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts deleted file mode 100644 index 949fee694..000000000 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ /dev/null @@ -1,693 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, Linaro Ltd. - */ - -/dts-v1/; - -#include -#include -#include "sm8250.dtsi" -#include "pm8150.dtsi" -#include "pm8150b.dtsi" -#include "pm8150l.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Robotics RB5"; - compatible = "qcom,qrb5165-rb5", "qcom,sm8250"; - - aliases { - serial0 = &uart12; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - dc12v: dc12v-regulator { - compatible = "regulator-fixed"; - regulator-name = "DC12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - leds { - compatible = "gpio-leds"; - - user4 { - label = "green:user4"; - gpios = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "panic-indicator"; - default-state = "off"; - }; - - wlan { - label = "yellow:wlan"; - gpios = <&pm8150_gpios 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - bt { - label = "blue:bt"; - gpios = <&pm8150_gpios 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "bluetooth-power"; - default-state = "off"; - }; - - }; - - vbat: vbat-regulator { - compatible = "regulator-fixed"; - regulator-name = "VBAT"; - vin-supply = <&vreg_l11c_3p3>; - regulator-min-microvolt = <4200000>; - regulator-max-microvolt = <4200000>; - regulator-always-on; - }; - - vbat_som: vbat-som-regulator { - compatible = "regulator-fixed"; - regulator-name = "VBAT_SOM"; - vin-supply = <&dc12v>; - regulator-min-microvolt = <4200000>; - regulator-max-microvolt = <4200000>; - regulator-always-on; - }; - - vdc_3v3: vdc-3v3-regulator { - compatible = "regulator-fixed"; - regulator-name = "VDC_3V3"; - vin-supply = <&dc12v>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdc_5v: vdc-5v-regulator { - compatible = "regulator-fixed"; - regulator-name = "VDC_5V"; - - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vreg_l11c_3p3>; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - }; - - vreg_s4a_1p8: vreg-s4a-1p8 { - compatible = "regulator-fixed"; - regulator-name = "vreg_s4a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; -}; - -&apps_rsc { - pm8009-rpmh-regulators { - compatible = "qcom,pm8009-1-rpmh-regulators"; - qcom,pmic-id = "f"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-l2-supply = <&vreg_s8c_1p3>; - vdd-l5-l6-supply = <&vreg_bob>; - vdd-l7-supply = <&vreg_s4a_1p8>; - - vreg_s2f_0p95: smps2 { - regulator-name = "vreg_s2f_0p95"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <952000>; - regulator-initial-mode = ; - }; - - vreg_l1f_1p1: ldo1 { - regulator-name = "vreg_l1f_1p1"; - regulator-min-microvolt = <1104000>; - regulator-max-microvolt = <1104000>; - regulator-initial-mode = ; - }; - - vreg_l2f_1p2: ldo2 { - regulator-name = "vreg_l2f_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l6f_2p8: ldo6 { - regulator-name = "vreg_l6f_2p8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-initial-mode = ; - }; - - vreg_l7f_1p8: ldo7 { - regulator-name = "vreg_l7f_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - }; - - pm8150-rpmh-regulators { - compatible = "qcom,pm8150-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-s8-supply = <&vph_pwr>; - vdd-s9-supply = <&vph_pwr>; - vdd-s10-supply = <&vph_pwr>; - vdd-l2-l10-supply = <&vreg_bob>; - vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p95>; - vdd-l6-l9-supply = <&vreg_s8c_1p3>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>; - vdd-l13-l16-l17-supply = <&vreg_bob>; - - vreg_l2a_3p1: ldo2 { - regulator-name = "vreg_l2a_3p1"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l3a_0p9: ldo3 { - regulator-name = "vreg_l3a_0p9"; - regulator-min-microvolt = <928000>; - regulator-max-microvolt = <932000>; - regulator-initial-mode = ; - }; - - vreg_l5a_0p88: ldo5 { - regulator-name = "vreg_l5a_0p88"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - - vreg_l6a_1p2: ldo6 { - regulator-name = "vreg_l6a_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l7a_1p7: ldo7 { - regulator-name = "vreg_l7a_1p7"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l9a_1p2: ldo9 { - regulator-name = "vreg_l9a_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l10a_1p8: ldo10 { - regulator-name = "vreg_l10a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l12a_1p8: ldo12 { - regulator-name = "vreg_l12a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l13a_ts_3p0: ldo13 { - regulator-name = "vreg_l13a_ts_3p0"; - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - - vreg_l14a_1p8: ldo14 { - regulator-name = "vreg_l14a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1880000>; - regulator-initial-mode = ; - }; - - vreg_l15a_1p8: ldo15 { - regulator-name = "vreg_l15a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l16a_2p7: ldo16 { - regulator-name = "vreg_l16a_2p7"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l17a_3p0: ldo17 { - regulator-name = "vreg_l17a_3p0"; - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - - vreg_l18a_0p92: ldo18 { - regulator-name = "vreg_l18a_0p92"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <912000>; - regulator-initial-mode = ; - }; - - vreg_s5a_1p9: smps5 { - regulator-name = "vreg_s5a_1p9"; - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - - vreg_s6a_0p95: smps6 { - regulator-name = "vreg_s6a_0p95"; - regulator-min-microvolt = <920000>; - regulator-max-microvolt = <1128000>; - regulator-initial-mode = ; - }; - }; - - pm8150l-rpmh-regulators { - compatible = "qcom,pm8150l-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-s8-supply = <&vph_pwr>; - vdd-l1-l8-supply = <&vreg_s4a_1p8>; - vdd-l2-l3-supply = <&vreg_s8c_1p3>; - vdd-l4-l5-l6-supply = <&vreg_bob>; - vdd-l7-l11-supply = <&vreg_bob>; - vdd-l9-l10-supply = <&vreg_bob>; - vdd-bob-supply = <&vph_pwr>; - - vreg_bob: bob { - regulator-name = "vreg_bob"; - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <4000000>; - regulator-initial-mode = ; - }; - - vreg_l1c_1p8: ldo1 { - regulator-name = "vreg_l1c_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l2c_1p2: ldo2 { - regulator-name = "vreg_l2c_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l3c_0p8: ldo3 { - regulator-name = "vreg_l3c_0p8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vreg_l4c_1p7: ldo4 { - regulator-name = "vreg_l4c_1p7"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l5c_1p8: ldo5 { - regulator-name = "vreg_l5c_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l6c_2p96: ldo6 { - regulator-name = "vreg_l6c_2p96"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l7c_cam_vcm0_2p85: ldo7 { - regulator-name = "vreg_l7c_cam_vcm0_2p85"; - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <3104000>; - regulator-initial-mode = ; - }; - - vreg_l8c_1p8: ldo8 { - regulator-name = "vreg_l8c_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l9c_2p96: ldo9 { - regulator-name = "vreg_l9c_2p96"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l10c_3p0: ldo10 { - regulator-name = "vreg_l10c_3p0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-initial-mode = ; - }; - - vreg_l11c_3p3: ldo11 { - regulator-name = "vreg_l11c_3p3"; - regulator-min-microvolt = <3296000>; - regulator-max-microvolt = <3296000>; - regulator-initial-mode = ; - regulator-always-on; - }; - - vreg_s8c_1p3: smps8 { - regulator-name = "vreg_s8c_1p3"; - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - regulator-initial-mode = ; - }; - }; -}; - -/* LS-I2C0 */ -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -/* LS-I2C1 */ -&i2c15 { - status = "okay"; -}; - -&pm8150_gpios { - gpio-reserved-ranges = <1 1>, <3 2>, <7 1>; - gpio-line-names = - "NC", - "OPTION2", - "PM_GPIO-F", - "PM_SLP_CLK_IN", - "OPTION1", - "VOL_UP_N", - "PM8250_GPIO7", /* Blue LED */ - "SP_ARI_PWR_ALARM", - "GPIO_9_P", /* Yellow LED */ - "GPIO_10_P"; /* Green LED */ -}; - -&pm8150b_gpios { - gpio-line-names = - "NC", - "NC", - "NC", - "NC", - "HAP_BOOST_EN", /* SOM */ - "SMB_STAT", /* SOM */ - "NC", - "NC", - "SDM_FORCE_USB_BOOT", - "NC", - "NC", - "NC"; -}; - -&pm8150l_gpios { - gpio-line-names = - "NC", - "PM3003A_EN", - "NC", - "NC", - "PM_GPIO5", /* HDMI RST_N */ - "PM_GPIO-A", /* PWM */ - "PM_GPIO7", - "NC", - "NC", - "PM_GPIO-B", - "NC", - "PM3003A_MODE"; -}; - -&qupv3_id_0 { - status = "okay"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&qupv3_id_2 { - status = "okay"; -}; - -/* CAN */ -&spi0 { - status = "okay"; -}; - -&tlmm { - gpio-reserved-ranges = <40 4>; - gpio-line-names = - "GPIO-MM", - "GPIO-NN", - "GPIO-OO", - "GPIO-PP", - "GPIO-A", - "GPIO-C", - "GPIO-E", - "GPIO-D", - "I2C0-SDA", - "I2C0-SCL", - "GPIO-TT", /* GPIO_10 */ - "NC", - "GPIO_12_I2C_SDA", - "GPIO_13_I2C_SCL", - "GPIO-X", - "GPIO_15_RGMII_INT", - "HST_BT_UART_CTS", - "HST_BT_UART_RFR", - "HST_BT_UART_TX", - "HST_BT_UART_RX", - "HST_WLAN_EN", /* GPIO_20 */ - "HST_BT_EN", - "GPIO-AAA", - "GPIO-BBB", - "GPIO-CCC", - "GPIO-Z", - "GPIO-DDD", - "GPIO-BB", - "GPIO_28_CAN_SPI_MISO", - "GPIO_29_CAN_SPI_MOSI", - "GPIO_30_CAN_SPI_CLK", /* GPIO_30 */ - "GPIO_31_CAN_SPI_CS", - "GPIO-UU", - "NC", - "UART1_TXD_SOM", - "UART1_RXD_SOM", - "UART0_CTS", - "UART0_RTS", - "UART0_TXD", - "UART0_RXD", - "SPI1_MISO", /* GPIO_40 */ - "SPI1_MOSI", - "SPI1_CLK", - "SPI1_CS", - "I2C1_SDA", - "I2C1_SCL", - "GPIO-F", - "GPIO-JJ", - "Board_ID1", - "Board_ID2", - "NC", /* GPIO_50 */ - "NC", - "SPI0_MISO", - "SPI0_MOSI", - "SPI0_SCLK", - "SPI0_CS", - "GPIO-QQ", - "GPIO-RR", - "USB2LAN_RESET", - "USB2LAN_EXTWAKE", - "NC", /* GPIO_60 */ - "NC", - "NC", - "LT9611_INT", - "GPIO-AA", - "USB_CC_DIR", - "GPIO-G", - "GPIO-LL", - "USB_DP_HPD_1P8", - "NC", - "NC", /* GPIO_70 */ - "SD_CMD", - "SD_DAT3", - "SD_SCLK", - "SD_DAT2", - "SD_DAT1", - "SD_DAT0", /* BOOT_CFG3 */ - "SD_UFS_CARD_DET_N", - "GPIO-II", - "PCIE0_RST_N", - "PCIE0_CLK_REQ_N", /* GPIO_80 */ - "PCIE0_WAKE_N", - "GPIO-CC", - "GPIO-DD", - "GPIO-EE", - "GPIO-FF", - "GPIO-GG", - "GPIO-HH", - "GPIO-VV", - "GPIO-WW", - "NC", /* GPIO_90 */ - "NC", - "GPIO-K", - "GPIO-I", - "CSI0_MCLK", - "CSI1_MCLK", - "CSI2_MCLK", - "CSI3_MCLK", - "GPIO-AA", /* CSI4_MCLK */ - "GPIO-BB", /* CSI5_MCLK */ - "GPIO-KK", /* GPIO_100 */ - "CCI_I2C_SDA0", - "CCI_I2C_SCL0", - "CCI_I2C_SDA1", - "CCI_I2C_SCL1", - "CCI_I2C_SDA2", - "CCI_I2C_SCL2", - "CCI_I2C_SDA3", - "CCI_I2C_SCL3", - "GPIO-L", - "NC", /* GPIO_110 */ - "NC", - "ACCEL_INT", - "GYRO_INT", - "GPIO-J", - "GPIO-YY", - "GPIO-H", - "GPIO-ZZ", - "NC", - "NC", - "NC", /* GPIO_120 */ - "NC", - "MAG_INT", - "MAG_DRDY_INT", - "HST_SW_CTRL", - "GPIO-M", - "GPIO-N", - "GPIO-O", - "GPIO-P", - "PS_INT", - "WSA1_EN", /* GPIO_130 */ - "USB_HUB_RESET", - "SDM_FORCE_USB_BOOT", - "I2S1_CLK_HDMI", - "I2S1_DATA0_HDMI", - "I2S1_WS_HDMI", - "GPIO-B", - "GPIO_137", /* To LT9611_I2S_MCLK_3V3 */ - "PCM_CLK", - "PCM_DI", - "PCM_DO", /* GPIO_140 */ - "PCM_FS", - "HST_SLIM_CLK", - "HST_SLIM_DATA", - "GPIO-U", - "GPIO-Y", - "GPIO-R", - "GPIO-Q", - "GPIO-S", - "GPIO-T", - "GPIO-V", /* GPIO_150 */ - "GPIO-W", - "DMIC_CLK1", - "DMIC_DATA1", - "DMIC_CLK2", - "DMIC_DATA2", - "WSA_SWR_CLK", - "WSA_SWR_DATA", - "DMIC_CLK3", - "DMIC_DATA3", - "I2C4_SDA", /* GPIO_160 */ - "I2C4_SCL", - "SPI3_CS1", - "SPI3_CS2", - "SPI2_MISO_LS3", - "SPI2_MOSI_LS3", - "SPI2_CLK_LS3", - "SPI2_ACCEL_CS_LS3", - "SPI2_CS1", - "NC", - "GPIO-SS", /* GPIO_170 */ - "GPIO-XX", - "SPI3_MISO", - "SPI3_MOSI", - "SPI3_CLK", - "SPI3_CS", - "HST_BLE_SNS_UART_TX", - "HST_BLE_SNS_UART_RX", - "HST_WLAN_UART_TX", - "HST_WLAN_UART_RX"; -}; - -&uart12 { - status = "okay"; -}; - -&ufs_mem_hc { - status = "okay"; - - vcc-supply = <&vreg_l17a_3p0>; - vcc-max-microamp = <800000>; - vccq-supply = <&vreg_l6a_1p2>; - vccq-max-microamp = <800000>; - vccq2-supply = <&vreg_s4a_1p8>; - vccq2-max-microamp = <800000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l5a_0p88>; - vdda-max-microamp = <89900>; - vdda-pll-supply = <&vreg_l9a_1p2>; - vdda-pll-max-microamp = <18800>; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts deleted file mode 100644 index afe0f9c25..000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ /dev/null @@ -1,601 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * SC7180 IDP board device tree source - * - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include -#include -#include "sc7180.dtsi" -#include "pm6150.dtsi" -#include "pm6150l.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. SC7180 IDP"; - compatible = "qcom,sc7180-idp", "qcom,sc7180"; - - aliases { - bluetooth0 = &bluetooth; - hsuart0 = &uart3; - serial0 = &uart8; - wifi0 = &wifi; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -/* - * Reserved memory changes - * - * Delete all unused memory nodes and define the peripheral memory regions - * required by the board dts. - * - */ - -/delete-node/ &hyp_mem; -/delete-node/ &xbl_mem; -/delete-node/ &aop_mem; -/delete-node/ &sec_apps_mem; -/delete-node/ &tz_mem; - -/* Increase the size from 2MB to 8MB */ -&rmtfs_mem { - reg = <0x0 0x94600000 0x0 0x800000>; -}; - -/ { - reserved-memory { - atf_mem: memory@80b00000 { - reg = <0x0 0x80b00000 0x0 0x100000>; - no-map; - }; - - mpss_mem: memory@86000000 { - reg = <0x0 0x86000000 0x0 0x8c00000>; - no-map; - }; - - camera_mem: memory@8ec00000 { - reg = <0x0 0x8ec00000 0x0 0x500000>; - no-map; - }; - - venus_mem: memory@8f600000 { - reg = <0 0x8f600000 0 0x500000>; - no-map; - }; - - wlan_mem: memory@94100000 { - reg = <0x0 0x94100000 0x0 0x200000>; - no-map; - }; - - mba_mem: memory@94400000 { - reg = <0x0 0x94400000 0x0 0x200000>; - no-map; - }; - }; -}; - -&apps_rsc { - pm6150-rpmh-regulators { - compatible = "qcom,pm6150-rpmh-regulators"; - qcom,pmic-id = "a"; - - vreg_s1a_1p1: smps1 { - regulator-min-microvolt = <1128000>; - regulator-max-microvolt = <1128000>; - }; - - vreg_s4a_1p0: smps4 { - regulator-min-microvolt = <824000>; - regulator-max-microvolt = <1120000>; - }; - - vreg_s5a_2p0: smps5 { - regulator-min-microvolt = <1744000>; - regulator-max-microvolt = <2040000>; - }; - - vreg_l1a_1p2: ldo1 { - regulator-min-microvolt = <1178000>; - regulator-max-microvolt = <1256000>; - regulator-initial-mode = ; - }; - - vreg_l2a_1p0: ldo2 { - regulator-min-microvolt = <944000>; - regulator-max-microvolt = <1056000>; - regulator-initial-mode = ; - }; - - vreg_l3a_1p0: ldo3 { - regulator-min-microvolt = <968000>; - regulator-max-microvolt = <1064000>; - regulator-initial-mode = ; - }; - - vreg_l4a_0p8: ldo4 { - regulator-min-microvolt = <824000>; - regulator-max-microvolt = <928000>; - regulator-initial-mode = ; - }; - - vreg_l5a_2p7: ldo5 { - regulator-min-microvolt = <2496000>; - regulator-max-microvolt = <3000000>; - regulator-initial-mode = ; - }; - - vreg_l6a_0p6: ldo6 { - regulator-min-microvolt = <568000>; - regulator-max-microvolt = <648000>; - regulator-initial-mode = ; - }; - - vreg_l9a_0p6: ldo9 { - regulator-min-microvolt = <488000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vreg_l10a_1p8: ldo10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1832000>; - regulator-initial-mode = ; - }; - - vreg_l11a_1p8: ldo11 { - regulator-min-microvolt = <1696000>; - regulator-max-microvolt = <1904000>; - regulator-initial-mode = ; - }; - - vreg_l12a_1p8: ldo12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l13a_1p8: ldo13 { - regulator-min-microvolt = <1696000>; - regulator-max-microvolt = <1904000>; - regulator-initial-mode = ; - }; - - vreg_l14a_1p8: ldo14 { - regulator-min-microvolt = <1728000>; - regulator-max-microvolt = <1832000>; - regulator-initial-mode = ; - }; - - vreg_l15a_1p8: ldo15 { - regulator-min-microvolt = <1696000>; - regulator-max-microvolt = <1904000>; - regulator-initial-mode = ; - }; - - vreg_l16a_2p7: ldo16 { - regulator-min-microvolt = <2496000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - }; - - vreg_l17a_3p0: ldo17 { - regulator-min-microvolt = <2920000>; - regulator-max-microvolt = <3232000>; - regulator-initial-mode = ; - }; - - vreg_l18a_2p8: ldo18 { - regulator-min-microvolt = <2496000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - }; - - vreg_l19a_2p9: ldo19 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - }; - - pm6150l-rpmh-regulators { - compatible = "qcom,pm6150l-rpmh-regulators"; - qcom,pmic-id = "c"; - - vreg_s8c_1p3: smps8 { - regulator-min-microvolt = <1120000>; - regulator-max-microvolt = <1408000>; - }; - - vreg_l1c_1p8: ldo1 { - regulator-min-microvolt = <1616000>; - regulator-max-microvolt = <1984000>; - regulator-initial-mode = ; - }; - - vreg_l2c_1p3: ldo2 { - regulator-min-microvolt = <1168000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l3c_1p2: ldo3 { - regulator-min-microvolt = <1144000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l4c_1p8: ldo4 { - regulator-min-microvolt = <1648000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - }; - - vreg_l5c_1p8: ldo5 { - regulator-min-microvolt = <1648000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - }; - - vreg_l6c_2p9: ldo6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-initial-mode = ; - }; - - vreg_l7c_3p0: ldo7 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vreg_l8c_1p8: ldo8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1904000>; - regulator-initial-mode = ; - }; - - vreg_l9c_2p9: ldo9 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l10c_3p3: ldo10 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3400000>; - regulator-initial-mode = ; - }; - - vreg_l11c_3p3: ldo11 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3400000>; - regulator-initial-mode = ; - }; - - vreg_bob: bob { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3960000>; - regulator-initial-mode = ; - }; - }; -}; - -&qfprom { - vcc-supply = <&vreg_l11a_1p8>; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <25000000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; - }; -}; - -&qupv3_id_0 { - status = "okay"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&remoteproc_mpss { - status = "okay"; - compatible = "qcom,sc7180-mss-pil"; - iommus = <&apps_smmu 0x461 0x0>, <&apps_smmu 0x444 0x3>; - memory-region = <&mba_mem &mpss_mem>; -}; - -&sdhc_1 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; - vmmc-supply = <&vreg_l19a_2p9>; - vqmmc-supply = <&vreg_l12a_1p8>; -}; - -&sdhc_2 { - status = "okay"; - - pinctrl-names = "default","sleep"; - pinctrl-0 = <&sdc2_on>; - pinctrl-1 = <&sdc2_off>; - vmmc-supply = <&vreg_l9c_2p9>; - vqmmc-supply = <&vreg_l6c_2p9>; - - cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>; -}; - -&uart3 { - status = "okay"; - - /delete-property/interrupts; - interrupts-extended = <&intc GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, - <&tlmm 41 IRQ_TYPE_EDGE_FALLING>; - - pinctrl-names = "default", "sleep"; - pinctrl-1 = <&qup_uart3_sleep>; - - bluetooth: wcn3990-bt { - compatible = "qcom,wcn3990-bt"; - vddio-supply = <&vreg_l10a_1p8>; - vddxo-supply = <&vreg_l1c_1p8>; - vddrf-supply = <&vreg_l2c_1p3>; - vddch0-supply = <&vreg_l10c_3p3>; - max-speed = <3200000>; - }; -}; - -&uart8 { - status = "okay"; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "host"; -}; - -&usb_1_hsphy { - status = "okay"; - vdd-supply = <&vreg_l4a_0p8>; - vdda-pll-supply = <&vreg_l11a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l17a_3p0>; - qcom,imp-res-offset-value = <8>; - qcom,preemphasis-level = ; - qcom,preemphasis-width = ; - qcom,bias-ctrl-value = <0x22>; - qcom,charge-ctrl-value = <3>; - qcom,hsdisc-trim-value = <0>; -}; - -&usb_1_qmpphy { - status = "okay"; - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l4a_0p8>; -}; - -&venus { - video-firmware { - iommus = <&apps_smmu 0x0c42 0x0>; - }; -}; - -&wifi { - status = "okay"; - vdd-0.8-cx-mx-supply = <&vreg_l9a_0p6>; - vdd-1.8-xo-supply = <&vreg_l1c_1p8>; - vdd-1.3-rfa-supply = <&vreg_l2c_1p3>; - vdd-3.3-ch0-supply = <&vreg_l10c_3p3>; - vdd-3.3-ch1-supply = <&vreg_l11c_3p3>; - wifi-firmware { - iommus = <&apps_smmu 0xc2 0x1>; - }; -}; - -/* PINCTRL - additions to nodes defined in sc7180.dtsi */ - -&qspi_clk { - pinconf { - pins = "gpio63"; - bias-disable; - }; -}; - -&qspi_cs0 { - pinconf { - pins = "gpio68"; - bias-disable; - }; -}; - -&qspi_data01 { - pinconf { - pins = "gpio64", "gpio65"; - - /* High-Z when no transfers; nice to park the lines */ - bias-pull-up; - }; -}; - -&qup_i2c2_default { - pinconf { - pins = "gpio15", "gpio16"; - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; - }; -}; - -&qup_i2c4_default { - pinconf { - pins = "gpio115", "gpio116"; - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; - }; -}; - -&qup_i2c7_default { - pinconf { - pins = "gpio6", "gpio7"; - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; - }; -}; - -&qup_i2c9_default { - pinconf { - pins = "gpio46", "gpio47"; - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; - }; -}; - -&qup_uart3_default { - pinconf-cts { - /* - * Configure a pull-down on CTS to match the pull of - * the Bluetooth module. - */ - pins = "gpio38"; - bias-pull-down; - }; - - pinconf-rts { - /* We'll drive RTS, so no pull */ - pins = "gpio39"; - drive-strength = <2>; - bias-disable; - }; - - pinconf-tx { - /* We'll drive TX, so no pull */ - pins = "gpio40"; - drive-strength = <2>; - bias-disable; - }; - - pinconf-rx { - /* - * Configure a pull-up on RX. This is needed to avoid - * garbage data when the TX pin of the Bluetooth module is - * in tri-state (module powered off or not driving the - * signal yet). - */ - pins = "gpio41"; - bias-pull-up; - }; -}; - -&qup_uart8_default { - pinconf-tx { - pins = "gpio44"; - drive-strength = <2>; - bias-disable; - }; - - pinconf-rx { - pins = "gpio45"; - drive-strength = <2>; - bias-pull-up; - }; -}; - -&qup_spi0_default { - pinconf { - pins = "gpio34", "gpio35", "gpio36", "gpio37"; - drive-strength = <2>; - bias-disable; - }; -}; - -&qup_spi6_default { - pinconf { - pins = "gpio59", "gpio60", "gpio61", "gpio62"; - drive-strength = <2>; - bias-disable; - }; -}; - -&qup_spi10_default { - pinconf { - pins = "gpio86", "gpio87", "gpio88", "gpio89"; - drive-strength = <2>; - bias-disable; - }; -}; - -&tlmm { - qup_uart3_sleep: qup-uart3-sleep { - pinmux { - pins = "gpio38", "gpio39", - "gpio40", "gpio41"; - function = "gpio"; - }; - - pinconf-cts { - /* - * Configure a pull-down on CTS to match the pull of - * the Bluetooth module. - */ - pins = "gpio38"; - bias-pull-down; - }; - - pinconf-rts { - /* - * Configure pull-down on RTS. As RTS is active low - * signal, pull it low to indicate the BT SoC that it - * can wakeup the system anytime from suspend state by - * pulling RX low (by sending wakeup bytes). - */ - pins = "gpio39"; - bias-pull-down; - }; - - pinconf-tx { - /* - * Configure pull-up on TX when it isn't actively driven - * to prevent BT SoC from receiving garbage during sleep. - */ - pins = "gpio40"; - bias-pull-up; - }; - - pinconf-rx { - /* - * Configure a pull-up on RX. This is needed to avoid - * garbage data when the TX pin of the Bluetooth module - * is floating which may cause spurious wakeups. - */ - pins = "gpio41"; - bias-pull-up; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts deleted file mode 100644 index ae4c23a4f..000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Lazor board device tree source - * - * Copyright 2020 Google LLC. - */ - -/dts-v1/; - -#include "sc7180-trogdor-lazor.dtsi" - -/ { - model = "Google Lazor (rev0)"; - compatible = "google,lazor-rev0", "qcom,sc7180"; -}; - -&sn65dsi86_out { - /* - * Lane 0 was incorrectly mapped on the cable, but we've now decided - * that the cable is canon and in -rev1+ we'll make a board change - * that means we no longer need the swizzle. - */ - lane-polarities = <1 0>; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts deleted file mode 100644 index c3f426c3c..000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Lazor board device tree source - * - * Copyright 2020 Google LLC. - */ - -#include "sc7180-trogdor-lazor-r1.dts" - -/ { - model = "Google Lazor (rev1+) with KB Backlight"; - compatible = "google,lazor-sku2", "qcom,sc7180"; -}; - -&keyboard_backlight { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts deleted file mode 100644 index 73e59cf77..000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Lazor board device tree source - * - * Copyright 2020 Google LLC. - */ - -#include "sc7180-trogdor-lazor-r1.dts" -#include "sc7180-trogdor-lte-sku.dtsi" - -/ { - model = "Google Lazor (rev1+) with LTE"; - compatible = "google,lazor-sku0", "qcom,sc7180"; -}; - -&keyboard_backlight { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts deleted file mode 100644 index 3151ae31c..000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Lazor board device tree source - * - * Copyright 2020 Google LLC. - */ - -/dts-v1/; - -#include "sc7180-trogdor-lazor.dtsi" - -/ { - model = "Google Lazor (rev1+)"; - compatible = "google,lazor", "qcom,sc7180"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi deleted file mode 100644 index 180ef9e04..000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ /dev/null @@ -1,192 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Lazor board device tree source - * - * Copyright 2020 Google LLC. - */ - -#include "sc7180.dtsi" - -ap_ec_spi: &spi6 {}; -ap_h1_spi: &spi0 {}; - -#include "sc7180-trogdor.dtsi" - -/ { - panel: panel { - compatible = "boe,nv133fhm-n62"; - power-supply = <&pp3300_dx_edp>; - backlight = <&backlight>; - hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>; - - ports { - port { - panel_in_edp: endpoint { - remote-endpoint = <&sn65dsi86_out>; - }; - }; - }; - }; -}; - -&ap_sar_sensor { - status = "okay"; -}; - -ap_ts_pen_1v8: &i2c4 { - status = "okay"; - clock-frequency = <400000>; - - ap_ts: touchscreen@10 { - compatible = "hid-over-i2c"; - reg = <0x10>; - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; - - interrupt-parent = <&tlmm>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - - post-power-on-delay-ms = <20>; - hid-descr-addr = <0x0001>; - - vdd-supply = <&pp3300_ts>; - }; -}; - -/* PINCTRL - modifications to sc7180-trogdor.dtsi */ - -&ts_reset_l { - pinconf { - /* This pin is not connected on -rev0, pull up to park. */ - /delete-property/bias-disable; - bias-pull-up; - }; -}; - -/* PINCTRL - board-specific pinctrl */ - -&tlmm { - gpio-line-names = "ESIM_MISO", - "ESIM_MOSI", - "ESIM_CLK", - "ESIM_CS_L", - "", - "", - "AP_TP_I2C_SDA", - "AP_TP_I2C_SCL", - "TS_RESET_L", - "TS_INT_L", - "", - "EDP_BRIJ_IRQ", - "AP_EDP_BKLTEN", - "AP_RAM_ID2", - "", - "EDP_BRIJ_I2C_SDA", - "EDP_BRIJ_I2C_SCL", - "HUB_RST_L", - "", - "AP_RAM_ID1", - "AP_SKU_ID2", - "", - "", - "AMP_EN", - "P_SENSOR_INT_L", - "AP_SAR_SENSOR_SDA", - "AP_SAR_SENSOR_SCL", - "", - "HP_IRQ", - "AP_RAM_ID0", - "EN_PP3300_DX_EDP", - "AP_BRD_ID2", - "BRIJ_SUSPEND", - "AP_BRD_ID0", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - "AP_H1_SPI_CLK", - "AP_H1_SPI_CS_L", - "", - "", - "", - "", - "H1_AP_INT_ODL", - "", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "HP_I2C_SDA", - "HP_I2C_SCL", - "FORCED_USB_BOOT", - "", - "", - "AMP_DIN", - "", - "HP_BCLK", - "HP_LRCLK", - "HP_DOUT", - "HP_DIN", - "HP_MCLK", - "TRACKPAD_INT_1V8_ODL", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "AP_SPI_CLK", - "AP_SPI_MOSI", - "AP_SPI_MISO", - /* - * AP_FLASH_WP_L is crossystem ABI. Schematics - * call it BIOS_FLASH_WP_L. - */ - "AP_FLASH_WP_L", - "DBG_SPI_HOLD_L", - "AP_SPI_CS0_L", - "", - "", - "", - "", - "", - "", - "UIM2_DATA", - "UIM2_CLK", - "UIM2_RST", - "UIM2_PRESENT", - "UIM1_DATA", - "UIM1_CLK", - "UIM1_RST", - "", - "EN_PP3300_CODEC", - "EN_PP3300_HUB", - "", - "", - "", - "", - "", - "AP_SKU_ID1", - "AP_RST_REQ", - "", - "AP_BRD_ID1", - "AP_EC_INT_L", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "EDP_BRIJ_EN", - "AP_SKU_ID0", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "AP_TS_PEN_I2C_SDA", - "AP_TS_PEN_I2C_SCL", - "DP_HOT_PLUG_DET", - "EC_IN_RW_ODL"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi deleted file mode 100644 index 44956e316..000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Trogdor dts fragment for LTE SKUs - * - * Copyright 2020 Google LLC. - */ - -&ap_sar_sensor { - label = "proximity-wifi-lte"; -}; - -&remoteproc_mpss { - firmware-name = "qcom/sc7180-trogdor/modem/mba.mbn", - "qcom/sc7180-trogdor/modem/qdsp6sw.mbn"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1-lte.dts deleted file mode 100644 index 1123c02bd..000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1-lte.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Trogdor board device tree source - * - * Copyright 2020 Google LLC. - */ - -#include "sc7180-trogdor-r1.dts" -#include "sc7180-trogdor-lte-sku.dtsi" - -/ { - model = "Google Trogdor (rev1+) with LTE"; - compatible = "google,trogdor-sku0", "qcom,sc7180"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts deleted file mode 100644 index 0a281c248..000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts +++ /dev/null @@ -1,191 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Trogdor board device tree source - * - * Copyright 2020 Google LLC. - */ - -/dts-v1/; - -#include "sc7180.dtsi" - -ap_ec_spi: &spi6 {}; -ap_h1_spi: &spi0 {}; - -#include "sc7180-trogdor.dtsi" - -/ { - model = "Google Trogdor (rev1+)"; - compatible = "google,trogdor", "qcom,sc7180"; - - panel: panel { - compatible = "auo,b116xa01"; - power-supply = <&pp3300_dx_edp>; - backlight = <&backlight>; - hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>; - - ports { - port { - panel_in_edp: endpoint { - remote-endpoint = <&sn65dsi86_out>; - }; - }; - }; - }; -}; - -&ap_sar_sensor_i2c { - /* Not hooked up */ - status = "disabled"; -}; - -ap_ts_pen_1v8: &i2c4 { - status = "okay"; - clock-frequency = <400000>; - - ap_ts: touchscreen@10 { - compatible = "elan,ekth3500"; - reg = <0x10>; - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; - - interrupt-parent = <&tlmm>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - - vcc33-supply = <&pp3300_ts>; - - reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; - }; -}; - -&sdhc_2 { - status = "okay"; -}; - -/* PINCTRL - board-specific pinctrl */ - -&tlmm { - gpio-line-names = "ESIM_MISO", - "ESIM_MOSI", - "ESIM_CLK", - "ESIM_CS_L", - "FP_TO_AP_IRQ_L", - "FP_RST_L", - "AP_TP_I2C_SDA", - "AP_TP_I2C_SCL", - "TS_RESET_L", - "TS_INT_L", - "FPMCU_BOOT0", - "EDP_BRIJ_IRQ", - "AP_EDP_BKLTEN", - "", - "", - "EDP_BRIJ_I2C_SDA", - "EDP_BRIJ_I2C_SCL", - "HUB_RST_L", - "PEN_RST_ODL", - "AP_RAM_ID1", - "AP_RAM_ID2", - "PEN_IRQ_L", - "FPMCU_SEL", - "AMP_EN", - "P_SENSOR_INT_L", - "AP_SAR_SENSOR_SDA", - "AP_SAR_SENSOR_SCL", - "", - "HP_IRQ", - "AP_RAM_ID0", - "EN_PP3300_DX_EDP", - "AP_BRD_ID2", - "BRIJ_SUSPEND", - "AP_BRD_ID0", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - "AP_H1_SPI_CLK", - "AP_H1_SPI_CS_L", - "", - "", - "", - "", - "H1_AP_INT_ODL", - "", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "HP_I2C_SDA", - "HP_I2C_SCL", - "FORCED_USB_BOOT", - "", - "", - "AMP_DIN", - "PEN_PDCT_L", - "HP_BCLK", - "HP_LRCLK", - "HP_DOUT", - "HP_DIN", - "HP_MCLK", - "TRACKPAD_INT_1V8_ODL", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "AP_SPI_CLK", - "AP_SPI_MOSI", - "AP_SPI_MISO", - /* - * AP_FLASH_WP_L is crossystem ABI. Schematics - * call it BIOS_FLASH_WP_L. - */ - "AP_FLASH_WP_L", - "DBG_SPI_HOLD_L", - "AP_SPI_CS0_L", - "SD_CD_ODL", - "", - "", - "", - "", - "", - "UIM2_DATA", - "UIM2_CLK", - "UIM2_RST", - "UIM2_PRESENT", - "UIM1_DATA", - "UIM1_CLK", - "UIM1_RST", - "", - "EN_PP3300_CODEC", - "EN_PP3300_HUB", - "", - "AP_SPI_FP_MISO", - "AP_SPI_FP_MOSI", - "AP_SPI_FP_CLK", - "AP_SPI_FP_CS_L", - "AP_SKU_ID1", - "AP_RST_REQ", - "", - "AP_BRD_ID1", - "AP_EC_INT_L", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "EDP_BRIJ_EN", - "AP_SKU_ID0", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "AP_TS_PEN_I2C_SDA", - "AP_TS_PEN_I2C_SCL", - "DP_HOT_PLUG_DET", - "EC_IN_RW_ODL"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi deleted file mode 100644 index 5b2a616c6..000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ /dev/null @@ -1,1404 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Trogdor device tree source (common between revisions) - * - * Copyright 2019 Google LLC. - */ - -#include -#include -#include - -/* PMICs depend on spmi_bus label and so must come after SoC */ -#include "pm6150.dtsi" -#include "pm6150l.dtsi" - -/* - * Reserved memory changes - * - * Delete all unused memory nodes and define the peripheral memory regions - * required by the board dts. - */ - -/delete-node/ &hyp_mem; -/delete-node/ &xbl_mem; -/delete-node/ &aop_mem; -/delete-node/ &sec_apps_mem; -/delete-node/ &tz_mem; - -/* Increase the size from 2MB to 8MB */ -&rmtfs_mem { - reg = <0x0 0x84400000 0x0 0x800000>; -}; - -/ { - reserved-memory { - atf_mem: memory@80b00000 { - reg = <0x0 0x80b00000 0x0 0x100000>; - no-map; - }; - - mpss_mem: memory@86000000 { - reg = <0x0 0x86000000 0x0 0x8c00000>; - no-map; - }; - - camera_mem: memory@8ec00000 { - reg = <0x0 0x8ec00000 0x0 0x500000>; - no-map; - }; - - venus_mem: memory@8f600000 { - reg = <0 0x8f600000 0 0x500000>; - no-map; - }; - - wlan_mem: memory@94100000 { - reg = <0x0 0x94100000 0x0 0x200000>; - no-map; - }; - - mba_mem: memory@94400000 { - reg = <0x0 0x94400000 0x0 0x200000>; - no-map; - }; - }; - - aliases { - bluetooth0 = &bluetooth; - hsuart0 = &uart3; - serial0 = &uart8; - wifi0 = &wifi; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - /* FIXED REGULATORS - parents above children */ - - /* This is the top level supply and variable voltage */ - ppvar_sys: ppvar-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "ppvar_sys"; - regulator-always-on; - regulator-boot-on; - }; - - /* This divides ppvar_sys by 2, so voltage is variable */ - src_vph_pwr: src-vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "src_vph_pwr"; - - /* EC turns on with switchcap_on; always on for AP */ - regulator-always-on; - regulator-boot-on; - - vin-supply = <&ppvar_sys>; - }; - - pp5000_a: pp5000-a-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp5000_a"; - - /* EC turns on with en_pp5000_a; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - vin-supply = <&ppvar_sys>; - }; - - pp3300_a: pp3300-a-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_a"; - - /* EC turns on with en_pp3300_a; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - /* - * Actually should be pp3300 but that's practically an alias for - * pp3300_a so we use pp3300's vin-supply here to avoid one more - * node. - */ - vin-supply = <&ppvar_sys>; - }; - - pp3300_audio: - pp3300_codec: pp3300-codec-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_codec"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 83 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&en_pp3300_codec>; - - vin-supply = <&pp3300_a>; - }; - - pp3300_dx_edp: - pp3300_ts: pp3300-dx-edp-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_dx_edp"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 30 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&en_pp3300_dx_edp>; - - vin-supply = <&pp3300_a>; - }; - - pp3300_fp_tp: pp3300-fp-tp-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_fp_tp"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - /* AP turns on with PP1800_VIO_OUT; always on for AP */ - regulator-always-on; - regulator-boot-on; - - vin-supply = <&pp3300_a>; - }; - - /* BOARD-SPECIFIC TOP LEVEL NODES */ - - backlight: backlight { - compatible = "pwm-backlight"; - - pwms = <&cros_ec_pwm 1>; - enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; - power-supply = <&ppvar_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&ap_edp_bklten>; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&pen_pdct_l>; - - pen-insert { - label = "Pen Insert"; - - /* Insert = low, eject = high */ - gpios = <&tlmm 52 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - wakeup-source; - }; - }; - - max98357a: audio-codec-0 { - compatible = "maxim,max98357a"; - pinctrl-names = "default"; - pinctrl-0 = <&_en>; - sdmode-gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>; - #sound-dai-cells = <0>; - }; - - pwmleds { - compatible = "pwm-leds"; - keyboard_backlight: keyboard-backlight { - status = "disabled"; - label = "cros_ec::kbd_backlight"; - pwms = <&cros_ec_pwm 0>; - max-brightness = <1023>; - }; - }; -}; - -&qfprom { - vcc-supply = <&pp1800_l11a>; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - - /* TODO: Increase frequency after testing */ - spi-max-frequency = <25000000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; - }; -}; - -&apps_rsc { - pm6150-rpmh-regulators { - compatible = "qcom,pm6150-rpmh-regulators"; - qcom,pmic-id = "a"; - - vddpx_1: - vdd2: - pp1125_s1a: smps1 { - regulator-min-microvolt = <1128000>; - regulator-max-microvolt = <1128000>; - }; - - /* - * pp2040_s5a (smps5) and pp1056_s4a (smps4) are just - * inputs to other rails on AOP-managed PMICs on trogdor. - * The system is already configured to manage these rails - * automatically (enable when needed, adjust voltage for - * headroom) so we won't specify anything here. - * - * NOTE: though the rails have a voltage implied by their - * name, the automatic headroom calculation might not result - * in them being that voltage. ...and that's OK. - * Specifically the only point of these rails is to provide - * an input source for other rails and if we can satisify the - * needs of those other rails with a lower source voltage then - * we save power. - */ - - pp1200_l1a: ldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - pp1000_l2a: ldo2 { - regulator-min-microvolt = <944000>; - regulator-max-microvolt = <1056000>; - regulator-initial-mode = ; - }; - - pp1000_l3a: ldo3 { - regulator-min-microvolt = <968000>; - regulator-max-microvolt = <1064000>; - regulator-initial-mode = ; - }; - - vdd_qlink_lv: - vdd_qlink_lv_ck: - vdd_qusb_hs0_core: - vdd_ufs1_core: - vdda_mipi_csi0_0p9: - vdda_mipi_csi1_0p9: - vdda_mipi_csi2_0p9: - vdda_mipi_csi3_0p9: - vdda_mipi_dsi0_pll: - vdda_pll_cc_ebi01: - vdda_qrefs_0p9: - vdda_usb_ss_dp_core: - pp900_l4a: ldo4 { - regulator-min-microvolt = <824000>; - regulator-max-microvolt = <928000>; - regulator-initial-mode = ; - }; - - pp2700_l5a: ldo5 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - regulator-initial-mode = ; - }; - - ebi0_cal: - ebi1_cal: - vddio_ck_ebi0: - vddio_ck_ebi1: - vddio_ebi0: - vddq: - pp600_l6a: ldo6 { - regulator-min-microvolt = <568000>; - regulator-max-microvolt = <648000>; - regulator-initial-mode = ; - }; - - vdd_cx_wlan: - pp800_l9a: ldo9 { - regulator-min-microvolt = <488000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vdd1: - vddpx_3: - vddpx_7: - vio_in: - pp1800_l10a: ldo10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vdd_qfprom: - vdda_apc1_cs_1p8: - vdda_qrefs_1p8: - vdda_qusb_hs0_1p8: - vddpx_11: - vreg_bb_clk: - pp1800_l11a: ldo11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - mcp_vccq: - pp1800_l12a_r: ldo12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - pp1800_l13a: ldo13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - pp1800_prox: - pp1800_l14a: ldo14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - pp1800_alc5682: - pp1800_l15a: ldo15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - pp2700_l16a: ldo16 { - regulator-min-microvolt = <2496000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - }; - - vdda_qusb_hs0_3p1: - vdd_pdphy: - pp3100_l17a: ldo17 { - regulator-min-microvolt = <2920000>; - regulator-max-microvolt = <3232000>; - regulator-initial-mode = ; - }; - - pp1800_pen: - pp1800_l18a: ldo18 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - mcp_vcc: - pp2850_l19a: ldo19 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - }; - - pm6150l-rpmh-regulators { - compatible = "qcom,pm6150l-rpmh-regulators"; - qcom,pmic-id = "c"; - - pp1300_s8c: smps8 { - regulator-min-microvolt = <1120000>; - regulator-max-microvolt = <1408000>; - }; - - pp1800_l1c: ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vdd_wcss_adc_dac: - pp1300_l2c: ldo2 { - regulator-min-microvolt = <1168000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - pp1200_brij: - vdd_ufs1_1p2: - vdda_csi0_1p25: - vdda_csi1_1p25: - vdda_csi2_1p25: - vdda_csi3_1p25: - vdda_hv_ebi0: - vdda_mipi_dsi0_1p2: - vdda_usb_ss_dp_1p2: - vddpx_10: - pp1200_l3c: ldo3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - ld_pp1800_esim_l4c: - vddpx_5: - pp1800_l4c: ldo4 { - regulator-min-microvolt = <1648000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - }; - - vddpx_6: - pp1800_l5c: ldo5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vddpx_2: - ppvar_l6c: ldo6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - }; - - pp3300_hub: - pp3300_l7c: ldo7 { - regulator-min-microvolt = <3304000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - regulator-always-on; - regulator-boot-on; - }; - - pp1800_brij_vccio: - pp1800_edp_vpll: - pp1800_l8c: ldo8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - pp2950_l9c: ldo9 { - regulator-min-microvolt = <2952000>; - regulator-max-microvolt = <2952000>; - regulator-initial-mode = ; - }; - - pp3300_l10c: ldo10 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3400000>; - regulator-initial-mode = ; - }; - - pp3300_l11c: ldo11 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3400000>; - regulator-initial-mode = ; - }; - - src_vreg_bob: bob { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3960000>; - regulator-initial-mode = ; - }; - }; -}; - -&ap_ec_spi { - status = "okay"; - cros_ec: ec@0 { - compatible = "google,cros-ec-spi"; - reg = <0>; - interrupt-parent = <&tlmm>; - interrupts = <94 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ap_ec_int_l>; - spi-max-frequency = <3000000>; - - cros_ec_pwm: ec-pwm { - compatible = "google,cros-ec-pwm"; - #pwm-cells = <1>; - }; - - i2c_tunnel: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - google,remote-bus = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - pdupdate { - compatible = "google,cros-ec-pd-update"; - }; - - typec { - compatible = "google,cros-ec-typec"; - #address-cells = <1>; - #size-cells = <0>; - - usb_c0: connector@0 { - compatible = "usb-c-connector"; - reg = <0>; - label = "left"; - power-role = "dual"; - data-role = "host"; - try-power-role = "source"; - }; - - usb_c1: connector@1 { - compatible = "usb-c-connector"; - reg = <1>; - label = "right"; - power-role = "dual"; - data-role = "host"; - try-power-role = "source"; - }; - }; - }; -}; - -&ap_h1_spi { - status = "okay"; - cr50: tpm@0 { - compatible = "google,cr50"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&h1_ap_int_odl>; - spi-max-frequency = <800000>; - interrupt-parent = <&tlmm>; - interrupts = <42 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&dsi0 { - status = "okay"; - vdda-supply = <&vdda_mipi_dsi0_1p2>; - - ports { - port@1 { - endpoint { - remote-endpoint = <&sn65dsi86_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&dsi_phy { - status = "okay"; - vdds-supply = <&vdda_mipi_dsi0_pll>; -}; - -edp_brij_i2c: &i2c2 { - status = "okay"; - clock-frequency = <400000>; - - sn65dsi86_bridge: bridge@2d { - compatible = "ti,sn65dsi86"; - reg = <0x2d>; - pinctrl-names = "default"; - pinctrl-0 = <&edp_brij_en>, <&edp_brij_irq>; - gpio-controller; - #gpio-cells = <2>; - - interrupt-parent = <&tlmm>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; - - enable-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; - - vpll-supply = <&pp1800_edp_vpll>; - vccio-supply = <&pp1800_brij_vccio>; - vcca-supply = <&pp1200_brij>; - vcc-supply = <&pp1200_brij>; - - clocks = <&rpmhcc RPMH_LN_BB_CLK3>; - clock-names = "refclk"; - - no-hpd; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - sn65dsi86_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - sn65dsi86_out: endpoint { - data-lanes = <0 1>; - remote-endpoint = <&panel_in_edp>; - }; - }; - }; - }; -}; - -ap_sar_sensor_i2c: &i2c5 { - status = "okay"; - clock-frequency = <400000>; - - ap_sar_sensor: proximity@28 { - compatible = "semtech,sx9310"; - reg = <0x28>; - #io-channel-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&p_sensor_int_l>; - - interrupt-parent = <&tlmm>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - - vdd-supply = <&pp3300_a>; - svdd-supply = <&pp1800_prox>; - - status = "disabled"; - label = "proximity-wifi"; - }; -}; - -ap_tp_i2c: &i2c7 { - status = "okay"; - clock-frequency = <400000>; - - trackpad@15 { - compatible = "elan,ekth3000"; - reg = <0x15>; - pinctrl-names = "default"; - pinctrl-0 = <&trackpad_int_1v8_odl>; - - interrupt-parent = <&tlmm>; - interrupts = <58 IRQ_TYPE_EDGE_FALLING>; - - vcc-supply = <&pp3300_fp_tp>; - - wakeup-source; - }; -}; - -hp_i2c: &i2c9 { - status = "okay"; - clock-frequency = <400000>; - - alc5682: codec@1a { - compatible = "realtek,rt5682i"; - reg = <0x1a>; - pinctrl-names = "default"; - pinctrl-0 = <&hp_irq>; - - #sound-dai-cells = <1>; - - interrupt-parent = <&tlmm>; - /* - * This will get ignored because the interrupt type - * is set in rt5682.c. - */ - interrupts = <28 IRQ_TYPE_EDGE_BOTH>; - - AVDD-supply = <&pp1800_alc5682>; - MICVDD-supply = <&pp3300_codec>; - VBAT-supply = <&pp3300_audio>; - - realtek,dmic1-data-pin = <1>; - realtek,dmic1-clk-pin = <1>; - realtek,jd-src = <1>; - }; -}; - -&ipa { - status = "okay"; - - /* - * Trogdor doesn't have QHEE (Qualcomm's EL2 blob), so the - * modem needs to cover certain init steps (GSI init), and - * the AP needs to wait for it. - */ - modem-init; -}; - -&mdp { - status = "okay"; -}; - -&mdss { - status = "okay"; -}; - -&pm6150_pwrkey { - status = "disabled"; -}; - -&qupv3_id_0 { - status = "okay"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&remoteproc_mpss { - status = "okay"; - compatible = "qcom,sc7180-mss-pil"; - iommus = <&apps_smmu 0x461 0x0>, <&apps_smmu 0x444 0x3>; - memory-region = <&mba_mem &mpss_mem>; - - /* This gets overridden for SKUs with LTE support. */ - firmware-name = "qcom/sc7180-trogdor/modem-nolte/mba.mbn", - "qcom/sc7180-trogdor/modem-nolte/qdsp6sw.mbn"; -}; - -&sdhc_1 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; - vmmc-supply = <&mcp_vcc>; - vqmmc-supply = <&mcp_vccq>; -}; - -&sdhc_2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_on>; - pinctrl-1 = <&sdc2_off>; - vmmc-supply = <&pp2950_l9c>; - vqmmc-supply = <&ppvar_l6c>; - - cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>; -}; - -ap_spi_fp: &spi10 { - cros_ec_fp: ec@0 { - compatible = "google,cros-ec-spi"; - reg = <0>; - interrupt-parent = <&tlmm>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&fp_to_ap_irq_l>, <&fp_rst_l>, <&fpmcu_boot0>, <&fpmcu_sel>; - spi-max-frequency = <3000000>; - }; -}; - -#include -#include - -&uart3 { - status = "okay"; - - /delete-property/interrupts; - interrupts-extended = <&intc GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, - <&tlmm 41 IRQ_TYPE_EDGE_FALLING>; - - pinctrl-names = "default", "sleep"; - pinctrl-1 = <&qup_uart3_sleep>; - - bluetooth: bluetooth { - compatible = "qcom,wcn3991-bt"; - vddio-supply = <&pp1800_l10a>; - vddxo-supply = <&pp1800_l1c>; - vddrf-supply = <&pp1300_l2c>; - vddch0-supply = <&pp3300_l10c>; - max-speed = <3200000>; - clocks = <&rpmhcc RPMH_RF_CLK2>; - }; -}; - -&uart8 { - status = "okay"; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "host"; -}; - -&usb_1_hsphy { - status = "okay"; - vdd-supply = <&vdd_qusb_hs0_core>; - vdda-pll-supply = <&vdda_qusb_hs0_1p8>; - vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; - qcom,imp-res-offset-value = <8>; - qcom,preemphasis-level = ; - qcom,preemphasis-width = ; - qcom,bias-ctrl-value = <0x22>; - qcom,charge-ctrl-value = <3>; - qcom,hsdisc-trim-value = <0>; -}; - -&usb_1_qmpphy { - status = "okay"; - vdda-phy-supply = <&vdda_usb_ss_dp_1p2>; - vdda-pll-supply = <&vdda_usb_ss_dp_core>; -}; - -&venus { - video-firmware { - iommus = <&apps_smmu 0x0c42 0x0>; - }; -}; - -&wifi { - status = "okay"; - vdd-0.8-cx-mx-supply = <&vdd_cx_wlan>; - vdd-1.8-xo-supply = <&pp1800_l1c>; - vdd-1.3-rfa-supply = <&pp1300_l2c>; - vdd-3.3-ch0-supply = <&pp3300_l10c>; - vdd-3.3-ch1-supply = <&pp3300_l11c>; - - wifi-firmware { - iommus = <&apps_smmu 0xc2 0x1>; - }; -}; - -/* PINCTRL - additions to nodes defined in sc7180.dtsi */ - -&qspi_cs0 { - pinconf { - pins = "gpio68"; - bias-disable; - }; -}; - -&qspi_clk { - pinconf { - pins = "gpio63"; - bias-disable; - }; -}; - -&qspi_data01 { - pinconf { - pins = "gpio64", "gpio65"; - - /* High-Z when no transfers; nice to park the lines */ - bias-pull-up; - }; -}; - -&qup_i2c2_default { - pinconf { - pins = "gpio15", "gpio16"; - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; - }; -}; - -&qup_i2c4_default { - pinconf { - pins = "gpio115", "gpio116"; - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; - }; -}; - -&qup_i2c5_default { - pinconf { - pins = "gpio25", "gpio26"; - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; - }; -}; - -&qup_i2c7_default { - pinconf { - pins = "gpio6", "gpio7"; - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; - }; -}; - -&qup_i2c9_default { - pinconf { - pins = "gpio46", "gpio47"; - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; - }; -}; - -&qup_spi0_default { - pinconf { - pins = "gpio34", "gpio35", "gpio36", "gpio37"; - drive-strength = <2>; - bias-disable; - }; -}; - -&qup_spi6_default { - pinconf { - pins = "gpio59", "gpio60", "gpio61", "gpio62"; - drive-strength = <2>; - bias-disable; - }; -}; - -&qup_spi10_default { - pinconf { - pins = "gpio86", "gpio87", "gpio88", "gpio89"; - drive-strength = <2>; - bias-disable; - }; -}; - -&qup_uart3_default { - pinconf-cts { - /* - * Configure a pull-down on CTS to match the pull of - * the Bluetooth module. - */ - pins = "gpio38"; - bias-pull-down; - }; - - pinconf-rts-tx { - /* We'll drive RTS and TX, so no pull */ - pins = "gpio39", "gpio40"; - drive-strength = <2>; - bias-disable; - }; - - pinconf-rx { - /* - * Configure a pull-up on RX. This is needed to avoid - * garbage data when the TX pin of the Bluetooth module is - * in tri-state (module powered off or not driving the - * signal yet). - */ - pins = "gpio41"; - bias-pull-up; - }; -}; - -&qup_uart8_default { - pinconf-tx { - pins = "gpio44"; - drive-strength = <2>; - bias-disable; - }; - - pinconf-rx { - pins = "gpio45"; - drive-strength = <2>; - bias-pull-up; - }; -}; - -/* PINCTRL - board-specific pinctrl */ - -&pm6150_gpio { - status = "disabled"; /* No GPIOs are connected */ -}; - -&pm6150l_gpio { - gpio-line-names = "AP_SUSPEND", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - ""; -}; - -&tlmm { - /* - * pinctrl settings for pins that have no real owners. - */ - pinctrl-names = "default"; - pinctrl-0 = <&bios_flash_wp_l>, <&ap_suspend_l_neuter>; - - amp_en: amp-en { - pinmux { - pins = "gpio23"; - function = "gpio"; - }; - - pinconf { - pins = "gpio23"; - bias-pull-down; - }; - }; - - ap_ec_int_l: ap-ec-int-l { - pinmux { - pins = "gpio94"; - function = "gpio"; - input-enable; - }; - - pinconf { - pins = "gpio94"; - bias-pull-up; - }; - }; - - ap_edp_bklten: ap-edp-bklten { - pinmux { - pins = "gpio12"; - function = "gpio"; - }; - - pinconf { - pins = "gpio12"; - drive-strength = <2>; - bias-disable; - - /* Force backlight to be disabled to match state at boot. */ - output-low; - }; - }; - - ap_suspend_l_neuter: ap-suspend-l-neuter { - pinmux { - pins = "gpio27"; - function = "gpio"; - }; - - pinconf { - pins = "gpio27"; - bias-disable; - }; - }; - - bios_flash_wp_l: bios-flash-wp-l { - pinmux { - pins = "gpio66"; - function = "gpio"; - input-enable; - }; - - pinconf { - pins = "gpio66"; - bias-disable; - }; - }; - - dp_hot_plug_det: dp-hot-plug-det { - pinmux { - pins = "gpio117"; - function = "dp_hot"; - }; - - config { - pins = "gpio117"; - bias-disable; - input-enable; - drive-strength = <2>; - }; - }; - - edp_brij_en: edp-brij-en { - pinmux { - pins = "gpio104"; - function = "gpio"; - }; - - pinconf { - pins = "gpio104"; - drive-strength = <2>; - bias-disable; - }; - }; - - edp_brij_irq: edp-brij-irq { - pinmux { - pins = "gpio11"; - function = "gpio"; - }; - - pinconf { - pins = "gpio11"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - en_pp3300_codec: en-pp3300-codec { - pinmux { - pins = "gpio83"; - function = "gpio"; - }; - - pinconf { - pins = "gpio83"; - drive-strength = <2>; - bias-disable; - }; - }; - - en_pp3300_dx_edp: en-pp3300-dx-edp { - pinmux { - pins = "gpio30"; - function = "gpio"; - }; - - pinconf { - pins = "gpio30"; - drive-strength = <2>; - bias-disable; - }; - }; - - fpmcu_boot0: fpmcu-boot0 { - pinmux { - pins = "gpio10"; - function = "gpio"; - }; - - pinconf { - pins = "gpio10"; - bias-disable; - drive-strength = <2>; - output-low; - }; - }; - - fpmcu_sel: fpmcu-sel { - pinmux { - pins = "gpio22"; - function = "gpio"; - }; - - pinconf { - pins = "gpio22"; - bias-disable; - drive-strength = <2>; - output-high; - }; - }; - - fp_rst_l: fp-rst-l { - pinmux { - pins = "gpio5"; - function = "gpio"; - }; - - pinconf { - pins = "gpio5"; - bias-disable; - drive-strength = <2>; - output-high; - }; - }; - - fp_to_ap_irq_l: fp-to-ap-irq-l { - pinmux { - pins = "gpio4"; - function = "gpio"; - input-enable; - }; - - pinconf { - pins = "gpio4"; - - /* Has external pullup */ - bias-disable; - }; - }; - - - h1_ap_int_odl: h1-ap-int-odl { - pinmux { - pins = "gpio42"; - function = "gpio"; - input-enable; - }; - - pinconf { - pins = "gpio42"; - bias-pull-up; - }; - }; - - hp_irq: hp-irq { - pinmux { - pins = "gpio28"; - function = "gpio"; - }; - - pinconf { - pins = "gpio28"; - bias-pull-up; - }; - }; - - pen_irq_l: pen-irq-l { - pinmux { - pins = "gpio21"; - function = "gpio"; - }; - - pinconf { - pins = "gpio21"; - - /* Has external pullup */ - bias-disable; - }; - }; - - pen_pdct_l: pen-pdct-l { - pinmux { - pins = "gpio52"; - function = "gpio"; - }; - - pinconf { - pins = "gpio52"; - - /* Has external pullup */ - bias-disable; - }; - }; - - pen_rst_odl: pen-rst-odl { - pinmux { - pins = "gpio18"; - function = "gpio"; - }; - - pinconf { - pins = "gpio18"; - bias-disable; - drive-strength = <2>; - - /* - * The pen driver doesn't currently support - * driving this reset line. By specifying - * output-high here we're relying on the fact - * that this pin has a default pulldown at boot - * (which makes sure the pen was in reset if it - * was powered) and then we set it high here to - * take it out of reset. Better would be if the - * pen driver could control this and we could - * remove "output-high" here. - */ - output-high; /* TODO: Remove this? */ - }; - }; - - p_sensor_int_l: p-sensor-int-l { - pinmux { - pins = "gpio24"; - function = "gpio"; - input-enable; - }; - - pinconf { - pins = "gpio24"; - bias-pull-up; - }; - }; - - qup_uart3_sleep: qup-uart3-sleep { - pinmux { - pins = "gpio38", "gpio39", - "gpio40", "gpio41"; - function = "gpio"; - }; - - pinconf-cts { - /* - * Configure a pull-down on CTS to match the pull of - * the Bluetooth module. - */ - pins = "gpio38"; - bias-pull-down; - }; - - pinconf-rts { - /* - * Configure pull-down on RTS. As RTS is active low - * signal, pull it low to indicate the BT SoC that it - * can wakeup the system anytime from suspend state by - * pulling RX low (by sending wakeup bytes). - */ - pins = "gpio39"; - bias-pull-down; - }; - - pinconf-tx { - /* - * Configure pull-up on TX when it isn't actively driven - * to prevent BT SoC from receiving garbage during sleep. - */ - pins = "gpio40"; - bias-pull-up; - }; - - pinconf-rx { - /* - * Configure a pull-up on RX. This is needed to avoid - * garbage data when the TX pin of the Bluetooth module - * is floating which may cause spurious wakeups. - */ - pins = "gpio41"; - bias-pull-up; - }; - }; - - trackpad_int_1v8_odl: trackpad-int-1v8-odl { - pinmux { - pins = "gpio58"; - function = "gpio"; - }; - - pinconf { - pins = "gpio58"; - - /* Has external pullup */ - bias-disable; - }; - }; - - ts_int_l: ts-int-l { - pinmux { - pins = "gpio9"; - function = "gpio"; - }; - - pinconf { - pins = "gpio9"; - bias-pull-up; - }; - }; - - ts_reset_l: ts-reset-l { - pinmux { - pins = "gpio8"; - function = "gpio"; - }; - - pinconf { - pins = "gpio8"; - bias-disable; - drive-strength = <2>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi deleted file mode 100644 index c71f3afc1..000000000 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ /dev/null @@ -1,4184 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * SC7180 SoC device tree source - * - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - i2c9 = &i2c9; - i2c10 = &i2c10; - i2c11 = &i2c11; - spi0 = &spi0; - spi1 = &spi1; - spi3 = &spi3; - spi5 = &spi5; - spi6 = &spi6; - spi8 = &spi8; - spi10 = &spi10; - spi11 = &spi11; - }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - clock-frequency = <38400000>; - #clock-cells = <0>; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - clock-frequency = <32764>; - #clock-cells = <0>; - }; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@80000000 { - reg = <0x0 0x80000000 0x0 0x600000>; - no-map; - }; - - xbl_mem: memory@80600000 { - reg = <0x0 0x80600000 0x0 0x200000>; - no-map; - }; - - aop_mem: memory@80800000 { - reg = <0x0 0x80800000 0x0 0x20000>; - no-map; - }; - - aop_cmd_db_mem: memory@80820000 { - reg = <0x0 0x80820000 0x0 0x20000>; - compatible = "qcom,cmd-db"; - no-map; - }; - - sec_apps_mem: memory@808ff000 { - reg = <0x0 0x808ff000 0x0 0x1000>; - no-map; - }; - - smem_mem: memory@80900000 { - reg = <0x0 0x80900000 0x0 0x200000>; - no-map; - }; - - tz_mem: memory@80b00000 { - reg = <0x0 0x80b00000 0x0 0x3900000>; - no-map; - }; - - rmtfs_mem: memory@84400000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x84400000 0x0 0x200000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo468"; - reg = <0x0 0x0>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <100>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - next-level-cache = <&L2_0>; - #cooling-cells = <2>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo468"; - reg = <0x0 0x100>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <100>; - next-level-cache = <&L2_100>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo468"; - reg = <0x0 0x200>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <100>; - next-level-cache = <&L2_200>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo468"; - reg = <0x0 0x300>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <100>; - next-level-cache = <&L2_300>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo468"; - reg = <0x0 0x400>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <100>; - next-level-cache = <&L2_400>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo468"; - reg = <0x0 0x500>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <100>; - next-level-cache = <&L2_500>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - qcom,freq-domain = <&cpufreq_hw 0>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo468"; - reg = <0x0 0x600>; - enable-method = "psci"; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1740>; - dynamic-power-coefficient = <405>; - next-level-cache = <&L2_600>; - operating-points-v2 = <&cpu6_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - qcom,freq-domain = <&cpufreq_hw 1>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo468"; - reg = <0x0 0x700>; - enable-method = "psci"; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1740>; - dynamic-power-coefficient = <405>; - next-level-cache = <&L2_700>; - operating-points-v2 = <&cpu6_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - qcom,freq-domain = <&cpufreq_hw 1>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - - core4 { - cpu = <&CPU4>; - }; - - core5 { - cpu = <&CPU5>; - }; - - core6 { - cpu = <&CPU6>; - }; - - core7 { - cpu = <&CPU7>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "little-power-down"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <549>; - exit-latency-us = <901>; - min-residency-us = <1774>; - local-timer-stop; - }; - - LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { - compatible = "arm,idle-state"; - idle-state-name = "little-rail-power-down"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <702>; - exit-latency-us = <915>; - min-residency-us = <4001>; - local-timer-stop; - }; - - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "big-power-down"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <523>; - exit-latency-us = <1244>; - min-residency-us = <2207>; - local-timer-stop; - }; - - BIG_CPU_SLEEP_1: cpu-sleep-1-1 { - compatible = "arm,idle-state"; - idle-state-name = "big-rail-power-down"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <526>; - exit-latency-us = <1854>; - min-residency-us = <5555>; - local-timer-stop; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - idle-state-name = "cluster-power-down"; - arm,psci-suspend-param = <0x40003444>; - entry-latency-us = <3263>; - exit-latency-us = <6562>; - min-residency-us = <9926>; - local-timer-stop; - }; - }; - }; - - cpu0_opp_table: cpu0_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - cpu0_opp1: opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-peak-kBps = <1200000 4800000>; - }; - - cpu0_opp2: opp-576000000 { - opp-hz = /bits/ 64 <576000000>; - opp-peak-kBps = <1200000 4800000>; - }; - - cpu0_opp3: opp-768000000 { - opp-hz = /bits/ 64 <768000000>; - opp-peak-kBps = <1200000 4800000>; - }; - - cpu0_opp4: opp-1017600000 { - opp-hz = /bits/ 64 <1017600000>; - opp-peak-kBps = <1804000 8908800>; - }; - - cpu0_opp5: opp-1248000000 { - opp-hz = /bits/ 64 <1248000000>; - opp-peak-kBps = <2188000 12902400>; - }; - - cpu0_opp6: opp-1324800000 { - opp-hz = /bits/ 64 <1324800000>; - opp-peak-kBps = <2188000 12902400>; - }; - - cpu0_opp7: opp-1516800000 { - opp-hz = /bits/ 64 <1516800000>; - opp-peak-kBps = <3072000 15052800>; - }; - - cpu0_opp8: opp-1612800000 { - opp-hz = /bits/ 64 <1612800000>; - opp-peak-kBps = <3072000 15052800>; - }; - - cpu0_opp9: opp-1708800000 { - opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <3072000 15052800>; - }; - - cpu0_opp10: opp-1804800000 { - opp-hz = /bits/ 64 <1804800000>; - opp-peak-kBps = <4068000 22425600>; - }; - }; - - cpu6_opp_table: cpu6_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - cpu6_opp1: opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-peak-kBps = <2188000 8908800>; - }; - - cpu6_opp2: opp-652800000 { - opp-hz = /bits/ 64 <652800000>; - opp-peak-kBps = <2188000 8908800>; - }; - - cpu6_opp3: opp-825600000 { - opp-hz = /bits/ 64 <825600000>; - opp-peak-kBps = <2188000 8908800>; - }; - - cpu6_opp4: opp-979200000 { - opp-hz = /bits/ 64 <979200000>; - opp-peak-kBps = <2188000 8908800>; - }; - - cpu6_opp5: opp-1113600000 { - opp-hz = /bits/ 64 <1113600000>; - opp-peak-kBps = <2188000 8908800>; - }; - - cpu6_opp6: opp-1267200000 { - opp-hz = /bits/ 64 <1267200000>; - opp-peak-kBps = <4068000 12902400>; - }; - - cpu6_opp7: opp-1555200000 { - opp-hz = /bits/ 64 <1555200000>; - opp-peak-kBps = <4068000 15052800>; - }; - - cpu6_opp8: opp-1708800000 { - opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <6220000 19353600>; - }; - - cpu6_opp9: opp-1843200000 { - opp-hz = /bits/ 64 <1843200000>; - opp-peak-kBps = <6220000 19353600>; - }; - - cpu6_opp10: opp-1900800000 { - opp-hz = /bits/ 64 <1900800000>; - opp-peak-kBps = <6220000 22425600>; - }; - - cpu6_opp11: opp-1996800000 { - opp-hz = /bits/ 64 <1996800000>; - opp-peak-kBps = <6220000 22425600>; - }; - - cpu6_opp12: opp-2112000000 { - opp-hz = /bits/ 64 <2112000000>; - opp-peak-kBps = <6220000 22425600>; - }; - - cpu6_opp13: opp-2208000000 { - opp-hz = /bits/ 64 <2208000000>; - opp-peak-kBps = <7216000 22425600>; - }; - - cpu6_opp14: opp-2323200000 { - opp-hz = /bits/ 64 <2323200000>; - opp-peak-kBps = <7216000 22425600>; - }; - - cpu6_opp15: opp-2400000000 { - opp-hz = /bits/ 64 <2400000000>; - opp-peak-kBps = <8532000 23347200>; - }; - }; - - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0 0x80000000 0 0>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - firmware { - scm { - compatible = "qcom,scm-sc7180", "qcom,scm"; - }; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - - interrupts = ; - - mboxes = <&apss_shared 6>; - - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - cdsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - cdsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-lpass { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - - interrupts = ; - - mboxes = <&apss_shared 10>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - adsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - adsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-mpss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - interrupts = ; - mboxes = <&apss_shared 14>; - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - ipa_smp2p_out: ipa-ap-to-modem { - qcom,entry-name = "ipa"; - #qcom,smem-state-cells = <1>; - }; - - ipa_smp2p_in: ipa-modem-to-ap { - qcom,entry-name = "ipa"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - soc: soc@0 { - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0 0 0 0x10 0>; - dma-ranges = <0 0 0 0 0x10 0>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sc7180"; - reg = <0 0x00100000 0 0x1f0000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>, - <&sleep_clk>; - clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - qfprom: efuse@784000 { - compatible = "qcom,qfprom"; - reg = <0 0x00784000 0 0x8ff>, - <0 0x00780000 0 0x7a0>, - <0 0x00782000 0 0x100>, - <0 0x00786000 0 0x1fff>; - - clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; - clock-names = "core"; - #address-cells = <1>; - #size-cells = <1>; - - qusb2p_hstx_trim: hstx-trim-primary@25b { - reg = <0x25b 0x1>; - bits = <1 3>; - }; - }; - - sdhc_1: sdhci@7c4000 { - compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; - reg = <0 0x7c4000 0 0x1000>, - <0 0x07c5000 0 0x1000>; - reg-names = "hc", "cqhci"; - - iommus = <&apps_smmu 0x60 0x0>; - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; - interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; - interconnect-names = "sdhc-ddr","cpu-sdhc"; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&sdhc1_opp_table>; - - bus-width = <8>; - non-removable; - supports-cqe; - - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - - status = "disabled"; - - sdhc1_opp_table: sdhc1-opp-table { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <100000 100000>; - opp-avg-kBps = <100000 50000>; - }; - - opp-384000000 { - opp-hz = /bits/ 64 <384000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - opp-peak-kBps = <600000 900000>; - opp-avg-kBps = <261438 300000>; - }; - }; - }; - - qup_opp_table: qup-opp-table { - compatible = "operating-points-v2"; - - opp-75000000 { - opp-hz = /bits/ 64 <75000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-128000000 { - opp-hz = /bits/ 64 <128000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - - qupv3_id_0: geniqup@8c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0 0x008c0000 0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - iommus = <&apps_smmu 0x43 0x0>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>; - interconnect-names = "qup-core"; - status = "disabled"; - - i2c0: i2c@880000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c0_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, - <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", - "qup-memory"; - status = "disabled"; - }; - - spi0: spi@880000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi0_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - uart0: serial@880000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart0_default>; - interrupts = ; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c1: i2c@884000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c1_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, - <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", - "qup-memory"; - status = "disabled"; - }; - - spi1: spi@884000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi1_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - uart1: serial@884000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart1_default>; - interrupts = ; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c2: i2c@888000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00888000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c2_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, - <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", - "qup-memory"; - status = "disabled"; - }; - - uart2: serial@888000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00888000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart2_default>; - interrupts = ; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c3: i2c@88c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c3_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, - <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", - "qup-memory"; - status = "disabled"; - }; - - spi3: spi@88c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi3_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - uart3: serial@88c000 { - compatible = "qcom,geni-uart"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart3_default>; - interrupts = ; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c4: i2c@890000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c4_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, - <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", - "qup-memory"; - status = "disabled"; - }; - - uart4: serial@890000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart4_default>; - interrupts = ; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c5: i2c@894000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c5_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, - <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", - "qup-memory"; - status = "disabled"; - }; - - spi5: spi@894000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi5_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - uart5: serial@894000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart5_default>; - interrupts = ; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - }; - - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0 0x00ac0000 0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - iommus = <&apps_smmu 0x4c3 0x0>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>; - interconnect-names = "qup-core"; - status = "disabled"; - - i2c6: i2c@a80000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c6_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", - "qup-memory"; - status = "disabled"; - }; - - spi6: spi@a80000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi6_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - uart6: serial@a80000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart6_default>; - interrupts = ; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c7: i2c@a84000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c7_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", - "qup-memory"; - status = "disabled"; - }; - - uart7: serial@a84000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart7_default>; - interrupts = ; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c8: i2c@a88000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c8_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", - "qup-memory"; - status = "disabled"; - }; - - spi8: spi@a88000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi8_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - uart8: serial@a88000 { - compatible = "qcom,geni-debug-uart"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart8_default>; - interrupts = ; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c9: i2c@a8c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c9_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", - "qup-memory"; - status = "disabled"; - }; - - uart9: serial@a8c000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart9_default>; - interrupts = ; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c10: i2c@a90000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c10_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", - "qup-memory"; - status = "disabled"; - }; - - spi10: spi@a90000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi10_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - uart10: serial@a90000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart10_default>; - interrupts = ; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - i2c11: i2c@a94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c11_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "qup-core", "qup-config", - "qup-memory"; - status = "disabled"; - }; - - spi11: spi@a94000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi11_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - - uart11: serial@a94000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart11_default>; - interrupts = ; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&qup_opp_table>; - interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; - interconnect-names = "qup-core", "qup-config"; - status = "disabled"; - }; - }; - - config_noc: interconnect@1500000 { - compatible = "qcom,sc7180-config-noc"; - reg = <0 0x01500000 0 0x28000>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect@1620000 { - compatible = "qcom,sc7180-system-noc"; - reg = <0 0x01620000 0 0x17080>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mc_virt: interconnect@1638000 { - compatible = "qcom,sc7180-mc-virt"; - reg = <0 0x01638000 0 0x1000>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - qup_virt: interconnect@1650000 { - compatible = "qcom,sc7180-qup-virt"; - reg = <0 0x01650000 0 0x1000>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre1_noc: interconnect@16e0000 { - compatible = "qcom,sc7180-aggre1-noc"; - reg = <0 0x016e0000 0 0x15080>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect@1705000 { - compatible = "qcom,sc7180-aggre2-noc"; - reg = <0 0x01705000 0 0x9000>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - compute_noc: interconnect@170e000 { - compatible = "qcom,sc7180-compute-noc"; - reg = <0 0x0170e000 0 0x6000>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mmss_noc: interconnect@1740000 { - compatible = "qcom,sc7180-mmss-noc"; - reg = <0 0x01740000 0 0x1c100>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - ipa_virt: interconnect@1e00000 { - compatible = "qcom,sc7180-ipa-virt"; - reg = <0 0x01e00000 0 0x1000>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - ipa: ipa@1e40000 { - compatible = "qcom,sc7180-ipa"; - - iommus = <&apps_smmu 0x440 0x0>, - <&apps_smmu 0x442 0x0>; - reg = <0 0x1e40000 0 0x7000>, - <0 0x1e47000 0 0x2000>, - <0 0x1e04000 0 0x2c000>; - reg-names = "ipa-reg", - "ipa-shared", - "gsi"; - - interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>, - <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, - <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ipa", - "gsi", - "ipa-clock-query", - "ipa-setup-ready"; - - clocks = <&rpmhcc RPMH_IPA_CLK>; - clock-names = "core"; - - interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, - <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; - interconnect-names = "memory", - "imem", - "config"; - - qcom,smem-states = <&ipa_smp2p_out 0>, - <&ipa_smp2p_out 1>; - qcom,smem-state-names = "ipa-clock-enabled-valid", - "ipa-clock-enabled"; - - modem-remoteproc = <&remoteproc_mpss>; - - status = "disabled"; - }; - - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0 0x01f40000 0 0x40000>; - }; - - tcsr_regs: syscon@1fc0000 { - compatible = "syscon"; - reg = <0 0x01fc0000 0 0x40000>; - }; - - tlmm: pinctrl@3500000 { - compatible = "qcom,sc7180-pinctrl"; - reg = <0 0x03500000 0 0x300000>, - <0 0x03900000 0 0x300000>, - <0 0x03d00000 0 0x300000>; - reg-names = "west", "north", "south"; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 120>; - wakeup-parent = <&pdc>; - - dp_hot_plug_det: dp-hot-plug-det { - pinmux { - pins = "gpio117"; - function = "dp_hot"; - }; - - pinconf { - pins = "gpio117"; - bias-disable; - input-enable; - }; - }; - - qspi_clk: qspi-clk { - pinmux { - pins = "gpio63"; - function = "qspi_clk"; - }; - }; - - qspi_cs0: qspi-cs0 { - pinmux { - pins = "gpio68"; - function = "qspi_cs"; - }; - }; - - qspi_cs1: qspi-cs1 { - pinmux { - pins = "gpio72"; - function = "qspi_cs"; - }; - }; - - qspi_data01: qspi-data01 { - pinmux-data { - pins = "gpio64", "gpio65"; - function = "qspi_data"; - }; - }; - - qspi_data12: qspi-data12 { - pinmux-data { - pins = "gpio66", "gpio67"; - function = "qspi_data"; - }; - }; - - qup_i2c0_default: qup-i2c0-default { - pinmux { - pins = "gpio34", "gpio35"; - function = "qup00"; - }; - }; - - qup_i2c1_default: qup-i2c1-default { - pinmux { - pins = "gpio0", "gpio1"; - function = "qup01"; - }; - }; - - qup_i2c2_default: qup-i2c2-default { - pinmux { - pins = "gpio15", "gpio16"; - function = "qup02_i2c"; - }; - }; - - qup_i2c3_default: qup-i2c3-default { - pinmux { - pins = "gpio38", "gpio39"; - function = "qup03"; - }; - }; - - qup_i2c4_default: qup-i2c4-default { - pinmux { - pins = "gpio115", "gpio116"; - function = "qup04_i2c"; - }; - }; - - qup_i2c5_default: qup-i2c5-default { - pinmux { - pins = "gpio25", "gpio26"; - function = "qup05"; - }; - }; - - qup_i2c6_default: qup-i2c6-default { - pinmux { - pins = "gpio59", "gpio60"; - function = "qup10"; - }; - }; - - qup_i2c7_default: qup-i2c7-default { - pinmux { - pins = "gpio6", "gpio7"; - function = "qup11_i2c"; - }; - }; - - qup_i2c8_default: qup-i2c8-default { - pinmux { - pins = "gpio42", "gpio43"; - function = "qup12"; - }; - }; - - qup_i2c9_default: qup-i2c9-default { - pinmux { - pins = "gpio46", "gpio47"; - function = "qup13_i2c"; - }; - }; - - qup_i2c10_default: qup-i2c10-default { - pinmux { - pins = "gpio86", "gpio87"; - function = "qup14"; - }; - }; - - qup_i2c11_default: qup-i2c11-default { - pinmux { - pins = "gpio53", "gpio54"; - function = "qup15"; - }; - }; - - qup_spi0_default: qup-spi0-default { - pinmux { - pins = "gpio34", "gpio35", - "gpio36", "gpio37"; - function = "qup00"; - }; - }; - - qup_spi1_default: qup-spi1-default { - pinmux { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - function = "qup01"; - }; - }; - - qup_spi3_default: qup-spi3-default { - pinmux { - pins = "gpio38", "gpio39", - "gpio40", "gpio41"; - function = "qup03"; - }; - }; - - qup_spi5_default: qup-spi5-default { - pinmux { - pins = "gpio25", "gpio26", - "gpio27", "gpio28"; - function = "qup05"; - }; - }; - - qup_spi6_default: qup-spi6-default { - pinmux { - pins = "gpio59", "gpio60", - "gpio61", "gpio62"; - function = "qup10"; - }; - }; - - qup_spi8_default: qup-spi8-default { - pinmux { - pins = "gpio42", "gpio43", - "gpio44", "gpio45"; - function = "qup12"; - }; - }; - - qup_spi10_default: qup-spi10-default { - pinmux { - pins = "gpio86", "gpio87", - "gpio88", "gpio89"; - function = "qup14"; - }; - }; - - qup_spi11_default: qup-spi11-default { - pinmux { - pins = "gpio53", "gpio54", - "gpio55", "gpio56"; - function = "qup15"; - }; - }; - - qup_uart0_default: qup-uart0-default { - pinmux { - pins = "gpio34", "gpio35", - "gpio36", "gpio37"; - function = "qup00"; - }; - }; - - qup_uart1_default: qup-uart1-default { - pinmux { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - function = "qup01"; - }; - }; - - qup_uart2_default: qup-uart2-default { - pinmux { - pins = "gpio15", "gpio16"; - function = "qup02_uart"; - }; - }; - - qup_uart3_default: qup-uart3-default { - pinmux { - pins = "gpio38", "gpio39", - "gpio40", "gpio41"; - function = "qup03"; - }; - }; - - qup_uart4_default: qup-uart4-default { - pinmux { - pins = "gpio115", "gpio116"; - function = "qup04_uart"; - }; - }; - - qup_uart5_default: qup-uart5-default { - pinmux { - pins = "gpio25", "gpio26", - "gpio27", "gpio28"; - function = "qup05"; - }; - }; - - qup_uart6_default: qup-uart6-default { - pinmux { - pins = "gpio59", "gpio60", - "gpio61", "gpio62"; - function = "qup10"; - }; - }; - - qup_uart7_default: qup-uart7-default { - pinmux { - pins = "gpio6", "gpio7"; - function = "qup11_uart"; - }; - }; - - qup_uart8_default: qup-uart8-default { - pinmux { - pins = "gpio44", "gpio45"; - function = "qup12"; - }; - }; - - qup_uart9_default: qup-uart9-default { - pinmux { - pins = "gpio46", "gpio47"; - function = "qup13_uart"; - }; - }; - - qup_uart10_default: qup-uart10-default { - pinmux { - pins = "gpio86", "gpio87", - "gpio88", "gpio89"; - function = "qup14"; - }; - }; - - qup_uart11_default: qup-uart11-default { - pinmux { - pins = "gpio53", "gpio54", - "gpio55", "gpio56"; - function = "qup15"; - }; - }; - - sdc1_on: sdc1-on { - pinconf-clk { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <16>; - }; - - pinconf-cmd { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - pinconf-data { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <10>; - }; - - pinconf-rclk { - pins = "sdc1_rclk"; - bias-pull-down; - }; - }; - - sdc1_off: sdc1-off { - pinconf-clk { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <2>; - }; - - pinconf-cmd { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - pinconf-data { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <2>; - }; - - pinconf-rclk { - pins = "sdc1_rclk"; - bias-pull-down; - }; - }; - - sdc2_on: sdc2-on { - pinconf-clk { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <16>; - }; - - pinconf-cmd { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - pinconf-data { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <10>; - }; - - pinconf-sd-cd { - pins = "gpio69"; - bias-pull-up; - drive-strength = <2>; - }; - }; - - sdc2_off: sdc2-off { - pinconf-clk { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <2>; - }; - - pinconf-cmd { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - pinconf-data { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <2>; - }; - - pinconf-sd-cd { - pins = "gpio69"; - bias-disable; - drive-strength = <2>; - }; - }; - }; - - remoteproc_mpss: remoteproc@4080000 { - compatible = "qcom,sc7180-mpss-pas"; - reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; - reg-names = "qdsp6", "rmb"; - - interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", - "stop-ack", "shutdown-ack"; - - clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, - <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, - <&gcc GCC_MSS_NAV_AXI_CLK>, - <&gcc GCC_MSS_SNOC_AXI_CLK>, - <&gcc GCC_MSS_MFAB_AXIS_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "bus", "nav", "snoc_axi", - "mnoc_axi", "xo"; - - power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, - <&rpmhpd SC7180_CX>, - <&rpmhpd SC7180_MX>, - <&rpmhpd SC7180_MSS>; - power-domain-names = "load_state", "cx", "mx", "mss"; - - memory-region = <&mpss_mem>; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - resets = <&aoss_reset AOSS_CC_MSS_RESTART>, - <&pdc_reset PDC_MODEM_SYNC_RESET>; - reset-names = "mss_restart", "pdc_reset"; - - qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; - qcom,spare-regs = <&tcsr_regs 0xb3e4>; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "modem"; - qcom,remote-pid = <1>; - mboxes = <&apss_shared 12>; - }; - }; - - gpu: gpu@5000000 { - compatible = "qcom,adreno-618.0", "qcom,adreno"; - #stream-id-cells = <16>; - reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, - <0 0x05061000 0 0x800>; - reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; - interrupts = ; - iommus = <&adreno_smmu 0>; - operating-points-v2 = <&gpu_opp_table>; - qcom,gmu = <&gmu>; - - interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "gfx-mem"; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-level = ; - opp-peak-kBps = <8532000>; - }; - - opp-650000000 { - opp-hz = /bits/ 64 <650000000>; - opp-level = ; - opp-peak-kBps = <7216000>; - }; - - opp-565000000 { - opp-hz = /bits/ 64 <565000000>; - opp-level = ; - opp-peak-kBps = <5412000>; - }; - - opp-430000000 { - opp-hz = /bits/ 64 <430000000>; - opp-level = ; - opp-peak-kBps = <5412000>; - }; - - opp-355000000 { - opp-hz = /bits/ 64 <355000000>; - opp-level = ; - opp-peak-kBps = <3072000>; - }; - - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-level = ; - opp-peak-kBps = <3072000>; - }; - - opp-180000000 { - opp-hz = /bits/ 64 <180000000>; - opp-level = ; - opp-peak-kBps = <1804000>; - }; - }; - }; - - adreno_smmu: iommu@5040000 { - compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; - reg = <0 0x05040000 0 0x10000>; - #iommu-cells = <1>; - #global-interrupts = <2>; - interrupts = , - , - , - , - , - , - , - , - , - ; - - clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gcc GCC_GPU_CFG_AHB_CLK>; - clock-names = "bus", "iface"; - - power-domains = <&gpucc CX_GDSC>; - }; - - gmu: gmu@506a000 { - compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; - reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, - <0 0x0b490000 0 0x10000>; - reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; - interrupts = , - ; - interrupt-names = "hfi", "gmu"; - clocks = <&gpucc GPU_CC_CX_GMU_CLK>, - <&gpucc GPU_CC_CXO_CLK>, - <&gcc GCC_DDRSS_GPU_AXI_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>; - clock-names = "gmu", "cxo", "axi", "memnoc"; - power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; - power-domain-names = "cx", "gx"; - iommus = <&adreno_smmu 5>; - operating-points-v2 = <&gmu_opp_table>; - - gmu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-level = ; - }; - }; - }; - - gpucc: clock-controller@5090000 { - compatible = "qcom,sc7180-gpucc"; - reg = <0 0x05090000 0 0x9000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_GPU_GPLL0_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; - clock-names = "bi_tcxo", - "gcc_gpu_gpll0_clk_src", - "gcc_gpu_gpll0_div_clk_src"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - stm@6002000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0 0x06002000 0 0x1000>, - <0 0x16280000 0 0x180000>; - reg-names = "stm-base", "stm-stimulus-base"; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - stm_out: endpoint { - remote-endpoint = <&funnel0_in7>; - }; - }; - }; - }; - - funnel@6041000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06041000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel0_out: endpoint { - remote-endpoint = <&merge_funnel_in0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@7 { - reg = <7>; - funnel0_in7: endpoint { - remote-endpoint = <&stm_out>; - }; - }; - }; - }; - - funnel@6042000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06042000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel1_out: endpoint { - remote-endpoint = <&merge_funnel_in1>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@4 { - reg = <4>; - funnel1_in4: endpoint { - remote-endpoint = <&apss_merge_funnel_out>; - }; - }; - }; - }; - - funnel@6045000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06045000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - merge_funnel_out: endpoint { - remote-endpoint = <&swao_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - merge_funnel_in0: endpoint { - remote-endpoint = <&funnel0_out>; - }; - }; - - port@1 { - reg = <1>; - merge_funnel_in1: endpoint { - remote-endpoint = <&funnel1_out>; - }; - }; - }; - }; - - replicator@6046000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x06046000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - replicator_out: endpoint { - remote-endpoint = <&etr_in>; - }; - }; - }; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = <&swao_replicator_out>; - }; - }; - }; - }; - - etr@6048000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06048000 0 0x1000>; - iommus = <&apps_smmu 0x04a0 0x20>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,scatter-gather; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = <&replicator_out>; - }; - }; - }; - }; - - funnel@6b04000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06b04000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - swao_funnel_out: endpoint { - remote-endpoint = <&etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@7 { - reg = <7>; - swao_funnel_in: endpoint { - remote-endpoint = <&merge_funnel_out>; - }; - }; - }; - }; - - etf@6b05000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06b05000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = <&swao_replicator_in>; - }; - }; - }; - - in-ports { - port { - etf_in: endpoint { - remote-endpoint = <&swao_funnel_out>; - }; - }; - }; - }; - - replicator@6b06000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x06b06000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - qcom,replicator-loses-context; - - out-ports { - port { - swao_replicator_out: endpoint { - remote-endpoint = <&replicator_in>; - }; - }; - }; - - in-ports { - port { - swao_replicator_in: endpoint { - remote-endpoint = <&etf_out>; - }; - }; - }; - }; - - etm@7040000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07040000 0 0x1000>; - - cpu = <&CPU0>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = <&apss_funnel_in0>; - }; - }; - }; - }; - - etm@7140000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07140000 0 0x1000>; - - cpu = <&CPU1>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = <&apss_funnel_in1>; - }; - }; - }; - }; - - etm@7240000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07240000 0 0x1000>; - - cpu = <&CPU2>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = <&apss_funnel_in2>; - }; - }; - }; - }; - - etm@7340000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07340000 0 0x1000>; - - cpu = <&CPU3>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = <&apss_funnel_in3>; - }; - }; - }; - }; - - etm@7440000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07440000 0 0x1000>; - - cpu = <&CPU4>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm4_out: endpoint { - remote-endpoint = <&apss_funnel_in4>; - }; - }; - }; - }; - - etm@7540000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07540000 0 0x1000>; - - cpu = <&CPU5>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm5_out: endpoint { - remote-endpoint = <&apss_funnel_in5>; - }; - }; - }; - }; - - etm@7640000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07640000 0 0x1000>; - - cpu = <&CPU6>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm6_out: endpoint { - remote-endpoint = <&apss_funnel_in6>; - }; - }; - }; - }; - - etm@7740000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07740000 0 0x1000>; - - cpu = <&CPU7>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - qcom,skip-power-up; - - out-ports { - port { - etm7_out: endpoint { - remote-endpoint = <&apss_funnel_in7>; - }; - }; - }; - }; - - funnel@7800000 { /* APSS Funnel */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x07800000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - apss_funnel_out: endpoint { - remote-endpoint = <&apss_merge_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - apss_funnel_in0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - apss_funnel_in1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - - port@2 { - reg = <2>; - apss_funnel_in2: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - - port@3 { - reg = <3>; - apss_funnel_in3: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - - port@4 { - reg = <4>; - apss_funnel_in4: endpoint { - remote-endpoint = <&etm4_out>; - }; - }; - - port@5 { - reg = <5>; - apss_funnel_in5: endpoint { - remote-endpoint = <&etm5_out>; - }; - }; - - port@6 { - reg = <6>; - apss_funnel_in6: endpoint { - remote-endpoint = <&etm6_out>; - }; - }; - - port@7 { - reg = <7>; - apss_funnel_in7: endpoint { - remote-endpoint = <&etm7_out>; - }; - }; - }; - }; - - funnel@7810000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x07810000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - apss_merge_funnel_out: endpoint { - remote-endpoint = <&funnel1_in4>; - }; - }; - }; - - in-ports { - port { - apss_merge_funnel_in: endpoint { - remote-endpoint = <&apss_funnel_out>; - }; - }; - }; - }; - - sdhc_2: sdhci@8804000 { - compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; - reg = <0 0x08804000 0 0x1000>; - - iommus = <&apps_smmu 0x80 0>; - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>; - clock-names = "core", "iface"; - - interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; - interconnect-names = "sdhc-ddr","cpu-sdhc"; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&sdhc2_opp_table>; - - bus-width = <4>; - - status = "disabled"; - - sdhc2_opp_table: sdhc2-opp-table { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <160000 100000>; - opp-avg-kBps = <80000 50000>; - }; - - opp-202000000 { - opp-hz = /bits/ 64 <202000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - opp-peak-kBps = <200000 120000>; - opp-avg-kBps = <100000 60000>; - }; - }; - }; - - qspi_opp_table: qspi-opp-table { - compatible = "operating-points-v2"; - - opp-75000000 { - opp-hz = /bits/ 64 <75000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-150000000 { - opp-hz = /bits/ 64 <150000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - - qspi: spi@88dc000 { - compatible = "qcom,qspi-v1"; - reg = <0 0x088dc000 0 0x600>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, - <&gcc GCC_QSPI_CORE_CLK>; - clock-names = "iface", "core"; - interconnects = <&gem_noc MASTER_APPSS_PROC 0 - &config_noc SLAVE_QSPI_0 0>; - interconnect-names = "qspi-config"; - power-domains = <&rpmhpd SC7180_CX>; - operating-points-v2 = <&qspi_opp_table>; - status = "disabled"; - }; - - usb_1_hsphy: phy@88e3000 { - compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; - reg = <0 0x088e3000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "cfg_ahb", "ref"; - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - - nvmem-cells = <&qusb2p_hstx_trim>; - }; - - usb_1_qmpphy: phy-wrapper@88e9000 { - compatible = "qcom,sc7180-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x18c>, - <0 0x088e8000 0 0x38>; - reg-names = "reg-base", "dp_com"; - status = "disabled"; - #clock-cells = <1>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_USB3_PRIM_CLKREF_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "com_aux"; - - resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, - <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; - reset-names = "phy", "common"; - - usb_1_ssphy: phy@88e9200 { - reg = <0 0x088e9200 0 0x128>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x218>, - <0 0x088e9600 0 0x128>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x18>; - #clock-cells = <0>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; - }; - - dc_noc: interconnect@9160000 { - compatible = "qcom,sc7180-dc-noc"; - reg = <0 0x09160000 0 0x03200>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system-cache-controller@9200000 { - compatible = "qcom,sc7180-llcc"; - reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; - }; - - gem_noc: interconnect@9680000 { - compatible = "qcom,sc7180-gem-noc"; - reg = <0 0x09680000 0 0x3e200>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - npu_noc: interconnect@9990000 { - compatible = "qcom,sc7180-npu-noc"; - reg = <0 0x09990000 0 0x1600>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - usb_1: usb@a6f8800 { - compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <150000000>; - - interrupts = , - , - , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_PRIM_GDSC>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; - interconnect-names = "usb-ddr", "apps-usb"; - - usb_1_dwc3: dwc3@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xe000>; - interrupts = ; - iommus = <&apps_smmu 0x540 0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - maximum-speed = "super-speed"; - }; - }; - - venus: video-codec@aa00000 { - compatible = "qcom,sc7180-venus"; - reg = <0 0x0aa00000 0 0xff000>; - interrupts = ; - power-domains = <&videocc VENUS_GDSC>, - <&videocc VCODEC0_GDSC>, - <&rpmhpd SC7180_CX>; - power-domain-names = "venus", "vcodec0", "cx"; - operating-points-v2 = <&venus_opp_table>; - clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, - <&videocc VIDEO_CC_VENUS_AHB_CLK>, - <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, - <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, - <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; - clock-names = "core", "iface", "bus", - "vcodec0_core", "vcodec0_bus"; - iommus = <&apps_smmu 0x0c00 0x60>; - memory-region = <&venus_mem>; - interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; - interconnect-names = "video-mem", "cpu-cfg"; - - video-decoder { - compatible = "venus-decoder"; - }; - - video-encoder { - compatible = "venus-encoder"; - }; - - venus_opp_table: venus-opp-table { - compatible = "operating-points-v2"; - - opp-150000000 { - opp-hz = /bits/ 64 <150000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-270000000 { - opp-hz = /bits/ 64 <270000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-340000000 { - opp-hz = /bits/ 64 <340000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-434000000 { - opp-hz = /bits/ 64 <434000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - - opp-500000097 { - opp-hz = /bits/ 64 <500000097>; - required-opps = <&rpmhpd_opp_turbo>; - }; - }; - }; - - videocc: clock-controller@ab00000 { - compatible = "qcom,sc7180-videocc"; - reg = <0 0x0ab00000 0 0x10000>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "bi_tcxo"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - camnoc_virt: interconnect@ac00000 { - compatible = "qcom,sc7180-camnoc-virt"; - reg = <0 0x0ac00000 0 0x1000>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mdss: mdss@ae00000 { - compatible = "qcom,sc7180-mdss"; - reg = <0 0x0ae00000 0 0x1000>; - reg-names = "mdss"; - - power-domains = <&dispcc MDSS_GDSC>; - - clocks = <&gcc GCC_DISP_AHB_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", "ahb", "core"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - - interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "mdp0-mem"; - - iommus = <&apps_smmu 0x800 0x2>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - status = "disabled"; - - mdp: mdp@ae01000 { - compatible = "qcom,sc7180-dpu"; - reg = <0 0x0ae01000 0 0x8f000>, - <0 0x0aeb0000 0 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&gcc GCC_DISP_HF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_ROT_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "bus", "iface", "rot", "lut", "core", - "vsync"; - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, - <&dispcc DISP_CC_MDSS_ROT_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>; - assigned-clock-rates = <300000000>, - <19200000>, - <19200000>, - <19200000>; - operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd SC7180_CX>; - - interrupt-parent = <&mdss>; - interrupts = <0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; - - mdp_opp_table: mdp-opp-table { - compatible = "operating-points-v2"; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-345000000 { - opp-hz = /bits/ 64 <345000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-460000000 { - opp-hz = /bits/ 64 <460000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - - }; - - dsi0: dsi@ae94000 { - compatible = "qcom,mdss-dsi-ctrl"; - reg = <0 0x0ae94000 0 0x400>; - reg-names = "dsi_ctrl"; - - interrupt-parent = <&mdss>; - interrupts = <4>; - - clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, - <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK0_CLK>, - <&dispcc DISP_CC_MDSS_ESC0_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>; - clock-names = "byte", - "byte_intf", - "pixel", - "core", - "iface", - "bus"; - - operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmhpd SC7180_CX>; - - phys = <&dsi_phy>; - phy-names = "dsi"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - remote-endpoint = <&dpu_intf1_out>; - }; - }; - - port@1 { - reg = <1>; - dsi0_out: endpoint { - }; - }; - }; - - dsi_opp_table: dsi-opp-table { - compatible = "operating-points-v2"; - - opp-187500000 { - opp-hz = /bits/ 64 <187500000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-358000000 { - opp-hz = /bits/ 64 <358000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - }; - }; - - dsi_phy: dsi-phy@ae94400 { - compatible = "qcom,dsi-phy-10nm"; - reg = <0 0x0ae94400 0 0x200>, - <0 0x0ae94600 0 0x280>, - <0 0x0ae94a00 0 0x1e0>; - reg-names = "dsi_phy", - "dsi_phy_lane", - "dsi_pll"; - - #clock-cells = <1>; - #phy-cells = <0>; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "ref"; - - status = "disabled"; - }; - }; - - dispcc: clock-controller@af00000 { - compatible = "qcom,sc7180-dispcc"; - reg = <0 0x0af00000 0 0x200000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_DISP_GPLL0_CLK_SRC>, - <&dsi_phy 0>, - <&dsi_phy 1>, - <0>, - <0>; - clock-names = "bi_tcxo", - "gcc_disp_gpll0_clk_src", - "dsi0_phy_pll_out_byteclk", - "dsi0_phy_pll_out_dsiclk", - "dp_phy_pll_link_clk", - "dp_phy_pll_vco_div_clk"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - pdc: interrupt-controller@b220000 { - compatible = "qcom,sc7180-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>; - qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - pdc_reset: reset-controller@b2e0000 { - compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; - reg = <0 0x0b2e0000 0 0x20000>; - #reset-cells = <1>; - }; - - tsens0: thermal-sensor@c263000 { - compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1ff>, /* TM */ - <0 0x0c222000 0 0x1ff>; /* SROT */ - #qcom,sensors = <15>; - interrupts = , - ; - interrupt-names = "uplow","critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c265000 { - compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1ff>, /* TM */ - <0 0x0c223000 0 0x1ff>; /* SROT */ - #qcom,sensors = <10>; - interrupts = , - ; - interrupt-names = "uplow","critical"; - #thermal-sensor-cells = <1>; - }; - - aoss_reset: reset-controller@c2a0000 { - compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; - reg = <0 0x0c2a0000 0 0x31000>; - #reset-cells = <1>; - }; - - aoss_qmp: qmp@c300000 { - compatible = "qcom,sc7180-aoss-qmp"; - reg = <0 0x0c300000 0 0x100000>; - interrupts = ; - mboxes = <&apss_shared 0>; - - #clock-cells = <0>; - #power-domain-cells = <1>; - }; - - spmi_bus: spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0 0x0c440000 0 0x1100>, - <0 0x0c600000 0 0x2000000>, - <0 0x0e600000 0 0x100000>, - <0 0x0e700000 0 0xa0000>, - <0 0x0c40a000 0 0x26000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <1>; - #size-cells = <1>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; - reg = <0 0x15000000 0 0x100000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0 0x17a00000 0 0x10000>, /* GICD */ - <0 0x17a60000 0 0x100000>; /* GICR * 8 */ - interrupts = ; - - msi-controller@17a40000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0 0x17a40000 0 0x20000>; - status = "disabled"; - }; - }; - - apss_shared: mailbox@17c00000 { - compatible = "qcom,sc7180-apss-shared"; - reg = <0 0x17c00000 0 0x10000>; - #mbox-cells = <1>; - }; - - watchdog@17c10000 { - compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; - reg = <0 0x17c10000 0 0x1000>; - clocks = <&sleep_clk>; - }; - - timer@17c20000{ - #address-cells = <2>; - #size-cells = <2>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0 0x17c20000 0 0x1000>; - - frame@17c21000 { - frame-number = <0>; - interrupts = , - ; - reg = <0 0x17c21000 0 0x1000>, - <0 0x17c22000 0 0x1000>; - }; - - frame@17c23000 { - frame-number = <1>; - interrupts = ; - reg = <0 0x17c23000 0 0x1000>; - status = "disabled"; - }; - - frame@17c25000 { - frame-number = <2>; - interrupts = ; - reg = <0 0x17c25000 0 0x1000>; - status = "disabled"; - }; - - frame@17c27000 { - frame-number = <3>; - interrupts = ; - reg = <0 0x17c27000 0 0x1000>; - status = "disabled"; - }; - - frame@17c29000 { - frame-number = <4>; - interrupts = ; - reg = <0 0x17c29000 0 0x1000>; - status = "disabled"; - }; - - frame@17c2b000 { - frame-number = <5>; - interrupts = ; - reg = <0 0x17c2b000 0 0x1000>; - status = "disabled"; - }; - - frame@17c2d000 { - frame-number = <6>; - interrupts = ; - reg = <0 0x17c2d000 0 0x1000>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@18200000 { - compatible = "qcom,rpmh-rsc"; - reg = <0 0x18200000 0 0x10000>, - <0 0x18210000 0 0x10000>, - <0 0x18220000 0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , - , - , - ; - - rpmhcc: clock-controller { - compatible = "qcom,sc7180-rpmh-clk"; - clocks = <&xo_board>; - clock-names = "xo"; - #clock-cells = <1>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sc7180-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_svs_l2: opp6 { - opp-level = <224>; - }; - - rpmhpd_opp_nom: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp8 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp10 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp11 { - opp-level = ; - }; - }; - }; - - apps_bcm_voter: bcm_voter { - compatible = "qcom,bcm-voter"; - }; - }; - - osm_l3: interconnect@18321000 { - compatible = "qcom,sc7180-osm-l3"; - reg = <0 0x18321000 0 0x1400>; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #interconnect-cells = <1>; - }; - - cpufreq_hw: cpufreq@18323000 { - compatible = "qcom,cpufreq-hw"; - reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; - reg-names = "freq-domain0", "freq-domain1"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; - - wifi: wifi@18800000 { - compatible = "qcom,wcn3990-wifi"; - reg = <0 0x18800000 0 0x800000>; - reg-names = "membase"; - iommus = <&apps_smmu 0xc0 0x1>; - interrupts = - , - , - , - , - , - , - , - , - , - , - , - ; - memory-region = <&wlan_mem>; - qcom,msa-fixed-perm; - status = "disabled"; - }; - - lpasscc: clock-controller@62d00000 { - compatible = "qcom,sc7180-lpasscorecc"; - reg = <0 0x62d00000 0 0x50000>, - <0 0x62780000 0 0x30000>; - reg-names = "lpass_core_cc", "lpass_audio_cc"; - clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "bi_tcxo"; - power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; - #clock-cells = <1>; - #power-domain-cells = <1>; - }; - - lpass_hm: clock-controller@63000000 { - compatible = "qcom,sc7180-lpasshm"; - reg = <0 0x63000000 0 0x28>; - clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "bi_tcxo"; - #clock-cells = <1>; - #power-domain-cells = <1>; - }; - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens0 1>; - sustainable-power = <768>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens0 2>; - sustainable-power = <768>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens0 3>; - sustainable-power = <768>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens0 4>; - sustainable-power = <768>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens0 5>; - sustainable-power = <768>; - - trips { - cpu4_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens0 6>; - sustainable-power = <768>; - - trips { - cpu5_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens0 9>; - sustainable-power = <1202>; - - trips { - cpu6_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_alert0>; - cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_alert1>; - cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens0 10>; - sustainable-power = <1202>; - - trips { - cpu7_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_alert0>; - cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_alert1>; - cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu8-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens0 11>; - sustainable-power = <1202>; - - trips { - cpu8_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu8_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu8_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu8_alert0>; - cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu8_alert1>; - cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu9-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens0 12>; - sustainable-power = <1202>; - - trips { - cpu9_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu9_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu9_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu9_alert0>; - cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu9_alert1>; - cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - aoss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens0 0>; - - trips { - aoss0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - aoss0_crit: aoss0_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens0 7>; - - trips { - cpuss0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cpuss0_crit: cluster0_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens0 8>; - - trips { - cpuss1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cpuss1_crit: cluster0_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - gpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens0 13>; - - trips { - gpuss0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - gpuss0_crit: gpuss0_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - gpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens0 14>; - - trips { - gpuss1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - gpuss1_crit: gpuss1_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - aoss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens1 0>; - - trips { - aoss1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - aoss1_crit: aoss1_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cwlan-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens1 1>; - - trips { - cwlan_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - cwlan_crit: cwlan_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - audio-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens1 2>; - - trips { - audio_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - audio_crit: audio_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - ddr-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens1 3>; - - trips { - ddr_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - ddr_crit: ddr_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - q6-hvx-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens1 4>; - - trips { - q6_hvx_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - q6_hvx_crit: q6_hvx_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - camera-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens1 5>; - - trips { - camera_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - camera_crit: camera_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - mdm-core-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens1 6>; - - trips { - mdm_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - mdm_crit: mdm_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - mdm-dsp-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens1 7>; - - trips { - mdm_dsp_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - mdm_dsp_crit: mdm_dsp_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - npu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens1 8>; - - trips { - npu_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - npu_crit: npu_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = <&tsens1 9>; - - trips { - video_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - video_crit: video_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts deleted file mode 100644 index 46a7f2b26..000000000 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, Martin Botka - */ - -/dts-v1/; - -#include "sdm630-sony-xperia-ganges.dtsi" - -/ { - model = "Sony Xperia 10"; - compatible = "sony,kirin-row", "qcom,sdm630"; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges.dtsi deleted file mode 100644 index cf2e8b5d6..000000000 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges.dtsi +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, Martin Botka - */ - -/dts-v1/; - -/* Ganges is very similar to Nile, but - * there are some differences that will need - * to be addresed when more peripherals are - * enabled upstream. Hence the separate DTSI. - */ -#include "sdm630-sony-xperia-nile.dtsi" - -/ { - chosen { - framebuffer@9d400000 { - reg = <0 0x9d400000 0 (2520 * 1080 * 4)>; - height = <2520>; - }; - }; - - /* Yes, this is intentional. - * Ganges devices only use gpio-keys for - * Volume Down, but currently there's an - * issue with it that has to be resolved. - * Until then, let's not make the kernel panic - */ - /delete-node/ gpio-keys; - - soc { - - i2c@c175000 { - status = "okay"; - - /* Novatek touchscreen */ - }; - }; - -}; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-discovery.dts b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-discovery.dts deleted file mode 100644 index 8fca0b69f..000000000 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-discovery.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, Konrad Dybcio - */ - -/dts-v1/; - -#include "sdm630-sony-xperia-nile.dtsi" - -/ { - model = "Sony Xperia XA2 Ultra"; - compatible = "sony,discovery-row", "qcom,sdm630"; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-pioneer.dts b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-pioneer.dts deleted file mode 100644 index 90dcd4eba..000000000 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-pioneer.dts +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, Konrad Dybcio - */ - -/dts-v1/; - -#include "sdm630-sony-xperia-nile.dtsi" - -/ { - model = "Sony Xperia XA2"; - compatible = "sony,pioneer-row", "qcom,sdm630"; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-voyager.dts b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-voyager.dts deleted file mode 100644 index fae5f1bb6..000000000 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-voyager.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, Konrad Dybcio - */ - -/dts-v1/; - -#include "sdm630-sony-xperia-nile.dtsi" - -/ { - model = "Sony Xperia XA2 Plus"; - compatible = "sony,voyager-row", "qcom,sdm630"; - - chosen { - framebuffer@9d400000 { - reg = <0 0x9d400000 0 (2160 * 1080 * 4)>; - height = <2160>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi deleted file mode 100644 index 9ba359c84..000000000 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ /dev/null @@ -1,136 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, Konrad Dybcio - */ - -/dts-v1/; - -#include "sdm630.dtsi" -#include "pm660.dtsi" -#include "pm660l.dtsi" -#include -#include -#include - -/ { - /* required for bootloader to select correct board */ - qcom,msm-id = <318 0>; - qcom,board-id = <8 1>; - qcom,pmic-id = <0x1001b 0x101011a 0x00 0x00 0x1001b 0x201011a 0x00 0x00>; - - /* This part enables graphical output via bootloader-enabled display */ - chosen { - bootargs = "earlycon=tty0 console=tty0"; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - stdout-path = "framebuffer0"; - - framebuffer0: framebuffer@9d400000 { - compatible = "simple-framebuffer"; - reg = <0 0x9d400000 0 (1920 * 1080 * 4)>; - width = <1080>; - height = <1920>; - stride = <(1080 * 4)>; - format = "a8r8g8b8"; - status= "okay"; - }; - }; - - gpio_keys { - status = "okay"; - compatible = "gpio-keys"; - input-name = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - - camera_focus { - label = "Camera Focus"; - gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - debounce-interval = <15>; - }; - - camera_snapshot { - label = "Camera Snapshot"; - gpios = <&tlmm 113 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - debounce-interval = <15>; - }; - - vol_down { - label = "Volume Down"; - gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - gpio-key,wakeup; - debounce-interval = <15>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ramoops@ffc00000 { - compatible = "ramoops"; - reg = <0x0 0xffc00000 0x0 0x100000>; - record-size = <0x10000>; - console-size = <0x60000>; - ftrace-size = <0x10000>; - pmsg-size = <0x20000>; - ecc-size = <16>; - status = "okay"; - }; - - debug_region@ffb00000 { - reg = <0x00 0xffb00000 0x00 0x100000>; - no-map; - }; - - removed_region@85800000 { - reg = <0x00 0x85800000 0x00 0x3700000>; - no-map; - }; - }; - - soc { - sdhci@c0c4000 { - status = "okay"; - - mmc-ddr-1_8v; - /* SoMC Nile platform's eMMC doesn't support HS200 mode */ - mmc-hs400-1_8v; - }; - - i2c@c175000 { - status = "okay"; - - /* Synaptics touchscreen */ - }; - - i2c@c176000 { - status = "okay"; - - /* SMB1351 charger */ - }; - - serial@c1af000 { - status = "okay"; - }; - - /* I2C3, 4, 5, 7 and 8 are disabled on this board. */ - - i2c@c1b6000 { - status = "okay"; - - /* NXP NFC */ - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi deleted file mode 100644 index f87054575..000000000 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ /dev/null @@ -1,1243 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, Konrad Dybcio - */ - -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "xo_board"; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; - clock-output-names = "sleep_clk"; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x100>; - enable-method = "psci"; - cpu-idle-states = <&PERF_CPU_SLEEP_0 - &PERF_CPU_SLEEP_1 - &PERF_CLUSTER_SLEEP_0 - &PERF_CLUSTER_SLEEP_1 - &PERF_CLUSTER_SLEEP_2>; - capacity-dmips-mhz = <1126>; - #cooling-cells = <2>; - next-level-cache = <&L2_1>; - L2_1: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - CPU1: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x101>; - enable-method = "psci"; - cpu-idle-states = <&PERF_CPU_SLEEP_0 - &PERF_CPU_SLEEP_1 - &PERF_CLUSTER_SLEEP_0 - &PERF_CLUSTER_SLEEP_1 - &PERF_CLUSTER_SLEEP_2>; - capacity-dmips-mhz = <1126>; - #cooling-cells = <2>; - next-level-cache = <&L2_1>; - }; - - CPU2: cpu@102 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x102>; - enable-method = "psci"; - cpu-idle-states = <&PERF_CPU_SLEEP_0 - &PERF_CPU_SLEEP_1 - &PERF_CLUSTER_SLEEP_0 - &PERF_CLUSTER_SLEEP_1 - &PERF_CLUSTER_SLEEP_2>; - capacity-dmips-mhz = <1126>; - #cooling-cells = <2>; - next-level-cache = <&L2_1>; - }; - - CPU3: cpu@103 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x103>; - enable-method = "psci"; - cpu-idle-states = <&PERF_CPU_SLEEP_0 - &PERF_CPU_SLEEP_1 - &PERF_CLUSTER_SLEEP_0 - &PERF_CLUSTER_SLEEP_1 - &PERF_CLUSTER_SLEEP_2>; - capacity-dmips-mhz = <1126>; - #cooling-cells = <2>; - next-level-cache = <&L2_1>; - }; - - CPU4: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - cpu-idle-states = <&PWR_CPU_SLEEP_0 - &PWR_CPU_SLEEP_1 - &PWR_CLUSTER_SLEEP_0 - &PWR_CLUSTER_SLEEP_1 - &PWR_CLUSTER_SLEEP_2>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - next-level-cache = <&L2_0>; - L2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - CPU5: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - cpu-idle-states = <&PWR_CPU_SLEEP_0 - &PWR_CPU_SLEEP_1 - &PWR_CLUSTER_SLEEP_0 - &PWR_CLUSTER_SLEEP_1 - &PWR_CLUSTER_SLEEP_2>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - next-level-cache = <&L2_0>; - }; - - CPU6: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - cpu-idle-states = <&PWR_CPU_SLEEP_0 - &PWR_CPU_SLEEP_1 - &PWR_CLUSTER_SLEEP_0 - &PWR_CLUSTER_SLEEP_1 - &PWR_CLUSTER_SLEEP_2>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - next-level-cache = <&L2_0>; - }; - - CPU7: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - cpu-idle-states = <&PWR_CPU_SLEEP_0 - &PWR_CPU_SLEEP_1 - &PWR_CLUSTER_SLEEP_0 - &PWR_CLUSTER_SLEEP_1 - &PWR_CLUSTER_SLEEP_2>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - next-level-cache = <&L2_0>; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU4>; - }; - - core1 { - cpu = <&CPU5>; - }; - - core2 { - cpu = <&CPU6>; - }; - - core3 { - cpu = <&CPU7>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - PWR_CPU_SLEEP_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "pwr-retention"; - arm,psci-suspend-param = <0x40000002>; - entry-latency-us = <338>; - exit-latency-us = <423>; - min-residency-us = <200>; - }; - - PWR_CPU_SLEEP_1: cpu-sleep-0-1 { - compatible = "arm,idle-state"; - idle-state-name = "pwr-power-collapse"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <515>; - exit-latency-us = <1821>; - min-residency-us = <1000>; - local-timer-stop; - }; - - PERF_CPU_SLEEP_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "perf-retention"; - arm,psci-suspend-param = <0x40000002>; - entry-latency-us = <154>; - exit-latency-us = <87>; - min-residency-us = <200>; - }; - - PERF_CPU_SLEEP_1: cpu-sleep-1-1 { - compatible = "arm,idle-state"; - idle-state-name = "perf-power-collapse"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <262>; - exit-latency-us = <301>; - min-residency-us = <1000>; - local-timer-stop; - }; - - PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "pwr-cluster-dynamic-retention"; - arm,psci-suspend-param = <0x400000F2>; - entry-latency-us = <284>; - exit-latency-us = <384>; - min-residency-us = <9987>; - local-timer-stop; - }; - - PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 { - compatible = "arm,idle-state"; - idle-state-name = "pwr-cluster-retention"; - arm,psci-suspend-param = <0x400000F3>; - entry-latency-us = <338>; - exit-latency-us = <423>; - min-residency-us = <9987>; - local-timer-stop; - }; - - PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 { - compatible = "arm,idle-state"; - idle-state-name = "pwr-cluster-retention"; - arm,psci-suspend-param = <0x400000F4>; - entry-latency-us = <515>; - exit-latency-us = <1821>; - min-residency-us = <9987>; - local-timer-stop; - }; - - PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "perf-cluster-dynamic-retention"; - arm,psci-suspend-param = <0x400000F2>; - entry-latency-us = <272>; - exit-latency-us = <329>; - min-residency-us = <9987>; - local-timer-stop; - }; - - PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 { - compatible = "arm,idle-state"; - idle-state-name = "perf-cluster-retention"; - arm,psci-suspend-param = <0x400000F3>; - entry-latency-us = <332>; - exit-latency-us = <368>; - min-residency-us = <9987>; - local-timer-stop; - }; - - PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 { - compatible = "arm,idle-state"; - idle-state-name = "perf-cluster-retention"; - arm,psci-suspend-param = <0x400000F4>; - entry-latency-us = <545>; - exit-latency-us = <1609>; - min-residency-us = <9987>; - local-timer-stop; - }; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-msm8998", "qcom,scm"; - }; - }; - - memory { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - wlan_msa_guard: wlan-msa-guard@85600000 { - reg = <0x0 0x85600000 0x0 0x100000>; - no-map; - }; - - wlan_msa_mem: wlan-msa-mem@85700000 { - reg = <0x0 0x85700000 0x0 0x100000>; - no-map; - }; - - qhee_code: qhee-code@85800000 { - reg = <0x0 0x85800000 0x0 0x600000>; - no-map; - }; - - rmtfs_mem: memory@85e00000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x85e00000 0x0 0x200000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - smem_region: smem-mem@86000000 { - reg = <0 0x86000000 0 0x200000>; - no-map; - }; - - tz_mem: memory@86200000 { - reg = <0x0 0x86200000 0x0 0x3300000>; - no-map; - }; - - mpss_region: mpss@8ac00000 { - reg = <0x0 0x8ac00000 0x0 0x7e00000>; - no-map; - }; - - adsp_region: adsp@92a00000 { - reg = <0x0 0x92a00000 0x0 0x1e00000>; - no-map; - }; - - mba_region: mba@94800000 { - reg = <0x0 0x94800000 0x0 0x200000>; - no-map; - }; - - buffer_mem: tzbuffer@94a00000 { - reg = <0x0 0x94a00000 0x0 0x100000>; - no-map; - }; - - venus_region: venus@9f800000 { - reg = <0x0 0x9f800000 0x0 0x800000>; - no-map; - }; - - adsp_mem: adsp-region@f6000000 { - reg = <0x0 0xf6000000 0x0 0x800000>; - no-map; - }; - - qseecom_mem: qseecom-region@f6800000 { - reg = <0x0 0xf6800000 0x0 0x1400000>; - no-map; - }; - - zap_shader_region: gpu@fed00000 { - compatible = "shared-dma-pool"; - reg = <0x0 0xfed00000 0x0 0xa00000>; - no-map; - }; - }; - - rpm-glink { - compatible = "qcom,glink-rpm"; - - interrupts = ; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-sdm660"; - qcom,glink-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; - #clock-cells = <1>; - }; - }; - }; - - smem: smem { - compatible = "qcom,smem"; - memory-region = <&smem_region>; - hwlocks = <&tcsr_mutex 3>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sdm630"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0x00100000 0x94000>; - - clock-names = "xo", "sleep_clk"; - clocks = <&xo_board>, - <&sleep_clk>; - }; - - rpm_msg_ram: memory@778000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0x00778000 0x7000>; - }; - - qfprom: qfprom@780000 { - compatible = "qcom,qfprom"; - reg = <0x00780000 0x621c>; - #address-cells = <1>; - #size-cells = <1>; - }; - - rng: rng@793000 { - compatible = "qcom,prng-ee"; - reg = <0x00793000 0x1000>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; - - restart@10ac000 { - compatible = "qcom,pshold"; - reg = <0x010ac000 0x4>; - }; - - anoc2_smmu: iommu@16c0000 { - compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; - reg = <0x016c0000 0x40000>; - #iommu-cells = <1>; - - #global-interrupts = <2>; - interrupts = - , - , - - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - - status = "disabled"; - }; - - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0x01f40000 0x20000>; - }; - - tlmm: pinctrl@3100000 { - compatible = "qcom,sdm630-pinctrl"; - reg = <0x03100000 0x400000>, - <0x03500000 0x400000>, - <0x03900000 0x400000>; - reg-names = "south", "center", "north"; - interrupts = ; - gpio-controller; - gpio-ranges = <&tlmm 0 0 114>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - - blsp1_uart1_default: blsp1-uart1-default { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - drive-strength = <2>; - bias-disable; - }; - - blsp1_uart1_sleep: blsp1-uart1-sleep { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - drive-strength = <2>; - bias-disable; - }; - - blsp1_uart2_default: blsp1-uart2-default { - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-disable; - }; - - blsp2_uart1_default: blsp2-uart1-active { - tx-rts { - pins = "gpio16", "gpio19"; - function = "blsp_uart5"; - drive-strength = <2>; - bias-disable; - }; - - rx { - /* - * Avoid garbage data while BT module - * is powered off or not driving signal - */ - pins = "gpio17"; - function = "blsp_uart5"; - drive-strength = <2>; - bias-pull-up; - }; - - cts { - /* Match the pull of the BT module */ - pins = "gpio18"; - function = "blsp_uart5"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - blsp2_uart1_sleep: blsp2-uart1-sleep { - tx { - pins = "gpio16"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - - rx-cts-rts { - pins = "gpio17", "gpio18", "gpio19"; - function = "gpio"; - drive-strength = <2>; - bias-no-pull; - }; - }; - - i2c1_default: i2c1-default { - pins = "gpio2", "gpio3"; - drive-strength = <2>; - bias-disable; - }; - - i2c1_sleep: i2c1-sleep { - pins = "gpio2", "gpio3"; - drive-strength = <2>; - bias-pull-up; - }; - - i2c2_default: i2c2-default { - pins = "gpio6", "gpio7"; - drive-strength = <2>; - bias-disable; - }; - - i2c2_sleep: i2c2-sleep { - pins = "gpio6", "gpio7"; - drive-strength = <2>; - bias-pull-up; - }; - - i2c3_default: i2c3-default { - pins = "gpio10", "gpio11"; - drive-strength = <2>; - bias-disable; - }; - - i2c3_sleep: i2c3-sleep { - pins = "gpio10", "gpio11"; - drive-strength = <2>; - bias-pull-up; - }; - - i2c4_default: i2c4-default { - pins = "gpio14", "gpio15"; - drive-strength = <2>; - bias-disable; - }; - - i2c4_sleep: i2c4-sleep { - pins = "gpio14", "gpio15"; - drive-strength = <2>; - bias-pull-up; - }; - - i2c5_default: i2c5-default { - pins = "gpio18", "gpio19"; - drive-strength = <2>; - bias-disable; - }; - - i2c5_sleep: i2c5-sleep { - pins = "gpio18", "gpio19"; - drive-strength = <2>; - bias-pull-up; - }; - - i2c6_default: i2c6-default { - pins = "gpio22", "gpio23"; - drive-strength = <2>; - bias-disable; - }; - - i2c6_sleep: i2c6-sleep { - pins = "gpio22", "gpio23"; - drive-strength = <2>; - bias-pull-up; - }; - - i2c7_default: i2c7-default { - pins = "gpio26", "gpio27"; - drive-strength = <2>; - bias-disable; - }; - - i2c7_sleep: i2c7-sleep { - pins = "gpio26", "gpio27"; - drive-strength = <2>; - bias-pull-up; - }; - - i2c8_default: i2c8-default { - pins = "gpio30", "gpio31"; - drive-strength = <2>; - bias-disable; - }; - - i2c8_sleep: i2c8-sleep { - pins = "gpio30", "gpio31"; - drive-strength = <2>; - bias-pull-up; - }; - - sdc1_state_on: sdc1-on { - clk { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <16>; - }; - - cmd { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - data { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <10>; - }; - - rclk { - pins = "sdc1_rclk"; - bias-pull-down; - }; - }; - - sdc1_state_off: sdc1-off { - clk { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <2>; - }; - - cmd { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - data { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <2>; - }; - - rclk { - pins = "sdc1_rclk"; - bias-pull-down; - }; - }; - - sdc2_state_on: sdc2-on { - clk { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <16>; - }; - - cmd { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - data { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <10>; - }; - - sd-cd { - pins = "gpio54"; - bias-pull-up; - drive-strength = <2>; - }; - }; - - sdc2_state_off: sdc2-off { - clk { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <2>; - }; - - cmd { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - data { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <2>; - }; - - sd-cd { - pins = "gpio54"; - bias-disable; - drive-strength = <2>; - }; - }; - }; - - kgsl_smmu: iommu@5040000 { - compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; - reg = <0x05040000 0x10000>; - #iommu-cells = <1>; - - #global-interrupts = <2>; - interrupts = - , - , - - , - , - , - , - , - , - , - ; - - status = "disabled"; - }; - - lpass_smmu: iommu@5100000 { - compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; - reg = <0x05100000 0x40000>; - #iommu-cells = <1>; - - #global-interrupts = <2>; - interrupts = - , - , - - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - - status = "disabled"; - }; - - spmi_bus: spmi@800f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0800f000 0x1000>, - <0x08400000 0x1000000>, - <0x09400000 0x1000000>, - <0x0a400000 0x220000>, - <0x0800a000 0x3000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - sdhc_1: sdhci@c0c4000 { - compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x0c0c4000 0x1000>, - <0x0c0c5000 0x1000>; - reg-names = "hc", "cqhci"; - - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_state_on>; - pinctrl-1 = <&sdc1_state_off>; - - bus-width = <8>; - non-removable; - - status = "disabled"; - }; - - blsp1_dma: dma@c144000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x0c144000 0x1f000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - qcom,controlled-remotely; - num-channels = <18>; - qcom,num-ees = <4>; - }; - - blsp1_uart1: serial@c16f000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x0c16f000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart1_default>; - pinctrl-1 = <&blsp1_uart1_sleep>; - status = "disabled"; - }; - - blsp1_uart2: serial@c170000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x0c170000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&blsp1_uart2_default>; - status = "disabled"; - }; - - blsp_i2c1: i2c@c175000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c175000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c1_default>; - pinctrl-1 = <&i2c1_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c2: i2c@c176000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c176000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_default>; - pinctrl-1 = <&i2c2_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c3: i2c@c177000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c177000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c3_default>; - pinctrl-1 = <&i2c3_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c4: i2c@c178000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c178000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c4_default>; - pinctrl-1 = <&i2c4_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_dma: dma@c184000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x0c184000 0x1f000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - qcom,controlled-remotely; - num-channels = <18>; - qcom,num-ees = <4>; - }; - - blsp2_uart1: serial@c1af000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x0c1af000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart1_default>; - pinctrl-1 = <&blsp2_uart1_sleep>; - status = "disabled"; - }; - - blsp_i2c5: i2c@c1b5000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c1b5000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c5_default>; - pinctrl-1 = <&i2c5_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c6: i2c@c1b6000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c1b6000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c6_default>; - pinctrl-1 = <&i2c6_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c7: i2c@c1b7000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c1b7000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c7_default>; - pinctrl-1 = <&i2c7_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c8: i2c@c1b8000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x0c1b8000 0x600>; - interrupts = ; - - clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - clock-frequency = <400000>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c8_default>; - pinctrl-1 = <&i2c8_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmss_smmu: iommu@cd00000 { - compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; - reg = <0x0cd00000 0x40000>; - #iommu-cells = <1>; - - #global-interrupts = <2>; - interrupts = - , - , - - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - - status = "disabled"; - }; - - apcs_glb: mailbox@17911000 { - compatible = "qcom,sdm660-apcs-hmss-global"; - reg = <0x17911000 0x1000>; - - #mbox-cells = <1>; - }; - - timer@17920000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x17920000 0x1000>; - clock-frequency = <19200000>; - - frame@17921000 { - frame-number = <0>; - interrupts = <0 8 0x4>, - <0 7 0x4>; - reg = <0x17921000 0x1000>, - <0x17922000 0x1000>; - }; - - frame@17923000 { - frame-number = <1>; - interrupts = <0 9 0x4>; - reg = <0x17923000 0x1000>; - status = "disabled"; - }; - - frame@17924000 { - frame-number = <2>; - interrupts = <0 10 0x4>; - reg = <0x17924000 0x1000>; - status = "disabled"; - }; - - frame@17925000 { - frame-number = <3>; - interrupts = <0 11 0x4>; - reg = <0x17925000 0x1000>; - status = "disabled"; - }; - - frame@17926000 { - frame-number = <4>; - interrupts = <0 12 0x4>; - reg = <0x17926000 0x1000>; - status = "disabled"; - }; - - frame@17927000 { - frame-number = <5>; - interrupts = <0 13 0x4>; - reg = <0x17927000 0x1000>; - status = "disabled"; - }; - - frame@17928000 { - frame-number = <6>; - interrupts = <0 14 0x4>; - reg = <0x17928000 0x1000>; - status = "disabled"; - }; - }; - - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - reg = <0x17a00000 0x10000>, /* GICD */ - <0x17b00000 0x100000>; /* GICR * 8 */ - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x20000>; - interrupts = ; - }; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; - diff --git a/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts b/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts deleted file mode 100644 index 7c0830e6a..000000000 --- a/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, Martin Botka - */ - -/dts-v1/; - -/* Mermaid uses sdm636, but it's different ever so slightly - * that we can ignore it for the time being. Sony also commonizes - * the Ganges platform as a whole in downstream kernels. - */ -#include "sdm630-sony-xperia-ganges.dtsi" - -/ { - model = "Sony Xperia 10 Plus"; - compatible = "sony,mermaid-row", "qcom,sdm636"; - - qcom,msm-id = <345 0>; - qcom,pmic-id = <0x1001b 0x101011a 0x00 0x00 0x1001b 0x201011a 0x00 0x00 0x1001b 0x102001a 0x00 0x00>; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts deleted file mode 100644 index 76533e8b2..000000000 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ /dev/null @@ -1,46 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2020, Alexey Minnekhanov - */ - -/dts-v1/; - -#include "sdm660.dtsi" - -/ { - model = "Xiaomi Redmi Note 7"; - compatible = "xiaomi,lavender", "qcom,sdm660"; - - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ramoops@a0000000 { - compatible = "ramoops"; - reg = <0x0 0xa0000000 0x0 0x400000>; - console-size = <0x20000>; - record-size = <0x20000>; - ftrace-size = <0x0>; - pmsg-size = <0x20000>; - }; - }; -}; - -&blsp1_uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart_console_active>; -}; - -&tlmm { - gpio-reserved-ranges = <8 4>; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi deleted file mode 100644 index 4abbdd03d..000000000 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ /dev/null @@ -1,372 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2018, Craig Tatlor. - * Copyright (c) 2020, Alexey Minnekhanov - */ - -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "xo_board"; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; - clock-output-names = "sleep_clk"; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo260"; - reg = <0x0 0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&L2_1>; - L2_1: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - L1_I_100: l1-icache { - compatible = "cache"; - }; - L1_D_100: l1-dcache { - compatible = "cache"; - }; - }; - - CPU1: cpu@101 { - device_type = "cpu"; - compatible = "qcom,kryo260"; - reg = <0x0 0x101>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&L2_1>; - L1_I_101: l1-icache { - compatible = "cache"; - }; - L1_D_101: l1-dcache { - compatible = "cache"; - }; - }; - - CPU2: cpu@102 { - device_type = "cpu"; - compatible = "qcom,kryo260"; - reg = <0x0 0x102>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&L2_1>; - L1_I_102: l1-icache { - compatible = "cache"; - }; - L1_D_102: l1-dcache { - compatible = "cache"; - }; - }; - - CPU3: cpu@103 { - device_type = "cpu"; - compatible = "qcom,kryo260"; - reg = <0x0 0x103>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - next-level-cache = <&L2_1>; - L1_I_103: l1-icache { - compatible = "cache"; - }; - L1_D_103: l1-dcache { - compatible = "cache"; - }; - }; - - CPU4: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo260"; - reg = <0x0 0x0>; - enable-method = "psci"; - capacity-dmips-mhz = <640>; - next-level-cache = <&L2_0>; - L2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - L1_I_0: l1-icache { - compatible = "cache"; - }; - L1_D_0: l1-dcache { - compatible = "cache"; - }; - }; - - CPU5: cpu@1 { - device_type = "cpu"; - compatible = "qcom,kryo260"; - reg = <0x0 0x1>; - enable-method = "psci"; - capacity-dmips-mhz = <640>; - next-level-cache = <&L2_0>; - L1_I_1: l1-icache { - compatible = "cache"; - }; - L1_D_1: l1-dcache { - compatible = "cache"; - }; - }; - - CPU6: cpu@2 { - device_type = "cpu"; - compatible = "qcom,kryo260"; - reg = <0x0 0x2>; - enable-method = "psci"; - capacity-dmips-mhz = <640>; - next-level-cache = <&L2_0>; - L1_I_2: l1-icache { - compatible = "cache"; - }; - L1_D_2: l1-dcache { - compatible = "cache"; - }; - }; - - CPU7: cpu@3 { - device_type = "cpu"; - compatible = "qcom,kryo260"; - reg = <0x0 0x3>; - enable-method = "psci"; - capacity-dmips-mhz = <640>; - next-level-cache = <&L2_0>; - L1_I_3: l1-icache { - compatible = "cache"; - }; - L1_D_3: l1-dcache { - compatible = "cache"; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU4>; - }; - - core1 { - cpu = <&CPU5>; - }; - - core2 { - cpu = <&CPU6>; - }; - - core3 { - cpu = <&CPU7>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - }; - }; - }; - - firmware { - scm { - compatible = "qcom,scm"; - }; - }; - - memory { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sdm660"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0x00100000 0x94000>; - }; - - tlmm: pinctrl@3100000 { - compatible = "qcom,sdm660-pinctrl"; - reg = <0x03100000 0x400000>, - <0x03500000 0x400000>, - <0x03900000 0x400000>; - reg-names = "south", "center", "north"; - interrupts = ; - gpio-controller; - gpio-ranges = <&tlmm 0 0 114>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - - uart_console_active: uart_console_active { - pinmux { - pins = "gpio4", "gpio5"; - function = "blsp_uart2"; - }; - - pinconf { - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - - spmi_bus: spmi@800f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0800f000 0x1000>, - <0x08400000 0x1000000>, - <0x09400000 0x1000000>, - <0x0a400000 0x220000>, - <0x0800a000 0x3000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - blsp1_uart2: serial@c170000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x0c170000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - timer@17920000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x17920000 0x1000>; - - frame@17921000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x17921000 0x1000>, - <0x17922000 0x1000>; - }; - - frame@17923000 { - frame-number = <1>; - interrupts = ; - reg = <0x17923000 0x1000>; - status = "disabled"; - }; - - frame@17924000 { - frame-number = <2>; - interrupts = ; - reg = <0x17924000 0x1000>; - status = "disabled"; - }; - - frame@17925000 { - frame-number = <3>; - interrupts = ; - reg = <0x17925000 0x1000>; - status = "disabled"; - }; - - frame@17926000 { - frame-number = <4>; - interrupts = ; - reg = <0x17926000 0x1000>; - status = "disabled"; - }; - - frame@17927000 { - frame-number = <5>; - interrupts = ; - reg = <0x17927000 0x1000>; - status = "disabled"; - }; - - frame@17928000 { - frame-number = <6>; - interrupts = ; - reg = <0x17928000 0x1000>; - status = "disabled"; - }; - }; - - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - reg = <0x17a00000 0x10000>, - <0x17b00000 0x100000>; - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x20000>; - interrupts = ; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts b/arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts deleted file mode 100644 index bd7c25bb8..000000000 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts +++ /dev/null @@ -1,238 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Cheza board device tree source - * - * Copyright 2018 Google LLC. - */ - -/dts-v1/; - -#include "sdm845-cheza.dtsi" - -/ { - model = "Google Cheza (rev1)"; - compatible = "google,cheza-rev1", "qcom,sdm845"; - - /* - * FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children - */ - - /* - * NOTE: Technically pp3500_a is not the exact same signal as - * pp3500_a_vbob (there's a load switch between them and the EC can - * control pp3500_a via "en_pp3300_a"), but from the AP's point of - * view they are the same. - */ - pp3500_a: - pp3500_a_vbob: pp3500-a-vbob-regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_bob"; - - /* - * Comes on automatically when pp5000_ldo comes on, which - * comes on automatically when ppvar_sys comes on - */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - - vin-supply = <&ppvar_sys>; - }; - - pp3300_dx_edp: pp3300-dx-edp-regulator { - /* Yes, it's really 3.5 despite the name of the signal */ - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - - vin-supply = <&pp3500_a>; - }; -}; - -/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */ - -/* - * L19 and L28 technically go to 3.3V, but most boards have old AOP firmware - * that limits them to 3.0, and trying to run at 3.3V with that old firmware - * prevents the system from booting. - */ -&src_pp3000_l19a { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; -}; - -&src_pp3300_l22a { - /delete-property/regulator-boot-on; - /delete-property/regulator-always-on; -}; - -&src_pp3300_l28a { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; -}; - -&src_vreg_bob { - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - vin-supply = <&pp3500_a_vbob>; -}; - -/* - * NON-REGULATOR OVERRIDES - * (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label - */ - -/* PINCTRL - board-specific pinctrl */ - -&tlmm { - gpio-line-names = "AP_SPI_FP_MISO", - "AP_SPI_FP_MOSI", - "AP_SPI_FP_CLK", - "AP_SPI_FP_CS_L", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "", - "FP_RST_L", - "FCAM_EN", - "", - "EDP_BRIJ_IRQ", - "EC_IN_RW_ODL", - "", - "RCAM_MCLK", - "FCAM_MCLK", - "", - "RCAM_EN", - "CCI0_SDA", - "CCI0_SCL", - "CCI1_SDA", - "CCI1_SCL", - "FCAM_RST_L", - "", - "PEN_RST_L", - "PEN_IRQ_L", - "", - "RCAM_VSYNC", - "ESIM_MISO", - "ESIM_MOSI", - "ESIM_CLK", - "ESIM_CS_L", - "AP_PEN_1V8_SDA", - "AP_PEN_1V8_SCL", - "AP_TS_I2C_SDA", - "AP_TS_I2C_SCL", - "RCAM_RST_L", - "", - "AP_EDP_BKLTEN", - "AP_BRD_ID1", - "BOOT_CONFIG_4", - "AMP_IRQ_L", - "EDP_BRIJ_I2C_SDA", - "EDP_BRIJ_I2C_SCL", - "EN_PP3300_DX_EDP", - "SD_CD_ODL", - "BT_UART_RTS", - "BT_UART_CTS", - "BT_UART_RXD", - "BT_UART_TXD", - "AMP_I2C_SDA", - "AMP_I2C_SCL", - "AP_BRD_ID3", - "", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "FORCED_USB_BOOT", - "AMP_BCLK", - "AMP_LRCLK", - "AMP_DOUT", - "AMP_DIN", - "AP_BRD_ID2", - "PEN_PDCT_L", - "HP_MCLK", - "HP_BCLK", - "HP_LRCLK", - "HP_DOUT", - "HP_DIN", - "", - "", - "", - "", - "BT_SLIMBUS_DATA", - "BT_SLIMBUS_CLK", - "AMP_RESET_L", - "", - "FCAM_VSYNC", - "", - "AP_SKU_ID1", - "EC_WOV_BCLK", - "EC_WOV_LRCLK", - "EC_WOV_DOUT", - "", - "", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - "AP_H1_SPI_CLK", - "AP_H1_SPI_CS_L", - "", - "AP_SPI_CS0_L", - "AP_SPI_MOSI", - "AP_SPI_MISO", - "", - "", - "AP_SPI_CLK", - "", - "RFFE6_CLK", - "RFFE6_DATA", - "BOOT_CONFIG_1", - "BOOT_CONFIG_2", - "BOOT_CONFIG_0", - "EDP_BRIJ_EN", - "", - "USB_HS_TX_EN", - "UIM2_DATA", - "UIM2_CLK", - "UIM2_RST", - "UIM2_PRESENT", - "UIM1_DATA", - "UIM1_CLK", - "UIM1_RST", - "", - "AP_SKU_ID2", - "SDM_GRFC_8", - "SDM_GRFC_9", - "AP_RST_REQ", - "HP_IRQ", - "TS_RESET_L", - "PEN_EJECT_ODL", - "HUB_RST_L", - "FP_TO_AP_IRQ", - "AP_EC_INT_L", - "", - "", - "TS_INT_L", - "AP_SUSPEND_L", - "SDM_GRFC_3", - "", - "H1_AP_INT_ODL", - "QLINK_REQ", - "QLINK_EN", - "SDM_GRFC_2", - "BOOT_CONFIG_3", - "WMSS_RESET_L", - "SDM_GRFC_0", - "SDM_GRFC_1", - "RFFE3_DATA", - "RFFE3_CLK", - "RFFE4_DATA", - "RFFE4_CLK", - "RFFE5_DATA", - "RFFE5_CLK", - "GNSS_EN", - "WCI2_LTE_COEX_RXD", - "WCI2_LTE_COEX_TXD", - "AP_RAM_ID1", - "AP_RAM_ID2", - "RFFE1_DATA", - "RFFE1_CLK"; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts b/arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts deleted file mode 100644 index 2b7230594..000000000 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts +++ /dev/null @@ -1,238 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Cheza board device tree source - * - * Copyright 2018 Google LLC. - */ - -/dts-v1/; - -#include "sdm845-cheza.dtsi" - -/ { - model = "Google Cheza (rev2)"; - compatible = "google,cheza-rev2", "qcom,sdm845"; - - /* - * FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children - */ - - /* - * NOTE: Technically pp3500_a is not the exact same signal as - * pp3500_a_vbob (there's a load switch between them and the EC can - * control pp3500_a via "en_pp3300_a"), but from the AP's point of - * view they are the same. - */ - pp3500_a: - pp3500_a_vbob: pp3500-a-vbob-regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_bob"; - - /* - * Comes on automatically when pp5000_ldo comes on, which - * comes on automatically when ppvar_sys comes on - */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - - vin-supply = <&ppvar_sys>; - }; - - pp3300_dx_edp: pp3300-dx-edp-regulator { - /* Yes, it's really 3.5 despite the name of the signal */ - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - - vin-supply = <&pp3500_a>; - }; -}; - -/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */ - -/* - * L19 and L28 technically go to 3.3V, but most boards have old AOP firmware - * that limits them to 3.0, and trying to run at 3.3V with that old firmware - * prevents the system from booting. - */ -&src_pp3000_l19a { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; -}; - -&src_pp3300_l22a { - /delete-property/regulator-boot-on; - /delete-property/regulator-always-on; -}; - -&src_pp3300_l28a { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; -}; - -&src_vreg_bob { - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - vin-supply = <&pp3500_a_vbob>; -}; - -/* - * NON-REGULATOR OVERRIDES - * (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label - */ - -/* PINCTRL - board-specific pinctrl */ - -&tlmm { - gpio-line-names = "AP_SPI_FP_MISO", - "AP_SPI_FP_MOSI", - "AP_SPI_FP_CLK", - "AP_SPI_FP_CS_L", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "BRIJ_SUSPEND", - "FP_RST_L", - "FCAM_EN", - "", - "EDP_BRIJ_IRQ", - "EC_IN_RW_ODL", - "", - "RCAM_MCLK", - "FCAM_MCLK", - "", - "RCAM_EN", - "CCI0_SDA", - "CCI0_SCL", - "CCI1_SDA", - "CCI1_SCL", - "FCAM_RST_L", - "FPMCU_BOOT0", - "PEN_RST_L", - "PEN_IRQ_L", - "FPMCU_SEL_OD", - "RCAM_VSYNC", - "ESIM_MISO", - "ESIM_MOSI", - "ESIM_CLK", - "ESIM_CS_L", - "AP_PEN_1V8_SDA", - "AP_PEN_1V8_SCL", - "AP_TS_I2C_SDA", - "AP_TS_I2C_SCL", - "RCAM_RST_L", - "", - "AP_EDP_BKLTEN", - "AP_BRD_ID1", - "BOOT_CONFIG_4", - "AMP_IRQ_L", - "EDP_BRIJ_I2C_SDA", - "EDP_BRIJ_I2C_SCL", - "EN_PP3300_DX_EDP", - "SD_CD_ODL", - "BT_UART_RTS", - "BT_UART_CTS", - "BT_UART_RXD", - "BT_UART_TXD", - "AMP_I2C_SDA", - "AMP_I2C_SCL", - "AP_BRD_ID3", - "", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "FORCED_USB_BOOT", - "AMP_BCLK", - "AMP_LRCLK", - "AMP_DOUT", - "AMP_DIN", - "AP_BRD_ID2", - "PEN_PDCT_L", - "HP_MCLK", - "HP_BCLK", - "HP_LRCLK", - "HP_DOUT", - "HP_DIN", - "", - "", - "", - "", - "BT_SLIMBUS_DATA", - "BT_SLIMBUS_CLK", - "AMP_RESET_L", - "", - "FCAM_VSYNC", - "", - "AP_SKU_ID1", - "EC_WOV_BCLK", - "EC_WOV_LRCLK", - "EC_WOV_DOUT", - "", - "", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - "AP_H1_SPI_CLK", - "AP_H1_SPI_CS_L", - "", - "AP_SPI_CS0_L", - "AP_SPI_MOSI", - "AP_SPI_MISO", - "", - "", - "AP_SPI_CLK", - "", - "RFFE6_CLK", - "RFFE6_DATA", - "BOOT_CONFIG_1", - "BOOT_CONFIG_2", - "BOOT_CONFIG_0", - "EDP_BRIJ_EN", - "", - "USB_HS_TX_EN", - "UIM2_DATA", - "UIM2_CLK", - "UIM2_RST", - "UIM2_PRESENT", - "UIM1_DATA", - "UIM1_CLK", - "UIM1_RST", - "", - "AP_SKU_ID2", - "SDM_GRFC_8", - "SDM_GRFC_9", - "AP_RST_REQ", - "HP_IRQ", - "TS_RESET_L", - "PEN_EJECT_ODL", - "HUB_RST_L", - "FP_TO_AP_IRQ", - "AP_EC_INT_L", - "", - "", - "TS_INT_L", - "AP_SUSPEND_L", - "SDM_GRFC_3", - "", - "H1_AP_INT_ODL", - "QLINK_REQ", - "QLINK_EN", - "SDM_GRFC_2", - "BOOT_CONFIG_3", - "WMSS_RESET_L", - "SDM_GRFC_0", - "SDM_GRFC_1", - "RFFE3_DATA", - "RFFE3_CLK", - "RFFE4_DATA", - "RFFE4_CLK", - "RFFE5_DATA", - "RFFE5_CLK", - "GNSS_EN", - "WCI2_LTE_COEX_RXD", - "WCI2_LTE_COEX_TXD", - "AP_RAM_ID1", - "AP_RAM_ID2", - "RFFE1_DATA", - "RFFE1_CLK"; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts b/arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts deleted file mode 100644 index 1ba67be08..000000000 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts +++ /dev/null @@ -1,174 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Cheza board device tree source - * - * Copyright 2018 Google LLC. - */ - -/dts-v1/; - -#include "sdm845-cheza.dtsi" - -/ { - model = "Google Cheza (rev3+)"; - compatible = "google,cheza", "qcom,sdm845"; -}; - -/* PINCTRL - board-specific pinctrl */ - -&tlmm { - gpio-line-names = "AP_SPI_FP_MISO", - "AP_SPI_FP_MOSI", - "AP_SPI_FP_CLK", - "AP_SPI_FP_CS_L", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "BRIJ_SUSPEND", - "FP_RST_L", - "FCAM_EN", - "", - "EDP_BRIJ_IRQ", - "EC_IN_RW_ODL", - "", - "RCAM_MCLK", - "FCAM_MCLK", - "", - "RCAM_EN", - "CCI0_SDA", - "CCI0_SCL", - "CCI1_SDA", - "CCI1_SCL", - "FCAM_RST_L", - "FPMCU_BOOT0", - "PEN_RST_L", - "PEN_IRQ_L", - "FPMCU_SEL_OD", - "RCAM_VSYNC", - "ESIM_MISO", - "ESIM_MOSI", - "ESIM_CLK", - "ESIM_CS_L", - "AP_PEN_1V8_SDA", - "AP_PEN_1V8_SCL", - "AP_TS_I2C_SDA", - "AP_TS_I2C_SCL", - "RCAM_RST_L", - "", - "AP_EDP_BKLTEN", - "AP_BRD_ID0", - "BOOT_CONFIG_4", - "AMP_IRQ_L", - "EDP_BRIJ_I2C_SDA", - "EDP_BRIJ_I2C_SCL", - "EN_PP3300_DX_EDP", - "SD_CD_ODL", - "BT_UART_RTS", - "BT_UART_CTS", - "BT_UART_RXD", - "BT_UART_TXD", - "AMP_I2C_SDA", - "AMP_I2C_SCL", - "AP_BRD_ID2", - "", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "FORCED_USB_BOOT", - "AMP_BCLK", - "AMP_LRCLK", - "AMP_DOUT", - "AMP_DIN", - "AP_BRD_ID1", - "PEN_PDCT_L", - "HP_MCLK", - "HP_BCLK", - "HP_LRCLK", - "HP_DOUT", - "HP_DIN", - "", - "", - "", - "", - "BT_SLIMBUS_DATA", - "BT_SLIMBUS_CLK", - "AMP_RESET_L", - "", - "FCAM_VSYNC", - "", - "AP_SKU_ID0", - "EC_WOV_BCLK", - "EC_WOV_LRCLK", - "EC_WOV_DOUT", - "", - "", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - "AP_H1_SPI_CLK", - "AP_H1_SPI_CS_L", - "", - "AP_SPI_CS0_L", - "AP_SPI_MOSI", - "AP_SPI_MISO", - "", - "", - "AP_SPI_CLK", - "", - "RFFE6_CLK", - "RFFE6_DATA", - "BOOT_CONFIG_1", - "BOOT_CONFIG_2", - "BOOT_CONFIG_0", - "EDP_BRIJ_EN", - "", - "USB_HS_TX_EN", - "UIM2_DATA", - "UIM2_CLK", - "UIM2_RST", - "UIM2_PRESENT", - "UIM1_DATA", - "UIM1_CLK", - "UIM1_RST", - "", - "AP_SKU_ID1", - "SDM_GRFC_8", - "SDM_GRFC_9", - "AP_RST_REQ", - "HP_IRQ", - "TS_RESET_L", - "PEN_EJECT_ODL", - "HUB_RST_L", - "FP_TO_AP_IRQ", - "AP_EC_INT_L", - "", - "", - "TS_INT_L", - "AP_SUSPEND_L", - "SDM_GRFC_3", - /* - * AP_FLASH_WP_L is crossystem ABI. Rev3 schematics - * call it BIOS_FLASH_WP_R_L. - */ - "AP_FLASH_WP_L", - "H1_AP_INT_ODL", - "QLINK_REQ", - "QLINK_EN", - "SDM_GRFC_2", - "BOOT_CONFIG_3", - "WMSS_RESET_L", - "SDM_GRFC_0", - "SDM_GRFC_1", - "RFFE3_DATA", - "RFFE3_CLK", - "RFFE4_DATA", - "RFFE4_CLK", - "RFFE5_DATA", - "RFFE5_CLK", - "GNSS_EN", - "WCI2_LTE_COEX_RXD", - "WCI2_LTE_COEX_TXD", - "AP_RAM_ID0", - "AP_RAM_ID1", - "RFFE1_DATA", - "RFFE1_CLK"; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi deleted file mode 100644 index 64fc1bfd6..000000000 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ /dev/null @@ -1,1316 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Cheza device tree source (common between revisions) - * - * Copyright 2018 Google LLC. - */ - -#include -#include -#include -#include "sdm845.dtsi" - -/* PMICs depend on spmi_bus label and so must come after SoC */ -#include "pm8005.dtsi" -#include "pm8998.dtsi" - -/ { - aliases { - bluetooth0 = &bluetooth; - hsuart0 = &uart6; - serial0 = &uart9; - wifi0 = &wifi; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&cros_ec_pwm 0>; - enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; - power-supply = <&ppvar_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&ap_edp_bklten>; - }; - - /* FIXED REGULATORS - parents above children */ - - /* This is the top level supply and variable voltage */ - ppvar_sys: ppvar-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "ppvar_sys"; - regulator-always-on; - regulator-boot-on; - }; - - /* This divides ppvar_sys by 2, so voltage is variable */ - src_vph_pwr: src-vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "src_vph_pwr"; - - /* EC turns on with switchcap_on_l; always on for AP */ - regulator-always-on; - regulator-boot-on; - - vin-supply = <&ppvar_sys>; - }; - - pp5000_a: pp5000-a-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp5000_a"; - - /* EC turns on with en_pp5000_a; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - vin-supply = <&ppvar_sys>; - }; - - src_vreg_bob: src-vreg-bob-regulator { - compatible = "regulator-fixed"; - regulator-name = "src_vreg_bob"; - - /* EC turns on with vbob_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - - vin-supply = <&ppvar_sys>; - }; - - pp3300_dx_edp: pp3300-dx-edp-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_dx_edp"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&en_pp3300_dx_edp>; - }; - - /* - * Apparently RPMh does not provide support for PM8998 S4 because it - * is always-on; model it as a fixed regulator. - */ - src_pp1800_s4a: pm8998-smps4 { - compatible = "regulator-fixed"; - regulator-name = "src_pp1800_s4a"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - - vin-supply = <&src_vph_pwr>; - }; - - /* BOARD-SPECIFIC TOP LEVEL NODES */ - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pen_eject_odl>; - - pen-insert { - label = "Pen Insert"; - /* Insert = low, eject = high */ - gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - wakeup-source; - }; - }; - - panel: panel { - compatible ="innolux,p120zdg-bf1"; - power-supply = <&pp3300_dx_edp>; - backlight = <&backlight>; - no-hpd; - - ports { - panel_in: port { - panel_in_edp: endpoint { - remote-endpoint = <&sn65dsi86_out>; - }; - }; - }; - }; -}; - -/* - * Reserved memory changes - * - * Putting this all together (out of order with the rest of the file) to keep - * all modifications to the memory map (from sdm845.dtsi) in one place. - */ - -/* - * Our mpss_region is 8MB bigger than the default one and that conflicts - * with venus_mem and cdsp_mem. - * - * For venus_mem we'll delete and re-create at a different address. - * - * cdsp_mem isn't used on cheza right now so we won't bother re-creating it; but - * that also means we need to delete cdsp_pas. - */ -/delete-node/ &venus_mem; -/delete-node/ &cdsp_mem; -/delete-node/ &cdsp_pas; -/delete-node/ &gpu_mem; - -/* Increase the size from 120 MB to 128 MB */ -&mpss_region { - reg = <0 0x8e000000 0 0x8000000>; -}; - -/* Increase the size from 2MB to 8MB */ -&rmtfs_mem { - reg = <0 0x88f00000 0 0x800000>; -}; - -/ { - reserved-memory { - venus_mem: memory@96000000 { - reg = <0 0x96000000 0 0x500000>; - no-map; - }; - }; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - - /* - * In theory chip supports up to 104 MHz and controller up - * to 80 MHz, but above 25 MHz wasn't reliable so we'll use - * that for now. b:117440651 - */ - spi-max-frequency = <25000000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; - }; -}; - - -&apps_rsc { - pm8998-rpmh-regulators { - compatible = "qcom,pm8998-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-s1-supply = <&src_vph_pwr>; - vdd-s2-supply = <&src_vph_pwr>; - vdd-s3-supply = <&src_vph_pwr>; - vdd-s4-supply = <&src_vph_pwr>; - vdd-s5-supply = <&src_vph_pwr>; - vdd-s6-supply = <&src_vph_pwr>; - vdd-s7-supply = <&src_vph_pwr>; - vdd-s8-supply = <&src_vph_pwr>; - vdd-s9-supply = <&src_vph_pwr>; - vdd-s10-supply = <&src_vph_pwr>; - vdd-s11-supply = <&src_vph_pwr>; - vdd-s12-supply = <&src_vph_pwr>; - vdd-s13-supply = <&src_vph_pwr>; - vdd-l1-l27-supply = <&src_pp1025_s7a>; - vdd-l2-l8-l17-supply = <&src_pp1350_s3a>; - vdd-l3-l11-supply = <&src_pp1025_s7a>; - vdd-l4-l5-supply = <&src_pp1025_s7a>; - vdd-l6-supply = <&src_vph_pwr>; - vdd-l7-l12-l14-l15-supply = <&src_pp2040_s5a>; - vdd-l9-supply = <&src_pp2040_s5a>; - vdd-l10-l23-l25-supply = <&src_vreg_bob>; - vdd-l13-l19-l21-supply = <&src_vreg_bob>; - vdd-l16-l28-supply = <&src_vreg_bob>; - vdd-l18-l22-supply = <&src_vreg_bob>; - vdd-l20-l24-supply = <&src_vreg_bob>; - vdd-l26-supply = <&src_pp1350_s3a>; - vin-lvs-1-2-supply = <&src_pp1800_s4a>; - - src_pp1125_s2a: smps2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - src_pp1350_s3a: smps3 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - - src_pp2040_s5a: smps5 { - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2040000>; - }; - - src_pp1025_s7a: smps7 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1028000>; - }; - - vdd_qusb_hs0: - vdda_hp_pcie_core: - vdda_mipi_csi0_0p9: - vdda_mipi_csi1_0p9: - vdda_mipi_csi2_0p9: - vdda_mipi_dsi0_pll: - vdda_mipi_dsi1_pll: - vdda_qlink_lv: - vdda_qlink_lv_ck: - vdda_qrefs_0p875: - vdda_pcie_core: - vdda_pll_cc_ebi01: - vdda_pll_cc_ebi23: - vdda_sp_sensor: - vdda_ufs1_core: - vdda_ufs2_core: - vdda_usb1_ss_core: - vdda_usb2_ss_core: - src_pp875_l1a: ldo1 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - - vddpx_10: - src_pp1200_l2a: ldo2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - - /* TODO: why??? */ - regulator-always-on; - }; - - pp1000_l3a_sdr845: ldo3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-initial-mode = ; - }; - - vdd_wcss_cx: - vdd_wcss_mx: - vdda_wcss_pll: - src_pp800_l5a: ldo5 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vddpx_13: - src_pp1800_l6a: ldo6 { - regulator-min-microvolt = <1856000>; - regulator-max-microvolt = <1856000>; - regulator-initial-mode = ; - }; - - pp1800_l7a_wcn3990: ldo7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - src_pp1200_l8a: ldo8 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1248000>; - regulator-initial-mode = ; - }; - - pp1800_dx_pen: - src_pp1800_l9a: ldo9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - src_pp1800_l10a: ldo10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - pp1000_l11a_sdr845: ldo11 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1048000>; - regulator-initial-mode = ; - }; - - vdd_qfprom: - vdd_qfprom_sp: - vdda_apc1_cs_1p8: - vdda_gfx_cs_1p8: - vdda_qrefs_1p8: - vdda_qusb_hs0_1p8: - vddpx_11: - src_pp1800_l12a: ldo12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vddpx_2: - src_pp2950_l13a: ldo13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - src_pp1800_l14a: ldo14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - src_pp1800_l15a: ldo15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - pp2700_l16a: ldo16 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - regulator-initial-mode = ; - }; - - src_pp1300_l17a: ldo17 { - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - pp2700_l18a: ldo18 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - /* - * NOTE: this rail should have been called - * src_pp3300_l19a in the schematic - */ - src_pp3000_l19a: ldo19 { - regulator-min-microvolt = <3304000>; - regulator-max-microvolt = <3304000>; - - regulator-initial-mode = ; - }; - - src_pp2950_l20a: ldo20 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - src_pp2950_l21a: ldo21 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - pp3300_hub: - src_pp3300_l22a: ldo22 { - regulator-min-microvolt = <3304000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - /* - * HACK: Should add a usb hub node and driver - * to turn this on and off at suspend/resume time - */ - regulator-boot-on; - regulator-always-on; - }; - - pp3300_l23a_ch1_wcn3990: ldo23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vdda_qusb_hs0_3p1: - src_pp3075_l24a: ldo24 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3088000>; - regulator-initial-mode = ; - }; - - pp3300_l25a_ch0_wcn3990: ldo25 { - regulator-min-microvolt = <3304000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - }; - - pp1200_hub: - vdda_hp_pcie_1p2: - vdda_hv_ebi0: - vdda_hv_ebi1: - vdda_hv_ebi2: - vdda_hv_ebi3: - vdda_mipi_csi_1p25: - vdda_mipi_dsi0_1p2: - vdda_mipi_dsi1_1p2: - vdda_pcie_1p2: - vdda_ufs1_1p2: - vdda_ufs2_1p2: - vdda_usb1_ss_1p2: - vdda_usb2_ss_1p2: - src_pp1200_l26a: ldo26 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - pp3300_dx_pen: - src_pp3300_l28a: ldo28 { - regulator-min-microvolt = <3304000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - }; - - src_pp1800_lvs1: lvs1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - src_pp1800_lvs2: lvs2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - - pm8005-rpmh-regulators { - compatible = "qcom,pm8005-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-s1-supply = <&src_vph_pwr>; - vdd-s2-supply = <&src_vph_pwr>; - vdd-s3-supply = <&src_vph_pwr>; - vdd-s4-supply = <&src_vph_pwr>; - - src_pp600_s3c: smps3 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <600000>; - }; - }; -}; - -&dsi0 { - status = "okay"; - vdda-supply = <&vdda_mipi_dsi0_1p2>; - - ports { - port@1 { - endpoint { - remote-endpoint = <&sn65dsi86_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&dsi0_phy { - status = "okay"; - vdds-supply = <&vdda_mipi_dsi0_pll>; -}; - -edp_brij_i2c: &i2c3 { - status = "okay"; - clock-frequency = <400000>; - - sn65dsi86_bridge: bridge@2d { - compatible = "ti,sn65dsi86"; - reg = <0x2d>; - pinctrl-names = "default"; - pinctrl-0 = <&edp_brij_en &edp_brij_irq>; - - interrupt-parent = <&tlmm>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - - enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; - - vpll-supply = <&src_pp1800_s4a>; - vccio-supply = <&src_pp1800_s4a>; - vcca-supply = <&src_pp1200_l2a>; - vcc-supply = <&src_pp1200_l2a>; - - clocks = <&rpmhcc RPMH_LN_BB_CLK2>; - clock-names = "refclk"; - - no-hpd; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - sn65dsi86_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - sn65dsi86_out: endpoint { - remote-endpoint = <&panel_in_edp>; - }; - }; - }; - }; -}; - -ap_pen_1v8: &i2c11 { - status = "okay"; - clock-frequency = <400000>; - - digitizer@9 { - compatible = "wacom,w9013", "hid-over-i2c"; - reg = <0x9>; - pinctrl-names = "default"; - pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>; - - vdd-supply = <&pp3300_dx_pen>; - vddl-supply = <&pp1800_dx_pen>; - post-power-on-delay-ms = <100>; - - interrupt-parent = <&tlmm>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - - hid-descr-addr = <0x1>; - }; -}; - -amp_i2c: &i2c12 { - status = "okay"; - clock-frequency = <400000>; -}; - -ap_ts_i2c: &i2c14 { - status = "okay"; - clock-frequency = <400000>; - - touchscreen@10 { - compatible = "elan,ekth3500"; - reg = <0x10>; - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_l &ts_reset_l>; - - interrupt-parent = <&tlmm>; - interrupts = <125 IRQ_TYPE_LEVEL_LOW>; - - vcc33-supply = <&src_pp3300_l28a>; - - reset-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>; - }; -}; - -&ipa { - status = "okay"; - modem-init; -}; - -&lpasscc { - status = "okay"; -}; - -&mdss { - status = "okay"; -}; - -&mdss_mdp { - status = "okay"; -}; - -&mss_pil { - iommus = <&apps_smmu 0x781 0x0>, - <&apps_smmu 0x724 0x3>; -}; - -&pm8998_pwrkey { - status = "disabled"; -}; - -&qupv3_id_0 { - status = "okay"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&sdhc_2 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_cd_odl>; - - vmmc-supply = <&src_pp2950_l21a>; - vqmmc-supply = <&vddpx_2>; - - cd-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; -}; - -&spi0 { - status = "okay"; -}; - -&spi5 { - status = "okay"; - - tpm@0 { - compatible = "google,cr50"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&h1_ap_int_odl>; - spi-max-frequency = <800000>; - interrupt-parent = <&tlmm>; - interrupts = <129 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&spi10 { - status = "okay"; - - cros_ec: ec@0 { - compatible = "google,cros-ec-spi"; - reg = <0>; - interrupt-parent = <&tlmm>; - interrupts = <122 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_ap_int_l>; - spi-max-frequency = <3000000>; - - cros_ec_pwm: ec-pwm { - compatible = "google,cros-ec-pwm"; - #pwm-cells = <1>; - }; - - i2c_tunnel: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - google,remote-bus = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - pdupdate { - compatible = "google,cros-ec-pd-update"; - }; - }; -}; - -#include -#include - -&uart6 { - status = "okay"; - - bluetooth: wcn3990-bt { - compatible = "qcom,wcn3990-bt"; - vddio-supply = <&src_pp1800_s4a>; - vddxo-supply = <&pp1800_l7a_wcn3990>; - vddrf-supply = <&src_pp1300_l17a>; - vddch0-supply = <&pp3300_l25a_ch0_wcn3990>; - max-speed = <3200000>; - }; -}; - -&uart9 { - status = "okay"; -}; - -&ufs_mem_hc { - status = "okay"; - - reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; - - vcc-supply = <&src_pp2950_l20a>; - vcc-max-microamp = <600000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vdda_ufs1_core>; - vdda-pll-supply = <&vdda_ufs1_1p2>; -}; - -&usb_1 { - status = "okay"; - - /* We'll use this as USB 2.0 only */ - qcom,select-utmi-as-pipe-clk; -}; - -&usb_1_dwc3 { - /* - * The hardware design intends this port to be hooked up in peripheral - * mode, so we'll hardcode it here. Some details: - * - SDM845 expects only a single Type C connector so it has only one - * native Type C port but cheza has two Type C connectors. - * - The only source of DP is the single native Type C port. - * - On cheza we want to be able to hook DP up to _either_ of the - * two Type C connectors and want to be able to achieve 4 lanes of DP. - * - When you configure a Type C port for 4 lanes of DP you lose USB3. - * - In order to make everything work, the native Type C port is always - * configured as 4-lanes DP so it's always available. - * - The extra USB3 port on SDM845 goes to a USB 3 hub which is then - * sent to the two Type C connectors. - * - The extra USB2 lines from the native Type C port are always - * setup as "peripheral" so that we can mux them over to one connector - * or the other if someone needs the connector configured as a gadget - * (but they only get USB2 speeds). - * - * All the hardware muxes would allow us to hook things up in different - * ways to some potential benefit for static configurations (you could - * achieve extra USB2 bandwidth by using two different ports for the - * two connectors or possibly even get USB3 peripheral mode), but in - * each case you end up forcing to disconnect/reconnect an in-use - * USB session in some cases depending on what you hotplug into the - * other connector. Thus hardcoding this as peripheral makes sense. - */ - dr_mode = "peripheral"; - - /* - * We always need the high speed pins as 4-lanes DP in case someone - * hotplugs a DP peripheral. Thus limit this port to a max of high - * speed. - */ - maximum-speed = "high-speed"; - - /* - * We don't need the usb3-phy since we run in highspeed mode always, so - * re-define these properties removing the superspeed USB PHY reference. - */ - phys = <&usb_1_hsphy>; - phy-names = "usb2-phy"; -}; - -&usb_1_hsphy { - status = "okay"; - - vdd-supply = <&vdda_usb1_ss_core>; - vdda-pll-supply = <&vdda_qusb_hs0_1p8>; - vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = ; - qcom,preemphasis-level = ; - qcom,preemphasis-width = ; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - /* We have this hooked up to a hub and we always use in host mode */ - dr_mode = "host"; -}; - -&usb_2_hsphy { - status = "okay"; - - vdd-supply = <&vdda_usb2_ss_core>; - vdda-pll-supply = <&vdda_qusb_hs0_1p8>; - vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = ; -}; - -&usb_2_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vdda_usb2_ss_1p2>; - vdda-pll-supply = <&vdda_usb2_ss_core>; -}; - -&wifi { - status = "okay"; - - vdd-0.8-cx-mx-supply = <&src_pp800_l5a >; - vdd-1.8-xo-supply = <&pp1800_l7a_wcn3990>; - vdd-1.3-rfa-supply = <&src_pp1300_l17a>; - vdd-3.3-ch0-supply = <&pp3300_l25a_ch0_wcn3990>; -}; - -/* PINCTRL - additions to nodes defined in sdm845.dtsi */ - -&qspi_cs0 { - pinconf { - pins = "gpio90"; - bias-disable; - }; -}; - -&qspi_clk { - pinconf { - pins = "gpio95"; - bias-disable; - }; -}; - -&qspi_data01 { - pinconf { - pins = "gpio91", "gpio92"; - - /* High-Z when no transfers; nice to park the lines */ - bias-pull-up; - }; -}; - -&qup_i2c3_default { - pinconf { - pins = "gpio41", "gpio42"; - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; - }; -}; - -&qup_i2c11_default { - pinconf { - pins = "gpio31", "gpio32"; - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; - }; -}; - -&qup_i2c12_default { - pinconf { - pins = "gpio49", "gpio50"; - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; - }; -}; - -&qup_i2c14_default { - pinconf { - pins = "gpio33", "gpio34"; - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; - }; -}; - -&qup_spi0_default { - pinconf { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - drive-strength = <2>; - bias-disable; - }; -}; - -&qup_spi5_default { - pinconf { - pins = "gpio85", "gpio86", "gpio87", "gpio88"; - drive-strength = <2>; - bias-disable; - }; -}; - -&qup_spi10_default { - pinconf { - pins = "gpio53", "gpio54", "gpio55", "gpio56"; - drive-strength = <2>; - bias-disable; - }; -}; - -&qup_uart6_default { - /* Change pinmux to all 4 pins since CTS and RTS are connected */ - pinmux { - pins = "gpio45", "gpio46", - "gpio47", "gpio48"; - }; - - pinconf-cts { - /* - * Configure a pull-down on 45 (CTS) to match the pull of - * the Bluetooth module. - */ - pins = "gpio45"; - bias-pull-down; - }; - - pinconf-rts-tx { - /* We'll drive 46 (RTS) and 47 (TX), so no pull */ - pins = "gpio46", "gpio47"; - drive-strength = <2>; - bias-disable; - }; - - pinconf-rx { - /* - * Configure a pull-up on 48 (RX). This is needed to avoid - * garbage data when the TX pin of the Bluetooth module is - * in tri-state (module powered off or not driving the - * signal yet). - */ - pins = "gpio48"; - bias-pull-up; - }; -}; - -&qup_uart9_default { - pinconf-tx { - pins = "gpio4"; - drive-strength = <2>; - bias-disable; - }; - - pinconf-rx { - pins = "gpio5"; - drive-strength = <2>; - bias-pull-up; - }; -}; - -/* PINCTRL - board-specific pinctrl */ -&pm8005_gpio { - gpio-line-names = "", - "", - "SLB", - ""; -}; - -&pm8998_adc { - adc-chan@4d { - reg = ; - label = "sdm_temp"; - }; - - adc-chan@4e { - reg = ; - label = "quiet_temp"; - }; - - adc-chan@4f { - reg = ; - label = "lte_temp_1"; - }; - - adc-chan@50 { - reg = ; - label = "lte_temp_2"; - }; - - adc-chan@51 { - reg = ; - label = "charger_temp"; - }; -}; - -&pm8998_gpio { - gpio-line-names = "", - "", - "SW_CTRL", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "CFG_OPT1", - "WCSS_PWR_REQ", - "", - "CFG_OPT2", - "SLB"; -}; - -&tlmm { - /* - * pinctrl settings for pins that have no real owners. - */ - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&bios_flash_wp_r_l>, - <&ap_suspend_l_deassert>; - - pinctrl-1 = <&bios_flash_wp_r_l>, - <&ap_suspend_l_assert>; - - /* - * Hogs prevent usermode from changing the value. A GPIO can be both - * here and in the pinctrl section. - */ - ap-suspend-l-hog { - gpio-hog; - gpios = <126 GPIO_ACTIVE_LOW>; - output-low; - }; - - ap_edp_bklten: ap-edp-bklten { - pinmux { - pins = "gpio37"; - function = "gpio"; - }; - - pinconf { - pins = "gpio37"; - drive-strength = <2>; - bias-disable; - }; - }; - - bios_flash_wp_r_l: bios-flash-wp-r-l { - pinmux { - pins = "gpio128"; - function = "gpio"; - input-enable; - }; - - pinconf { - pins = "gpio128"; - bias-disable; - }; - }; - - ec_ap_int_l: ec-ap-int-l { - pinmux { - pins = "gpio122"; - function = "gpio"; - input-enable; - }; - - pinconf { - pins = "gpio122"; - bias-pull-up; - }; - }; - - edp_brij_en: edp-brij-en { - pinmux { - pins = "gpio102"; - function = "gpio"; - }; - - pinconf { - pins = "gpio102"; - drive-strength = <2>; - bias-disable; - }; - }; - - edp_brij_irq: edp-brij-irq { - pinmux { - pins = "gpio10"; - function = "gpio"; - }; - - pinconf { - pins = "gpio10"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - en_pp3300_dx_edp: en-pp3300-dx-edp { - pinmux { - pins = "gpio43"; - function = "gpio"; - }; - - pinconf { - pins = "gpio43"; - drive-strength = <2>; - bias-disable; - }; - }; - - h1_ap_int_odl: h1-ap-int-odl { - pinmux { - pins = "gpio129"; - function = "gpio"; - input-enable; - }; - - pinconf { - pins = "gpio129"; - bias-pull-up; - }; - }; - - pen_eject_odl: pen-eject-odl { - pinmux { - pins = "gpio119"; - function = "gpio"; - bias-pull-up; - }; - }; - - pen_irq_l: pen-irq-l { - pinmux { - pins = "gpio24"; - function = "gpio"; - }; - - pinconf { - pins = "gpio24"; - - /* Has external pullup */ - bias-disable; - }; - }; - - pen_pdct_l: pen-pdct-l { - pinmux { - pins = "gpio63"; - function = "gpio"; - }; - - pinconf { - pins = "gpio63"; - - /* Has external pullup */ - bias-disable; - }; - }; - - pen_rst_l: pen-rst-l { - pinmux { - pins = "gpio23"; - function = "gpio"; - }; - - pinconf { - pins = "gpio23"; - bias-disable; - drive-strength = <2>; - - /* - * The pen driver doesn't currently support - * driving this reset line. By specifying - * output-high here we're relying on the fact - * that this pin has a default pulldown at boot - * (which makes sure the pen was in reset if it - * was powered) and then we set it high here to - * take it out of reset. Better would be if the - * pen driver could control this and we could - * remove "output-high" here. - */ - output-high; - }; - }; - - sdc2_clk: sdc2-clk { - pinconf { - pins = "sdc2_clk"; - bias-disable; - - /* - * It seems that mmc_test reports errors if drive - * strength is not 16. - */ - drive-strength = <16>; - }; - }; - - sdc2_cmd: sdc2-cmd { - pinconf { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <16>; - }; - }; - - sdc2_data: sdc2-data { - pinconf { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <16>; - }; - }; - - sd_cd_odl: sd-cd-odl { - pinmux { - pins = "gpio44"; - function = "gpio"; - }; - - pinconf { - pins = "gpio44"; - bias-pull-up; - }; - }; - - ts_int_l: ts-int-l { - pinmux { - pins = "gpio125"; - function = "gpio"; - }; - - pinconf { - pins = "gpio125"; - bias-pull-up; - }; - }; - - ts_reset_l: ts-reset-l { - pinmux { - pins = "gpio118"; - function = "gpio"; - }; - - pinconf { - pins = "gpio118"; - bias-disable; - drive-strength = <2>; - }; - }; - - ap_suspend_l_assert: ap_suspend_l_assert { - config { - pins = "gpio126"; - function = "gpio"; - bias-no-pull; - drive-strength = <2>; - output-low; - }; - }; - - ap_suspend_l_deassert: ap_suspend_l_deassert { - config { - pins = "gpio126"; - function = "gpio"; - bias-no-pull; - drive-strength = <2>; - output-high; - }; - }; -}; - -&venus { - video-firmware { - iommus = <&apps_smmu 0x10b2 0x0>; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts deleted file mode 100644 index 96d36b38f..000000000 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ /dev/null @@ -1,1195 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019, Linaro Ltd. - */ - -/dts-v1/; - -#include -#include -#include -#include -#include -#include "sdm845.dtsi" -#include "pm8998.dtsi" -#include "pmi8998.dtsi" - -/ { - model = "Thundercomm Dragonboard 845c"; - compatible = "thundercomm,db845c", "qcom,sdm845"; - - aliases { - serial0 = &uart9; - hsuart0 = &uart6; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - dc12v: dc12v-regulator { - compatible = "regulator-fixed"; - regulator-name = "DC12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - gpio_keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&vol_up_pin_a>; - - vol-up { - label = "Volume Up"; - linux,code = ; - gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - - user4 { - label = "green:user4"; - gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "panic-indicator"; - default-state = "off"; - }; - - wlan { - label = "yellow:wlan"; - gpios = <&pm8998_gpio 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - bt { - label = "blue:bt"; - gpios = <&pm8998_gpio 5 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "bluetooth-power"; - default-state = "off"; - }; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <<9611_out>; - }; - }; - }; - - lt9611_1v8: lt9611-vdd18-regulator { - compatible = "regulator-fixed"; - regulator-name = "LT9611_1V8"; - - vin-supply = <&vdc_5v>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - lt9611_3v3: lt9611-3v3 { - compatible = "regulator-fixed"; - regulator-name = "LT9611_3V3"; - - vin-supply = <&vdc_3v3>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - // TODO: make it possible to drive same GPIO from two clients - // gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; - // enable-active-high; - }; - - pcie0_1p05v: pcie-0-1p05v-regulator { - compatible = "regulator-fixed"; - regulator-name = "PCIE0_1.05V"; - - vin-supply = <&vbat>; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - - // TODO: make it possible to drive same GPIO from two clients - // gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>; - // enable-active-high; - }; - - cam0_dvdd_1v2: reg_cam0_dvdd_1v2 { - compatible = "regulator-fixed"; - regulator-name = "CAM0_DVDD_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - enable-active-high; - gpio = <&pm8998_gpio 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cam0_dvdd_1v2_en_default>; - vin-supply = <&vbat>; - }; - - cam0_avdd_2v8: reg_cam0_avdd_2v8 { - compatible = "regulator-fixed"; - regulator-name = "CAM0_AVDD_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - enable-active-high; - gpio = <&pm8998_gpio 10 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cam0_avdd_2v8_en_default>; - vin-supply = <&vbat>; - }; - - /* This regulator is enabled when the VREG_LVS1A_1P8 trace is enabled */ - cam3_avdd_2v8: reg_cam3_avdd_2v8 { - compatible = "regulator-fixed"; - regulator-name = "CAM3_AVDD_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - vin-supply = <&vbat>; - }; - - pcie0_3p3v_dual: vldo-3v3-regulator { - compatible = "regulator-fixed"; - regulator-name = "VLDO_3V3"; - - vin-supply = <&vbat>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pwren_state>; - }; - - v5p0_hdmiout: v5p0-hdmiout-regulator { - compatible = "regulator-fixed"; - regulator-name = "V5P0_HDMIOUT"; - - vin-supply = <&vdc_5v>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <500000>; - - // TODO: make it possible to drive same GPIO from two clients - // gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; - // enable-active-high; - }; - - vbat: vbat-regulator { - compatible = "regulator-fixed"; - regulator-name = "VBAT"; - - vin-supply = <&dc12v>; - regulator-min-microvolt = <4200000>; - regulator-max-microvolt = <4200000>; - regulator-always-on; - }; - - vbat_som: vbat-som-regulator { - compatible = "regulator-fixed"; - regulator-name = "VBAT_SOM"; - - vin-supply = <&dc12v>; - regulator-min-microvolt = <4200000>; - regulator-max-microvolt = <4200000>; - regulator-always-on; - }; - - vdc_3v3: vdc-3v3-regulator { - compatible = "regulator-fixed"; - regulator-name = "VDC_3V3"; - vin-supply = <&dc12v>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdc_5v: vdc-5v-regulator { - compatible = "regulator-fixed"; - regulator-name = "VDC_5V"; - - vin-supply = <&dc12v>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <500000>; - regulator-always-on; - }; - - vreg_s4a_1p8: vreg-s4a-1p8 { - compatible = "regulator-fixed"; - regulator-name = "vreg_s4a_1p8"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - - vin-supply = <&vbat_som>; - }; -}; - -&adsp_pas { - status = "okay"; - - firmware-name = "qcom/sdm845/adsp.mdt"; -}; - -&apps_rsc { - pm8998-rpmh-regulators { - compatible = "qcom,pm8998-rpmh-regulators"; - qcom,pmic-id = "a"; - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-s8-supply = <&vph_pwr>; - vdd-s9-supply = <&vph_pwr>; - vdd-s10-supply = <&vph_pwr>; - vdd-s11-supply = <&vph_pwr>; - vdd-s12-supply = <&vph_pwr>; - vdd-s13-supply = <&vph_pwr>; - vdd-l1-l27-supply = <&vreg_s7a_1p025>; - vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; - vdd-l3-l11-supply = <&vreg_s7a_1p025>; - vdd-l4-l5-supply = <&vreg_s7a_1p025>; - vdd-l6-supply = <&vph_pwr>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; - vdd-l9-supply = <&vreg_bob>; - vdd-l10-l23-l25-supply = <&vreg_bob>; - vdd-l13-l19-l21-supply = <&vreg_bob>; - vdd-l16-l28-supply = <&vreg_bob>; - vdd-l18-l22-supply = <&vreg_bob>; - vdd-l20-l24-supply = <&vreg_bob>; - vdd-l26-supply = <&vreg_s3a_1p35>; - vin-lvs-1-2-supply = <&vreg_s4a_1p8>; - - vreg_s3a_1p35: smps3 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_s5a_2p04: smps5 { - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2040000>; - }; - - vreg_s7a_1p025: smps7 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1028000>; - }; - - vreg_l1a_0p875: ldo1 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - - vreg_l5a_0p8: ldo5 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vreg_l12a_1p8: ldo12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l7a_1p8: ldo7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l13a_2p95: ldo13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l17a_1p3: ldo17 { - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l20a_2p95: ldo20 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2968000>; - regulator-initial-mode = ; - }; - - vreg_l21a_2p95: ldo21 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2968000>; - regulator-initial-mode = ; - }; - - vreg_l24a_3p075: ldo24 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3088000>; - regulator-initial-mode = ; - }; - - vreg_l25a_3p3: ldo25 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vreg_l26a_1p2: ldo26 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_lvs1a_1p8: lvs1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vreg_lvs2a_1p8: lvs2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - - pmi8998-rpmh-regulators { - compatible = "qcom,pmi8998-rpmh-regulators"; - qcom,pmic-id = "b"; - - vdd-bob-supply = <&vph_pwr>; - - vreg_bob: bob { - regulator-min-microvolt = <3312000>; - regulator-max-microvolt = <3600000>; - regulator-initial-mode = ; - regulator-allow-bypass; - }; - }; -}; - -&cdsp_pas { - status = "okay"; - firmware-name = "qcom/sdm845/cdsp.mdt"; -}; - -&dsi0 { - status = "okay"; - vdda-supply = <&vreg_l26a_1p2>; - - ports { - port@1 { - endpoint { - remote-endpoint = <<9611_a>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&dsi0_phy { - status = "okay"; - vdds-supply = <&vreg_l1a_0p875>; -}; - -&gcc { - protected-clocks = , - , - , - , - ; -}; - -&gpu { - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sdm845/a630_zap.mbn"; - }; -}; - -&i2c10 { - status = "okay"; - clock-frequency = <400000>; - - lt9611_codec: hdmi-bridge@3b { - compatible = "lontium,lt9611"; - reg = <0x3b>; - #sound-dai-cells = <1>; - - interrupts-extended = <&tlmm 84 IRQ_TYPE_EDGE_FALLING>; - - reset-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>; - - vdd-supply = <<9611_1v8>; - vcc-supply = <<9611_3v3>; - - pinctrl-names = "default"; - pinctrl-0 = <<9611_irq_pin>, <&dsi_sw_sel>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lt9611_a: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@2 { - reg = <2>; - - lt9611_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&i2c11 { - /* On Low speed expansion */ - label = "LS-I2C1"; - status = "okay"; -}; - -&i2c14 { - /* On Low speed expansion */ - label = "LS-I2C0"; - status = "okay"; -}; - -&mdss { - status = "okay"; -}; - -&mdss_mdp { - status = "okay"; -}; - -&mss_pil { - status = "okay"; - firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn"; -}; - -&pcie0 { - status = "okay"; - perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>; - enable-gpio = <&tlmm 134 GPIO_ACTIVE_HIGH>; - - vddpe-3v3-supply = <&pcie0_3p3v_dual>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_default_state>; -}; - -&pcie0_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l26a_1p2>; -}; - -&pcie1 { - status = "okay"; - perst-gpio = <&tlmm 102 GPIO_ACTIVE_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_default_state>; -}; - -&pcie1_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l26a_1p2>; -}; - -&pm8998_gpio { - gpio-line-names = - "NC", - "NC", - "WLAN_SW_CTRL", - "NC", - "PM_GPIO5_BLUE_BT_LED", - "VOL_UP_N", - "NC", - "ADC_IN1", - "PM_GPIO9_YEL_WIFI_LED", - "CAM0_AVDD_EN", - "NC", - "CAM0_DVDD_EN", - "PM_GPIO13_GREEN_U4_LED", - "DIV_CLK2", - "NC", - "NC", - "NC", - "SMB_STAT", - "NC", - "NC", - "ADC_IN2", - "OPTION1", - "WCSS_PWR_REQ", - "PM845_GPIO24", - "OPTION2", - "PM845_SLB"; - - cam0_dvdd_1v2_en_default: cam0-dvdd-1v2-en { - pins = "gpio12"; - function = "normal"; - - bias-pull-up; - drive-push-pull; - qcom,drive-strength = ; - }; - - cam0_avdd_2v8_en_default: cam0-avdd-2v8-en { - pins = "gpio10"; - function = "normal"; - - bias-pull-up; - drive-push-pull; - qcom,drive-strength = ; - }; - - vol_up_pin_a: vol-up-active { - pins = "gpio6"; - function = "normal"; - input-enable; - bias-pull-up; - qcom,drive-strength = ; - }; -}; - -&pm8998_pon { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; -}; - -/* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */ -&q6afedai { - qi2s@22 { - reg = <22>; - qcom,sd-lines = <0 1 2 3>; - }; -}; - -&q6asmdai { - dai@0 { - reg = <0>; - }; - - dai@1 { - reg = <1>; - }; - - dai@2 { - reg = <2>; - }; - - dai@3 { - reg = <3>; - direction = <2>; - is-compress-dai; - }; -}; - -&qupv3_id_0 { - status = "okay"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&sdhc_2 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; - - vmmc-supply = <&vreg_l21a_2p95>; - vqmmc-supply = <&vreg_l13a_2p95>; - - bus-width = <4>; - cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; -}; - -&sound { - compatible = "qcom,db845c-sndcard"; - pinctrl-0 = <&quat_mi2s_active - &quat_mi2s_sd0_active - &quat_mi2s_sd1_active - &quat_mi2s_sd2_active - &quat_mi2s_sd3_active>; - pinctrl-names = "default"; - model = "DB845c"; - audio-routing = - "RX_BIAS", "MCLK", - "AMIC1", "MIC BIAS1", - "AMIC2", "MIC BIAS2", - "DMIC0", "MIC BIAS1", - "DMIC1", "MIC BIAS1", - "DMIC2", "MIC BIAS3", - "DMIC3", "MIC BIAS3", - "SpkrLeft IN", "SPK1 OUT", - "SpkrRight IN", "SPK2 OUT", - "MM_DL1", "MultiMedia1 Playback", - "MM_DL2", "MultiMedia2 Playback", - "MM_DL4", "MultiMedia4 Playback", - "MultiMedia3 Capture", "MM_UL3"; - - mm1-dai-link { - link-name = "MultiMedia1"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; - }; - }; - - mm2-dai-link { - link-name = "MultiMedia2"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; - }; - }; - - mm3-dai-link { - link-name = "MultiMedia3"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; - }; - }; - - mm4-dai-link { - link-name = "MultiMedia4"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA4>; - }; - }; - - hdmi-dai-link { - link-name = "HDMI Playback"; - cpu { - sound-dai = <&q6afedai QUATERNARY_MI2S_RX>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <<9611_codec 0>; - }; - }; - - slim-dai-link { - link-name = "SLIM Playback"; - cpu { - sound-dai = <&q6afedai SLIMBUS_0_RX>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; - }; - }; - - slimcap-dai-link { - link-name = "SLIM Capture"; - cpu { - sound-dai = <&q6afedai SLIMBUS_0_TX>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&wcd9340 1>; - }; - }; -}; - -&spi2 { - /* On Low speed expansion */ - label = "LS-SPI0"; - status = "okay"; -}; - -&tlmm { - cam0_default: cam0_default { - rst { - pins = "gpio9"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - }; - - mclk0 { - pins = "gpio13"; - function = "cam_mclk"; - - drive-strength = <16>; - bias-disable; - }; - }; - - cam3_default: cam3_default { - rst { - function = "gpio"; - pins = "gpio21"; - - drive-strength = <16>; - bias-disable; - }; - - mclk3 { - function = "cam_mclk"; - pins = "gpio16"; - - drive-strength = <16>; - bias-disable; - }; - }; - - dsi_sw_sel: dsi-sw-sel { - pins = "gpio120"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - output-high; - }; - - lt9611_irq_pin: lt9611-irq { - pins = "gpio84"; - function = "gpio"; - bias-disable; - }; - - pcie0_default_state: pcie0-default { - clkreq { - pins = "gpio36"; - function = "pci_e0"; - bias-pull-up; - }; - - reset-n { - pins = "gpio35"; - function = "gpio"; - - drive-strength = <2>; - output-low; - bias-pull-down; - }; - - wake-n { - pins = "gpio37"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie0_pwren_state: pcie0-pwren { - pins = "gpio90"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - pcie1_default_state: pcie1-default { - perst-n { - pins = "gpio102"; - function = "gpio"; - - drive-strength = <16>; - bias-disable; - }; - - clkreq { - pins = "gpio103"; - function = "pci_e1"; - bias-pull-up; - }; - - wake-n { - pins = "gpio11"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; - - reset-n { - pins = "gpio75"; - function = "gpio"; - - drive-strength = <16>; - bias-pull-up; - output-high; - }; - }; - - sdc2_default_state: sdc2-default { - clk { - pins = "sdc2_clk"; - bias-disable; - - /* - * It seems that mmc_test reports errors if drive - * strength is not 16 on clk, cmd, and data pins. - */ - drive-strength = <16>; - }; - - cmd { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - data { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <10>; - }; - }; - - sdc2_card_det_n: sd-card-det-n { - pins = "gpio126"; - function = "gpio"; - bias-pull-up; - }; - - wcd_intr_default: wcd_intr_default { - pins = <54>; - function = "gpio"; - - input-enable; - bias-pull-down; - drive-strength = <2>; - }; -}; - -&uart3 { - label = "LS-UART0"; - status = "disabled"; -}; - -&uart6 { - status = "okay"; - - bluetooth { - compatible = "qcom,wcn3990-bt"; - - vddio-supply = <&vreg_s4a_1p8>; - vddxo-supply = <&vreg_l7a_1p8>; - vddrf-supply = <&vreg_l17a_1p3>; - vddch0-supply = <&vreg_l25a_3p3>; - max-speed = <3200000>; - }; -}; - -&uart9 { - label = "LS-UART1"; - status = "okay"; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "peripheral"; -}; - -&usb_1_hsphy { - status = "okay"; - - vdd-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l12a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = ; - qcom,preemphasis-level = ; - qcom,preemphasis-width = ; -}; - -&usb_1_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vreg_l26a_1p2>; - vdda-pll-supply = <&vreg_l1a_0p875>; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "host"; -}; - -&usb_2_hsphy { - status = "okay"; - - vdd-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l12a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = ; -}; - -&usb_2_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vreg_l26a_1p2>; - vdda-pll-supply = <&vreg_l1a_0p875>; -}; - -&ufs_mem_hc { - status = "okay"; - - reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; - - vcc-supply = <&vreg_l20a_2p95>; - vcc-max-microamp = <800000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l26a_1p2>; -}; - -&wcd9340{ - pinctrl-0 = <&wcd_intr_default>; - pinctrl-names = "default"; - clock-names = "extclk"; - clocks = <&rpmhcc RPMH_LN_BB_CLK2>; - reset-gpios = <&tlmm 64 0>; - vdd-buck-supply = <&vreg_s4a_1p8>; - vdd-buck-sido-supply = <&vreg_s4a_1p8>; - vdd-tx-supply = <&vreg_s4a_1p8>; - vdd-rx-supply = <&vreg_s4a_1p8>; - vdd-io-supply = <&vreg_s4a_1p8>; - - swm: swm@c85 { - left_spkr: wsa8810-left{ - compatible = "sdw10217201000"; - reg = <0 1>; - powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; - #thermal-sensor-cells = <0>; - sound-name-prefix = "SpkrLeft"; - #sound-dai-cells = <0>; - }; - - right_spkr: wsa8810-right{ - compatible = "sdw10217201000"; - powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; - reg = <0 2>; - #thermal-sensor-cells = <0>; - sound-name-prefix = "SpkrRight"; - #sound-dai-cells = <0>; - }; - }; -}; - -&wifi { - status = "okay"; - - vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; - vdd-1.8-xo-supply = <&vreg_l7a_1p8>; - vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; - vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; - - qcom,snoc-host-cap-8bit-quirk; -}; - -/* PINCTRL - additions to nodes defined in sdm845.dtsi */ -&qup_spi2_default { - drive-strength = <16>; -}; - -&qup_uart3_default{ - pinmux { - pins = "gpio41", "gpio42", "gpio43", "gpio44"; - function = "qup3"; - }; -}; - -&qup_i2c10_default { - pinconf { - pins = "gpio55", "gpio56"; - drive-strength = <2>; - bias-disable; - }; -}; - -&qup_uart6_default { - pinmux { - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - function = "qup6"; - }; - - cts { - pins = "gpio45"; - bias-disable; - }; - - rts-tx { - pins = "gpio46", "gpio47"; - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio48"; - bias-pull-up; - }; -}; - -&qup_uart9_default { - pinconf-tx { - pins = "gpio4"; - drive-strength = <2>; - bias-disable; - }; - - pinconf-rx { - pins = "gpio5"; - drive-strength = <2>; - bias-pull-up; - }; -}; - -&pm8998_gpio { - -}; - -&cci { - status = "okay"; -}; - -&cci_i2c0 { - camera@10 { - compatible = "ovti,ov8856"; - reg = <0x10>; - - // CAM0_RST_N - reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&cam0_default>; - gpios = <&tlmm 13 0>, - <&tlmm 9 GPIO_ACTIVE_LOW>; - - clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; - clock-names = "xvclk"; - clock-frequency = <19200000>; - - /* The &vreg_s4a_1p8 trace is powered on as a, - * so it is represented by a fixed regulator. - * - * The 2.8V vdda-supply and 1.2V vddd-supply regulators - * both have to be enabled through the power management - * gpios. - */ - power-domains = <&clock_camcc TITAN_TOP_GDSC>; - - dovdd-supply = <&vreg_lvs1a_1p8>; - avdd-supply = <&cam0_avdd_2v8>; - dvdd-supply = <&cam0_dvdd_1v2>; - - status = "disable"; - - port { - ov8856_ep: endpoint { - clock-lanes = <1>; - link-frequencies = /bits/ 64 - <360000000 180000000>; - data-lanes = <1 2 3 4>; -// remote-endpoint = <&csiphy0_ep>; - }; - }; - }; -}; - -&cci_i2c1 { - camera@60 { - compatible = "ovti,ov7251"; - - // I2C address as per ov7251.txt linux documentation - reg = <0x60>; - - // CAM3_RST_N - enable-gpios = <&tlmm 21 0>; - pinctrl-names = "default"; - pinctrl-0 = <&cam3_default>; - gpios = <&tlmm 16 0>, - <&tlmm 21 0>; - - clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; - clock-names = "xclk"; - clock-frequency = <24000000>; - - /* The &vreg_s4a_1p8 trace always powered on. - * - * The 2.8V vdda-supply regulator is enabled when the - * vreg_s4a_1p8 trace is pulled high. - * It too is represented by a fixed regulator. - * - * No 1.2V vddd-supply regulator is used. - */ - power-domains = <&clock_camcc TITAN_TOP_GDSC>; - - vdddo-supply = <&vreg_lvs1a_1p8>; - vdda-supply = <&cam3_avdd_2v8>; - - status = "disable"; - - port { - ov7251_ep: endpoint { - clock-lanes = <1>; - data-lanes = <0 1>; -// remote-endpoint = <&csiphy3_ep>; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts deleted file mode 100644 index 1372fe860..000000000 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ /dev/null @@ -1,636 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * SDM845 MTP board device tree source - * - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include -#include -#include "sdm845.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. SDM845 MTP"; - compatible = "qcom,sdm845-mtp", "qcom,sdm845"; - - aliases { - serial0 = &uart9; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - - /* - * Apparently RPMh does not provide support for PM8998 S4 because it - * is always-on; model it as a fixed regulator. - */ - vreg_s4a_1p8: pm8998-smps4 { - compatible = "regulator-fixed"; - regulator-name = "vreg_s4a_1p8"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - - vin-supply = <&vph_pwr>; - }; -}; - -&adsp_pas { - status = "okay"; - firmware-name = "qcom/sdm845/adsp.mdt"; -}; - -&apps_rsc { - pm8998-rpmh-regulators { - compatible = "qcom,pm8998-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-s8-supply = <&vph_pwr>; - vdd-s9-supply = <&vph_pwr>; - vdd-s10-supply = <&vph_pwr>; - vdd-s11-supply = <&vph_pwr>; - vdd-s12-supply = <&vph_pwr>; - vdd-s13-supply = <&vph_pwr>; - vdd-l1-l27-supply = <&vreg_s7a_1p025>; - vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; - vdd-l3-l11-supply = <&vreg_s7a_1p025>; - vdd-l4-l5-supply = <&vreg_s7a_1p025>; - vdd-l6-supply = <&vph_pwr>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; - vdd-l9-supply = <&vreg_bob>; - vdd-l10-l23-l25-supply = <&vreg_bob>; - vdd-l13-l19-l21-supply = <&vreg_bob>; - vdd-l16-l28-supply = <&vreg_bob>; - vdd-l18-l22-supply = <&vreg_bob>; - vdd-l20-l24-supply = <&vreg_bob>; - vdd-l26-supply = <&vreg_s3a_1p35>; - vin-lvs-1-2-supply = <&vreg_s4a_1p8>; - - vreg_s2a_1p125: smps2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - vreg_s3a_1p35: smps3 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_s5a_2p04: smps5 { - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2040000>; - }; - - vreg_s7a_1p025: smps7 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1028000>; - }; - - vdd_qusb_hs0: - vdda_hp_pcie_core: - vdda_mipi_csi0_0p9: - vdda_mipi_csi1_0p9: - vdda_mipi_csi2_0p9: - vdda_mipi_dsi0_pll: - vdda_mipi_dsi1_pll: - vdda_qlink_lv: - vdda_qlink_lv_ck: - vdda_qrefs_0p875: - vdda_pcie_core: - vdda_pll_cc_ebi01: - vdda_pll_cc_ebi23: - vdda_sp_sensor: - vdda_ufs1_core: - vdda_ufs2_core: - vdda_usb1_ss_core: - vdda_usb2_ss_core: - vreg_l1a_0p875: ldo1 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - - vddpx_10: - vreg_l2a_1p2: ldo2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-always-on; - }; - - vreg_l3a_1p0: ldo3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-initial-mode = ; - }; - - vdd_wcss_cx: - vdd_wcss_mx: - vdda_wcss_pll: - vreg_l5a_0p8: ldo5 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vddpx_13: - vreg_l6a_1p8: ldo6 { - regulator-min-microvolt = <1856000>; - regulator-max-microvolt = <1856000>; - regulator-initial-mode = ; - }; - - vreg_l7a_1p8: ldo7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l8a_1p2: ldo8 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1248000>; - regulator-initial-mode = ; - }; - - vreg_l9a_1p8: ldo9 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l10a_1p8: ldo10 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l11a_1p0: ldo11 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1048000>; - regulator-initial-mode = ; - }; - - vdd_qfprom: - vdd_qfprom_sp: - vdda_apc1_cs_1p8: - vdda_gfx_cs_1p8: - vdda_qrefs_1p8: - vdda_qusb_hs0_1p8: - vddpx_11: - vreg_l12a_1p8: ldo12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vddpx_2: - vreg_l13a_2p95: ldo13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l14a_1p88: ldo14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l15a_1p8: ldo15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l16a_2p7: ldo16 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - regulator-initial-mode = ; - }; - - vreg_l17a_1p3: ldo17 { - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l18a_2p7: ldo18 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l19a_3p0: ldo19 { - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <3104000>; - regulator-initial-mode = ; - }; - - vreg_l20a_2p95: ldo20 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l21a_2p95: ldo21 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l22a_2p85: ldo22 { - regulator-min-microvolt = <2864000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vreg_l23a_3p3: ldo23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vdda_qusb_hs0_3p1: - vreg_l24a_3p075: ldo24 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3088000>; - regulator-initial-mode = ; - }; - - vreg_l25a_3p3: ldo25 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vdda_hp_pcie_1p2: - vdda_hv_ebi0: - vdda_hv_ebi1: - vdda_hv_ebi2: - vdda_hv_ebi3: - vdda_mipi_csi_1p25: - vdda_mipi_dsi0_1p2: - vdda_mipi_dsi1_1p2: - vdda_pcie_1p2: - vdda_ufs1_1p2: - vdda_ufs2_1p2: - vdda_usb1_ss_1p2: - vdda_usb2_ss_1p2: - vreg_l26a_1p2: ldo26 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l28a_3p0: ldo28 { - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - - vreg_lvs1a_1p8: lvs1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vreg_lvs2a_1p8: lvs2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - - pmi8998-rpmh-regulators { - compatible = "qcom,pmi8998-rpmh-regulators"; - qcom,pmic-id = "b"; - - vdd-bob-supply = <&vph_pwr>; - - vreg_bob: bob { - regulator-min-microvolt = <3312000>; - regulator-max-microvolt = <3600000>; - regulator-initial-mode = ; - regulator-allow-bypass; - }; - }; - - pm8005-rpmh-regulators { - compatible = "qcom,pm8005-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - - vreg_s3c_0p6: smps3 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <600000>; - }; - }; -}; - -&cdsp_pas { - status = "okay"; - firmware-name = "qcom/sdm845/cdsp.mdt"; -}; - -&dsi0 { - status = "okay"; - vdda-supply = <&vdda_mipi_dsi0_1p2>; - - qcom,dual-dsi-mode; - qcom,master-dsi; - - #address-cells = <1>; - #size-cells = <0>; - - ports { - port@1 { - endpoint { - remote-endpoint = <&truly_in_0>; - data-lanes = <0 1 2 3>; - }; - }; - }; - - panel@0 { - compatible = "truly,nt35597-2K-display"; - reg = <0>; - vdda-supply = <&vreg_l14a_1p88>; - - reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; - mode-gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - truly_in_0: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - truly_in_1: endpoint { - remote-endpoint = <&dsi1_out>; - }; - }; - }; - }; -}; - -&dsi0_phy { - status = "okay"; - vdds-supply = <&vdda_mipi_dsi0_pll>; -}; - -&dsi1 { - status = "okay"; - vdda-supply = <&vdda_mipi_dsi1_1p2>; - - qcom,dual-dsi-mode; - - ports { - port@1 { - endpoint { - remote-endpoint = <&truly_in_1>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&dsi1_phy { - status = "okay"; - vdds-supply = <&vdda_mipi_dsi1_pll>; -}; - -&gcc { - protected-clocks = , - , - , - , - ; -}; - -&gpu { - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sdm845/a630_zap.mbn"; - }; -}; - -&i2c10 { - status = "okay"; - clock-frequency = <400000>; -}; - -&mdss { - status = "okay"; -}; - -&mdss_mdp { - status = "okay"; -}; - -&mss_pil { - status = "okay"; - firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&sdhc_2 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_card_det_n>; - - vmmc-supply = <&vreg_l21a_2p95>; - vqmmc-supply = <&vddpx_2>; - - cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; -}; - -&uart9 { - status = "okay"; -}; - -&ufs_mem_hc { - status = "okay"; - - reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; - - vcc-supply = <&vreg_l20a_2p95>; - vcc-max-microamp = <600000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vdda_ufs1_core>; - vdda-pll-supply = <&vdda_ufs1_1p2>; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - /* Until we have Type C hooked up we'll force this as peripheral. */ - dr_mode = "peripheral"; -}; - -&usb_1_hsphy { - status = "okay"; - - vdd-supply = <&vdda_usb1_ss_core>; - vdda-pll-supply = <&vdda_qusb_hs0_1p8>; - vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = ; - qcom,preemphasis-level = ; - qcom,preemphasis-width = ; -}; - -&usb_1_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vdda_usb1_ss_1p2>; - vdda-pll-supply = <&vdda_usb1_ss_core>; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - /* - * Though the USB block on SDM845 can support host, there's no vbus - * signal for this port on MTP. Thus (unless you have a non-compliant - * hub that works without vbus) the only sensible thing is to force - * peripheral mode. - */ - dr_mode = "peripheral"; -}; - -&usb_2_hsphy { - status = "okay"; - - vdd-supply = <&vdda_usb2_ss_core>; - vdda-pll-supply = <&vdda_qusb_hs0_1p8>; - vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = ; -}; - -&usb_2_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vdda_usb2_ss_1p2>; - vdda-pll-supply = <&vdda_usb2_ss_core>; -}; - -&wifi { - status = "okay"; - vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; - vdd-1.8-xo-supply = <&vreg_l7a_1p8>; - vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; - vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; -}; - -/* PINCTRL - additions to nodes defined in sdm845.dtsi */ - -&qup_i2c10_default { - pinconf { - pins = "gpio55", "gpio56"; - drive-strength = <2>; - bias-disable; - }; -}; - -&qup_uart9_default { - pinconf-tx { - pins = "gpio4"; - drive-strength = <2>; - bias-disable; - }; - - pinconf-rx { - pins = "gpio5"; - drive-strength = <2>; - bias-pull-up; - }; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; - - sdc2_clk: sdc2-clk { - pinconf { - pins = "sdc2_clk"; - bias-disable; - - /* - * It seems that mmc_test reports errors if drive - * strength is not 16 on clk, cmd, and data pins. - */ - drive-strength = <16>; - }; - }; - - sdc2_cmd: sdc2-cmd { - pinconf { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <16>; - }; - }; - - sdc2_data: sdc2-data { - pinconf { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <16>; - }; - }; - - sd_card_det_n: sd-card-det-n { - pinmux { - pins = "gpio126"; - function = "gpio"; - }; - - pinconf { - pins = "gpio126"; - bias-pull-up; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts deleted file mode 100644 index 86cbae63e..000000000 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ /dev/null @@ -1,380 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/dts-v1/; - -#include -#include -#include -#include "sdm845.dtsi" -#include "pm8998.dtsi" -#include "pmi8998.dtsi" - -/* - * Delete following upstream (sdm845.dtsi) reserved - * memory mappings which are different in this device. - */ -/delete-node/ &tz_mem; -/delete-node/ &adsp_mem; -/delete-node/ &wlan_msa_mem; -/delete-node/ &mpss_region; -/delete-node/ &venus_mem; -/delete-node/ &cdsp_mem; -/delete-node/ &mba_region; -/delete-node/ &slpi_mem; -/delete-node/ &spss_mem; -/delete-node/ &rmtfs_mem; - -/ { - model = "Xiaomi Pocophone F1"; - compatible = "xiaomi,beryllium", "qcom,sdm845"; - - /* required for bootloader to select correct board */ - qcom,board-id = <69 0>; - qcom,msm-id = <321 0x20001>; - - aliases { - hsuart0 = &uart6; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&vol_up_pin_a>; - - vol-up { - label = "Volume Up"; - linux,code = ; - gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; - }; - }; - - /* Reserved memory changes from downstream */ - reserved-memory { - tz_mem: memory@86200000 { - reg = <0 0x86200000 0 0x4900000>; - no-map; - }; - - adsp_mem: memory@8c500000 { - reg = <0 0x8c500000 0 0x1e00000>; - no-map; - }; - - wlan_msa_mem: memory@8e300000 { - reg = <0 0x8e300000 0 0x100000>; - no-map; - }; - - mpss_region: memory@8e400000 { - reg = <0 0x8e400000 0 0x7800000>; - no-map; - }; - - venus_mem: memory@95c00000 { - reg = <0 0x95c00000 0 0x500000>; - no-map; - }; - - cdsp_mem: memory@96100000 { - reg = <0 0x96100000 0 0x800000>; - no-map; - }; - - mba_region: memory@96900000 { - reg = <0 0x96900000 0 0x200000>; - no-map; - }; - - slpi_mem: memory@96b00000 { - reg = <0 0x96b00000 0 0x1400000>; - no-map; - }; - - spss_mem: memory@97f00000 { - reg = <0 0x97f00000 0 0x100000>; - no-map; - }; - - rmtfs_mem: memory@f6301000 { - compatible = "qcom,rmtfs-mem"; - reg = <0 0xf6301000 0 0x200000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - }; - - vreg_s4a_1p8: vreg-s4a-1p8 { - compatible = "regulator-fixed"; - regulator-name = "vreg_s4a_1p8"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; -}; - -&adsp_pas { - status = "okay"; - firmware-name = "qcom/sdm845/adsp.mdt"; -}; - -&apps_rsc { - pm8998-rpmh-regulators { - compatible = "qcom,pm8998-rpmh-regulators"; - qcom,pmic-id = "a"; - - vreg_l1a_0p875: ldo1 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - - vreg_l5a_0p8: ldo5 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vreg_l7a_1p8: ldo7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l12a_1p8: ldo12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l13a_2p95: ldo13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l17a_1p3: ldo17 { - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l20a_2p95: ldo20 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2968000>; - regulator-initial-mode = ; - }; - - vreg_l21a_2p95: ldo21 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2968000>; - regulator-initial-mode = ; - }; - - vreg_l24a_3p075: ldo24 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3088000>; - regulator-initial-mode = ; - }; - - vreg_l25a_3p3: ldo25 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vreg_l26a_1p2: ldo26 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - }; -}; - -&cdsp_pas { - status = "okay"; - firmware-name = "qcom/sdm845/cdsp.mdt"; -}; - -&gcc { - protected-clocks = , - , - , - , - ; -}; - -&gpu { - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/sdm845/a630_zap.mbn"; - }; -}; - -&mss_pil { - status = "okay"; - firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mdt"; -}; - -&pm8998_gpio { - vol_up_pin_a: vol-up-active { - pins = "gpio6"; - function = "normal"; - input-enable; - bias-pull-up; - qcom,drive-strength = ; - }; -}; - -&pm8998_pon { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; -}; - -&qupv3_id_0 { - status = "okay"; -}; - -&sdhc_2 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; - - vmmc-supply = <&vreg_l21a_2p95>; - vqmmc-supply = <&vreg_l13a_2p95>; - - bus-width = <4>; - cd-gpios = <&tlmm 126 GPIO_ACTIVE_HIGH>; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; - - sdc2_default_state: sdc2-default { - clk { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <16>; - }; - - cmd { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - data { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <10>; - }; - }; - - sdc2_card_det_n: sd-card-det-n { - pins = "gpio126"; - function = "gpio"; - bias-pull-up; - }; -}; - -&uart6 { - status = "okay"; - - bluetooth { - compatible = "qcom,wcn3990-bt"; - - vddio-supply = <&vreg_s4a_1p8>; - vddxo-supply = <&vreg_l7a_1p8>; - vddrf-supply = <&vreg_l17a_1p3>; - vddch0-supply = <&vreg_l25a_3p3>; - max-speed = <3200000>; - }; -}; - -&ufs_mem_hc { - status = "okay"; - - reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; - - vcc-supply = <&vreg_l20a_2p95>; - vcc-max-microamp = <800000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l26a_1p2>; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "peripheral"; -}; - -&usb_1_hsphy { - status = "okay"; - - vdd-supply = <&vreg_l1a_0p875>; - vdda-pll-supply = <&vreg_l12a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = ; - qcom,preemphasis-level = ; - qcom,preemphasis-width = ; -}; - -&usb_1_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vreg_l26a_1p2>; - vdda-pll-supply = <&vreg_l1a_0p875>; -}; - -&wifi { - status = "okay"; - - vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; - vdd-1.8-xo-supply = <&vreg_l7a_1p8>; - vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; - vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; -}; - -/* PINCTRL - additions to nodes defined in sdm845.dtsi */ - -&qup_uart6_default { - pinmux { - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - function = "qup6"; - }; - - cts { - pins = "gpio45"; - bias-disable; - }; - - rts-tx { - pins = "gpio46", "gpio47"; - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio48"; - bias-pull-up; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi deleted file mode 100644 index 9beb3c34f..000000000 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ /dev/null @@ -1,5162 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * SDM845 SoC device tree source - * - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - i2c9 = &i2c9; - i2c10 = &i2c10; - i2c11 = &i2c11; - i2c12 = &i2c12; - i2c13 = &i2c13; - i2c14 = &i2c14; - i2c15 = &i2c15; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - spi4 = &spi4; - spi5 = &spi5; - spi6 = &spi6; - spi7 = &spi7; - spi8 = &spi8; - spi9 = &spi9; - spi10 = &spi10; - spi11 = &spi11; - spi12 = &spi12; - spi13 = &spi13; - spi14 = &spi14; - spi15 = &spi15; - }; - - chosen { }; - - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0 0x80000000 0 0>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@85700000 { - reg = <0 0x85700000 0 0x600000>; - no-map; - }; - - xbl_mem: memory@85e00000 { - reg = <0 0x85e00000 0 0x100000>; - no-map; - }; - - aop_mem: memory@85fc0000 { - reg = <0 0x85fc0000 0 0x20000>; - no-map; - }; - - aop_cmd_db_mem: memory@85fe0000 { - compatible = "qcom,cmd-db"; - reg = <0x0 0x85fe0000 0 0x20000>; - no-map; - }; - - smem_mem: memory@86000000 { - reg = <0x0 0x86000000 0 0x200000>; - no-map; - }; - - tz_mem: memory@86200000 { - reg = <0 0x86200000 0 0x2d00000>; - no-map; - }; - - rmtfs_mem: memory@88f00000 { - compatible = "qcom,rmtfs-mem"; - reg = <0 0x88f00000 0 0x200000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - qseecom_mem: memory@8ab00000 { - reg = <0 0x8ab00000 0 0x1400000>; - no-map; - }; - - camera_mem: memory@8bf00000 { - reg = <0 0x8bf00000 0 0x500000>; - no-map; - }; - - ipa_fw_mem: memory@8c400000 { - reg = <0 0x8c400000 0 0x10000>; - no-map; - }; - - ipa_gsi_mem: memory@8c410000 { - reg = <0 0x8c410000 0 0x5000>; - no-map; - }; - - gpu_mem: memory@8c415000 { - reg = <0 0x8c415000 0 0x2000>; - no-map; - }; - - adsp_mem: memory@8c500000 { - reg = <0 0x8c500000 0 0x1a00000>; - no-map; - }; - - wlan_msa_mem: memory@8df00000 { - reg = <0 0x8df00000 0 0x100000>; - no-map; - }; - - mpss_region: memory@8e000000 { - reg = <0 0x8e000000 0 0x7800000>; - no-map; - }; - - venus_mem: memory@95800000 { - reg = <0 0x95800000 0 0x500000>; - no-map; - }; - - cdsp_mem: memory@95d00000 { - reg = <0 0x95d00000 0 0x800000>; - no-map; - }; - - mba_region: memory@96500000 { - reg = <0 0x96500000 0 0x200000>; - no-map; - }; - - slpi_mem: memory@96700000 { - reg = <0 0x96700000 0 0x1400000>; - no-map; - }; - - spss_mem: memory@97b00000 { - reg = <0 0x97b00000 0 0x100000>; - no-map; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x0>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <607>; - dynamic-power-coefficient = <100>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - next-level-cache = <&L2_0>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x100>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <607>; - dynamic-power-coefficient = <100>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - next-level-cache = <&L2_100>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x200>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <607>; - dynamic-power-coefficient = <100>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - next-level-cache = <&L2_200>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x300>; - enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <607>; - dynamic-power-coefficient = <100>; - qcom,freq-domain = <&cpufreq_hw 0>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - next-level-cache = <&L2_300>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x400>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - dynamic-power-coefficient = <396>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - next-level-cache = <&L2_400>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x500>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - dynamic-power-coefficient = <396>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - next-level-cache = <&L2_500>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x600>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - dynamic-power-coefficient = <396>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - next-level-cache = <&L2_600>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo385"; - reg = <0x0 0x700>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; - dynamic-power-coefficient = <396>; - qcom,freq-domain = <&cpufreq_hw 1>; - operating-points-v2 = <&cpu4_opp_table>; - interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; - #cooling-cells = <2>; - next-level-cache = <&L2_700>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - - core4 { - cpu = <&CPU4>; - }; - - core5 { - cpu = <&CPU5>; - }; - - core6 { - cpu = <&CPU6>; - }; - - core7 { - cpu = <&CPU7>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "little-power-down"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <350>; - exit-latency-us = <461>; - min-residency-us = <1890>; - local-timer-stop; - }; - - LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { - compatible = "arm,idle-state"; - idle-state-name = "little-rail-power-down"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <360>; - exit-latency-us = <531>; - min-residency-us = <3934>; - local-timer-stop; - }; - - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "big-power-down"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <264>; - exit-latency-us = <621>; - min-residency-us = <952>; - local-timer-stop; - }; - - BIG_CPU_SLEEP_1: cpu-sleep-1-1 { - compatible = "arm,idle-state"; - idle-state-name = "big-rail-power-down"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <702>; - exit-latency-us = <1061>; - min-residency-us = <4488>; - local-timer-stop; - }; - - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - idle-state-name = "cluster-power-down"; - arm,psci-suspend-param = <0x400000F4>; - entry-latency-us = <3263>; - exit-latency-us = <6562>; - min-residency-us = <9987>; - local-timer-stop; - }; - }; - }; - - cpu0_opp_table: cpu0_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - cpu0_opp1: opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-peak-kBps = <800000 4800000>; - }; - - cpu0_opp2: opp-403200000 { - opp-hz = /bits/ 64 <403200000>; - opp-peak-kBps = <800000 4800000>; - }; - - cpu0_opp3: opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - opp-peak-kBps = <800000 6451200>; - }; - - cpu0_opp4: opp-576000000 { - opp-hz = /bits/ 64 <576000000>; - opp-peak-kBps = <800000 6451200>; - }; - - cpu0_opp5: opp-652800000 { - opp-hz = /bits/ 64 <652800000>; - opp-peak-kBps = <800000 7680000>; - }; - - cpu0_opp6: opp-748800000 { - opp-hz = /bits/ 64 <748800000>; - opp-peak-kBps = <1804000 9216000>; - }; - - cpu0_opp7: opp-825600000 { - opp-hz = /bits/ 64 <825600000>; - opp-peak-kBps = <1804000 9216000>; - }; - - cpu0_opp8: opp-902400000 { - opp-hz = /bits/ 64 <902400000>; - opp-peak-kBps = <1804000 10444800>; - }; - - cpu0_opp9: opp-979200000 { - opp-hz = /bits/ 64 <979200000>; - opp-peak-kBps = <1804000 11980800>; - }; - - cpu0_opp10: opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-peak-kBps = <1804000 11980800>; - }; - - cpu0_opp11: opp-1132800000 { - opp-hz = /bits/ 64 <1132800000>; - opp-peak-kBps = <2188000 13516800>; - }; - - cpu0_opp12: opp-1228800000 { - opp-hz = /bits/ 64 <1228800000>; - opp-peak-kBps = <2188000 15052800>; - }; - - cpu0_opp13: opp-1324800000 { - opp-hz = /bits/ 64 <1324800000>; - opp-peak-kBps = <2188000 16588800>; - }; - - cpu0_opp14: opp-1420800000 { - opp-hz = /bits/ 64 <1420800000>; - opp-peak-kBps = <3072000 18124800>; - }; - - cpu0_opp15: opp-1516800000 { - opp-hz = /bits/ 64 <1516800000>; - opp-peak-kBps = <3072000 19353600>; - }; - - cpu0_opp16: opp-1612800000 { - opp-hz = /bits/ 64 <1612800000>; - opp-peak-kBps = <4068000 19353600>; - }; - - cpu0_opp17: opp-1689600000 { - opp-hz = /bits/ 64 <1689600000>; - opp-peak-kBps = <4068000 20889600>; - }; - - cpu0_opp18: opp-1766400000 { - opp-hz = /bits/ 64 <1766400000>; - opp-peak-kBps = <4068000 22425600>; - }; - }; - - cpu4_opp_table: cpu4_opp_table { - compatible = "operating-points-v2"; - opp-shared; - - cpu4_opp1: opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-peak-kBps = <800000 4800000>; - }; - - cpu4_opp2: opp-403200000 { - opp-hz = /bits/ 64 <403200000>; - opp-peak-kBps = <800000 4800000>; - }; - - cpu4_opp3: opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - opp-peak-kBps = <1804000 4800000>; - }; - - cpu4_opp4: opp-576000000 { - opp-hz = /bits/ 64 <576000000>; - opp-peak-kBps = <1804000 4800000>; - }; - - cpu4_opp5: opp-652800000 { - opp-hz = /bits/ 64 <652800000>; - opp-peak-kBps = <1804000 4800000>; - }; - - cpu4_opp6: opp-748800000 { - opp-hz = /bits/ 64 <748800000>; - opp-peak-kBps = <1804000 4800000>; - }; - - cpu4_opp7: opp-825600000 { - opp-hz = /bits/ 64 <825600000>; - opp-peak-kBps = <2188000 9216000>; - }; - - cpu4_opp8: opp-902400000 { - opp-hz = /bits/ 64 <902400000>; - opp-peak-kBps = <2188000 9216000>; - }; - - cpu4_opp9: opp-979200000 { - opp-hz = /bits/ 64 <979200000>; - opp-peak-kBps = <2188000 9216000>; - }; - - cpu4_opp10: opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-peak-kBps = <3072000 9216000>; - }; - - cpu4_opp11: opp-1132800000 { - opp-hz = /bits/ 64 <1132800000>; - opp-peak-kBps = <3072000 11980800>; - }; - - cpu4_opp12: opp-1209600000 { - opp-hz = /bits/ 64 <1209600000>; - opp-peak-kBps = <4068000 11980800>; - }; - - cpu4_opp13: opp-1286400000 { - opp-hz = /bits/ 64 <1286400000>; - opp-peak-kBps = <4068000 11980800>; - }; - - cpu4_opp14: opp-1363200000 { - opp-hz = /bits/ 64 <1363200000>; - opp-peak-kBps = <4068000 15052800>; - }; - - cpu4_opp15: opp-1459200000 { - opp-hz = /bits/ 64 <1459200000>; - opp-peak-kBps = <4068000 15052800>; - }; - - cpu4_opp16: opp-1536000000 { - opp-hz = /bits/ 64 <1536000000>; - opp-peak-kBps = <5412000 15052800>; - }; - - cpu4_opp17: opp-1612800000 { - opp-hz = /bits/ 64 <1612800000>; - opp-peak-kBps = <5412000 15052800>; - }; - - cpu4_opp18: opp-1689600000 { - opp-hz = /bits/ 64 <1689600000>; - opp-peak-kBps = <5412000 19353600>; - }; - - cpu4_opp19: opp-1766400000 { - opp-hz = /bits/ 64 <1766400000>; - opp-peak-kBps = <6220000 19353600>; - }; - - cpu4_opp20: opp-1843200000 { - opp-hz = /bits/ 64 <1843200000>; - opp-peak-kBps = <6220000 19353600>; - }; - - cpu4_opp21: opp-1920000000 { - opp-hz = /bits/ 64 <1920000000>; - opp-peak-kBps = <7216000 19353600>; - }; - - cpu4_opp22: opp-1996800000 { - opp-hz = /bits/ 64 <1996800000>; - opp-peak-kBps = <7216000 20889600>; - }; - - cpu4_opp23: opp-2092800000 { - opp-hz = /bits/ 64 <2092800000>; - opp-peak-kBps = <7216000 20889600>; - }; - - cpu4_opp24: opp-2169600000 { - opp-hz = /bits/ 64 <2169600000>; - opp-peak-kBps = <7216000 20889600>; - }; - - cpu4_opp25: opp-2246400000 { - opp-hz = /bits/ 64 <2246400000>; - opp-peak-kBps = <7216000 20889600>; - }; - - cpu4_opp26: opp-2323200000 { - opp-hz = /bits/ 64 <2323200000>; - opp-peak-kBps = <7216000 20889600>; - }; - - cpu4_opp27: opp-2400000000 { - opp-hz = /bits/ 64 <2400000000>; - opp-peak-kBps = <7216000 22425600>; - }; - - cpu4_opp28: opp-2476800000 { - opp-hz = /bits/ 64 <2476800000>; - opp-peak-kBps = <7216000 22425600>; - }; - - cpu4_opp29: opp-2553600000 { - opp-hz = /bits/ 64 <2553600000>; - opp-peak-kBps = <7216000 22425600>; - }; - - cpu4_opp30: opp-2649600000 { - opp-hz = /bits/ 64 <2649600000>; - opp-peak-kBps = <7216000 22425600>; - }; - - cpu4_opp31: opp-2745600000 { - opp-hz = /bits/ 64 <2745600000>; - opp-peak-kBps = <7216000 25497600>; - }; - - cpu4_opp32: opp-2803200000 { - opp-hz = /bits/ 64 <2803200000>; - opp-peak-kBps = <7216000 25497600>; - }; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - clock-output-names = "xo_board"; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-sdm845", "qcom,scm"; - }; - }; - - adsp_pas: remoteproc-adsp { - compatible = "qcom,sdm845-adsp-pas"; - - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - memory-region = <&adsp_mem>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "lpass"; - qcom,remote-pid = <2>; - mboxes = <&apss_shared 8>; - - apr { - compatible = "qcom,apr-v2"; - qcom,glink-channels = "apr_audio_svc"; - qcom,apr-domain = ; - #address-cells = <1>; - #size-cells = <0>; - qcom,intents = <512 20>; - - apr-service@3 { - reg = ; - compatible = "qcom,q6core"; - qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; - }; - - q6afe: apr-service@4 { - compatible = "qcom,q6afe"; - reg = ; - qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; - q6afedai: dais { - compatible = "qcom,q6afe-dais"; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <1>; - }; - }; - - q6asm: apr-service@7 { - compatible = "qcom,q6asm"; - reg = ; - qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; - q6asmdai: dais { - compatible = "qcom,q6asm-dais"; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <1>; - iommus = <&apps_smmu 0x1821 0x0>; - }; - }; - - q6adm: apr-service@8 { - compatible = "qcom,q6adm"; - reg = ; - qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; - q6routing: routing { - compatible = "qcom,q6adm-routing"; - #sound-dai-cells = <0>; - }; - }; - }; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "adsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x1823 0x0>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x1824 0x0>; - }; - }; - }; - }; - - cdsp_pas: remoteproc-cdsp { - compatible = "qcom,sdm845-cdsp-pas"; - - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - memory-region = <&cdsp_mem>; - - qcom,smem-states = <&cdsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "turing"; - qcom,remote-pid = <5>; - mboxes = <&apss_shared 4>; - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "cdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x1401 0x30>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x1402 0x30>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x1403 0x30>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x1404 0x30>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x1405 0x30>; - }; - - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - iommus = <&apps_smmu 0x1406 0x30>; - }; - - compute-cb@7 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <7>; - iommus = <&apps_smmu 0x1407 0x30>; - }; - - compute-cb@8 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <8>; - iommus = <&apps_smmu 0x1408 0x30>; - }; - }; - }; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - - interrupts = ; - - mboxes = <&apss_shared 6>; - - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - cdsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - cdsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-lpass { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - - interrupts = ; - - mboxes = <&apss_shared 10>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - adsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - adsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-mpss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - interrupts = ; - mboxes = <&apss_shared 14>; - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - ipa_smp2p_out: ipa-ap-to-modem { - qcom,entry-name = "ipa"; - #qcom,smem-state-cells = <1>; - }; - - ipa_smp2p_in: ipa-modem-to-ap { - qcom,entry-name = "ipa"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - interrupts = ; - mboxes = <&apss_shared 26>; - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - slpi_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - slpi_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - soc: soc@0 { - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0 0 0 0x10 0>; - dma-ranges = <0 0 0 0 0x10 0>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sdm845"; - reg = <0 0x00100000 0 0x1f0000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - qfprom@784000 { - compatible = "qcom,qfprom"; - reg = <0 0x00784000 0 0x8ff>; - #address-cells = <1>; - #size-cells = <1>; - - qusb2p_hstx_trim: hstx-trim-primary@1eb { - reg = <0x1eb 0x1>; - bits = <1 4>; - }; - - qusb2s_hstx_trim: hstx-trim-secondary@1eb { - reg = <0x1eb 0x2>; - bits = <6 4>; - }; - }; - - rng: rng@793000 { - compatible = "qcom,prng-ee"; - reg = <0 0x00793000 0 0x1000>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; - - qup_opp_table: qup-opp-table { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-75000000 { - opp-hz = /bits/ 64 <75000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-128000000 { - opp-hz = /bits/ 64 <128000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - - qupv3_id_0: geniqup@8c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0 0x008c0000 0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c0: i2c@880000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c0_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - spi0: spi@880000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi0_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart0: serial@880000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart0_default>; - interrupts = ; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c1: i2c@884000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c1_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - spi1: spi@884000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi1_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart1: serial@884000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart1_default>; - interrupts = ; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c2: i2c@888000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00888000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c2_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - spi2: spi@888000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00888000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi2_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart2: serial@888000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00888000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart2_default>; - interrupts = ; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c3: i2c@88c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c3_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - spi3: spi@88c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi3_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart3: serial@88c000 { - compatible = "qcom,geni-uart"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart3_default>; - interrupts = ; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c4: i2c@890000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c4_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - spi4: spi@890000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi4_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart4: serial@890000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart4_default>; - interrupts = ; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c5: i2c@894000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c5_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - spi5: spi@894000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi5_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart5: serial@894000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart5_default>; - interrupts = ; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c6: i2c@898000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00898000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c6_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - spi6: spi@898000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00898000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi6_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart6: serial@898000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00898000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart6_default>; - interrupts = ; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c7: i2c@89c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0089c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c7_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - spi7: spi@89c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x0089c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi7_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart7: serial@89c000 { - compatible = "qcom,geni-uart"; - reg = <0 0x0089c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart7_default>; - interrupts = ; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - }; - - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0 0x00ac0000 0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c8: i2c@a80000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c8_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - spi8: spi@a80000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi8_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart8: serial@a80000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart8_default>; - interrupts = ; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c9: i2c@a84000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c9_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - spi9: spi@a84000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi9_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart9: serial@a84000 { - compatible = "qcom,geni-debug-uart"; - reg = <0 0x00a84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart9_default>; - interrupts = ; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c10: i2c@a88000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c10_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - spi10: spi@a88000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi10_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart10: serial@a88000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart10_default>; - interrupts = ; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c11: i2c@a8c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c11_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - spi11: spi@a8c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi11_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart11: serial@a8c000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart11_default>; - interrupts = ; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c12: i2c@a90000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c12_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - spi12: spi@a90000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi12_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart12: serial@a90000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart12_default>; - interrupts = ; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c13: i2c@a94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c13_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - spi13: spi@a94000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi13_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart13: serial@a94000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart13_default>; - interrupts = ; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c14: i2c@a98000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a98000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c14_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - spi14: spi@a98000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a98000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi14_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart14: serial@a98000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a98000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart14_default>; - interrupts = ; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c15: i2c@a9c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a9c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c15_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - spi15: spi@a9c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a9c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi15_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart15: serial@a9c000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00a9c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart15_default>; - interrupts = ; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - }; - - system-cache-controller@1100000 { - compatible = "qcom,sdm845-llcc"; - reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; - }; - - pcie0: pci@1c00000 { - compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; - reg = <0 0x01c00000 0 0x2000>, - <0 0x60000000 0 0xf1d>, - <0 0x60000f20 0 0xa8>, - <0 0x60100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>; - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; - clock-names = "pipe", - "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "tbu"; - - iommus = <&apps_smmu 0x1c10 0xf>; - iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, - <0x100 &apps_smmu 0x1c11 0x1>, - <0x200 &apps_smmu 0x1c12 0x1>, - <0x300 &apps_smmu 0x1c13 0x1>, - <0x400 &apps_smmu 0x1c14 0x1>, - <0x500 &apps_smmu 0x1c15 0x1>, - <0x600 &apps_smmu 0x1c16 0x1>, - <0x700 &apps_smmu 0x1c17 0x1>, - <0x800 &apps_smmu 0x1c18 0x1>, - <0x900 &apps_smmu 0x1c19 0x1>, - <0xa00 &apps_smmu 0x1c1a 0x1>, - <0xb00 &apps_smmu 0x1c1b 0x1>, - <0xc00 &apps_smmu 0x1c1c 0x1>, - <0xd00 &apps_smmu 0x1c1d 0x1>, - <0xe00 &apps_smmu 0x1c1e 0x1>, - <0xf00 &apps_smmu 0x1c1f 0x1>; - - resets = <&gcc GCC_PCIE_0_BCR>; - reset-names = "pci"; - - power-domains = <&gcc PCIE_0_GDSC>; - - phys = <&pcie0_lane>; - phy-names = "pciephy"; - - status = "disabled"; - }; - - pcie0_phy: phy@1c06000 { - compatible = "qcom,sdm845-qmp-pcie-phy"; - reg = <0 0x01c06000 0 0x18c>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_CLKREF_CLK>, - <&gcc GCC_PCIE_PHY_REFGEN_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; - - resets = <&gcc GCC_PCIE_0_PHY_BCR>; - reset-names = "phy"; - - assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; - assigned-clock-rates = <100000000>; - - status = "disabled"; - - pcie0_lane: lanes@1c06200 { - reg = <0 0x01c06200 0 0x128>, - <0 0x01c06400 0 0x1fc>, - <0 0x01c06800 0 0x218>, - <0 0x01c06600 0 0x70>; - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "pipe0"; - - #phy-cells = <0>; - clock-output-names = "pcie_0_pipe_clk"; - }; - }; - - pcie1: pci@1c08000 { - compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; - reg = <0 0x01c08000 0 0x2000>, - <0 0x40000000 0 0xf1d>, - <0 0x40000f20 0 0xa8>, - <0 0x40100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "config"; - device_type = "pci"; - linux,pci-domain = <1>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, - <&gcc GCC_PCIE_1_CLKREF_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; - clock-names = "pipe", - "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "ref", - "tbu"; - - assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; - assigned-clock-rates = <19200000>; - - iommus = <&apps_smmu 0x1c00 0xf>; - iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, - <0x100 &apps_smmu 0x1c01 0x1>, - <0x200 &apps_smmu 0x1c02 0x1>, - <0x300 &apps_smmu 0x1c03 0x1>, - <0x400 &apps_smmu 0x1c04 0x1>, - <0x500 &apps_smmu 0x1c05 0x1>, - <0x600 &apps_smmu 0x1c06 0x1>, - <0x700 &apps_smmu 0x1c07 0x1>, - <0x800 &apps_smmu 0x1c08 0x1>, - <0x900 &apps_smmu 0x1c09 0x1>, - <0xa00 &apps_smmu 0x1c0a 0x1>, - <0xb00 &apps_smmu 0x1c0b 0x1>, - <0xc00 &apps_smmu 0x1c0c 0x1>, - <0xd00 &apps_smmu 0x1c0d 0x1>, - <0xe00 &apps_smmu 0x1c0e 0x1>, - <0xf00 &apps_smmu 0x1c0f 0x1>; - - resets = <&gcc GCC_PCIE_1_BCR>; - reset-names = "pci"; - - power-domains = <&gcc PCIE_1_GDSC>; - - phys = <&pcie1_lane>; - phy-names = "pciephy"; - - status = "disabled"; - }; - - pcie1_phy: phy@1c0a000 { - compatible = "qcom,sdm845-qhp-pcie-phy"; - reg = <0 0x01c0a000 0 0x800>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_CLKREF_CLK>, - <&gcc GCC_PCIE_PHY_REFGEN_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; - - resets = <&gcc GCC_PCIE_1_PHY_BCR>; - reset-names = "phy"; - - assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; - assigned-clock-rates = <100000000>; - - status = "disabled"; - - pcie1_lane: lanes@1c06200 { - reg = <0 0x01c0a800 0 0x800>, - <0 0x01c0a800 0 0x800>, - <0 0x01c0b800 0 0x400>; - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; - clock-names = "pipe0"; - - #phy-cells = <0>; - clock-output-names = "pcie_1_pipe_clk"; - }; - }; - - mem_noc: interconnect@1380000 { - compatible = "qcom,sdm845-mem-noc"; - reg = <0 0x01380000 0 0x27200>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - dc_noc: interconnect@14e0000 { - compatible = "qcom,sdm845-dc-noc"; - reg = <0 0x014e0000 0 0x400>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - config_noc: interconnect@1500000 { - compatible = "qcom,sdm845-config-noc"; - reg = <0 0x01500000 0 0x5080>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect@1620000 { - compatible = "qcom,sdm845-system-noc"; - reg = <0 0x01620000 0 0x18080>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre1_noc: interconnect@16e0000 { - compatible = "qcom,sdm845-aggre1-noc"; - reg = <0 0x016e0000 0 0x15080>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect@1700000 { - compatible = "qcom,sdm845-aggre2-noc"; - reg = <0 0x01700000 0 0x1f300>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mmss_noc: interconnect@1740000 { - compatible = "qcom,sdm845-mmss-noc"; - reg = <0 0x01740000 0 0x1c100>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sdm845-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x2500>, - <0 0x01d90000 0 0x8000>; - reg-names = "std", "ice"; - interrupts = ; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - power-domains = <&gcc UFS_PHY_GDSC>; - #reset-cells = <1>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - iommus = <&apps_smmu 0x100 0xf>; - - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk", - "ice_core_clk"; - clocks = - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; - freq-table-hz = - <50000000 200000000>, - <0 0>, - <0 0>, - <37500000 150000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>, - <0 300000000>; - - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sdm845-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0x18c>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", - "ref_aux"; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: lanes@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; - #phy-cells = <0>; - }; - }; - - ipa: ipa@1e40000 { - compatible = "qcom,sdm845-ipa"; - - iommus = <&apps_smmu 0x720 0x0>, - <&apps_smmu 0x722 0x0>; - reg = <0 0x1e40000 0 0x7000>, - <0 0x1e47000 0 0x2000>, - <0 0x1e04000 0 0x2c000>; - reg-names = "ipa-reg", - "ipa-shared", - "gsi"; - - interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>, - <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, - <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ipa", - "gsi", - "ipa-clock-query", - "ipa-setup-ready"; - - clocks = <&rpmhcc RPMH_IPA_CLK>; - clock-names = "core"; - - interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, - <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; - interconnect-names = "memory", - "imem", - "config"; - - qcom,smem-states = <&ipa_smp2p_out 0>, - <&ipa_smp2p_out 1>; - qcom,smem-state-names = "ipa-clock-enabled-valid", - "ipa-clock-enabled"; - - modem-remoteproc = <&mss_pil>; - - status = "disabled"; - }; - - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0 0x01f40000 0 0x40000>; - }; - - tlmm: pinctrl@3400000 { - compatible = "qcom,sdm845-pinctrl"; - reg = <0 0x03400000 0 0xc00000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 151>; - wakeup-parent = <&pdc_intc>; - - cci0_default: cci0-default { - /* SDA, SCL */ - pins = "gpio17", "gpio18"; - function = "cci_i2c"; - - bias-pull-up; - drive-strength = <2>; /* 2 mA */ - }; - - cci0_sleep: cci0-sleep { - /* SDA, SCL */ - pins = "gpio17", "gpio18"; - function = "cci_i2c"; - - drive-strength = <2>; /* 2 mA */ - bias-pull-down; - }; - - cci1_default: cci1-default { - /* SDA, SCL */ - pins = "gpio19", "gpio20"; - function = "cci_i2c"; - - bias-pull-up; - drive-strength = <2>; /* 2 mA */ - }; - - cci1_sleep: cci1-sleep { - /* SDA, SCL */ - pins = "gpio19", "gpio20"; - function = "cci_i2c"; - - drive-strength = <2>; /* 2 mA */ - bias-pull-down; - }; - - qspi_clk: qspi-clk { - pinmux { - pins = "gpio95"; - function = "qspi_clk"; - }; - }; - - qspi_cs0: qspi-cs0 { - pinmux { - pins = "gpio90"; - function = "qspi_cs"; - }; - }; - - qspi_cs1: qspi-cs1 { - pinmux { - pins = "gpio89"; - function = "qspi_cs"; - }; - }; - - qspi_data01: qspi-data01 { - pinmux-data { - pins = "gpio91", "gpio92"; - function = "qspi_data"; - }; - }; - - qspi_data12: qspi-data12 { - pinmux-data { - pins = "gpio93", "gpio94"; - function = "qspi_data"; - }; - }; - - qup_i2c0_default: qup-i2c0-default { - pinmux { - pins = "gpio0", "gpio1"; - function = "qup0"; - }; - }; - - qup_i2c1_default: qup-i2c1-default { - pinmux { - pins = "gpio17", "gpio18"; - function = "qup1"; - }; - }; - - qup_i2c2_default: qup-i2c2-default { - pinmux { - pins = "gpio27", "gpio28"; - function = "qup2"; - }; - }; - - qup_i2c3_default: qup-i2c3-default { - pinmux { - pins = "gpio41", "gpio42"; - function = "qup3"; - }; - }; - - qup_i2c4_default: qup-i2c4-default { - pinmux { - pins = "gpio89", "gpio90"; - function = "qup4"; - }; - }; - - qup_i2c5_default: qup-i2c5-default { - pinmux { - pins = "gpio85", "gpio86"; - function = "qup5"; - }; - }; - - qup_i2c6_default: qup-i2c6-default { - pinmux { - pins = "gpio45", "gpio46"; - function = "qup6"; - }; - }; - - qup_i2c7_default: qup-i2c7-default { - pinmux { - pins = "gpio93", "gpio94"; - function = "qup7"; - }; - }; - - qup_i2c8_default: qup-i2c8-default { - pinmux { - pins = "gpio65", "gpio66"; - function = "qup8"; - }; - }; - - qup_i2c9_default: qup-i2c9-default { - pinmux { - pins = "gpio6", "gpio7"; - function = "qup9"; - }; - }; - - qup_i2c10_default: qup-i2c10-default { - pinmux { - pins = "gpio55", "gpio56"; - function = "qup10"; - }; - }; - - qup_i2c11_default: qup-i2c11-default { - pinmux { - pins = "gpio31", "gpio32"; - function = "qup11"; - }; - }; - - qup_i2c12_default: qup-i2c12-default { - pinmux { - pins = "gpio49", "gpio50"; - function = "qup12"; - }; - }; - - qup_i2c13_default: qup-i2c13-default { - pinmux { - pins = "gpio105", "gpio106"; - function = "qup13"; - }; - }; - - qup_i2c14_default: qup-i2c14-default { - pinmux { - pins = "gpio33", "gpio34"; - function = "qup14"; - }; - }; - - qup_i2c15_default: qup-i2c15-default { - pinmux { - pins = "gpio81", "gpio82"; - function = "qup15"; - }; - }; - - qup_spi0_default: qup-spi0-default { - pinmux { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - function = "qup0"; - }; - }; - - qup_spi1_default: qup-spi1-default { - pinmux { - pins = "gpio17", "gpio18", - "gpio19", "gpio20"; - function = "qup1"; - }; - }; - - qup_spi2_default: qup-spi2-default { - pinmux { - pins = "gpio27", "gpio28", - "gpio29", "gpio30"; - function = "qup2"; - }; - }; - - qup_spi3_default: qup-spi3-default { - pinmux { - pins = "gpio41", "gpio42", - "gpio43", "gpio44"; - function = "qup3"; - }; - }; - - qup_spi4_default: qup-spi4-default { - pinmux { - pins = "gpio89", "gpio90", - "gpio91", "gpio92"; - function = "qup4"; - }; - }; - - qup_spi5_default: qup-spi5-default { - pinmux { - pins = "gpio85", "gpio86", - "gpio87", "gpio88"; - function = "qup5"; - }; - }; - - qup_spi6_default: qup-spi6-default { - pinmux { - pins = "gpio45", "gpio46", - "gpio47", "gpio48"; - function = "qup6"; - }; - }; - - qup_spi7_default: qup-spi7-default { - pinmux { - pins = "gpio93", "gpio94", - "gpio95", "gpio96"; - function = "qup7"; - }; - }; - - qup_spi8_default: qup-spi8-default { - pinmux { - pins = "gpio65", "gpio66", - "gpio67", "gpio68"; - function = "qup8"; - }; - }; - - qup_spi9_default: qup-spi9-default { - pinmux { - pins = "gpio6", "gpio7", - "gpio4", "gpio5"; - function = "qup9"; - }; - }; - - qup_spi10_default: qup-spi10-default { - pinmux { - pins = "gpio55", "gpio56", - "gpio53", "gpio54"; - function = "qup10"; - }; - }; - - qup_spi11_default: qup-spi11-default { - pinmux { - pins = "gpio31", "gpio32", - "gpio33", "gpio34"; - function = "qup11"; - }; - }; - - qup_spi12_default: qup-spi12-default { - pinmux { - pins = "gpio49", "gpio50", - "gpio51", "gpio52"; - function = "qup12"; - }; - }; - - qup_spi13_default: qup-spi13-default { - pinmux { - pins = "gpio105", "gpio106", - "gpio107", "gpio108"; - function = "qup13"; - }; - }; - - qup_spi14_default: qup-spi14-default { - pinmux { - pins = "gpio33", "gpio34", - "gpio31", "gpio32"; - function = "qup14"; - }; - }; - - qup_spi15_default: qup-spi15-default { - pinmux { - pins = "gpio81", "gpio82", - "gpio83", "gpio84"; - function = "qup15"; - }; - }; - - qup_uart0_default: qup-uart0-default { - pinmux { - pins = "gpio2", "gpio3"; - function = "qup0"; - }; - }; - - qup_uart1_default: qup-uart1-default { - pinmux { - pins = "gpio19", "gpio20"; - function = "qup1"; - }; - }; - - qup_uart2_default: qup-uart2-default { - pinmux { - pins = "gpio29", "gpio30"; - function = "qup2"; - }; - }; - - qup_uart3_default: qup-uart3-default { - pinmux { - pins = "gpio43", "gpio44"; - function = "qup3"; - }; - }; - - qup_uart4_default: qup-uart4-default { - pinmux { - pins = "gpio91", "gpio92"; - function = "qup4"; - }; - }; - - qup_uart5_default: qup-uart5-default { - pinmux { - pins = "gpio87", "gpio88"; - function = "qup5"; - }; - }; - - qup_uart6_default: qup-uart6-default { - pinmux { - pins = "gpio47", "gpio48"; - function = "qup6"; - }; - }; - - qup_uart7_default: qup-uart7-default { - pinmux { - pins = "gpio95", "gpio96"; - function = "qup7"; - }; - }; - - qup_uart8_default: qup-uart8-default { - pinmux { - pins = "gpio67", "gpio68"; - function = "qup8"; - }; - }; - - qup_uart9_default: qup-uart9-default { - pinmux { - pins = "gpio4", "gpio5"; - function = "qup9"; - }; - }; - - qup_uart10_default: qup-uart10-default { - pinmux { - pins = "gpio53", "gpio54"; - function = "qup10"; - }; - }; - - qup_uart11_default: qup-uart11-default { - pinmux { - pins = "gpio33", "gpio34"; - function = "qup11"; - }; - }; - - qup_uart12_default: qup-uart12-default { - pinmux { - pins = "gpio51", "gpio52"; - function = "qup12"; - }; - }; - - qup_uart13_default: qup-uart13-default { - pinmux { - pins = "gpio107", "gpio108"; - function = "qup13"; - }; - }; - - qup_uart14_default: qup-uart14-default { - pinmux { - pins = "gpio31", "gpio32"; - function = "qup14"; - }; - }; - - qup_uart15_default: qup-uart15-default { - pinmux { - pins = "gpio83", "gpio84"; - function = "qup15"; - }; - }; - - quat_mi2s_sleep: quat_mi2s_sleep { - mux { - pins = "gpio58", "gpio59"; - function = "gpio"; - }; - - config { - pins = "gpio58", "gpio59"; - drive-strength = <2>; - bias-pull-down; - input-enable; - }; - }; - - quat_mi2s_active: quat_mi2s_active { - mux { - pins = "gpio58", "gpio59"; - function = "qua_mi2s"; - }; - - config { - pins = "gpio58", "gpio59"; - drive-strength = <8>; - bias-disable; - output-high; - }; - }; - - quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { - mux { - pins = "gpio60"; - function = "gpio"; - }; - - config { - pins = "gpio60"; - drive-strength = <2>; - bias-pull-down; - input-enable; - }; - }; - - quat_mi2s_sd0_active: quat_mi2s_sd0_active { - mux { - pins = "gpio60"; - function = "qua_mi2s"; - }; - - config { - pins = "gpio60"; - drive-strength = <8>; - bias-disable; - }; - }; - - quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { - mux { - pins = "gpio61"; - function = "gpio"; - }; - - config { - pins = "gpio61"; - drive-strength = <2>; - bias-pull-down; - input-enable; - }; - }; - - quat_mi2s_sd1_active: quat_mi2s_sd1_active { - mux { - pins = "gpio61"; - function = "qua_mi2s"; - }; - - config { - pins = "gpio61"; - drive-strength = <8>; - bias-disable; - }; - }; - - quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { - mux { - pins = "gpio62"; - function = "gpio"; - }; - - config { - pins = "gpio62"; - drive-strength = <2>; - bias-pull-down; - input-enable; - }; - }; - - quat_mi2s_sd2_active: quat_mi2s_sd2_active { - mux { - pins = "gpio62"; - function = "qua_mi2s"; - }; - - config { - pins = "gpio62"; - drive-strength = <8>; - bias-disable; - }; - }; - - quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { - mux { - pins = "gpio63"; - function = "gpio"; - }; - - config { - pins = "gpio63"; - drive-strength = <2>; - bias-pull-down; - input-enable; - }; - }; - - quat_mi2s_sd3_active: quat_mi2s_sd3_active { - mux { - pins = "gpio63"; - function = "qua_mi2s"; - }; - - config { - pins = "gpio63"; - drive-strength = <8>; - bias-disable; - }; - }; - }; - - mss_pil: remoteproc@4080000 { - compatible = "qcom,sdm845-mss-pil"; - reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; - reg-names = "qdsp6", "rmb"; - - interrupts-extended = - <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack", - "shutdown-ack"; - - clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, - <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, - <&gcc GCC_BOOT_ROM_AHB_CLK>, - <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, - <&gcc GCC_MSS_SNOC_AXI_CLK>, - <&gcc GCC_MSS_MFAB_AXIS_CLK>, - <&gcc GCC_PRNG_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "bus", "mem", "gpll0_mss", - "snoc_axi", "mnoc_axi", "prng", "xo"; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - resets = <&aoss_reset AOSS_CC_MSS_RESTART>, - <&pdc_reset PDC_MODEM_SYNC_RESET>; - reset-names = "mss_restart", "pdc_reset"; - - qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; - - power-domains = <&aoss_qmp 2>, - <&rpmhpd SDM845_CX>, - <&rpmhpd SDM845_MX>, - <&rpmhpd SDM845_MSS>; - power-domain-names = "load_state", "cx", "mx", "mss"; - - mba { - memory-region = <&mba_region>; - }; - - mpss { - memory-region = <&mpss_region>; - }; - - glink-edge { - interrupts = ; - label = "modem"; - qcom,remote-pid = <1>; - mboxes = <&apss_shared 12>; - }; - }; - - gpucc: clock-controller@5090000 { - compatible = "qcom,sdm845-gpucc"; - reg = <0 0x05090000 0 0x9000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_GPU_GPLL0_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; - clock-names = "bi_tcxo", - "gcc_gpu_gpll0_clk_src", - "gcc_gpu_gpll0_div_clk_src"; - }; - - stm@6002000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0 0x06002000 0 0x1000>, - <0 0x16280000 0 0x180000>; - reg-names = "stm-base", "stm-stimulus-base"; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - stm_out: endpoint { - remote-endpoint = - <&funnel0_in7>; - }; - }; - }; - }; - - funnel@6041000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06041000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel0_out: endpoint { - remote-endpoint = - <&merge_funnel_in0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@7 { - reg = <7>; - funnel0_in7: endpoint { - remote-endpoint = <&stm_out>; - }; - }; - }; - }; - - funnel@6043000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06043000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel2_out: endpoint { - remote-endpoint = - <&merge_funnel_in2>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@5 { - reg = <5>; - funnel2_in5: endpoint { - remote-endpoint = - <&apss_merge_funnel_out>; - }; - }; - }; - }; - - funnel@6045000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x06045000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - merge_funnel_out: endpoint { - remote-endpoint = <&etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - merge_funnel_in0: endpoint { - remote-endpoint = - <&funnel0_out>; - }; - }; - - port@2 { - reg = <2>; - merge_funnel_in2: endpoint { - remote-endpoint = - <&funnel2_out>; - }; - }; - }; - }; - - replicator@6046000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0 0x06046000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - replicator_out: endpoint { - remote-endpoint = <&etr_in>; - }; - }; - }; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = <&etf_out>; - }; - }; - }; - }; - - etf@6047000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06047000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - etf_out: endpoint { - remote-endpoint = - <&replicator_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - etf_in: endpoint { - remote-endpoint = - <&merge_funnel_out>; - }; - }; - }; - }; - - etr@6048000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x06048000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,scatter-gather; - - in-ports { - port { - etr_in: endpoint { - remote-endpoint = - <&replicator_out>; - }; - }; - }; - }; - - etm@7040000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07040000 0 0x1000>; - - cpu = <&CPU0>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = - <&apss_funnel_in0>; - }; - }; - }; - }; - - etm@7140000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07140000 0 0x1000>; - - cpu = <&CPU1>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = - <&apss_funnel_in1>; - }; - }; - }; - }; - - etm@7240000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07240000 0 0x1000>; - - cpu = <&CPU2>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = - <&apss_funnel_in2>; - }; - }; - }; - }; - - etm@7340000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07340000 0 0x1000>; - - cpu = <&CPU3>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = - <&apss_funnel_in3>; - }; - }; - }; - }; - - etm@7440000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07440000 0 0x1000>; - - cpu = <&CPU4>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - - out-ports { - port { - etm4_out: endpoint { - remote-endpoint = - <&apss_funnel_in4>; - }; - }; - }; - }; - - etm@7540000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07540000 0 0x1000>; - - cpu = <&CPU5>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - - out-ports { - port { - etm5_out: endpoint { - remote-endpoint = - <&apss_funnel_in5>; - }; - }; - }; - }; - - etm@7640000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07640000 0 0x1000>; - - cpu = <&CPU6>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - - out-ports { - port { - etm6_out: endpoint { - remote-endpoint = - <&apss_funnel_in6>; - }; - }; - }; - }; - - etm@7740000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x07740000 0 0x1000>; - - cpu = <&CPU7>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - arm,coresight-loses-context-with-cpu; - - out-ports { - port { - etm7_out: endpoint { - remote-endpoint = - <&apss_funnel_in7>; - }; - }; - }; - }; - - funnel@7800000 { /* APSS Funnel */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x07800000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - apss_funnel_out: endpoint { - remote-endpoint = - <&apss_merge_funnel_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - apss_funnel_in0: endpoint { - remote-endpoint = - <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - apss_funnel_in1: endpoint { - remote-endpoint = - <&etm1_out>; - }; - }; - - port@2 { - reg = <2>; - apss_funnel_in2: endpoint { - remote-endpoint = - <&etm2_out>; - }; - }; - - port@3 { - reg = <3>; - apss_funnel_in3: endpoint { - remote-endpoint = - <&etm3_out>; - }; - }; - - port@4 { - reg = <4>; - apss_funnel_in4: endpoint { - remote-endpoint = - <&etm4_out>; - }; - }; - - port@5 { - reg = <5>; - apss_funnel_in5: endpoint { - remote-endpoint = - <&etm5_out>; - }; - }; - - port@6 { - reg = <6>; - apss_funnel_in6: endpoint { - remote-endpoint = - <&etm6_out>; - }; - }; - - port@7 { - reg = <7>; - apss_funnel_in7: endpoint { - remote-endpoint = - <&etm7_out>; - }; - }; - }; - }; - - funnel@7810000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x07810000 0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - apss_merge_funnel_out: endpoint { - remote-endpoint = - <&funnel2_in5>; - }; - }; - }; - - in-ports { - port { - apss_merge_funnel_in: endpoint { - remote-endpoint = - <&apss_funnel_out>; - }; - }; - }; - }; - - sdhc_2: sdhci@8804000 { - compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; - reg = <0 0x08804000 0 0x1000>; - - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - - clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>; - clock-names = "iface", "core"; - iommus = <&apps_smmu 0xa0 0xf>; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&sdhc2_opp_table>; - - status = "disabled"; - - sdhc2_opp_table: sdhc2-opp-table { - compatible = "operating-points-v2"; - - opp-9600000 { - opp-hz = /bits/ 64 <9600000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-201500000 { - opp-hz = /bits/ 64 <201500000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - }; - }; - - qspi_opp_table: qspi-opp-table { - compatible = "operating-points-v2"; - - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-150000000 { - opp-hz = /bits/ 64 <150000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - - qspi: spi@88df000 { - compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; - reg = <0 0x088df000 0 0x600>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, - <&gcc GCC_QSPI_CORE_CLK>; - clock-names = "iface", "core"; - power-domains = <&rpmhpd SDM845_CX>; - operating-points-v2 = <&qspi_opp_table>; - status = "disabled"; - }; - - slim: slim@171c0000 { - compatible = "qcom,slim-ngd-v2.1.0"; - reg = <0 0x171c0000 0 0x2c000>; - interrupts = ; - - qcom,apps-ch-pipes = <0x780000>; - qcom,ea-pc = <0x270>; - status = "okay"; - dmas = <&slimbam 3>, <&slimbam 4>, - <&slimbam 5>, <&slimbam 6>; - dma-names = "rx", "tx", "tx2", "rx2"; - - iommus = <&apps_smmu 0x1806 0x0>; - #address-cells = <1>; - #size-cells = <0>; - - ngd@1 { - reg = <1>; - #address-cells = <2>; - #size-cells = <0>; - - wcd9340_ifd: ifd@0{ - compatible = "slim217,250"; - reg = <0 0>; - }; - - wcd9340: codec@1{ - compatible = "slim217,250"; - reg = <1 0>; - slim-ifc-dev = <&wcd9340_ifd>; - - #sound-dai-cells = <1>; - - interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <1>; - - #clock-cells = <0>; - clock-frequency = <9600000>; - clock-output-names = "mclk"; - qcom,micbias1-microvolt = <1800000>; - qcom,micbias2-microvolt = <1800000>; - qcom,micbias3-microvolt = <1800000>; - qcom,micbias4-microvolt = <1800000>; - - #address-cells = <1>; - #size-cells = <1>; - - wcdgpio: gpio-controller@42 { - compatible = "qcom,wcd9340-gpio"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x42 0x2>; - }; - - swm: swm@c85 { - compatible = "qcom,soundwire-v1.3.0"; - reg = <0xc85 0x40>; - interrupts-extended = <&wcd9340 20>; - - qcom,dout-ports = <6>; - qcom,din-ports = <2>; - qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>; - qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >; - qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>; - - #sound-dai-cells = <1>; - clocks = <&wcd9340>; - clock-names = "iface"; - #address-cells = <2>; - #size-cells = <0>; - - - }; - }; - }; - }; - - sound: sound { - }; - - usb_1_hsphy: phy@88e2000 { - compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; - reg = <0 0x088e2000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "cfg_ahb", "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - - nvmem-cells = <&qusb2p_hstx_trim>; - }; - - usb_2_hsphy: phy@88e3000 { - compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; - reg = <0 0x088e3000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "cfg_ahb", "ref"; - - resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; - - nvmem-cells = <&qusb2s_hstx_trim>; - }; - - usb_1_qmpphy: phy@88e9000 { - compatible = "qcom,sdm845-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x18c>, - <0 0x088e8000 0 0x10>; - reg-names = "reg-base", "dp_com"; - status = "disabled"; - #clock-cells = <1>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_USB3_PRIM_CLKREF_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "com_aux"; - - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; - reset-names = "phy", "common"; - - usb_1_ssphy: lanes@88e9200 { - reg = <0 0x088e9200 0 0x128>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x218>, - <0 0x088e9600 0 0x128>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; - }; - - usb_2_qmpphy: phy@88eb000 { - compatible = "qcom,sdm845-qmp-usb3-uni-phy"; - reg = <0 0x088eb000 0 0x18c>; - status = "disabled"; - #clock-cells = <1>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_CLK>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "com_aux"; - - resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, - <&gcc GCC_USB3_PHY_SEC_BCR>; - reset-names = "phy", "common"; - - usb_2_ssphy: lane@88eb200 { - reg = <0 0x088eb200 0 0x128>, - <0 0x088eb400 0 0x1fc>, - <0 0x088eb800 0 0x218>, - <0 0x088eb600 0 0x70>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_uni_phy_pipe_clk_src"; - }; - }; - - usb_1: usb@a6f8800 { - compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <150000000>; - - interrupts = , - , - , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_PRIM_GDSC>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; - interconnect-names = "usb-ddr", "apps-usb"; - - usb_1_dwc3: dwc3@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x740 0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - usb_2: usb@a8f8800 { - compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; - reg = <0 0x0a8f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_SLEEP_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep"; - - assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>; - assigned-clock-rates = <19200000>, <150000000>; - - interrupts = , - , - , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_SEC_GDSC>; - - resets = <&gcc GCC_USB30_SEC_BCR>; - - interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, - <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; - interconnect-names = "usb-ddr", "apps-usb"; - - usb_2_dwc3: dwc3@a800000 { - compatible = "snps,dwc3"; - reg = <0 0x0a800000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x760 0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_2_hsphy>, <&usb_2_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - venus: video-codec@aa00000 { - compatible = "qcom,sdm845-venus-v2"; - reg = <0 0x0aa00000 0 0xff000>; - interrupts = ; - power-domains = <&videocc VENUS_GDSC>, - <&videocc VCODEC0_GDSC>, - <&videocc VCODEC1_GDSC>, - <&rpmhpd SDM845_CX>; - power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; - operating-points-v2 = <&venus_opp_table>; - clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, - <&videocc VIDEO_CC_VENUS_AHB_CLK>, - <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, - <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, - <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, - <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, - <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; - clock-names = "core", "iface", "bus", - "vcodec0_core", "vcodec0_bus", - "vcodec1_core", "vcodec1_bus"; - iommus = <&apps_smmu 0x10a0 0x8>, - <&apps_smmu 0x10b0 0x0>; - memory-region = <&venus_mem>; - - video-core0 { - compatible = "venus-decoder"; - }; - - video-core1 { - compatible = "venus-encoder"; - }; - - venus_opp_table: venus-opp-table { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-320000000 { - opp-hz = /bits/ 64 <320000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-380000000 { - opp-hz = /bits/ 64 <380000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-444000000 { - opp-hz = /bits/ 64 <444000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - - opp-533000097 { - opp-hz = /bits/ 64 <533000097>; - required-opps = <&rpmhpd_opp_turbo>; - }; - }; - }; - - videocc: clock-controller@ab00000 { - compatible = "qcom,sdm845-videocc"; - reg = <0 0x0ab00000 0 0x10000>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "bi_tcxo"; - #clock-cells = <1>; - #power-domain-cells = <1>; - #reset-cells = <1>; - }; - - cci: cci@ac4a000 { - compatible = "qcom,sdm845-cci"; - #address-cells = <1>; - #size-cells = <0>; - - reg = <0 0x0ac4a000 0 0x4000>; - interrupts = ; - power-domains = <&clock_camcc TITAN_TOP_GDSC>; - - clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, - <&clock_camcc CAM_CC_SOC_AHB_CLK>, - <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, - <&clock_camcc CAM_CC_CPAS_AHB_CLK>, - <&clock_camcc CAM_CC_CCI_CLK>, - <&clock_camcc CAM_CC_CCI_CLK_SRC>; - clock-names = "camnoc_axi", - "soc_ahb", - "slow_ahb_src", - "cpas_ahb", - "cci", - "cci_src"; - - assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, - <&clock_camcc CAM_CC_CCI_CLK>; - assigned-clock-rates = <80000000>, <37500000>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cci0_default &cci1_default>; - pinctrl-1 = <&cci0_sleep &cci1_sleep>; - - status = "disabled"; - - cci_i2c0: i2c-bus@0 { - reg = <0>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - cci_i2c1: i2c-bus@1 { - reg = <1>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - clock_camcc: clock-controller@ad00000 { - compatible = "qcom,sdm845-camcc"; - reg = <0 0x0ad00000 0 0x10000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - dsi_opp_table: dsi-opp-table { - compatible = "operating-points-v2"; - - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-180000000 { - opp-hz = /bits/ 64 <180000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-275000000 { - opp-hz = /bits/ 64 <275000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-328580000 { - opp-hz = /bits/ 64 <328580000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-358000000 { - opp-hz = /bits/ 64 <358000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - - mdss: mdss@ae00000 { - compatible = "qcom,sdm845-mdss"; - reg = <0 0x0ae00000 0 0x1000>; - reg-names = "mdss"; - - power-domains = <&dispcc MDSS_GDSC>; - - clocks = <&gcc GCC_DISP_AHB_CLK>, - <&gcc GCC_DISP_AXI_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", "bus", "core"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates = <300000000>; - - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - - interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, - <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; - interconnect-names = "mdp0-mem", "mdp1-mem"; - - iommus = <&apps_smmu 0x880 0x8>, - <&apps_smmu 0xc80 0x8>; - - status = "disabled"; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - mdss_mdp: mdp@ae01000 { - compatible = "qcom,sdm845-dpu"; - reg = <0 0x0ae01000 0 0x8f000>, - <0 0x0aeb0000 0 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_AXI_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "iface", "bus", "core", "vsync"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <300000000>, - <19200000>; - operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd SDM845_CX>; - - interrupt-parent = <&mdss>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - - port@1 { - reg = <1>; - dpu_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; - }; - - mdp_opp_table: mdp-opp-table { - compatible = "operating-points-v2"; - - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-171428571 { - opp-hz = /bits/ 64 <171428571>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-344000000 { - opp-hz = /bits/ 64 <344000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-430000000 { - opp-hz = /bits/ 64 <430000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - }; - - dsi0: dsi@ae94000 { - compatible = "qcom,mdss-dsi-ctrl"; - reg = <0 0x0ae94000 0 0x400>; - reg-names = "dsi_ctrl"; - - interrupt-parent = <&mdss>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, - <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK0_CLK>, - <&dispcc DISP_CC_MDSS_ESC0_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_AXI_CLK>; - clock-names = "byte", - "byte_intf", - "pixel", - "core", - "iface", - "bus"; - operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmhpd SDM845_CX>; - - phys = <&dsi0_phy>; - phy-names = "dsi"; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - remote-endpoint = <&dpu_intf1_out>; - }; - }; - - port@1 { - reg = <1>; - dsi0_out: endpoint { - }; - }; - }; - }; - - dsi0_phy: dsi-phy@ae94400 { - compatible = "qcom,dsi-phy-10nm"; - reg = <0 0x0ae94400 0 0x200>, - <0 0x0ae94600 0 0x280>, - <0 0x0ae94a00 0 0x1e0>; - reg-names = "dsi_phy", - "dsi_phy_lane", - "dsi_pll"; - - #clock-cells = <1>; - #phy-cells = <0>; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "ref"; - - status = "disabled"; - }; - - dsi1: dsi@ae96000 { - compatible = "qcom,mdss-dsi-ctrl"; - reg = <0 0x0ae96000 0 0x400>; - reg-names = "dsi_ctrl"; - - interrupt-parent = <&mdss>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, - <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK1_CLK>, - <&dispcc DISP_CC_MDSS_ESC1_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_AXI_CLK>; - clock-names = "byte", - "byte_intf", - "pixel", - "core", - "iface", - "bus"; - operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmhpd SDM845_CX>; - - phys = <&dsi1_phy>; - phy-names = "dsi"; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi1_in: endpoint { - remote-endpoint = <&dpu_intf2_out>; - }; - }; - - port@1 { - reg = <1>; - dsi1_out: endpoint { - }; - }; - }; - }; - - dsi1_phy: dsi-phy@ae96400 { - compatible = "qcom,dsi-phy-10nm"; - reg = <0 0x0ae96400 0 0x200>, - <0 0x0ae96600 0 0x280>, - <0 0x0ae96a00 0 0x10e>; - reg-names = "dsi_phy", - "dsi_phy_lane", - "dsi_pll"; - - #clock-cells = <1>; - #phy-cells = <0>; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "ref"; - - status = "disabled"; - }; - }; - - gpu: gpu@5000000 { - compatible = "qcom,adreno-630.2", "qcom,adreno"; - #stream-id-cells = <16>; - - reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; - reg-names = "kgsl_3d0_reg_memory", "cx_mem"; - - /* - * Look ma, no clocks! The GPU clocks and power are - * controlled entirely by the GMU - */ - - interrupts = ; - - iommus = <&adreno_smmu 0>; - - operating-points-v2 = <&gpu_opp_table>; - - qcom,gmu = <&gmu>; - - interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; - interconnect-names = "gfx-mem"; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-710000000 { - opp-hz = /bits/ 64 <710000000>; - opp-level = ; - opp-peak-kBps = <7216000>; - }; - - opp-675000000 { - opp-hz = /bits/ 64 <675000000>; - opp-level = ; - opp-peak-kBps = <7216000>; - }; - - opp-596000000 { - opp-hz = /bits/ 64 <596000000>; - opp-level = ; - opp-peak-kBps = <6220000>; - }; - - opp-520000000 { - opp-hz = /bits/ 64 <520000000>; - opp-level = ; - opp-peak-kBps = <6220000>; - }; - - opp-414000000 { - opp-hz = /bits/ 64 <414000000>; - opp-level = ; - opp-peak-kBps = <4068000>; - }; - - opp-342000000 { - opp-hz = /bits/ 64 <342000000>; - opp-level = ; - opp-peak-kBps = <2724000>; - }; - - opp-257000000 { - opp-hz = /bits/ 64 <257000000>; - opp-level = ; - opp-peak-kBps = <1648000>; - }; - }; - }; - - adreno_smmu: iommu@5040000 { - compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; - reg = <0 0x5040000 0 0x10000>; - #iommu-cells = <1>; - #global-interrupts = <2>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gcc GCC_GPU_CFG_AHB_CLK>; - clock-names = "bus", "iface"; - - power-domains = <&gpucc GPU_CX_GDSC>; - }; - - gmu: gmu@506a000 { - compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; - - reg = <0 0x506a000 0 0x30000>, - <0 0xb280000 0 0x10000>, - <0 0xb480000 0 0x10000>; - reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; - - interrupts = , - ; - interrupt-names = "hfi", "gmu"; - - clocks = <&gpucc GPU_CC_CX_GMU_CLK>, - <&gpucc GPU_CC_CXO_CLK>, - <&gcc GCC_DDRSS_GPU_AXI_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>; - clock-names = "gmu", "cxo", "axi", "memnoc"; - - power-domains = <&gpucc GPU_CX_GDSC>, - <&gpucc GPU_GX_GDSC>; - power-domain-names = "cx", "gx"; - - iommus = <&adreno_smmu 5>; - - operating-points-v2 = <&gmu_opp_table>; - - gmu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-level = ; - }; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-level = ; - }; - }; - }; - - dispcc: clock-controller@af00000 { - compatible = "qcom,sdm845-dispcc"; - reg = <0 0x0af00000 0 0x10000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_DISP_GPLL0_CLK_SRC>, - <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, - <&dsi0_phy 0>, - <&dsi0_phy 1>, - <&dsi1_phy 0>, - <&dsi1_phy 1>, - <0>, - <0>; - clock-names = "bi_tcxo", - "gcc_disp_gpll0_clk_src", - "gcc_disp_gpll0_div_clk_src", - "dsi0_phy_pll_out_byteclk", - "dsi0_phy_pll_out_dsiclk", - "dsi1_phy_pll_out_byteclk", - "dsi1_phy_pll_out_dsiclk", - "dp_link_clk_divsel_ten", - "dp_vco_divided_clk_src_mux"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - pdc_intc: interrupt-controller@b220000 { - compatible = "qcom,sdm845-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>; - qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - pdc_reset: reset-controller@b2e0000 { - compatible = "qcom,sdm845-pdc-global"; - reg = <0 0x0b2e0000 0 0x20000>; - #reset-cells = <1>; - }; - - tsens0: thermal-sensor@c263000 { - compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1ff>, /* TM */ - <0 0x0c222000 0 0x1ff>; /* SROT */ - #qcom,sensors = <13>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c265000 { - compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1ff>, /* TM */ - <0 0x0c223000 0 0x1ff>; /* SROT */ - #qcom,sensors = <8>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - aoss_reset: reset-controller@c2a0000 { - compatible = "qcom,sdm845-aoss-cc"; - reg = <0 0x0c2a0000 0 0x31000>; - #reset-cells = <1>; - }; - - aoss_qmp: qmp@c300000 { - compatible = "qcom,sdm845-aoss-qmp"; - reg = <0 0x0c300000 0 0x100000>; - interrupts = ; - mboxes = <&apss_shared 0>; - - #clock-cells = <0>; - #power-domain-cells = <1>; - - cx_cdev: cx { - #cooling-cells = <2>; - }; - - ebi_cdev: ebi { - #cooling-cells = <2>; - }; - }; - - spmi_bus: spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0 0x0c440000 0 0x1100>, - <0 0x0c600000 0 0x2000000>, - <0 0x0e600000 0 0x100000>, - <0 0x0e700000 0 0xa0000>, - <0 0x0c40a000 0 0x26000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - imem@146bf000 { - compatible = "simple-mfd"; - reg = <0 0x146bf000 0 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0 0x146bf000 0x1000>; - - pil-reloc@94c { - compatible = "qcom,pil-reloc-info"; - reg = <0x94c 0xc8>; - }; - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; - reg = <0 0x15000000 0 0x80000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - - lpasscc: clock-controller@17014000 { - compatible = "qcom,sdm845-lpasscc"; - reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; - reg-names = "cc", "qdsp6ss"; - #clock-cells = <1>; - status = "disabled"; - }; - - gladiator_noc: interconnect@17900000 { - compatible = "qcom,sdm845-gladiator-noc"; - reg = <0 0x17900000 0 0xd080>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - watchdog@17980000 { - compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; - reg = <0 0x17980000 0 0x1000>; - clocks = <&sleep_clk>; - }; - - apss_shared: mailbox@17990000 { - compatible = "qcom,sdm845-apss-shared"; - reg = <0 0x17990000 0 0x1000>; - #mbox-cells = <1>; - }; - - apps_rsc: rsc@179c0000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0 0x179c0000 0 0x10000>, - <0 0x179d0000 0 0x10000>, - <0 0x179e0000 0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , - , - , - ; - - apps_bcm_voter: bcm-voter { - compatible = "qcom,bcm-voter"; - }; - - rpmhcc: clock-controller { - compatible = "qcom,sdm845-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sdm845-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_nom: opp6 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp8 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp10 { - opp-level = ; - }; - }; - }; - }; - - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0 0x17a00000 0 0x10000>, /* GICD */ - <0 0x17a60000 0 0x100000>; /* GICR * 8 */ - interrupts = ; - - msi-controller@17a40000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0 0x17a40000 0 0x20000>; - status = "disabled"; - }; - }; - - slimbam: dma@17184000 { - compatible = "qcom,bam-v1.7.0"; - qcom,controlled-remotely; - reg = <0 0x17184000 0 0x2a000>; - num-channels = <31>; - interrupts = ; - #dma-cells = <1>; - qcom,ee = <1>; - qcom,num-ees = <2>; - iommus = <&apps_smmu 0x1806 0x0>; - }; - - timer@17c90000 { - #address-cells = <2>; - #size-cells = <2>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0 0x17c90000 0 0x1000>; - - frame@17ca0000 { - frame-number = <0>; - interrupts = , - ; - reg = <0 0x17ca0000 0 0x1000>, - <0 0x17cb0000 0 0x1000>; - }; - - frame@17cc0000 { - frame-number = <1>; - interrupts = ; - reg = <0 0x17cc0000 0 0x1000>; - status = "disabled"; - }; - - frame@17cd0000 { - frame-number = <2>; - interrupts = ; - reg = <0 0x17cd0000 0 0x1000>; - status = "disabled"; - }; - - frame@17ce0000 { - frame-number = <3>; - interrupts = ; - reg = <0 0x17ce0000 0 0x1000>; - status = "disabled"; - }; - - frame@17cf0000 { - frame-number = <4>; - interrupts = ; - reg = <0 0x17cf0000 0 0x1000>; - status = "disabled"; - }; - - frame@17d00000 { - frame-number = <5>; - interrupts = ; - reg = <0 0x17d00000 0 0x1000>; - status = "disabled"; - }; - - frame@17d10000 { - frame-number = <6>; - interrupts = ; - reg = <0 0x17d10000 0 0x1000>; - status = "disabled"; - }; - }; - - osm_l3: interconnect@17d41000 { - compatible = "qcom,sdm845-osm-l3"; - reg = <0 0x17d41000 0 0x1400>; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #interconnect-cells = <1>; - }; - - cpufreq_hw: cpufreq@17d43000 { - compatible = "qcom,cpufreq-hw"; - reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; - reg-names = "freq-domain0", "freq-domain1"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; - - wifi: wifi@18800000 { - compatible = "qcom,wcn3990-wifi"; - status = "disabled"; - reg = <0 0x18800000 0 0x800000>; - reg-names = "membase"; - memory-region = <&wlan_msa_mem>; - clock-names = "cxo_ref_clk_pin"; - clocks = <&rpmhcc RPMH_RF_CLK2>; - interrupts = - , - , - , - , - , - , - , - , - , - , - , - ; - iommus = <&apps_smmu 0x0040 0x1>; - }; - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 1>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 2>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 3>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 4>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 7>; - - trips { - cpu4_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 8>; - - trips { - cpu5_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 9>; - - trips { - cpu6_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 10>; - - trips { - cpu7_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - aoss0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 0>; - - trips { - aoss0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 5>; - - trips { - cluster0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster0_crit: cluster0_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cluster1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 6>; - - trips { - cluster1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster1_crit: cluster1_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - gpu-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 11>; - - trips { - gpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - gpu-thermal-bottom { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 12>; - - trips { - gpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - aoss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 0>; - - trips { - aoss1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-modem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 1>; - - trips { - q6_modem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 2>; - - trips { - mem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - wlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 3>; - - trips { - wlan_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-hvx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 4>; - - trips { - q6_hvx_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 5>; - - trips { - camera_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - video-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 6>; - - trips { - video_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 7>; - - trips { - modem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts deleted file mode 100644 index e080c317b..000000000 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ /dev/null @@ -1,620 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Lenovo Yoga C630 - * - * Copyright (c) 2019, Linaro Ltd. - */ - -/dts-v1/; - -#include -#include -#include -#include -#include "sdm845.dtsi" -#include "pm8998.dtsi" - -/ { - model = "Lenovo Yoga C630"; - compatible = "lenovo,yoga-c630", "qcom,sdm845"; - - aliases { - hsuart0 = &uart6; - }; -}; - -&adsp_pas { - firmware-name = "qcom/LENOVO/81JL/qcadsp850.mbn"; - status = "okay"; -}; - -&apps_rsc { - pm8998-rpmh-regulators { - compatible = "qcom,pm8998-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; - - vreg_s2a_1p125: smps2 { - }; - - vreg_s3a_1p35: smps3 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - regulator-initial-mode = ; - }; - - vreg_s4a_1p8: smps4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_s5a_2p04: smps5 { - regulator-min-microvolt = <2040000>; - regulator-max-microvolt = <2040000>; - regulator-initial-mode = ; - }; - - vreg_s7a_1p025: smps7 { - }; - - vdd_qusb_hs0: - vdda_hp_pcie_core: - vdda_mipi_csi0_0p9: - vdda_mipi_csi1_0p9: - vdda_mipi_csi2_0p9: - vdda_mipi_dsi0_pll: - vdda_mipi_dsi1_pll: - vdda_qlink_lv: - vdda_qlink_lv_ck: - vdda_qrefs_0p875: - vdda_pcie_core: - vdda_pll_cc_ebi01: - vdda_pll_cc_ebi23: - vdda_sp_sensor: - vdda_ufs1_core: - vdda_ufs2_core: - vdda_usb1_ss_core: - vdda_usb2_ss_core: - vreg_l1a_0p875: ldo1 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - - vddpx_10: - vreg_l2a_1p2: ldo2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-always-on; - }; - - vreg_l3a_1p0: ldo3 { - }; - - vdd_wcss_cx: - vdd_wcss_mx: - vdda_wcss_pll: - vreg_l5a_0p8: ldo5 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vddpx_13: - vreg_l6a_1p8: ldo6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l7a_1p8: ldo7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l8a_1p2: ldo8 { - }; - - vreg_l9a_1p8: ldo9 { - }; - - vreg_l10a_1p8: ldo10 { - }; - - vreg_l11a_1p0: ldo11 { - }; - - vdd_qfprom: - vdd_qfprom_sp: - vdda_apc1_cs_1p8: - vdda_gfx_cs_1p8: - vdda_qrefs_1p8: - vdda_qusb_hs0_1p8: - vddpx_11: - vreg_l12a_1p8: ldo12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vddpx_2: - vreg_l13a_2p95: ldo13 { - }; - - vreg_l14a_1p88: ldo14 { - regulator-min-microvolt = <1880000>; - regulator-max-microvolt = <1880000>; - regulator-initial-mode = ; - regulator-always-on; - }; - - vreg_l15a_1p8: ldo15 { - }; - - vreg_l16a_2p7: ldo16 { - }; - - vreg_l17a_1p3: ldo17 { - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l18a_2p7: ldo18 { - }; - - vreg_l19a_3p0: ldo19 { - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3108000>; - regulator-initial-mode = ; - }; - - vreg_l20a_2p95: ldo20 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l21a_2p95: ldo21 { - }; - - vreg_l22a_2p85: ldo22 { - }; - - vreg_l23a_3p3: ldo23 { - }; - - vdda_qusb_hs0_3p1: - vreg_l24a_3p075: ldo24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3083000>; - regulator-initial-mode = ; - }; - - vreg_l25a_3p3: ldo25 { - regulator-min-microvolt = <3104000>; - regulator-max-microvolt = <3112000>; - regulator-initial-mode = ; - }; - - vdda_hp_pcie_1p2: - vdda_hv_ebi0: - vdda_hv_ebi1: - vdda_hv_ebi2: - vdda_hv_ebi3: - vdda_mipi_csi_1p25: - vdda_mipi_dsi0_1p2: - vdda_mipi_dsi1_1p2: - vdda_pcie_1p2: - vdda_ufs1_1p2: - vdda_ufs2_1p2: - vdda_usb1_ss_1p2: - vdda_usb2_ss_1p2: - vreg_l26a_1p2: ldo26 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1208000>; - regulator-initial-mode = ; - }; - - vreg_l28a_3p0: ldo28 { - }; - - vreg_lvs1a_1p8: lvs1 { - }; - - vreg_lvs2a_1p8: lvs2 { - }; - }; -}; - -&apps_smmu { - /* TODO: Figure out how to survive booting with this enabled */ - status = "disabled"; -}; - -&cdsp_pas { - firmware-name = "qcom/LENOVO/81JL/qccdsp850.mbn"; - status = "okay"; -}; - -&gcc { - protected-clocks = , - , - , - , - ; -}; - -&gpu { - zap-shader { - memory-region = <&gpu_mem>; - firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn"; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; -}; - -&i2c3 { - status = "okay"; - clock-frequency = <400000>; - /* Overwrite pinctrl-0 from sdm845.dtsi */ - pinctrl-0 = <&qup_i2c3_default &i2c3_hid_active>; - - tsel: hid@15 { - compatible = "hid-over-i2c"; - reg = <0x15>; - hid-descr-addr = <0x1>; - - interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_HIGH>; - }; - - tsc2: hid@2c { - compatible = "hid-over-i2c"; - reg = <0x2c>; - hid-descr-addr = <0x20>; - - interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&i2c5 { - status = "okay"; - clock-frequency = <400000>; - - tsc1: hid@10 { - compatible = "hid-over-i2c"; - reg = <0x10>; - hid-descr-addr = <0x1>; - - interrupts-extended = <&tlmm 125 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_hid_active>; - }; -}; - -&i2c11 { - status = "okay"; - clock-frequency = <400000>; - - ecsh: hid@5c { - compatible = "hid-over-i2c"; - reg = <0x5c>; - hid-descr-addr = <0x1>; - - interrupts-extended = <&tlmm 92 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c11_hid_active>; - }; -}; - -&mss_pil { - firmware-name = "qcom/LENOVO/81JL/qcdsp1v2850.mbn", "qcom/LENOVO/81JL/qcdsp2850.mbn"; -}; - -&qup_i2c12_default { - drive-strength = <2>; - bias-disable; -}; - -&qup_uart6_default { - pinmux { - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - function = "qup6"; - }; - - cts { - pins = "gpio45"; - bias-pull-down; - }; - - rts-tx { - pins = "gpio46", "gpio47"; - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio48"; - bias-pull-up; - }; -}; - -&qupv3_id_0 { - status = "okay"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&q6asmdai { - dai@0 { - reg = <0>; - }; - - dai@1 { - reg = <1>; - }; - - dai@2 { - reg = <2>; - }; -}; - -&sound { - compatible = "qcom,db845c-sndcard"; - model = "Lenovo-YOGA-C630-13Q50"; - - audio-routing = - "RX_BIAS", "MCLK", - "AMIC2", "MIC BIAS2", - "SpkrLeft IN", "SPK1 OUT", - "SpkrRight IN", "SPK2 OUT", - "MM_DL1", "MultiMedia1 Playback", - "MM_DL3", "MultiMedia3 Playback", - "MultiMedia2 Capture", "MM_UL2"; - - mm1-dai-link { - link-name = "MultiMedia1"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; - }; - }; - - mm2-dai-link { - link-name = "MultiMedia2"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; - }; - }; - - mm3-dai-link { - link-name = "MultiMedia3"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; - }; - }; - - slim-dai-link { - link-name = "SLIM Playback"; - cpu { - sound-dai = <&q6afedai SLIMBUS_0_RX>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; - }; - }; - - slimcap-dai-link { - link-name = "SLIM Capture"; - cpu { - sound-dai = <&q6afedai SLIMBUS_0_TX>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&wcd9340 1>; - }; - }; - - slim-wcd-dai-link { - link-name = "SLIM WCD Playback"; - cpu { - sound-dai = <&q6afedai SLIMBUS_1_RX>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&wcd9340 2>; - }; - }; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; - - i2c3_hid_active: i2c2-hid-active { - pins = "gpio37"; - function = "gpio"; - - input-enable; - bias-pull-up; - drive-strength = <2>; - }; - - i2c5_hid_active: i2c5-hid-active { - pins = "gpio125"; - function = "gpio"; - - input-enable; - bias-pull-up; - drive-strength = <2>; - }; - - i2c11_hid_active: i2c11-hid-active { - pins = "gpio92"; - function = "gpio"; - - input-enable; - bias-pull-up; - drive-strength = <2>; - }; - - wcd_intr_default: wcd_intr_default { - pins = "gpio54"; - function = "gpio"; - - input-enable; - bias-pull-down; - drive-strength = <2>; - }; -}; - -&uart6 { - status = "okay"; - - bluetooth { - compatible = "qcom,wcn3990-bt"; - - vddio-supply = <&vreg_s4a_1p8>; - vddxo-supply = <&vreg_l7a_1p8>; - vddrf-supply = <&vreg_l17a_1p3>; - vddch0-supply = <&vreg_l25a_3p3>; - max-speed = <3200000>; - }; -}; - -&ufs_mem_hc { - status = "okay"; - - reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; - - vcc-supply = <&vreg_l20a_2p95>; - vcc-max-microamp = <600000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vdda_ufs1_core>; - vdda-pll-supply = <&vdda_ufs1_1p2>; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "host"; -}; - -&usb_1_hsphy { - status = "okay"; - - vdd-supply = <&vdda_usb1_ss_core>; - vdda-pll-supply = <&vdda_qusb_hs0_1p8>; - vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = ; - qcom,preemphasis-level = ; - qcom,preemphasis-width = ; -}; - -&usb_1_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vdda_usb1_ss_1p2>; - vdda-pll-supply = <&vdda_usb1_ss_core>; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "host"; -}; - -&usb_2_hsphy { - status = "okay"; - - vdd-supply = <&vdda_usb2_ss_core>; - vdda-pll-supply = <&vdda_qusb_hs0_1p8>; - vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = ; -}; - -&usb_2_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vdda_usb2_ss_1p2>; - vdda-pll-supply = <&vdda_usb2_ss_core>; -}; - -&wcd9340{ - pinctrl-0 = <&wcd_intr_default>; - pinctrl-names = "default"; - clock-names = "extclk"; - clocks = <&rpmhcc RPMH_LN_BB_CLK2>; - reset-gpios = <&tlmm 64 0>; - vdd-buck-supply = <&vreg_s4a_1p8>; - vdd-buck-sido-supply = <&vreg_s4a_1p8>; - vdd-tx-supply = <&vreg_s4a_1p8>; - vdd-rx-supply = <&vreg_s4a_1p8>; - vdd-io-supply = <&vreg_s4a_1p8>; - - swm: swm@c85 { - left_spkr: wsa8810-left{ - compatible = "sdw10217211000"; - reg = <0 3>; - powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; - #thermal-sensor-cells = <0>; - sound-name-prefix = "SpkrLeft"; - #sound-dai-cells = <0>; - }; - - right_spkr: wsa8810-right{ - compatible = "sdw10217211000"; - powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>; - reg = <0 4>; - #thermal-sensor-cells = <0>; - sound-name-prefix = "SpkrRight"; - #sound-dai-cells = <0>; - }; - }; -}; - -&wifi { - status = "okay"; - - vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; - vdd-1.8-xo-supply = <&vreg_l7a_1p8>; - vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; - vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; - - qcom,snoc-host-cap-8bit-quirk; -}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts deleted file mode 100644 index 6c6325c3a..000000000 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts +++ /dev/null @@ -1,431 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2019, Linaro Limited - */ - -/dts-v1/; - -#include -#include -#include "sm8150.dtsi" -#include "pm8150.dtsi" -#include "pm8150b.dtsi" -#include "pm8150l.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. SM8150 MTP"; - compatible = "qcom,sm8150-mtp"; - - aliases { - serial0 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - - /* - * Apparently RPMh does not provide support for PM8150 S4 because it - * is always-on; model it as a fixed regulator. - */ - vreg_s4a_1p8: pm8150-s4 { - compatible = "regulator-fixed"; - regulator-name = "vreg_s4a_1p8"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - - vin-supply = <&vph_pwr>; - }; -}; - -&apps_rsc { - pm8150-rpmh-regulators { - compatible = "qcom,pm8150-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-s8-supply = <&vph_pwr>; - vdd-s9-supply = <&vph_pwr>; - vdd-s10-supply = <&vph_pwr>; - - vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>; - vdd-l2-l10-supply = <&vreg_bob>; - vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p9>; - vdd-l6-l9-supply = <&vreg_s8c_1p3>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p0>; - vdd-l13-l16-l17-supply = <&vreg_bob>; - - vreg_s5a_2p0: smps5 { - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2000000>; - }; - - vreg_s6a_0p9: smps6 { - regulator-min-microvolt = <920000>; - regulator-max-microvolt = <1128000>; - }; - - vdda_wcss_pll: - vreg_l1a_0p75: ldo1 { - regulator-min-microvolt = <752000>; - regulator-max-microvolt = <752000>; - regulator-initial-mode = ; - }; - - vdd_pdphy: - vdda_usb_hs_3p1: - vreg_l2a_3p1: ldo2 { - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l3a_0p8: ldo3 { - regulator-min-microvolt = <480000>; - regulator-max-microvolt = <932000>; - regulator-initial-mode = ; - }; - - vdd_usb_hs_core: - vdda_csi_0_0p9: - vdda_csi_1_0p9: - vdda_csi_2_0p9: - vdda_csi_3_0p9: - vdda_dsi_0_0p9: - vdda_dsi_1_0p9: - vdda_dsi_0_pll_0p9: - vdda_dsi_1_pll_0p9: - vdda_pcie_1ln_core: - vdda_pcie_2ln_core: - vdda_pll_hv_cc_ebi01: - vdda_pll_hv_cc_ebi23: - vdda_qrefs_0p875_5: - vdda_sp_sensor: - vdda_ufs_2ln_core_1: - vdda_ufs_2ln_core_2: - vdda_usb_ss_dp_core_1: - vdda_usb_ss_dp_core_2: - vdda_qlink_lv: - vdda_qlink_lv_ck: - vreg_l5a_0p875: ldo5 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - - vreg_l6a_1p2: ldo6 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l7a_1p8: ldo7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vddpx_10: - vreg_l9a_1p2: ldo9 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l10a_2p5: ldo10 { - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l11a_0p8: ldo11 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vdd_qfprom: - vdd_qfprom_sp: - vdda_apc_cs_1p8: - vdda_gfx_cs_1p8: - vdda_usb_hs_1p8: - vdda_qrefs_vref_1p8: - vddpx_10_a: - vreg_l12a_1p8: ldo12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l13a_2p7: ldo13 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - regulator-initial-mode = ; - }; - - vreg_l14a_1p8: ldo14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1880000>; - regulator-initial-mode = ; - }; - - vreg_l15a_1p7: ldo15 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <1704000>; - regulator-initial-mode = ; - }; - - vreg_l16a_2p7: ldo16 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l17a_3p0: ldo17 { - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - }; - - pm8150l-rpmh-regulators { - compatible = "qcom,pm8150l-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-s8-supply = <&vph_pwr>; - - vdd-l1-l8-supply = <&vreg_s4a_1p8>; - vdd-l2-l3-supply = <&vreg_s8c_1p3>; - vdd-l4-l5-l6-supply = <&vreg_bob>; - vdd-l7-l11-supply = <&vreg_bob>; - vdd-l9-l10-supply = <&vreg_bob>; - - vdd-bob-supply = <&vph_pwr>; - vdd-flash-supply = <&vreg_bob>; - vdd-rgb-supply = <&vreg_bob>; - - vreg_bob: bob { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <4000000>; - regulator-initial-mode = ; - regulator-allow-bypass; - }; - - vreg_s8c_1p3: smps8 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - - vreg_l1c_1p8: ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vdda_wcss_adcdac_1: - vdda_wcss_adcdac_22: - vreg_l2c_1p3: ldo2 { - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vdda_hv_ebi0: - vdda_hv_ebi1: - vdda_hv_ebi2: - vdda_hv_ebi3: - vdda_hv_refgen0: - vdda_qlink_hv_ck: - vreg_l3c_1p2: ldo3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vddpx_5: - vreg_l4c_1p8: ldo4 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vddpx_6: - vreg_l5c_1p8: ldo5 { - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vddpx_2: - vreg_l6c_2p9: ldo6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l7c_3p0: ldo7 { - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <3104000>; - regulator-initial-mode = ; - }; - - vreg_l8c_1p8: ldo8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l9c_2p9: ldo9 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l10c_3p3: ldo10 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vreg_l11c_3p3: ldo11 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - }; - - pm8009-rpmh-regulators { - compatible = "qcom,pm8009-rpmh-regulators"; - qcom,pmic-id = "f"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vreg_bob>; - - vdd-l2-supply = <&vreg_s8c_1p3>; - vdd-l5-l6-supply = <&vreg_bob>; - - vreg_l2f_1p2: ldo2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l5f_2p85: ldo5 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-initial-mode = ; - }; - - vreg_l6f_2p85: ldo6 { - regulator-initial-mode = ; - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <2856000>; - }; - }; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&pon { - pwrkey { - status = "okay"; - }; - - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; -}; - -&remoteproc_adsp { - status = "okay"; -}; - -&remoteproc_cdsp { - status = "okay"; -}; - -&remoteproc_slpi { - status = "okay"; -}; - -&tlmm { - gpio-reserved-ranges = <0 4>, <126 4>; -}; - -&uart2 { - status = "okay"; -}; - -&ufs_mem_hc { - status = "okay"; - - reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; - - vcc-supply = <&vreg_l10a_2p5>; - vcc-max-microamp = <750000>; - vccq-supply = <&vreg_l9a_1p2>; - vccq-max-microamp = <700000>; - vccq2-supply = <&vreg_s4a_1p8>; - vccq2-max-microamp = <750000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vdda_ufs_2ln_core_1>; - vdda-max-microamp = <90200>; - vdda-pll-supply = <&vreg_l3c_1p2>; - vdda-pll-max-microamp = <19000>; -}; - -&usb_1_hsphy { - status = "okay"; - vdda-pll-supply = <&vdd_usb_hs_core>; - vdda33-supply = <&vdda_usb_hs_3p1>; - vdda18-supply = <&vdda_usb_hs_1p8>; -}; - -&usb_1_qmpphy { - status = "okay"; - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "peripheral"; -}; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi deleted file mode 100644 index a8a47378b..000000000 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ /dev/null @@ -1,1998 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2019, Linaro Limited - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - clock-output-names = "xo_board"; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; - clock-output-names = "sleep_clk"; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&L2_100>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x200>; - enable-method = "psci"; - next-level-cache = <&L2_200>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x300>; - enable-method = "psci"; - next-level-cache = <&L2_300>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x400>; - enable-method = "psci"; - next-level-cache = <&L2_400>; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x500>; - enable-method = "psci"; - next-level-cache = <&L2_500>; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x600>; - enable-method = "psci"; - next-level-cache = <&L2_600>; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x700>; - enable-method = "psci"; - next-level-cache = <&L2_700>; - qcom,freq-domain = <&cpufreq_hw 2>; - #cooling-cells = <2>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - }; - - firmware { - scm: scm { - compatible = "qcom,scm-sm8150", "qcom,scm"; - #reset-cells = <1>; - }; - }; - - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x1000>; - #hwlock-cells = <1>; - }; - - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0x0 0x80000000 0x0 0x0>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@85700000 { - reg = <0x0 0x85700000 0x0 0x600000>; - no-map; - }; - - xbl_mem: memory@85d00000 { - reg = <0x0 0x85d00000 0x0 0x140000>; - no-map; - }; - - aop_mem: memory@85f00000 { - reg = <0x0 0x85f00000 0x0 0x20000>; - no-map; - }; - - aop_cmd_db: memory@85f20000 { - compatible = "qcom,cmd-db"; - reg = <0x0 0x85f20000 0x0 0x20000>; - no-map; - }; - - smem_mem: memory@86000000 { - reg = <0x0 0x86000000 0x0 0x200000>; - no-map; - }; - - tz_mem: memory@86200000 { - reg = <0x0 0x86200000 0x0 0x3900000>; - no-map; - }; - - rmtfs_mem: memory@89b00000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x89b00000 0x0 0x200000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - camera_mem: memory@8b700000 { - reg = <0x0 0x8b700000 0x0 0x500000>; - no-map; - }; - - wlan_mem: memory@8bc00000 { - reg = <0x0 0x8bc00000 0x0 0x180000>; - no-map; - }; - - npu_mem: memory@8bd80000 { - reg = <0x0 0x8bd80000 0x0 0x80000>; - no-map; - }; - - adsp_mem: memory@8be00000 { - reg = <0x0 0x8be00000 0x0 0x1a00000>; - no-map; - }; - - mpss_mem: memory@8d800000 { - reg = <0x0 0x8d800000 0x0 0x9600000>; - no-map; - }; - - venus_mem: memory@96e00000 { - reg = <0x0 0x96e00000 0x0 0x500000>; - no-map; - }; - - slpi_mem: memory@97300000 { - reg = <0x0 0x97300000 0x0 0x1400000>; - no-map; - }; - - ipa_fw_mem: memory@98700000 { - reg = <0x0 0x98700000 0x0 0x10000>; - no-map; - }; - - ipa_gsi_mem: memory@98710000 { - reg = <0x0 0x98710000 0x0 0x5000>; - no-map; - }; - - gpu_mem: memory@98715000 { - reg = <0x0 0x98715000 0x0 0x2000>; - no-map; - }; - - spss_mem: memory@98800000 { - reg = <0x0 0x98800000 0x0 0x100000>; - no-map; - }; - - cdsp_mem: memory@98900000 { - reg = <0x0 0x98900000 0x0 0x1400000>; - no-map; - }; - - qseecom_mem: memory@9e400000 { - reg = <0x0 0x9e400000 0x0 0x1400000>; - no-map; - }; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - - interrupts = ; - - mboxes = <&apss_shared 6>; - - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - cdsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - cdsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-lpass { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - - interrupts = ; - - mboxes = <&apss_shared 10>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - adsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - adsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-mpss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - - interrupts = ; - - mboxes = <&apss_shared 14>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - - interrupts = ; - - mboxes = <&apss_shared 26>; - - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - slpi_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - slpi_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc@0 { - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0 0 0 0x10 0>; - dma-ranges = <0 0 0 0 0x10 0>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sm8150"; - reg = <0x0 0x00100000 0x0 0x1f0000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clock-names = "bi_tcxo", - "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>; - }; - - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00ac0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - uart2: serial@a90000 { - compatible = "qcom,geni-debug-uart"; - reg = <0x0 0x00a90000 0x0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - interrupts = ; - status = "disabled"; - }; - }; - - config_noc: interconnect@1500000 { - compatible = "qcom,sm8150-config-noc"; - reg = <0 0x01500000 0 0x7400>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect@1620000 { - compatible = "qcom,sm8150-system-noc"; - reg = <0 0x01620000 0 0x19400>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mc_virt: interconnect@163a000 { - compatible = "qcom,sm8150-mc-virt"; - reg = <0 0x0163a000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre1_noc: interconnect@16e0000 { - compatible = "qcom,sm8150-aggre1-noc"; - reg = <0 0x016e0000 0 0xd080>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect@1700000 { - compatible = "qcom,sm8150-aggre2-noc"; - reg = <0 0x01700000 0 0x20000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - compute_noc: interconnect@1720000 { - compatible = "qcom,sm8150-compute-noc"; - reg = <0 0x01720000 0 0x7000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mmss_noc: interconnect@1740000 { - compatible = "qcom,sm8150-mmss-noc"; - reg = <0 0x01740000 0 0x1c100>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sm8150-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x2500>; - interrupts = ; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - #reset-cells = <1>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - clocks = - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz = - <37500000 300000000>, - <0 0>, - <0 0>, - <37500000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; - - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sm8150-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", - "ref_aux"; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: lanes@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; - #phy-cells = <0>; - }; - }; - - ipa_virt: interconnect@1e00000 { - compatible = "qcom,sm8150-ipa-virt"; - reg = <0 0x01e00000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - tcsr_mutex_regs: syscon@1f40000 { - compatible = "syscon"; - reg = <0x0 0x01f40000 0x0 0x40000>; - }; - - remoteproc_slpi: remoteproc@2400000 { - compatible = "qcom,sm8150-slpi-pas"; - reg = <0x0 0x02400000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, - <&rpmhpd 3>, - <&rpmhpd 2>; - power-domain-names = "load_state", "lcx", "lmx"; - - memory-region = <&slpi_mem>; - - qcom,smem-states = <&slpi_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "dsps"; - qcom,remote-pid = <3>; - mboxes = <&apss_shared 24>; - }; - }; - - gpu: gpu@2c00000 { - /* - * note: the amd,imageon compatible makes it possible - * to use the drm/msm driver without the display node, - * make sure to remove it when display node is added - */ - compatible = "qcom,adreno-640.1", - "qcom,adreno", - "amd,imageon"; - #stream-id-cells = <16>; - - reg = <0 0x02c00000 0 0x40000>; - reg-names = "kgsl_3d0_reg_memory"; - - interrupts = ; - - iommus = <&adreno_smmu 0 0x401>; - - operating-points-v2 = <&gpu_opp_table>; - - qcom,gmu = <&gmu>; - - zap-shader { - memory-region = <&gpu_mem>; - }; - - /* note: downstream checks gpu binning for 675 Mhz */ - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-675000000 { - opp-hz = /bits/ 64 <675000000>; - opp-level = ; - }; - - opp-585000000 { - opp-hz = /bits/ 64 <585000000>; - opp-level = ; - }; - - opp-499200000 { - opp-hz = /bits/ 64 <499200000>; - opp-level = ; - }; - - opp-427000000 { - opp-hz = /bits/ 64 <427000000>; - opp-level = ; - }; - - opp-345000000 { - opp-hz = /bits/ 64 <345000000>; - opp-level = ; - }; - - opp-257000000 { - opp-hz = /bits/ 64 <257000000>; - opp-level = ; - }; - }; - }; - - gmu: gmu@2c6a000 { - compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; - - reg = <0 0x02c6a000 0 0x30000>, - <0 0x0b290000 0 0x10000>, - <0 0x0b490000 0 0x10000>; - reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; - - interrupts = , - ; - interrupt-names = "hfi", "gmu"; - - clocks = <&gpucc GPU_CC_AHB_CLK>, - <&gpucc GPU_CC_CX_GMU_CLK>, - <&gpucc GPU_CC_CXO_CLK>, - <&gcc GCC_DDRSS_GPU_AXI_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>; - clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; - - power-domains = <&gpucc GPU_CX_GDSC>, - <&gpucc GPU_GX_GDSC>; - power-domain-names = "cx", "gx"; - - iommus = <&adreno_smmu 5 0x400>; - - operating-points-v2 = <&gmu_opp_table>; - - gmu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-level = ; - }; - }; - }; - - gpucc: clock-controller@2c90000 { - compatible = "qcom,sm8150-gpucc"; - reg = <0 0x02c90000 0 0x9000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_GPU_GPLL0_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; - clock-names = "bi_tcxo", - "gcc_gpu_gpll0_clk_src", - "gcc_gpu_gpll0_div_clk_src"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - adreno_smmu: iommu@2ca0000 { - compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; - reg = <0 0x02ca0000 0 0x10000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - ; - clocks = <&gpucc GPU_CC_AHB_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; - clock-names = "ahb", "bus", "iface"; - - power-domains = <&gpucc GPU_CX_GDSC>; - }; - - tlmm: pinctrl@3100000 { - compatible = "qcom,sm8150-pinctrl"; - reg = <0x0 0x03100000 0x0 0x300000>, - <0x0 0x03500000 0x0 0x300000>, - <0x0 0x03900000 0x0 0x300000>, - <0x0 0x03D00000 0x0 0x300000>; - reg-names = "west", "east", "north", "south"; - interrupts = ; - gpio-ranges = <&tlmm 0 0 176>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - remoteproc_mpss: remoteproc@4080000 { - compatible = "qcom,sm8150-mpss-pas"; - reg = <0x0 0x04080000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", - "stop-ack", "shutdown-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, - <&rpmhpd 7>, - <&rpmhpd 0>; - power-domain-names = "load_state", "cx", "mss"; - - memory-region = <&mpss_mem>; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - glink-edge { - interrupts = ; - label = "modem"; - qcom,remote-pid = <1>; - mboxes = <&apss_shared 12>; - }; - }; - - remoteproc_cdsp: remoteproc@8300000 { - compatible = "qcom,sm8150-cdsp-pas"; - reg = <0x0 0x08300000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, - <&rpmhpd 7>; - power-domain-names = "load_state", "cx"; - - memory-region = <&cdsp_mem>; - - qcom,smem-states = <&cdsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "cdsp"; - qcom,remote-pid = <5>; - mboxes = <&apss_shared 4>; - }; - }; - - usb_1_hsphy: phy@88e2000 { - compatible = "qcom,sm8150-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e2000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - }; - - usb_1_qmpphy: phy@88e9000 { - compatible = "qcom,sm8150-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x18c>, - <0 0x088e8000 0 0x10>; - reg-names = "reg-base", "dp_com"; - status = "disabled"; - #clock-cells = <1>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_CLKREF_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; - - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; - reset-names = "phy", "common"; - - usb_1_ssphy: lanes@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x218>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; - }; - - dc_noc: interconnect@9160000 { - compatible = "qcom,sm8150-dc-noc"; - reg = <0 0x09160000 0 0x3200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - gem_noc: interconnect@9680000 { - compatible = "qcom,sm8150-gem-noc"; - reg = <0 0x09680000 0 0x3e200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - usb_1: usb@a6f8800 { - compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_CLK>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep", "xo"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts = , - , - , - ; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_PRIM_GDSC>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - usb_1_dwc3: dwc3@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; - interrupts = ; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - camnoc_virt: interconnect@ac00000 { - compatible = "qcom,sm8150-camnoc-virt"; - reg = <0 0x0ac00000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aoss_qmp: power-controller@c300000 { - compatible = "qcom,sm8150-aoss-qmp"; - reg = <0x0 0x0c300000 0x0 0x100000>; - interrupts = ; - mboxes = <&apss_shared 0>; - - #clock-cells = <0>; - #power-domain-cells = <1>; - }; - - tsens0: thermal-sensor@c263000 { - compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1ff>, /* TM */ - <0 0x0c222000 0 0x1ff>; /* SROT */ - #qcom,sensors = <16>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c265000 { - compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1ff>, /* TM */ - <0 0x0c223000 0 0x1ff>; /* SROT */ - #qcom,sensors = <8>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - spmi_bus: spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0 0x0c440000 0x0 0x0001100>, - <0x0 0x0c600000 0x0 0x2000000>, - <0x0 0x0e600000 0x0 0x0100000>, - <0x0 0x0e700000 0x0 0x00a0000>, - <0x0 0x0c40a000 0x0 0x0026000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - remoteproc_adsp: remoteproc@17300000 { - compatible = "qcom,sm8150-adsp-pas"; - reg = <0x0 0x17300000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, - <&rpmhpd 7>; - power-domain-names = "load_state", "cx"; - - memory-region = <&adsp_mem>; - - qcom,smem-states = <&adsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - label = "lpass"; - qcom,remote-pid = <2>; - mboxes = <&apss_shared 8>; - }; - }; - - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ - <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ - interrupts = ; - }; - - apss_shared: mailbox@17c00000 { - compatible = "qcom,sm8150-apss-shared"; - reg = <0x0 0x17c00000 0x0 0x1000>; - #mbox-cells = <1>; - }; - - watchdog@17c10000 { - compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; - reg = <0 0x17c10000 0 0x1000>; - clocks = <&sleep_clk>; - }; - - timer@17c20000 { - #address-cells = <2>; - #size-cells = <2>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x17c20000 0x0 0x1000>; - clock-frequency = <19200000>; - - frame@17c21000{ - frame-number = <0>; - interrupts = , - ; - reg = <0x0 0x17c21000 0x0 0x1000>, - <0x0 0x17c22000 0x0 0x1000>; - }; - - frame@17c23000 { - frame-number = <1>; - interrupts = ; - reg = <0x0 0x17c23000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c25000 { - frame-number = <2>; - interrupts = ; - reg = <0x0 0x17c25000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c27000 { - frame-number = <3>; - interrupts = ; - reg = <0x0 0x17c26000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c29000 { - frame-number = <4>; - interrupts = ; - reg = <0x0 0x17c29000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c2b000 { - frame-number = <5>; - interrupts = ; - reg = <0x0 0x17c2b000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c2d000 { - frame-number = <6>; - interrupts = ; - reg = <0x0 0x17c2d000 0x0 0x1000>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@18200000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x18200000 0x0 0x10000>, - <0x0 0x18210000 0x0 0x10000>, - <0x0 0x18220000 0x0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , - , - , - ; - - rpmhcc: clock-controller { - compatible = "qcom,sm8150-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sm8150-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_svs_l2: opp6 { - opp-level = <224>; - }; - - rpmhpd_opp_nom: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp8 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp10 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp11 { - opp-level = ; - }; - }; - }; - - apps_bcm_voter: bcm_voter { - compatible = "qcom,bcm-voter"; - }; - }; - - osm_l3: interconnect@18321000 { - compatible = "qcom,sm8150-osm-l3"; - reg = <0 0x18321000 0 0x1400>; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #interconnect-cells = <1>; - }; - - cpufreq_hw: cpufreq@18323000 { - compatible = "qcom,cpufreq-hw"; - reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, - <0 0x18327800 0 0x1400>; - reg-names = "freq-domain0", "freq-domain1", - "freq-domain2"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 1>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 2>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 3>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 4>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 7>; - - trips { - cpu4_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 8>; - - trips { - cpu5_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 9>; - - trips { - cpu6_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 10>; - - trips { - cpu7_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 11>; - - trips { - cpu4_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 12>; - - trips { - cpu5_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 13>; - - trips { - cpu6_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 14>; - - trips { - cpu7_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - aoss0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 0>; - - trips { - aoss0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 5>; - - trips { - cluster0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster0_crit: cluster0_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cluster1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 6>; - - trips { - cluster1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster1_crit: cluster1_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - gpu-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 15>; - - trips { - gpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - aoss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 0>; - - trips { - aoss1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - wlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 1>; - - trips { - wlan_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - video-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 2>; - - trips { - video_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 3>; - - trips { - mem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-hvx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 4>; - - trips { - q6_hvx_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 5>; - - trips { - camera_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - compute-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 6>; - - trips { - compute_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 7>; - - trips { - modem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - npu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 8>; - - trips { - npu_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-vec-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 9>; - - trips { - modem_vec_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - modem-scl-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 10>; - - trips { - modem_scl_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - gpu-thermal-bottom { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 11>; - - trips { - gpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts deleted file mode 100644 index 98675e1f8..000000000 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ /dev/null @@ -1,424 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -/dts-v1/; - -#include -#include "sm8250.dtsi" -#include "pm8150.dtsi" -#include "pm8150b.dtsi" -#include "pm8150l.dtsi" -#include "pm8009.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. SM8250 MTP"; - compatible = "qcom,sm8250-mtp", "qcom,sm8250"; - - aliases { - serial0 = &uart12; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - - vreg_s4a_1p8: pm8150-s4 { - compatible = "regulator-fixed"; - regulator-name = "vreg_s4a_1p8"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - - vin-supply = <&vph_pwr>; - }; - - vreg_s6c_0p88: smpc6-regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_s6c_0p88"; - - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-always-on; - vin-supply = <&vph_pwr>; - }; -}; - -&adsp { - status = "okay"; - firmware-name = "qcom/sm8250/adsp.mbn"; -}; - -&apps_rsc { - pm8150-rpmh-regulators { - compatible = "qcom,pm8150-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-s8-supply = <&vph_pwr>; - vdd-s9-supply = <&vph_pwr>; - vdd-s10-supply = <&vph_pwr>; - vdd-l1-l8-l11-supply = <&vreg_s6c_0p88>; - vdd-l2-l10-supply = <&vreg_bob>; - vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p95>; - vdd-l6-l9-supply = <&vreg_s8c_1p3>; - vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>; - vdd-l13-l16-l17-supply = <&vreg_bob>; - - vreg_s5a_1p9: smps5 { - regulator-name = "vreg_s5a_1p9"; - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - - vreg_s6a_0p95: smps6 { - regulator-name = "vreg_s6a_0p95"; - regulator-min-microvolt = <920000>; - regulator-max-microvolt = <1128000>; - regulator-initial-mode = ; - }; - - vreg_l2a_3p1: ldo2 { - regulator-name = "vreg_l2a_3p1"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l3a_0p9: ldo3 { - regulator-name = "vreg_l3a_0p9"; - regulator-min-microvolt = <928000>; - regulator-max-microvolt = <932000>; - regulator-initial-mode = ; - }; - - vreg_l5a_0p875: ldo5 { - regulator-name = "vreg_l5a_0p875"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - - vreg_l6a_1p2: ldo6 { - regulator-name = "vreg_l6a_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l7a_1p7: ldo7 { - regulator-name = "vreg_l7a_1p7"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l9a_1p2: ldo9 { - regulator-name = "vreg_l9a_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l10a_1p8: ldo10 { - regulator-name = "vreg_l10a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l12a_1p8: ldo12 { - regulator-name = "vreg_l12a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l13a_ts_3p0: ldo13 { - regulator-name = "vreg_l13a_ts_3p0"; - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - - vreg_l14a_1p8: ldo14 { - regulator-name = "vreg_l14a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1880000>; - regulator-initial-mode = ; - }; - - vreg_l15a_11ad_io_1p8: ldo15 { - regulator-name = "vreg_l15a_11ad_io_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l16a_2p7: ldo16 { - regulator-name = "vreg_l16a_2p7"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l17a_3p0: ldo17 { - regulator-name = "vreg_l17a_3p0"; - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - }; - - pm8150l-rpmh-regulators { - compatible = "qcom,pm8150l-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-s8-supply = <&vph_pwr>; - vdd-l1-l8-supply = <&vreg_s4a_1p8>; - vdd-l2-l3-supply = <&vreg_s8c_1p3>; - vdd-l4-l5-l6-supply = <&vreg_bob>; - vdd-l7-l11-supply = <&vreg_bob>; - vdd-l9-l10-supply = <&vreg_bob>; - vdd-bob-supply = <&vph_pwr>; - - vreg_bob: bob { - regulator-name = "vreg_bob"; - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <4000000>; - regulator-initial-mode = ; - }; - - vreg_s8c_1p3: smps8 { - regulator-name = "vreg_s8c_1p3"; - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - regulator-initial-mode = ; - }; - - vreg_l1c_1p8: ldo1 { - regulator-name = "vreg_l1c_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l2c_1p2: ldo2 { - regulator-name = "vreg_l2c_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l3c_0p92: ldo3 { - regulator-name = "vreg_l3c_0p92"; - regulator-min-microvolt = <920000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_l4c_1p7: ldo4 { - regulator-name = "vreg_l4c_1p7"; - regulator-min-microvolt = <1704000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l5c_1p8: ldo5 { - regulator-name = "vreg_l5c_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2928000>; - regulator-initial-mode = ; - }; - - vreg_l6c_2p9: ldo6 { - regulator-name = "vreg_l6c_2p9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l7c_cam_vcm0_2p85: ldo7 { - regulator-name = "vreg_l7c_cam_vcm0_2p85"; - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <3104000>; - regulator-initial-mode = ; - }; - - vreg_l8c_1p8: ldo8 { - regulator-name = "vreg_l8c_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l9c_2p9: ldo9 { - regulator-name = "vreg_l9c_2p9"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l10c_3p0: ldo10 { - regulator-name = "vreg_l10c_3p0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-initial-mode = ; - }; - - vreg_l11c_3p3: ldo11 { - regulator-name = "vreg_l11c_3p3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - }; - - pm8009-rpmh-regulators { - compatible = "qcom,pm8009-rpmh-regulators"; - qcom,pmic-id = "f"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vreg_bob>; - vdd-l2-supply = <&vreg_s8c_1p3>; - vdd-l5-l6-supply = <&vreg_bob>; - vdd-l7-supply = <&vreg_s4a_1p8>; - - vreg_l1f_cam_dvdd1_1p1: ldo1 { - regulator-name = "vreg_l1f_cam_dvdd1_1p1"; - regulator-min-microvolt = <1104000>; - regulator-max-microvolt = <1104000>; - regulator-initial-mode = ; - }; - - vreg_l2f_cam_dvdd0_1p2: ldo2 { - regulator-name = "vreg_l2f_cam_dvdd0_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l3f_cam_dvdd2_1p05: ldo3 { - regulator-name = "vreg_l3f_cam_dvdd2_1p05"; - regulator-min-microvolt = <1056000>; - regulator-max-microvolt = <1056000>; - regulator-initial-mode = ; - }; - - vreg_l5f_cam_avdd0_2p85: ldo5 { - regulator-name = "vreg_l5f_cam_avdd0_2p85"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-initial-mode = ; - }; - - vreg_l6f_cam_avdd1_2p85: ldo6 { - regulator-name = "vreg_l6f_cam_avdd1_2p85"; - regulator-min-microvolt = <2856000>; - regulator-max-microvolt = <2856000>; - regulator-initial-mode = ; - }; - - vreg_l7f_1p8: ldo7 { - regulator-name = "vreg_l7f_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - }; -}; - -&cdsp { - status = "okay"; - firmware-name = "qcom/sm8250/cdsp.mbn"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <1000000>; - - /* NQ NFC chip @28 */ -}; - -&i2c13 { - status = "okay"; - - /* st,stmfts @ 49 */ -}; - -&i2c15 { - status = "okay"; - - /* smb1390 @ 10 */ - /* rtc6226 @ 64 */ -}; - -&qupv3_id_0 { - status = "okay"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&qupv3_id_2 { - status = "okay"; -}; - -&slpi { - status = "okay"; - firmware-name = "qcom/sm8250/slpi.mbn"; -}; - -&tlmm { - gpio-reserved-ranges = <28 4>, <40 4>; -}; - -&uart12 { - status = "okay"; -}; - -&ufs_mem_hc { - status = "okay"; - - vcc-supply = <&vreg_l17a_3p0>; - vcc-max-microamp = <750000>; - vccq-supply = <&vreg_l6a_1p2>; - vccq-max-microamp = <700000>; - vccq2-supply = <&vreg_s4a_1p8>; - vccq2-max-microamp = <750000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l5a_0p875>; - vdda-max-microamp = <90200>; - vdda-pll-supply = <&vreg_l9a_1p2>; - vdda-pll-max-microamp = <19000>; -}; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi deleted file mode 100644 index ec356fe07..000000000 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ /dev/null @@ -1,3120 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - i2c9 = &i2c9; - i2c10 = &i2c10; - i2c11 = &i2c11; - i2c12 = &i2c12; - i2c13 = &i2c13; - i2c14 = &i2c14; - i2c15 = &i2c15; - i2c16 = &i2c16; - i2c17 = &i2c17; - i2c18 = &i2c18; - i2c19 = &i2c19; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - spi4 = &spi4; - spi5 = &spi5; - spi6 = &spi6; - spi7 = &spi7; - spi8 = &spi8; - spi9 = &spi9; - spi10 = &spi10; - spi11 = &spi11; - spi12 = &spi12; - spi13 = &spi13; - spi14 = &spi14; - spi15 = &spi15; - spi16 = &spi16; - spi17 = &spi17; - spi18 = &spi18; - spi19 = &spi19; - }; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - clock-output-names = "xo_board"; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&L2_100>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x200>; - enable-method = "psci"; - next-level-cache = <&L2_200>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x300>; - enable-method = "psci"; - next-level-cache = <&L2_300>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x400>; - enable-method = "psci"; - next-level-cache = <&L2_400>; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x500>; - enable-method = "psci"; - next-level-cache = <&L2_500>; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x600>; - enable-method = "psci"; - next-level-cache = <&L2_600>; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo485"; - reg = <0x0 0x700>; - enable-method = "psci"; - next-level-cache = <&L2_700>; - qcom,freq-domain = <&cpufreq_hw 2>; - #cooling-cells = <2>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - }; - - firmware { - scm: scm { - compatible = "qcom,scm"; - #reset-cells = <1>; - }; - }; - - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0x0 0x80000000 0x0 0x0>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@80000000 { - reg = <0x0 0x80000000 0x0 0x600000>; - no-map; - }; - - xbl_aop_mem: memory@80700000 { - reg = <0x0 0x80700000 0x0 0x160000>; - no-map; - }; - - cmd_db: memory@80860000 { - compatible = "qcom,cmd-db"; - reg = <0x0 0x80860000 0x0 0x20000>; - no-map; - }; - - smem_mem: memory@80900000 { - reg = <0x0 0x80900000 0x0 0x200000>; - no-map; - }; - - removed_mem: memory@80b00000 { - reg = <0x0 0x80b00000 0x0 0x5300000>; - no-map; - }; - - camera_mem: memory@86200000 { - reg = <0x0 0x86200000 0x0 0x500000>; - no-map; - }; - - wlan_mem: memory@86700000 { - reg = <0x0 0x86700000 0x0 0x100000>; - no-map; - }; - - ipa_fw_mem: memory@86800000 { - reg = <0x0 0x86800000 0x0 0x10000>; - no-map; - }; - - ipa_gsi_mem: memory@86810000 { - reg = <0x0 0x86810000 0x0 0xa000>; - no-map; - }; - - gpu_mem: memory@8681a000 { - reg = <0x0 0x8681a000 0x0 0x2000>; - no-map; - }; - - npu_mem: memory@86900000 { - reg = <0x0 0x86900000 0x0 0x500000>; - no-map; - }; - - video_mem: memory@86e00000 { - reg = <0x0 0x86e00000 0x0 0x500000>; - no-map; - }; - - cvp_mem: memory@87300000 { - reg = <0x0 0x87300000 0x0 0x500000>; - no-map; - }; - - cdsp_mem: memory@87800000 { - reg = <0x0 0x87800000 0x0 0x1400000>; - no-map; - }; - - slpi_mem: memory@88c00000 { - reg = <0x0 0x88c00000 0x0 0x1500000>; - no-map; - }; - - adsp_mem: memory@8a100000 { - reg = <0x0 0x8a100000 0x0 0x1d00000>; - no-map; - }; - - spss_mem: memory@8be00000 { - reg = <0x0 0x8be00000 0x0 0x100000>; - no-map; - }; - - cdsp_secure_heap: memory@8bf00000 { - reg = <0x0 0x8bf00000 0x0 0x4600000>; - no-map; - }; - }; - - smem: qcom,smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - - smp2p-adsp { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - smp2p_adsp_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_adsp_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - interrupts-extended = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - smp2p_cdsp_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_cdsp_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - smp2p_slpi_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_slpi_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc@0 { - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0 0 0 0x10 0>; - dma-ranges = <0 0 0 0 0x10 0>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sm8250"; - reg = <0x0 0x00100000 0x0 0x1f0000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clock-names = "bi_tcxo", - "bi_tcxo_ao", - "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>, - <&sleep_clk>; - }; - - ipcc: mailbox@408000 { - compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; - reg = <0 0x00408000 0 0x1000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - #mbox-cells = <2>; - }; - - qup_opp_table: qup-opp-table { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-75000000 { - opp-hz = /bits/ 64 <75000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-120000000 { - opp-hz = /bits/ 64 <120000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - }; - - qupv3_id_2: geniqup@8c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x008c0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c14: i2c@880000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c14_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi14: spi@880000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00880000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi14_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c15: i2c@884000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c15_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi15: spi@884000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00884000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi15_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c16: i2c@888000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00888000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c16_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi16: spi@888000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00888000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi16_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c17: i2c@88c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c17_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi17: spi@88c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi17_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - uart17: serial@88c000 { - compatible = "qcom,geni-uart"; - reg = <0 0x0088c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart17_default>; - interrupts = ; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c18: i2c@890000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c18_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi18: spi@890000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi18_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - uart18: serial@890000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00890000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart18_default>; - interrupts = ; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c19: i2c@894000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c19_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi19: spi@894000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi19_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - }; - - qupv3_id_0: geniqup@9c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x009c0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c0: i2c@980000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00980000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c0_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@980000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00980000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi0_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c1: i2c@984000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00984000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c1_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@984000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00984000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi1_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c2: i2c@988000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00988000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c2_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@988000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00988000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi2_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - uart2: serial@988000 { - compatible = "qcom,geni-debug-uart"; - reg = <0 0x00988000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart2_default>; - interrupts = ; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c3: i2c@98c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0098c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c3_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@98c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x0098c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi3_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c4: i2c@990000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00990000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c4_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@990000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00990000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi4_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c5: i2c@994000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00994000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c5_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi5: spi@994000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00994000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi5_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c6: i2c@998000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00998000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c6_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi6: spi@998000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00998000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi6_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - uart6: serial@998000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00998000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart6_default>; - interrupts = ; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c7: i2c@99c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x0099c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c7_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi7: spi@99c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x0099c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi7_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - }; - - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00ac0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c8: i2c@a80000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c8_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi8: spi@a80000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a80000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi8_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c9: i2c@a84000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c9_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi9: spi@a84000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a84000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi9_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c10: i2c@a88000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c10_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi10: spi@a88000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a88000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi10_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c11: i2c@a8c000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c11_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi11: spi@a8c000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a8c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi11_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c12: i2c@a90000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c12_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi12: spi@a90000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a90000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi12_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - uart12: serial@a90000 { - compatible = "qcom,geni-debug-uart"; - reg = <0x0 0x00a90000 0x0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart12_default>; - interrupts = ; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - - i2c13: i2c@a94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c13_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi13: spi@a94000 { - compatible = "qcom,geni-spi"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_spi13_default>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&rpmhpd SM8250_CX>; - operating-points-v2 = <&qup_opp_table>; - status = "disabled"; - }; - }; - - config_noc: interconnect@1500000 { - compatible = "qcom,sm8250-config-noc"; - reg = <0 0x01500000 0 0xa580>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect@1620000 { - compatible = "qcom,sm8250-system-noc"; - reg = <0 0x01620000 0 0x1c200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mc_virt: interconnect@163d000 { - compatible = "qcom,sm8250-mc-virt"; - reg = <0 0x0163d000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre1_noc: interconnect@16e0000 { - compatible = "qcom,sm8250-aggre1-noc"; - reg = <0 0x016e0000 0 0x1f180>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect@1700000 { - compatible = "qcom,sm8250-aggre2-noc"; - reg = <0 0x01700000 0 0x33000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - compute_noc: interconnect@1733000 { - compatible = "qcom,sm8250-compute-noc"; - reg = <0 0x01733000 0 0xa180>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mmss_noc: interconnect@1740000 { - compatible = "qcom,sm8250-mmss-noc"; - reg = <0 0x01740000 0 0x1f080>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sm8250-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>; - interrupts = ; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - #reset-cells = <1>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - power-domains = <&gcc UFS_PHY_GDSC>; - - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - clocks = - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz = - <37500000 300000000>, - <0 0>, - <0 0>, - <37500000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; - - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sm8250-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", - "ref_aux"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: lanes@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; - #phy-cells = <0>; - }; - }; - - ipa_virt: interconnect@1e00000 { - compatible = "qcom,sm8250-ipa-virt"; - reg = <0 0x01e00000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - tcsr_mutex: hwlock@1f40000 { - compatible = "qcom,tcsr-mutex"; - reg = <0x0 0x01f40000 0x0 0x40000>; - #hwlock-cells = <1>; - }; - - gpu: gpu@3d00000 { - /* - * note: the amd,imageon compatible makes it possible - * to use the drm/msm driver without the display node, - * make sure to remove it when display node is added - */ - compatible = "qcom,adreno-650.2", - "qcom,adreno", - "amd,imageon"; - #stream-id-cells = <16>; - - reg = <0 0x03d00000 0 0x40000>; - reg-names = "kgsl_3d0_reg_memory"; - - interrupts = ; - - iommus = <&adreno_smmu 0 0x401>; - - operating-points-v2 = <&gpu_opp_table>; - - qcom,gmu = <&gmu>; - - zap-shader { - memory-region = <&gpu_mem>; - }; - - /* note: downstream checks gpu binning for 670 Mhz */ - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-670000000 { - opp-hz = /bits/ 64 <670000000>; - opp-level = ; - }; - - opp-587000000 { - opp-hz = /bits/ 64 <587000000>; - opp-level = ; - }; - - opp-525000000 { - opp-hz = /bits/ 64 <525000000>; - opp-level = ; - }; - - opp-490000000 { - opp-hz = /bits/ 64 <490000000>; - opp-level = ; - }; - - opp-441600000 { - opp-hz = /bits/ 64 <441600000>; - opp-level = ; - }; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-level = ; - }; - - opp-305000000 { - opp-hz = /bits/ 64 <305000000>; - opp-level = ; - }; - }; - }; - - gmu: gmu@3d6a000 { - compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; - - reg = <0 0x03d6a000 0 0x30000>, - <0 0x3de0000 0 0x10000>, - <0 0xb290000 0 0x10000>, - <0 0xb490000 0 0x10000>; - reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; - - interrupts = , - ; - interrupt-names = "hfi", "gmu"; - - clocks = <&gpucc GPU_CC_AHB_CLK>, - <&gpucc GPU_CC_CX_GMU_CLK>, - <&gpucc GPU_CC_CXO_CLK>, - <&gcc GCC_DDRSS_GPU_AXI_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>; - clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; - - power-domains = <&gpucc GPU_CX_GDSC>, - <&gpucc GPU_GX_GDSC>; - power-domain-names = "cx", "gx"; - - iommus = <&adreno_smmu 5 0x400>; - - operating-points-v2 = <&gmu_opp_table>; - - gmu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-level = ; - }; - }; - }; - - gpucc: clock-controller@3d90000 { - compatible = "qcom,sm8250-gpucc"; - reg = <0 0x03d90000 0 0x9000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_GPU_GPLL0_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; - clock-names = "bi_tcxo", - "gcc_gpu_gpll0_clk_src", - "gcc_gpu_gpll0_div_clk_src"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - adreno_smmu: iommu@3da0000 { - compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; - reg = <0 0x03da0000 0 0x10000>; - #iommu-cells = <2>; - #global-interrupts = <2>; - interrupts = , - , - , - , - , - , - , - , - , - ; - clocks = <&gpucc GPU_CC_AHB_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; - clock-names = "ahb", "bus", "iface"; - - power-domains = <&gpucc GPU_CX_GDSC>; - }; - - slpi: remoteproc@5c00000 { - compatible = "qcom,sm8250-slpi-pas"; - reg = <0 0x05c00000 0 0x4000>; - - interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, - <&rpmhpd SM8250_LCX>, - <&rpmhpd SM8250_LMX>; - power-domain-names = "load_state", "lcx", "lmx"; - - memory-region = <&slpi_mem>; - - qcom,smem-states = <&smp2p_slpi_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "lpass"; - qcom,remote-pid = <3>; - }; - }; - - cdsp: remoteproc@8300000 { - compatible = "qcom,sm8250-cdsp-pas"; - reg = <0 0x08300000 0 0x10000>; - - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, - <&rpmhpd SM8250_CX>; - power-domain-names = "load_state", "cx"; - - memory-region = <&cdsp_mem>; - - qcom,smem-states = <&smp2p_cdsp_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "lpass"; - qcom,remote-pid = <5>; - }; - }; - - dc_noc: interconnect@90c0000 { - compatible = "qcom,sm8250-dc-noc"; - reg = <0 0x090c0000 0 0x4200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - gem_noc: interconnect@9100000 { - compatible = "qcom,sm8250-gem-noc"; - reg = <0 0x09100000 0 0xb4000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - npu_noc: interconnect@9990000 { - compatible = "qcom,sm8250-npu-noc"; - reg = <0 0x09990000 0 0x1600>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - pdc: interrupt-controller@b220000 { - compatible = "qcom,sm8250-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; - qcom,pdc-ranges = <0 480 94>, <94 609 31>, - <125 63 1>, <126 716 12>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - tsens0: thermal-sensor@c263000 { - compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1ff>, /* TM */ - <0 0x0c222000 0 0x1ff>; /* SROT */ - #qcom,sensors = <16>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c265000 { - compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1ff>, /* TM */ - <0 0x0c223000 0 0x1ff>; /* SROT */ - #qcom,sensors = <9>; - interrupts = , - ; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - aoss_qmp: qmp@c300000 { - compatible = "qcom,sm8250-aoss-qmp"; - reg = <0 0x0c300000 0 0x100000>; - interrupts-extended = <&ipcc IPCC_CLIENT_AOP - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_AOP - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - #clock-cells = <0>; - #power-domain-cells = <1>; - }; - - spmi_bus: spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0 0x0c440000 0x0 0x0001100>, - <0x0 0x0c600000 0x0 0x2000000>, - <0x0 0x0e600000 0x0 0x0100000>, - <0x0 0x0e700000 0x0 0x00a0000>, - <0x0 0x0c40a000 0x0 0x0026000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - tlmm: pinctrl@f100000 { - compatible = "qcom,sm8250-pinctrl"; - reg = <0 0x0f100000 0 0x300000>, - <0 0x0f500000 0 0x300000>, - <0 0x0f900000 0 0x300000>; - reg-names = "west", "south", "north"; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 181>; - wakeup-parent = <&pdc>; - - qup_i2c0_default: qup-i2c0-default { - mux { - pins = "gpio28", "gpio29"; - function = "qup0"; - }; - - config { - pins = "gpio28", "gpio29"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c1_default: qup-i2c1-default { - pinmux { - pins = "gpio4", "gpio5"; - function = "qup1"; - }; - - config { - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c2_default: qup-i2c2-default { - mux { - pins = "gpio115", "gpio116"; - function = "qup2"; - }; - - config { - pins = "gpio115", "gpio116"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c3_default: qup-i2c3-default { - mux { - pins = "gpio119", "gpio120"; - function = "qup3"; - }; - - config { - pins = "gpio119", "gpio120"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c4_default: qup-i2c4-default { - mux { - pins = "gpio8", "gpio9"; - function = "qup4"; - }; - - config { - pins = "gpio8", "gpio9"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c5_default: qup-i2c5-default { - mux { - pins = "gpio12", "gpio13"; - function = "qup5"; - }; - - config { - pins = "gpio12", "gpio13"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c6_default: qup-i2c6-default { - mux { - pins = "gpio16", "gpio17"; - function = "qup6"; - }; - - config { - pins = "gpio16", "gpio17"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c7_default: qup-i2c7-default { - mux { - pins = "gpio20", "gpio21"; - function = "qup7"; - }; - - config { - pins = "gpio20", "gpio21"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c8_default: qup-i2c8-default { - mux { - pins = "gpio24", "gpio25"; - function = "qup8"; - }; - - config { - pins = "gpio24", "gpio25"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c9_default: qup-i2c9-default { - mux { - pins = "gpio125", "gpio126"; - function = "qup9"; - }; - - config { - pins = "gpio125", "gpio126"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c10_default: qup-i2c10-default { - mux { - pins = "gpio129", "gpio130"; - function = "qup10"; - }; - - config { - pins = "gpio129", "gpio130"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c11_default: qup-i2c11-default { - mux { - pins = "gpio60", "gpio61"; - function = "qup11"; - }; - - config { - pins = "gpio60", "gpio61"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c12_default: qup-i2c12-default { - mux { - pins = "gpio32", "gpio33"; - function = "qup12"; - }; - - config { - pins = "gpio32", "gpio33"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c13_default: qup-i2c13-default { - mux { - pins = "gpio36", "gpio37"; - function = "qup13"; - }; - - config { - pins = "gpio36", "gpio37"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c14_default: qup-i2c14-default { - mux { - pins = "gpio40", "gpio41"; - function = "qup14"; - }; - - config { - pins = "gpio40", "gpio41"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c15_default: qup-i2c15-default { - mux { - pins = "gpio44", "gpio45"; - function = "qup15"; - }; - - config { - pins = "gpio44", "gpio45"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c16_default: qup-i2c16-default { - mux { - pins = "gpio48", "gpio49"; - function = "qup16"; - }; - - config { - pins = "gpio48", "gpio49"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c17_default: qup-i2c17-default { - mux { - pins = "gpio52", "gpio53"; - function = "qup17"; - }; - - config { - pins = "gpio52", "gpio53"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c18_default: qup-i2c18-default { - mux { - pins = "gpio56", "gpio57"; - function = "qup18"; - }; - - config { - pins = "gpio56", "gpio57"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_i2c19_default: qup-i2c19-default { - mux { - pins = "gpio0", "gpio1"; - function = "qup19"; - }; - - config { - pins = "gpio0", "gpio1"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_spi0_default: qup-spi0-default { - mux { - pins = "gpio28", "gpio29", - "gpio30", "gpio31"; - function = "qup0"; - }; - - config { - pins = "gpio28", "gpio29", - "gpio30", "gpio31"; - drive-strength = <6>; - bias-disable; - }; - }; - - qup_spi1_default: qup-spi1-default { - mux { - pins = "gpio4", "gpio5", - "gpio6", "gpio7"; - function = "qup1"; - }; - - config { - pins = "gpio4", "gpio5", - "gpio6", "gpio7"; - drive-strength = <6>; - bias-disable; - }; - }; - - qup_spi2_default: qup-spi2-default { - mux { - pins = "gpio115", "gpio116", - "gpio117", "gpio118"; - function = "qup2"; - }; - - config { - pins = "gpio115", "gpio116", - "gpio117", "gpio118"; - drive-strength = <6>; - bias-disable; - }; - }; - - qup_spi3_default: qup-spi3-default { - mux { - pins = "gpio119", "gpio120", - "gpio121", "gpio122"; - function = "qup3"; - }; - - config { - pins = "gpio119", "gpio120", - "gpio121", "gpio122"; - drive-strength = <6>; - bias-disable; - }; - }; - - qup_spi4_default: qup-spi4-default { - mux { - pins = "gpio8", "gpio9", - "gpio10", "gpio11"; - function = "qup4"; - }; - - config { - pins = "gpio8", "gpio9", - "gpio10", "gpio11"; - drive-strength = <6>; - bias-disable; - }; - }; - - qup_spi5_default: qup-spi5-default { - mux { - pins = "gpio12", "gpio13", - "gpio14", "gpio15"; - function = "qup5"; - }; - - config { - pins = "gpio12", "gpio13", - "gpio14", "gpio15"; - drive-strength = <6>; - bias-disable; - }; - }; - - qup_spi6_default: qup-spi6-default { - mux { - pins = "gpio16", "gpio17", - "gpio18", "gpio19"; - function = "qup6"; - }; - - config { - pins = "gpio16", "gpio17", - "gpio18", "gpio19"; - drive-strength = <6>; - bias-disable; - }; - }; - - qup_spi7_default: qup-spi7-default { - mux { - pins = "gpio20", "gpio21", - "gpio22", "gpio23"; - function = "qup7"; - }; - - config { - pins = "gpio20", "gpio21", - "gpio22", "gpio23"; - drive-strength = <6>; - bias-disable; - }; - }; - - qup_spi8_default: qup-spi8-default { - mux { - pins = "gpio24", "gpio25", - "gpio26", "gpio27"; - function = "qup8"; - }; - - config { - pins = "gpio24", "gpio25", - "gpio26", "gpio27"; - drive-strength = <6>; - bias-disable; - }; - }; - - qup_spi9_default: qup-spi9-default { - mux { - pins = "gpio125", "gpio126", - "gpio127", "gpio128"; - function = "qup9"; - }; - - config { - pins = "gpio125", "gpio126", - "gpio127", "gpio128"; - drive-strength = <6>; - bias-disable; - }; - }; - - qup_spi10_default: qup-spi10-default { - mux { - pins = "gpio129", "gpio130", - "gpio131", "gpio132"; - function = "qup10"; - }; - - config { - pins = "gpio129", "gpio130", - "gpio131", "gpio132"; - drive-strength = <6>; - bias-disable; - }; - }; - - qup_spi11_default: qup-spi11-default { - mux { - pins = "gpio60", "gpio61", - "gpio62", "gpio63"; - function = "qup11"; - }; - - config { - pins = "gpio60", "gpio61", - "gpio62", "gpio63"; - drive-strength = <6>; - bias-disable; - }; - }; - - qup_spi12_default: qup-spi12-default { - mux { - pins = "gpio32", "gpio33", - "gpio34", "gpio35"; - function = "qup12"; - }; - - config { - pins = "gpio32", "gpio33", - "gpio34", "gpio35"; - drive-strength = <6>; - bias-disable; - }; - }; - - qup_spi13_default: qup-spi13-default { - mux { - pins = "gpio36", "gpio37", - "gpio38", "gpio39"; - function = "qup13"; - }; - - config { - pins = "gpio36", "gpio37", - "gpio38", "gpio39"; - drive-strength = <6>; - bias-disable; - }; - }; - - qup_spi14_default: qup-spi14-default { - mux { - pins = "gpio40", "gpio41", - "gpio42", "gpio43"; - function = "qup14"; - }; - - config { - pins = "gpio40", "gpio41", - "gpio42", "gpio43"; - drive-strength = <6>; - bias-disable; - }; - }; - - qup_spi15_default: qup-spi15-default { - mux { - pins = "gpio44", "gpio45", - "gpio46", "gpio47"; - function = "qup15"; - }; - - config { - pins = "gpio44", "gpio45", - "gpio46", "gpio47"; - drive-strength = <6>; - bias-disable; - }; - }; - - qup_spi16_default: qup-spi16-default { - mux { - pins = "gpio48", "gpio49", - "gpio50", "gpio51"; - function = "qup16"; - }; - - config { - pins = "gpio48", "gpio49", - "gpio50", "gpio51"; - drive-strength = <6>; - bias-disable; - }; - }; - - qup_spi17_default: qup-spi17-default { - mux { - pins = "gpio52", "gpio53", - "gpio54", "gpio55"; - function = "qup17"; - }; - - config { - pins = "gpio52", "gpio53", - "gpio54", "gpio55"; - drive-strength = <6>; - bias-disable; - }; - }; - - qup_spi18_default: qup-spi18-default { - mux { - pins = "gpio56", "gpio57", - "gpio58", "gpio59"; - function = "qup18"; - }; - - config { - pins = "gpio56", "gpio57", - "gpio58", "gpio59"; - drive-strength = <6>; - bias-disable; - }; - }; - - qup_spi19_default: qup-spi19-default { - mux { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - function = "qup19"; - }; - - config { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - drive-strength = <6>; - bias-disable; - }; - }; - - qup_uart2_default: qup-uart2-default { - mux { - pins = "gpio117", "gpio118"; - function = "qup2"; - }; - }; - - qup_uart6_default: qup-uart6-default { - mux { - pins = "gpio16", "gpio17", - "gpio18", "gpio19"; - function = "qup6"; - }; - }; - - qup_uart12_default: qup-uart12-default { - mux { - pins = "gpio34", "gpio35"; - function = "qup12"; - }; - }; - - qup_uart17_default: qup-uart17-default { - mux { - pins = "gpio52", "gpio53", - "gpio54", "gpio55"; - function = "qup17"; - }; - }; - - qup_uart18_default: qup-uart18-default { - mux { - pins = "gpio58", "gpio59"; - function = "qup18"; - }; - }; - }; - - adsp: remoteproc@17300000 { - compatible = "qcom,sm8250-adsp-pas"; - reg = <0 0x17300000 0 0x100>; - - interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, - <&rpmhpd SM8250_LCX>, - <&rpmhpd SM8250_LMX>; - power-domain-names = "load_state", "lcx", "lmx"; - - memory-region = <&adsp_mem>; - - qcom,smem-states = <&smp2p_adsp_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "lpass"; - qcom,remote-pid = <2>; - }; - }; - - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ - <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ - interrupts = ; - }; - - watchdog@17c10000 { - compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; - reg = <0 0x17c10000 0 0x1000>; - clocks = <&sleep_clk>; - }; - - timer@17c20000 { - #address-cells = <2>; - #size-cells = <2>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x17c20000 0x0 0x1000>; - clock-frequency = <19200000>; - - frame@17c21000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x0 0x17c21000 0x0 0x1000>, - <0x0 0x17c22000 0x0 0x1000>; - }; - - frame@17c23000 { - frame-number = <1>; - interrupts = ; - reg = <0x0 0x17c23000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c25000 { - frame-number = <2>; - interrupts = ; - reg = <0x0 0x17c25000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c27000 { - frame-number = <3>; - interrupts = ; - reg = <0x0 0x17c27000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c29000 { - frame-number = <4>; - interrupts = ; - reg = <0x0 0x17c29000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c2b000 { - frame-number = <5>; - interrupts = ; - reg = <0x0 0x17c2b000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17c2d000 { - frame-number = <6>; - interrupts = ; - reg = <0x0 0x17c2d000 0x0 0x1000>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@18200000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x18200000 0x0 0x10000>, - <0x0 0x18210000 0x0 0x10000>, - <0x0 0x18220000 0x0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , , - , ; - - rpmhcc: clock-controller { - compatible = "qcom,sm8250-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sm8250-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_nom: opp6 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp8 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp10 { - opp-level = ; - }; - }; - }; - - apps_bcm_voter: bcm_voter { - compatible = "qcom,bcm-voter"; - }; - }; - - epss_l3: interconnect@18590000 { - compatible = "qcom,sm8250-epss-l3"; - reg = <0 0x18590000 0 0x1000>; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #interconnect-cells = <1>; - }; - - cpufreq_hw: cpufreq@18591000 { - compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; - reg = <0 0x18591000 0 0x1000>, - <0 0x18592000 0 0x1000>, - <0 0x18593000 0 0x1000>; - reg-names = "freq-domain0", "freq-domain1", - "freq-domain2"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 1>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 2>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 3>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 4>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 7>; - - trips { - cpu4_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 8>; - - trips { - cpu5_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 9>; - - trips { - cpu6_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-top-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 10>; - - trips { - cpu7_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 11>; - - trips { - cpu4_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 12>; - - trips { - cpu5_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 13>; - - trips { - cpu6_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-bottom-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 14>; - - trips { - cpu7_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - aoss0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 0>; - - trips { - aoss0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - cluster0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 5>; - - trips { - cluster0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster0_crit: cluster0_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cluster1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 6>; - - trips { - cluster1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cluster1_crit: cluster1_crit { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - gpu-thermal-top { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens0 15>; - - trips { - gpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - aoss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 0>; - - trips { - aoss1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - wlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 1>; - - trips { - wlan_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - video-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 2>; - - trips { - video_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 3>; - - trips { - mem_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - q6-hvx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 4>; - - trips { - q6_hvx_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 5>; - - trips { - camera_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - compute-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 6>; - - trips { - compute_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - npu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 7>; - - trips { - npu_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - - gpu-thermal-bottom { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens1 8>; - - trips { - gpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/realtek/Makefile b/arch/arm64/boot/dts/realtek/Makefile deleted file mode 100644 index ef8d8fcba..000000000 --- a/arch/arm64/boot/dts/realtek/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -dtb-$(CONFIG_ARCH_REALTEK) += rtd1293-ds418j.dtb - -dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-mele-v9.dtb -dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb -dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-xnano-x5.dtb -dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb - -dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb - -dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-bpi-m4.dtb -dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-lionskin.dtb - -dtb-$(CONFIG_ARCH_REALTEK) += rtd1619-mjolnir.dtb diff --git a/arch/arm64/boot/dts/realtek/rtd1293-ds418j.dts b/arch/arm64/boot/dts/realtek/rtd1293-ds418j.dts deleted file mode 100644 index b2e44c6c2..000000000 --- a/arch/arm64/boot/dts/realtek/rtd1293-ds418j.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Copyright (c) 2017-2019 Andreas Färber - */ - -/dts-v1/; - -#include "rtd1293.dtsi" - -/ { - compatible = "synology,ds418j", "realtek,rtd1293"; - model = "Synology DiskStation DS418j"; - - memory@1f000 { - device_type = "memory"; - reg = <0x1f000 0x3ffe1000>; /* boot ROM to 1 GiB */ - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/realtek/rtd1293.dtsi b/arch/arm64/boot/dts/realtek/rtd1293.dtsi deleted file mode 100644 index 2d92b56ac..000000000 --- a/arch/arm64/boot/dts/realtek/rtd1293.dtsi +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Realtek RTD1293 SoC - * - * Copyright (c) 2017-2019 Andreas Färber - */ - -#include "rtd129x.dtsi" - -/ { - compatible = "realtek,rtd1293"; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - next-level-cache = <&l2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - next-level-cache = <&l2>; - }; - - l2: l2-cache { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; - -&arm_pmu { - interrupt-affinity = <&cpu0>, <&cpu1>; -}; - -&gic { - interrupts = ; -}; diff --git a/arch/arm64/boot/dts/realtek/rtd1295-mele-v9.dts b/arch/arm64/boot/dts/realtek/rtd1295-mele-v9.dts deleted file mode 100644 index cf4a57c01..000000000 --- a/arch/arm64/boot/dts/realtek/rtd1295-mele-v9.dts +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2017-2019 Andreas Färber - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -/dts-v1/; - -#include "rtd1295.dtsi" - -/ { - compatible = "mele,v9", "realtek,rtd1295"; - model = "MeLE V9"; - - memory@1f000 { - device_type = "memory"; - reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */ - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/realtek/rtd1295-probox2-ava.dts b/arch/arm64/boot/dts/realtek/rtd1295-probox2-ava.dts deleted file mode 100644 index 14161c3f3..000000000 --- a/arch/arm64/boot/dts/realtek/rtd1295-probox2-ava.dts +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2017-2019 Andreas Färber - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -/dts-v1/; - -#include "rtd1295.dtsi" - -/ { - compatible = "probox2,ava", "realtek,rtd1295"; - model = "PROBOX2 AVA"; - - memory@1f000 { - device_type = "memory"; - reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */ - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/realtek/rtd1295-xnano-x5.dts b/arch/arm64/boot/dts/realtek/rtd1295-xnano-x5.dts deleted file mode 100644 index d7878ff94..000000000 --- a/arch/arm64/boot/dts/realtek/rtd1295-xnano-x5.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Copyright (c) 2017-2019 Andreas Färber - */ - -/dts-v1/; - -#include "rtd1295.dtsi" - -/ { - compatible = "xnano,x5", "realtek,rtd1295"; - model = "Xnano X5"; - - memory@1f000 { - device_type = "memory"; - reg = <0x1f000 0x3ffe1000>; /* boot ROM to 1 GiB or 2 GiB */ - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/realtek/rtd1295-zidoo-x9s.dts b/arch/arm64/boot/dts/realtek/rtd1295-zidoo-x9s.dts deleted file mode 100644 index 4beb37bb9..000000000 --- a/arch/arm64/boot/dts/realtek/rtd1295-zidoo-x9s.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Copyright (c) 2016-2017 Andreas Färber - */ - -/dts-v1/; - -#include "rtd1295.dtsi" - -/ { - compatible = "zidoo,x9s", "realtek,rtd1295"; - model = "Zidoo X9S"; - - memory@1f000 { - device_type = "memory"; - reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */ - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi b/arch/arm64/boot/dts/realtek/rtd1295.dtsi deleted file mode 100644 index 1402abe80..000000000 --- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Realtek RTD1295 SoC - * - * Copyright (c) 2016-2019 Andreas Färber - */ - -#include "rtd129x.dtsi" - -/ { - compatible = "realtek,rtd1295"; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - next-level-cache = <&l2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - next-level-cache = <&l2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - next-level-cache = <&l2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - next-level-cache = <&l2>; - }; - - l2: l2-cache { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; - -&arm_pmu { - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; -}; diff --git a/arch/arm64/boot/dts/realtek/rtd1296-ds418.dts b/arch/arm64/boot/dts/realtek/rtd1296-ds418.dts deleted file mode 100644 index cc706d13d..000000000 --- a/arch/arm64/boot/dts/realtek/rtd1296-ds418.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Copyright (c) 2017-2019 Andreas Färber - */ - -/dts-v1/; - -#include "rtd1296.dtsi" - -/ { - compatible = "synology,ds418", "realtek,rtd1296"; - model = "Synology DiskStation DS418"; - - memory@1f000 { - device_type = "memory"; - reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */ - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/realtek/rtd1296.dtsi b/arch/arm64/boot/dts/realtek/rtd1296.dtsi deleted file mode 100644 index fb864a139..000000000 --- a/arch/arm64/boot/dts/realtek/rtd1296.dtsi +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Realtek RTD1296 SoC - * - * Copyright (c) 2017-2019 Andreas Färber - */ - -#include "rtd129x.dtsi" - -/ { - compatible = "realtek,rtd1296"; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - next-level-cache = <&l2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - next-level-cache = <&l2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - next-level-cache = <&l2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - next-level-cache = <&l2>; - }; - - l2: l2-cache { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; - -&arm_pmu { - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; -}; diff --git a/arch/arm64/boot/dts/realtek/rtd129x.dtsi b/arch/arm64/boot/dts/realtek/rtd129x.dtsi deleted file mode 100644 index 39aefe66a..000000000 --- a/arch/arm64/boot/dts/realtek/rtd129x.dtsi +++ /dev/null @@ -1,195 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Realtek RTD1293/RTD1295/RTD1296 SoC - * - * Copyright (c) 2016-2019 Andreas Färber - */ - -/memreserve/ 0x0000000000000000 0x000000000001f000; -/memreserve/ 0x000000000001f000 0x00000000000e1000; -/memreserve/ 0x0000000001b00000 0x00000000004be000; - -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - rpc_comm: rpc@1f000 { - reg = <0x1f000 0x1000>; - }; - - rpc_ringbuf: rpc@1ffe000 { - reg = <0x1ffe000 0x4000>; - }; - - tee: tee@10100000 { - reg = <0x10100000 0xf00000>; - no-map; - }; - }; - - arm_pmu: arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - }; - - osc27M: osc { - compatible = "fixed-clock"; - clock-frequency = <27000000>; - #clock-cells = <0>; - clock-output-names = "osc27M"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */ - /* Exclude up to 2 GiB of RAM */ - <0x80000000 0x80000000 0x80000000>; - - rbus: bus@98000000 { - compatible = "simple-bus"; - reg = <0x98000000 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x98000000 0x200000>; - - crt: syscon@0 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0x1800>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1800>; - }; - - iso: syscon@7000 { - compatible = "syscon", "simple-mfd"; - reg = <0x7000 0x1000>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7000 0x1000>; - }; - - sb2: syscon@1a000 { - compatible = "syscon", "simple-mfd"; - reg = <0x1a000 0x1000>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1a000 0x1000>; - }; - - misc: syscon@1b000 { - compatible = "syscon", "simple-mfd"; - reg = <0x1b000 0x1000>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1b000 0x1000>; - }; - - scpu_wrapper: syscon@1d000 { - compatible = "syscon", "simple-mfd"; - reg = <0x1d000 0x2000>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1d000 0x2000>; - }; - }; - - gic: interrupt-controller@ff011000 { - compatible = "arm,gic-400"; - reg = <0xff011000 0x1000>, - <0xff012000 0x2000>, - <0xff014000 0x2000>, - <0xff016000 0x2000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - }; -}; - -&crt { - reset1: reset-controller@0 { - compatible = "snps,dw-low-reset"; - reg = <0x0 0x4>; - #reset-cells = <1>; - }; - - reset2: reset-controller@4 { - compatible = "snps,dw-low-reset"; - reg = <0x4 0x4>; - #reset-cells = <1>; - }; - - reset3: reset-controller@8 { - compatible = "snps,dw-low-reset"; - reg = <0x8 0x4>; - #reset-cells = <1>; - }; - - reset4: reset-controller@50 { - compatible = "snps,dw-low-reset"; - reg = <0x50 0x4>; - #reset-cells = <1>; - }; -}; - -&iso { - iso_reset: reset-controller@88 { - compatible = "snps,dw-low-reset"; - reg = <0x88 0x4>; - #reset-cells = <1>; - }; - - wdt: watchdog@680 { - compatible = "realtek,rtd1295-watchdog"; - reg = <0x680 0x100>; - clocks = <&osc27M>; - }; - - uart0: serial@800 { - compatible = "snps,dw-apb-uart"; - reg = <0x800 0x400>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <27000000>; - resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; - status = "disabled"; - }; -}; - -&misc { - uart1: serial@200 { - compatible = "snps,dw-apb-uart"; - reg = <0x200 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <432000000>; - resets = <&reset2 RTD1295_RSTN_UR1>; - status = "disabled"; - }; - - uart2: serial@400 { - compatible = "snps,dw-apb-uart"; - reg = <0x400 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <432000000>; - resets = <&reset2 RTD1295_RSTN_UR2>; - status = "disabled"; - }; -}; diff --git a/arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts b/arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts deleted file mode 100644 index 9891967d1..000000000 --- a/arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Copyright (c) 2019 Andreas Färber - */ - -/dts-v1/; - -#include "rtd1395.dtsi" - -/ { - compatible = "bananapi,bpi-m4", "realtek,rtd1395"; - model = "Banana Pi BPI-M4"; - - memory@2f000 { - device_type = "memory"; - reg = <0x2f000 0x3ffd1000>; /* boot ROM to 1 GiB or 2 GiB */ - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/realtek/rtd1395-lionskin.dts b/arch/arm64/boot/dts/realtek/rtd1395-lionskin.dts deleted file mode 100644 index 83f9b536c..000000000 --- a/arch/arm64/boot/dts/realtek/rtd1395-lionskin.dts +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Copyright (c) 2019 Andreas Färber - */ - -/dts-v1/; - -#include "rtd1395.dtsi" - -/ { - compatible = "realtek,lion-skin", "realtek,rtd1395"; - model = "Realtek Lion Skin EVB"; - - memory@2f000 { - device_type = "memory"; - reg = <0x2f000 0x3ffd1000>; /* boot ROM to 1 GiB or 2 GiB */ - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -/* debug console (J1) */ -&uart0 { - status = "okay"; -}; - -/* M.2 slot (CON1) */ -&uart1 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/realtek/rtd1395.dtsi b/arch/arm64/boot/dts/realtek/rtd1395.dtsi deleted file mode 100644 index 05c9216a8..000000000 --- a/arch/arm64/boot/dts/realtek/rtd1395.dtsi +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Realtek RTD1395 SoC - * - * Copyright (c) 2019 Andreas Färber - */ - -#include "rtd139x.dtsi" - -/ { - compatible = "realtek,rtd1395"; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - next-level-cache = <&l2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - next-level-cache = <&l2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - next-level-cache = <&l2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - next-level-cache = <&l2>; - }; - - l2: l2-cache { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; - -&arm_pmu { - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; -}; diff --git a/arch/arm64/boot/dts/realtek/rtd139x.dtsi b/arch/arm64/boot/dts/realtek/rtd139x.dtsi deleted file mode 100644 index a3c10ceeb..000000000 --- a/arch/arm64/boot/dts/realtek/rtd139x.dtsi +++ /dev/null @@ -1,193 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Realtek RTD1395 SoC family - * - * Copyright (c) 2019 Andreas Färber - */ - -/memreserve/ 0x0000000000000000 0x000000000002f000; -/memreserve/ 0x000000000002f000 0x00000000000d1000; - -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - rpc_comm: rpc@2f000 { - reg = <0x2f000 0x1000>; - }; - - rpc_ringbuf: rpc@1ffe000 { - reg = <0x1ffe000 0x4000>; - }; - - tee: tee@10100000 { - reg = <0x10100000 0xf00000>; - no-map; - }; - }; - - arm_pmu: arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - }; - - osc27M: osc { - compatible = "fixed-clock"; - clock-frequency = <27000000>; - #clock-cells = <0>; - clock-output-names = "osc27M"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */ - <0x98000000 0x98000000 0x68000000>; - - rbus: bus@98000000 { - compatible = "simple-bus"; - reg = <0x98000000 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x98000000 0x200000>; - - crt: syscon@0 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0x1000>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - }; - - iso: syscon@7000 { - compatible = "syscon", "simple-mfd"; - reg = <0x7000 0x1000>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7000 0x1000>; - }; - - sb2: syscon@1a000 { - compatible = "syscon", "simple-mfd"; - reg = <0x1a000 0x1000>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1a000 0x1000>; - }; - - misc: syscon@1b000 { - compatible = "syscon", "simple-mfd"; - reg = <0x1b000 0x1000>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1b000 0x1000>; - }; - - scpu_wrapper: syscon@1d000 { - compatible = "syscon", "simple-mfd"; - reg = <0x1d000 0x2000>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1d000 0x2000>; - }; - }; - - gic: interrupt-controller@ff011000 { - compatible = "arm,gic-400"; - reg = <0xff011000 0x1000>, - <0xff012000 0x2000>, - <0xff014000 0x2000>, - <0xff016000 0x2000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - }; -}; - -&crt { - reset1: reset-controller@0 { - compatible = "snps,dw-low-reset"; - reg = <0x0 0x4>; - #reset-cells = <1>; - }; - - reset2: reset-controller@4 { - compatible = "snps,dw-low-reset"; - reg = <0x4 0x4>; - #reset-cells = <1>; - }; - - reset3: reset-controller@8 { - compatible = "snps,dw-low-reset"; - reg = <0x8 0x4>; - #reset-cells = <1>; - }; - - reset4: reset-controller@50 { - compatible = "snps,dw-low-reset"; - reg = <0x50 0x4>; - #reset-cells = <1>; - }; -}; - -&iso { - iso_reset: reset-controller@88 { - compatible = "snps,dw-low-reset"; - reg = <0x88 0x4>; - #reset-cells = <1>; - }; - - wdt: watchdog@680 { - compatible = "realtek,rtd1295-watchdog"; - reg = <0x680 0x100>; - clocks = <&osc27M>; - }; - - uart0: serial@800 { - compatible = "snps,dw-apb-uart"; - reg = <0x800 0x400>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <27000000>; - resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; - status = "disabled"; - }; -}; - -&misc { - uart1: serial@200 { - compatible = "snps,dw-apb-uart"; - reg = <0x200 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <432000000>; - resets = <&reset2 RTD1295_RSTN_UR1>; - status = "disabled"; - }; - - uart2: serial@400 { - compatible = "snps,dw-apb-uart"; - reg = <0x400 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <432000000>; - resets = <&reset2 RTD1295_RSTN_UR2>; - status = "disabled"; - }; -}; diff --git a/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts b/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts deleted file mode 100644 index 90ed66814..000000000 --- a/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Copyright (c) 2019 Realtek Semiconductor Corp. - * Copyright (c) 2019 Andreas Färber - */ - -/dts-v1/; - -#include "rtd1619.dtsi" - -/ { - compatible = "realtek,mjolnir", "realtek,rtd1619"; - model = "Realtek Mjolnir EVB"; - - memory@2e000 { - device_type = "memory"; - reg = <0x2e000 0x7ffd2000>; /* boot ROM to 2 GiB */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; -}; - -/* debug console (J1) */ -&uart0 { - status = "okay"; -}; - -/* M.2 slot (CON4) */ -&uart1 { - status = "disabled"; -}; - -/* GPIO connector (T1) */ -&uart2 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/realtek/rtd1619.dtsi b/arch/arm64/boot/dts/realtek/rtd1619.dtsi deleted file mode 100644 index e52bf708b..000000000 --- a/arch/arm64/boot/dts/realtek/rtd1619.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Realtek RTD1619 SoC - * - * Copyright (c) 2019 Realtek Semiconductor Corp. - */ - -#include "rtd16xx.dtsi" - -/ { - compatible = "realtek,rtd1619"; -}; diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi deleted file mode 100644 index afba5f04c..000000000 --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi +++ /dev/null @@ -1,229 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -/* - * Realtek RTD16xx SoC family - * - * Copyright (c) 2019 Realtek Semiconductor Corp. - * Copyright (c) 2019 Andreas Färber - */ - -#include -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - rpc_comm: rpc@2f000 { - reg = <0x2f000 0x1000>; - }; - - rpc_ringbuf: rpc@1ffe000 { - reg = <0x1ffe000 0x4000>; - }; - - tee: tee@10100000 { - reg = <0x10100000 0xf00000>; - no-map; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - }; - - cpu1: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x100>; - enable-method = "psci"; - next-level-cache = <&l3>; - }; - - cpu2: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x200>; - enable-method = "psci"; - next-level-cache = <&l3>; - }; - - cpu3: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x300>; - enable-method = "psci"; - next-level-cache = <&l3>; - }; - - cpu4: cpu@400 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x400>; - enable-method = "psci"; - next-level-cache = <&l3>; - }; - - cpu5: cpu@500 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x500>; - enable-method = "psci"; - next-level-cache = <&l3>; - }; - - l2: l2-cache { - compatible = "cache"; - next-level-cache = <&l3>; - - }; - - l3: l3-cache { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - arm_pmu: pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, - <&cpu3>, <&cpu4>, <&cpu5>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - osc27M: osc { - compatible = "fixed-clock"; - clock-frequency = <27000000>; - clock-output-names = "osc27M"; - #clock-cells = <0>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00000000 0x00000000 0x0002e000>, /* boot ROM */ - <0x98000000 0x98000000 0x68000000>; - - rbus: bus@98000000 { - compatible = "simple-bus"; - reg = <0x98000000 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x98000000 0x200000>; - - crt: syscon@0 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0x1000>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1000>; - }; - - iso: syscon@7000 { - compatible = "syscon", "simple-mfd"; - reg = <0x7000 0x1000>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x7000 0x1000>; - }; - - sb2: syscon@1a000 { - compatible = "syscon", "simple-mfd"; - reg = <0x1a000 0x1000>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1a000 0x1000>; - }; - - misc: syscon@1b000 { - compatible = "syscon", "simple-mfd"; - reg = <0x1b000 0x1000>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1b000 0x1000>; - }; - - scpu_wrapper: syscon@1d000 { - compatible = "syscon", "simple-mfd"; - reg = <0x1d000 0x1000>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1d000 0x1000>; - }; - }; - - gic: interrupt-controller@ff100000 { - compatible = "arm,gic-v3"; - reg = <0xff100000 0x10000>, - <0xff140000 0xc0000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - }; - }; -}; - -&iso { - uart0: serial0@800 { - compatible = "snps,dw-apb-uart"; - reg = <0x800 0x400>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <27000000>; - status = "disabled"; - }; -}; - -&misc { - uart1: serial1@200 { - compatible = "snps,dw-apb-uart"; - reg = <0x200 0x400>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <432000000>; - status = "disabled"; - }; - - uart2: serial2@400 { - compatible = "snps,dw-apb-uart"; - reg = <0x400 0x400>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <432000000>; - status = "disabled"; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile deleted file mode 100644 index dffefe030..000000000 --- a/arch/arm64/boot/dts/renesas/Makefile +++ /dev/null @@ -1,58 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-beacon-rzg2m-kit.dtb -dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m.dtb -dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex.dtb -dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-idk-1110wr.dtb -dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2.dtb -dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex.dtb -dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb - -dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb -dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb -dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-idk-1110wr.dtb -dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2.dtb -dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2-ex.dtb -dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dtb - -dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb -dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874.dtb -dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874-idk-2121wr.dtb -dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874-mipi-2.1.dtb - -dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h.dtb -dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex.dtb -dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-idk-1110wr.dtb - -dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-salvator-x.dtb -dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb.dtb -dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb-kf.dtb - -dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-x.dtb -dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-xs.dtb -dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-ulcb.dtb -dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-ulcb-kf.dtb - -dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-salvator-x.dtb -dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-salvator-xs.dtb -dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-ulcb.dtb -dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-ulcb-kf.dtb - -dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-salvator-xs.dtb -dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-ulcb.dtb - -dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb -dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-xs.dtb -dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb.dtb -dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb-kf.dtb - -dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb -dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-v3msk.dtb - -dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb -dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-v3hsk.dtb - -dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb - -dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb - -dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb diff --git a/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi b/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi deleted file mode 100644 index dac6ff490..000000000 --- a/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the AISTARVISION MIPI Adapter V2.1 - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -/ { - ov5645_vdddo_1v8: 1p8v { - compatible = "regulator-fixed"; - regulator-name = "camera_vdddo"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ov5645_vdda_2v8: 2p8v { - compatible = "regulator-fixed"; - regulator-name = "camera_vdda"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - ov5645_vddd_1v5: 1p5v { - compatible = "regulator-fixed"; - regulator-name = "camera_vddd"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - imx219_vana_2v8: 2p8v { - compatible = "regulator-fixed"; - regulator-name = "camera_vana"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - imx219_vdig_1v8: 1p8v { - compatible = "regulator-fixed"; - regulator-name = "camera_vdig"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - imx219_vddl_1v2: 1p2v { - compatible = "regulator-fixed"; - regulator-name = "camera_vddl"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - osc25250_clk: osc25250_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; -}; - -&MIPI_PARENT_I2C { - ov5645: ov5645@3c { - compatible = "ovti,ov5645"; - reg = <0x3c>; - clock-names = "xclk"; - clocks = <&osc25250_clk>; - clock-frequency = <24000000>; - vdddo-supply = <&ov5645_vdddo_1v8>; - vdda-supply = <&ov5645_vdda_2v8>; - vddd-supply = <&ov5645_vddd_1v5>; - - port { - ov5645_ep: endpoint { - }; - }; - }; - - imx219: imx219@10 { - compatible = "sony,imx219"; - reg = <0x10>; - clocks = <&osc25250_clk>; - VANA-supply = <&imx219_vana_2v8>; - VDIG-supply = <&imx219_vdig_1v8>; - VDDL-supply = <&imx219_vddl_1v2>; - - port { - imx219_ep: endpoint { - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi deleted file mode 100644 index bc4bb5dd8..000000000 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ /dev/null @@ -1,758 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2020, Compass Electronics Group, LLC - */ - -#include -#include - -/ { - backlight_lvds: backlight-lvds { - compatible = "pwm-backlight"; - power-supply = <®_lcd>; - enable-gpios = <&gpio_exp1 3 GPIO_ACTIVE_LOW>; - pwms = <&pwm2 0 50000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - backlight_rgb: backlight-rgb { - compatible = "pwm-backlight"; - power-supply = <®_lcd>; - enable-gpios = <&gpio_exp1 7 GPIO_ACTIVE_LOW>; - pwms = <&pwm0 0 50000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - hdmi0-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi0_con: endpoint { - remote-endpoint = <&rcar_dw_hdmi0_out>; - }; - }; - }; - - keys { - compatible = "gpio-keys"; - - key-1 { - gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "Switch-1"; - wakeup-source; - debounce-interval = <20>; - }; - key-2 { - gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "Switch-2"; - wakeup-source; - debounce-interval = <20>; - }; - key-3 { - gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "Switch-3"; - wakeup-source; - debounce-interval = <20>; - }; - key-4 { - gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "Switch-4"; - wakeup-source; - debounce-interval = <20>; - }; - key-5 { - gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "Switch-4"; - wakeup-source; - debounce-interval = <20>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - led0 { - gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; - label = "LED0"; - linux,default-trigger = "heartbeat"; - }; - led1 { - gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - label = "LED1"; - }; - led2 { - gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - label = "LED2"; - }; - led3 { - gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; - label = "LED3"; - }; - }; - - lvds { - compatible = "panel-lvds"; - power-supply = <®_lcd_reset>; - width-mm = <223>; - height-mm = <125>; - backlight = <&backlight_lvds>; - data-mapping = "vesa-24"; - - panel-timing { - /* 800x480@60Hz */ - clock-frequency = <30000000>; - hactive = <800>; - vactive = <480>; - hsync-len = <48>; - hfront-porch = <40>; - hback-porch = <40>; - vfront-porch = <13>; - vback-porch = <29>; - vsync-len = <3>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <1>; - pixelclk-active = <0>; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - rgb { - /* Different LCD with compatible timings */ - compatible = "rocktech,rk070er9427"; - backlight = <&backlight_rgb>; - enable-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - power-supply = <®_lcd>; - port { - rgb_panel: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - }; - - reg_audio: regulator_audio { - compatible = "regulator-fixed"; - regulator-name = "audio-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio_exp4 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lcd: regulator-lcd { - compatible = "regulator-fixed"; - regulator-name = "lcd_panel_pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio_exp1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lcd_reset: regulator-lcd-reset { - compatible = "regulator-fixed"; - regulator-name = "nLCD_RESET"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_lcd>; - }; - - reg_cam0: regulator_camera { - compatible = "regulator-fixed"; - regulator-name = "reg_cam0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio_exp2 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_cam1: regulator_camera { - compatible = "regulator-fixed"; - regulator-name = "reg_cam1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio_exp2 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100000>; - }; - - sound_card { - compatible = "audio-graph-card"; - label = "rcar-sound"; - dais = <&rsnd_port0>, <&rsnd_port1>; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - regulator-always-on; - }; - - /* External DU dot clocks */ - x302_clk: x302-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <33000000>; - }; - - x304_clk: x304-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; -}; - -&audio_clk_a { - clock-frequency = <24576000>; - assigned-clocks = <&versaclock6_bb 4>; - assigned-clock-rates = <24576000>; -}; - -&audio_clk_b { - clock-frequency = <22579200>; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - renesas,can-clock-select = <0x0>; - status = "okay"; -}; - -&can1 { - pinctrl-0 = <&can1_pins>; - pinctrl-names = "default"; - renesas,can-clock-select = <0x0>; - status = "okay"; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&versaclock5 1>, - <&x302_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", - "dclkin.0", "dclkin.1", "dclkin.2"; -}; - -&du_out_rgb { - remote-endpoint = <&rgb_panel>; -}; - -&ehci0 { - dr_mode = "otg"; - status = "okay"; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>; -}; - -&ehci1 { - status = "okay"; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>; -}; - -&hdmi0 { - status = "okay"; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dw_hdmi0_in: endpoint { - remote-endpoint = <&du_out_hdmi0>; - }; - }; - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi0_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint1>; - }; - }; - }; -}; - -&hscif1 { - pinctrl-0 = <&hscif1_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - status = "okay"; -}; - -&hsusb { - dr_mode = "otg"; - status = "okay"; -}; - -&i2c2 { - status = "okay"; - clock-frequency = <100000>; - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - - gpio_exp2: gpio@21 { - compatible = "onnn,pca9654"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio_exp3: gpio@22 { - compatible = "onnn,pca9654"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio_exp4: gpio@23 { - compatible = "onnn,pca9654"; - reg = <0x23>; - gpio-controller; - #gpio-cells = <2>; - }; - - versaclock6_bb: clock-controller@6a { - compatible = "idt,5p49v6965"; - reg = <0x6a>; - #clock-cells = <1>; - clocks = <&x304_clk>; - clock-names = "xin"; - /* CSI0_MCLK, CSI1_MCLK, AUDIO_CLKIN, USB_HUB_MCLK_BB */ - assigned-clocks = <&versaclock6_bb 1>, - <&versaclock6_bb 2>, - <&versaclock6_bb 3>, - <&versaclock6_bb 4>; - assigned-clock-rates = <24000000>, <24000000>, <24000000>, <24576000>; - }; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; -}; - -&i2c5 { - status = "okay"; - clock-frequency = <100000>; - pinctrl-0 = <&i2c5_pins>; - pinctrl-names = "default"; - - codec: wm8962@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - DCVDD-supply = <®_audio>; - DBVDD-supply = <®_audio>; - AVDD-supply = <®_audio>; - CPVDD-supply = <®_audio>; - MICVDD-supply = <®_audio>; - PLLVDD-supply = <®_audio>; - SPKVDD1-supply = <®_audio>; - SPKVDD2-supply = <®_audio>; - gpio-cfg = < - 0x0000 /* 0:Default */ - 0x0000 /* 1:Default */ - 0x0000 /* 2:Default */ - 0x0000 /* 3:Default */ - 0x0000 /* 4:Default */ - 0x0000 /* 5:Default */ - >; - port { - wm8962_endpoint: endpoint { - remote-endpoint = <&rsnd_endpoint0>; - }; - }; - }; - - /* 0 - lcd_reset */ - /* 1 - lcd_pwr */ - /* 2 - lcd_select */ - /* 3 - backlight-enable */ - /* 4 - Touch_shdwn */ - /* 5 - LCD_H_pol */ - /* 6 - lcd_V_pol */ - gpio_exp1: gpio@20 { - compatible = "onnn,pca9654"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - touchscreen@26 { - compatible = "ilitek,ili2117"; - reg = <0x26>; - interrupt-parent = <&gpio5>; - interrupts = <9 IRQ_TYPE_EDGE_RISING>; - wakeup-source; - }; - - hd3ss3220@47 { - compatible = "ti,hd3ss3220"; - reg = <0x47>; - interrupt-parent = <&gpio6>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - hd3ss3220_ep: endpoint { - remote-endpoint = <&usb3_role_switch>; - }; - }; - }; - }; - }; -}; - -&lvds0 { - status = "okay"; - - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&ohci0 { - dr_mode = "otg"; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pciec0 { - status = "okay"; -}; - -&pciec1 { - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pfc { - can0_pins: can0 { - groups = "can0_data_a"; - function = "can0"; - }; - - can1_pins: can1 { - groups = "can1_data"; - function = "can1"; - }; - - du_pins: du { - groups = "du_rgb888", "du_sync", "du_clk_out_1", "du_disp"; - function = "du"; - }; - - i2c2_pins: i2c2 { - groups = "i2c2_a"; - function = "i2c2"; - }; - - i2c5_pins: i2c5 { - groups = "i2c5"; - function = "i2c5"; - }; - - led_pins: leds { - /* GP_0_4 , AVS1, AVS2, GP_7_3 */ - pins = "GP_0_4", "GP_7_0", "GP_7_1", "GP_7_3"; - bias-pull-down; - }; - - pwm0_pins: pwm0 { - groups = "pwm0"; - function = "pwm0"; - }; - - pwm2_pins: pwm2 { - groups = "pwm2_a"; - function = "pwm2_a"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sound_pins: sound { - groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; - function = "ssi"; - }; - - sound_clk_pins: sound_clk { - groups = "audio_clk_a_a"; - function = "audio_clk"; - }; - - usb0_pins: usb0 { - mux { - groups = "usb0"; - function = "usb0"; - }; - }; - - usb1_pins: usb1 { - mux { - groups = "usb1"; - function = "usb1"; - }; - }; - - usb30_pins: usb30 { - mux { - groups = "usb30"; - function = "usb30"; - }; - }; -}; - -&pwm0 { - pinctrl-0 = <&pwm0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pwm2 { - pinctrl-0 = <&pwm2_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins &sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - /* audio_clkout0/1/2/3 */ - #clock-cells = <1>; - clock-frequency = <11289600>; - - status = "okay"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A774A1_CLK_S0D4>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - rsnd_port0: port@0 { - reg = <0>; - rsnd_endpoint0: endpoint { - remote-endpoint = <&wm8962_endpoint>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint0>; - frame-master = <&rsnd_endpoint0>; - - playback = <&ssi1 &dvc1 &src1>; - capture = <&ssi0>; - }; - }; - rsnd_port1: port@1 { - reg = <0x01>; - rsnd_endpoint1: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint1>; - frame-master = <&rsnd_endpoint1>; - - playback = <&ssi2>; - }; - }; - }; -}; - -&rwdt { - status = "okay"; - timeout-sec = <60>; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&scif5 { - pinctrl-0 = <&scif5_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&ssi1 { - shared-pin; -}; - -&tmu0 { - status = "okay"; -}; - -&tmu1 { - status = "okay"; -}; - -&tmu2 { - status = "okay"; -}; - -&tmu3 { - status = "okay"; -}; - -&tmu4 { - status = "okay"; -}; - -&usb2_phy0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usb2_phy1 { - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usb3_peri0 { - companion = <&xhci0>; - status = "okay"; - usb-role-switch; - - port { - usb3_role_switch: endpoint { - remote-endpoint = <&hd3ss3220_ep>; - }; - }; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&vin0 { - status = "okay"; -}; -&vin1 { - status = "okay"; -}; -&vin2 { - status = "okay"; -}; -&vin3 { - status = "okay"; -}; -&vin4 { - status = "okay"; -}; -&vin5 { - status = "okay"; -}; -&vin6 { - status = "okay"; -}; -&vin7 { - status = "okay"; -}; - -&xhci0 -{ - pinctrl-0 = <&usb30_pins>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi deleted file mode 100644 index 929c7910c..000000000 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ /dev/null @@ -1,316 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2020, Compass Electronics Group, LLC - */ - -#include - -/ { - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x80000000>; - }; - - osc_32k: osc_32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "osc_32k"; - }; - - reg_1p8v: regulator0 { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator1 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - wlan_pwrseq: wlan_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pca9654 1 GPIO_ACTIVE_LOW>; - clocks = <&osc_32k>; - clock-names = "ext_clock"; - post-power-on-delay-ms = <80>; - }; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - phy-mode = "rgmii-rxid"; - phy-handle = <&phy0>; - rx-internal-delay-ps = <1800>; - tx-internal-delay-ps = <2000>; - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - interrupt-parent = <&gpio2>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; - }; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&gpio6 { - usb_hub_reset { - gpio-hog; - gpios = <10 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "usb-hub-reset"; - }; -}; - -&hscif0 { - pinctrl-0 = <&hscif0_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - shutdown-gpios = <&pca9654 2 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - device-wakeup-gpios = <&pca9654 5 GPIO_ACTIVE_HIGH>; - clocks = <&osc_32k>; - clock-names = "extclk"; - max-speed = <4000000>; - }; -}; - -&hscif2 { - status = "okay"; - pinctrl-0 = <&hscif2_pins>; - pinctrl-names = "default"; -}; - -&i2c4 { - status = "okay"; - clock-frequency = <400000>; - - pca9654: gpio@20 { - compatible = "onnn,pca9654"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - "i2c4_20_0", - "wl_reg_on", - "bt_reg_on", - "i2c4_20_3", - "i2c4_20_4", - "bt_dev_wake", - "i2c4_20_6", - "i2c4_20_7"; - }; - - pca9654_lte: gpio@21 { - compatible = "onnn,pca9654"; - reg = <0x21>; - interrupt-parent = <&gpio5>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - "i2c4_21_0", - "zoe_pwr_on", - "zoe_extint", - "zoe_reset_n", - "sara_reset", - "i2c4_21_5", - "sara_pwr_off", - "sara_networking_status"; - }; - - eeprom@50 { - compatible = "microchip,24c64", "atmel,24c64"; - pagesize = <32>; - read-only; /* Manufacturing EEPROM programmed at factory */ - reg = <0x50>; - }; - - rtc@51 { - compatible = "nxp,pcf85263"; - reg = <0x51>; - }; - - versaclock5: versaclock_som@6a { - compatible = "idt,5p49v6965"; - reg = <0x6a>; - #clock-cells = <1>; - clocks = <&x304_clk>; - clock-names = "xin"; - /* du_dotclkin0, du_dotclkin2, usb_extal, avb_txcrefclk */ - assigned-clocks = <&versaclock5 1>, - <&versaclock5 2>, - <&versaclock5 3>, - <&versaclock5 4>; - assigned-clock-rates = <33333333>, <33333333>, <50000000>, <125000000>; - }; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - avb_pins: avb { - mux { - groups = "avb_link", "avb_mdio", "avb_mii"; - function = "avb"; - }; - - pins_mdio { - groups = "avb_mdio"; - drive-strength = <24>; - }; - - pins_mii_tx { - pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", - "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; - drive-strength = <12>; - }; - }; - - scif2_pins: scif2 { - groups = "scif2_data_a"; - function = "scif2"; - }; - - hscif0_pins: hscif0 { - groups = "hscif0_data", "hscif0_ctrl"; - function = "hscif0"; - }; - - hscif1_pins: hscif1 { - groups = "hscif1_data_a", "hscif1_ctrl_a"; - function = "hscif1"; - }; - - hscif2_pins: hscif2 { - groups = "hscif2_data_a"; - function = "hscif2"; - }; - - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; - - scif5_pins: scif5 { - groups = "scif5_data_a"; - function = "scif5"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk_a"; - function = "scif_clk"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <1800>; - }; - - sdhi3_pins: sd3 { - groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; - function = "sdhi3"; - power-source = <1800>; - }; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&sdhi2 { - pinctrl-names = "default"; - pinctrl-0 = <&sdhi2_pins>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - non-removable; - cap-power-off-card; - pm-ignore-notify; - keep-power-in-suspend; - mmc-pwrseq = <&wlan_pwrseq>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio1>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "host-wake"; - }; -}; - -&sdhi3 { - pinctrl-0 = <&sdhi3_pins>; - pinctrl-1 = <&sdhi3_pins>; - pinctrl-names = "default", "state_uhs"; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - fixed-emmc-driver-type = <1>; - status = "okay"; -}; - -&usb2_clksel { - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, - <&versaclock5 3>, <&usb3s0_clk>; - status = "okay"; -}; - -&usb3s0_clk { - clock-frequency = <100000000>; -}; - -&vspb { - status = "okay"; -}; - -&vspi0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi deleted file mode 100644 index 20f8adc63..000000000 --- a/arch/arm64/boot/dts/renesas/cat875.dtsi +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Silicon Linux sub board for CAT874 (CAT875) - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -/ { - model = "Silicon Linux sub board for CAT874 (CAT875)"; - - aliases { - ethernet0 = &avb; - }; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - renesas,no-ether-link; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - interrupt-parent = <&gpio2>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - }; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&can1 { - pinctrl-0 = <&can1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pciec0 { - status = "okay"; -}; - -&pfc { - avb_pins: avb { - mux { - groups = "avb_mii"; - function = "avb"; - }; - }; - - can0_pins: can0 { - groups = "can0_data"; - function = "can0"; - }; - - can1_pins: can1 { - groups = "can1_data"; - function = "can1"; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi b/arch/arm64/boot/dts/renesas/hihope-common.dtsi deleted file mode 100644 index e8bf6f0c4..000000000 --- a/arch/arm64/boot/dts/renesas/hihope-common.dtsi +++ /dev/null @@ -1,380 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and - * HiHope RZ/G2[MN] Rev.[2.0/3.0/4.0] main board common parts - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -#include - -/ { - aliases { - serial0 = &scif2; - serial1 = &hscif0; - mmc0 = &sdhi3; - mmc1 = &sdhi0; - mmc2 = &sdhi2; - }; - - chosen { - bootargs = "ignore_loglevel"; - stdout-path = "serial0:115200n8"; - }; - - hdmi0-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi0_con: endpoint { - remote-endpoint = <&rcar_dw_hdmi0_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led1 { - gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; - }; - - led2 { - gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; - }; - - led3 { - gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - }; - - led4 { - gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_1p8v: regulator0 { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator1 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sound_card: sound { - compatible = "audio-graph-card"; - - label = "rcar-sound"; - - dais = <&rsnd_port>; - }; - - vbus0_usb2: regulator-vbus0-usb2 { - compatible = "regulator-fixed"; - - regulator-name = "USB20_VBUS0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - x302_clk: x302-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <33000000>; - }; - - x304_clk: x304-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; -}; - -&audio_clk_a { - clock-frequency = <22579200>; -}; - -&du { - status = "okay"; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&gpio6 { - usb1-reset { - gpio-hog; - gpios = <10 GPIO_ACTIVE_LOW>; - output-low; - line-name = "usb1-reset"; - }; -}; - -&hdmi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi0_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint>; - }; - }; - }; -}; - -&hscif0 { - pinctrl-0 = <&hscif0_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; -}; - -&hsusb { - dr_mode = "otg"; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <400000>; - status = "okay"; - - versaclock5: clock-generator@6a { - compatible = "idt,5p49v5923"; - reg = <0x6a>; - #clock-cells = <1>; - clocks = <&x304_clk>; - clock-names = "xin"; - }; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - hscif0_pins: hscif0 { - groups = "hscif0_data", "hscif0_ctrl"; - function = "hscif0"; - }; - - scif2_pins: scif2 { - groups = "scif2_data_a"; - function = "scif2"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk_a"; - function = "scif_clk"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data4", "sdhi2_ctrl"; - function = "sdhi2"; - power-source = <1800>; - }; - - sdhi3_pins: sd3 { - groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; - function = "sdhi3"; - power-source = <1800>; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - mux { - groups = "usb1"; - function = "usb1"; - }; - - ovc { - pins = "GP_6_27"; - bias-pull-up; - }; - }; - - usb30_pins: usb30 { - groups = "usb30"; - function = "usb30"; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi2 { - status = "okay"; - pinctrl-0 = <&sdhi2_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; - interrupt-parent = <&gpio2>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&sdhi3 { - pinctrl-0 = <&sdhi3_pins>; - pinctrl-1 = <&sdhi3_pins>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - fixed-emmc-driver-type = <1>; - status = "okay"; -}; - -&usb_extal_clk { - clock-frequency = <50000000>; -}; - -&usb2_phy0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - vbus-supply = <&vbus0_usb2>; - status = "okay"; -}; - -&usb2_phy1 { - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&usb3_peri0 { - phys = <&usb3_phy0>; - phy-names = "usb"; - - companion = <&xhci0>; - - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb3s0_clk { - clock-frequency = <100000000>; -}; - -&xhci0 { - pinctrl-0 = <&usb30_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/hihope-rev2.dtsi b/arch/arm64/boot/dts/renesas/hihope-rev2.dtsi deleted file mode 100644 index 8e2db1d6c..000000000 --- a/arch/arm64/boot/dts/renesas/hihope-rev2.dtsi +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2[MN] main board Rev.2.0 common - * parts - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include -#include "hihope-common.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - - bt_active_led { - label = "blue:bt"; - gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "hci0-power"; - default-state = "off"; - }; - - wlan_active_led { - label = "yellow:wlan"; - gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - }; - - wlan_en_reg: regulator-wlan_en { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <70000>; - - gpio = <&gpio_expander 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&hscif0 { - bluetooth { - compatible = "ti,wl1837-st"; - enable-gpios = <&gpio_expander 2 GPIO_ACTIVE_HIGH>; - }; -}; - -&i2c4 { - gpio_expander: gpio@20 { - compatible = "onnn,pca9654"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&pfc { - sound_clk_pins: sound_clk { - groups = "audio_clk_a_a"; - function = "audio_clk"; - }; -}; - -&rcar_sound { - pinctrl-0 = <&sound_clk_pins>; - pinctrl-names = "default"; - - status = "okay"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - rsnd_port: port { - rsnd_endpoint: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint>; - frame-master = <&rsnd_endpoint>; - - playback = <&ssi2>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi deleted file mode 100644 index 3046c07a2..000000000 --- a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and - * HiHope RZ/G2[MN] Rev.3.0/4.0 main board common parts - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include -#include "hihope-common.dtsi" - -/ { - audio_clkout: audio-clkout { - /* - * This is same as <&rcar_sound 0> - * but needed to avoid cs2000/rcar_sound probe dead-lock - */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12288000>; - }; - - wlan_en_reg: regulator-wlan_en { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <70000>; - - gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - x1801_clk: x1801-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; -}; - -&hscif0 { - bluetooth { - compatible = "ti,wl1837-st"; - enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; - }; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - status = "okay"; - - cs2000: clk_multiplier@4f { - #clock-cells = <0>; - compatible = "cirrus,cs2000-cp"; - reg = <0x4f>; - clocks = <&audio_clkout>, <&x1801_clk>; - clock-names = "clk_in", "ref_clk"; - - assigned-clocks = <&cs2000>; - assigned-clock-rates = <24576000>; /* 1/1 divide */ - }; -}; - -&pfc { - i2c2_pins: i2c2 { - groups = "i2c2_a"; - function = "i2c2"; - }; - - sound_clk_pins: sound_clk { - groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clkout_a"; - function = "audio_clk"; - }; - - sound_pins: sound { - groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; - function = "ssi"; - }; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins &sound_clk_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - /* audio_clkout0/1/2/3 */ - #clock-cells = <1>; - clock-frequency = <12288000 11289600>; - - /* update to */ - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&cs2000>, - <&audio_clk_c>, - <&cpg CPG_CORE CPG_AUDIO_CLK_I>; - - rsnd_port: port { - rsnd_endpoint: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint>; - frame-master = <&rsnd_endpoint>; - - playback = <&ssi2>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi deleted file mode 100644 index 40c5e8d6d..000000000 --- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the RZ/G2[MN] HiHope sub board LVDS common parts - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -/ { - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm0 0 50000>; - - brightness-levels = <0 2 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; -}; - -&gpio1 { - /* - * When GP1_20 is LOW LVDS0 is connected to the LVDS connector - * When GP1_20 is HIGH LVDS0 is connected to the LT8918L - */ - lvds-connector-en-gpio { - gpio-hog; - gpios = <20 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "lvds-connector-en-gpio"; - }; -}; - -&lvds0 { - ports { - port@1 { - lvds_connector: endpoint { - }; - }; - }; -}; - -&pfc { - pwm0_pins: pwm0 { - groups = "pwm0"; - function = "pwm0"; - }; -}; - -&pwm0 { - pinctrl-0 = <&pwm0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi deleted file mode 100644 index dde3a07bc..000000000 --- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the RZ/G2[HMN] HiHope sub board common parts - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -/ { - aliases { - ethernet0 = &avb; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - }; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - phy-handle = <&phy0>; - tx-internal-delay-ps = <2000>; - rx-internal-delay-ps = <1800>; - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - interrupt-parent = <&gpio2>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; - }; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&can1 { - pinctrl-0 = <&can1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pciec0 { - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - avb_pins: avb { - mux { - groups = "avb_link", "avb_mdio", "avb_mii"; - function = "avb"; - }; - - pins_mdio { - groups = "avb_mdio"; - drive-strength = <24>; - }; - - pins_mii_tx { - pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", - "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; - drive-strength = <12>; - }; - }; - - can0_pins: can0 { - groups = "can0_data_a"; - function = "can0"; - }; - - can1_pins: can1 { - groups = "can1_data"; - function = "can1"; - }; - - pwm0_pins: pwm0 { - groups = "pwm0"; - function = "pwm0"; - }; -}; - -&pwm0 { - pinctrl-0 = <&pwm0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts b/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts deleted file mode 100644 index ad26f5bf0..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2020, Compass Electronics Group, LLC - */ - -/dts-v1/; - -#include "r8a774a1.dtsi" -#include "beacon-renesom-som.dtsi" -#include "beacon-renesom-baseboard.dtsi" - -/ { - model = "Beacon EmbeddedWorks RZ/G2M Development Kit"; - compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1"; - - aliases { - serial0 = &scif2; - serial1 = &hscif0; - serial2 = &hscif1; - serial3 = &scif0; - serial4 = &hscif2; - serial5 = &scif5; - ethernet0 = &avb; - mmc0 = &sdhi3; - mmc1 = &sdhi0; - mmc2 = &sdhi2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-idk-1110wr.dts b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-idk-1110wr.dts deleted file mode 100644 index 06c04c59c..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-idk-1110wr.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 sub board connected - * to an Advantech IDK-1110WR 10.1" LVDS panel - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include "r8a774a1-hihope-rzg2m-ex.dts" -#include "hihope-rzg2-ex-lvds.dtsi" -#include "rzg2-advantech-idk-1110wr-panel.dtsi" - -&lvds0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts deleted file mode 100644 index a5ca86196..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 connected to - * sub board - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include "r8a774a1-hihope-rzg2m.dts" -#include "hihope-rzg2-ex.dtsi" - -/ { - model = "HopeRun HiHope RZ/G2M with sub board"; - compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m", - "renesas,r8a774a1"; -}; - -/* SW43 should be OFF, if in ON state SATA port will be activated */ -&pciec1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dts b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dts deleted file mode 100644 index c0e9d8ca4..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2M Rev.2.0 sub board connected to an - * Advantech IDK-1110WR 10.1" LVDS panel - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include "r8a774a1-hihope-rzg2m-rev2-ex.dts" -#include "hihope-rzg2-ex-lvds.dtsi" -#include "rzg2-advantech-idk-1110wr-panel.dtsi" - -&lvds0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-rev2-ex.dts b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-rev2-ex.dts deleted file mode 100644 index 2221cf6ae..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-rev2-ex.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2M Rev.2.0 connected to sub board - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -#include "r8a774a1-hihope-rzg2m-rev2.dts" -#include "hihope-rzg2-ex.dtsi" - -/ { - model = "HopeRun HiHope RZ/G2M (Rev.2.0) with sub board"; - compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m", - "renesas,r8a774a1"; -}; - -/* SW43 should be OFF, if in ON state SATA port will be activated */ -&pciec1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-rev2.dts b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-rev2.dts deleted file mode 100644 index bb18f6ee2..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-rev2.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2M Rev.2.0 main board - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a774a1.dtsi" -#include "hihope-rev2.dtsi" - -/ { - model = "HopeRun HiHope RZ/G2M main board (Rev.2.0) based on r8a774a1"; - compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x80000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&versaclock5 1>, - <&x302_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", - "dclkin.0", "dclkin.1", "dclkin.2"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m.dts b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m.dts deleted file mode 100644 index 25ae255de..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2M Rev.3.0/4.0 main board - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a774a1.dtsi" -#include "hihope-rev4.dtsi" - -/ { - model = "HopeRun HiHope RZ/G2M main board based on r8a774a1"; - compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x80000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&versaclock5 1>, - <&x302_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", - "dclkin.0", "dclkin.1", "dclkin.2"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi deleted file mode 100644 index a5ebe574f..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ /dev/null @@ -1,2845 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the r8a774a1 SoC - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ - -#include -#include -#include -#include - -#define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4 - -/ { - compatible = "renesas,r8a774a1"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c_dvfs; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - }; - - cluster1_opp: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&a57_0>; - }; - core1 { - cpu = <&a57_1>; - }; - }; - - cluster1 { - core0 { - cpu = <&a53_0>; - }; - core1 { - cpu = <&a53_1>; - }; - core2 { - cpu = <&a53_2>; - }; - core3 { - cpu = <&a53_3>; - }; - }; - }; - - a57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A774A1_PD_CA57_CPU0>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - dynamic-power-coefficient = <854>; - clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x1>; - device_type = "cpu"; - power-domains = <&sysc R8A774A1_PD_CA57_CPU1>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a53_0: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x100>; - device_type = "cpu"; - power-domains = <&sysc R8A774A1_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - #cooling-cells = <2>; - dynamic-power-coefficient = <277>; - clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <560>; - }; - - a53_1: cpu@101 { - compatible = "arm,cortex-a53"; - reg = <0x101>; - device_type = "cpu"; - power-domains = <&sysc R8A774A1_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <560>; - }; - - a53_2: cpu@102 { - compatible = "arm,cortex-a53"; - reg = <0x102>; - device_type = "cpu"; - power-domains = <&sysc R8A774A1_PD_CA53_CPU2>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <560>; - }; - - a53_3: cpu@103 { - compatible = "arm,cortex-a53"; - reg = <0x103>; - device_type = "cpu"; - power-domains = <&sysc R8A774A1_PD_CA53_CPU3>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <560>; - }; - - L2_CA57: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A774A1_PD_CA57_SCU>; - cache-unified; - cache-level = <2>; - }; - - L2_CA53: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A774A1_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; - }; - - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, <&a57_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a774a1-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a774a1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 4>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a774a1"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a774a1-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a774a1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a774a1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a774a1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a774a1-cpg-mssr"; - reg = <0 0xe6150000 0 0x0bb0>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a774a1-rst"; - reg = <0 0xe6160000 0 0x018c>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a774a1-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a774a1-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 125>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 125>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 123>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 123>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 122>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 122>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 121>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 121>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774a1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774a1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774a1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774a1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774a1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774a1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774a1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a774a1", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a774a1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a774a1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a774a1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a774a1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a774a1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a774a1", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb2_clksel: clock-controller@e6590630 { - compatible = "renesas,r8a774a1-rcar-usb2-clock-sel", - "renesas,rcar-gen3-usb2-clock-sel"; - reg = <0 0xe6590630 0 0x02>; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, - <&usb_extal_clk>, <&usb3s0_clk>; - clock-names = "ehci_ohci", "hs-usb-if", - "usb_extal", "usb_xtal"; - #clock-cells = <0>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - reset-names = "ehci_ohci", "hs-usb-if"; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a774a1-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a774a1-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a774a1-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; - status = "disabled"; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a774a1", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a774a1", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a774a1", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: iommu@e6570000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp: iommu@ec670000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: iommu@fd800000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 5>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv1: iommu@fd950000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xfd950000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: iommu@fe6b0000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; - power-domains = <&sysc R8A774A1_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a774a1"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a774a1", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a774a1", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A774A1_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a774a1", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A774A1_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a774a1-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A774A1_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a774a1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a774a1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a774a1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a774a1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a774a1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a774a1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A774A1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a774a1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a774a1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a774a1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a774a1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin0>; - }; - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 810>; - renesas,id = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin1>; - }; - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin2>; - }; - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin3>; - }; - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin4>; - }; - vin4csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin5>; - }; - vin5csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin5>; - }; - }; - }; - }; - - vin6: video@e6ef6000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 805>; - renesas,id = <6>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin6csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin6>; - }; - vin6csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin6>; - }; - }; - }; - }; - - vin7: video@e6ef7000 { - compatible = "renesas,vin-r8a774a1"; - reg = <0 0xe6ef7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 804>; - renesas,id = <7>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin7csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin7>; - }; - vin7csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin7>; - }; - }; - }; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A774A1_CLK_S0D4>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>; - dma-names = "rx", "tx"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>; - dma-names = "rx", "tx"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>; - dma-names = "rx", "tx"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>; - dma-names = "rx", "tx"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>; - dma-names = "rx", "tx"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>; - dma-names = "rx", "tx"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>; - dma-names = "rx", "tx"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>; - dma-names = "rx", "tx"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>; - dma-names = "rx", "tx"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssiu { - ssiu00: ssiu-0 { - dmas = <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx"; - }; - ssiu01: ssiu-1 { - dmas = <&audma0 0x35>, <&audma1 0x36>; - dma-names = "rx", "tx"; - }; - ssiu02: ssiu-2 { - dmas = <&audma0 0x37>, <&audma1 0x38>; - dma-names = "rx", "tx"; - }; - ssiu03: ssiu-3 { - dmas = <&audma0 0x47>, <&audma1 0x48>; - dma-names = "rx", "tx"; - }; - ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; - dma-names = "rx", "tx"; - }; - ssiu05: ssiu-5 { - dmas = <&audma0 0x43>, <&audma1 0x44>; - dma-names = "rx", "tx"; - }; - ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; - dma-names = "rx", "tx"; - }; - ssiu07: ssiu-7 { - dmas = <&audma0 0x53>, <&audma1 0x54>; - dma-names = "rx", "tx"; - }; - ssiu10: ssiu-8 { - dmas = <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx"; - }; - ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; - dma-names = "rx", "tx"; - }; - ssiu12: ssiu-10 { - dmas = <&audma0 0x57>, <&audma1 0x58>; - dma-names = "rx", "tx"; - }; - ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; - dma-names = "rx", "tx"; - }; - ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; - dma-names = "rx", "tx"; - }; - ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; - dma-names = "rx", "tx"; - }; - ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; - dma-names = "rx", "tx"; - }; - ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; - dma-names = "rx", "tx"; - }; - ssiu20: ssiu-16 { - dmas = <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx"; - }; - ssiu21: ssiu-17 { - dmas = <&audma0 0x67>, <&audma1 0x68>; - dma-names = "rx", "tx"; - }; - ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; - dma-names = "rx", "tx"; - }; - ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; - dma-names = "rx", "tx"; - }; - ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; - dma-names = "rx", "tx"; - }; - ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; - dma-names = "rx", "tx"; - }; - ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; - dma-names = "rx", "tx"; - }; - ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; - dma-names = "rx", "tx"; - }; - ssiu30: ssiu-24 { - dmas = <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx"; - }; - ssiu31: ssiu-25 { - dmas = <&audma0 0x21>, <&audma1 0x22>; - dma-names = "rx", "tx"; - }; - ssiu32: ssiu-26 { - dmas = <&audma0 0x23>, <&audma1 0x24>; - dma-names = "rx", "tx"; - }; - ssiu33: ssiu-27 { - dmas = <&audma0 0x25>, <&audma1 0x26>; - dma-names = "rx", "tx"; - }; - ssiu34: ssiu-28 { - dmas = <&audma0 0x27>, <&audma1 0x28>; - dma-names = "rx", "tx"; - }; - ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; - dma-names = "rx", "tx"; - }; - ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; - dma-names = "rx", "tx"; - }; - ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; - dma-names = "rx", "tx"; - }; - ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx"; - }; - ssiu41: ssiu-33 { - dmas = <&audma0 0x17>, <&audma1 0x18>; - dma-names = "rx", "tx"; - }; - ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; - dma-names = "rx", "tx"; - }; - ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; - dma-names = "rx", "tx"; - }; - ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; - dma-names = "rx", "tx"; - }; - ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; - dma-names = "rx", "tx"; - }; - ssiu46: ssiu-38 { - dmas = <&audma0 0x31>, <&audma1 0x32>; - dma-names = "rx", "tx"; - }; - ssiu47: ssiu-39 { - dmas = <&audma0 0x33>, <&audma1 0x34>; - dma-names = "rx", "tx"; - }; - ssiu50: ssiu-40 { - dmas = <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx"; - }; - ssiu60: ssiu-41 { - dmas = <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx"; - }; - ssiu70: ssiu-42 { - dmas = <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx"; - }; - ssiu80: ssiu-43 { - dmas = <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx"; - }; - ssiu90: ssiu-44 { - dmas = <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx"; - }; - ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; - dma-names = "rx", "tx"; - }; - ssiu92: ssiu-46 { - dmas = <&audma0 0x81>, <&audma1 0x82>; - dma-names = "rx", "tx"; - }; - ssiu93: ssiu-47 { - dmas = <&audma0 0x83>, <&audma1 0x84>; - dma-names = "rx", "tx"; - }; - ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; - dma-names = "rx", "tx"; - }; - ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; - dma-names = "rx", "tx"; - }; - ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; - dma-names = "rx", "tx"; - }; - ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; - dma-names = "rx", "tx"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a774a1", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, - <&ipmmu_mp 2>, <&ipmmu_mp 3>, - <&ipmmu_mp 4>, <&ipmmu_mp 5>, - <&ipmmu_mp 6>, <&ipmmu_mp 7>, - <&ipmmu_mp 8>, <&ipmmu_mp 9>, - <&ipmmu_mp 10>, <&ipmmu_mp 11>, - <&ipmmu_mp 12>, <&ipmmu_mp 13>, - <&ipmmu_mp 14>, <&ipmmu_mp 15>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a774a1", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, - <&ipmmu_mp 18>, <&ipmmu_mp 19>, - <&ipmmu_mp 20>, <&ipmmu_mp 21>, - <&ipmmu_mp 22>, <&ipmmu_mp 23>, - <&ipmmu_mp 24>, <&ipmmu_mp 25>, - <&ipmmu_mp 26>, <&ipmmu_mp 27>, - <&ipmmu_mp 28>, <&ipmmu_mp 29>, - <&ipmmu_mp 30>, <&ipmmu_mp 31>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a774a1", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a774a1-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 1>; - phy-names = "usb"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 2>; - phy-names = "usb"; - companion = <&ohci1>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a774a1", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a774a1", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a774a1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-r8a774a1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; - }; - - sdhi2: mmc@ee140000 { - compatible = "renesas,sdhi-r8a774a1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi3: mmc@ee160000 { - compatible = "renesas,sdhi-r8a774a1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a774a1", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - pciec1: pcie@ee800000 { - compatible = "renesas,pcie-r8a774a1", - "renesas,pcie-rcar-gen3"; - reg = <0 0xee800000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, - <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, - <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, - <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - pciec0_ep: pcie-ep@fe000000 { - compatible = "renesas,r8a774a1-pcie-ep", - "renesas,rcar-gen3-pcie-ep"; - reg = <0x0 0xfe000000 0 0x80000>, - <0x0 0xfe100000 0 0x100000>, - <0x0 0xfe200000 0 0x200000>, - <0x0 0x30000000 0 0x8000000>, - <0x0 0x38000000 0 0x8000000>; - reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 319>; - clock-names = "pcie"; - resets = <&cpg 319>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pciec1_ep: pcie-ep@ee800000 { - compatible = "renesas,r8a774a1-pcie-ep", - "renesas,rcar-gen3-pcie-ep"; - reg = <0x0 0xee800000 0 0x80000>, - <0x0 0xee900000 0 0x100000>, - <0x0 0xeea00000 0 0x200000>, - <0x0 0xc0000000 0 0x8000000>, - <0x0 0xc8000000 0 0x8000000>; - reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 318>; - clock-names = "pcie"; - resets = <&cpg 318>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A774A1_PD_A3VC>; - resets = <&cpg 119>; - renesas,fcp = <&fcpf0>; - }; - - fcpf0: fcp@fe950000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe950000 0 0x200>; - clocks = <&cpg CPG_MOD 615>; - power-domains = <&sysc R8A774A1_PD_A3VC>; - resets = <&cpg 615>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A774A1_PD_A3VC>; - resets = <&cpg 607>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - - fcpvd2: fcp@fea37000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea37000 0 0x200>; - clocks = <&cpg CPG_MOD 601>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 601>; - iommus = <&ipmmu_vi0 10>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A774A1_PD_A3VC>; - resets = <&cpg 611>; - iommus = <&ipmmu_vc0 19>; - }; - - vspb: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A774A1_PD_A3VC>; - resets = <&cpg 626>; - - renesas,fcp = <&fcpvb0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 623>; - - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 622>; - - renesas,fcp = <&fcpvd1>; - }; - - vspd2: vsp@fea30000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea30000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 621>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 621>; - - renesas,fcp = <&fcpvd2>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A774A1_PD_A3VC>; - resets = <&cpg 631>; - - renesas,fcp = <&fcpvi0>; - }; - - csi20: csi2@fea80000 { - compatible = "renesas,r8a774a1-csi2"; - reg = <0 0xfea80000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi20vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi20>; - }; - csi20vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi20>; - }; - csi20vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi20>; - }; - csi20vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi20>; - }; - csi20vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi20>; - }; - csi20vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi20>; - }; - csi20vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi20>; - }; - csi20vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi20>; - }; - }; - }; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a774a1-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - csi40vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi40>; - }; - csi40vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi40>; - }; - csi40vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi40>; - }; - csi40vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi40>; - }; - }; - - }; - }; - - hdmi0: hdmi@fead0000 { - compatible = "renesas,r8a774a1-hdmi", - "renesas,rcar-gen3-hdmi"; - reg = <0 0xfead0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 729>, - <&cpg CPG_CORE R8A774A1_CLK_HDMI>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 729>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dw_hdmi0_in: endpoint { - remote-endpoint = <&du_out_hdmi0>; - }; - }; - port@1 { - reg = <1>; - }; - port@2 { - /* HDMI sound */ - reg = <2>; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a774a1"; - reg = <0 0xfeb00000 0 0x70000>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>; - clock-names = "du.0", "du.1", "du.2"; - resets = <&cpg 724>, <&cpg 722>; - reset-names = "du.0", "du.2"; - status = "disabled"; - - renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_hdmi0: endpoint { - remote-endpoint = <&dw_hdmi0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a774a1-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - sensor_thermal1: sensor-thermal1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - sustainable-power = <3874>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal2: sensor-thermal2 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - sustainable-power = <3874>; - - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal3: sensor-thermal3 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; - sustainable-power = <3874>; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a57_0 0 2>; - contribution = <1024>; - }; - map1 { - trip = <&target>; - cooling-device = <&a53_0 0 2>; - contribution = <1024>; - }; - }; - trips { - target: trip-point1 { - temperature = <100000>; - hysteresis = <1000>; - type = "passive"; - }; - - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-idk-1110wr.dts b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-idk-1110wr.dts deleted file mode 100644 index 4b5154f02..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-idk-1110wr.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2N Rev.3.0/4.0 with sub board connected - * to an Advantech IDK-1110WR 10.1" LVDS panel - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include "r8a774b1-hihope-rzg2n-ex.dts" -#include "hihope-rzg2-ex-lvds.dtsi" -#include "rzg2-advantech-idk-1110wr-panel.dtsi" - -&lvds0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts deleted file mode 100644 index 60d7c8ade..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2N Rev.3.0/4.0 connected to - * sub board - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include "r8a774b1-hihope-rzg2n.dts" -#include "hihope-rzg2-ex.dtsi" - -/ { - model = "HopeRun HiHope RZ/G2N with sub board"; - compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n", - "renesas,r8a774b1"; -}; - -/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */ -&sata { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dts b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dts deleted file mode 100644 index e730b3b25..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2N Rev.2.0 with sub board connected - * to an Advantech IDK-1110WR 10.1" LVDS panel - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include "r8a774b1-hihope-rzg2n-rev2-ex.dts" -#include "hihope-rzg2-ex-lvds.dtsi" -#include "rzg2-advantech-idk-1110wr-panel.dtsi" - -&lvds0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2-ex.dts b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2-ex.dts deleted file mode 100644 index 2e5e1de04..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2-ex.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2N Rev.2.0 connected to sub board - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -#include "r8a774b1-hihope-rzg2n-rev2.dts" -#include "hihope-rzg2-ex.dtsi" - -/ { - model = "HopeRun HiHope RZ/G2N (Rev.2.0) with sub board"; - compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n", - "renesas,r8a774b1"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2.dts b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2.dts deleted file mode 100644 index c69ca5cf6..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2N Rev.2.0 main board - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a774b1.dtsi" -#include "hihope-rev2.dtsi" - -/ { - model = "HopeRun HiHope RZ/G2N main board (Rev.2.0) based on r8a774b1"; - compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@480000000 { - device_type = "memory"; - reg = <0x4 0x80000000 0x0 0x80000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&x302_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.3", - "dclkin.0", "dclkin.1", "dclkin.3"; -}; - -&sdhi3 { - mmc-hs400-1_8v; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n.dts b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n.dts deleted file mode 100644 index f1883cbd1..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2N main board Rev.3.0/4.0 - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a774b1.dtsi" -#include "hihope-rev4.dtsi" - -/ { - model = "HopeRun HiHope RZ/G2N main board based on r8a774b1"; - compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@480000000 { - device_type = "memory"; - reg = <0x4 0x80000000 0x0 0x80000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&x302_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.3", - "dclkin.0", "dclkin.1", "dclkin.3"; -}; - -&sdhi3 { - mmc-hs400-1_8v; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi deleted file mode 100644 index 20003a41a..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ /dev/null @@ -1,2685 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the r8a774b1 SoC - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -#include -#include -#include -#include - -#define CPG_AUDIO_CLK_I R8A774B1_CLK_S0D4 - -/ { - compatible = "renesas,r8a774b1"; - #address-cells = <2>; - #size-cells = <2>; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A774B1_PD_CA57_CPU0>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - #cooling-cells = <2>; - dynamic-power-coefficient = <854>; - clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - }; - - a57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x1>; - device_type = "cpu"; - power-domains = <&sysc R8A774B1_PD_CA57_CPU1>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - }; - - L2_CA57: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A774B1_PD_CA57_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, <&a57_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a774b1-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a774b1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 4>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a774b1"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a774b1-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a774b1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a774b1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a774b1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a774b1-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a774b1-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a774b1-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a774b1-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a774b1", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 125>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 125>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 123>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 123>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 122>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 122>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 121>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 121>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774b1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774b1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774b1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774b1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774b1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774b1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774b1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a774b1", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a774b1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a774b1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a774b1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a774b1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a774b1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a774b1", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb2_clksel: clock-controller@e6590630 { - compatible = "renesas,r8a774b1-rcar-usb2-clock-sel", - "renesas,rcar-gen3-usb2-clock-sel"; - reg = <0 0xe6590630 0 0x02>; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, - <&usb_extal_clk>, <&usb3s0_clk>; - clock-names = "ehci_ohci", "hs-usb-if", - "usb_extal", "usb_xtal"; - #clock-cells = <0>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - reset-names = "ehci_ohci", "hs-usb-if"; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a774b1-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a774b1-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a774b1-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; - status = "disabled"; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a774b1", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a774b1", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a774b1", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: iommu@e6570000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp: iommu@ec670000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: iommu@fd800000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: iommu@fe6b0000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A774B1_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vp0: iommu@fe990000 { - compatible = "renesas,ipmmu-r8a774b1"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A774B1_PD_A3VP>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a774b1", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a774b1", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A774B1_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a774b1", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A774B1_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a774b1-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A774B1_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a774b1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a774b1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a774b1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a774b1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a774b1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a774b1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A774B1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a774b1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a774b1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a774b1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a774b1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin0>; - }; - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 810>; - renesas,id = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin1>; - }; - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin2>; - }; - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin3>; - }; - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin4>; - }; - vin4csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin5>; - }; - vin5csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin5>; - }; - }; - }; - }; - - vin6: video@e6ef6000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 805>; - renesas,id = <6>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin6csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin6>; - }; - vin6csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin6>; - }; - }; - }; - }; - - vin7: video@e6ef7000 { - compatible = "renesas,vin-r8a774b1"; - reg = <0 0xe6ef7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 804>; - renesas,id = <7>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin7csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin7>; - }; - vin7csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin7>; - }; - }; - }; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a774b1", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A774B1_CLK_S0D4>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>; - dma-names = "rx", "tx"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>; - dma-names = "rx", "tx"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>; - dma-names = "rx", "tx"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>; - dma-names = "rx", "tx"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>; - dma-names = "rx", "tx"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>; - dma-names = "rx", "tx"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>; - dma-names = "rx", "tx"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>; - dma-names = "rx", "tx"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>; - dma-names = "rx", "tx"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssiu { - ssiu00: ssiu-0 { - dmas = <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx"; - }; - ssiu01: ssiu-1 { - dmas = <&audma0 0x35>, <&audma1 0x36>; - dma-names = "rx", "tx"; - }; - ssiu02: ssiu-2 { - dmas = <&audma0 0x37>, <&audma1 0x38>; - dma-names = "rx", "tx"; - }; - ssiu03: ssiu-3 { - dmas = <&audma0 0x47>, <&audma1 0x48>; - dma-names = "rx", "tx"; - }; - ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; - dma-names = "rx", "tx"; - }; - ssiu05: ssiu-5 { - dmas = <&audma0 0x43>, <&audma1 0x44>; - dma-names = "rx", "tx"; - }; - ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; - dma-names = "rx", "tx"; - }; - ssiu07: ssiu-7 { - dmas = <&audma0 0x53>, <&audma1 0x54>; - dma-names = "rx", "tx"; - }; - ssiu10: ssiu-8 { - dmas = <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx"; - }; - ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; - dma-names = "rx", "tx"; - }; - ssiu12: ssiu-10 { - dmas = <&audma0 0x57>, <&audma1 0x58>; - dma-names = "rx", "tx"; - }; - ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; - dma-names = "rx", "tx"; - }; - ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; - dma-names = "rx", "tx"; - }; - ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; - dma-names = "rx", "tx"; - }; - ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; - dma-names = "rx", "tx"; - }; - ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; - dma-names = "rx", "tx"; - }; - ssiu20: ssiu-16 { - dmas = <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx"; - }; - ssiu21: ssiu-17 { - dmas = <&audma0 0x67>, <&audma1 0x68>; - dma-names = "rx", "tx"; - }; - ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; - dma-names = "rx", "tx"; - }; - ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; - dma-names = "rx", "tx"; - }; - ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; - dma-names = "rx", "tx"; - }; - ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; - dma-names = "rx", "tx"; - }; - ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; - dma-names = "rx", "tx"; - }; - ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; - dma-names = "rx", "tx"; - }; - ssiu30: ssiu-24 { - dmas = <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx"; - }; - ssiu31: ssiu-25 { - dmas = <&audma0 0x21>, <&audma1 0x22>; - dma-names = "rx", "tx"; - }; - ssiu32: ssiu-26 { - dmas = <&audma0 0x23>, <&audma1 0x24>; - dma-names = "rx", "tx"; - }; - ssiu33: ssiu-27 { - dmas = <&audma0 0x25>, <&audma1 0x26>; - dma-names = "rx", "tx"; - }; - ssiu34: ssiu-28 { - dmas = <&audma0 0x27>, <&audma1 0x28>; - dma-names = "rx", "tx"; - }; - ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; - dma-names = "rx", "tx"; - }; - ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; - dma-names = "rx", "tx"; - }; - ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; - dma-names = "rx", "tx"; - }; - ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx"; - }; - ssiu41: ssiu-33 { - dmas = <&audma0 0x17>, <&audma1 0x18>; - dma-names = "rx", "tx"; - }; - ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; - dma-names = "rx", "tx"; - }; - ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; - dma-names = "rx", "tx"; - }; - ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; - dma-names = "rx", "tx"; - }; - ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; - dma-names = "rx", "tx"; - }; - ssiu46: ssiu-38 { - dmas = <&audma0 0x31>, <&audma1 0x32>; - dma-names = "rx", "tx"; - }; - ssiu47: ssiu-39 { - dmas = <&audma0 0x33>, <&audma1 0x34>; - dma-names = "rx", "tx"; - }; - ssiu50: ssiu-40 { - dmas = <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx"; - }; - ssiu60: ssiu-41 { - dmas = <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx"; - }; - ssiu70: ssiu-42 { - dmas = <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx"; - }; - ssiu80: ssiu-43 { - dmas = <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx"; - }; - ssiu90: ssiu-44 { - dmas = <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx"; - }; - ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; - dma-names = "rx", "tx"; - }; - ssiu92: ssiu-46 { - dmas = <&audma0 0x81>, <&audma1 0x82>; - dma-names = "rx", "tx"; - }; - ssiu93: ssiu-47 { - dmas = <&audma0 0x83>, <&audma1 0x84>; - dma-names = "rx", "tx"; - }; - ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; - dma-names = "rx", "tx"; - }; - ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; - dma-names = "rx", "tx"; - }; - ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; - dma-names = "rx", "tx"; - }; - ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; - dma-names = "rx", "tx"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a774b1", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a774b1", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a774b1", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a774b1-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 1>; - phy-names = "usb"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 2>; - phy-names = "usb"; - companion = <&ohci1>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a774b1", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a774b1", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a774b1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-r8a774b1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; - }; - - sdhi2: mmc@ee140000 { - compatible = "renesas,sdhi-r8a774b1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi3: mmc@ee160000 { - compatible = "renesas,sdhi-r8a774b1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - sata: sata@ee300000 { - compatible = "renesas,sata-r8a774b1", - "renesas,rcar-gen3-sata"; - reg = <0 0xee300000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a774b1", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - pciec1: pcie@ee800000 { - compatible = "renesas,pcie-r8a774b1", - "renesas,pcie-rcar-gen3"; - reg = <0 0xee800000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, - <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, - <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, - <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - pciec0_ep: pcie-ep@fe000000 { - compatible = "renesas,r8a774b1-pcie-ep", - "renesas,rcar-gen3-pcie-ep"; - reg = <0x0 0xfe000000 0 0x80000>, - <0x0 0xfe100000 0 0x100000>, - <0x0 0xfe200000 0 0x200000>, - <0x0 0x30000000 0 0x8000000>, - <0x0 0x38000000 0 0x8000000>; - reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 319>; - clock-names = "pcie"; - resets = <&cpg 319>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pciec1_ep: pcie-ep@ee800000 { - compatible = "renesas,r8a774b1-pcie-ep", - "renesas,rcar-gen3-pcie-ep"; - reg = <0x0 0xee800000 0 0x80000>, - <0x0 0xee900000 0 0x100000>, - <0x0 0xeea00000 0 0x200000>, - <0x0 0xc0000000 0 0x8000000>, - <0x0 0xc8000000 0 0x8000000>; - reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 318>; - clock-names = "pcie"; - resets = <&cpg 318>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A774B1_PD_A3VP>; - resets = <&cpg 119>; - renesas,fcp = <&fcpf0>; - }; - - fcpf0: fcp@fe950000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe950000 0 0x200>; - clocks = <&cpg CPG_MOD 615>; - power-domains = <&sysc R8A774B1_PD_A3VP>; - resets = <&cpg 615>; - }; - - vspb: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A774B1_PD_A3VP>; - resets = <&cpg 626>; - - renesas,fcp = <&fcpvb0>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A774B1_PD_A3VP>; - resets = <&cpg 631>; - - renesas,fcp = <&fcpvi0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 623>; - - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 622>; - - renesas,fcp = <&fcpvd1>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A774B1_PD_A3VP>; - resets = <&cpg 607>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 603>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 602>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A774B1_PD_A3VP>; - resets = <&cpg 611>; - }; - - csi20: csi2@fea80000 { - compatible = "renesas,r8a774b1-csi2"; - reg = <0 0xfea80000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi20vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi20>; - }; - csi20vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi20>; - }; - csi20vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi20>; - }; - csi20vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi20>; - }; - csi20vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi20>; - }; - csi20vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi20>; - }; - csi20vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi20>; - }; - csi20vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi20>; - }; - }; - }; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a774b1-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - csi40vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi40>; - }; - csi40vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi40>; - }; - csi40vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi40>; - }; - csi40vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi40>; - }; - }; - }; - }; - - hdmi0: hdmi@fead0000 { - compatible = "renesas,r8a774b1-hdmi", - "renesas,rcar-gen3-hdmi"; - reg = <0 0xfead0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 729>, - <&cpg CPG_CORE R8A774B1_CLK_HDMI>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 729>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dw_hdmi0_in: endpoint { - remote-endpoint = <&du_out_hdmi0>; - }; - }; - port@1 { - reg = <1>; - }; - port@2 { - /* HDMI sound */ - reg = <2>; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a774b1"; - reg = <0 0xfeb00000 0 0x80000>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>; - clock-names = "du.0", "du.1", "du.3"; - resets = <&cpg 724>, <&cpg 722>; - reset-names = "du.0", "du.3"; - status = "disabled"; - - renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_hdmi0: endpoint { - remote-endpoint = <&dw_hdmi0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a774b1-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - sensor_thermal1: sensor-thermal1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - sustainable-power = <2439>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal2: sensor-thermal2 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - sustainable-power = <2439>; - - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal3: sensor-thermal3 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; - sustainable-power = <2439>; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a57_0 0 2>; - contribution = <1024>; - }; - }; - trips { - target: trip-point1 { - temperature = <100000>; - hysteresis = <1000>; - type = "passive"; - }; - - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts deleted file mode 100644 index c4b50a5e3..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts +++ /dev/null @@ -1,422 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874) - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a774c0.dtsi" -#include -#include - -/ { - model = "Silicon Linux RZ/G2E 96board platform (CAT874)"; - compatible = "si-linux,cat874", "renesas,r8a774c0"; - - aliases { - serial0 = &scif2; - serial1 = &hscif2; - mmc0 = &sdhi0; - mmc1 = &sdhi3; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&tda19988_out>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led0 { - gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; - label = "LED0"; - }; - - led1 { - gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - label = "LED1"; - }; - - led2 { - gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; - label = "LED2"; - }; - - led3 { - gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; - label = "LED3"; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - reg_12p0v: regulator-12p0v { - compatible = "regulator-fixed"; - regulator-name = "D12.0V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-boot-on; - regulator-always-on; - }; - - sound: sound { - compatible = "simple-audio-card"; - - simple-audio-card,name = "CAT874 HDMI sound"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sndcpu>; - simple-audio-card,frame-master = <&sndcpu>; - - sndcodec: simple-audio-card,codec { - sound-dai = <&tda19988>; - }; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - wlan_en_reg: fixedregulator { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <70000>; - - gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - x13_clk: x13 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; -}; - -&audio_clk_a { - clock-frequency = <22579200>; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&x13_clk>; - clock-names = "du.0", "du.1", "dclkin.0"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&tda19988_in>; - }; - }; - }; -}; - -&ehci0 { - dr_mode = "host"; - status = "okay"; -}; - -&extal_clk { - clock-frequency = <48000000>; -}; - -&hscif2 { - pinctrl-0 = <&hscif2_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "ti,wl1837-st"; - enable-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; - - hd3ss3220@47 { - compatible = "ti,hd3ss3220"; - reg = <0x47>; - interrupt-parent = <&gpio6>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - hd3ss3220_ep: endpoint { - remote-endpoint = <&usb3_role_switch>; - }; - }; - }; - }; - }; - - tda19988: tda19988@70 { - compatible = "nxp,tda998x"; - reg = <0x70>; - interrupt-parent = <&gpio1>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - - video-ports = <0x234501>; - - #sound-dai-cells = <0>; - audio-ports = ; - clocks = <&rcar_sound 1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - tda19988_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - - port@1 { - reg = <1>; - tda19988_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - rtc@32 { - compatible = "epson,rx8571"; - reg = <0x32>; - }; -}; - -&lvds0 { - status = "okay"; - - clocks = <&cpg CPG_MOD 727>, <&x13_clk>, <&extal_clk>; - clock-names = "fck", "dclkin.0", "extal"; -}; - -&ohci0 { - dr_mode = "host"; - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pciec0 { - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; -}; - -&pfc { - du_pins: du { - groups = "du_rgb888", "du_clk_out_0", "du_sync", "du_disp", - "du_clk_in_0"; - function = "du"; - }; - - hscif2_pins: hscif2 { - groups = "hscif2_data_a", "hscif2_ctrl_a"; - function = "hscif2"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1_b"; - function = "i2c1"; - }; - - scif2_pins: scif2 { - groups = "scif2_data_a"; - function = "scif2"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi3_pins: sd3 { - groups = "sdhi3_data4", "sdhi3_ctrl"; - function = "sdhi3"; - power-source = <1800>; - }; - - sound_clk_pins: sound_clk { - groups = "audio_clkout1_a"; - function = "audio_clk"; - }; - - sound_pins: sound { - groups = "ssi01239_ctrl", "ssi0_data"; - function = "ssi"; - }; - - usb30_pins: usb30 { - groups = "usb30", "usb30_id"; - function = "usb30"; - }; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins &sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - /* audio_clkout0/1/2/3 */ - #clock-cells = <1>; - clock-frequency = <11289600>; - - status = "okay"; - - rcar_sound,dai { - dai0 { - playback = <&ssi0 &src0 &dvc0>; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi3 { - status = "okay"; - pinctrl-0 = <&sdhi3_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&usb2_phy0 { - renesas,no-otg-pins; - status = "okay"; -}; - -&usb3_peri0 { - companion = <&xhci0>; - status = "okay"; - usb-role-switch; - - port { - usb3_role_switch: endpoint { - remote-endpoint = <&hd3ss3220_ep>; - }; - }; -}; - -&xhci0 { - pinctrl-0 = <&usb30_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts b/arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts deleted file mode 100644 index a7b27d09f..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Silicon Linux RZ/G2E evaluation kit (EK874), - * connected to an Advantech IDK-2121WR 21.5" LVDS panel - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -#include "r8a774c0-ek874.dts" - -/ { - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm5 0 50000>; - - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - - power-supply = <®_12p0v>; - enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; - }; - - panel-lvds { - compatible = "advantech,idk-2121wr", "panel-lvds"; - - width-mm = <476>; - height-mm = <268>; - - data-mapping = "vesa-24"; - - panel-timing { - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hsync-len = <44>; - hfront-porch = <88>; - hback-porch = <148>; - vfront-porch = <4>; - vback-porch = <36>; - vsync-len = <5>; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dual-lvds-odd-pixels; - panel_in0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@1 { - reg = <1>; - dual-lvds-even-pixels; - panel_in1: endpoint { - remote-endpoint = <&lvds1_out>; - }; - }; - }; - }; -}; - -&gpio0 { - /* - * When GP0_17 is low LVDS[01] are connected to the LVDS connector - * When GP0_17 is high LVDS[01] are connected to the LT8918L - */ - lvds-connector-en-gpio{ - gpio-hog; - gpios = <17 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "lvds-connector-en-gpio"; - }; -}; - -&lvds0 { - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&panel_in0>; - }; - }; - }; -}; - -&lvds1 { - status = "okay"; - - clocks = <&cpg CPG_MOD 727>, <&x13_clk>, <&extal_clk>; - clock-names = "fck", "dclkin.0", "extal"; - - ports { - port@1 { - lvds1_out: endpoint { - remote-endpoint = <&panel_in1>; - }; - }; - }; -}; - -&pfc { - pwm5_pins: pwm5 { - groups = "pwm5_a"; - function = "pwm5"; - }; -}; - -&pwm5 { - pinctrl-0 = <&pwm5_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts b/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts deleted file mode 100644 index f0829e905..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874) - * connected with aistarvision-mipi-v2-adapter board - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a774c0-ek874.dts" -#define MIPI_PARENT_I2C i2c3 -#include "aistarvision-mipi-adapter-2.1.dtsi" - -/ { - model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875) with aistarvision-mipi-v2-adapter board"; - compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0"; -}; - -&i2c3 { - status = "okay"; -}; - -&vin4 { - status = "okay"; -}; - -&vin5 { - status = "okay"; -}; - -&csi40 { - status = "okay"; - - ports { - port { - csi40_in: endpoint { - clock-lanes = <0>; - data-lanes = <1 2>; - remote-endpoint = <&ov5645_ep>; - }; - }; - }; -}; - -&ov5645 { - enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; - - port { - ov5645_ep: endpoint { - clock-lanes = <0>; - data-lanes = <1 2>; - remote-endpoint = <&csi40_in>; - }; - }; -}; - -&imx219 { - port { - imx219_ep: endpoint { - clock-lanes = <0>; - data-lanes = <1 2>; - link-frequencies = /bits/ 64 <456000000>; - /* uncomment remote-endpoint property to tie imx219 to - * CSI2 also make sure remote-endpoint for ov5645 camera - * is commented and remote endpoint phandle in csi40_in - * is imx219_ep - */ - /* remote-endpoint = <&csi40_in>; */ - }; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts deleted file mode 100644 index e7b6619ab..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Silicon Linux RZ/G2E evaluation kit (EK874) - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -#include "r8a774c0-cat874.dts" -#include "cat875.dtsi" - -/ { - model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875)"; - compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi deleted file mode 100644 index e0e54342c..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ /dev/null @@ -1,1979 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the RZ/G2E (R8A774C0) SoC - * - * Copyright (C) 2018-2019 Renesas Electronics Corp. - */ - -#include -#include -#include - -/ { - compatible = "renesas,r8a774c0"; - #address-cells = <2>; - #size-cells = <2>; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster1_opp: opp_table10 { - compatible = "operating-points-v2"; - opp-shared; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a53_0: cpu@0 { - compatible = "arm,cortex-a53"; - reg = <0>; - device_type = "cpu"; - #cooling-cells = <2>; - power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - dynamic-power-coefficient = <277>; - clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - a53_1: cpu@1 { - compatible = "arm,cortex-a53"; - reg = <1>; - device_type = "cpu"; - power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - L2_CA53: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A774C0_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, <&a53_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc: soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a774c0-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a774c0", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a774c0", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 23>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a774c0", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a774c0", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a774c0", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 11>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a774c0", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 20>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a774c0", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a774c0"; - reg = <0 0xe6060000 0 0x508>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a774c0-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a774c0-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a774c0-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a774c0-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a774c0-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; - clock-names = "extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a774c0-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a774c0-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - thermal: thermal@e6190000 { - compatible = "renesas,thermal-r8a774c0"; - reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 125>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 125>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 123>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 123>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 122>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 122>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 121>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 121>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c7: i2c@e6690000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774c0", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6690000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1003>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 1003>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a774c0"; - reg = <0 0xe60b0000 0 0x15>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a774c0", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a774c0", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a774c0", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a774c0", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a774c0", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a774c0", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a774c0-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a774c0-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a774c0", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a774c0", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a774c0", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: iommu@e6570000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp: iommu@ec670000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: iommu@fd800000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: iommu@fe6b0000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A774C0_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vp0: iommu@fe990000 { - compatible = "renesas,ipmmu-r8a774c0"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a774c0", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a774c0", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A774C0_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a774c0", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A774C0_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a774c0-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A774C0_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a774c0", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a774c0", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a774c0", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a774c0", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a774c0", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a774c0", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x5b>, <&dmac0 0x5a>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a774c0", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a774c0", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac0 0x43>, <&dmac0 0x42>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a774c0", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a774c0", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a774c0"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi40: endpoint@2 { - reg = <2>; - remote-endpoint= <&csi40vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a774c0"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi40: endpoint@2 { - reg = <2>; - remote-endpoint= <&csi40vin5>; - }; - }; - }; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a774c0", - "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A774C0_CLK_ZA2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma0 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma0 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma0 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma0 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma0 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma0 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma0 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma0 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma0 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma0 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma0 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma0 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma0 0x02>, - <&audma0 0x15>, <&audma0 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma0 0x04>, - <&audma0 0x49>, <&audma0 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma0 0x06>, - <&audma0 0x63>, <&audma0 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma0 0x08>, - <&audma0 0x6f>, <&audma0 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma0 0x0a>, - <&audma0 0x71>, <&audma0 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma0 0x0c>, - <&audma0 0x73>, <&audma0 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma0 0x0e>, - <&audma0 0x75>, <&audma0 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma0 0x10>, - <&audma0 0x79>, <&audma0 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma0 0x12>, - <&audma0 0x7b>, <&audma0 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma0 0x14>, - <&audma0 0x7d>, <&audma0 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a774c0", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, - <&ipmmu_mp 2>, <&ipmmu_mp 3>, - <&ipmmu_mp 4>, <&ipmmu_mp 5>, - <&ipmmu_mp 6>, <&ipmmu_mp 7>, - <&ipmmu_mp 8>, <&ipmmu_mp 9>, - <&ipmmu_mp 10>, <&ipmmu_mp 11>, - <&ipmmu_mp 12>, <&ipmmu_mp 13>, - <&ipmmu_mp 14>, <&ipmmu_mp 15>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a774c0", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a774c0-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a774c0", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a774c0", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-r8a774c0", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; - }; - - sdhi3: mmc@ee160000 { - compatible = "renesas,sdhi-r8a774c0", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a774c0", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - pciec0_ep: pcie-ep@fe000000 { - compatible = "renesas,r8a774c0-pcie-ep", - "renesas,rcar-gen3-pcie-ep"; - reg = <0x0 0xfe000000 0 0x80000>, - <0x0 0xfe100000 0 0x100000>, - <0x0 0xfe200000 0 0x200000>, - <0x0 0x30000000 0 0x8000000>, - <0x0 0x38000000 0 0x8000000>; - reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 319>; - clock-names = "pcie"; - resets = <&cpg 319>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - status = "disabled"; - }; - - vspb0: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 626>; - renesas,fcp = <&fcpvb0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x7000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 623>; - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x7000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 622>; - renesas,fcp = <&fcpvd1>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 631>; - renesas,fcp = <&fcpvi0>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 607>; - iommus = <&ipmmu_vp0 5>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 611>; - iommus = <&ipmmu_vp0 8>; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a774c0-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin4: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin4csi40>; - }; - csi40vin5: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin5csi40>; - }; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a774c0"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - resets = <&cpg 724>; - reset-names = "du.0"; - renesas,vsps = <&vspd0 0>, <&vspd1 0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - - port@2 { - reg = <2>; - du_out_lvds1: endpoint { - remote-endpoint = <&lvds1_in>; - }; - }; - }; - }; - - lvds0: lvds-encoder@feb90000 { - compatible = "renesas,r8a774c0-lvds"; - reg = <0 0xfeb90000 0 0x20>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - renesas,companion = <&lvds1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - lvds1: lvds-encoder@feb90100 { - compatible = "renesas,r8a774c0-lvds"; - reg = <0 0xfeb90100 0 0x20>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; - resets = <&cpg 726>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds1_in: endpoint { - remote-endpoint = <&du_out_lvds1>; - }; - }; - - port@1 { - reg = <1>; - lvds1_out: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <0>; - thermal-sensors = <&thermal 0>; - sustainable-power = <717>; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a53_0 0 2>; - contribution = <1024>; - }; - }; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - - target: trip-point1 { - temperature = <100000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts deleted file mode 100644 index 3b7339127..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-idk-1110wr.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2H sub board connected - * to an Advantech IDK-1110WR 10.1" LVDS panel - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include "r8a774e1-hihope-rzg2h-ex.dts" -#include "hihope-rzg2-ex-lvds.dtsi" -#include "rzg2-advantech-idk-1110wr-panel.dtsi" - -&lvds0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts deleted file mode 100644 index 812995939..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2H sub board - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include "r8a774e1-hihope-rzg2h.dts" -#include "hihope-rzg2-ex.dtsi" - -/ { - model = "HopeRun HiHope RZ/G2H with sub board"; - compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2h", - "renesas,r8a774e1"; -}; - -/* Set SW43 = ON and SW1001[7] = OFF for SATA port to be activated */ -&sata { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts deleted file mode 100644 index 9525d5ed6..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the HiHope RZ/G2H main board - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a774e1.dtsi" -#include "hihope-rev4.dtsi" - -/ { - model = "HopeRun HiHope RZ/G2H main board based on r8a774e1"; - compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@500000000 { - device_type = "memory"; - reg = <0x5 0x00000000 0x0 0x80000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&x302_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.3", - "dclkin.0", "dclkin.1", "dclkin.3"; -}; - -&sdhi3 { - mmc-hs400-1_8v; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi deleted file mode 100644 index 2e6c12a46..000000000 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ /dev/null @@ -1,2967 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the r8a774e1 SoC - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include -#include -#include -#include - -#define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4 - -/ { - compatible = "renesas,r8a774e1"; - #address-cells = <2>; - #size-cells = <2>; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - }; - - cluster1_opp: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&a57_0>; - }; - core1 { - cpu = <&a57_1>; - }; - core2 { - cpu = <&a57_2>; - }; - core3 { - cpu = <&a57_3>; - }; - }; - - cluster1 { - core0 { - cpu = <&a53_0>; - }; - core1 { - cpu = <&a53_1>; - }; - core2 { - cpu = <&a53_2>; - }; - core3 { - cpu = <&a53_3>; - }; - }; - }; - - a57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - dynamic-power-coefficient = <854>; - clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x1>; - device_type = "cpu"; - power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_2: cpu@2 { - compatible = "arm,cortex-a57"; - reg = <0x2>; - device_type = "cpu"; - power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_3: cpu@3 { - compatible = "arm,cortex-a57"; - reg = <0x3>; - device_type = "cpu"; - power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a53_0: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x100>; - device_type = "cpu"; - power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - #cooling-cells = <2>; - dynamic-power-coefficient = <277>; - clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_1: cpu@101 { - compatible = "arm,cortex-a53"; - reg = <0x101>; - device_type = "cpu"; - power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_2: cpu@102 { - compatible = "arm,cortex-a53"; - reg = <0x102>; - device_type = "cpu"; - power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_3: cpu@103 { - compatible = "arm,cortex-a53"; - reg = <0x103>; - device_type = "cpu"; - power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - L2_CA57: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A774E1_PD_CA57_SCU>; - cache-unified; - cache-level = <2>; - }; - - L2_CA53: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A774E1_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <400>; - exit-latency-us = <500>; - min-residency-us = <4000>; - }; - - CPU_SLEEP_1: cpu-sleep-1 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <700>; - exit-latency-us = <700>; - min-residency-us = <5000>; - }; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; - }; - - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a774e1-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - interrupts = ; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a774e1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a774e1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a774e1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a774e1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a774e1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a774e1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a774e1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a774e1", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 4>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a774e1"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a774e1-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a774e1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a774e1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a774e1-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a774e1-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a774e1-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a774e1-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a774e1-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 125>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 125>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 123>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 123>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 122>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 122>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 121>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 121>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774e1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774e1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774e1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774e1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774e1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774e1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a774e1", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a774e1", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a774e1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A774E1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a774e1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A774E1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a774e1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A774E1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a774e1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A774E1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a774e1", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A774E1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a774e1", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb2_clksel: clock-controller@e6590630 { - compatible = "renesas,r8a774e1-rcar-usb2-clock-sel", - "renesas,rcar-gen3-usb2-clock-sel"; - reg = <0 0xe6590630 0 0x02>; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, - <&usb_extal_clk>, <&usb3s0_clk>; - clock-names = "ehci_ohci", "hs-usb-if", - "usb_extal", "usb_xtal"; - #clock-cells = <0>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - reset-names = "ehci_ohci", "hs-usb-if"; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a774e1-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a774e1-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a774e1-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; - status = "disabled"; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a774e1", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a774e1", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a774e1", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: iommu@e6570000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp0: iommu@ec670000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: iommu@fd800000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv1: iommu@fd950000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xfd950000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 7>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv2: iommu@fd960000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xfd960000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv3: iommu@fd970000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xfd970000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: iommu@fe6b0000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A774E1_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vc1: iommu@fe6f0000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xfe6f0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 13>; - power-domains = <&sysc R8A774E1_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vi1: iommu@febe0000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xfebe0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 15>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vp0: iommu@fe990000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - #iommu-cells = <1>; - }; - - ipmmu_vp1: iommu@fe980000 { - compatible = "renesas,ipmmu-r8a774e1"; - reg = <0 0xfe980000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 17>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a774e1", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - rx-internal-delay-ps = <0>; - tx-internal-delay-ps = <0>; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a774e1", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A774E1_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a774e1", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A774E1_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a774e1-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A774E1_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a774e1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A774E1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a774e1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A774E1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a774e1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A774E1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a774e1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A774E1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a774e1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A774E1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a774e1", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A774E1_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a774e1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a774e1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a774e1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a774e1", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a774e1"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin0>; - }; - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a774e1"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 810>; - renesas,id = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin1>; - }; - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a774e1"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin2>; - }; - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a774e1"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin3>; - }; - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a774e1"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a774e1"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin5>; - }; - }; - }; - }; - - vin6: video@e6ef6000 { - compatible = "renesas,vin-r8a774e1"; - reg = <0 0xe6ef6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 805>; - renesas,id = <6>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin6csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin6>; - }; - }; - }; - }; - - vin7: video@e6ef7000 { - compatible = "renesas,vin-r8a774e1"; - reg = <0 0xe6ef7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 804>; - renesas,id = <7>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin7csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin7>; - }; - }; - }; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A774E1_CLK_S0D4>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssiu { - ssiu00: ssiu-0 { - dmas = <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx"; - }; - ssiu01: ssiu-1 { - dmas = <&audma0 0x35>, <&audma1 0x36>; - dma-names = "rx", "tx"; - }; - ssiu02: ssiu-2 { - dmas = <&audma0 0x37>, <&audma1 0x38>; - dma-names = "rx", "tx"; - }; - ssiu03: ssiu-3 { - dmas = <&audma0 0x47>, <&audma1 0x48>; - dma-names = "rx", "tx"; - }; - ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; - dma-names = "rx", "tx"; - }; - ssiu05: ssiu-5 { - dmas = <&audma0 0x43>, <&audma1 0x44>; - dma-names = "rx", "tx"; - }; - ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; - dma-names = "rx", "tx"; - }; - ssiu07: ssiu-7 { - dmas = <&audma0 0x53>, <&audma1 0x54>; - dma-names = "rx", "tx"; - }; - ssiu10: ssiu-8 { - dmas = <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx"; - }; - ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; - dma-names = "rx", "tx"; - }; - ssiu12: ssiu-10 { - dmas = <&audma0 0x57>, <&audma1 0x58>; - dma-names = "rx", "tx"; - }; - ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; - dma-names = "rx", "tx"; - }; - ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; - dma-names = "rx", "tx"; - }; - ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; - dma-names = "rx", "tx"; - }; - ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; - dma-names = "rx", "tx"; - }; - ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; - dma-names = "rx", "tx"; - }; - ssiu20: ssiu-16 { - dmas = <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx"; - }; - ssiu21: ssiu-17 { - dmas = <&audma0 0x67>, <&audma1 0x68>; - dma-names = "rx", "tx"; - }; - ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; - dma-names = "rx", "tx"; - }; - ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; - dma-names = "rx", "tx"; - }; - ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; - dma-names = "rx", "tx"; - }; - ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; - dma-names = "rx", "tx"; - }; - ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; - dma-names = "rx", "tx"; - }; - ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; - dma-names = "rx", "tx"; - }; - ssiu30: ssiu-24 { - dmas = <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx"; - }; - ssiu31: ssiu-25 { - dmas = <&audma0 0x21>, <&audma1 0x22>; - dma-names = "rx", "tx"; - }; - ssiu32: ssiu-26 { - dmas = <&audma0 0x23>, <&audma1 0x24>; - dma-names = "rx", "tx"; - }; - ssiu33: ssiu-27 { - dmas = <&audma0 0x25>, <&audma1 0x26>; - dma-names = "rx", "tx"; - }; - ssiu34: ssiu-28 { - dmas = <&audma0 0x27>, <&audma1 0x28>; - dma-names = "rx", "tx"; - }; - ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; - dma-names = "rx", "tx"; - }; - ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; - dma-names = "rx", "tx"; - }; - ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; - dma-names = "rx", "tx"; - }; - ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx"; - }; - ssiu41: ssiu-33 { - dmas = <&audma0 0x17>, <&audma1 0x18>; - dma-names = "rx", "tx"; - }; - ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; - dma-names = "rx", "tx"; - }; - ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; - dma-names = "rx", "tx"; - }; - ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; - dma-names = "rx", "tx"; - }; - ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; - dma-names = "rx", "tx"; - }; - ssiu46: ssiu-38 { - dmas = <&audma0 0x31>, <&audma1 0x32>; - dma-names = "rx", "tx"; - }; - ssiu47: ssiu-39 { - dmas = <&audma0 0x33>, <&audma1 0x34>; - dma-names = "rx", "tx"; - }; - ssiu50: ssiu-40 { - dmas = <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx"; - }; - ssiu60: ssiu-41 { - dmas = <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx"; - }; - ssiu70: ssiu-42 { - dmas = <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx"; - }; - ssiu80: ssiu-43 { - dmas = <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx"; - }; - ssiu90: ssiu-44 { - dmas = <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx"; - }; - ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; - dma-names = "rx", "tx"; - }; - ssiu92: ssiu-46 { - dmas = <&audma0 0x81>, <&audma1 0x82>; - dma-names = "rx", "tx"; - }; - ssiu93: ssiu-47 { - dmas = <&audma0 0x83>, <&audma1 0x84>; - dma-names = "rx", "tx"; - }; - ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; - dma-names = "rx", "tx"; - }; - ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; - dma-names = "rx", "tx"; - }; - ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; - dma-names = "rx", "tx"; - }; - ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>; - dma-names = "rx", "tx"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>; - dma-names = "rx", "tx"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>; - dma-names = "rx", "tx"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>; - dma-names = "rx", "tx"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>; - dma-names = "rx", "tx"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>; - dma-names = "rx", "tx"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>; - dma-names = "rx", "tx"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>; - dma-names = "rx", "tx"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>; - dma-names = "rx", "tx"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>; - dma-names = "rx", "tx"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a774e1", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, - <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, - <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, - <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, - <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, - <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, - <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, - <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a774e1", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, - <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, - <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, - <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, - <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, - <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, - <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, - <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a774e1", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a774e1-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 1>; - phy-names = "usb"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 2>; - phy-names = "usb"; - companion = <&ohci1>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a774e1", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a774e1", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 702>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a774e1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 314>; - iommus = <&ipmmu_ds1 32>; - status = "disabled"; - }; - - sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-r8a774e1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 313>; - iommus = <&ipmmu_ds1 33>; - status = "disabled"; - }; - - sdhi2: mmc@ee140000 { - compatible = "renesas,sdhi-r8a774e1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 312>; - iommus = <&ipmmu_ds1 34>; - status = "disabled"; - }; - - sdhi3: mmc@ee160000 { - compatible = "renesas,sdhi-r8a774e1", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 311>; - iommus = <&ipmmu_ds1 35>; - status = "disabled"; - }; - - sata: sata@ee300000 { - compatible = "renesas,sata-r8a774e1", - "renesas,rcar-gen3-sata"; - reg = <0 0xee300000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 815>; - iommus = <&ipmmu_hc 2>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a774e1", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - pciec1: pcie@ee800000 { - compatible = "renesas,pcie-r8a774e1", - "renesas,pcie-rcar-gen3"; - reg = <0 0xee800000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, - <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, - <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, - <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - pciec0_ep: pcie-ep@fe000000 { - compatible = "renesas,r8a774e1-pcie-ep", - "renesas,rcar-gen3-pcie-ep"; - reg = <0x0 0xfe000000 0 0x80000>, - <0x0 0xfe100000 0 0x100000>, - <0x0 0xfe200000 0 0x200000>, - <0x0 0x30000000 0 0x8000000>, - <0x0 0x38000000 0 0x8000000>; - reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 319>; - clock-names = "pcie"; - resets = <&cpg 319>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pciec1_ep: pcie-ep@ee800000 { - compatible = "renesas,r8a774e1-pcie-ep", - "renesas,rcar-gen3-pcie-ep"; - reg = <0x0 0xee800000 0 0x80000>, - <0x0 0xee900000 0 0x100000>, - <0x0 0xeea00000 0 0x200000>, - <0x0 0xc0000000 0 0x8000000>, - <0x0 0xc8000000 0 0x8000000>; - reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 318>; - clock-names = "pcie"; - resets = <&cpg 318>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - status = "disabled"; - }; - - vspbc: vsp@fe920000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe920000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 624>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 624>; - - renesas,fcp = <&fcpvb1>; - }; - - vspbd: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 626>; - - renesas,fcp = <&fcpvb0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 623>; - - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 622>; - - renesas,fcp = <&fcpvd1>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 631>; - - renesas,fcp = <&fcpvi0>; - }; - - vspi1: vsp@fe9b0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9b0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 630>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 630>; - - renesas,fcp = <&fcpvi1>; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 119>; - renesas,fcp = <&fcpf0>; - }; - - fdp1@fe944000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe944000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 118>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 118>; - renesas,fcp = <&fcpf1>; - }; - - fcpf0: fcp@fe950000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe950000 0 0x200>; - clocks = <&cpg CPG_MOD 615>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 615>; - }; - - fcpf1: fcp@fe951000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe951000 0 0x200>; - clocks = <&cpg CPG_MOD 614>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 614>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 607>; - }; - - fcpvb1: fcp@fe92f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe92f000 0 0x200>; - clocks = <&cpg CPG_MOD 606>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 606>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 611>; - }; - - fcpvi1: fcp@fe9bf000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9bf000 0 0x200>; - clocks = <&cpg CPG_MOD 610>; - power-domains = <&sysc R8A774E1_PD_A3VP>; - resets = <&cpg 610>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 603>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 602>; - }; - - csi20: csi2@fea80000 { - compatible = "renesas,r8a774e1-csi2"; - reg = <0 0xfea80000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi20vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi20>; - }; - csi20vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi20>; - }; - csi20vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi20>; - }; - csi20vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi20>; - }; - csi20vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi20>; - }; - csi20vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi20>; - }; - csi20vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi20>; - }; - csi20vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi20>; - }; - }; - }; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a774e1-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - }; - }; - }; - - hdmi0: hdmi@fead0000 { - compatible = "renesas,r8a774e1-hdmi", - "renesas,rcar-gen3-hdmi"; - reg = <0 0xfead0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 729>, - <&cpg CPG_CORE R8A774E1_CLK_HDMI>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 729>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dw_hdmi0_in: endpoint { - remote-endpoint = <&du_out_hdmi0>; - }; - }; - port@1 { - reg = <1>; - }; - port@2 { - /* HDMI sound */ - reg = <2>; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a774e1"; - reg = <0 0xfeb00000 0 0x80000>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>; - clock-names = "du.0", "du.1", "du.3"; - resets = <&cpg 724>, <&cpg 722>; - reset-names = "du.0", "du.3"; - status = "disabled"; - - renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_hdmi0: endpoint { - remote-endpoint = <&dw_hdmi0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a774e1-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - sensor_thermal1: sensor-thermal1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - sustainable-power = <6313>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal2: sensor-thermal2 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - sustainable-power = <6313>; - - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal3: sensor-thermal3 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; - sustainable-power = <6313>; - - trips { - target: trip-point1 { - temperature = <100000>; - hysteresis = <1000>; - type = "passive"; - }; - - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a57_0 0 2>; - contribution = <1024>; - }; - - map1 { - trip = <&target>; - cooling-device = <&a53_0 0 2>; - contribution = <1024>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77950-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a77950-salvator-x.dts deleted file mode 100644 index 2438825c9..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77950-salvator-x.dts +++ /dev/null @@ -1,157 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X board with R-Car H3 ES1.x - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a77950.dtsi" -#include "salvator-x.dtsi" - -/ { - model = "Renesas Salvator-X board based on r8a77950"; - compatible = "renesas,salvator-x", "renesas,r8a7795"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - memory@500000000 { - device_type = "memory"; - reg = <0x5 0x00000000 0x0 0x40000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x40000000>; - }; - - memory@700000000 { - device_type = "memory"; - reg = <0x7 0x00000000 0x0 0x40000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&x21_clk>, - <&x22_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", "du.3", - "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; -}; - -&ehci2 { - status = "okay"; -}; - -&hdmi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi0_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint1>; - }; - }; - }; -}; - -&hdmi0_con { - remote-endpoint = <&rcar_dw_hdmi0_out>; -}; - -&hdmi1 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi1_out: endpoint { - remote-endpoint = <&hdmi1_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi1_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint2>; - }; - }; - }; -}; - -&hdmi1_con { - remote-endpoint = <&rcar_dw_hdmi1_out>; -}; - -&ohci2 { - status = "okay"; -}; - -&pfc { - usb2_pins: usb2 { - groups = "usb2"; - function = "usb2"; - }; -}; - -&rcar_sound { - ports { - /* rsnd_port0 is on salvator-common */ - rsnd_port1: port@1 { - reg = <1>; - rsnd_endpoint1: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint1>; - frame-master = <&rsnd_endpoint1>; - - playback = <&ssi2>; - }; - }; - rsnd_port2: port@2 { - reg = <2>; - rsnd_endpoint2: endpoint { - remote-endpoint = <&dw_hdmi1_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint2>; - frame-master = <&rsnd_endpoint2>; - - playback = <&ssi3>; - }; - }; - }; -}; - -&sata { - status = "okay"; -}; - -&sound_card { - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1 /* HDMI0 */ - &rsnd_port2>; /* HDMI1 */ -}; - -&usb2_phy2 { - pinctrl-0 = <&usb2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77950-ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a77950-ulcb-kf.dts deleted file mode 100644 index dcaaf12ce..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77950-ulcb-kf.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the H3ULCB Kingfisher board - * - * Copyright (C) 2017 Renesas Electronics Corp. - * Copyright (C) 2017 Cogent Embedded, Inc. - */ - -#include "r8a77950-ulcb.dts" -#include "ulcb-kf.dtsi" - -/ { - model = "Renesas H3ULCB Kingfisher board based on r8a77950"; - compatible = "shimafuji,kingfisher", "renesas,h3ulcb", - "renesas,r8a7795"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77950-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a77950-ulcb.dts deleted file mode 100644 index 38a6d6a10..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77950-ulcb.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board - * - * Copyright (C) 2016 Renesas Electronics Corp. - * Copyright (C) 2016 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77950.dtsi" -#include "ulcb.dtsi" - -/ { - model = "Renesas H3ULCB board based on r8a77950"; - compatible = "renesas,h3ulcb", "renesas,r8a7795"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - memory@500000000 { - device_type = "memory"; - reg = <0x5 0x00000000 0x0 0x40000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x40000000>; - }; - - memory@700000000 { - device_type = "memory"; - reg = <0x7 0x00000000 0x0 0x40000000>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77950.dtsi b/arch/arm64/boot/dts/renesas/r8a77950.dtsi deleted file mode 100644 index d716c4386..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77950.dtsi +++ /dev/null @@ -1,319 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car H3 (R8A77950) SoC - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -#include "r8a77951.dtsi" - -&audma0 { - iommus = <&ipmmu_mp1 0>, <&ipmmu_mp1 1>, - <&ipmmu_mp1 2>, <&ipmmu_mp1 3>, - <&ipmmu_mp1 4>, <&ipmmu_mp1 5>, - <&ipmmu_mp1 6>, <&ipmmu_mp1 7>, - <&ipmmu_mp1 8>, <&ipmmu_mp1 9>, - <&ipmmu_mp1 10>, <&ipmmu_mp1 11>, - <&ipmmu_mp1 12>, <&ipmmu_mp1 13>, - <&ipmmu_mp1 14>, <&ipmmu_mp1 15>; -}; - -&audma1 { - iommus = <&ipmmu_mp1 16>, <&ipmmu_mp1 17>, - <&ipmmu_mp1 18>, <&ipmmu_mp1 19>, - <&ipmmu_mp1 20>, <&ipmmu_mp1 21>, - <&ipmmu_mp1 22>, <&ipmmu_mp1 23>, - <&ipmmu_mp1 24>, <&ipmmu_mp1 25>, - <&ipmmu_mp1 26>, <&ipmmu_mp1 27>, - <&ipmmu_mp1 28>, <&ipmmu_mp1 29>, - <&ipmmu_mp1 30>, <&ipmmu_mp1 31>; -}; - -&du { - renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd3 0>; -}; - -&fcpvb1 { - iommus = <&ipmmu_vp0 7>; -}; - -&fcpf1 { - iommus = <&ipmmu_vp0 1>; -}; - -&fcpvi1 { - iommus = <&ipmmu_vp0 9>; -}; - -&fcpvd2 { - iommus = <&ipmmu_vi0 10>; -}; - -&gpio1 { - gpio-ranges = <&pfc 0 32 28>; -}; - -&ipmmu_vi0 { - renesas,ipmmu-main = <&ipmmu_mm 11>; -}; - -&ipmmu_vp0 { - renesas,ipmmu-main = <&ipmmu_mm 12>; -}; - -&ipmmu_vc0 { - renesas,ipmmu-main = <&ipmmu_mm 9>; -}; - -&ipmmu_vc1 { - renesas,ipmmu-main = <&ipmmu_mm 10>; -}; - -&ipmmu_rt { - renesas,ipmmu-main = <&ipmmu_mm 7>; -}; - -&soc { - /delete-node/ dma-controller@e6460000; - /delete-node/ dma-controller@e6470000; - - ipmmu_mp1: iommu@ec680000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xec680000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 5>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_sy: iommu@e7730000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe7730000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - /delete-node/ iommu@fd950000; - /delete-node/ iommu@fd960000; - /delete-node/ iommu@fd970000; - /delete-node/ iommu@febe0000; - /delete-node/ iommu@fe980000; - - xhci1: usb@ee040000 { - compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; - reg = <0 0xee040000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 327>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 327>; - status = "disabled"; - }; - - /delete-node/ usb@e659c000; - /delete-node/ usb@ee0e0000; - /delete-node/ usb@ee0e0100; - - /delete-node/ usb-phy@ee0e0200; - - fdp1@fe948000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe948000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 117>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 117>; - renesas,fcp = <&fcpf2>; - }; - - fcpf2: fcp@fe952000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe952000 0 0x200>; - clocks = <&cpg CPG_MOD 613>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 613>; - iommus = <&ipmmu_vp0 2>; - }; - - fcpvd3: fcp@fea3f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea3f000 0 0x200>; - clocks = <&cpg CPG_MOD 600>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 600>; - iommus = <&ipmmu_vi0 11>; - }; - - fcpvi2: fcp@fe9cf000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9cf000 0 0x200>; - clocks = <&cpg CPG_MOD 609>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 609>; - iommus = <&ipmmu_vp0 10>; - }; - - vspd3: vsp@fea38000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea38000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 620>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 620>; - - renesas,fcp = <&fcpvd3>; - }; - - vspi2: vsp@fe9c0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9c0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 629>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 629>; - - renesas,fcp = <&fcpvi2>; - }; - - csi21: csi2@fea90000 { - compatible = "renesas,r8a7795-csi2"; - reg = <0 0xfea90000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi21vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi21>; - }; - csi21vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi21>; - }; - csi21vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi21>; - }; - csi21vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi21>; - }; - csi21vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi21>; - }; - csi21vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi21>; - }; - csi21vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi21>; - }; - csi21vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi21>; - }; - }; - }; - }; -}; - -&vin0 { - ports { - port@1 { - vin0csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin0>; - }; - }; - }; -}; - -&vin1 { - ports { - port@1 { - vin1csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin1>; - }; - }; - }; -}; - -&vin2 { - ports { - port@1 { - vin2csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin2>; - }; - }; - }; -}; - -&vin3 { - ports { - port@1 { - vin3csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin3>; - }; - }; - }; -}; - -&vin4 { - ports { - port@1 { - vin4csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin4>; - }; - }; - }; -}; - -&vin5 { - ports { - port@1 { - vin5csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin5>; - }; - }; - }; -}; - -&vin6 { - ports { - port@1 { - vin6csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin6>; - }; - }; - }; -}; - -&vin7 { - ports { - port@1 { - vin7csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin7>; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77951-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a77951-salvator-x.dts deleted file mode 100644 index a402a2fb6..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77951-salvator-x.dts +++ /dev/null @@ -1,157 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X board with R-Car H3 ES2.0 - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a77951.dtsi" -#include "salvator-x.dtsi" - -/ { - model = "Renesas Salvator-X board based on r8a77951"; - compatible = "renesas,salvator-x", "renesas,r8a7795"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - memory@500000000 { - device_type = "memory"; - reg = <0x5 0x00000000 0x0 0x40000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x40000000>; - }; - - memory@700000000 { - device_type = "memory"; - reg = <0x7 0x00000000 0x0 0x40000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&x21_clk>, - <&x22_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", "du.3", - "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; -}; - -&ehci2 { - status = "okay"; -}; - -&hdmi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi0_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint1>; - }; - }; - }; -}; - -&hdmi0_con { - remote-endpoint = <&rcar_dw_hdmi0_out>; -}; - -&hdmi1 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi1_out: endpoint { - remote-endpoint = <&hdmi1_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi1_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint2>; - }; - }; - }; -}; - -&hdmi1_con { - remote-endpoint = <&rcar_dw_hdmi1_out>; -}; - -&ohci2 { - status = "okay"; -}; - -&pfc { - usb2_pins: usb2 { - groups = "usb2"; - function = "usb2"; - }; -}; - -&rcar_sound { - ports { - /* rsnd_port0 is on salvator-common */ - rsnd_port1: port@1 { - reg = <1>; - rsnd_endpoint1: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint1>; - frame-master = <&rsnd_endpoint1>; - - playback = <&ssi2>; - }; - }; - rsnd_port2: port@2 { - reg = <2>; - rsnd_endpoint2: endpoint { - remote-endpoint = <&dw_hdmi1_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint2>; - frame-master = <&rsnd_endpoint2>; - - playback = <&ssi3>; - }; - }; - }; -}; - -&sata { - status = "okay"; -}; - -&sound_card { - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1 /* HDMI0 */ - &rsnd_port2>; /* HDMI1 */ -}; - -&usb2_phy2 { - pinctrl-0 = <&usb2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dts deleted file mode 100644 index cef9da437..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dts +++ /dev/null @@ -1,206 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X 2nd version board with R-Car H3 ES2.0+ - * - * Copyright (C) 2015-2017 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a77951.dtsi" -#include "salvator-xs.dtsi" - -/ { - model = "Renesas Salvator-X 2nd version board based on r8a77951"; - compatible = "renesas,salvator-xs", "renesas,r8a7795"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - memory@500000000 { - device_type = "memory"; - reg = <0x5 0x00000000 0x0 0x40000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x40000000>; - }; - - memory@700000000 { - device_type = "memory"; - reg = <0x7 0x00000000 0x0 0x40000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 721>, - <&versaclock6 1>, - <&x21_clk>, - <&x22_clk>, - <&versaclock6 2>; - clock-names = "du.0", "du.1", "du.2", "du.3", - "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; -}; - -&ehci2 { - status = "okay"; -}; - -&ehci3 { - dr_mode = "otg"; - status = "okay"; -}; - -&hdmi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi0_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint1>; - }; - }; - }; -}; - -&hdmi0_con { - remote-endpoint = <&rcar_dw_hdmi0_out>; -}; - -&hdmi1 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi1_out: endpoint { - remote-endpoint = <&hdmi1_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi1_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint2>; - }; - }; - }; -}; - -&hdmi1_con { - remote-endpoint = <&rcar_dw_hdmi1_out>; -}; - -&hsusb3 { - dr_mode = "otg"; - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&ohci3 { - dr_mode = "otg"; - status = "okay"; -}; - -&pca9654 { - pcie_sata_switch { - gpio-hog; - gpios = <7 GPIO_ACTIVE_HIGH>; - output-low; /* enable SATA by default */ - line-name = "PCIE/SATA switch"; - }; -}; - -&pfc { - usb2_pins: usb2 { - groups = "usb2"; - function = "usb2"; - }; - - /* - * - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins - * (when SW31 is the default setting on Salvator-XS). - * - If SW31 is the default setting, you cannot use USB2.0 ch3 on - * r8a77951 with Salvator-XS. - * Hence the SW31 setting must be changed like 2) below. - * 1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF: - * - Connect GP6_3[01] to ADV7842. - * 2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON: - * - Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power). - * - Connect GP6_{04,21} to ADV7842. - */ - usb2_ch3_pins: usb2_ch3 { - groups = "usb2_ch3"; - function = "usb2_ch3"; - }; -}; - -&rcar_sound { - ports { - /* rsnd_port0 is on salvator-common */ - rsnd_port1: port@1 { - reg = <1>; - rsnd_endpoint1: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint1>; - frame-master = <&rsnd_endpoint1>; - - playback = <&ssi2>; - }; - }; - rsnd_port2: port@2 { - reg = <2>; - rsnd_endpoint2: endpoint { - remote-endpoint = <&dw_hdmi1_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint2>; - frame-master = <&rsnd_endpoint2>; - - playback = <&ssi3>; - }; - }; - }; -}; - -/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */ -&sata { - status = "okay"; -}; - -&sound_card { - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1 /* HDMI0 */ - &rsnd_port2>; /* HDMI1 */ -}; - -&usb2_phy2 { - pinctrl-0 = <&usb2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&usb2_phy3 { - pinctrl-0 = <&usb2_ch3_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77951-ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a77951-ulcb-kf.dts deleted file mode 100644 index 11f943a67..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77951-ulcb-kf.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the H3ULCB Kingfisher board - * - * Copyright (C) 2017 Renesas Electronics Corp. - * Copyright (C) 2017 Cogent Embedded, Inc. - */ - -#include "r8a77951-ulcb.dts" -#include "ulcb-kf.dtsi" - -/ { - model = "Renesas H3ULCB Kingfisher board based on r8a77951"; - compatible = "shimafuji,kingfisher", "renesas,h3ulcb", - "renesas,r8a7795"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77951-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a77951-ulcb.dts deleted file mode 100644 index 8ad8f2a53..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77951-ulcb.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board - * - * Copyright (C) 2016 Renesas Electronics Corp. - * Copyright (C) 2016 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77951.dtsi" -#include "ulcb.dtsi" - -/ { - model = "Renesas H3ULCB board based on r8a77951"; - compatible = "renesas,h3ulcb", "renesas,r8a7795"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - memory@500000000 { - device_type = "memory"; - reg = <0x5 0x00000000 0x0 0x40000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x40000000>; - }; - - memory@700000000 { - device_type = "memory"; - reg = <0x7 0x00000000 0x0 0x40000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&versaclock5 3>, - <&versaclock5 4>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", "du.3", - "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi deleted file mode 100644 index 18ce0face..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ /dev/null @@ -1,3340 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car H3 (R8A77951) SoC - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -#include -#include -#include - -#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 - -/ { - compatible = "renesas,r8a7795"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c_dvfs; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <960000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - }; - - cluster1_opp: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&a57_0>; - }; - core1 { - cpu = <&a57_1>; - }; - core2 { - cpu = <&a57_2>; - }; - core3 { - cpu = <&a57_3>; - }; - }; - - cluster1 { - core0 { - cpu = <&a53_0>; - }; - core1 { - cpu = <&a53_1>; - }; - core2 { - cpu = <&a53_2>; - }; - core3 { - cpu = <&a53_3>; - }; - }; - }; - - a57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA57_CPU0>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - dynamic-power-coefficient = <854>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x1>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA57_CPU1>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_2: cpu@2 { - compatible = "arm,cortex-a57"; - reg = <0x2>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA57_CPU2>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_3: cpu@3 { - compatible = "arm,cortex-a57"; - reg = <0x3>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA57_CPU3>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a53_0: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x100>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - #cooling-cells = <2>; - dynamic-power-coefficient = <277>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_1: cpu@101 { - compatible = "arm,cortex-a53"; - reg = <0x101>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_2: cpu@102 { - compatible = "arm,cortex-a53"; - reg = <0x102>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA53_CPU2>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_3: cpu@103 { - compatible = "arm,cortex-a53"; - reg = <0x103>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA53_CPU3>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - L2_CA57: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A7795_PD_CA57_SCU>; - cache-unified; - cache-level = <2>; - }; - - L2_CA53: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A7795_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <400>; - exit-latency-us = <500>; - min-residency-us = <4000>; - }; - - CPU_SLEEP_1: cpu-sleep-1 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <700>; - exit-latency-us = <700>; - min-residency-us = <5000>; - }; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, - <&a53_1>, - <&a53_2>, - <&a53_3>; - }; - - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, - <&a57_1>, - <&a57_2>, - <&a57_3>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc: soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7795", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 4>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a7795"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a7795-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7795-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a7795-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a7795-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7795-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7795-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7795-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a7795-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a7795", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7795", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7795", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - hsusb3: usb@e659c000 { - compatible = "renesas,usbhs-r8a7795", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe659c000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 705>, <&cpg CPG_MOD 700>; - dmas = <&usb_dmac2 0>, <&usb_dmac2 1>, - <&usb_dmac3 0>, <&usb_dmac3 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy3 3>; - phy-names = "usb"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 705>, <&cpg 700>; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac2: dma-controller@e6460000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe6460000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 326>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 326>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac3: dma-controller@e6470000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe6470000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 329>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 329>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a7795-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; - status = "disabled"; - }; - - arm_cc630p: crypto@e6601000 { - compatible = "arm,cryptocell-630p-ree"; - interrupts = ; - reg = <0x0 0xe6601000 0 0x1000>; - clocks = <&cpg CPG_MOD 229>; - resets = <&cpg 229>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7795", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a7795", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a7795", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: iommu@e6570000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ir: iommu@ff8b0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A7795_PD_A3IR>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp0: iommu@ec670000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: iommu@fd800000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv1: iommu@fd950000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd950000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 7>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv2: iommu@fd960000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd960000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv3: iommu@fd970000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd970000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt: iommu@ffc80000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: iommu@fe6b0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A7795_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vc1: iommu@fe6f0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe6f0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 13>; - power-domains = <&sysc R8A7795_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vi1: iommu@febe0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfebe0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 15>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vp0: iommu@fe990000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A7795_PD_A3VP>; - #iommu-cells = <1>; - }; - - ipmmu_vp1: iommu@fe980000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe980000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 17>; - power-domains = <&sysc R8A7795_PD_A3VP>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7795", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a7795", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7795_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a7795", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7795_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a7795-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A7795_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - tpu: pwm@e6e80000 { - compatible = "renesas,tpu-r8a7795", "renesas,tpu"; - reg = <0 0xe6e80000 0 0x148>; - interrupts = ; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a7795", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a7795", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a7795", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a7795", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin0>; - }; - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 810>; - renesas,id = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin1>; - }; - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin2>; - }; - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin3>; - }; - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin4>; - }; - vin4csi41: endpoint@3 { - reg = <3>; - remote-endpoint = <&csi41vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin5>; - }; - vin5csi41: endpoint@3 { - reg = <3>; - remote-endpoint = <&csi41vin5>; - }; - }; - }; - }; - - vin6: video@e6ef6000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 805>; - renesas,id = <6>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin6csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin6>; - }; - vin6csi41: endpoint@3 { - reg = <3>; - remote-endpoint = <&csi41vin6>; - }; - }; - }; - }; - - vin7: video@e6ef7000 { - compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 804>; - renesas,id = <7>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin7csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin7>; - }; - vin7csi41: endpoint@3 { - reg = <3>; - remote-endpoint = <&csi41vin7>; - }; - }; - }; - }; - - drif00: rif@e6f40000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f40000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 515>; - clock-names = "fck"; - dmas = <&dmac1 0x20>, <&dmac2 0x20>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 515>; - renesas,bonding = <&drif01>; - status = "disabled"; - }; - - drif01: rif@e6f50000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f50000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 514>; - clock-names = "fck"; - dmas = <&dmac1 0x22>, <&dmac2 0x22>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 514>; - renesas,bonding = <&drif00>; - status = "disabled"; - }; - - drif10: rif@e6f60000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f60000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 513>; - clock-names = "fck"; - dmas = <&dmac1 0x24>, <&dmac2 0x24>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 513>; - renesas,bonding = <&drif11>; - status = "disabled"; - }; - - drif11: rif@e6f70000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f70000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 512>; - clock-names = "fck"; - dmas = <&dmac1 0x26>, <&dmac2 0x26>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 512>; - renesas,bonding = <&drif10>; - status = "disabled"; - }; - - drif20: rif@e6f80000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f80000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 511>; - clock-names = "fck"; - dmas = <&dmac1 0x28>, <&dmac2 0x28>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 511>; - renesas,bonding = <&drif21>; - status = "disabled"; - }; - - drif21: rif@e6f90000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f90000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 510>; - clock-names = "fck"; - dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 510>; - renesas,bonding = <&drif20>; - status = "disabled"; - }; - - drif30: rif@e6fa0000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fa0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 509>; - clock-names = "fck"; - dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 509>; - renesas,bonding = <&drif31>; - status = "disabled"; - }; - - drif31: rif@e6fb0000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fb0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 508>; - clock-names = "fck"; - dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 508>; - renesas,bonding = <&drif30>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A7795_CLK_S0D4>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssiu { - ssiu00: ssiu-0 { - dmas = <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx"; - }; - ssiu01: ssiu-1 { - dmas = <&audma0 0x35>, <&audma1 0x36>; - dma-names = "rx", "tx"; - }; - ssiu02: ssiu-2 { - dmas = <&audma0 0x37>, <&audma1 0x38>; - dma-names = "rx", "tx"; - }; - ssiu03: ssiu-3 { - dmas = <&audma0 0x47>, <&audma1 0x48>; - dma-names = "rx", "tx"; - }; - ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; - dma-names = "rx", "tx"; - }; - ssiu05: ssiu-5 { - dmas = <&audma0 0x43>, <&audma1 0x44>; - dma-names = "rx", "tx"; - }; - ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; - dma-names = "rx", "tx"; - }; - ssiu07: ssiu-7 { - dmas = <&audma0 0x53>, <&audma1 0x54>; - dma-names = "rx", "tx"; - }; - ssiu10: ssiu-8 { - dmas = <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx"; - }; - ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; - dma-names = "rx", "tx"; - }; - ssiu12: ssiu-10 { - dmas = <&audma0 0x57>, <&audma1 0x58>; - dma-names = "rx", "tx"; - }; - ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; - dma-names = "rx", "tx"; - }; - ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; - dma-names = "rx", "tx"; - }; - ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; - dma-names = "rx", "tx"; - }; - ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; - dma-names = "rx", "tx"; - }; - ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; - dma-names = "rx", "tx"; - }; - ssiu20: ssiu-16 { - dmas = <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx"; - }; - ssiu21: ssiu-17 { - dmas = <&audma0 0x67>, <&audma1 0x68>; - dma-names = "rx", "tx"; - }; - ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; - dma-names = "rx", "tx"; - }; - ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; - dma-names = "rx", "tx"; - }; - ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; - dma-names = "rx", "tx"; - }; - ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; - dma-names = "rx", "tx"; - }; - ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; - dma-names = "rx", "tx"; - }; - ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; - dma-names = "rx", "tx"; - }; - ssiu30: ssiu-24 { - dmas = <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx"; - }; - ssiu31: ssiu-25 { - dmas = <&audma0 0x21>, <&audma1 0x22>; - dma-names = "rx", "tx"; - }; - ssiu32: ssiu-26 { - dmas = <&audma0 0x23>, <&audma1 0x24>; - dma-names = "rx", "tx"; - }; - ssiu33: ssiu-27 { - dmas = <&audma0 0x25>, <&audma1 0x26>; - dma-names = "rx", "tx"; - }; - ssiu34: ssiu-28 { - dmas = <&audma0 0x27>, <&audma1 0x28>; - dma-names = "rx", "tx"; - }; - ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; - dma-names = "rx", "tx"; - }; - ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; - dma-names = "rx", "tx"; - }; - ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; - dma-names = "rx", "tx"; - }; - ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx"; - }; - ssiu41: ssiu-33 { - dmas = <&audma0 0x17>, <&audma1 0x18>; - dma-names = "rx", "tx"; - }; - ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; - dma-names = "rx", "tx"; - }; - ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; - dma-names = "rx", "tx"; - }; - ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; - dma-names = "rx", "tx"; - }; - ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; - dma-names = "rx", "tx"; - }; - ssiu46: ssiu-38 { - dmas = <&audma0 0x31>, <&audma1 0x32>; - dma-names = "rx", "tx"; - }; - ssiu47: ssiu-39 { - dmas = <&audma0 0x33>, <&audma1 0x34>; - dma-names = "rx", "tx"; - }; - ssiu50: ssiu-40 { - dmas = <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx"; - }; - ssiu60: ssiu-41 { - dmas = <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx"; - }; - ssiu70: ssiu-42 { - dmas = <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx"; - }; - ssiu80: ssiu-43 { - dmas = <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx"; - }; - ssiu90: ssiu-44 { - dmas = <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx"; - }; - ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; - dma-names = "rx", "tx"; - }; - ssiu92: ssiu-46 { - dmas = <&audma0 0x81>, <&audma1 0x82>; - dma-names = "rx", "tx"; - }; - ssiu93: ssiu-47 { - dmas = <&audma0 0x83>, <&audma1 0x84>; - dma-names = "rx", "tx"; - }; - ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; - dma-names = "rx", "tx"; - }; - ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; - dma-names = "rx", "tx"; - }; - ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; - dma-names = "rx", "tx"; - }; - ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>; - dma-names = "rx", "tx"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>; - dma-names = "rx", "tx"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>; - dma-names = "rx", "tx"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>; - dma-names = "rx", "tx"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>; - dma-names = "rx", "tx"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>; - dma-names = "rx", "tx"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>; - dma-names = "rx", "tx"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>; - dma-names = "rx", "tx"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>; - dma-names = "rx", "tx"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>; - dma-names = "rx", "tx"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7795", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, - <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, - <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, - <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, - <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, - <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, - <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, - <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7795", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, - <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, - <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, - <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, - <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, - <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, - <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, - <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a7795-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 1>; - phy-names = "usb"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ohci2: usb@ee0c0000 { - compatible = "generic-ohci"; - reg = <0 0xee0c0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 701>; - phys = <&usb2_phy2 1>; - phy-names = "usb"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 701>; - status = "disabled"; - }; - - ohci3: usb@ee0e0000 { - compatible = "generic-ohci"; - reg = <0 0xee0e0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; - phys = <&usb2_phy3 1>; - phy-names = "usb"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 700>, <&cpg 705>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 2>; - phy-names = "usb"; - companion = <&ohci1>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ehci2: usb@ee0c0100 { - compatible = "generic-ehci"; - reg = <0 0xee0c0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 701>; - phys = <&usb2_phy2 2>; - phy-names = "usb"; - companion = <&ohci2>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 701>; - status = "disabled"; - }; - - ehci3: usb@ee0e0100 { - compatible = "generic-ehci"; - reg = <0 0xee0e0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; - phys = <&usb2_phy3 2>; - phy-names = "usb"; - companion = <&ohci3>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 700>, <&cpg 705>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 702>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy2: usb-phy@ee0c0200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0c0200 0 0x700>; - clocks = <&cpg CPG_MOD 701>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 701>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy3: usb-phy@ee0e0200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0e0200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 700>, <&cpg 705>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 314>; - iommus = <&ipmmu_ds1 32>; - status = "disabled"; - }; - - sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 313>; - iommus = <&ipmmu_ds1 33>; - status = "disabled"; - }; - - sdhi2: mmc@ee140000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 312>; - iommus = <&ipmmu_ds1 34>; - status = "disabled"; - }; - - sdhi3: mmc@ee160000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 311>; - iommus = <&ipmmu_ds1 35>; - status = "disabled"; - }; - - sata: sata@ee300000 { - compatible = "renesas,sata-r8a7795", - "renesas,rcar-gen3-sata"; - reg = <0 0xee300000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - iommus = <&ipmmu_hc 2>; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a7795", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - pciec1: pcie@ee800000 { - compatible = "renesas,pcie-r8a7795", - "renesas,pcie-rcar-gen3"; - reg = <0 0xee800000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, - <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, - <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, - <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - imr-lx4@fe860000 { - compatible = "renesas,r8a7795-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe860000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 823>; - power-domains = <&sysc R8A7795_PD_A3VC>; - resets = <&cpg 823>; - }; - - imr-lx4@fe870000 { - compatible = "renesas,r8a7795-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe870000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 822>; - power-domains = <&sysc R8A7795_PD_A3VC>; - resets = <&cpg 822>; - }; - - imr-lx4@fe880000 { - compatible = "renesas,r8a7795-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe880000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 821>; - power-domains = <&sysc R8A7795_PD_A3VC>; - resets = <&cpg 821>; - }; - - imr-lx4@fe890000 { - compatible = "renesas,r8a7795-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe890000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 820>; - power-domains = <&sysc R8A7795_PD_A3VC>; - resets = <&cpg 820>; - }; - - vspbc: vsp@fe920000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe920000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 624>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 624>; - - renesas,fcp = <&fcpvb1>; - }; - - vspbd: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 626>; - - renesas,fcp = <&fcpvb0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 623>; - - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 622>; - - renesas,fcp = <&fcpvd1>; - }; - - vspd2: vsp@fea30000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea30000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 621>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 621>; - - renesas,fcp = <&fcpvd2>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 631>; - - renesas,fcp = <&fcpvi0>; - }; - - vspi1: vsp@fe9b0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9b0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 630>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 630>; - - renesas,fcp = <&fcpvi1>; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 119>; - renesas,fcp = <&fcpf0>; - }; - - fdp1@fe944000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe944000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 118>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 118>; - renesas,fcp = <&fcpf1>; - }; - - fcpf0: fcp@fe950000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe950000 0 0x200>; - clocks = <&cpg CPG_MOD 615>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 615>; - iommus = <&ipmmu_vp0 0>; - }; - - fcpf1: fcp@fe951000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe951000 0 0x200>; - clocks = <&cpg CPG_MOD 614>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 614>; - iommus = <&ipmmu_vp1 1>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 607>; - iommus = <&ipmmu_vp0 5>; - }; - - fcpvb1: fcp@fe92f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe92f000 0 0x200>; - clocks = <&cpg CPG_MOD 606>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 606>; - iommus = <&ipmmu_vp1 7>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 611>; - iommus = <&ipmmu_vp0 8>; - }; - - fcpvi1: fcp@fe9bf000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9bf000 0 0x200>; - clocks = <&cpg CPG_MOD 610>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 610>; - iommus = <&ipmmu_vp1 9>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - - fcpvd2: fcp@fea37000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea37000 0 0x200>; - clocks = <&cpg CPG_MOD 601>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 601>; - iommus = <&ipmmu_vi1 10>; - }; - - cmm0: cmm@fea40000 { - compatible = "renesas,r8a7795-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea40000 0 0x1000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 711>; - resets = <&cpg 711>; - }; - - cmm1: cmm@fea50000 { - compatible = "renesas,r8a7795-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea50000 0 0x1000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 710>; - resets = <&cpg 710>; - }; - - cmm2: cmm@fea60000 { - compatible = "renesas,r8a7795-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea60000 0 0x1000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 709>; - resets = <&cpg 709>; - }; - - cmm3: cmm@fea70000 { - compatible = "renesas,r8a7795-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea70000 0 0x1000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 708>; - resets = <&cpg 708>; - }; - - csi20: csi2@fea80000 { - compatible = "renesas,r8a7795-csi2"; - reg = <0 0xfea80000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi20vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi20>; - }; - csi20vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi20>; - }; - csi20vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi20>; - }; - csi20vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi20>; - }; - csi20vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi20>; - }; - csi20vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi20>; - }; - csi20vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi20>; - }; - csi20vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi20>; - }; - }; - }; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a7795-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - }; - }; - }; - - csi41: csi2@feab0000 { - compatible = "renesas,r8a7795-csi2"; - reg = <0 0xfeab0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi41vin4: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin4csi41>; - }; - csi41vin5: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin5csi41>; - }; - csi41vin6: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin6csi41>; - }; - csi41vin7: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin7csi41>; - }; - }; - }; - }; - - hdmi0: hdmi@fead0000 { - compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; - reg = <0 0xfead0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7795_CLK_HDMI>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 729>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dw_hdmi0_in: endpoint { - remote-endpoint = <&du_out_hdmi0>; - }; - }; - port@1 { - reg = <1>; - }; - port@2 { - /* HDMI sound */ - reg = <2>; - }; - }; - }; - - hdmi1: hdmi@feae0000 { - compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; - reg = <0 0xfeae0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 728>, <&cpg CPG_CORE R8A7795_CLK_HDMI>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 728>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dw_hdmi1_in: endpoint { - remote-endpoint = <&du_out_hdmi1>; - }; - }; - port@1 { - reg = <1>; - }; - port@2 { - /* HDMI sound */ - reg = <2>; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7795"; - reg = <0 0xfeb00000 0 0x80000>; - interrupts = , - , - , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>; - clock-names = "du.0", "du.1", "du.2", "du.3"; - resets = <&cpg 724>, <&cpg 722>; - reset-names = "du.0", "du.2"; - - renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>; - renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, - <&vspd0 1>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_hdmi0: endpoint { - remote-endpoint = <&dw_hdmi0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_hdmi1: endpoint { - remote-endpoint = <&dw_hdmi1_in>; - }; - }; - port@3 { - reg = <3>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a7795-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - sensor_thermal1: sensor-thermal1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - sustainable-power = <6313>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal2: sensor-thermal2 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - sustainable-power = <6313>; - - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal3: sensor-thermal3 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; - - trips { - target: trip-point1 { - temperature = <100000>; - hysteresis = <1000>; - type = "passive"; - }; - - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a57_0 2 4>; - contribution = <1024>; - }; - - map1 { - trip = <&target>; - cooling-device = <&a53_0 0 2>; - contribution = <1024>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dts deleted file mode 100644 index ecfbeafea..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77960-salvator-x.dts +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X board with R-Car M3-W - * - * Copyright (C) 2016 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a77960.dtsi" -#include "salvator-x.dtsi" - -/ { - model = "Renesas Salvator-X board based on r8a77960"; - compatible = "renesas,salvator-x", "renesas,r8a7796"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x80000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&versaclock5 1>, - <&x21_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", - "dclkin.0", "dclkin.1", "dclkin.2"; -}; - -&hdmi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi0_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint1>; - }; - }; - }; -}; - -&hdmi0_con { - remote-endpoint = <&rcar_dw_hdmi0_out>; -}; - -&rcar_sound { - ports { - /* rsnd_port0 is on salvator-common */ - rsnd_port1: port@1 { - reg = <1>; - rsnd_endpoint1: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint1>; - frame-master = <&rsnd_endpoint1>; - - playback = <&ssi2>; - }; - }; - }; -}; - -&sound_card { - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1>; /* HDMI0 */ -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dts deleted file mode 100644 index 249896a38..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77960-salvator-xs.dts +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X 2nd version board with R-Car M3-W - * - * Copyright (C) 2015-2017 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a77960.dtsi" -#include "salvator-xs.dtsi" - -/ { - model = "Renesas Salvator-X 2nd version board based on r8a77960"; - compatible = "renesas,salvator-xs", "renesas,r8a7796"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x80000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&versaclock6 1>, - <&x21_clk>, - <&versaclock6 2>; - clock-names = "du.0", "du.1", "du.2", - "dclkin.0", "dclkin.1", "dclkin.2"; -}; - -&hdmi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi0_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint1>; - }; - }; - }; -}; - -&hdmi0_con { - remote-endpoint = <&rcar_dw_hdmi0_out>; -}; - -&rcar_sound { - ports { - /* rsnd_port0 is on salvator-common */ - rsnd_port1: port@1 { - reg = <1>; - rsnd_endpoint1: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint1>; - frame-master = <&rsnd_endpoint1>; - - playback = <&ssi2>; - }; - }; - }; -}; - -&sound_card { - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1>; /* HDMI0 */ -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77960-ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a77960-ulcb-kf.dts deleted file mode 100644 index 2151c37d7..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77960-ulcb-kf.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the M3ULCB Kingfisher board - * - * Copyright (C) 2017 Renesas Electronics Corp. - * Copyright (C) 2017 Cogent Embedded, Inc. - */ - -#include "r8a77960-ulcb.dts" -#include "ulcb-kf.dtsi" - -/ { - model = "Renesas M3ULCB Kingfisher board based on r8a77960"; - compatible = "shimafuji,kingfisher", "renesas,m3ulcb", - "renesas,r8a7796"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77960-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a77960-ulcb.dts deleted file mode 100644 index d041042a5..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77960-ulcb.dts +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board - * - * Copyright (C) 2016 Renesas Electronics Corp. - * Copyright (C) 2016 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77960.dtsi" -#include "ulcb.dtsi" - -/ { - model = "Renesas M3ULCB board based on r8a77960"; - compatible = "renesas,m3ulcb", "renesas,r8a7796"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x40000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&versaclock5 1>, - <&versaclock5 3>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", - "dclkin.0", "dclkin.1", "dclkin.2"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi deleted file mode 100644 index fa9567ed5..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ /dev/null @@ -1,2983 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car M3-W (R8A77960) SoC - * - * Copyright (C) 2016-2017 Renesas Electronics Corp. - */ - -#include -#include -#include - -#define CPG_AUDIO_CLK_I R8A7796_CLK_S0D4 - -/ { - compatible = "renesas,r8a7796"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c_dvfs; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <960000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - }; - - cluster1_opp: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&a57_0>; - }; - core1 { - cpu = <&a57_1>; - }; - }; - - cluster1 { - core0 { - cpu = <&a53_0>; - }; - core1 { - cpu = <&a53_1>; - }; - core2 { - cpu = <&a53_2>; - }; - core3 { - cpu = <&a53_3>; - }; - }; - }; - - a57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA57_CPU0>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - dynamic-power-coefficient = <854>; - clocks = <&cpg CPG_CORE R8A7796_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x1>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA57_CPU1>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A7796_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a53_0: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x100>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - #cooling-cells = <2>; - dynamic-power-coefficient = <277>; - clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_1: cpu@101 { - compatible = "arm,cortex-a53"; - reg = <0x101>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_2: cpu@102 { - compatible = "arm,cortex-a53"; - reg = <0x102>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA53_CPU2>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_3: cpu@103 { - compatible = "arm,cortex-a53"; - reg = <0x103>; - device_type = "cpu"; - power-domains = <&sysc R8A7796_PD_CA53_CPU3>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - L2_CA57: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A7796_PD_CA57_SCU>; - cache-unified; - cache-level = <2>; - }; - - L2_CA53: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A7796_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <400>; - exit-latency-us = <500>; - min-residency-us = <4000>; - }; - - CPU_SLEEP_1: cpu-sleep-1 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <700>; - exit-latency-us = <700>; - min-residency-us = <5000>; - }; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; - }; - - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, <&a57_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7796-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a7796", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 4>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a7796"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a7796-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7796-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a7796-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a7796-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7796-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7796-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7796-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a7796-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a7796", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7796", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7796", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7796", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7796", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7796", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7796", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7796", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7796", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a7796", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a7796", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a7796", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a7796", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a7796", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7796", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7796-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7796-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a7796-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; - status = "disabled"; - }; - - arm_cc630p: crypto@e6601000 { - compatible = "arm,cryptocell-630p-ree"; - interrupts = ; - reg = <0x0 0xe6601000 0 0x1000>; - clocks = <&cpg CPG_MOD 229>; - resets = <&cpg 229>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: iommu@e6570000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ir: iommu@ff8b0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A7796_PD_A3IR>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp: iommu@ec670000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: iommu@fd800000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 5>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv1: iommu@fd950000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfd950000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt: iommu@ffc80000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 7>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: iommu@fe6b0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; - power-domains = <&sysc R8A7796_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7796", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a7796", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7796_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a7796", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7796_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a7796-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A7796_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - tpu: pwm@e6e80000 { - compatible = "renesas,tpu-r8a7796", "renesas,tpu"; - reg = <0 0xe6e80000 0 0x148>; - interrupts = ; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a7796", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a7796", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a7796", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a7796", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin0>; - }; - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 810>; - renesas,id = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin1>; - }; - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin2>; - }; - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin3>; - }; - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin4>; - }; - vin4csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin5>; - }; - vin5csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin5>; - }; - }; - }; - }; - - vin6: video@e6ef6000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 805>; - renesas,id = <6>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin6csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin6>; - }; - vin6csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin6>; - }; - }; - }; - }; - - vin7: video@e6ef7000 { - compatible = "renesas,vin-r8a7796"; - reg = <0 0xe6ef7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 804>; - renesas,id = <7>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin7csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin7>; - }; - vin7csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin7>; - }; - }; - }; - }; - - drif00: rif@e6f40000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f40000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 515>; - clock-names = "fck"; - dmas = <&dmac1 0x20>, <&dmac2 0x20>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 515>; - renesas,bonding = <&drif01>; - status = "disabled"; - }; - - drif01: rif@e6f50000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f50000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 514>; - clock-names = "fck"; - dmas = <&dmac1 0x22>, <&dmac2 0x22>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 514>; - renesas,bonding = <&drif00>; - status = "disabled"; - }; - - drif10: rif@e6f60000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f60000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 513>; - clock-names = "fck"; - dmas = <&dmac1 0x24>, <&dmac2 0x24>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 513>; - renesas,bonding = <&drif11>; - status = "disabled"; - }; - - drif11: rif@e6f70000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f70000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 512>; - clock-names = "fck"; - dmas = <&dmac1 0x26>, <&dmac2 0x26>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 512>; - renesas,bonding = <&drif10>; - status = "disabled"; - }; - - drif20: rif@e6f80000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f80000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 511>; - clock-names = "fck"; - dmas = <&dmac1 0x28>, <&dmac2 0x28>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 511>; - renesas,bonding = <&drif21>; - status = "disabled"; - }; - - drif21: rif@e6f90000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f90000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 510>; - clock-names = "fck"; - dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 510>; - renesas,bonding = <&drif20>; - status = "disabled"; - }; - - drif30: rif@e6fa0000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fa0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 509>; - clock-names = "fck"; - dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 509>; - renesas,bonding = <&drif31>; - status = "disabled"; - }; - - drif31: rif@e6fb0000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fb0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 508>; - clock-names = "fck"; - dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 508>; - renesas,bonding = <&drif30>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A7796_CLK_S0D4>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>; - dma-names = "rx", "tx"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>; - dma-names = "rx", "tx"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>; - dma-names = "rx", "tx"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>; - dma-names = "rx", "tx"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>; - dma-names = "rx", "tx"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>; - dma-names = "rx", "tx"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>; - dma-names = "rx", "tx"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>; - dma-names = "rx", "tx"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>; - dma-names = "rx", "tx"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssiu { - ssiu00: ssiu-0 { - dmas = <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx"; - }; - ssiu01: ssiu-1 { - dmas = <&audma0 0x35>, <&audma1 0x36>; - dma-names = "rx", "tx"; - }; - ssiu02: ssiu-2 { - dmas = <&audma0 0x37>, <&audma1 0x38>; - dma-names = "rx", "tx"; - }; - ssiu03: ssiu-3 { - dmas = <&audma0 0x47>, <&audma1 0x48>; - dma-names = "rx", "tx"; - }; - ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; - dma-names = "rx", "tx"; - }; - ssiu05: ssiu-5 { - dmas = <&audma0 0x43>, <&audma1 0x44>; - dma-names = "rx", "tx"; - }; - ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; - dma-names = "rx", "tx"; - }; - ssiu07: ssiu-7 { - dmas = <&audma0 0x53>, <&audma1 0x54>; - dma-names = "rx", "tx"; - }; - ssiu10: ssiu-8 { - dmas = <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx"; - }; - ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; - dma-names = "rx", "tx"; - }; - ssiu12: ssiu-10 { - dmas = <&audma0 0x57>, <&audma1 0x58>; - dma-names = "rx", "tx"; - }; - ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; - dma-names = "rx", "tx"; - }; - ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; - dma-names = "rx", "tx"; - }; - ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; - dma-names = "rx", "tx"; - }; - ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; - dma-names = "rx", "tx"; - }; - ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; - dma-names = "rx", "tx"; - }; - ssiu20: ssiu-16 { - dmas = <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx"; - }; - ssiu21: ssiu-17 { - dmas = <&audma0 0x67>, <&audma1 0x68>; - dma-names = "rx", "tx"; - }; - ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; - dma-names = "rx", "tx"; - }; - ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; - dma-names = "rx", "tx"; - }; - ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; - dma-names = "rx", "tx"; - }; - ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; - dma-names = "rx", "tx"; - }; - ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; - dma-names = "rx", "tx"; - }; - ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; - dma-names = "rx", "tx"; - }; - ssiu30: ssiu-24 { - dmas = <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx"; - }; - ssiu31: ssiu-25 { - dmas = <&audma0 0x21>, <&audma1 0x22>; - dma-names = "rx", "tx"; - }; - ssiu32: ssiu-26 { - dmas = <&audma0 0x23>, <&audma1 0x24>; - dma-names = "rx", "tx"; - }; - ssiu33: ssiu-27 { - dmas = <&audma0 0x25>, <&audma1 0x26>; - dma-names = "rx", "tx"; - }; - ssiu34: ssiu-28 { - dmas = <&audma0 0x27>, <&audma1 0x28>; - dma-names = "rx", "tx"; - }; - ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; - dma-names = "rx", "tx"; - }; - ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; - dma-names = "rx", "tx"; - }; - ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; - dma-names = "rx", "tx"; - }; - ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx"; - }; - ssiu41: ssiu-33 { - dmas = <&audma0 0x17>, <&audma1 0x18>; - dma-names = "rx", "tx"; - }; - ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; - dma-names = "rx", "tx"; - }; - ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; - dma-names = "rx", "tx"; - }; - ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; - dma-names = "rx", "tx"; - }; - ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; - dma-names = "rx", "tx"; - }; - ssiu46: ssiu-38 { - dmas = <&audma0 0x31>, <&audma1 0x32>; - dma-names = "rx", "tx"; - }; - ssiu47: ssiu-39 { - dmas = <&audma0 0x33>, <&audma1 0x34>; - dma-names = "rx", "tx"; - }; - ssiu50: ssiu-40 { - dmas = <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx"; - }; - ssiu60: ssiu-41 { - dmas = <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx"; - }; - ssiu70: ssiu-42 { - dmas = <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx"; - }; - ssiu80: ssiu-43 { - dmas = <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx"; - }; - ssiu90: ssiu-44 { - dmas = <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx"; - }; - ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; - dma-names = "rx", "tx"; - }; - ssiu92: ssiu-46 { - dmas = <&audma0 0x81>, <&audma1 0x82>; - dma-names = "rx", "tx"; - }; - ssiu93: ssiu-47 { - dmas = <&audma0 0x83>, <&audma1 0x84>; - dma-names = "rx", "tx"; - }; - ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; - dma-names = "rx", "tx"; - }; - ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; - dma-names = "rx", "tx"; - }; - ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; - dma-names = "rx", "tx"; - }; - ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; - dma-names = "rx", "tx"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, - <&ipmmu_mp 2>, <&ipmmu_mp 3>, - <&ipmmu_mp 4>, <&ipmmu_mp 5>, - <&ipmmu_mp 6>, <&ipmmu_mp 7>, - <&ipmmu_mp 8>, <&ipmmu_mp 9>, - <&ipmmu_mp 10>, <&ipmmu_mp 11>, - <&ipmmu_mp 12>, <&ipmmu_mp 13>, - <&ipmmu_mp 14>, <&ipmmu_mp 15>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, - <&ipmmu_mp 18>, <&ipmmu_mp 19>, - <&ipmmu_mp 20>, <&ipmmu_mp 21>, - <&ipmmu_mp 22>, <&ipmmu_mp 23>, - <&ipmmu_mp 24>, <&ipmmu_mp 25>, - <&ipmmu_mp 26>, <&ipmmu_mp 27>, - <&ipmmu_mp 28>, <&ipmmu_mp 29>, - <&ipmmu_mp 30>, <&ipmmu_mp 31>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a7796", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a7796-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 1>; - phy-names = "usb"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 2>; - phy-names = "usb"; - companion = <&ohci1>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a7796", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a7796", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 702>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 314>; - iommus = <&ipmmu_ds1 32>; - status = "disabled"; - }; - - sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 313>; - iommus = <&ipmmu_ds1 33>; - status = "disabled"; - }; - - sdhi2: mmc@ee140000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 312>; - iommus = <&ipmmu_ds1 34>; - status = "disabled"; - }; - - sdhi3: mmc@ee160000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 311>; - iommus = <&ipmmu_ds1 35>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a7796", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - pciec1: pcie@ee800000 { - compatible = "renesas,pcie-r8a7796", - "renesas,pcie-rcar-gen3"; - reg = <0 0xee800000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, - <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, - <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, - <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - imr-lx4@fe860000 { - compatible = "renesas,r8a7796-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe860000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 823>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 823>; - }; - - imr-lx4@fe870000 { - compatible = "renesas,r8a7796-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe870000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 822>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 822>; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 119>; - renesas,fcp = <&fcpf0>; - }; - - fcpf0: fcp@fe950000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe950000 0 0x200>; - clocks = <&cpg CPG_MOD 615>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 615>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 607>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 611>; - iommus = <&ipmmu_vc0 19>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - - fcpvd2: fcp@fea37000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea37000 0 0x200>; - clocks = <&cpg CPG_MOD 601>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 601>; - iommus = <&ipmmu_vi0 10>; - }; - - vspb: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 626>; - - renesas,fcp = <&fcpvb0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 623>; - - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 622>; - - renesas,fcp = <&fcpvd1>; - }; - - vspd2: vsp@fea30000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea30000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 621>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 621>; - - renesas,fcp = <&fcpvd2>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 631>; - - renesas,fcp = <&fcpvi0>; - }; - - cmm0: cmm@fea40000 { - compatible = "renesas,r8a7796-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea40000 0 0x1000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 711>; - resets = <&cpg 711>; - }; - - cmm1: cmm@fea50000 { - compatible = "renesas,r8a7796-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea50000 0 0x1000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 710>; - resets = <&cpg 710>; - }; - - cmm2: cmm@fea60000 { - compatible = "renesas,r8a7796-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea60000 0 0x1000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 709>; - resets = <&cpg 709>; - }; - - csi20: csi2@fea80000 { - compatible = "renesas,r8a7796-csi2"; - reg = <0 0xfea80000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi20vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi20>; - }; - csi20vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi20>; - }; - csi20vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi20>; - }; - csi20vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi20>; - }; - csi20vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi20>; - }; - csi20vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi20>; - }; - csi20vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi20>; - }; - csi20vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi20>; - }; - }; - }; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a7796-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - csi40vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi40>; - }; - csi40vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi40>; - }; - csi40vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi40>; - }; - csi40vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi40>; - }; - }; - - }; - }; - - hdmi0: hdmi@fead0000 { - compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi"; - reg = <0 0xfead0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 729>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dw_hdmi0_in: endpoint { - remote-endpoint = <&du_out_hdmi0>; - }; - }; - port@1 { - reg = <1>; - }; - port@2 { - /* HDMI sound */ - reg = <2>; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a7796"; - reg = <0 0xfeb00000 0 0x70000>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>; - clock-names = "du.0", "du.1", "du.2"; - resets = <&cpg 724>, <&cpg 722>; - reset-names = "du.0", "du.2"; - - renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>; - renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_hdmi0: endpoint { - remote-endpoint = <&dw_hdmi0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a7796-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - sensor_thermal1: sensor-thermal1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - sustainable-power = <3874>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal2: sensor-thermal2 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - sustainable-power = <3874>; - - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal3: sensor-thermal3 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; - sustainable-power = <3874>; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a57_0 2 4>; - contribution = <1024>; - }; - map1 { - trip = <&target>; - cooling-device = <&a53_0 0 2>; - contribution = <1024>; - }; - }; - trips { - target: trip-point1 { - temperature = <100000>; - hysteresis = <1000>; - type = "passive"; - }; - - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts deleted file mode 100644 index 1e7603365..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77961-salvator-xs.dts +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X 2nd version board with R-Car M3-W+ - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a77961.dtsi" -#include "salvator-xs.dtsi" - -/ { - model = "Renesas Salvator-X 2nd version board based on r8a77961"; - compatible = "renesas,salvator-xs", "renesas,r8a77961"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@480000000 { - device_type = "memory"; - reg = <0x4 0x80000000 0x0 0x80000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x1 0x00000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&versaclock6 1>, - <&x21_clk>, - <&versaclock6 2>; - clock-names = "du.0", "du.1", "du.2", - "dclkin.0", "dclkin.1", "dclkin.2"; -}; - -&hdmi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi0_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint1>; - }; - }; - }; -}; - -&hdmi0_con { - remote-endpoint = <&rcar_dw_hdmi0_out>; -}; - -&rcar_sound { - ports { - /* rsnd_port0 is on salvator-common */ - rsnd_port1: port@1 { - reg = <1>; - rsnd_endpoint1: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint1>; - frame-master = <&rsnd_endpoint1>; - - playback = <&ssi2>; - }; - }; - }; -}; - -&sound_card { - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1>; /* HDMI0 */ -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts deleted file mode 100644 index 7c6e60f6f..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77961-ulcb.dts +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board with R-Car - * M3-W+ - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a77961.dtsi" -#include "ulcb.dtsi" - -/ { - model = "Renesas M3ULCB board based on r8a77961"; - compatible = "renesas,m3ulcb", "renesas,r8a77961"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@480000000 { - device_type = "memory"; - reg = <0x4 0x80000000 0x0 0x80000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x1 0x00000000>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi deleted file mode 100644 index b23f49b89..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ /dev/null @@ -1,2234 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC - * - * Copyright (C) 2016-2017 Renesas Electronics Corp. - */ - -#include -#include -#include - -#define CPG_AUDIO_CLK_I R8A77961_CLK_S0D4 - -/ { - compatible = "renesas,r8a77961"; - #address-cells = <2>; - #size-cells = <2>; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <960000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - }; - - cluster1_opp: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&a57_0>; - }; - core1 { - cpu = <&a57_1>; - }; - }; - - cluster1 { - core0 { - cpu = <&a53_0>; - }; - core1 { - cpu = <&a53_1>; - }; - core2 { - cpu = <&a53_2>; - }; - core3 { - cpu = <&a53_3>; - }; - }; - }; - - a57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A77961_PD_CA57_CPU0>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - dynamic-power-coefficient = <854>; - clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x1>; - device_type = "cpu"; - power-domains = <&sysc R8A77961_PD_CA57_CPU1>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - capacity-dmips-mhz = <1024>; - #cooling-cells = <2>; - }; - - a53_0: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x100>; - device_type = "cpu"; - power-domains = <&sysc R8A77961_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - #cooling-cells = <2>; - dynamic-power-coefficient = <277>; - clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_1: cpu@101 { - compatible = "arm,cortex-a53"; - reg = <0x101>; - device_type = "cpu"; - power-domains = <&sysc R8A77961_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_2: cpu@102 { - compatible = "arm,cortex-a53"; - reg = <0x102>; - device_type = "cpu"; - power-domains = <&sysc R8A77961_PD_CA53_CPU2>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - a53_3: cpu@103 { - compatible = "arm,cortex-a53"; - reg = <0x103>; - device_type = "cpu"; - power-domains = <&sysc R8A77961_PD_CA53_CPU3>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_1>; - clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - capacity-dmips-mhz = <535>; - }; - - L2_CA57: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A77961_PD_CA57_SCU>; - cache-unified; - cache-level = <2>; - }; - - L2_CA53: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A77961_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <400>; - exit-latency-us = <500>; - min-residency-us = <4000>; - }; - - CPU_SLEEP_1: cpu-sleep-1 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <700>; - exit-latency-us = <700>; - min-residency-us = <5000>; - }; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; - }; - - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, <&a57_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a77961-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77961", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a77961", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a77961", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77961", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a77961", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a77961", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a77961", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a77961", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 4>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a77961"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77961-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77961-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77961-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a77961-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - /* placeholder */ - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77961", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77961", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77961", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77961", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77961", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77961", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77961", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a77961", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a77961", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A77961_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a77961", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A77961_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a77961", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A77961_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a77961", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A77961_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a77961", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A77961_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a77961", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a77961-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a77961-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a77961-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; - status = "disabled"; - }; - - arm_cc630p: crypto@e6601000 { - compatible = "arm,cryptocell-630p-ree"; - interrupts = ; - reg = <0x0 0xe6601000 0 0x1000>; - clocks = <&cpg CPG_MOD 229>; - resets = <&cpg 229>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a77961", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a77961", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a77961", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - }; - - ipmmu_ds0: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a77961"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a77961"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: iommu@e6570000 { - compatible = "renesas,ipmmu-r8a77961"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ir: iommu@ff8b0000 { - compatible = "renesas,ipmmu-r8a77961"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A77961_PD_A3IR>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a77961"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp: iommu@ec670000 { - compatible = "renesas,ipmmu-r8a77961"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: iommu@fd800000 { - compatible = "renesas,ipmmu-r8a77961"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 5>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv1: iommu@fd950000 { - compatible = "renesas,ipmmu-r8a77961"; - reg = <0 0xfd950000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt: iommu@ffc80000 { - compatible = "renesas,ipmmu-r8a77961"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 7>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: iommu@fe6b0000 { - compatible = "renesas,ipmmu-r8a77961"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; - power-domains = <&sysc R8A77961_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a77961"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77961", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a77961", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A77961_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a77961", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A77961_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a77961", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A77961_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a77961", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A77961_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a77961", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A77961_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a77961", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A77961_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - reg = <0 0xe6ef0000 0 0x1000>; - /* placeholder */ - }; - - vin1: video@e6ef1000 { - reg = <0 0xe6ef1000 0 0x1000>; - /* placeholder */ - }; - - vin2: video@e6ef2000 { - reg = <0 0xe6ef2000 0 0x1000>; - /* placeholder */ - }; - - vin3: video@e6ef3000 { - reg = <0 0xe6ef3000 0 0x1000>; - /* placeholder */ - }; - - vin4: video@e6ef4000 { - reg = <0 0xe6ef4000 0 0x1000>; - /* placeholder */ - }; - - vin5: video@e6ef5000 { - reg = <0 0xe6ef5000 0 0x1000>; - /* placeholder */ - }; - - vin6: video@e6ef6000 { - reg = <0 0xe6ef6000 0 0x1000>; - /* placeholder */ - }; - - vin7: video@e6ef7000 { - reg = <0 0xe6ef7000 0 0x1000>; - /* placeholder */ - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a77961", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A77961_CLK_S0D4>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>; - dma-names = "rx", "tx"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>; - dma-names = "rx", "tx"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>; - dma-names = "rx", "tx"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>; - dma-names = "rx", "tx"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>; - dma-names = "rx", "tx"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>; - dma-names = "rx", "tx"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>; - dma-names = "rx", "tx"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>; - dma-names = "rx", "tx"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>; - dma-names = "rx", "tx"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssiu { - ssiu00: ssiu-0 { - dmas = <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx"; - }; - ssiu01: ssiu-1 { - dmas = <&audma0 0x35>, <&audma1 0x36>; - dma-names = "rx", "tx"; - }; - ssiu02: ssiu-2 { - dmas = <&audma0 0x37>, <&audma1 0x38>; - dma-names = "rx", "tx"; - }; - ssiu03: ssiu-3 { - dmas = <&audma0 0x47>, <&audma1 0x48>; - dma-names = "rx", "tx"; - }; - ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; - dma-names = "rx", "tx"; - }; - ssiu05: ssiu-5 { - dmas = <&audma0 0x43>, <&audma1 0x44>; - dma-names = "rx", "tx"; - }; - ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; - dma-names = "rx", "tx"; - }; - ssiu07: ssiu-7 { - dmas = <&audma0 0x53>, <&audma1 0x54>; - dma-names = "rx", "tx"; - }; - ssiu10: ssiu-8 { - dmas = <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx"; - }; - ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; - dma-names = "rx", "tx"; - }; - ssiu12: ssiu-10 { - dmas = <&audma0 0x57>, <&audma1 0x58>; - dma-names = "rx", "tx"; - }; - ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; - dma-names = "rx", "tx"; - }; - ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; - dma-names = "rx", "tx"; - }; - ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; - dma-names = "rx", "tx"; - }; - ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; - dma-names = "rx", "tx"; - }; - ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; - dma-names = "rx", "tx"; - }; - ssiu20: ssiu-16 { - dmas = <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx"; - }; - ssiu21: ssiu-17 { - dmas = <&audma0 0x67>, <&audma1 0x68>; - dma-names = "rx", "tx"; - }; - ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; - dma-names = "rx", "tx"; - }; - ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; - dma-names = "rx", "tx"; - }; - ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; - dma-names = "rx", "tx"; - }; - ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; - dma-names = "rx", "tx"; - }; - ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; - dma-names = "rx", "tx"; - }; - ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; - dma-names = "rx", "tx"; - }; - ssiu30: ssiu-24 { - dmas = <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx"; - }; - ssiu31: ssiu-25 { - dmas = <&audma0 0x21>, <&audma1 0x22>; - dma-names = "rx", "tx"; - }; - ssiu32: ssiu-26 { - dmas = <&audma0 0x23>, <&audma1 0x24>; - dma-names = "rx", "tx"; - }; - ssiu33: ssiu-27 { - dmas = <&audma0 0x25>, <&audma1 0x26>; - dma-names = "rx", "tx"; - }; - ssiu34: ssiu-28 { - dmas = <&audma0 0x27>, <&audma1 0x28>; - dma-names = "rx", "tx"; - }; - ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; - dma-names = "rx", "tx"; - }; - ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; - dma-names = "rx", "tx"; - }; - ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; - dma-names = "rx", "tx"; - }; - ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx"; - }; - ssiu41: ssiu-33 { - dmas = <&audma0 0x17>, <&audma1 0x18>; - dma-names = "rx", "tx"; - }; - ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; - dma-names = "rx", "tx"; - }; - ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; - dma-names = "rx", "tx"; - }; - ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; - dma-names = "rx", "tx"; - }; - ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; - dma-names = "rx", "tx"; - }; - ssiu46: ssiu-38 { - dmas = <&audma0 0x31>, <&audma1 0x32>; - dma-names = "rx", "tx"; - }; - ssiu47: ssiu-39 { - dmas = <&audma0 0x33>, <&audma1 0x34>; - dma-names = "rx", "tx"; - }; - ssiu50: ssiu-40 { - dmas = <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx"; - }; - ssiu60: ssiu-41 { - dmas = <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx"; - }; - ssiu70: ssiu-42 { - dmas = <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx"; - }; - ssiu80: ssiu-43 { - dmas = <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx"; - }; - ssiu90: ssiu-44 { - dmas = <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx"; - }; - ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; - dma-names = "rx", "tx"; - }; - ssiu92: ssiu-46 { - dmas = <&audma0 0x81>, <&audma1 0x82>; - dma-names = "rx", "tx"; - }; - ssiu93: ssiu-47 { - dmas = <&audma0 0x83>, <&audma1 0x84>; - dma-names = "rx", "tx"; - }; - ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; - dma-names = "rx", "tx"; - }; - ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; - dma-names = "rx", "tx"; - }; - ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; - dma-names = "rx", "tx"; - }; - ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; - dma-names = "rx", "tx"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a77961", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, - <&ipmmu_mp 2>, <&ipmmu_mp 3>, - <&ipmmu_mp 4>, <&ipmmu_mp 5>, - <&ipmmu_mp 6>, <&ipmmu_mp 7>, - <&ipmmu_mp 8>, <&ipmmu_mp 9>, - <&ipmmu_mp 10>, <&ipmmu_mp 11>, - <&ipmmu_mp 12>, <&ipmmu_mp 13>, - <&ipmmu_mp 14>, <&ipmmu_mp 15>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a77961", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, - <&ipmmu_mp 18>, <&ipmmu_mp 19>, - <&ipmmu_mp 20>, <&ipmmu_mp 21>, - <&ipmmu_mp 22>, <&ipmmu_mp 23>, - <&ipmmu_mp 24>, <&ipmmu_mp 25>, - <&ipmmu_mp 26>, <&ipmmu_mp 27>, - <&ipmmu_mp 28>, <&ipmmu_mp 29>, - <&ipmmu_mp 30>, <&ipmmu_mp 31>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a77961", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a77961-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 1>; - phy-names = "usb"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 2>; - phy-names = "usb"; - companion = <&ohci1>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a77961", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a77961", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 702>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a77961", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-r8a77961", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; - }; - - sdhi2: mmc@ee140000 { - compatible = "renesas,sdhi-r8a77961", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 312>; - status = "disabled"; - }; - - sdhi3: mmc@ee160000 { - compatible = "renesas,sdhi-r8a77961", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 311>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a77961", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - pciec1: pcie@ee800000 { - compatible = "renesas,pcie-r8a77961", - "renesas,pcie-rcar-gen3"; - reg = <0 0xee800000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, - <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, - <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, - <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - fcpf0: fcp@fe950000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe950000 0 0x200>; - clocks = <&cpg CPG_MOD 615>; - power-domains = <&sysc R8A77961_PD_A3VC>; - resets = <&cpg 615>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A77961_PD_A3VC>; - resets = <&cpg 607>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A77961_PD_A3VC>; - resets = <&cpg 611>; - iommus = <&ipmmu_vc0 19>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - - fcpvd2: fcp@fea37000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea37000 0 0x200>; - clocks = <&cpg CPG_MOD 601>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 601>; - iommus = <&ipmmu_vi0 10>; - }; - - vspb: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A77961_PD_A3VC>; - resets = <&cpg 626>; - - renesas,fcp = <&fcpvb0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 623>; - - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 622>; - - renesas,fcp = <&fcpvd1>; - }; - - vspd2: vsp@fea30000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea30000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 621>; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 621>; - - renesas,fcp = <&fcpvd2>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A77961_PD_A3VC>; - resets = <&cpg 631>; - - renesas,fcp = <&fcpvi0>; - }; - - csi20: csi2@fea80000 { - reg = <0 0xfea80000 0 0x10000>; - /* placeholder */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; - }; - - csi40: csi2@feaa0000 { - reg = <0 0xfeaa0000 0 0x10000>; - /* placeholder */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - }; - }; - }; - - hdmi0: hdmi@fead0000 { - compatible = "renesas,r8a77961-hdmi", "renesas,rcar-gen3-hdmi"; - reg = <0 0xfead0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A77961_CLK_HDMI>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; - resets = <&cpg 729>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dw_hdmi0_in: endpoint { - remote-endpoint = <&du_out_hdmi0>; - }; - }; - port@1 { - reg = <1>; - }; - port@2 { - /* HDMI sound */ - reg = <2>; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a77961"; - reg = <0 0xfeb00000 0 0x70000>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>; - clock-names = "du.0", "du.1", "du.2"; - resets = <&cpg 724>, <&cpg 722>; - reset-names = "du.0", "du.2"; - - renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_hdmi0: endpoint { - remote-endpoint = <&dw_hdmi0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_lvds0: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - sensor_thermal1: sensor-thermal1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - sustainable-power = <3874>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal2: sensor-thermal2 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - sustainable-power = <3874>; - - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal3: sensor-thermal3 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; - sustainable-power = <3874>; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a57_0 2 4>; - contribution = <1024>; - }; - map1 { - trip = <&target>; - cooling-device = <&a53_0 0 2>; - contribution = <1024>; - }; - }; - trips { - target: trip-point1 { - temperature = <100000>; - hysteresis = <1000>; - type = "passive"; - }; - - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts deleted file mode 100644 index 660a0240e..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X board with R-Car M3-N - * - * Copyright (C) 2018 Jacopo Mondi - */ - -/dts-v1/; -#include "r8a77965.dtsi" -#include "salvator-x.dtsi" - -/ { - model = "Renesas Salvator-X board based on r8a77965"; - compatible = "renesas,salvator-x", "renesas,r8a77965"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&x21_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.3", - "dclkin.0", "dclkin.1", "dclkin.3"; -}; - -&hdmi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi0_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint1>; - }; - }; - }; -}; - -&hdmi0_con { - remote-endpoint = <&rcar_dw_hdmi0_out>; -}; - -&rcar_sound { - ports { - rsnd_port1: port@1 { - reg = <1>; - rsnd_endpoint1: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint1>; - frame-master = <&rsnd_endpoint1>; - - playback = <&ssi2>; - }; - }; - }; -}; - -&sound_card { - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1>; /* HDMI0 */ -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts deleted file mode 100644 index 5cef64605..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X 2nd version board with R-Car M3-N - * - * Copyright (C) 2017 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a77965.dtsi" -#include "salvator-xs.dtsi" - -/ { - model = "Renesas Salvator-X 2nd version board based on r8a77965"; - compatible = "renesas,salvator-xs", "renesas,r8a77965"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>, - <&versaclock6 1>, - <&x21_clk>, - <&versaclock6 2>; - clock-names = "du.0", "du.1", "du.3", - "dclkin.0", "dclkin.1", "dclkin.3"; -}; - -&hdmi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi0_snd_in: endpoint { - remote-endpoint = <&rsnd_endpoint1>; - }; - }; - }; -}; - -&hdmi0_con { - remote-endpoint = <&rcar_dw_hdmi0_out>; -}; - -&pca9654 { - pcie_sata_switch { - gpio-hog; - gpios = <7 GPIO_ACTIVE_HIGH>; - output-low; /* enable SATA by default */ - line-name = "PCIE/SATA switch"; - }; -}; - -&rcar_sound { - ports { - rsnd_port1: port@1 { - reg = <1>; - rsnd_endpoint1: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_endpoint1>; - frame-master = <&rsnd_endpoint1>; - - playback = <&ssi2>; - }; - }; - }; -}; - -/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */ -&sata { - status = "okay"; -}; - -&sound_card { - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1>; /* HDMI0 */ -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77965-ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a77965-ulcb-kf.dts deleted file mode 100644 index 12aa08fd6..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77965-ulcb-kf.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the M3NULCB Kingfisher board - * - * Copyright (C) 2018 Renesas Electronics Corp. - * Copyright (C) 2018 Cogent Embedded, Inc. - */ - -#include "r8a77965-ulcb.dts" -#include "ulcb-kf.dtsi" - -/ { - model = "Renesas M3NULCB Kingfisher board based on r8a77965"; - compatible = "shimafuji,kingfisher", "renesas,m3nulcb", - "renesas,r8a77965"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77965-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a77965-ulcb.dts deleted file mode 100644 index 964078b6c..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77965-ulcb.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the M3NULCB (R-Car Starter Kit Pro) board - * - * Copyright (C) 2018 Renesas Electronics Corp. - * Copyright (C) 2018 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77965.dtsi" -#include "ulcb.dtsi" - -/ { - model = "Renesas M3NULCB board based on r8a77965"; - compatible = "renesas,m3nulcb", "renesas,r8a77965"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&versaclock5 3>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.3", - "dclkin.0", "dclkin.1", "dclkin.3"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi deleted file mode 100644 index c355460e5..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ /dev/null @@ -1,2670 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car M3-N (R8A77965) SoC - * - * Copyright (C) 2018 Jacopo Mondi - * - * Based on r8a7796.dtsi - * Copyright (C) 2016 Renesas Electronics Corp. - */ - -#include -#include -#include - -#define CPG_AUDIO_CLK_I R8A77965_CLK_S0D4 - -/ { - compatible = "renesas,r8a77965"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c_dvfs; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <960000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a57_0: cpu@0 { - compatible = "arm,cortex-a57"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A77965_PD_CA57_CPU0>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - #cooling-cells = <2>; - dynamic-power-coefficient = <854>; - clocks = <&cpg CPG_CORE R8A77965_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - }; - - a57_1: cpu@1 { - compatible = "arm,cortex-a57"; - reg = <0x1>; - device_type = "cpu"; - power-domains = <&sysc R8A77965_PD_CA57_CPU1>; - next-level-cache = <&L2_CA57>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks = <&cpg CPG_CORE R8A77965_CLK_Z>; - operating-points-v2 = <&cluster0_opp>; - }; - - L2_CA57: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A77965_PD_CA57_SCU>; - cache-unified; - cache-level = <2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <400>; - exit-latency-us = <500>; - min-residency-us = <4000>; - }; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, - <&a57_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a77965-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 29>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - gpio7: gpio@e6055800 { - compatible = "renesas,gpio-r8a77965", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055800 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 4>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 905>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a77965"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a77965-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a77965-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a77965-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a77965-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77965-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77965-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77965-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a77965-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a77965", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77965", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77965", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77965", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77965", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77965", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77965", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77965", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a77965", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a77965", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a77965", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a77965", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a77965", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a77965", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a77965", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a77965-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a77965-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a77965-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; - status = "disabled"; - }; - - arm_cc630p: crypto@e6601000 { - compatible = "arm,cryptocell-630p-ree"; - interrupts = ; - reg = <0x0 0xe6601000 0 0x1000>; - clocks = <&cpg CPG_MOD 229>; - resets = <&cpg 229>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a77965", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a77965", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a77965", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: iommu@e6570000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp: iommu@ec670000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: iommu@fd800000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt: iommu@ffc80000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: iommu@fe6b0000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A77965_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vp0: iommu@fe990000 { - compatible = "renesas,ipmmu-r8a77965"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A77965_PD_A3VP>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77965", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a77965", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A77965_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a77965", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A77965_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a77965-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A77965_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A77965_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - tpu: pwm@e6e80000 { - compatible = "renesas,tpu-r8a77965", "renesas,tpu"; - reg = <0 0xe6e80000 0 0x148>; - interrupts = ; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a77965", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a77965", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a77965", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a77965", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin0>; - }; - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 810>; - renesas,id = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin1>; - }; - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin2>; - }; - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin3>; - }; - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin4>; - }; - vin4csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin5>; - }; - vin5csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin5>; - }; - }; - }; - }; - - vin6: video@e6ef6000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 805>; - renesas,id = <6>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin6csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin6>; - }; - vin6csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin6>; - }; - }; - }; - }; - - vin7: video@e6ef7000 { - compatible = "renesas,vin-r8a77965"; - reg = <0 0xe6ef7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 804>; - renesas,id = <7>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin7csi20: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi20vin7>; - }; - vin7csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin7>; - }; - }; - }; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a77965", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A77965_CLK_S0D4>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma1 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma1 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma1 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma1 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma1 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma1 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma1 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma1 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma1 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma1 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma1 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma1 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssiu { - ssiu00: ssiu-0 { - dmas = <&audma0 0x15>, <&audma1 0x16>; - dma-names = "rx", "tx"; - }; - ssiu01: ssiu-1 { - dmas = <&audma0 0x35>, <&audma1 0x36>; - dma-names = "rx", "tx"; - }; - ssiu02: ssiu-2 { - dmas = <&audma0 0x37>, <&audma1 0x38>; - dma-names = "rx", "tx"; - }; - ssiu03: ssiu-3 { - dmas = <&audma0 0x47>, <&audma1 0x48>; - dma-names = "rx", "tx"; - }; - ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; - dma-names = "rx", "tx"; - }; - ssiu05: ssiu-5 { - dmas = <&audma0 0x43>, <&audma1 0x44>; - dma-names = "rx", "tx"; - }; - ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; - dma-names = "rx", "tx"; - }; - ssiu07: ssiu-7 { - dmas = <&audma0 0x53>, <&audma1 0x54>; - dma-names = "rx", "tx"; - }; - ssiu10: ssiu-8 { - dmas = <&audma0 0x49>, <&audma1 0x4a>; - dma-names = "rx", "tx"; - }; - ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; - dma-names = "rx", "tx"; - }; - ssiu12: ssiu-10 { - dmas = <&audma0 0x57>, <&audma1 0x58>; - dma-names = "rx", "tx"; - }; - ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; - dma-names = "rx", "tx"; - }; - ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; - dma-names = "rx", "tx"; - }; - ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; - dma-names = "rx", "tx"; - }; - ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; - dma-names = "rx", "tx"; - }; - ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; - dma-names = "rx", "tx"; - }; - ssiu20: ssiu-16 { - dmas = <&audma0 0x63>, <&audma1 0x64>; - dma-names = "rx", "tx"; - }; - ssiu21: ssiu-17 { - dmas = <&audma0 0x67>, <&audma1 0x68>; - dma-names = "rx", "tx"; - }; - ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; - dma-names = "rx", "tx"; - }; - ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; - dma-names = "rx", "tx"; - }; - ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; - dma-names = "rx", "tx"; - }; - ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; - dma-names = "rx", "tx"; - }; - ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; - dma-names = "rx", "tx"; - }; - ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; - dma-names = "rx", "tx"; - }; - ssiu30: ssiu-24 { - dmas = <&audma0 0x6f>, <&audma1 0x70>; - dma-names = "rx", "tx"; - }; - ssiu31: ssiu-25 { - dmas = <&audma0 0x21>, <&audma1 0x22>; - dma-names = "rx", "tx"; - }; - ssiu32: ssiu-26 { - dmas = <&audma0 0x23>, <&audma1 0x24>; - dma-names = "rx", "tx"; - }; - ssiu33: ssiu-27 { - dmas = <&audma0 0x25>, <&audma1 0x26>; - dma-names = "rx", "tx"; - }; - ssiu34: ssiu-28 { - dmas = <&audma0 0x27>, <&audma1 0x28>; - dma-names = "rx", "tx"; - }; - ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; - dma-names = "rx", "tx"; - }; - ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; - dma-names = "rx", "tx"; - }; - ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; - dma-names = "rx", "tx"; - }; - ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; - dma-names = "rx", "tx"; - }; - ssiu41: ssiu-33 { - dmas = <&audma0 0x17>, <&audma1 0x18>; - dma-names = "rx", "tx"; - }; - ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; - dma-names = "rx", "tx"; - }; - ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; - dma-names = "rx", "tx"; - }; - ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; - dma-names = "rx", "tx"; - }; - ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; - dma-names = "rx", "tx"; - }; - ssiu46: ssiu-38 { - dmas = <&audma0 0x31>, <&audma1 0x32>; - dma-names = "rx", "tx"; - }; - ssiu47: ssiu-39 { - dmas = <&audma0 0x33>, <&audma1 0x34>; - dma-names = "rx", "tx"; - }; - ssiu50: ssiu-40 { - dmas = <&audma0 0x73>, <&audma1 0x74>; - dma-names = "rx", "tx"; - }; - ssiu60: ssiu-41 { - dmas = <&audma0 0x75>, <&audma1 0x76>; - dma-names = "rx", "tx"; - }; - ssiu70: ssiu-42 { - dmas = <&audma0 0x79>, <&audma1 0x7a>; - dma-names = "rx", "tx"; - }; - ssiu80: ssiu-43 { - dmas = <&audma0 0x7b>, <&audma1 0x7c>; - dma-names = "rx", "tx"; - }; - ssiu90: ssiu-44 { - dmas = <&audma0 0x7d>, <&audma1 0x7e>; - dma-names = "rx", "tx"; - }; - ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; - dma-names = "rx", "tx"; - }; - ssiu92: ssiu-46 { - dmas = <&audma0 0x81>, <&audma1 0x82>; - dma-names = "rx", "tx"; - }; - ssiu93: ssiu-47 { - dmas = <&audma0 0x83>, <&audma1 0x84>; - dma-names = "rx", "tx"; - }; - ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; - dma-names = "rx", "tx"; - }; - ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; - dma-names = "rx", "tx"; - }; - ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; - dma-names = "rx", "tx"; - }; - ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma1 0x02>; - dma-names = "rx", "tx"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma1 0x04>; - dma-names = "rx", "tx"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma1 0x06>; - dma-names = "rx", "tx"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma1 0x08>; - dma-names = "rx", "tx"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma1 0x0a>; - dma-names = "rx", "tx"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma1 0x0c>; - dma-names = "rx", "tx"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma1 0x0e>; - dma-names = "rx", "tx"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma1 0x10>; - dma-names = "rx", "tx"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma1 0x12>; - dma-names = "rx", "tx"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma1 0x14>; - dma-names = "rx", "tx"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a77965", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - }; - - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a77965", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a77965", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a77965-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 1>; - phy-names = "usb"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1 2>; - phy-names = "usb"; - companion = <&ohci1>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a77965", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a77965", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 702>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a77965", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 314>; - iommus = <&ipmmu_ds1 32>; - status = "disabled"; - }; - - sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-r8a77965", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 313>; - iommus = <&ipmmu_ds1 33>; - status = "disabled"; - }; - - sdhi2: mmc@ee140000 { - compatible = "renesas,sdhi-r8a77965", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 312>; - iommus = <&ipmmu_ds1 34>; - status = "disabled"; - }; - - sdhi3: mmc@ee160000 { - compatible = "renesas,sdhi-r8a77965", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 311>; - iommus = <&ipmmu_ds1 35>; - status = "disabled"; - }; - - sata: sata@ee300000 { - compatible = "renesas,sata-r8a77965", - "renesas,rcar-gen3-sata"; - reg = <0 0xee300000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a77965", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - pciec1: pcie@ee800000 { - compatible = "renesas,pcie-r8a77965", - "renesas,pcie-rcar-gen3"; - reg = <0 0xee800000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, - <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, - <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, - <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 318>; - status = "disabled"; - }; - - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; - power-domains = <&sysc R8A77965_PD_A3VP>; - resets = <&cpg 119>; - renesas,fcp = <&fcpf0>; - }; - - fcpf0: fcp@fe950000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe950000 0 0x200>; - clocks = <&cpg CPG_MOD 615>; - power-domains = <&sysc R8A77965_PD_A3VP>; - resets = <&cpg 615>; - }; - - vspb: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A77965_PD_A3VP>; - resets = <&cpg 626>; - - renesas,fcp = <&fcpvb0>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A77965_PD_A3VP>; - resets = <&cpg 631>; - - renesas,fcp = <&fcpvi0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 623>; - - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 622>; - - renesas,fcp = <&fcpvd1>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A77965_PD_A3VP>; - resets = <&cpg 607>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 603>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 602>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A77965_PD_A3VP>; - resets = <&cpg 611>; - }; - - cmm0: cmm@fea40000 { - compatible = "renesas,r8a77965-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea40000 0 0x1000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 711>; - resets = <&cpg 711>; - }; - - cmm1: cmm@fea50000 { - compatible = "renesas,r8a77965-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea50000 0 0x1000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 710>; - resets = <&cpg 710>; - }; - - cmm3: cmm@fea70000 { - compatible = "renesas,r8a77965-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea70000 0 0x1000>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 708>; - resets = <&cpg 708>; - }; - - csi20: csi2@fea80000 { - compatible = "renesas,r8a77965-csi2"; - reg = <0 0xfea80000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 714>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 714>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi20vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi20>; - }; - csi20vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi20>; - }; - csi20vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi20>; - }; - csi20vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi20>; - }; - csi20vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi20>; - }; - csi20vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi20>; - }; - csi20vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi20>; - }; - csi20vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi20>; - }; - }; - }; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a77965-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - csi40vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi40>; - }; - csi40vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi40>; - }; - csi40vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi40>; - }; - csi40vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi40>; - }; - }; - }; - }; - - hdmi0: hdmi@fead0000 { - compatible = "renesas,r8a77965-hdmi", - "renesas,rcar-gen3-hdmi"; - reg = <0 0xfead0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 729>, - <&cpg CPG_CORE R8A77965_CLK_HDMI>; - clock-names = "iahb", "isfr"; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 729>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dw_hdmi0_in: endpoint { - remote-endpoint = <&du_out_hdmi0>; - }; - }; - port@1 { - reg = <1>; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a77965"; - reg = <0 0xfeb00000 0 0x80000>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 721>; - clock-names = "du.0", "du.1", "du.3"; - resets = <&cpg 724>, <&cpg 722>; - reset-names = "du.0", "du.3"; - - renesas,cmms = <&cmm0>, <&cmm1>, <&cmm3>; - renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - port@1 { - reg = <1>; - du_out_hdmi0: endpoint { - remote-endpoint = <&dw_hdmi0_in>; - }; - }; - port@2 { - reg = <2>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds@feb90000 { - compatible = "renesas,r8a77965-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - sensor_thermal1: sensor-thermal1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - sustainable-power = <2439>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal2: sensor-thermal2 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - sustainable-power = <2439>; - - trips { - sensor2_crit: sensor2-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - sensor_thermal3: sensor-thermal3 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 2>; - sustainable-power = <2439>; - - trips { - target: trip-point1 { - /* miliCelsius */ - temperature = <100000>; - hysteresis = <1000>; - type = "passive"; - }; - - sensor3_crit: sensor3-crit { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a57_0 2 4>; - contribution = <1024>; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts deleted file mode 100644 index 5c28f303e..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ /dev/null @@ -1,273 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Eagle board - * - * Copyright (C) 2016-2017 Renesas Electronics Corp. - * Copyright (C) 2017 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77970.dtsi" - -/ { - model = "Renesas Eagle board based on r8a77970"; - compatible = "renesas,eagle", "renesas,r8a77970"; - - aliases { - serial0 = &scif0; - ethernet0 = &avb; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - d3p3: regulator-fixed { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - lvds-decoder { - compatible = "thine,thc63lvd1024"; - - vcc-supply = <&d3p3>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - thc63lvd1024_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@2 { - reg = <2>; - thc63lvd1024_out: endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - - renesas,no-ether-link; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - status = "okay"; - - phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&canfd { - pinctrl-0 = <&canfd0_pins>; - pinctrl-names = "default"; - status = "okay"; - - channel0 { - status = "okay"; - }; -}; - -&du { - status = "okay"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - io_expander: gpio@20 { - compatible = "onnn,pca9654"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&thc63lvd1024_out>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; -}; - -&lvds0 { - status = "okay"; - - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&thc63lvd1024_in>; - }; - }; - }; -}; - -&pfc { - avb_pins: avb0 { - groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; - function = "avb0"; - }; - - canfd0_pins: canfd0 { - groups = "canfd0_data_a"; - function = "canfd0"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - qspi0_pins: qspi0 { - groups = "qspi0_ctrl", "qspi0_data4"; - function = "qspi0"; - }; - - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; -}; - -&rpc { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fs512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - bootparam@0 { - reg = <0x00000000 0x040000>; - read-only; - }; - cr7@40000 { - reg = <0x00040000 0x080000>; - read-only; - }; - cert_header_sa3@c0000 { - reg = <0x000c0000 0x080000>; - read-only; - }; - bl2@140000 { - reg = <0x00140000 0x040000>; - read-only; - }; - cert_header_sa6@180000 { - reg = <0x00180000 0x040000>; - read-only; - }; - bl31@1c0000 { - reg = <0x001c0000 0x460000>; - read-only; - }; - uboot@640000 { - reg = <0x00640000 0x0c0000>; - read-only; - }; - uboot-env@700000 { - reg = <0x00700000 0x040000>; - read-only; - }; - dtb@740000 { - reg = <0x00740000 0x080000>; - }; - kernel@7c0000 { - reg = <0x007c0000 0x1400000>; - }; - user@1bc0000 { - reg = <0x01bc0000 0x2440000>; - }; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts deleted file mode 100644 index 0c66cc0a1..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ /dev/null @@ -1,293 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the V3M Starter Kit board - * - * Copyright (C) 2017 Renesas Electronics Corp. - * Copyright (C) 2017 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77970.dtsi" - -/ { - model = "Renesas V3M Starter Kit board"; - compatible = "renesas,v3msk", "renesas,r8a77970"; - - aliases { - serial0 = &scif0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - lvds-decoder { - compatible = "thine,thc63lvd1024"; - vcc-supply = <&vcc_d3_3v>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - thc63lvd1024_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@2 { - reg = <2>; - thc63lvd1024_out: endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - osc5_clk: osc5-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - vcc_d1_8v: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "VCC_D1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_d3_3v: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "VCC_D3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_vddq_vin0: regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "VCC_VDDQ_VIN0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - - renesas,no-ether-link; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - status = "okay"; - - phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&osc5_clk>; - clock-names = "du.0", "dclkin.0"; - status = "okay"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - hdmi@39{ - compatible = "adi,adv7511w"; - #sound-dai-cells = <0>; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - avdd-supply = <&vcc_d1_8v>; - dvdd-supply = <&vcc_d1_8v>; - pvdd-supply = <&vcc_d1_8v>; - bgvdd-supply = <&vcc_d1_8v>; - dvdd-3v-supply = <&vcc_d3_3v>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&thc63lvd1024_out>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&lvds0 { - status = "okay"; - - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&thc63lvd1024_in>; - }; - }; - }; -}; - -&mmc0 { - pinctrl-0 = <&mmc_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_d3_3v>; - vqmmc-supply = <&vcc_vddq_vin0>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&pfc { - avb_pins: avb0 { - groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; - function = "avb0"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - mmc_pins: mmc_3_3v { - groups = "mmc_data8", "mmc_ctrl"; - function = "mmc"; - power-source = <3300>; - }; - - qspi0_pins: qspi0 { - groups = "qspi0_ctrl", "qspi0_data4"; - function = "qspi0"; - }; - - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; -}; - -&rpc { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fs512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - bootparam@0 { - reg = <0x00000000 0x040000>; - read-only; - }; - cr7@40000 { - reg = <0x00040000 0x080000>; - read-only; - }; - cert_header_sa3@c0000 { - reg = <0x000c0000 0x080000>; - read-only; - }; - bl2@140000 { - reg = <0x00140000 0x040000>; - read-only; - }; - cert_header_sa6@180000 { - reg = <0x00180000 0x040000>; - read-only; - }; - bl31@1c0000 { - reg = <0x001c0000 0x460000>; - read-only; - }; - uboot@640000 { - reg = <0x00640000 0x0c0000>; - read-only; - }; - uboot-env@700000 { - reg = <0x00700000 0x040000>; - read-only; - }; - dtb@740000 { - reg = <0x00740000 0x080000>; - }; - kernel@7c0000 { - reg = <0x007c0000 0x1400000>; - }; - user@1bc0000 { - reg = <0x01bc0000 0x2440000>; - }; - }; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi deleted file mode 100644 index baf8cc821..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ /dev/null @@ -1,1224 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car V3M (R8A77970) SoC - * - * Copyright (C) 2016-2017 Renesas Electronics Corp. - * Copyright (C) 2017 Cogent Embedded, Inc. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a77970"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a53_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0>; - clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; - power-domains = <&sysc R8A77970_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - }; - - a53_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <1>; - clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; - power-domains = <&sysc R8A77970_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - }; - - L2_CA53: cache-controller { - compatible = "cache"; - power-domains = <&sysc R8A77970_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, <&a53_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a77970-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77970", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 22>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a77970", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 28>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a77970", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77970", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a77970", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 6>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a77970", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a77970"; - reg = <0 0xe6060000 0 0x504>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a77970-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a77970-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a77970-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a77970-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77970-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77970-rst"; - reg = <0 0xe6160000 0 0x200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77970-sysc"; - reg = <0 0xe6180000 0 0x440>; - #power-domain-cells = <1>; - }; - - thermal: thermal@e6190000 { - compatible = "renesas,thermal-r8a77970"; - reg = <0 0xe6190000 0 0x10>, - <0 0xe6190100 0 0x120>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a77970", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 125>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 125>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a77970", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a77970", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 123>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 123>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a77970", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 122>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 122>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a77970", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 121>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 121>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - compatible = "renesas,i2c-r8a77970", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - compatible = "renesas,i2c-r8a77970", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - compatible = "renesas,i2c-r8a77970", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - compatible = "renesas,i2c-r8a77970", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac1 0x97>, <&dmac1 0x96>, - <&dmac2 0x97>, <&dmac2 0x96>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - compatible = "renesas,i2c-r8a77970", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac1 0x99>, <&dmac1 0x98>, - <&dmac2 0x99>, <&dmac2 0x98>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a77970", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a77970", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a77970", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a77970", - "renesas,rcar-gen3-hscif", "renesas,hscif"; - reg = <0 0xe66a0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x37>, <&dmac1 0x36>, - <&dmac2 0x37>, <&dmac2 0x36>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a77970-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A77970_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77970", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_rt 3>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a77970", - "renesas,rcar-gen3-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a77970", - "renesas,rcar-gen3-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a77970", - "renesas,rcar-gen3-scif", - "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x57>, <&dmac1 0x56>, - <&dmac2 0x57>, <&dmac2 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a77970", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A77970_CLK_S2D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x59>, <&dmac1 0x58>, - <&dmac2 0x59>, <&dmac2 0x58>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - tpu: pwm@e6e80000 { - compatible = "renesas,tpu-r8a77970", "renesas,tpu"; - reg = <0 0xe6e80000 0 0x148>; - interrupts = ; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a77970", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a77970", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a77970", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 209>; - dmas = <&dmac1 0x45>, <&dmac1 0x44>, - <&dmac2 0x45>, <&dmac2 0x44>; - dma-names = "tx", "rx", "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a77970", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 208>; - dmas = <&dmac1 0x47>, <&dmac1 0x46>, - <&dmac2 0x47>, <&dmac2 0x46>; - dma-names = "tx", "rx", "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a77970"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a77970"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 810>; - renesas,id = <1>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a77970"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a77970"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a77970", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <8>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a77970", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <8>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ir: iommu@ff8b0000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A77970_PD_A3IR>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt: iommu@ffc80000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 7>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - mmc0: mmc@ee140000 { - compatible = "renesas,sdhi-r8a77970", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 314>; - max-frequency = <200000000>; - iommus = <&ipmmu_ds1 32>; - status = "disabled"; - }; - - rpc: spi@ee200000 { - compatible = "renesas,r8a77970-rpc-if", - "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x200>, - <0 0x08000000 0 0x4000000>, - <0 0xee208000 0 0x100>; - reg-names = "regs", "dirmap", "wbuf"; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - clock-names = "rpc"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 917>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1010000 0 0x1000>, - <0 0xf1020000 0 0x20000>, - <0 0xf1040000 0 0x20000>, - <0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 623>; - renesas,fcp = <&fcpvd0>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 603>; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a77970-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a77970"; - reg = <0 0xfeb00000 0 0x80000>; - interrupts = ; - clocks = <&cpg CPG_MOD 724>; - clock-names = "du.0"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 724>; - reset-names = "du.0"; - renesas,vsps = <&vspd0 0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds-encoder@feb90000 { - compatible = "renesas,r8a77970-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = - <&du_out_lvds0>; - }; - }; - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&thermal>; - - cooling-maps { - }; - - trips { - cpu-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts deleted file mode 100644 index 422ec5374..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts +++ /dev/null @@ -1,357 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Condor board - * - * Copyright (C) 2018 Renesas Electronics Corp. - * Copyright (C) 2018 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77980.dtsi" - -/ { - model = "Renesas Condor board based on r8a77980"; - compatible = "renesas,condor", "renesas,r8a77980"; - - aliases { - serial0 = &scif0; - ethernet0 = &gether; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - d1_8v: regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "D1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - d3_3v: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "D3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - lvds-decoder { - compatible = "thine,thc63lvd1024"; - vcc-supply = <&d3_3v>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - thc63lvd1024_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@2 { - reg = <2>; - thc63lvd1024_out: endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0 0x48000000 0 0x78000000>; - }; - - vddq_vin01: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "VDDQ_VIN01"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - x1_clk: x1-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; -}; - -&canfd { - pinctrl-0 = <&canfd0_pins>; - pinctrl-names = "default"; - status = "okay"; - - channel0 { - status = "okay"; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&x1_clk>; - clock-names = "du.0", "dclkin.0"; - status = "okay"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&gether { - pinctrl-0 = <&gether_pins>; - pinctrl-names = "default"; - - phy-mode = "rgmii-id"; - phy-handle = <&phy0>; - renesas,no-ether-link; - status = "okay"; - - phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio4>; - interrupts = <23 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - io_expander0: gpio@20 { - compatible = "onnn,pca9654"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - io_expander1: gpio@21 { - compatible = "onnn,pca9654"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - avdd-supply = <&d1_8v>; - dvdd-supply = <&d1_8v>; - pvdd-supply = <&d1_8v>; - bgvdd-supply = <&d1_8v>; - dvdd-3v-supply = <&d3_3v>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&thc63lvd1024_out>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&lvds0 { - status = "okay"; - - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&thc63lvd1024_in>; - }; - }; - }; -}; - -&mmc0 { - pinctrl-0 = <&mmc_pins>; - pinctrl-1 = <&mmc_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&d3_3v>; - vqmmc-supply = <&vddq_vin01>; - mmc-hs200-1_8v; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&pciec { - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pcie_phy { - status = "okay"; -}; - -&pfc { - canfd0_pins: canfd0 { - groups = "canfd0_data_a"; - function = "canfd0"; - }; - - gether_pins: gether { - groups = "gether_mdio_a", "gether_rgmii", - "gether_txcrefclk", "gether_txcrefclk_mega"; - function = "gether"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - mmc_pins: mmc { - groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; - function = "mmc"; - power-source = <3300>; - }; - - mmc_pins_uhs: mmc_uhs { - groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; - function = "mmc"; - power-source = <1800>; - }; - - qspi0_pins: qspi0 { - groups = "qspi0_ctrl", "qspi0_data4"; - function = "qspi0"; - }; - - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk_b"; - function = "scif_clk"; - }; -}; - -&rpc { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fs512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - bootparam@0 { - reg = <0x00000000 0x040000>; - read-only; - }; - cr7@40000 { - reg = <0x00040000 0x080000>; - read-only; - }; - cert_header_sa3@c0000 { - reg = <0x000c0000 0x080000>; - read-only; - }; - bl2@140000 { - reg = <0x00140000 0x040000>; - read-only; - }; - cert_header_sa6@180000 { - reg = <0x00180000 0x040000>; - read-only; - }; - bl31@1c0000 { - reg = <0x001c0000 0x460000>; - read-only; - }; - uboot@640000 { - reg = <0x00640000 0x0c0000>; - read-only; - }; - uboot-env@700000 { - reg = <0x00700000 0x040000>; - read-only; - }; - dtb@740000 { - reg = <0x00740000 0x080000>; - }; - kernel@7c0000 { - reg = <0x007c0000 0x1400000>; - }; - user@1bc0000 { - reg = <0x01bc0000 0x2440000>; - }; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts deleted file mode 100644 index 7838dcee3..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts +++ /dev/null @@ -1,282 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the V3H Starter Kit board - * - * Copyright (C) 2018 Renesas Electronics Corp. - * Copyright (C) 2018 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77980.dtsi" - -/ { - model = "Renesas V3H Starter Kit board"; - compatible = "renesas,v3hsk", "renesas,r8a77980"; - - aliases { - serial0 = &scif0; - ethernet0 = &gether; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - lvds-decoder { - compatible = "thine,thc63lvd1024"; - vcc-supply = <&vcc3v3_d5>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - thc63lvd1024_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@2 { - reg = <2>; - thc63lvd1024_out: endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0 0x48000000 0 0x78000000>; - }; - - osc1_clk: osc1-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; - - vcc1v8_d4: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "VCC1V8_D4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc3v3_d5: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "VCC3V3_D5"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&osc1_clk>; - clock-names = "du.0", "dclkin.0"; - status = "okay"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&gether { - pinctrl-0 = <&gether_pins>; - pinctrl-names = "default"; - - phy-mode = "rgmii"; - phy-handle = <&phy0>; - renesas,no-ether-link; - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - interrupt-parent = <&gpio4>; - interrupts = <23 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - hdmi@39 { - compatible = "adi,adv7511w"; - #sound-dai-cells = <0>; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - avdd-supply = <&vcc1v8_d4>; - dvdd-supply = <&vcc1v8_d4>; - pvdd-supply = <&vcc1v8_d4>; - bgvdd-supply = <&vcc1v8_d4>; - dvdd-3v-supply = <&vcc3v3_d5>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&thc63lvd1024_out>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&lvds0 { - status = "okay"; - - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&thc63lvd1024_in>; - }; - }; - }; -}; - -&pfc { - gether_pins: gether { - groups = "gether_mdio_a", "gether_rgmii", - "gether_txcrefclk", "gether_txcrefclk_mega"; - function = "gether"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - qspi0_pins: qspi0 { - groups = "qspi0_ctrl", "qspi0_data4"; - function = "qspi0"; - }; - - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk_b"; - function = "scif_clk"; - }; -}; - -&rpc { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fs512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - bootparam@0 { - reg = <0x00000000 0x040000>; - read-only; - }; - cr7@40000 { - reg = <0x00040000 0x080000>; - read-only; - }; - cert_header_sa3@c0000 { - reg = <0x000c0000 0x080000>; - read-only; - }; - bl2@140000 { - reg = <0x00140000 0x040000>; - read-only; - }; - cert_header_sa6@180000 { - reg = <0x00180000 0x040000>; - read-only; - }; - bl31@1c0000 { - reg = <0x001c0000 0x460000>; - read-only; - }; - uboot@640000 { - reg = <0x00640000 0x0c0000>; - read-only; - }; - uboot-env@700000 { - reg = <0x00700000 0x040000>; - read-only; - }; - dtb@740000 { - reg = <0x00740000 0x080000>; - }; - kernel@7c0000 { - reg = <0x007c0000 0x1400000>; - }; - user@1bc0000 { - reg = <0x01bc0000 0x2440000>; - }; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi deleted file mode 100644 index e6ef837c4..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ /dev/null @@ -1,1622 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car V3H (R8A77980) SoC - * - * Copyright (C) 2018 Renesas Electronics Corp. - * Copyright (C) 2018 Cogent Embedded, Inc. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a77980"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a53_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0>; - clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; - power-domains = <&sysc R8A77980_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - }; - - a53_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <1>; - clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; - power-domains = <&sysc R8A77980_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - }; - - a53_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <2>; - clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; - power-domains = <&sysc R8A77980_PD_CA53_CPU2>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - }; - - a53_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <3>; - clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; - power-domains = <&sysc R8A77980_PD_CA53_CPU3>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - }; - - L2_CA53: cache-controller { - compatible = "cache"; - power-domains = <&sysc R8A77980_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a77980-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77980", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 22>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a77980", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 28>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a77980", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 30>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77980", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 17>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a77980", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 25>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a77980", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 15>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a77980"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a77980-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a77980-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a77980-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a77980-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77980-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77980-rst"; - reg = <0 0xe6160000 0 0x200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77980-sysc"; - reg = <0 0xe6180000 0 0x440>; - #power-domain-cells = <1>; - }; - - tsc: thermal@e6198000 { - compatible = "renesas,r8a77980-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a77980", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - tmu0: timer@e61e0000 { - compatible = "renesas,tmu-r8a77980", "renesas,tmu"; - reg = <0 0xe61e0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 125>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 125>; - status = "disabled"; - }; - - tmu1: timer@e6fc0000 { - compatible = "renesas,tmu-r8a77980", "renesas,tmu"; - reg = <0 0xe6fc0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 124>; - status = "disabled"; - }; - - tmu2: timer@e6fd0000 { - compatible = "renesas,tmu-r8a77980", "renesas,tmu"; - reg = <0 0xe6fd0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 123>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 123>; - status = "disabled"; - }; - - tmu3: timer@e6fe0000 { - compatible = "renesas,tmu-r8a77980", "renesas,tmu"; - reg = <0 0xe6fe0000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 122>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 122>; - status = "disabled"; - }; - - tmu4: timer@ffc00000 { - compatible = "renesas,tmu-r8a77980", "renesas,tmu"; - reg = <0 0xffc00000 0 0x30>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 121>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 121>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - compatible = "renesas,i2c-r8a77980", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - compatible = "renesas,i2c-r8a77980", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - compatible = "renesas,i2c-r8a77980", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - compatible = "renesas,i2c-r8a77980", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 928>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - compatible = "renesas,i2c-r8a77980", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 927>; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - compatible = "renesas,i2c-r8a77980", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac1 0x9b>, <&dmac1 0x9a>, - <&dmac2 0x9b>, <&dmac2 0x9a>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a77980", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a77980", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a77980", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a77980", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x37>, <&dmac1 0x36>, - <&dmac2 0x37>, <&dmac2 0x36>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - pcie_phy: pcie-phy@e65d0000 { - compatible = "renesas,r8a77980-pcie-phy"; - reg = <0 0xe65d0000 0 0x8000>; - #phy-cells = <0>; - clocks = <&cpg CPG_MOD 319>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a77980-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A77980_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77980", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_ds1 33>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x10>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a77980", - "renesas,rcar-gen3-scif", - "renesas,scif"; - reg = <0 0xe6e60000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a77980", - "renesas,rcar-gen3-scif", - "renesas,scif"; - reg = <0 0xe6e68000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a77980", - "renesas,rcar-gen3-scif", - "renesas,scif"; - reg = <0 0xe6c50000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x57>, <&dmac1 0x56>, - <&dmac2 0x57>, <&dmac2 0x56>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a77980", - "renesas,rcar-gen3-scif", - "renesas,scif"; - reg = <0 0xe6c40000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A77980_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x59>, <&dmac1 0x58>, - <&dmac2 0x59>, <&dmac2 0x58>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - tpu: pwm@e6e80000 { - compatible = "renesas,tpu-r8a77980", "renesas,tpu"; - reg = <0 0xe6e80000 0 0x148>; - interrupts = ; - clocks = <&cpg CPG_MOD 304>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 304>; - #pwm-cells = <3>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a77980", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a77980", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a77980", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a77980", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin0: video@e6ef0000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef0000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 811>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 811>; - renesas,id = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin0csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin0>; - }; - }; - }; - }; - - vin1: video@e6ef1000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef1000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 810>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - status = "disabled"; - renesas,id = <1>; - resets = <&cpg 810>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin1csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin1>; - }; - }; - }; - }; - - vin2: video@e6ef2000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef2000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 809>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 809>; - renesas,id = <2>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin2csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin2>; - }; - }; - }; - }; - - vin3: video@e6ef3000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef3000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 808>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 808>; - renesas,id = <3>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin3csi40: endpoint@2 { - reg = <2>; - remote-endpoint = <&csi40vin3>; - }; - }; - }; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi41: endpoint@3 { - reg = <3>; - remote-endpoint = <&csi41vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi41: endpoint@3 { - reg = <3>; - remote-endpoint = <&csi41vin5>; - }; - }; - }; - }; - - vin6: video@e6ef6000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef6000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 805>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 805>; - renesas,id = <6>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin6csi41: endpoint@3 { - reg = <3>; - remote-endpoint = <&csi41vin6>; - }; - }; - }; - }; - - vin7: video@e6ef7000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef7000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 804>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 804>; - renesas,id = <7>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin7csi41: endpoint@3 { - reg = <3>; - remote-endpoint = <&csi41vin7>; - }; - }; - }; - }; - - vin8: video@e6ef8000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef8000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 628>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 628>; - renesas,id = <8>; - status = "disabled"; - }; - - vin9: video@e6ef9000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6ef9000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 627>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 627>; - renesas,id = <9>; - status = "disabled"; - }; - - vin10: video@e6efa000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6efa000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 625>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 625>; - renesas,id = <10>; - status = "disabled"; - }; - - vin11: video@e6efb000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6efb000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 618>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 618>; - renesas,id = <11>; - status = "disabled"; - }; - - vin12: video@e6efc000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6efc000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 612>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 612>; - renesas,id = <12>; - status = "disabled"; - }; - - vin13: video@e6efd000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6efd000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 608>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 608>; - renesas,id = <13>; - status = "disabled"; - }; - - vin14: video@e6efe000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6efe000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 605>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 605>; - renesas,id = <14>; - status = "disabled"; - }; - - vin15: video@e6eff000 { - compatible = "renesas,vin-r8a77980"; - reg = <0 0xe6eff000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 604>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 604>; - renesas,id = <15>; - status = "disabled"; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a77980", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a77980", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - gether: ethernet@e7400000 { - compatible = "renesas,gether-r8a77980"; - reg = <0 0xe7400000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 813>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 813>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ir: iommu@ff8b0000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A77980_PD_A3IR>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt: iommu@ffc80000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: iommu@fe990000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vip0: iommu@e7b00000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xe7b00000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vip1: iommu@e7960000 { - compatible = "renesas,ipmmu-r8a77980"; - reg = <0 0xe7960000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 11>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - mmc0: mmc@ee140000 { - compatible = "renesas,sdhi-r8a77980", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 314>; - max-frequency = <200000000>; - iommus = <&ipmmu_ds1 32>; - status = "disabled"; - }; - - rpc: spi@ee200000 { - compatible = "renesas,r8a77980-rpc-if", - "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x200>, - <0 0x08000000 0 0x4000000>, - <0 0xee208000 0 0x100>; - reg-names = "regs", "dirmap", "wbuf"; - interrupts = ; - clocks = <&cpg CPG_MOD 917>; - clock-names = "rpc"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 917>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec: pcie@fe000000 { - compatible = "renesas,pcie-r8a77980", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x8000000>; - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 319>; - phys = <&pcie_phy>; - phy-names = "pcie"; - status = "disabled"; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 623>; - renesas,fcp = <&fcpvd0>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 603>; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a77980-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi40>; - }; - csi40vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi40>; - }; - csi40vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi40>; - }; - csi40vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi40>; - }; - }; - }; - }; - - csi41: csi2@feab0000 { - compatible = "renesas,r8a77980-csi2"; - reg = <0 0xfeab0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 715>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 715>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi41vin4: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin4csi41>; - }; - csi41vin5: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin5csi41>; - }; - csi41vin6: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin6csi41>; - }; - csi41vin7: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin7csi41>; - }; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a77980"; - reg = <0 0xfeb00000 0 0x80000>; - interrupts = ; - clocks = <&cpg CPG_MOD 724>; - clock-names = "du.0"; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 724>; - reset-names = "du.0"; - renesas,vsps = <&vspd0 0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - }; - }; - - lvds0: lvds-encoder@feb90000 { - compatible = "renesas,r8a77980-lvds"; - reg = <0 0xfeb90000 0 0x14>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = - <&du_out_lvds0>; - }; - }; - - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - thermal-sensor-1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - - trips { - sensor1-passive { - temperature = <95000>; - hysteresis = <1000>; - type = "passive"; - }; - sensor1-critical { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - thermal-sensor-2 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 1>; - - trips { - sensor2-passive { - temperature = <95000>; - hysteresis = <1000>; - type = "passive"; - }; - sensor2-critical { - temperature = <120000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_LOW)>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts deleted file mode 100644 index b9e3b6762..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +++ /dev/null @@ -1,753 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the ebisu board - * - * Copyright (C) 2018 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a77990.dtsi" -#include - -/ { - model = "Renesas Ebisu board based on r8a77990"; - compatible = "renesas,ebisu", "renesas,r8a77990"; - - aliases { - serial0 = &scif2; - ethernet0 = &avb; - mmc0 = &sdhi3; - mmc1 = &sdhi0; - mmc2 = &sdhi1; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - audio_clkout: audio-clkout { - /* - * This is same as <&rcar_sound 0> - * but needed to avoid cs2000/rcar_sound probe dead-lock - */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 50000>; - - brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>; - default-brightness-level = <10>; - - power-supply = <®_12p0v>; - }; - - cvbs-in { - compatible = "composite-video-connector"; - label = "CVBS IN"; - - port { - cvbs_con: endpoint { - remote-endpoint = <&adv7482_ain7>; - }; - }; - }; - - hdmi-in { - compatible = "hdmi-connector"; - label = "HDMI IN"; - type = "a"; - - port { - hdmi_in_con: endpoint { - remote-endpoint = <&adv7482_hdmi>; - }; - }; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - lvds-decoder { - compatible = "thine,thc63lvd1024"; - vcc-supply = <®_3p3v>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - thc63lvd1024_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@2 { - reg = <2>; - thc63lvd1024_out: endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - reg_1p8v: regulator0 { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator1 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_12p0v: regulator2 { - compatible = "regulator-fixed"; - regulator-name = "D12.0V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-boot-on; - regulator-always-on; - }; - - rsnd_ak4613: sound { - compatible = "simple-audio-card"; - - simple-audio-card,name = "rsnd-ak4613"; - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcpu>; - simple-audio-card,frame-master = <&sndcpu>; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4613>; - }; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - }; - - vbus0_usb2: regulator-vbus0-usb2 { - compatible = "regulator-fixed"; - - regulator-name = "USB20_VBUS_CN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7123_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - port@1 { - reg = <1>; - adv7123_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - x12_clk: x12 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - x13_clk: x13 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; -}; - -&audio_clk_a { - clock-frequency = <22579200>; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - phy-handle = <&phy0>; - status = "okay"; - - phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio2>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - /* - * TX clock internal delay mode is required for reliable - * 1Gbps communication using the KSZ9031RNX phy present on - * the Ebisu board, however, TX clock internal delay mode - * isn't supported on r8a77990. Thus, limit speed to - * 100Mbps for reliable communication. - */ - max-speed = <100>; - }; -}; - -&canfd { - pinctrl-0 = <&canfd0_pins>; - pinctrl-names = "default"; - status = "okay"; - - channel0 { - status = "okay"; - }; -}; - -&csi40 { - status = "okay"; - - ports { - port@0 { - reg = <0>; - - csi40_in: endpoint { - clock-lanes = <0>; - data-lanes = <1 2>; - remote-endpoint = <&adv7482_txa>; - }; - }; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&x13_clk>; - clock-names = "du.0", "du.1", "dclkin.0"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7123_in>; - }; - }; - }; -}; - -&ehci0 { - dr_mode = "otg"; - status = "okay"; -}; - -&extal_clk { - clock-frequency = <48000000>; -}; - -&hsusb { - dr_mode = "otg"; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - io_expander: gpio@20 { - compatible = "onnn,pca9654"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio2>; - interrupts = <22 IRQ_TYPE_LEVEL_LOW>; - }; - - hdmi-encoder@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&thc63lvd1024_out>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; - - video-receiver@70 { - compatible = "adi,adv7482"; - reg = <0x70>; - - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gpio0>; - interrupt-names = "intrq1", "intrq2"; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>, - <17 IRQ_TYPE_LEVEL_LOW>; - - port@7 { - reg = <7>; - - adv7482_ain7: endpoint { - remote-endpoint = <&cvbs_con>; - }; - }; - - port@8 { - reg = <8>; - - adv7482_hdmi: endpoint { - remote-endpoint = <&hdmi_in_con>; - }; - }; - - port@a { - reg = <10>; - - adv7482_txa: endpoint { - clock-lanes = <0>; - data-lanes = <1 2>; - remote-endpoint = <&csi40_in>; - }; - }; - }; -}; - -&i2c3 { - status = "okay"; - - ak4613: codec@10 { - compatible = "asahi-kasei,ak4613"; - #sound-dai-cells = <0>; - reg = <0x10>; - clocks = <&rcar_sound 3>; - - asahi-kasei,in1-single-end; - asahi-kasei,in2-single-end; - asahi-kasei,out1-single-end; - asahi-kasei,out2-single-end; - asahi-kasei,out3-single-end; - asahi-kasei,out4-single-end; - asahi-kasei,out5-single-end; - asahi-kasei,out6-single-end; - }; - - cs2000: clk-multiplier@4f { - #clock-cells = <0>; - compatible = "cirrus,cs2000-cp"; - reg = <0x4f>; - clocks = <&audio_clkout>, <&x12_clk>; - clock-names = "clk_in", "ref_clk"; - - assigned-clocks = <&cs2000>; - assigned-clock-rates = <24576000>; /* 1/1 divide */ - }; -}; - -&i2c_dvfs { - status = "okay"; - - clock-frequency = <400000>; - - pmic: pmic@30 { - pinctrl-0 = <&irq0_pins>; - pinctrl-names = "default"; - - compatible = "rohm,bd9571mwv"; - reg = <0x30>; - interrupt-parent = <&intc_ex>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - rohm,ddr-backup-power = <0x1>; - rohm,rstbmode-level; - }; -}; - -&lvds0 { - status = "okay"; - - clocks = <&cpg CPG_MOD 727>, - <&x13_clk>, - <&extal_clk>; - clock-names = "fck", "dclkin.0", "extal"; - - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&thc63lvd1024_in>; - }; - }; - }; -}; - -&lvds1 { - /* - * Even though the LVDS1 output is not connected, the encoder must be - * enabled to supply a pixel clock to the DU for the DPAD output when - * LVDS0 is in use. - */ - status = "okay"; - - clocks = <&cpg CPG_MOD 727>, - <&x13_clk>, - <&extal_clk>; - clock-names = "fck", "dclkin.0", "extal"; -}; - -&ohci0 { - dr_mode = "otg"; - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pciec0 { - status = "okay"; -}; - -&pfc { - avb_pins: avb { - groups = "avb_link", "avb_mii"; - function = "avb"; - }; - - canfd0_pins: canfd0 { - groups = "canfd0_data"; - function = "canfd0"; - }; - - du_pins: du { - groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; - function = "du"; - }; - - irq0_pins: irq0 { - groups = "intc_ex_irq0"; - function = "intc_ex"; - }; - - pwm3_pins: pwm3 { - groups = "pwm3_b"; - function = "pwm3"; - }; - - pwm5_pins: pwm5 { - groups = "pwm5_a"; - function = "pwm5"; - }; - - scif2_pins: scif2 { - groups = "scif2_data_a"; - function = "scif2"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <3300>; - }; - - sdhi1_pins_uhs: sd1_uhs { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <1800>; - }; - - sdhi3_pins: sd3 { - groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; - function = "sdhi3"; - power-source = <1800>; - }; - - sound_clk_pins: sound_clk { - groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a", - "audio_clkout_a", "audio_clkout1_a"; - function = "audio_clk"; - }; - - sound_pins: sound { - groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data"; - function = "ssi"; - }; - - usb0_pins: usb { - groups = "usb0_b", "usb0_id"; - function = "usb0"; - }; - - usb30_pins: usb30 { - groups = "usb30"; - function = "usb30"; - }; -}; - -&pwm3 { - pinctrl-0 = <&pwm3_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pwm5 { - pinctrl-0 = <&pwm5_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins &sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - /* audio_clkout0/1/2/3 */ - #clock-cells = <1>; - clock-frequency = <12288000 11289600>; - - status = "okay"; - - /* update to */ - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&cs2000>, <&audio_clk_c>, - <&cpg CPG_CORE R8A77990_CLK_ZA2>; - - rcar_sound,dai { - dai0 { - playback = <&ssi0 &src0 &dvc0>; - capture = <&ssi1 &src1 &dvc1>; - }; - }; - -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; - bus-width = <4>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-1 = <&sdhi1_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>; - bus-width = <4>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi3 { - /* used for on-board 8bit eMMC */ - pinctrl-0 = <&sdhi3_pins>; - pinctrl-1 = <&sdhi3_pins>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - non-removable; - full-pwr-cycle-in-suspend; - status = "okay"; -}; - -&ssi1 { - shared-pin; -}; - -&usb2_phy0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - vbus-supply = <&vbus0_usb2>; - status = "okay"; -}; - -&usb3_peri0 { - companion = <&xhci0>; - status = "okay"; -}; - -&vin4 { - status = "okay"; -}; - -&vin5 { - status = "okay"; -}; - -&xhci0 { - pinctrl-0 = <&usb30_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi deleted file mode 100644 index 33d7e657b..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ /dev/null @@ -1,2066 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car E3 (R8A77990) SoC - * - * Copyright (C) 2018-2019 Renesas Electronics Corp. - */ - -#include -#include -#include - -/ { - compatible = "renesas,r8a77990"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - }; - - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster1_opp: opp_table10 { - compatible = "operating-points-v2"; - opp-shared; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a53_0: cpu@0 { - compatible = "arm,cortex-a53"; - reg = <0>; - device_type = "cpu"; - #cooling-cells = <2>; - power-domains = <&sysc R8A77990_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - dynamic-power-coefficient = <277>; - clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - a53_1: cpu@1 { - compatible = "arm,cortex-a53"; - reg = <1>; - device_type = "cpu"; - power-domains = <&sysc R8A77990_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP_0>; - clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - L2_CA53: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A77990_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010000>; - local-timer-stop; - entry-latency-us = <700>; - exit-latency-us = <700>; - min-residency-us = <5000>; - }; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>, <&a53_1>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc: soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a77990-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77990", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a77990", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 23>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a77990", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 26>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77990", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 16>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a77990", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 11>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a77990", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 20>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a77990", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 18>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a77990"; - reg = <0 0xe6060000 0 0x508>; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a77990"; - reg = <0 0xe60b0000 0 0x15>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - cmt0: timer@e60f0000 { - compatible = "renesas,r8a77990-cmt0", - "renesas,rcar-gen3-cmt0"; - reg = <0 0xe60f0000 0 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 303>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 303>; - status = "disabled"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a77990-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 302>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 302>; - status = "disabled"; - }; - - cmt2: timer@e6140000 { - compatible = "renesas,r8a77990-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6140000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 301>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 301>; - status = "disabled"; - }; - - cmt3: timer@e6148000 { - compatible = "renesas,r8a77990-cmt1", - "renesas,rcar-gen3-cmt1"; - reg = <0 0xe6148000 0 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 300>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 300>; - status = "disabled"; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77990-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; - clock-names = "extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77990-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77990-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - thermal: thermal@e6190000 { - compatible = "renesas,thermal-r8a77990"; - reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a77990", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; - status = "disabled"; - }; - - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c7: i2c@e6690000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77990", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6690000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 1003>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 1003>; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a77990", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a77990", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 519>; - status = "disabled"; - }; - - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a77990", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 518>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a77990", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a77990", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 516>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a77990", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a77990-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a77990-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - arm_cc630p: crypto@e6601000 { - compatible = "arm,cryptocell-630p-ree"; - interrupts = ; - reg = <0x0 0xe6601000 0 0x1000>; - clocks = <&cpg CPG_MOD 229>; - resets = <&cpg 229>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a77990", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, - <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, - <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, - <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, - <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a77990", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, - <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, - <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, - <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, - <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a77990", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, - <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, - <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, - <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, - <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; - }; - - ipmmu_ds0: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: iommu@e6570000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp: iommu@ec670000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: iommu@fd800000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt: iommu@ffc80000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: iommu@fe6b0000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A77990_PD_A3VC>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vp0: iommu@fe990000 { - compatible = "renesas,ipmmu-r8a77990"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77990", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a77990", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A77990_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a77990", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A77990_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a77990-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A77990_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a77990", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a77990", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a77990", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a77990", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a77990", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a77990", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A77990_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x5b>, <&dmac0 0x5a>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a77990", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a77990", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac0 0x43>, <&dmac0 0x42>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a77990", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a77990", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a77990"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin4csi40: endpoint@2 { - reg = <2>; - remote-endpoint= <&csi40vin4>; - }; - }; - }; - }; - - vin5: video@e6ef5000 { - compatible = "renesas,vin-r8a77990"; - reg = <0 0xe6ef5000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 806>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 806>; - renesas,id = <5>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - vin5csi40: endpoint@2 { - reg = <2>; - remote-endpoint= <&csi40vin5>; - }; - }; - }; - }; - - drif00: rif@e6f40000 { - compatible = "renesas,r8a77990-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f40000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 515>; - clock-names = "fck"; - dmas = <&dmac1 0x20>, <&dmac2 0x20>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 515>; - renesas,bonding = <&drif01>; - status = "disabled"; - }; - - drif01: rif@e6f50000 { - compatible = "renesas,r8a77990-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f50000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 514>; - clock-names = "fck"; - dmas = <&dmac1 0x22>, <&dmac2 0x22>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 514>; - renesas,bonding = <&drif00>; - status = "disabled"; - }; - - drif10: rif@e6f60000 { - compatible = "renesas,r8a77990-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f60000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 513>; - clock-names = "fck"; - dmas = <&dmac1 0x24>, <&dmac2 0x24>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 513>; - renesas,bonding = <&drif11>; - status = "disabled"; - }; - - drif11: rif@e6f70000 { - compatible = "renesas,r8a77990-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f70000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 512>; - clock-names = "fck"; - dmas = <&dmac1 0x26>, <&dmac2 0x26>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 512>; - renesas,bonding = <&drif10>; - status = "disabled"; - }; - - drif20: rif@e6f80000 { - compatible = "renesas,r8a77990-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f80000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 511>; - clock-names = "fck"; - dmas = <&dmac0 0x28>; - dma-names = "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 511>; - renesas,bonding = <&drif21>; - status = "disabled"; - }; - - drif21: rif@e6f90000 { - compatible = "renesas,r8a77990-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f90000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 510>; - clock-names = "fck"; - dmas = <&dmac0 0x2a>; - dma-names = "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 510>; - renesas,bonding = <&drif20>; - status = "disabled"; - }; - - drif30: rif@e6fa0000 { - compatible = "renesas,r8a77990-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fa0000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 509>; - clock-names = "fck"; - dmas = <&dmac0 0x2c>; - dma-names = "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 509>; - renesas,bonding = <&drif31>; - status = "disabled"; - }; - - drif31: rif@e6fb0000 { - compatible = "renesas,r8a77990-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fb0000 0 0x84>; - interrupts = ; - clocks = <&cpg CPG_MOD 508>; - clock-names = "fck"; - dmas = <&dmac0 0x2e>; - dma-names = "rx"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 508>; - renesas,bonding = <&drif30>; - status = "disabled"; - }; - - rcar_sound: sound@ec500000 { - /* - * #sound-dai-cells is required - * - * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; - * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; - */ - /* - * #clock-cells is required for audio_clkout0/1/2/3 - * - * clkout : #clock-cells = <0>; <&rcar_sound>; - * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; - */ - compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ - reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, - <&audio_clk_c>, - <&cpg CPG_CORE R8A77990_CLK_ZA2>; - clock-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0", - "src.9", "src.8", "src.7", "src.6", - "src.5", "src.4", "src.3", "src.2", - "src.1", "src.0", - "mix.1", "mix.0", - "ctu.1", "ctu.0", - "dvc.0", "dvc.1", - "clk_a", "clk_b", "clk_c", "clk_i"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 1005>, - <&cpg 1006>, <&cpg 1007>, - <&cpg 1008>, <&cpg 1009>, - <&cpg 1010>, <&cpg 1011>, - <&cpg 1012>, <&cpg 1013>, - <&cpg 1014>, <&cpg 1015>; - reset-names = "ssi-all", - "ssi.9", "ssi.8", "ssi.7", "ssi.6", - "ssi.5", "ssi.4", "ssi.3", "ssi.2", - "ssi.1", "ssi.0"; - status = "disabled"; - - rcar_sound,ctu { - ctu00: ctu-0 { }; - ctu01: ctu-1 { }; - ctu02: ctu-2 { }; - ctu03: ctu-3 { }; - ctu10: ctu-4 { }; - ctu11: ctu-5 { }; - ctu12: ctu-6 { }; - ctu13: ctu-7 { }; - }; - - rcar_sound,dvc { - dvc0: dvc-0 { - dmas = <&audma0 0xbc>; - dma-names = "tx"; - }; - dvc1: dvc-1 { - dmas = <&audma0 0xbe>; - dma-names = "tx"; - }; - }; - - rcar_sound,mix { - mix0: mix-0 { }; - mix1: mix-1 { }; - }; - - rcar_sound,src { - src0: src-0 { - interrupts = ; - dmas = <&audma0 0x85>, <&audma0 0x9a>; - dma-names = "rx", "tx"; - }; - src1: src-1 { - interrupts = ; - dmas = <&audma0 0x87>, <&audma0 0x9c>; - dma-names = "rx", "tx"; - }; - src2: src-2 { - interrupts = ; - dmas = <&audma0 0x89>, <&audma0 0x9e>; - dma-names = "rx", "tx"; - }; - src3: src-3 { - interrupts = ; - dmas = <&audma0 0x8b>, <&audma0 0xa0>; - dma-names = "rx", "tx"; - }; - src4: src-4 { - interrupts = ; - dmas = <&audma0 0x8d>, <&audma0 0xb0>; - dma-names = "rx", "tx"; - }; - src5: src-5 { - interrupts = ; - dmas = <&audma0 0x8f>, <&audma0 0xb2>; - dma-names = "rx", "tx"; - }; - src6: src-6 { - interrupts = ; - dmas = <&audma0 0x91>, <&audma0 0xb4>; - dma-names = "rx", "tx"; - }; - src7: src-7 { - interrupts = ; - dmas = <&audma0 0x93>, <&audma0 0xb6>; - dma-names = "rx", "tx"; - }; - src8: src-8 { - interrupts = ; - dmas = <&audma0 0x95>, <&audma0 0xb8>; - dma-names = "rx", "tx"; - }; - src9: src-9 { - interrupts = ; - dmas = <&audma0 0x97>, <&audma0 0xba>; - dma-names = "rx", "tx"; - }; - }; - - rcar_sound,ssi { - ssi0: ssi-0 { - interrupts = ; - dmas = <&audma0 0x01>, <&audma0 0x02>, - <&audma0 0x15>, <&audma0 0x16>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi1: ssi-1 { - interrupts = ; - dmas = <&audma0 0x03>, <&audma0 0x04>, - <&audma0 0x49>, <&audma0 0x4a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi2: ssi-2 { - interrupts = ; - dmas = <&audma0 0x05>, <&audma0 0x06>, - <&audma0 0x63>, <&audma0 0x64>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi3: ssi-3 { - interrupts = ; - dmas = <&audma0 0x07>, <&audma0 0x08>, - <&audma0 0x6f>, <&audma0 0x70>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi4: ssi-4 { - interrupts = ; - dmas = <&audma0 0x09>, <&audma0 0x0a>, - <&audma0 0x71>, <&audma0 0x72>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi5: ssi-5 { - interrupts = ; - dmas = <&audma0 0x0b>, <&audma0 0x0c>, - <&audma0 0x73>, <&audma0 0x74>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi6: ssi-6 { - interrupts = ; - dmas = <&audma0 0x0d>, <&audma0 0x0e>, - <&audma0 0x75>, <&audma0 0x76>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi7: ssi-7 { - interrupts = ; - dmas = <&audma0 0x0f>, <&audma0 0x10>, - <&audma0 0x79>, <&audma0 0x7a>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi8: ssi-8 { - interrupts = ; - dmas = <&audma0 0x11>, <&audma0 0x12>, - <&audma0 0x7b>, <&audma0 0x7c>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - ssi9: ssi-9 { - interrupts = ; - dmas = <&audma0 0x13>, <&audma0 0x14>, - <&audma0 0x7d>, <&audma0 0x7e>; - dma-names = "rx", "tx", "rxu", "txu"; - }; - }; - }; - - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a77990", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, - <&ipmmu_mp 2>, <&ipmmu_mp 3>, - <&ipmmu_mp 4>, <&ipmmu_mp 5>, - <&ipmmu_mp 6>, <&ipmmu_mp 7>, - <&ipmmu_mp 8>, <&ipmmu_mp 9>, - <&ipmmu_mp 10>, <&ipmmu_mp 11>, - <&ipmmu_mp 12>, <&ipmmu_mp 13>, - <&ipmmu_mp 14>, <&ipmmu_mp 15>; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a77990", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a77990-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a77990", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi0: mmc@ee100000 { - compatible = "renesas,sdhi-r8a77990", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 314>; - iommus = <&ipmmu_ds1 32>; - status = "disabled"; - }; - - sdhi1: mmc@ee120000 { - compatible = "renesas,sdhi-r8a77990", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 313>; - iommus = <&ipmmu_ds1 33>; - status = "disabled"; - }; - - sdhi3: mmc@ee160000 { - compatible = "renesas,sdhi-r8a77990", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 311>; - iommus = <&ipmmu_ds1 35>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - pciec0: pcie@fe000000 { - compatible = "renesas,pcie-r8a77990", - "renesas,pcie-rcar-gen3"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, - <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, - <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, - <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - /* Map all possible DDR as inbound ranges */ - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; - interrupts = , - , - ; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 319>; - status = "disabled"; - }; - - vspb0: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 626>; - renesas,fcp = <&fcpvb0>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 607>; - iommus = <&ipmmu_vp0 5>; - }; - - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 631>; - renesas,fcp = <&fcpvi0>; - }; - - fcpvi0: fcp@fe9af000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9af000 0 0x200>; - clocks = <&cpg CPG_MOD 611>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 611>; - iommus = <&ipmmu_vp0 8>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x7000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 623>; - renesas,fcp = <&fcpvd0>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x7000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 622>; - renesas,fcp = <&fcpvd1>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - - cmm0: cmm@fea40000 { - compatible = "renesas,r8a77990-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea40000 0 0x1000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 711>; - resets = <&cpg 711>; - }; - - cmm1: cmm@fea50000 { - compatible = "renesas,r8a77990-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea50000 0 0x1000>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 710>; - resets = <&cpg 710>; - }; - - csi40: csi2@feaa0000 { - compatible = "renesas,r8a77990-csi2"; - reg = <0 0xfeaa0000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 716>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 716>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi40vin4: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin4csi40>; - }; - csi40vin5: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin5csi40>; - }; - }; - }; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a77990"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - resets = <&cpg 724>; - reset-names = "du.0"; - - renesas,cmms = <&cmm0>, <&cmm1>; - renesas,vsps = <&vspd0 0>, <&vspd1 0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - - port@2 { - reg = <2>; - du_out_lvds1: endpoint { - remote-endpoint = <&lvds1_in>; - }; - }; - }; - }; - - lvds0: lvds-encoder@feb90000 { - compatible = "renesas,r8a77990-lvds"; - reg = <0 0xfeb90000 0 0x20>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - renesas,companion = <&lvds1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - lvds1: lvds-encoder@feb90100 { - compatible = "renesas,r8a77990-lvds"; - reg = <0 0xfeb90100 0 0x20>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 726>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds1_in: endpoint { - remote-endpoint = <&du_out_lvds1>; - }; - }; - - port@1 { - reg = <1>; - lvds1_out: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <0>; - thermal-sensors = <&thermal 0>; - sustainable-power = <717>; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&a53_0 0 2>; - contribution = <1024>; - }; - }; - - trips { - sensor1_crit: sensor1-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - - target: trip-point1 { - temperature = <100000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts deleted file mode 100644 index 2e4bb7ecd..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts +++ /dev/null @@ -1,520 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Draak board - * - * Copyright (C) 2016-2018 Renesas Electronics Corp. - * Copyright (C) 2017 Glider bvba - */ - -/dts-v1/; -#include "r8a77995.dtsi" -#include - -/ { - model = "Renesas Draak board based on r8a77995"; - compatible = "renesas,draak", "renesas,r8a77995"; - - aliases { - serial0 = &scif2; - ethernet0 = &avb; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 50000>; - - brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>; - default-brightness-level = <10>; - - power-supply = <®_12p0v>; - enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - composite-in { - compatible = "composite-video-connector"; - - port { - composite_con_in: endpoint { - remote-endpoint = <&adv7180_in>; - }; - }; - }; - - hdmi-in { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&adv7612_in>; - }; - }; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_out: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - lvds-decoder { - compatible = "thine,thc63lvd1024"; - vcc-supply = <®_3p3v>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - thc63lvd1024_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@2 { - reg = <2>; - thc63lvd1024_out: endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x18000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_12p0v: regulator-12p0v { - compatible = "regulator-fixed"; - regulator-name = "D12.0V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-boot-on; - regulator-always-on; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7123_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - port@1 { - reg = <1>; - adv7123_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - x12_clk: x12 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <74250000>; - }; -}; - -&avb { - pinctrl-0 = <&avb0_pins>; - pinctrl-names = "default"; - renesas,no-ether-link; - phy-handle = <&phy0>; - status = "okay"; - - phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio5>; - interrupts = <19 IRQ_TYPE_LEVEL_LOW>; - /* - * TX clock internal delay mode is required for reliable - * 1Gbps communication using the KSZ9031RNX phy present on - * the Draak board, however, TX clock internal delay mode - * isn't supported on r8a77995. Thus, limit speed to - * 100Mbps for reliable communication. - */ - max-speed = <100>; - }; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&can1 { - pinctrl-0 = <&can1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&x12_clk>; - clock-names = "du.0", "du.1", "dclkin.0"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7123_in>; - }; - }; - }; -}; - -&ehci0 { - dr_mode = "host"; - status = "okay"; -}; - -&extal_clk { - clock-frequency = <48000000>; -}; - -&hsusb { - dr_mode = "host"; - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - status = "okay"; - - composite-in@20 { - compatible = "adi,adv7180cp"; - reg = <0x20>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7180_in: endpoint { - remote-endpoint = <&composite_con_in>; - }; - }; - - port@3 { - reg = <3>; - - /* - * The VIN4 video input path is shared between - * CVBS and HDMI inputs through SW[49-53] - * switches. - * - * CVBS is the default selection, link it to - * VIN4 here. - */ - adv7180_out: endpoint { - remote-endpoint = <&vin4_in>; - }; - }; - }; - - }; - - hdmi-encoder@39 { - compatible = "adi,adv7511w"; - reg = <0x39>, <0x3f>, <0x3c>, <0x38>; - reg-names = "main", "edid", "cec", "packet"; - interrupt-parent = <&gpio1>; - interrupts = <28 IRQ_TYPE_LEVEL_LOW>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&thc63lvd1024_out>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con_out>; - }; - }; - }; - }; - - hdmi-decoder@4c { - compatible = "adi,adv7612"; - reg = <0x4c>; - default-input = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adv7612_in: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; - - port@2 { - reg = <2>; - - /* - * The VIN4 video input path is shared between - * CVBS and HDMI inputs through SW[49-53] - * switches. - * - * CVBS is the default selection, leave HDMI - * not connected here. - */ - adv7612_out: endpoint { - pclk-sample = <0>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; - }; - }; - - eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&lvds0 { - status = "okay"; - - clocks = <&cpg CPG_MOD 727>, - <&x12_clk>, - <&extal_clk>; - clock-names = "fck", "dclkin.0", "extal"; - - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&thc63lvd1024_in>; - }; - }; - }; -}; - -&lvds1 { - /* - * Even though the LVDS1 output is not connected, the encoder must be - * enabled to supply a pixel clock to the DU for the DPAD output when - * LVDS0 is in use. - */ - status = "okay"; - - clocks = <&cpg CPG_MOD 727>, - <&x12_clk>, - <&extal_clk>; - clock-names = "fck", "dclkin.0", "extal"; -}; - -&ohci0 { - dr_mode = "host"; - status = "okay"; -}; - -&pfc { - avb0_pins: avb { - groups = "avb0_link", "avb0_mdio", "avb0_mii"; - function = "avb0"; - }; - - can0_pins: can0 { - groups = "can0_data_a"; - function = "can0"; - }; - - can1_pins: can1 { - groups = "can1_data_a"; - function = "can1"; - }; - - du_pins: du { - groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; - function = "du"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - pwm0_pins: pwm0 { - groups = "pwm0_c"; - function = "pwm0"; - }; - - pwm1_pins: pwm1 { - groups = "pwm1_c"; - function = "pwm1"; - }; - - scif2_pins: scif2 { - groups = "scif2_data"; - function = "scif2"; - }; - - sdhi2_pins: sd2 { - groups = "mmc_data8", "mmc_ctrl"; - function = "mmc"; - power-source = <1800>; - }; - - sdhi2_pins_uhs: sd2_uhs { - groups = "mmc_data8", "mmc_ctrl"; - function = "mmc"; - power-source = <1800>; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - vin4_pins_cvbs: vin4 { - groups = "vin4_data8", "vin4_sync", "vin4_clk"; - function = "vin4"; - }; -}; - -&pwm0 { - pinctrl-0 = <&pwm0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pwm1 { - pinctrl-0 = <&pwm1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi2 { - /* used for on-board eMMC */ - pinctrl-0 = <&sdhi2_pins>; - pinctrl-1 = <&sdhi2_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - bus-width = <8>; - mmc-hs200-1_8v; - non-removable; - status = "okay"; -}; - -&usb2_phy0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - renesas,no-otg-pins; - status = "okay"; -}; - -&vin4 { - pinctrl-0 = <&vin4_pins_cvbs>; - pinctrl-names = "default"; - - status = "okay"; - - ports { - port { - vin4_in: endpoint { - remote-endpoint = <&adv7180_out>; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi deleted file mode 100644 index cd7ca9774..000000000 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ /dev/null @@ -1,1153 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car D3 (R8A77995) SoC - * - * Copyright (C) 2016 Renesas Electronics Corp. - * Copyright (C) 2017 Glider bvba - */ - -#include -#include -#include - -/ { - compatible = "renesas,r8a77995"; - #address-cells = <2>; - #size-cells = <2>; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a53_0: cpu@0 { - compatible = "arm,cortex-a53"; - reg = <0x0>; - device_type = "cpu"; - power-domains = <&sysc R8A77995_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - }; - - L2_CA53: cache-controller-1 { - compatible = "cache"; - power-domains = <&sysc R8A77995_PD_CA53_SCU>; - cache-unified; - cache-level = <2>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - pmu_a53 { - compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a77995-wdt", - "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 9>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - - gpio1: gpio@e6051000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6051000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 911>; - }; - - gpio2: gpio@e6052000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6052000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 910>; - }; - - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 10>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; - - gpio4: gpio@e6054000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6054000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 32>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 908>; - }; - - gpio5: gpio@e6055000 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 21>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 907>; - }; - - gpio6: gpio@e6055400 { - compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio"; - reg = <0 0xe6055400 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 14>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 906>; - }; - - pfc: pinctrl@e6060000 { - compatible = "renesas,pfc-r8a77995"; - reg = <0 0xe6060000 0 0x508>; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77995-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; - clock-names = "extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77995-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77995-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - thermal: thermal@e6190000 { - compatible = "renesas,thermal-r8a77995"; - reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <0>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a77995", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a77995", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 520>; - status = "disabled"; - }; - - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a77995", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 517>; - status = "disabled"; - }; - - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a77995", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0 3>; - phy-names = "usb"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 704>, <&cpg 703>; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a77995-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a77995-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = , - ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - arm_cc630p: crypto@e6601000 { - compatible = "arm,cryptocell-630p-ree"; - interrupts = ; - reg = <0x0 0xe6601000 0 0x1000>; - clocks = <&cpg CPG_MOD 229>; - resets = <&cpg 229>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a77995-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A77995_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a77995", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <8>; - iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, - <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, - <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, - <&ipmmu_ds0 6>, <&ipmmu_ds0 7>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a77995", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <8>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a77995", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <8>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; - }; - - ipmmu_ds0: iommu@e6740000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: iommu@e7740000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_hc: iommu@e6570000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: iommu@e67b0000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mp: iommu@ec670000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_pv0: iommu@fd800000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_rt: iommu@ffc80000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vc0: iommu@fe6b0000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vi0: iommu@febd0000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vp0: iommu@fe990000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77995", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - can0: can@e6c30000 { - compatible = "renesas,can-r8a77995", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A77995_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; - }; - - can1: can@e6c38000 { - compatible = "renesas,can-r8a77995", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A77995_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 523>; - status = "disabled"; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a77995", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 207>; - status = "disabled"; - }; - - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a77995", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a77995", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a77995", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a77995", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a77995", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a77995", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a77995", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a77995", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a77995", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - vin4: video@e6ef4000 { - compatible = "renesas,vin-r8a77995"; - reg = <0 0xe6ef4000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 807>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 807>; - renesas,id = <4>; - status = "disabled"; - }; - - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 1>; - phy-names = "usb"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - phys = <&usb2_phy0 2>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a77995", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 703>, <&cpg 704>; - #phy-cells = <1>; - status = "disabled"; - }; - - sdhi2: mmc@ee140000 { - compatible = "renesas,sdhi-r8a77995", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 312>; - iommus = <&ipmmu_ds1 34>; - status = "disabled"; - }; - - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - vspbs: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 627>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 627>; - renesas,fcp = <&fcpvb0>; - }; - - vspd0: vsp@fea20000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 623>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 623>; - renesas,fcp = <&fcpvd0>; - }; - - vspd1: vsp@fea28000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 622>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 622>; - renesas,fcp = <&fcpvd1>; - }; - - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 607>; - iommus = <&ipmmu_vp0 5>; - }; - - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - - cmm0: cmm@fea40000 { - compatible = "renesas,r8a77995-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea40000 0 0x1000>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 711>; - resets = <&cpg 711>; - }; - - cmm1: cmm@fea50000 { - compatible = "renesas,r8a77995-cmm", - "renesas,rcar-gen3-cmm"; - reg = <0 0xfea50000 0 0x1000>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - clocks = <&cpg CPG_MOD 710>; - resets = <&cpg 710>; - }; - - du: display@feb00000 { - compatible = "renesas,du-r8a77995"; - reg = <0 0xfeb00000 0 0x40000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; - clock-names = "du.0", "du.1"; - resets = <&cpg 724>; - reset-names = "du.0"; - - renesas,cmms = <&cmm0>, <&cmm1>; - renesas,vsps = <&vspd0 0>, <&vspd1 0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - du_out_rgb: endpoint { - }; - }; - - port@1 { - reg = <1>; - du_out_lvds0: endpoint { - remote-endpoint = <&lvds0_in>; - }; - }; - - port@2 { - reg = <2>; - du_out_lvds1: endpoint { - remote-endpoint = <&lvds1_in>; - }; - }; - }; - }; - - lvds0: lvds-encoder@feb90000 { - compatible = "renesas,r8a77995-lvds"; - reg = <0 0xfeb90000 0 0x20>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 727>; - status = "disabled"; - - renesas,companion = <&lvds1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&du_out_lvds0>; - }; - }; - - port@1 { - reg = <1>; - lvds0_out: endpoint { - }; - }; - }; - }; - - lvds1: lvds-encoder@feb90100 { - compatible = "renesas,r8a77995-lvds"; - reg = <0 0xfeb90100 0 0x20>; - clocks = <&cpg CPG_MOD 727>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 726>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - lvds1_in: endpoint { - remote-endpoint = <&du_out_lvds1>; - }; - }; - - port@1 { - reg = <1>; - lvds1_out: endpoint { - }; - }; - }; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&thermal>; - - cooling-maps { - }; - - trips { - cpu-crit { - temperature = <120000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi deleted file mode 100644 index 4ba269a4c..000000000 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi +++ /dev/null @@ -1,46 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Falcon CPU board - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include "r8a779a0.dtsi" - -/ { - model = "Renesas Falcon CPU board"; - compatible = "renesas,falcon-cpu", "renesas,r8a779a0"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@500000000 { - device_type = "memory"; - reg = <0x5 0x00000000 0x0 0x80000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x80000000>; - }; - - memory@700000000 { - device_type = "memory"; - reg = <0x7 0x00000000 0x0 0x80000000>; - }; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&scif0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts deleted file mode 100644 index 8eda70e5a..000000000 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Falcon CPU and BreakOut boards - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a779a0-falcon-cpu.dtsi" - -/ { - model = "Renesas Falcon CPU and Breakout boards based on r8a779a0"; - compatible = "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0"; - - aliases { - serial0 = &scif0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi deleted file mode 100644 index bfbb53bf5..000000000 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car V3U (R8A779A0) SoC - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -#include -#include -#include - -/ { - compatible = "renesas,r8a779a0"; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - a76_0: cpu@0 { - compatible = "arm,cortex-a76"; - reg = <0>; - device_type = "cpu"; - power-domains = <&sysc R8A779A0_PD_A1E0D0C0>; - next-level-cache = <&L3_CA76_0>; - }; - - L3_CA76_0: cache-controller-0 { - compatible = "cache"; - power-domains = <&sysc R8A779A0_PD_A2E0D0>; - cache-unified; - cache-level = <3>; - }; - }; - - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - extalr_clk: extalr { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board */ - clock-frequency = <0>; - }; - - pmu_a76 { - compatible = "arm,cortex-a76-pmu"; - interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - soc: soc { - compatible = "simple-bus"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a779a0-cpg-mssr"; - reg = <0 0xe6150000 0 0x4000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a779a0-rst"; - reg = <0 0xe6160000 0 0x4000>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a779a0-sysc"; - reg = <0 0xe6180000 0 0x4000>; - #power-domain-cells = <1>; - }; - - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a779a0", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>, - <&cpg CPG_CORE R8A779A0_CLK_S1D2>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 702>; - status = "disabled"; - }; - - gic: interrupt-controller@f1000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1000000 0 0x20000>, - <0x0 0xf1060000 0 0x110000>; - interrupts = ; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/rzg2-advantech-idk-1110wr-panel.dtsi b/arch/arm64/boot/dts/renesas/rzg2-advantech-idk-1110wr-panel.dtsi deleted file mode 100644 index bcc21178a..000000000 --- a/arch/arm64/boot/dts/renesas/rzg2-advantech-idk-1110wr-panel.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Advantech idk-1110wr LVDS panel connected - * to RZ/G2 boards - * - * Copyright (C) 2019 Renesas Electronics Corp. - */ - -/ { - panel-lvds { - compatible = "advantech,idk-1110wr", "panel-lvds"; - - width-mm = <223>; - height-mm = <125>; - - data-mapping = "jeida-24"; - - panel-timing { - /* 1024x600 @60Hz */ - clock-frequency = <51200000>; - hactive = <1024>; - vactive = <600>; - hsync-len = <240>; - hfront-porch = <40>; - hback-porch = <40>; - vfront-porch = <15>; - vback-porch = <10>; - vsync-len = <10>; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds_connector>; - }; - }; - }; -}; - -&lvds_connector { - remote-endpoint = <&panel_in>; -}; diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi deleted file mode 100644 index 08b8525bb..000000000 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ /dev/null @@ -1,935 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for common parts of Salvator-X board variants - * - * Copyright (C) 2015-2016 Renesas Electronics Corp. - */ - -/* - * SSI-AK4613 - * - * This command is required when Playback/Capture - * - * amixer set "DVC Out" 100% - * amixer set "DVC In" 100% - * - * You can use Mute - * - * amixer set "DVC Out Mute" on - * amixer set "DVC In Mute" on - * - * You can use Volume Ramp - * - * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" - * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" - * amixer set "DVC Out Ramp" on - * aplay xxx.wav & - * amixer set "DVC Out" 80% // Volume Down - * amixer set "DVC Out" 100% // Volume Up - */ - -#include -#include - -/ { - aliases { - serial0 = &scif2; - serial1 = &hscif1; - ethernet0 = &avb; - mmc0 = &sdhi2; - mmc1 = &sdhi0; - mmc2 = &sdhi3; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - audio_clkout: audio-clkout { - /* - * This is same as <&rcar_sound 0> - * but needed to avoid cs2000/rcar_sound probe dead-lock - */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12288000>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 50000>; - - brightness-levels = <256 128 64 16 8 4 0>; - default-brightness-level = <6>; - - power-supply = <®_12v>; - enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - }; - - cvbs-in { - compatible = "composite-video-connector"; - label = "CVBS IN"; - - port { - cvbs_con: endpoint { - remote-endpoint = <&adv7482_ain7>; - }; - }; - }; - - hdmi-in { - compatible = "hdmi-connector"; - label = "HDMI IN"; - type = "a"; - - port { - hdmi_in_con: endpoint { - remote-endpoint = <&adv7482_hdmi>; - }; - }; - }; - - hdmi0-out { - compatible = "hdmi-connector"; - label = "HDMI0 OUT"; - type = "a"; - - port { - hdmi0_con: endpoint { - }; - }; - }; - - hdmi1-out { - compatible = "hdmi-connector"; - label = "HDMI1 OUT"; - type = "a"; - - port { - hdmi1_con: endpoint { - }; - }; - }; - - keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&keys_pins>; - pinctrl-names = "default"; - - key-1 { - gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW4-1"; - wakeup-source; - debounce-interval = <20>; - }; - key-2 { - gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW4-2"; - wakeup-source; - debounce-interval = <20>; - }; - key-3 { - gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW4-3"; - wakeup-source; - debounce-interval = <20>; - }; - key-4 { - gpios = <&gpio5 23 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW4-4"; - wakeup-source; - debounce-interval = <20>; - }; - key-a { - gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "TSW0"; - wakeup-source; - debounce-interval = <20>; - }; - key-b { - gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "TSW1"; - wakeup-source; - debounce-interval = <20>; - }; - key-c { - gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "TSW2"; - wakeup-source; - debounce-interval = <20>; - }; - }; - - reg_1p8v: regulator0 { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator1 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_12v: regulator2 { - compatible = "regulator-fixed"; - regulator-name = "fixed-12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-boot-on; - regulator-always-on; - }; - - sound_card: sound { - compatible = "audio-graph-card"; - - label = "rcar-sound"; - - dais = <&rsnd_port0>; - }; - - vbus0_usb2: regulator-vbus0-usb2 { - compatible = "regulator-fixed"; - - regulator-name = "USB20_VBUS0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vcc_sdhi3: regulator-vcc-sdhi3 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI3 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi3: regulator-vccq-sdhi3 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI3 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vga { - compatible = "vga-connector"; - - port { - vga_in: endpoint { - remote-endpoint = <&adv7123_out>; - }; - }; - }; - - vga-encoder { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7123_in: endpoint { - remote-endpoint = <&du_out_rgb>; - }; - }; - port@1 { - reg = <1>; - adv7123_out: endpoint { - remote-endpoint = <&vga_in>; - }; - }; - }; - }; - - x12_clk: x12 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - /* External DU dot clocks */ - x21_clk: x21-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <33000000>; - }; - - x22_clk: x22-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <33000000>; - }; - - x23_clk: x23-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; -}; - -&audio_clk_a { - clock-frequency = <22579200>; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - phy-handle = <&phy0>; - phy-mode = "rgmii-txid"; - status = "okay"; - - phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio2>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; - }; -}; - -&csi20 { - status = "okay"; - - ports { - port@0 { - reg = <0>; - csi20_in: endpoint { - clock-lanes = <0>; - data-lanes = <1>; - remote-endpoint = <&adv7482_txb>; - }; - }; - }; -}; - -&csi40 { - status = "okay"; - - ports { - port@0 { - reg = <0>; - - csi40_in: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&adv7482_txa>; - }; - }; - }; -}; - -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - ports { - port@0 { - endpoint { - remote-endpoint = <&adv7123_in>; - }; - }; - }; -}; - -&ehci0 { - dr_mode = "otg"; - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&hscif1 { - pinctrl-0 = <&hscif1_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - /* Please only enable hscif1 or scif1 */ - status = "okay"; -}; - -&hsusb { - dr_mode = "otg"; - status = "okay"; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - - status = "okay"; - - clock-frequency = <100000>; - - ak4613: codec@10 { - compatible = "asahi-kasei,ak4613"; - #sound-dai-cells = <0>; - reg = <0x10>; - clocks = <&rcar_sound 3>; - - asahi-kasei,in1-single-end; - asahi-kasei,in2-single-end; - asahi-kasei,out1-single-end; - asahi-kasei,out2-single-end; - asahi-kasei,out3-single-end; - asahi-kasei,out4-single-end; - asahi-kasei,out5-single-end; - asahi-kasei,out6-single-end; - - port { - ak4613_endpoint: endpoint { - remote-endpoint = <&rsnd_endpoint0>; - }; - }; - }; - - cs2000: clk_multiplier@4f { - #clock-cells = <0>; - compatible = "cirrus,cs2000-cp"; - reg = <0x4f>; - clocks = <&audio_clkout>, <&x12_clk>; - clock-names = "clk_in", "ref_clk"; - - assigned-clocks = <&cs2000>; - assigned-clock-rates = <24576000>; /* 1/1 divide */ - }; -}; - -&i2c4 { - status = "okay"; - - pca9654: gpio@20 { - compatible = "onnn,pca9654"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - video-receiver@70 { - compatible = "adi,adv7482"; - reg = <0x70 0x71 0x72 0x73 0x74 0x75 - 0x60 0x61 0x62 0x63 0x64 0x65>; - reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater", - "infoframe", "cbus", "cec", "sdp", "txa", "txb" ; - - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gpio6>; - interrupt-names = "intrq1", "intrq2"; - interrupts = <30 IRQ_TYPE_LEVEL_LOW>, - <31 IRQ_TYPE_LEVEL_LOW>; - - port@7 { - reg = <7>; - - adv7482_ain7: endpoint { - remote-endpoint = <&cvbs_con>; - }; - }; - - port@8 { - reg = <8>; - - adv7482_hdmi: endpoint { - remote-endpoint = <&hdmi_in_con>; - }; - }; - - port@a { - reg = <10>; - - adv7482_txa: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&csi40_in>; - }; - }; - - port@b { - reg = <11>; - - adv7482_txb: endpoint { - clock-lanes = <0>; - data-lanes = <1>; - remote-endpoint = <&csi20_in>; - }; - }; - }; - - csa_vdd: adc@7c { - compatible = "maxim,max9611"; - reg = <0x7c>; - - shunt-resistor-micro-ohms = <5000>; - }; - - csa_dvfs: adc@7f { - compatible = "maxim,max9611"; - reg = <0x7f>; - - shunt-resistor-micro-ohms = <5000>; - }; -}; - -&i2c_dvfs { - status = "okay"; - - clock-frequency = <400000>; - - pmic: pmic@30 { - pinctrl-0 = <&irq0_pins>; - pinctrl-names = "default"; - - compatible = "rohm,bd9571mwv"; - reg = <0x30>; - interrupt-parent = <&intc_ex>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - rohm,ddr-backup-power = <0xf>; - rohm,rstbmode-level; - - regulators { - dvfs: dvfs { - regulator-name = "dvfs"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1030000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - eeprom@50 { - compatible = "rohm,br24t01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; - }; -}; - -&ohci0 { - dr_mode = "otg"; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pciec0 { - status = "okay"; -}; - -&pciec1 { - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - avb_pins: avb { - mux { - groups = "avb_link", "avb_mdio", "avb_mii"; - function = "avb"; - }; - - pins_mdio { - groups = "avb_mdio"; - drive-strength = <24>; - }; - - pins_mii_tx { - pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", - "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; - drive-strength = <12>; - }; - }; - - du_pins: du { - groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0"; - function = "du"; - }; - - hscif1_pins: hscif1 { - groups = "hscif1_data_a", "hscif1_ctrl_a"; - function = "hscif1"; - }; - - i2c2_pins: i2c2 { - groups = "i2c2_a"; - function = "i2c2"; - }; - - irq0_pins: irq0 { - groups = "intc_ex_irq0"; - function = "intc_ex"; - }; - - keys_pins: keys { - pins = "GP_5_17", "GP_5_20", "GP_5_22"; - bias-pull-up; - }; - - pwm1_pins: pwm1 { - groups = "pwm1_a"; - function = "pwm1"; - }; - - scif1_pins: scif1 { - groups = "scif1_data_a", "scif1_ctrl"; - function = "scif1"; - }; - - scif2_pins: scif2 { - groups = "scif2_data_a"; - function = "scif2"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk_a"; - function = "scif_clk"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; - function = "sdhi2"; - power-source = <1800>; - }; - - sdhi3_pins: sd3 { - groups = "sdhi3_data4", "sdhi3_ctrl"; - function = "sdhi3"; - power-source = <3300>; - }; - - sdhi3_pins_uhs: sd3_uhs { - groups = "sdhi3_data4", "sdhi3_ctrl"; - function = "sdhi3"; - power-source = <1800>; - }; - - sound_pins: sound { - groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; - function = "ssi"; - }; - - sound_clk_pins: sound_clk { - groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", - "audio_clkout_a", "audio_clkout3_a"; - function = "audio_clk"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - mux { - groups = "usb1"; - function = "usb1"; - }; - - ovc { - pins = "GP_6_27"; - bias-pull-up; - }; - - pwen { - pins = "GP_6_26"; - bias-pull-down; - }; - }; - - usb30_pins: usb30 { - groups = "usb30"; - function = "usb30"; - }; -}; - -&pwm1 { - pinctrl-0 = <&pwm1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins &sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - /* audio_clkout0/1/2/3 */ - #clock-cells = <1>; - clock-frequency = <12288000 11289600>; - - status = "okay"; - - /* update to */ - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&cs2000>, - <&audio_clk_c>, - <&cpg CPG_CORE CPG_AUDIO_CLK_I>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - rsnd_port0: port@0 { - reg = <0>; - rsnd_endpoint0: endpoint { - remote-endpoint = <&ak4613_endpoint>; - - dai-format = "left_j"; - bitclock-master = <&rsnd_endpoint0>; - frame-master = <&rsnd_endpoint0>; - - playback = <&ssi0 &src0 &dvc0>; - capture = <&ssi1 &src1 &dvc1>; - }; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif1 { - pinctrl-0 = <&scif1_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - /* Please only enable hscif1 or scif1 */ - /* status = "okay"; */ -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; - bus-width = <4>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi2 { - /* used for on-board 8bit eMMC */ - pinctrl-0 = <&sdhi2_pins>; - pinctrl-1 = <&sdhi2_pins>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - bus-width = <8>; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - non-removable; - fixed-emmc-driver-type = <1>; - full-pwr-cycle-in-suspend; - status = "okay"; -}; - -&sdhi3 { - pinctrl-0 = <&sdhi3_pins>; - pinctrl-1 = <&sdhi3_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi3>; - vqmmc-supply = <&vccq_sdhi3>; - cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; - bus-width = <4>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&ssi1 { - shared-pin; -}; - -&usb_extal_clk { - clock-frequency = <50000000>; -}; - -&usb2_phy0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - vbus-supply = <&vbus0_usb2>; - status = "okay"; -}; - -&usb2_phy1 { - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&usb3_peri0 { - phys = <&usb3_phy0>; - phy-names = "usb"; - - companion = <&xhci0>; - - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb3s0_clk { - clock-frequency = <100000000>; -}; - -&vin0 { - status = "okay"; -}; - -&vin1 { - status = "okay"; -}; - -&vin2 { - status = "okay"; -}; - -&vin3 { - status = "okay"; -}; - -&vin4 { - status = "okay"; -}; - -&vin5 { - status = "okay"; -}; - -&vin6 { - status = "okay"; -}; - -&vin7 { - status = "okay"; -}; - -&xhci0 { - pinctrl-0 = <&usb30_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/salvator-x.dtsi b/arch/arm64/boot/dts/renesas/salvator-x.dtsi deleted file mode 100644 index ddee50e64..000000000 --- a/arch/arm64/boot/dts/renesas/salvator-x.dtsi +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X board - * - * Copyright (C) 2015-2016 Renesas Electronics Corp. - */ - -#include "salvator-common.dtsi" - -/ { - model = "Renesas Salvator-X board"; - compatible = "renesas,salvator-x"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&i2c4 { - clock-frequency = <400000>; - - versaclock5: clock-generator@6a { - compatible = "idt,5p49v5923"; - reg = <0x6a>; - #clock-cells = <1>; - clocks = <&x23_clk>; - clock-names = "xin"; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/salvator-xs.dtsi b/arch/arm64/boot/dts/renesas/salvator-xs.dtsi deleted file mode 100644 index 717d42758..000000000 --- a/arch/arm64/boot/dts/renesas/salvator-xs.dtsi +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X 2nd version board - * - * Copyright (C) 2015-2017 Renesas Electronics Corp. - */ - -#include "salvator-common.dtsi" - -/ { - model = "Renesas Salvator-X 2nd version board"; - compatible = "renesas,salvator-xs"; -}; - -&extal_clk { - clock-frequency = <16640000>; -}; - -&i2c4 { - clock-frequency = <400000>; - - versaclock6: clock-generator@6a { - compatible = "idt,5p49v6901"; - reg = <0x6a>; - #clock-cells = <1>; - clocks = <&x23_clk>; - clock-names = "xin"; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi deleted file mode 100644 index 05e64bfad..000000000 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ /dev/null @@ -1,383 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Kingfisher (ULCB extension) board - * - * Copyright (C) 2017 Renesas Electronics Corp. - * Copyright (C) 2017 Cogent Embedded, Inc. - */ - -/* - * SSI-PCM3168A - * aplay -D plughw:0,2 xxx.wav - * arecord -D plughw:0,3 xxx.wav - */ - -/ { - aliases { - serial1 = &hscif0; - serial2 = &scif1; - mmc2 = &sdhi3; - }; - - clksndsel: clksndsel { - #clock-cells = <0>; - compatible = "gpio-mux-clock"; - clocks = <&cs2000>, <&audio_clk_a>; /* clk8snd, clksnd */ - select-gpios = <&gpio_exp_75 13 GPIO_ACTIVE_HIGH>; - }; - - snd_3p3v: regulator-snd_3p3v { - compatible = "regulator-fixed"; - regulator-name = "snd-3.3v"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - snd_vcc5v: regulator-snd_vcc5v { - compatible = "regulator-fixed"; - regulator-name = "snd-vcc5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - wlan_en: regulator-wlan_en { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio_exp_74 4 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&can1 { - pinctrl-0 = <&can1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&ehci0 { - dr_mode = "otg"; - status = "okay"; -}; - -&hscif0 { - pinctrl-0 = <&hscif0_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - status = "okay"; -}; - -&hsusb { - dr_mode = "otg"; - status = "okay"; -}; - -&i2c2 { - i2cswitch2: i2c-switch@71 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; - - /* Audio_SDA, Audio_SCL */ - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - - pcm3168a: audio-codec@44 { - #sound-dai-cells = <0>; - compatible = "ti,pcm3168a"; - reg = <0x44>; - clocks = <&clksndsel>; - clock-names = "scki"; - - VDD1-supply = <&snd_3p3v>; - VDD2-supply = <&snd_3p3v>; - VCCAD1-supply = <&snd_vcc5v>; - VCCAD2-supply = <&snd_vcc5v>; - VCCDA1-supply = <&snd_vcc5v>; - VCCDA2-supply = <&snd_vcc5v>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - mclk-fs = <512>; - port@0 { - reg = <0>; - pcm3168a_endpoint_p: endpoint { - remote-endpoint = <&rsnd_for_pcm3168a_play>; - clocks = <&clksndsel>; - }; - }; - port@1 { - reg = <1>; - pcm3168a_endpoint_c: endpoint { - remote-endpoint = <&rsnd_for_pcm3168a_capture>; - clocks = <&clksndsel>; - }; - }; - }; - }; - }; - }; - - /* U11 */ - gpio_exp_74: gpio@74 { - compatible = "ti,tca9539"; - reg = <0x74>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio6>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - audio_out_off { - gpio-hog; - gpios = <0 GPIO_ACTIVE_HIGH>; /* P00 */ - output-high; - line-name = "Audio_Out_OFF"; - }; - - hub_pwen { - gpio-hog; - gpios = <6 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "HUB pwen"; - }; - - hub_rst { - gpio-hog; - gpios = <7 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "HUB rst"; - }; - - otg_extlpn { - gpio-hog; - gpios = <9 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "OTG EXTLPn"; - }; - - otg_offvbusn { - gpio-hog; - gpios = <8 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "OTG OFFVBUSn"; - }; - - sd-wifi-mux { - gpio-hog; - gpios = <5 GPIO_ACTIVE_HIGH>; - output-low; /* Connect WL1837 */ - line-name = "SD WiFi mux"; - }; - - snd_rst { - gpio-hog; - gpios = <15 GPIO_ACTIVE_HIGH>; /* P17 */ - output-high; - line-name = "SND_RST"; - }; - }; - - /* U5 */ - gpio_exp_75: gpio@75 { - compatible = "ti,tca9539"; - reg = <0x75>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio6>; - interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&i2c4 { - i2cswitch4: i2c-switch@71 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; - }; - - gpio_exp_76: gpio@76 { - compatible = "ti,tca9539"; - reg = <0x76>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio7>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - }; - - gpio_exp_77: gpio@77 { - compatible = "ti,tca9539"; - reg = <0x77>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio5>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&ohci0 { - dr_mode = "otg"; - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pciec0 { - status = "okay"; -}; - -&pciec1 { - status = "okay"; -}; - -&pfc { - can0_pins: can0 { - groups = "can0_data_a"; - function = "can0"; - }; - - can1_pins: can1 { - groups = "can1_data"; - function = "can1"; - }; - - hscif0_pins: hscif0 { - groups = "hscif0_data", "hscif0_ctrl"; - function = "hscif0"; - }; - - scif1_pins: scif1 { - groups = "scif1_data_b", "scif1_ctrl"; - function = "scif1"; - }; - - sdhi3_pins: sdhi3 { - groups = "sdhi3_data4", "sdhi3_ctrl"; - function = "sdhi3"; - power-source = <3300>; - }; - - sound_pcm_pins: sound-pcm { - groups = "ssi349_ctrl", "ssi3_data", "ssi4_data"; - function = "ssi"; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins - &sound_clk_pins - &sound_pcm_pins>; - - ports { - /* rsnd_port0/1 are on salvator-common */ - rsnd_port2: port@2 { - reg = <2>; - rsnd_for_pcm3168a_play: endpoint { - remote-endpoint = <&pcm3168a_endpoint_p>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_for_pcm3168a_play>; - frame-master = <&rsnd_for_pcm3168a_play>; - dai-tdm-slot-num = <8>; - - playback = <&ssi3>; - }; - }; - rsnd_port3: port@3 { - reg = <3>; - rsnd_for_pcm3168a_capture: endpoint { - remote-endpoint = <&pcm3168a_endpoint_c>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_for_pcm3168a_capture>; - frame-master = <&rsnd_for_pcm3168a_capture>; - dai-tdm-slot-num = <6>; - - capture = <&ssi4>; - }; - }; - }; -}; - -&scif1 { - pinctrl-0 = <&scif1_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - status = "okay"; -}; - -&sdhi3 { - pinctrl-0 = <&sdhi3_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&wlan_en>; - vqmmc-supply = <&wlan_en>; - bus-width = <4>; - no-1-8-v; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - max-frequency = <26000000>; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1837"; - reg = <2>; - interrupt-parent = <&gpio1>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&sound_card { - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1 /* HDMI0 */ - &rsnd_port2 /* pcm3168a playback */ - &rsnd_port3 /* pcm3168a capture */ - >; -}; - -&ssi4 { - shared-pin; -}; - -&usb2_phy0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&xhci0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi deleted file mode 100644 index e11521b4b..000000000 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ /dev/null @@ -1,487 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car Gen3 ULCB board - * - * Copyright (C) 2016 Renesas Electronics Corp. - * Copyright (C) 2016 Cogent Embedded, Inc. - */ - -/* - * SSI-AK4613 - * aplay -D plughw:0,0 xxx.wav - * arecord -D plughw:0,0 xxx.wav - * SSI-HDMI - * aplay -D plughw:0,1 xxx.wav - */ - -#include -#include - -/ { - model = "Renesas R-Car Gen3 ULCB board"; - - aliases { - serial0 = &scif2; - ethernet0 = &avb; - mmc0 = &sdhi2; - mmc1 = &sdhi0; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; - }; - - audio_clkout: audio-clkout { - /* - * This is same as <&rcar_sound 0> - * but needed to avoid cs2000/rcar_sound probe dead-lock - */ - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12288000>; - }; - - hdmi0-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi0_con: endpoint { - }; - }; - }; - - keyboard { - compatible = "gpio-keys"; - - key-1 { - linux,code = ; - label = "SW3"; - wakeup-source; - debounce-interval = <20>; - gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led5 { - gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; - }; - led6 { - gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_1p8v: regulator0 { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator1 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sound_card: sound { - compatible = "audio-graph-card"; - label = "rcar-sound"; - - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1 /* HDMI0 */ - >; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - x12_clk: x12 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; - - x23_clk: x23-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; -}; - -&audio_clk_a { - clock-frequency = <22579200>; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - phy-handle = <&phy0>; - phy-mode = "rgmii-txid"; - status = "okay"; - - phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio2>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; - }; -}; - -&du { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&hdmi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - rcar_dw_hdmi0_out: endpoint { - remote-endpoint = <&hdmi0_con>; - }; - }; - port@2 { - reg = <2>; - dw_hdmi0_snd_in: endpoint { - remote-endpoint = <&rsnd_for_hdmi>; - }; - }; - }; -}; - -&hdmi0_con { - remote-endpoint = <&rcar_dw_hdmi0_out>; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - - status = "okay"; - - clock-frequency = <100000>; - - ak4613: codec@10 { - compatible = "asahi-kasei,ak4613"; - #sound-dai-cells = <0>; - reg = <0x10>; - clocks = <&rcar_sound 3>; - - asahi-kasei,in1-single-end; - asahi-kasei,in2-single-end; - asahi-kasei,out1-single-end; - asahi-kasei,out2-single-end; - asahi-kasei,out3-single-end; - asahi-kasei,out4-single-end; - asahi-kasei,out5-single-end; - asahi-kasei,out6-single-end; - - port { - ak4613_endpoint: endpoint { - remote-endpoint = <&rsnd_for_ak4613>; - }; - }; - }; - - cs2000: clk-multiplier@4f { - #clock-cells = <0>; - compatible = "cirrus,cs2000-cp"; - reg = <0x4f>; - clocks = <&audio_clkout>, <&x12_clk>; - clock-names = "clk_in", "ref_clk"; - - assigned-clocks = <&cs2000>; - assigned-clock-rates = <24576000>; /* 1/1 divide */ - }; -}; - -&i2c4 { - status = "okay"; - - clock-frequency = <400000>; - - versaclock5: clock-generator@6a { - compatible = "idt,5p49v5925"; - reg = <0x6a>; - #clock-cells = <1>; - clocks = <&x23_clk>; - clock-names = "xin"; - }; -}; - -&i2c_dvfs { - status = "okay"; - - clock-frequency = <400000>; - - pmic: pmic@30 { - pinctrl-0 = <&irq0_pins>; - pinctrl-names = "default"; - - compatible = "rohm,bd9571mwv"; - reg = <0x30>; - interrupt-parent = <&intc_ex>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - rohm,ddr-backup-power = <0xf>; - rohm,rstbmode-pulse; - - regulators { - dvfs: dvfs { - regulator-name = "dvfs"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1030000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&ohci1 { - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - avb_pins: avb { - mux { - groups = "avb_link", "avb_mdio", "avb_mii"; - function = "avb"; - }; - - pins_mdio { - groups = "avb_mdio"; - drive-strength = <24>; - }; - - pins_mii_tx { - pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", - "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; - drive-strength = <12>; - }; - }; - - i2c2_pins: i2c2 { - groups = "i2c2_a"; - function = "i2c2"; - }; - - irq0_pins: irq0 { - groups = "intc_ex_irq0"; - function = "intc_ex"; - }; - - scif2_pins: scif2 { - groups = "scif2_data_a"; - function = "scif2"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk_a"; - function = "scif_clk"; - }; - - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi2_pins: sd2 { - groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; - function = "sdhi2"; - power-source = <1800>; - }; - - sound_pins: sound { - groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; - function = "ssi"; - }; - - sound_clk_pins: sound-clk { - groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", - "audio_clkout_a", "audio_clkout3_a"; - function = "audio_clk"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; -}; - -&rcar_sound { - pinctrl-0 = <&sound_pins &sound_clk_pins>; - pinctrl-names = "default"; - - /* Single DAI */ - #sound-dai-cells = <0>; - - /* audio_clkout0/1/2/3 */ - #clock-cells = <1>; - clock-frequency = <12288000 11289600>; - - status = "okay"; - - /* update to */ - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&cs2000>, - <&audio_clk_c>, - <&cpg CPG_CORE CPG_AUDIO_CLK_I>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - rsnd_port0: port@0 { - reg = <0>; - rsnd_for_ak4613: endpoint { - remote-endpoint = <&ak4613_endpoint>; - - dai-format = "left_j"; - bitclock-master = <&rsnd_for_ak4613>; - frame-master = <&rsnd_for_ak4613>; - - playback = <&ssi0 &src0 &dvc0>; - capture = <&ssi1 &src1 &dvc1>; - }; - }; - rsnd_port1: port@1 { - reg = <1>; - rsnd_for_hdmi: endpoint { - remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_for_hdmi>; - frame-master = <&rsnd_for_hdmi>; - - playback = <&ssi2>; - }; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdhi2 { - /* used for on-board 8bit eMMC */ - pinctrl-0 = <&sdhi2_pins>; - pinctrl-1 = <&sdhi2_pins>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - bus-width = <8>; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - non-removable; - full-pwr-cycle-in-suspend; - status = "okay"; -}; - -&ssi1 { - shared-pin; -}; - -&usb2_phy1 { - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk-stb-ir-keymap.dtsi b/arch/arm64/boot/dts/rockchip/rk-stb-ir-keymap.dtsi deleted file mode 100644 index 0c0d9230a..000000000 --- a/arch/arm64/boot/dts/rockchip/rk-stb-ir-keymap.dtsi +++ /dev/null @@ -1,394 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. - */ -#include - -&pwm3 { - ir_key1 { - rockchip,usercode = <0xff00>; - rockchip,key_table = - <0xf9 KEY_HOME>, - <0xbf KEY_BACK>, - <0xfb KEY_MENU>, - <0xaa KEY_REPLY>, - <0xb9 KEY_UP>, - <0xe9 KEY_DOWN>, - <0xb8 KEY_LEFT>, - <0xea KEY_RIGHT>, - <0xeb KEY_VOLUMEDOWN>, - <0xef KEY_VOLUMEUP>, - <0xf7 KEY_MUTE>, - <0xe7 KEY_POWER>, - <0xfc KEY_POWER>, - <0xa9 KEY_VOLUMEDOWN>, - <0xa8 KEY_PLAYPAUSE>, - <0xe0 KEY_VOLUMEDOWN>, - <0xa5 KEY_VOLUMEDOWN>, - <0xab 183>, - <0xb7 388>, - <0xe8 388>, - <0xf8 184>, - <0xaf 185>, - <0xed KEY_VOLUMEDOWN>, - <0xee 186>, - <0xb3 KEY_VOLUMEDOWN>, - <0xf1 KEY_VOLUMEDOWN>, - <0xf2 KEY_VOLUMEDOWN>, - <0xf3 KEY_SEARCH>, - <0xb4 KEY_VOLUMEDOWN>, - <0xa4 KEY_SETUP>, - <0xbe KEY_SEARCH>; - }; - - /*for IPTV ltjc*/ - ir_key2 { - rockchip,usercode = <0xc43b>; - rockchip,key_table = - <0x7e KEY_REPLY>, - <0x7f KEY_BACK>, - <0x7a KEY_UP>, - <0x78 KEY_DOWN>, - <0x7b KEY_LEFT>, - <0x79 KEY_RIGHT>, - <0x66 KEY_VOLUMEUP>, - <0x65 KEY_VOLUMEDOWN>, - <0x69 KEY_POWER>, - <0x64 KEY_MUTE>, - <0x76 KEY_1>, - <0x75 KEY_2>, - <0x74 KEY_3>, - <0x73 KEY_4>, - <0x72 KEY_5>, - <0x71 KEY_6>, - <0x70 KEY_7>, - <0x6f KEY_8>, - <0x6e KEY_9>, - <0x77 KEY_0>, - <0x7c KEY_PAGEDOWN>, - <0x7d KEY_PAGEUP>, - <0x6a KEY_SETUP>, - <0x68 KEY_CHANNEL_UP>, - <0x67 KEY_CHANNEL_DN>, - <0x39 KEY_PORTAL>, - <0x29 KEY_HOME_PAGE>, - <0x33 KEY_CH_CUT_BACK>, - <0x34 KEY_LOCAL>, - <0x2d KEY_REVIEW>, - <0x2c KEY_ON_DEMAND>, - <0x2b KEY_INFO1>, - <0x2e KEY_DIRECT_SEEDING>, - <0x2d KEY_REVIEW>, - <0x2c KEY_ON_DEMAND>, - <0x2b KEY_INFO1>, - <0x63 KEY_SOUND1>, - <0x6c KEY_X1>, - <0x6d KEY_X2>, - <0x62 KEY_PLAYPAUSE>, - <0x6b KEY_EQUAL>, - <0x61 KEY_FASTFORWARD>, - <0x60 KEY_REWIND>, - <0x3b KEY_STOP>, - <0x35 KEY_BLUE>, - <0x36 KEY_YELLOW>, - <0x37 KEY_GREEN>, - <0x38 KEY_RED>; - }; - - ir_key3 { - rockchip,usercode = <0x1dcc>; - rockchip,key_table = - <0xee KEY_REPLY>, - <0xf0 KEY_BACK>, - <0xf8 KEY_UP>, - <0xbb KEY_DOWN>, - <0xef KEY_LEFT>, - <0xed KEY_RIGHT>, - <0xfc KEY_HOME>, - <0xf1 KEY_VOLUMEUP>, - <0xfd KEY_VOLUMEDOWN>, - <0xb7 KEY_SEARCH>, - <0xff KEY_POWER>, - <0xf3 KEY_MUTE>, - <0xbf KEY_MENU>, - <0xf9 0x191>, - <0xf5 0x192>, - <0xb3 388>, - <0xbe KEY_1>, - <0xba KEY_2>, - <0xb2 KEY_3>, - <0xbd KEY_4>, - <0xf9 KEY_5>, - <0xb1 KEY_6>, - <0xfc KEY_7>, - <0xf8 KEY_8>, - <0xb0 KEY_9>, - <0xb6 KEY_0>, - <0xb5 KEY_BACKSPACE>; - }; - - /* for IPTV */ - ir_key4 { - rockchip,usercode = <0x4db2>; - rockchip,key_table = - <0x31 KEY_REPLY>, - <0x3a KEY_BACK>, - <0x35 KEY_UP>, - <0x2d KEY_DOWN>, - <0x66 KEY_LEFT>, - <0x3e KEY_RIGHT>, - <0x7f KEY_VOLUMEUP>, - <0xfe KEY_VOLUMEDOWN>, - <0x23 KEY_POWER>, - <0x63 KEY_MUTE>, - <0x6d KEY_1>, - <0x6c KEY_2>, - <0x33 KEY_3>, - <0x71 KEY_4>, - <0x70 KEY_5>, - <0x37 KEY_6>, - <0x75 KEY_7>, - <0x74 KEY_8>, - <0x3b KEY_9>, - <0x78 KEY_0>, - <0x73 KEY_PAGEDOWN>, - <0x22 KEY_PAGEUP>, - <0x72 KEY_SETUP>, - <0x7a KEY_CHANNEL_UP>, - <0x79 KEY_CHANNEL_DN>, - <0x77 KEY_HOME_PAGE>, - <0x29 KEY_CH_CUT_BACK>, - <0x32 KEY_DIRECT_SEEDING>, - <0x6e KEY_REVIEW>, - <0x7c KEY_ON_DEMAND>, - <0x3c KEY_INFO1>, - <0x67 KEY_SOUND1>, - <0x25 KEY_X1>, - <0x2f KEY_X2>, - <0x7d KEY_LOCAL>, - <0x6a KEY_PLAYPAUSE>, - <0x0b KEY_EQUAL>; - }; - - /* for CMCC */ - ir_key5 { - rockchip,usercode = <0x1608>; - rockchip,key_table = - <0x4c KEY_REPLY>, - <0x4d KEY_BACK>, - <0x4b KEY_UP>, - <0x4a KEY_DOWN>, - <0x49 KEY_LEFT>, - <0x48 KEY_RIGHT>, - <0x4e KEY_HOME>, - <0x0b KEY_VOLUMEUP>, - <0x0c KEY_VOLUMEDOWN>, - <0x23 KEY_POWER>, - <0x45 KEY_MUTE>, - <0x44 KEY_MENU>, - <0x78 KEY_1>, - <0x77 KEY_2>, - <0x76 KEY_3>, - <0x75 KEY_4>, - <0x74 KEY_5>, - <0x73 KEY_6>, - <0x72 KEY_7>, - <0x71 KEY_8>, - <0x70 KEY_9>, - <0x79 KEY_0>, - <0x43 KEY_EQUAL>, - <0x72 KEY_X1>, - <0x5f KEY_SETUP>, - <0x25 KEY_DIRECT_SEEDING>, - <0x24 KEY_REVIEW>, - <0x21 KEY_ON_DEMAND>, - <0x20 KEY_INFO1>; - }; - - /* rk new remote */ - ir_key6 { - rockchip,usercode = <0xfe01>; - rockchip,key_table = - <0xec KEY_REPLY>, - <0xe6 KEY_BACK>, - <0xe9 KEY_UP>, - <0xe5 KEY_DOWN>, - <0xae KEY_LEFT>, - <0xaf KEY_RIGHT>, - <0xee KEY_HOME>, - <0xe7 KEY_VOLUMEUP>, - <0xef KEY_VOLUMEDOWN>, - <0xbf KEY_POWER>, - <0xbe KEY_MUTE>, - <0xb3 KEY_MENU>, - <0xff 388>, - <0xb1 KEY_1>, - <0xf2 KEY_2>, - <0xf3 KEY_3>, - <0xb5 KEY_4>, - <0xf6 KEY_5>, - <0xf7 KEY_6>, - <0xb9 KEY_7>, - <0xfa KEY_8>, - <0xfb KEY_9>, - <0xfe KEY_0>, - <0xbd KEY_EQUAL>, - <0xbc KEY_SETUP>, - <0xf0 KEY_LOCAL>, - <0x0d KEY_DIRECT_SEEDING>, - <0x0c KEY_REVIEW>, - <0x0b KEY_ON_DEMAND>, - <0x0a KEY_INFO1>, - <0x0e KEY_CH_CUT_BACK>; - }; - - /* for IPTV gd */ - ir_key7 { - rockchip,usercode = <0x4cb3>; - rockchip,key_table = - <0x31 KEY_REPLY>, - <0x3a KEY_BACK>, - <0x35 KEY_UP>, - <0x2d KEY_DOWN>, - <0x66 KEY_LEFT>, - <0x3e KEY_RIGHT>, - <0x7f KEY_VOLUMEUP>, - <0x7e KEY_VOLUMEDOWN>, - <0x23 KEY_POWER>, - <0x63 KEY_MUTE>, - <0x6d KEY_1>, - <0x6c KEY_2>, - <0x33 KEY_3>, - <0x71 KEY_4>, - <0x70 KEY_5>, - <0x37 KEY_6>, - <0x75 KEY_7>, - <0x74 KEY_8>, - <0x3b KEY_9>, - <0x78 KEY_0>, - <0x73 KEY_PAGEDOWN>, - <0x22 KEY_PAGEUP>, - <0x72 KEY_SETUP>, - <0x7a KEY_CHANNEL_UP>, - <0x79 KEY_CHANNEL_DN>, - <0x77 KEY_HOME_PAGE>, - <0x29 KEY_CH_CUT_BACK>, - <0x32 KEY_DIRECT_SEEDING>, - <0x6e KEY_REVIEW>, - <0x7c KEY_ON_DEMAND>, - <0x3c KEY_INFO1>, - <0x67 KEY_SOUND1>, - <0x25 KEY_X1>, - <0x2f KEY_X2>, - <0x7d KEY_LOCAL>, - <0x6a KEY_PLAYPAUSE>, - <0x0b KEY_EQUAL>; - }; - - /* for CMCC */ - ir_key8 { - rockchip,usercode = <0xdd22>; - rockchip,key_table = - <0x31 KEY_REPLY>, - <0x6a KEY_BACK>, - <0x35 KEY_UP>, - <0x2d KEY_DOWN>, - <0x66 KEY_LEFT>, - <0x3e KEY_RIGHT>, - <0x7f KEY_VOLUMEUP>, - <0x7e KEY_VOLUMEDOWN>, - <0x23 KEY_POWER>, - <0x63 KEY_MUTE>, - <0x6d KEY_1>, - <0x6c KEY_2>, - <0x33 KEY_3>, - <0x71 KEY_4>, - <0x70 KEY_5>, - <0x37 KEY_6>, - <0x75 KEY_7>, - <0x74 KEY_8>, - <0x3b KEY_9>, - <0x78 KEY_0>, - <0x73 KEY_PAGEDOWN>, - <0x22 KEY_PAGEUP>, - <0x72 KEY_SETUP>, - <0x7a KEY_CHANNEL_UP>, - <0x79 KEY_CHANNEL_DN>, - <0x77 KEY_HOME_PAGE>, - <0x2f KEY_CH_CUT_BACK>, - <0x32 KEY_DIRECT_SEEDING>, - <0x6e KEY_REVIEW>, - <0x7c KEY_ON_DEMAND>, - <0x3c KEY_INFO1>, - <0x3a KEY_HELP>, - <0x67 KEY_SOUND1>, - <0x25 KEY_X2>, - <0x7d KEY_MENU>, - <0x3f KEY_EQUAL>, - <0x29 388>, - <0x26 KEY_PLAYPAUSE>, - <0x76 401>, - <0x7b 400>, - <0x69 66>; - }; - - /* for BJLT IPTV */ - ir_key9 { - rockchip,usercode = <0x3bc4>; - rockchip,key_table = - <0x81 KEY_REPLY>, - <0x80 KEY_BACK>, - <0x85 KEY_UP>, - <0x87 KEY_DOWN>, - <0x84 KEY_LEFT>, - <0x86 KEY_RIGHT>, - <0x99 KEY_VOLUMEUP>, - <0x9a KEY_VOLUMEDOWN>, - <0x96 KEY_POWER>, - <0x9b KEY_MUTE>, - <0x89 KEY_1>, - <0x8a KEY_2>, - <0x8b KEY_3>, - <0x8c KEY_4>, - <0x8d KEY_5>, - <0x8e KEY_6>, - <0x8f KEY_7>, - <0x90 KEY_8>, - <0x91 KEY_9>, - <0x88 KEY_0>, - <0x83 KEY_PAGEDOWN>, - <0x82 KEY_PAGEUP>, - <0x95 KEY_SETUP>, - <0x97 KEY_CHANNEL_UP>, - <0x98 KEY_CHANNEL_DN>, - <0xc6 KEY_LOCAL>, - <0xd6 KEY_HOME_PAGE>, - <0xd7 KEY_TRACK>, - <0xcc KEY_CH_CUT_BACK>, - <0xc3 KEY_INTERX>, - <0xd1 KEY_DIRECT_SEEDING>, - <0xd2 KEY_REVIEW>, - <0xd3 KEY_ON_DEMAND>, - <0xd4 KEY_INFO1>, - <0xc7 KEY_DIRECT_SEEDING>, - <0xc8 KEY_REVIEW>, - <0xc9 KEY_ON_DEMAND>, - <0xca KEY_INFO1>, - <0xcd KEY_FAVORITE>, - <0xce KEY_CHANNEL_POS>, - <0xcf KEY_HELP>, - <0xd0 KEY_EVENT>, - <0x9c KEY_SOUND1>, - <0x93 KEY_X1>, - <0x92 KEY_X2>, - <0xc0 KEY_END>, - <0xc1 KEY_GO_BEGINNING>, - <0x9d KEY_PLAYPAUSE>, - <0xc4 KEY_STOP>, - <0x94 KEY_EQUAL>, - <0x9e KEY_YELLOW>, - <0x9f KEY_BLUE>, - <0xcb KEY_APPLICATION>, - <0xc5 KEY_POS>; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk1808-dram-default-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk1808-dram-default-timing.dtsi deleted file mode 100644 index 0fa79e2f0..000000000 --- a/arch/arm64/boot/dts/rockchip/rk1808-dram-default-timing.dtsi +++ /dev/null @@ -1,302 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd - */ - -#include -#include - -/ { - ddr_timing: ddr_timing { - compatible = "rockchip,ddr-timing"; - ddr2_speed_bin = ; - ddr3_speed_bin = ; - ddr4_speed_bin = ; - pd_idle = <0>; - sr_idle = <0>; - sr_mc_gate_idle = <0>; - srpd_lite_idle = <0>; - standby_idle = <0>; - - auto_pd_dis_freq = <1066>; - auto_sr_dis_freq = <800>; - ddr2_dll_dis_freq = <300>; - ddr3_dll_dis_freq = <300>; - ddr4_dll_dis_freq = <625>; - phy_dll_dis_freq = <400>; - - ddr2_odt_dis_freq = <100>; - phy_ddr2_odt_dis_freq = <100>; - ddr2_drv = ; - ddr2_odt = ; - phy_ddr2_ca_drv = ; - phy_ddr2_ck_drv = ; - phy_ddr2_dq_drv = ; - phy_ddr2_odt = ; - - ddr3_odt_dis_freq = <400>; - phy_ddr3_odt_dis_freq = <400>; - ddr3_drv = ; - ddr3_odt = ; - phy_ddr3_ca_drv = ; - phy_ddr3_ck_drv = ; - phy_ddr3_dq_drv = ; - phy_ddr3_odt = ; - - phy_lpddr2_odt_dis_freq = <666>; - lpddr2_drv = ; - phy_lpddr2_ca_drv = ; - phy_lpddr2_ck_drv = ; - phy_lpddr2_dq_drv = ; - phy_lpddr2_odt = ; - - lpddr3_odt_dis_freq = <400>; - phy_lpddr3_odt_dis_freq = <400>; - lpddr3_drv = ; - lpddr3_odt = ; - phy_lpddr3_ca_drv = ; - phy_lpddr3_ck_drv = ; - phy_lpddr3_dq_drv = ; - phy_lpddr3_odt = ; - - lpddr4_odt_dis_freq = <800>; - phy_lpddr4_odt_dis_freq = <800>; - lpddr4_drv = ; - lpddr4_dq_odt = ; - lpddr4_ca_odt = ; - phy_lpddr4_ca_drv = ; - phy_lpddr4_ck_cs_drv = ; - phy_lpddr4_dq_drv = ; - phy_lpddr4_odt = ; - - ddr4_odt_dis_freq = <666>; - phy_ddr4_odt_dis_freq = <666>; - ddr4_drv = ; - ddr4_odt = ; - phy_ddr4_ca_drv = ; - phy_ddr4_ck_drv = ; - phy_ddr4_dq_drv = ; - phy_ddr4_odt = ; - - /* - * CA de-skew, one step is 15ps, range 0-31 - * DDR3 CA define is different from others(DDR4/LPDDR2/LPDDR3). - */ - a0_ddr3a9_de-skew = <7>; - a1_ddr3a14_de-skew = <7>; - a2_ddr3a13_de-skew = <7>; - a3_ddr3a11_de-skew = <7>; - a4_ddr3a2_de-skew = <7>; - a5_ddr3a4_de-skew = <7>; - a6_ddr3a3_de-skew = <7>; - a7_ddr3a6_de-skew = <7>; - a8_ddr3a5_de-skew = <7>; - a9_ddr3a1_de-skew = <7>; - a10_ddr3a0_de-skew = <7>; - a11_ddr3a7_de-skew = <7>; - a12_ddr3casb_de-skew = <7>; - a13_ddr3a8_de-skew = <7>; - a14_ddr3odt0_de-skew = <7>; - a15_ddr3ba1_de-skew = <7>; - a16_ddr3rasb_de-skew = <7>; - a17_ddr3null_de-skew = <7>; - ba0_ddr3ba2_de-skew = <7>; - ba1_ddr3a12_de-skew = <7>; - bg0_ddr3ba0_de-skew = <7>; - bg1_ddr3web_de-skew = <7>; - cke_ddr3cke_de-skew = <7>; - ck_ddr3ck_de-skew = <7>; - ckb_ddr3ckb_de-skew = <7>; - csb0_ddr3a10_de-skew = <7>; - odt0_ddr3a15_de-skew = <7>; - resetn_ddr3resetn_de-skew = <7>; - actn_ddr3csb0_de-skew = <7>; - csb1_ddr3csb1_de-skew = <7>; - odt1_ddr3odt1_de-skew = <7>; - - /* DATA de-skew, one step is 15ps, range 0-31 */ - /* cs0_skew_a */ - cs0_dm0_rx_de-skew = <7>; - cs0_dm0_tx_de-skew = <7>; - cs0_dq0_rx_de-skew = <7>; - cs0_dq0_tx_de-skew = <7>; - cs0_dq1_rx_de-skew = <7>; - cs0_dq1_tx_de-skew = <7>; - cs0_dq2_rx_de-skew = <7>; - cs0_dq2_tx_de-skew = <7>; - cs0_dq3_rx_de-skew = <7>; - cs0_dq3_tx_de-skew = <7>; - cs0_dq4_rx_de-skew = <7>; - cs0_dq4_tx_de-skew = <7>; - cs0_dq5_rx_de-skew = <7>; - cs0_dq5_tx_de-skew = <7>; - cs0_dq6_rx_de-skew = <7>; - cs0_dq6_tx_de-skew = <7>; - cs0_dq7_rx_de-skew = <7>; - cs0_dq7_tx_de-skew = <7>; - cs0_dqs0p_rx_de-skew = <14>; - cs0_dqs0p_tx_de-skew = <9>; - cs0_dqs0n_tx_de-skew = <9>; - cs0_dm1_rx_de-skew = <7>; - cs0_dm1_tx_de-skew = <7>; - cs0_dq8_rx_de-skew = <7>; - cs0_dq8_tx_de-skew = <7>; - cs0_dq9_rx_de-skew = <7>; - cs0_dq9_tx_de-skew = <7>; - cs0_dq10_rx_de-skew = <7>; - cs0_dq10_tx_de-skew = <7>; - cs0_dq11_rx_de-skew = <7>; - cs0_dq11_tx_de-skew = <7>; - cs0_dq12_rx_de-skew = <7>; - cs0_dq12_tx_de-skew = <7>; - cs0_dq13_rx_de-skew = <7>; - cs0_dq13_tx_de-skew = <7>; - cs0_dq14_rx_de-skew = <7>; - cs0_dq14_tx_de-skew = <7>; - cs0_dq15_rx_de-skew = <7>; - cs0_dq15_tx_de-skew = <7>; - cs0_dqs1p_rx_de-skew = <14>; - cs0_dqs1p_tx_de-skew = <9>; - cs0_dqs1n_tx_de-skew = <9>; - cs0_dqs0n_rx_de-skew = <14>; - cs0_dqs1n_rx_de-skew = <14>; - - /* cs0_skew_b */ - cs0_dm2_rx_de-skew = <7>; - cs0_dm2_tx_de-skew = <7>; - cs0_dq16_rx_de-skew = <7>; - cs0_dq16_tx_de-skew = <7>; - cs0_dq17_rx_de-skew = <7>; - cs0_dq17_tx_de-skew = <7>; - cs0_dq18_rx_de-skew = <7>; - cs0_dq18_tx_de-skew = <7>; - cs0_dq19_rx_de-skew = <7>; - cs0_dq19_tx_de-skew = <7>; - cs0_dq20_rx_de-skew = <7>; - cs0_dq20_tx_de-skew = <7>; - cs0_dq21_rx_de-skew = <7>; - cs0_dq21_tx_de-skew = <7>; - cs0_dq22_rx_de-skew = <7>; - cs0_dq22_tx_de-skew = <7>; - cs0_dq23_rx_de-skew = <7>; - cs0_dq23_tx_de-skew = <7>; - cs0_dqs2p_rx_de-skew = <14>; - cs0_dqs2p_tx_de-skew = <9>; - cs0_dqs2n_tx_de-skew = <9>; - cs0_dm3_rx_de-skew = <7>; - cs0_dm3_tx_de-skew = <7>; - cs0_dq24_rx_de-skew = <7>; - cs0_dq24_tx_de-skew = <7>; - cs0_dq25_rx_de-skew = <7>; - cs0_dq25_tx_de-skew = <7>; - cs0_dq26_rx_de-skew = <7>; - cs0_dq26_tx_de-skew = <7>; - cs0_dq27_rx_de-skew = <7>; - cs0_dq27_tx_de-skew = <7>; - cs0_dq28_rx_de-skew = <7>; - cs0_dq28_tx_de-skew = <7>; - cs0_dq29_rx_de-skew = <7>; - cs0_dq29_tx_de-skew = <7>; - cs0_dq30_rx_de-skew = <7>; - cs0_dq30_tx_de-skew = <7>; - cs0_dq31_rx_de-skew = <7>; - cs0_dq31_tx_de-skew = <7>; - cs0_dqs3p_rx_de-skew = <14>; - cs0_dqs3p_tx_de-skew = <9>; - cs0_dqs3n_tx_de-skew = <9>; - cs0_dqs2n_rx_de-skew = <14>; - cs0_dqs3n_rx_de-skew = <14>; - - /* cs1_skew_a */ - cs1_dm0_rx_de-skew = <7>; - cs1_dm0_tx_de-skew = <7>; - cs1_dq0_rx_de-skew = <7>; - cs1_dq0_tx_de-skew = <7>; - cs1_dq1_rx_de-skew = <7>; - cs1_dq1_tx_de-skew = <7>; - cs1_dq2_rx_de-skew = <7>; - cs1_dq2_tx_de-skew = <7>; - cs1_dq3_rx_de-skew = <7>; - cs1_dq3_tx_de-skew = <7>; - cs1_dq4_rx_de-skew = <7>; - cs1_dq4_tx_de-skew = <7>; - cs1_dq5_rx_de-skew = <7>; - cs1_dq5_tx_de-skew = <7>; - cs1_dq6_rx_de-skew = <7>; - cs1_dq6_tx_de-skew = <7>; - cs1_dq7_rx_de-skew = <7>; - cs1_dq7_tx_de-skew = <7>; - cs1_dqs0p_rx_de-skew = <14>; - cs1_dqs0p_tx_de-skew = <9>; - cs1_dqs0n_tx_de-skew = <9>; - cs1_dm1_rx_de-skew = <7>; - cs1_dm1_tx_de-skew = <7>; - cs1_dq8_rx_de-skew = <7>; - cs1_dq8_tx_de-skew = <7>; - cs1_dq9_rx_de-skew = <7>; - cs1_dq9_tx_de-skew = <7>; - cs1_dq10_rx_de-skew = <7>; - cs1_dq10_tx_de-skew = <7>; - cs1_dq11_rx_de-skew = <7>; - cs1_dq11_tx_de-skew = <7>; - cs1_dq12_rx_de-skew = <7>; - cs1_dq12_tx_de-skew = <7>; - cs1_dq13_rx_de-skew = <7>; - cs1_dq13_tx_de-skew = <7>; - cs1_dq14_rx_de-skew = <7>; - cs1_dq14_tx_de-skew = <7>; - cs1_dq15_rx_de-skew = <7>; - cs1_dq15_tx_de-skew = <7>; - cs1_dqs1p_rx_de-skew = <14>; - cs1_dqs1p_tx_de-skew = <9>; - cs1_dqs1n_tx_de-skew = <9>; - cs1_dqs0n_rx_de-skew = <14>; - cs1_dqs1n_rx_de-skew = <14>; - - /* cs1_skew_b */ - cs1_dm2_rx_de-skew = <7>; - cs1_dm2_tx_de-skew = <7>; - cs1_dq16_rx_de-skew = <7>; - cs1_dq16_tx_de-skew = <7>; - cs1_dq17_rx_de-skew = <7>; - cs1_dq17_tx_de-skew = <7>; - cs1_dq18_rx_de-skew = <7>; - cs1_dq18_tx_de-skew = <7>; - cs1_dq19_rx_de-skew = <7>; - cs1_dq19_tx_de-skew = <7>; - cs1_dq20_rx_de-skew = <7>; - cs1_dq20_tx_de-skew = <7>; - cs1_dq21_rx_de-skew = <7>; - cs1_dq21_tx_de-skew = <7>; - cs1_dq22_rx_de-skew = <7>; - cs1_dq22_tx_de-skew = <7>; - cs1_dq23_rx_de-skew = <7>; - cs1_dq23_tx_de-skew = <7>; - cs1_dqs2p_rx_de-skew = <14>; - cs1_dqs2p_tx_de-skew = <9>; - cs1_dqs2n_tx_de-skew = <9>; - cs1_dm3_rx_de-skew = <7>; - cs1_dm3_tx_de-skew = <7>; - cs1_dq24_rx_de-skew = <7>; - cs1_dq24_tx_de-skew = <7>; - cs1_dq25_rx_de-skew = <7>; - cs1_dq25_tx_de-skew = <7>; - cs1_dq26_rx_de-skew = <7>; - cs1_dq26_tx_de-skew = <7>; - cs1_dq27_rx_de-skew = <7>; - cs1_dq27_tx_de-skew = <7>; - cs1_dq28_rx_de-skew = <7>; - cs1_dq28_tx_de-skew = <7>; - cs1_dq29_rx_de-skew = <7>; - cs1_dq29_tx_de-skew = <7>; - cs1_dq30_rx_de-skew = <7>; - cs1_dq30_tx_de-skew = <7>; - cs1_dq31_rx_de-skew = <7>; - cs1_dq31_tx_de-skew = <7>; - cs1_dqs3p_rx_de-skew = <14>; - cs1_dqs3p_tx_de-skew = <9>; - cs1_dqs3n_tx_de-skew = <9>; - cs1_dqs2n_rx_de-skew = <14>; - cs1_dqs3n_rx_de-skew = <14>; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk1808-evb-v10.dts b/arch/arm64/boot/dts/rockchip/rk1808-evb-v10.dts deleted file mode 100644 index a09824816..000000000 --- a/arch/arm64/boot/dts/rockchip/rk1808-evb-v10.dts +++ /dev/null @@ -1,305 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include -#include "rk1808-evb.dtsi" - -/ { - model = "Rockchip RK1808 EVB V10 Board"; - compatible = "rockchip,rk1808-evb-v10", "rockchip,rk1808"; - - chosen { - bootargs = "earlycon=uart8250,mmio32,0xff550000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait kpti=0 snd_aloop.index=7"; - }; - - vad-sound { - status = "okay"; - compatible = "rockchip,multicodecs-card"; - rockchip,card-name = "rockchip,rk1808-vad"; - rockchip,cpu = <&i2s0>; - rockchip,codec = <&vad>; - }; -}; - -&adc_key { - vol-down-key { - linux,code = ; - label = "volume down"; - press-threshold-microvolt = <300000>; - }; - - vol-up-key { - linux,code = ; - label = "volume up"; - press-threshold-microvolt = <18000>; - }; -}; - -&display_subsystem { - status = "okay"; -}; - -&dsi { - status = "okay"; - - panel@0 { - compatible = "sitronix,st7703", "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight>; - enable-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; - power-supply = <&vcc5v0_sys>; - prepare-delay-ms = <2>; - reset-delay-ms = <1>; - init-delay-ms = <20>; - enable-delay-ms = <120>; - disable-delay-ms = <50>; - unprepare-delay-ms = <20>; - - width-mm = <68>; - height-mm = <121>; - - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | - MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - - panel-init-sequence = [ - 05 fa 01 11 - 39 00 04 b9 f1 12 83 - 39 00 1c ba 33 81 05 f9 0e 0e 00 00 00 - 00 00 00 00 00 44 25 00 91 0a - 00 00 02 4f 01 00 00 37 - 15 00 02 b8 25 - 39 00 04 bf 02 11 00 - 39 00 0b b3 0c 10 0a 50 03 ff 00 00 00 - 00 - 39 00 0a c0 73 73 50 50 00 00 08 70 00 - 15 00 02 bc 46 - 15 00 02 cc 0b - 15 00 02 b4 80 - 39 00 04 b2 c8 12 30 - 39 00 0f e3 07 07 0b 0b 03 0b 00 00 00 - 00 ff 00 c0 10 - 39 00 0d c1 53 00 1e 1e 77 e1 cc dd 67 - 77 33 33 - 39 00 07 c6 00 00 ff ff 01 ff - 39 00 03 b5 09 09 - 39 00 03 b6 87 95 - 39 00 40 e9 c2 10 05 05 10 05 a0 12 31 - 23 3f 81 0a a0 37 18 00 80 01 - 00 00 00 00 80 01 00 00 00 48 - f8 86 42 08 88 88 80 88 88 88 - 58 f8 87 53 18 88 88 81 88 88 - 88 00 00 00 01 00 00 00 00 00 - 00 00 00 00 - 39 00 3e ea 00 1a 00 00 00 00 02 00 00 - 00 00 00 1f 88 81 35 78 88 88 - 85 88 88 88 0f 88 80 24 68 88 - 88 84 88 88 88 23 10 00 00 1c - 00 00 00 00 00 00 00 00 00 00 - 00 00 00 00 00 30 05 a0 00 00 - 00 00 - 39 00 23 e0 00 06 08 2a 31 3f 38 36 07 - 0c 0d 11 13 12 13 11 18 00 06 - 08 2a 31 3f 38 36 07 0c 0d 11 - 13 12 13 11 18 - 05 32 01 29 - ]; - - panel-exit-sequence = [ - 05 00 01 28 - 05 00 01 10 - ]; - - display-timings { - native-mode = <&timing0>; - - timing0: timing0 { - clock-frequency = <64000000>; - hactive = <720>; - vactive = <1280>; - hfront-porch = <40>; - hsync-len = <10>; - hback-porch = <40>; - vfront-porch = <22>; - vsync-len = <4>; - vback-porch = <11>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - panel_in_dsi: endpoint { - remote-endpoint = <&dsi_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi>; - }; - }; - }; -}; - -&i2c3 { - status = "okay"; - - clock-frequency = <100000>; - - ov5695: ov5695@36 { - compatible = "ovti,ov5695"; - reg = <0x36>; - clocks = <&cru SCLK_CIF_OUT>; - clock-names = "xvclk"; - avdd-supply = <&vcc2v8_dvp>; - dovdd-supply = <&vdd1v5_dvp>; - dvdd-supply = <&vcc1v8_dvp>; - pwdn-gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cif_clkout_m0>; - port { - ucam_out: endpoint { - remote-endpoint = <&mipi_in_ucam>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&i2s0 { - status = "okay"; - #sound-dai-cells = <0>; -}; - -&i2s1 { - status = "okay"; - #sound-dai-cells = <0>; -}; - -&isp_mmu { - status = "okay"; -}; - -&mipi_dphy { - status = "okay"; -}; - -&mipi_dphy_rx { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_ucam: endpoint@1 { - reg = <1>; - remote-endpoint = <&ucam_out>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - dphy_rx0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&isp0_mipi_in>; - }; - }; - }; -}; - -&rk_rga { - status = "okay"; -}; - -&rk809_sound { - status = "okay"; -}; - -&rkisp1 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_mipi_in: endpoint@0 { - reg = <0>; - remote-endpoint = <&dphy_rx0_out>; - }; - }; -}; - -&rng { - status = "okay"; -}; - -&rockchip_suspend { - status = "okay"; - rockchip,sleep-debug-en = <1>; -}; - -&route_dsi { - status = "disabled"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - pinctrl-names = "gpio", "otpout"; - pinctrl-0 = <&tsadc_otp_gpio>; - pinctrl-1 = <&tsadc_otp_out>; - status = "okay"; -}; - -&vad { - status = "okay"; - rockchip,audio-src = <&i2s0>; - rockchip,buffer-time-ms = <200>; - rockchip,det-channel = <0>; - rockchip,mode = <1>; - #sound-dai-cells = <0>; -}; - -&vop_lite { - status = "okay"; -}; - -&vopl_mmu { - status = "okay"; -}; - -&vpu_mmu { - status = "okay"; -}; - -&vpu_service { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk1808-evb-x4-second.dts b/arch/arm64/boot/dts/rockchip/rk1808-evb-x4-second.dts deleted file mode 100644 index 413d4f6fa..000000000 --- a/arch/arm64/boot/dts/rockchip/rk1808-evb-x4-second.dts +++ /dev/null @@ -1,272 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include -#include "rk1808-evb.dtsi" - -/ { - model = "Rockchip RK1808 EVB X4 Board"; - compatible = "rockchip,rk1808-evb-x4", "rockchip,rk1808"; - - chosen { - bootargs = "earlycon=uart8250,mmio32,0xff550000 console=ttyFIQ0 dump_initrd init=/init kpti=0"; - }; -}; - -&adc_key { - power-key { - linux,code = ; - label = "power key"; - press-threshold-microvolt = <18000>; - }; -}; - -/delete-node/ &backlight; -/delete-node/ &vcc1v8_dvp; -/delete-node/ &vdd1v5_dvp; -/delete-node/ &vcc2v8_dvp; - -&cif { - status = "okay"; - - port { - cif_in: endpoint@0 { - remote-endpoint = <&dphy_rx_out>; - data-lanes = <1 2 3 4>; - }; - }; -}; - -&cif_mmu { - status = "okay"; -}; - -&cru { - assigned-clocks = - <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru PLL_PPLL>, <&cru ARMCLK>, - <&cru MSCLK_PERI>, <&cru LSCLK_PERI>, - <&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>, - <&cru LSCLK_BUS_PRE>, <&cru DCLK_VOPRAW>; - assigned-clock-rates = - <1188000000>, <1000000000>, - <100000000>, <816000000>, - <200000000>, <100000000>, - <300000000>, <200000000>, - <100000000>, <80000000>; -}; - -&csi_tx { - status = "okay"; - csi-tx-bypass-mode = <1>; - - panel@0 { - compatible = "simple-panel-dsi"; - reg = <0>; - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | - MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET | - MIPI_DSI_CLOCK_NON_CONTINUOUS)>; - dsi,format = ; - dsi,lanes = <4>; - - display-timings { - native-mode = <&timing_1280x3_720>; - - timing_1280x3_720: timing-1280x3-720 { - clock-frequency = <80000000>; - hactive = <3840>; - vactive = <720>; - hfront-porch = <1200>; - hsync-len = <500>; - hback-porch = <30>; - vfront-porch = <40>; - vsync-len = <20>; - vback-porch = <40>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - timing_4k: timing-4k { - clock-frequency = <250000000>; - hactive = <3840>; - vactive = <2160>; - hfront-porch = <1500>; - hsync-len = <500>; - hback-porch = <30>; - vfront-porch = <40>; - vsync-len = <20>; - vback-porch = <40>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - timing_4096: timing-4096 { - clock-frequency = <100000000>; - hactive = <4096>; - vactive = <2048>; - hfront-porch = <1500>; - hsync-len = <500>; - hback-porch = <30>; - vfront-porch = <40>; - vsync-len = <20>; - vback-porch = <40>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - timing_1920x3_1080: timing-1920x3-1080 { - clock-frequency = <250000000>; - hactive = <5760>; - vactive = <1080>; - hfront-porch = <1500>; - hsync-len = <70>; - hback-porch = <30>; - vfront-porch = <40>; - vsync-len = <20>; - vback-porch = <40>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&display_subsystem { - status = "okay"; -}; - -&emmc { - status = "disabled"; -}; - -&gmac { - status = "disabled"; -}; - -&i2c0 { - status = "okay"; - - vcamera@30 { - compatible = "rockchip,virtual-camera"; - reg = <0x30>; - width = <3840>; - height = <720>; - bus-format = ; - - port { - vcamera_out: endpoint { - remote-endpoint = <&dphy_rx_in>; - link-frequencies = /bits/ 64 <320000000>; - }; - }; - }; -}; - -&i2c1 { - status = "disabled"; -}; - -&i2c4 { - status = "disabled"; -}; - -&mipi_dphy { - status = "okay"; -}; - -&mipi_dphy_rx { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dphy_rx_in: endpoint@1 { - reg = <1>; - remote-endpoint = <&vcamera_out>; - data-lanes = <1 2 3 4>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - dphy_rx_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_in>; - }; - }; - }; -}; - -&rk809_codec { - status = "disabled"; -}; - -&rk_rga { - status = "okay"; -}; - -&route_csi { - status = "disabled"; -}; - -&sdmmc { - status = "disabled"; -}; - -&sdio { - status = "disabled"; -}; - -&sfc { - status = "okay"; -}; - -&uart4 { - status = "disabled"; -}; - -&wireless_bluetooth { - status = "disabled"; -}; - -&wireless_wlan { - status = "disabled"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - pinctrl-names = "init", "default"; - pinctrl-0 = <&tsadc_otp_gpio>; - pinctrl-1 = <&tsadc_otp_out>; - status = "okay"; -}; - -&vop_raw { - status = "okay"; -}; - -&vopr_mmu { - status = "okay"; -}; - -&vpu_mmu { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk1808-evb-x4.dts b/arch/arm64/boot/dts/rockchip/rk1808-evb-x4.dts deleted file mode 100644 index 17993d1ff..000000000 --- a/arch/arm64/boot/dts/rockchip/rk1808-evb-x4.dts +++ /dev/null @@ -1,271 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd - */ - -/dts-v1/; -#include -#include "rk1808-evb.dtsi" - -/ { - model = "Rockchip RK1808 EVB X4 Board"; - compatible = "rockchip,rk1808-evb-x4", "rockchip,rk1808"; - - chosen { - bootargs = "earlycon=uart8250,mmio32,0xff550000 console=ttyFIQ0 dump_initrd init=/init kpti=0"; - }; -}; - -&adc_key { - power-key { - linux,code = ; - label = "power key"; - press-threshold-microvolt = <18000>; - }; -}; - -/delete-node/ &backlight; -/delete-node/ &vcc1v8_dvp; -/delete-node/ &vdd1v5_dvp; -/delete-node/ &vcc2v8_dvp; - -&cif { - status = "okay"; - - port { - cif_in: endpoint@0 { - remote-endpoint = <&dphy_rx_out>; - data-lanes = <1 2 3 4>; - }; - }; -}; - -&cif_mmu { - status = "okay"; -}; - -&cru { - assigned-clocks = - <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru PLL_PPLL>, <&cru ARMCLK>, - <&cru MSCLK_PERI>, <&cru LSCLK_PERI>, - <&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>, - <&cru LSCLK_BUS_PRE>, <&cru DCLK_VOPRAW>; - assigned-clock-rates = - <1188000000>, <1000000000>, - <100000000>, <816000000>, - <200000000>, <100000000>, - <300000000>, <200000000>, - <100000000>, <80000000>; -}; - -&csi_tx { - status = "okay"; - - panel@0 { - compatible = "simple-panel-dsi"; - reg = <0>; - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | - MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET | - MIPI_DSI_CLOCK_NON_CONTINUOUS)>; - dsi,format = ; - dsi,lanes = <4>; - - display-timings { - native-mode = <&timing_1280x3_720>; - - timing_1280x3_720: timing-1280x3-720 { - clock-frequency = <80000000>; - hactive = <3840>; - vactive = <720>; - hfront-porch = <1200>; - hsync-len = <500>; - hback-porch = <30>; - vfront-porch = <40>; - vsync-len = <20>; - vback-porch = <40>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - timing_4k: timing-4k { - clock-frequency = <250000000>; - hactive = <3840>; - vactive = <2160>; - hfront-porch = <1500>; - hsync-len = <500>; - hback-porch = <30>; - vfront-porch = <40>; - vsync-len = <20>; - vback-porch = <40>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - timing_4096: timing-4096 { - clock-frequency = <190000000>; - hactive = <4096>; - vactive = <2048>; - hfront-porch = <1500>; - hsync-len = <500>; - hback-porch = <30>; - vfront-porch = <40>; - vsync-len = <20>; - vback-porch = <40>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - timing_1920x3_1080: timing-1920x3-1080 { - clock-frequency = <250000000>; - hactive = <5760>; - vactive = <1080>; - hfront-porch = <1500>; - hsync-len = <70>; - hback-porch = <30>; - vfront-porch = <40>; - vsync-len = <20>; - vback-porch = <40>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - }; -}; - -&display_subsystem { - status = "okay"; -}; - -&emmc { - status = "disabled"; -}; - -&gmac { - status = "disabled"; -}; - -&i2c0 { - status = "okay"; - - vcamera@30 { - compatible = "rockchip,virtual-camera"; - reg = <0x30>; - width = <1280>; - height = <720>; - bus-format = ; - - port { - vcamera_out: endpoint { - remote-endpoint = <&dphy_rx_in>; - link-frequencies = /bits/ 64 <320000000>; - }; - }; - }; -}; - -&i2c1 { - status = "disabled"; -}; - -&i2c4 { - status = "disabled"; -}; - -&mipi_dphy { - status = "okay"; -}; - -&mipi_dphy_rx { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dphy_rx_in: endpoint@1 { - reg = <1>; - remote-endpoint = <&vcamera_out>; - data-lanes = <1 2 3 4>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - dphy_rx_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_in>; - }; - }; - }; -}; - -&rk809_codec { - status = "disabled"; -}; - -&rk_rga { - status = "okay"; -}; - -&route_csi { - status = "disabled"; -}; - -&sdmmc { - status = "disabled"; -}; - -&sdio { - status = "disabled"; -}; - -&sfc { - status = "okay"; -}; - -&uart4 { - status = "disabled"; -}; - -&wireless_bluetooth { - status = "disabled"; -}; - -&wireless_wlan { - status = "disabled"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - pinctrl-names = "init", "default"; - pinctrl-0 = <&tsadc_otp_gpio>; - pinctrl-1 = <&tsadc_otp_out>; - status = "okay"; -}; - -&vop_raw { - status = "okay"; -}; - -&vopr_mmu { - status = "okay"; -}; - -&vpu_mmu { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi deleted file mode 100644 index bb57ae176..000000000 --- a/arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi +++ /dev/null @@ -1,717 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. - -#include -#include -#include -#include -#include -#include "rk1808.dtsi" - -/ { - model = "Rockchip RK1808 EVB"; - compatible = "rockchip,rk1808-evb", "rockchip,rk1808"; - - adc_key: adc-keys { - compatible = "adc-keys"; - autorepeat; - io-channels = <&saradc 2>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 25000 0>; - brightness-levels = < - 0 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 - 24 25 26 27 28 29 30 31 - 32 33 34 35 36 37 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255>; - default-brightness-level = <200>; - }; - - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_lite_out>, <&vop_raw_out>; - logo-memory-region = <&drm_logo>; - status = "disabled"; - - route { - route_csi: route-csi { - status = "disabled"; - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <&vop_raw_out_csi>; - }; - - route_dsi: route-dsi { - status = "disabled"; - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <&vop_lite_out_dsi>; - }; - - route_rgb: route-rgb { - status = "disabled"; - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <&vop_lite_out_rgb>; - }; - }; - }; - - fiq-debugger { - compatible = "rockchip,fiq-debugger"; - rockchip,serial-id = <2>; - rockchip,wake-irq = <0>; - /* If enable uart uses irq instead of fiq */ - rockchip,irq-mode-enable = <0>; - rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ - interrupts = ; - status = "okay"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - drm_logo: drm-logo@00000000 { - compatible = "rockchip,drm-logo"; - reg = <0x0 0x0 0x0 0x0>; - }; - - ramoops: ramoops@110000 { - compatible = "ramoops"; - reg = <0x0 0x110000 0x0 0xf0000>; - record-size = <0x30000>; - console-size = <0xc0000>; - ftrace-size = <0x00000>; - pmsg-size = <0x00000>; - }; - }; - - rk809_sound: rk809-sound { - status = "disabled"; - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip,rk809-codec"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Mic Jack", "MICBIAS1", - "IN1P", "Mic Jack", - "Headphone Jack", "HPOL", - "Headphone Jack", "HPOR"; - simple-audio-card,cpu { - sound-dai = <&i2s1>; - }; - simple-audio-card,codec { - sound-dai = <&rk809_codec>; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>; - }; - - vcc_otg_vbus: otg-vbus-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-name = "vcc_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_phy"; - regulator-always-on; - regulator-boot-on; - }; - - wireless_bluetooth: wireless-bluetooth { - compatible = "bluetooth-platdata"; - uart_rts_gpios = <&gpio4 RK_PB7 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "rts_gpio"; - pinctrl-0 = <&uart4_rts>; - pinctrl-1 = <&uart4_rts_gpio>; - BT,power_gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; - BT,wake_host_irq = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - rockchip,grf = <&grf>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_wake_host>; - wifi_chip_type = "ap6212"; - WIFI,host_wake_irq = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&combphy { - status = "okay"; -}; - -&emmc { - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <200000000>; - mmc-hs200-1_8v; - no-sdio; - no-sd; - non-removable; - num-slots = <1>; - status = "okay"; -}; - -&gmac { - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - clock_in_out = "input"; - snps,reset-gpio = <&gpio0 10 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - assigned-clocks = <&cru SCLK_GMAC>; - assigned-clock-parents = <&gmac_clkin>; - tx_delay = <0x50>; - rx_delay = <0x3a>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - vdd_npu: tcs4525@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "fan53555-reg"; - pinctrl-0 = <&vsel_gpio>; - vsel-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; - regulator-name = "vdd_npu"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - fcs,suspend-voltage-selector = <0>; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default", "pmic-sleep", - "pmic-power-off", "pmic-reset"; - pinctrl-0 = <&pmic_int>; - pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; - pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; - pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_null>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - //fb-inner-reg-idxs = <2>; - /* 1: rst regs (default in codes), 0: rst the pmic */ - pmic-reset-func = <0>; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc_buck5>; - vcc6-supply = <&vcc_buck5>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc_3v3>; - vcc9-supply = <&vcc5v0_sys>; - - pwrkey { - status = "okay"; - }; - - rtc { - status = "okay"; - }; - - pinctrl_rk8xx: pinctrl_rk8xx { - gpio-controller; - #gpio-cells = <2>; - - rk817_slppin_null: rk817_slppin_null { - pins = "gpio_slp"; - function = "pin_fun0"; - }; - - rk817_slppin_slp: rk817_slppin_slp { - pins = "gpio_slp"; - function = "pin_fun1"; - }; - - rk817_slppin_pwrdn: rk817_slppin_pwrdn { - pins = "gpio_slp"; - function = "pin_fun2"; - }; - - rk817_slppin_rst: rk817_slppin_rst { - pins = "gpio_slp"; - function = "pin_fun3"; - }; - }; - - regulators { - vdd_log: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-name = "vdd_log"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <800000>; - }; - }; - - vdd_cpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-name = "vdd_cpu"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - regulator-initial-mode = <0x2>; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_3v3: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-initial-mode = <0x2>; - regulator-name = "vcc_3v3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdda_0v8: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-name = "vdda_0v8"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <800000>; - }; - }; - - vcc_1v8: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-name = "vcc_1v8"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v8: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - - regulator-name = "vdd_0v8"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <800000>; - }; - }; - - vcca_1v8: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-name = "vcca_1v8"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - - }; - }; - - vcc1v8_dvp: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-name = "vcc1v8_dvp"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd1v5_dvp: LDO_REG6 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1500000>; - - regulator-name = "vdd1v5_dvp"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1500000>; - - }; - }; - - vcc2v8_dvp: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-name = "vcc2v8_dvp"; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <2800000>; - }; - }; - - vccio_sd: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc3v3_sd: LDO_REG9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-name = "vcc3v3_sd"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_buck5: DCDC_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - regulator-name = "vcc_buck5"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2200000>; - }; - }; - - vcc5v0_host: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc5v0_host"; - }; - - vccio_3v3: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vccio_3v3"; - }; - - }; - - rk809_codec: codec { - #sound-dai-cells = <0>; - compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; - clocks = <&cru SCLK_I2S1_2CH_OUT>; - clock-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_2ch_mclk>; - hp-volume = <20>; - spk-volume = <3>; - status = "okay"; - }; - }; -}; - -&i2c1 { - status = "okay"; - - gt1x: gt1x@14 { - compatible = "goodix,gt1x"; - reg = <0x14>; - goodix,rst-gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; - goodix,irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c4 { - status = "okay"; - - sensor@d { - status = "okay"; - compatible = "ak8963"; - reg = <0x0d>; - type = ; - irq_enable = <0>; - poll_delay_ms = <30>; - layout = <1>; - reprobe_en = <1>; - }; - - sensor@4c { - status = "okay"; - compatible = "gs_mma7660"; - reg = <0x4c>; - type = ; - irq-gpio = <&gpio0 RK_PC6 IRQ_TYPE_LEVEL_LOW>; - irq_enable = <0>; - poll_delay_ms = <30>; - layout = <2>; - reprobe_en = <1>; - }; -}; - -&npu { - npu-supply = <&vdd_npu>; - status = "okay"; -}; - -&pcie0 { - reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - /* Disable usbdrd_dwc3 and usbdrd3 if using pcie0 */ - status = "disabled"; -}; - -&power { - npu-supply = <&vdd_npu>; -}; - -&pwm1 { - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc_1v8>; -}; - -&sdio { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - no-sd; - no-mmc; - keep-power-in-suspend; - non-removable; - mmc-pwrseq = <&sdio_pwrseq>; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - no-sdio; - no-mmc; - card-detect-delay = <300>; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_xfer &uart4_cts>; - status = "okay"; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -&u2phy_otg { - status = "okay"; - vbus-supply = <&vcc_otg_vbus>; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usbdrd3 { - status = "okay"; - extcon = <&u2phy>; -}; - -&usbdrd_dwc3 { - status = "okay"; -}; - -&pinctrl { - pmic { - pmic_int: pmic_int { - rockchip,pins = - <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - soc_slppin_gpio: soc_slppin_gpio { - rockchip,pins = - <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; - }; - - soc_slppin_slp: soc_slppin_slp { - rockchip,pins = - <0 RK_PA4 1 &pcfg_pull_none>; - }; - - vsel_gpio: vsel-gpio { - rockchip,pins = - <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = - <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb2 { - otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-bluetooth { - uart4_rts_gpio: uart4-rts-gpio { - rockchip,pins = <4 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-wlan { - wifi_wake_host: wifi-wake-host { - rockchip,pins = - <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk1808-fpga.dts b/arch/arm64/boot/dts/rockchip/rk1808-fpga.dts deleted file mode 100644 index d021918ca..000000000 --- a/arch/arm64/boot/dts/rockchip/rk1808-fpga.dts +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd - -/dts-v1/; -#include "rk1808.dtsi" - -/ { - model = "Rockchip rk1808 fpga board"; - compatible = "rockchip,fpga", "rockchip,rk1808"; - - chosen { - bootargs = "earlycon=uart8250,mmio32,0xff550000 console=ttyFIQ0 root=/dev/mmcblk1p8 rootfstype=ext4 rootwait clk_ignore_unused"; - }; - - memory@200000 { - device_type = "memory"; - reg = <0x0 0x00200000 0x0 0x0FE00000>; - }; - - fiq_debugger: fiq-debugger { - compatible = "rockchip,fiq-debugger"; - rockchip,serial-id = <2>; - rockchip,wake-irq = <0>; - rockchip,irq-mode-enable = <1>; - rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ - interrupts = ; - status = "okay"; - }; -}; - -&emmc { - max-frequency = <400000>; - clocks = <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>; - clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; - mmc-hs200-1_8v; - no-sdio; - no-sd; - num-slots = <1>; - status = "okay"; -}; - -&npu { - status = "okay"; -}; - -&sdmmc { - max-frequency = <400000>; - clocks = <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>; - clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; - no-sdio; - no-mmc; - status = "okay"; -}; - -/* If fiq_debugger set okay, need to define uart2 and to be disabled */ -&uart2 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk1808.dtsi b/arch/arm64/boot/dts/rockchip/rk1808.dtsi deleted file mode 100644 index d510d884e..000000000 --- a/arch/arm64/boot/dts/rockchip/rk1808.dtsi +++ /dev/null @@ -1,3039 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rk1808-dram-default-timing.dtsi" - -/ { - compatible = "rockchip,rk1808"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - serial6 = &uart6; - serial7 = &uart7; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a35", "arm,armv8"; - reg = <0x0 0x0>; - enable-method = "psci"; - clocks = <&cru ARMCLK>; - operating-points-v2 = <&cpu0_opp_table>; - dynamic-power-coefficient = <74>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP>; - power-model { - compatible = "simple-power-model"; - ref-leakage = <31>; - static-coefficient = <100000>; - ts = <597400 241050 (-2450) 70>; - thermal-zone = "soc-thermal"; - }; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a35", "arm,armv8"; - reg = <0x0 0x1>; - enable-method = "psci"; - clocks = <&cru ARMCLK>; - operating-points-v2 = <&cpu0_opp_table>; - dynamic-power-coefficient = <74>; - cpu-idle-states = <&CPU_SLEEP>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <120>; - exit-latency-us = <250>; - min-residency-us = <900>; - }; - - CLUSTER_SLEEP: cluster-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <400>; - exit-latency-us = <500>; - min-residency-us = <2000>; - }; - }; - }; - - cpu0_opp_table: cpu0-opp-table { - compatible = "operating-points-v2"; - opp-shared; - - rockchip,temp-hysteresis = <5000>; - rockchip,low-temp = <0>; - rockchip,low-temp-min-volt = <800000>; - rockchip,low-temp-adjust-volt = < - /* MHz MHz uV */ - 0 1608 50000 - >; - - rockchip,max-volt = <950000>; - rockchip,evb-irdrop = <25000>; - nvmem-cells = <&cpu_leakage>; - nvmem-cell-names = "leakage"; - - rockchip,pvtm-voltage-sel = < - 0 69000 0 - 69001 74000 1 - 74001 99999 2 - >; - rockchip,pvtm-freq = <408000>; - rockchip,pvtm-volt = <800000>; - rockchip,pvtm-ch = <0 0>; - rockchip,pvtm-sample-time = <1000>; - rockchip,pvtm-number = <10>; - rockchip,pvtm-error = <1000>; - rockchip,pvtm-ref-temp = <25>; - rockchip,pvtm-temp-prop = <(-20) (-26)>; - rockchip,thermal-zone = "soc-thermal"; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <750000 750000 950000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <750000 750000 950000>; - clock-latency-ns = <40000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <750000 750000 950000>; - clock-latency-ns = <40000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <750000 750000 950000>; - clock-latency-ns = <40000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <800000 800000 950000>; - opp-microvolt-L0 = <800000 800000 950000>; - opp-microvolt-L1 = <750000 750000 950000>; - opp-microvolt-L2 = <750000 750000 950000>; - clock-latency-ns = <40000>; - }; - opp-1296000000 { - opp-hz = /bits/ 64 <1296000000>; - opp-microvolt = <825000 825000 950000>; - opp-microvolt-L0 = <825000 825000 950000>; - opp-microvolt-L1 = <775000 775000 950000>; - opp-microvolt-L2 = <750000 750000 950000>; - clock-latency-ns = <40000>; - }; - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <850000 850000 950000>; - opp-microvolt-L0 = <850000 850000 950000>; - opp-microvolt-L1 = <800000 800000 950000>; - opp-microvolt-L2 = <775000 775000 950000>; - clock-latency-ns = <40000>; - }; - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <875000 875000 950000>; - opp-microvolt-L0 = <875000 875000 950000>; - opp-microvolt-L1 = <825000 825000 950000>; - opp-microvolt-L2 = <800000 800000 950000>; - clock-latency-ns = <40000>; - }; - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <900000 900000 950000>; - opp-microvolt-L0 = <900000 900000 950000>; - opp-microvolt-L1 = <850000 850000 950000>; - opp-microvolt-L2 = <825000 825000 950000>; - clock-latency-ns = <40000>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - cpuinfo { - compatible = "rockchip,cpuinfo"; - nvmem-cells = <&efuse_id>, <&efuse_cpu_version>; - nvmem-cell-names = "id", "cpu-version"; - }; - - bus_soc: bus-soc { - compatible = "rockchip,rk1808-bus"; - rockchip,busfreq-policy = "smc"; - soc-bus0 { - bus-id = <0>; - cfg-val = <0x1e0>; - enable-msk = <0x407f>; - status = "okay"; - }; - soc-bus1 { - bus-id = <1>; - cfg-val = <0x12c0>; - enable-msk = <0x41ff>; - status = "okay"; - }; - soc-bus2 { - bus-id = <2>; - cfg-val = <0x12c0>; - enable-msk = <0x4005>; - status = "okay"; - }; - soc-bus3 { - bus-id = <3>; - cfg-val = <0x12c0>; - enable-msk = <0x4001>; - status = "okay"; - }; - soc-bus4 { - bus-id = <4>; - cfg-val = <0x12c0>; - enable-msk = <0x4001>; - status = "disabled"; - }; - }; - - gmac_clkin: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; - }; - - mipi_csi2: mipi-csi2 { - compatible = "rockchip,rk1808-mipi-csi2"; - rockchip,hw = <&mipi_csi2_hw>; - status = "disabled"; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - rockchip_suspend: rockchip-suspend { - compatible = "rockchip,pm-rk1808"; - status = "disabled"; - rockchip,sleep-debug-en = <0>; - rockchip,sleep-mode-config = < - (0 - | RKPM_SLP_ARMOFF - | RKPM_SLP_PMU_PMUALIVE_32K - | RKPM_SLP_PMU_DIS_OSC - | RKPM_SLP_PMIC_LP - | RKPM_SLP_32K_EXT - ) - >; - rockchip,wakeup-config = < - (0 - | RKPM_GPIO_WKUP_EN - ) - >; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - arm,no-tick-in-suspend; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - xin32k: xin32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - #clock-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&clkin_32k>; - }; - - pcie0: pcie@fc400000 { - compatible = "rockchip,rk1808-pcie", "snps,dw-pcie"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0x1f>; - clocks = <&cru HSCLK_PCIE>, <&cru LSCLK_PCIE>, - <&cru ACLK_PCIE>, <&cru PCLK_PCIE>, - <&cru SCLK_PCIE_AUX>; - clock-names = "hsclk", "lsclk", - "aclk", "pclk", - "sclk-aux"; - interrupts = , - , - , - ; - interrupt-names = "sys", "legacy", "msg", "err"; - linux,pci-domain = <0>; - num-ib-windows = <6>; - num-ob-windows = <2>; - msi-map = <0x0 &its 0x0 0x1000>; - num-lanes = <2>; - phys = <&combphy PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_clkreq>; - power-domains = <&power RK1808_PD_PCIE>; - ranges = <0x00000800 0x0 0xf8000000 0x0 0xf8000000 0x0 0x800000 - 0x83000000 0x0 0xf8800000 0x0 0xf8800000 0x0 0x3700000 - 0x81000000 0x0 0xfbf00000 0x0 0xfbf00000 0x0 0x100000>; - reg = <0x0 0xfc000000 0x0 0x400000>, - <0x0 0xfc400000 0x0 0x10000>; - reg-names = "pcie-dbi", "pcie-apb"; - resets = <&cru SRST_PCIE_NIU_H>, <&cru SRST_PCIE_NIU_L>, - <&cru SRST_PCIEGRF_P>, <&cru SRST_PCIECTL_P>, - <&cru SRST_PCIECTL_POWERUP>, <&cru SRST_PCIECTL_MST_A>, - <&cru SRST_PCIECTL_SLV_A>, <&cru SRST_PCIECTL_DBI_A>, - <&cru SRST_PCIECTL_BUTTON>, <&cru SRST_PCIECTL_PE>, - <&cru SRST_PCIECTL_CORE>, <&cru SRST_PCIECTL_NSTICKY>, - <&cru SRST_PCIECTL_STICKY>, <&cru SRST_PCIECTL_PWR>, - <&cru SRST_PCIE_NIU_A>, <&cru SRST_PCIE_NIU_P>; - reset-names = "niu-h", "niu-l", "grf-p", "ctl-p", - "ctl-powerup", "ctl-mst-a", "ctl-slv-a", - "ctl-dbi-a", "ctl-button", "ctl-pe", - "ctl-core", "ctl-nsticky", "ctl-sticky", - "ctl-pwr", "ctl-niu-a", "ctl-niu-p"; - rockchip,usbpciegrf = <&usb_pcie_grf>; - rockchip,pmugrf = <&pmugrf>; - status = "disabled"; - }; - - usbdrd3: usb { - compatible = "rockchip,rk1808-dwc3", "rockchip,rk3399-dwc3"; - clocks = <&cru SCLK_USB3_OTG0_REF>, <&cru ACLK_USB3OTG>, - <&cru SCLK_USB3_OTG0_SUSPEND>; - clock-names = "ref_clk", "bus_clk", - "suspend_clk"; - assigned-clocks = <&cru SCLK_USB3_OTG0_SUSPEND>; - assigned-clock-rates = <24000000>; - power-domains = <&power RK1808_PD_PCIE>; - resets = <&cru SRST_USB3_OTG_A>; - reset-names = "usb3-otg"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - usbdrd_dwc3: dwc3@fd000000 { - compatible = "snps,dwc3"; - reg = <0x0 0xfd000000 0x0 0x200000>; - interrupts = ; - dr_mode = "otg"; - phys = <&u2phy_otg>, <&combphy PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - snps,dis_enblslpm_quirk; - snps,dis-u1u2-quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - snps,dis-del-phy-power-chg-quirk; - snps,tx-ipgap-linecheck-dis-quirk; - snps,xhci-trb-ent-quirk; - snps,parkmode-disable-ss-quirk; - status = "disabled"; - }; - }; - - grf: syscon@fe000000 { - compatible = "rockchip,rk1808-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfe000000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - npu_pvtm: npu-pvtm { - compatible = "rockchip,rk1808-npu-pvtm"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - pvtm@2 { - reg = <2>; - clocks = <&cru SCLK_PVTM_NPU>; - clock-names = "clk"; - }; - }; - - rgb: rgb { - compatible = "rockchip,rk1808-rgb"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - rgb_in_vop_lite: endpoint { - remote-endpoint = <&vop_lite_out_rgb>; - }; - }; - }; - }; - }; - - usb2phy_grf: syscon@fe010000 { - compatible = "rockchip,rk1808-usb2phy-grf", "syscon", - "simple-mfd"; - reg = <0x0 0xfe010000 0x0 0x8000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy: usb2-phy@100 { - compatible = "rockchip,rk1808-usb2phy"; - reg = <0x100 0x10>; - clocks = <&cru SCLK_USBPHY_REF>; - clock-names = "phyclk"; - #clock-cells = <0>; - assigned-clocks = <&cru USB480M>; - assigned-clock-parents = <&u2phy>; - clock-output-names = "usb480m_phy"; - status = "disabled"; - - u2phy_host: host-port { - #phy-cells = <0>; - interrupts = ; - interrupt-names = "linestate"; - status = "disabled"; - }; - - u2phy_otg: otg-port { - #phy-cells = <0>; - interrupts = , - , - ; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - status = "disabled"; - }; - }; - }; - - combphy_grf: syscon@fe018000 { - compatible = "rockchip,usb3phy-grf", "syscon"; - reg = <0x0 0xfe018000 0x0 0x8000>; - }; - - pmugrf: syscon@fe020000 { - compatible = "rockchip,rk1808-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xfe020000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - pmu_pvtm: pmu-pvtm { - compatible = "rockchip,rk1808-pmu-pvtm"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - pvtm@1 { - reg = <1>; - clocks = <&cru SCLK_PVTM_PMU>; - clock-names = "clk"; - }; - }; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x200>; - mode-bootloader = ; - mode-charge = ; - mode-fastboot = ; - mode-loader = ; - mode-normal = ; - mode-recovery = ; - mode-ums = ; - }; - }; - - usb_pcie_grf: syscon@fe040000 { - compatible = "rockchip,usb-pcie-grf", "syscon"; - reg = <0x0 0xfe040000 0x0 0x1000>; - }; - - coregrf: syscon@fe050000 { - compatible = "rockchip,rk1808-coregrf", "syscon", "simple-mfd"; - reg = <0x0 0xfe050000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - pvtm: pvtm { - compatible = "rockchip,rk1808-pvtm"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - pvtm@0 { - reg = <0>; - clocks = <&cru SCLK_PVTM_CORE>; - clock-names = "clk"; - }; - }; - }; - - qos_npu: qos@fe850000 { - compatible = "syscon"; - reg = <0x0 0xfe850000 0x0 0x20>; - }; - - qos_pcie: qos@fe880000 { - compatible = "syscon"; - reg = <0x0 0xfe880000 0x0 0x20>; - status = "disabled"; - }; - - qos_usb2: qos@fe890000 { - compatible = "syscon"; - reg = <0x0 0xfe890000 0x0 0x20>; - status = "disabled"; - }; - - qos_usb3: qos@fe890080 { - compatible = "syscon"; - reg = <0x0 0xfe890080 0x0 0x20>; - status = "disabled"; - }; - - qos_isp: qos@fe8a0000 { - compatible = "syscon"; - reg = <0x0 0xfe8a0000 0x0 0x20>; - }; - - qos_rga_rd: qos@fe8a0080 { - compatible = "syscon"; - reg = <0x0 0xfe8a0080 0x0 0x20>; - }; - - qos_rga_wr: qos@fe8a0100 { - compatible = "syscon"; - reg = <0x0 0xfe8a0100 0x0 0x20>; - }; - - qos_cif: qos@fe8a0180 { - compatible = "syscon"; - reg = <0x0 0xfe8a0180 0x0 0x20>; - }; - - qos_vop_raw: qos@fe8b0000 { - compatible = "syscon"; - reg = <0x0 0xfe8b0000 0x0 0x20>; - }; - - qos_vop_lite: qos@fe8b0080 { - compatible = "syscon"; - reg = <0x0 0xfe8b0080 0x0 0x20>; - }; - - qos_vpu: qos@fe8c0000 { - compatible = "syscon"; - reg = <0x0 0xfe8c0000 0x0 0x20>; - }; - - sram: sram@fec00000 { - compatible = "mmio-sram"; - reg = <0x0 0xfec00000 0x0 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0xfec00000 0x200000>; - /* reserved for ddr dvfs and system suspend/resume */ - ddr-sram@0 { - reg = <0x0 0x8000>; - }; - /* reserved for vad audio buffer */ - vad_sram: vad-sram@1c0000 { - reg = <0x1c0000 0x40000>; - }; - }; - - hwlock: hwspinlock@ff040000 { - compatible = "rockchip,hwspinlock"; - reg = <0 0xff040000 0 0x10000>; - #hwlock-cells = <1>; - }; - - gic: interrupt-controller@ff100000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - - reg = <0x0 0xff100000 0 0x10000>, /* GICD */ - <0x0 0xff140000 0 0xc0000>, /* GICR */ - <0x0 0xff300000 0 0x10000>, /* GICC */ - <0x0 0xff310000 0 0x10000>, /* GICH */ - <0x0 0xff320000 0 0x10000>; /* GICV */ - interrupts = ; - its: interrupt-controller@ff120000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x0 0xff120000 0x0 0x20000>; - }; - }; - - efuse: efuse@ff260000 { - compatible = "rockchip,rk1808-efuse"; - reg = <0x0 0xff3b0000 0x0 0x50>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru SCLK_EFUSE_NS>, <&cru PCLK_EFUSE>; - clock-names = "sclk_efuse", "pclk_efuse"; - assigned-clocks = <&cru SCLK_EFUSE_NS>; - assigned-clock-rates = <24000000>; - rockchip,efuse-size = <0x20>; - - /* Data cells */ - efuse_id: id@7 { - reg = <0x07 0x10>; - }; - cpu_leakage: cpu-leakage@17 { - reg = <0x17 0x1>; - }; - logic_leakage: logic-leakage@18 { - reg = <0x18 0x1>; - }; - npu_leakage: npu-leakage@19 { - reg = <0x19 0x1>; - }; - efuse_cpu_version: cpu-version@1c { - reg = <0x1c 0x1>; - bits = <3 3>; - }; - }; - - cru: clock-controller@ff350000 { - compatible = "rockchip,rk1808-cru"; - reg = <0x0 0xff350000 0x0 0x5000>; - rockchip,grf = <&grf>; - rockchip,pmugrf = <&pmugrf>; - #clock-cells = <1>; - #reset-cells = <1>; - - assigned-clocks = - <&cru SCLK_32K_IOE>, - <&cru PLL_GPLL>, <&cru PLL_CPLL>, - <&cru PLL_PPLL>, <&cru ARMCLK>, - <&cru MSCLK_PERI>, <&cru LSCLK_PERI>, - <&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>, - <&cru LSCLK_BUS_PRE>; - assigned-clock-parents = <&xin32k>; - assigned-clock-rates = - <32768>, - <1188000000>, <1000000000>, - <100000000>, <816000000>, - <200000000>, <100000000>, - <300000000>, <200000000>, - <100000000>; - }; - - mipi_dphy_rx: mipi-dphy-rx@ff360000 { - compatible = "rockchip,rk1808-mipi-dphy-rx"; - reg = <0x0 0xff360000 0x0 0x4000>; - clocks = <&cru PCLK_MIPICSIPHY>; - clock-names = "pclk"; - power-domains = <&power RK1808_PD_VIO>; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - mipi_dphy: mipi-dphy@ff370000 { - compatible = "rockchip,rk1808-mipi-dphy"; - reg = <0x0 0xff370000 0x0 0x500>; - clocks = <&cru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; - clock-names = "ref", "pclk"; - clock-output-names = "mipi_dphy_pll"; - #clock-cells = <0>; - resets = <&cru SRST_MIPIDSIPHY_P>; - reset-names = "apb"; - #phy-cells = <0>; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - combphy: phy@ff380000 { - compatible = "rockchip,rk1808-combphy"; - reg = <0x0 0xff380000 0x0 0x10000>; - #phy-cells = <1>; - clocks = <&cru SCLK_PCIEPHY_REF>; - clock-names = "refclk"; - assigned-clocks = <&cru SCLK_PCIEPHY_REF>; - assigned-clock-rates = <25000000>; - resets = <&cru SRST_USB3_OTG_A>, <&cru SRST_PCIEPHY_POR>, - <&cru SRST_PCIEPHY_P>, <&cru SRST_PCIEPHY_PIPE>, - <&cru SRST_USB3PHY_GRF_P>; - reset-names = "otg-rst", "combphy-por", - "combphy-apb", "combphy-pipe", - "usb3phy_grf_p"; - rockchip,combphygrf = <&combphy_grf>; - rockchip,usbpciegrf = <&usb_pcie_grf>; - status = "disabled"; - }; - - thermal_zones: thermal-zones { - soc_thermal: soc-thermal { - polling-delay-passive = <20>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - sustainable-power = <977>; /* milliwatts */ - - thermal-sensors = <&tsadc 0>; - - trips { - threshold: trip-point-0 { - /* millicelsius */ - temperature = <75000>; - /* millicelsius */ - hysteresis = <2000>; - type = "passive"; - }; - target: trip-point-1 { - /* millicelsius */ - temperature = <85000>; - /* millicelsius */ - hysteresis = <2000>; - type = "passive"; - }; - soc_crit: soc-crit { - /* millicelsius */ - temperature = <115000>; - /* millicelsius */ - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <4096>; - }; - map1 { - trip = <&target>; - cooling-device = - <&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <1024>; - }; - }; - }; - }; - - tsadc: tsadc@ff3a0000 { - compatible = "rockchip,rk1808-tsadc"; - reg = <0x0 0xff3a0000 0x0 0x100>; - interrupts = ; - rockchip,grf = <&grf>; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - assigned-clocks = <&cru SCLK_TSADC>; - assigned-clock-rates = <650000>; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - #thermal-sensor-cells = <1>; - rockchip,hw-tshut-temp = <120000>; - status = "disabled"; - }; - - saradc: saradc@ff3c0000 { - compatible = "rockchip,rk1808-saradc", "rockchip,rk3399-saradc"; - reg = <0x0 0xff3c0000 0x0 0x100>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC_P>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - pwm0: pwm@ff3d0000 { - compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff3d0000 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm0_pin>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm1: pwm@ff3d0010 { - compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff3d0010 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm1_pin>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm2: pwm@ff3d0020 { - compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff3d0020 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm2_pin>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm3: pwm@ff3d0030 { - compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff3d0030 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm3_pin>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm4: pwm@ff3d8000 { - compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff3d8000 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm4_pin>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm5: pwm@ff3d8010 { - compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff3d8010 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm5_pin>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm6: pwm@ff3d8020 { - compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff3d8020 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm6_pin>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm7: pwm@ff3d8030 { - compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff3d8030 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm7_pin>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pmu: power-management@ff3e0000 { - compatible = "rockchip,rk1808-pmu", "syscon", "simple-mfd"; - reg = <0x0 0xff3e0000 0x0 0x1000>; - - power: power-controller { - compatible = "rockchip,rk1808-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - /* These power domains are grouped by VD_NPU */ - pd_npu@RK1808_VD_NPU { - reg = ; - clocks = <&cru SCLK_NPU>, - <&cru ACLK_NPU>, - <&cru HCLK_NPU>; - pm_qos = <&qos_npu>; - }; - - /* These power domains are grouped by VD_LOGIC */ - pd_pcie@RK1808_PD_PCIE { - reg = ; - clocks = <&cru HSCLK_PCIE>, - <&cru LSCLK_PCIE>, - <&cru ACLK_PCIE>, - <&cru ACLK_PCIE_MST>, - <&cru ACLK_PCIE_SLV>, - <&cru PCLK_PCIE>, - <&cru SCLK_PCIE_AUX>, - <&cru SCLK_PCIE_AUX>, - <&cru ACLK_USB3OTG>, - <&cru HCLK_HOST>, - <&cru HCLK_HOST_ARB>, - <&cru SCLK_USB3_OTG0_REF>, - <&cru SCLK_USB3_OTG0_SUSPEND>; - pm_qos = <&qos_pcie>, - <&qos_usb2>, - <&qos_usb3>; - }; - pd_vpu@RK1808_PD_VPU { - reg = ; - clocks = <&cru ACLK_VPU>, - <&cru HCLK_VPU>; - pm_qos = <&qos_vpu>; - }; - pd_vio@RK1808_PD_VIO { - reg = ; - clocks = <&cru HSCLK_VIO>, - <&cru LSCLK_VIO>, - <&cru ACLK_VOPRAW>, - <&cru HCLK_VOPRAW>, - <&cru ACLK_VOPLITE>, - <&cru HCLK_VOPLITE>, - <&cru PCLK_DSI_TX>, - <&cru PCLK_CSI_TX>, - <&cru ACLK_RGA>, - <&cru HCLK_RGA>, - <&cru ACLK_ISP>, - <&cru HCLK_ISP>, - <&cru ACLK_CIF>, - <&cru HCLK_CIF>, - <&cru PCLK_CSI2HOST>, - <&cru DCLK_VOPRAW>, - <&cru DCLK_VOPLITE>; - pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, - <&qos_isp>, <&qos_cif>, - <&qos_vop_raw>, <&qos_vop_lite>; - }; - }; - }; - - i2c0: i2c@ff410000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff410000 0x0 0x1000>; - clocks = <&cru SCLK_PMU_I2C0>, <&cru PCLK_I2C0_PMU>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - dmac: dmac@ff4e0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff4e0000 0x0 0x4000>; - interrupts = ; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - arm,pl330-periph-burst; - }; - - uart0: serial@ff430000 { - compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff430000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART0_PMU>, <&cru PCLK_UART0_PMU>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac 0>, <&dmac 1>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "disabled"; - }; - - i2c1: i2c@ff500000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff500000 0x0 0x1000>; - clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@ff504000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff504000 0x0 0x1000>; - clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2m0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@ff508000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff508000 0x0 0x1000>; - clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@ff50c000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff50c000 0x0 0x1000>; - clocks = <&cru SCLK_I2C4>, <&cru PCLK_I2C4>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@ff510000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xff510000 0x0 0x1000>; - clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@ff520000 { - compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff520000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac 10>, <&dmac 11>; - pinctrl-names = "default", "high_speed"; - pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; - pinctrl-1 = <&spi0_clk_hs &spi0_csn &spi0_miso_hs &spi0_mosi_hs>; - status = "disabled"; - }; - - spi1: spi@ff530000 { - compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff530000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac 12>, <&dmac 13>; - pinctrl-names = "default", "high_speed"; - pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; - pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_csn1 &spi1_miso_hs &spi1_mosi_hs>; - status = "disabled"; - }; - - uart1: serial@ff540000 { - compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff540000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac 2>, <&dmac 3>; - pinctrl-names = "default"; - pinctrl-0 = <&uart1m0_xfer &uart1_cts &uart1_rts>; - status = "disabled"; - }; - - uart2: serial@ff550000 { - compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff550000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac 4>, <&dmac 5>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer>; - status = "disabled"; - }; - - uart3: serial@ff560000 { - compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff560000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac 6>, <&dmac 7>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3m0_xfer &uart3_ctsm0 &uart3_rtsm0>; - status = "disabled"; - }; - - uart4: serial@ff570000 { - compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff570000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac 8>, <&dmac 9>; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; - status = "disabled"; - }; - - spi2: spi@ff580000 { - compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff580000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac 14>, <&dmac 15>; - pinctrl-names = "default", "high_speed"; - pinctrl-0 = <&spi2m0_clk &spi2m0_csn &spi2m0_miso &spi2m0_mosi>; - pinctrl-1 = <&spi2m0_clk_hs &spi2m0_csn &spi2m0_miso_hs &spi2m0_mosi_hs>; - status = "disabled"; - }; - - uart5: serial@ff5a0000 { - compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff5a0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac 25>, <&dmac 26>; - pinctrl-names = "default"; - pinctrl-0 = <&uart5_xfer>; - status = "disabled"; - }; - - uart6: serial@ff5b0000 { - compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff5b0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac 27>, <&dmac 28>; - pinctrl-names = "default"; - pinctrl-0 = <&uart6_xfer>; - status = "disabled"; - }; - - uart7: serial@ff5c0000 { - compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff5c0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac 29>, <&dmac 30>; - pinctrl-names = "default"; - pinctrl-0 = <&uart7_xfer>; - status = "disabled"; - }; - - pwm8: pwm@ff5d0000 { - compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff5d0000 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm8_pin>; - clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm9: pwm@fff5d0010 { - compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff5d0010 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm9_pin>; - clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm10: pwm@ff5d0020 { - compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff5d0020 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm10_pin>; - clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm11: pwm@ff5d0030 { - compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff5d0030 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm11_pin>; - clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - rng: rng@ff630000 { - compatible = "rockchip,cryptov2-rng"; - reg = <0x0 0xff630000 0x0 0x4000>; - clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>, - <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>; - clock-names = "clk_crypto", "clk_crypto_apk", - "aclk_crypto", "hclk_crypto"; - resets = <&cru SRST_CRYPTO_CORE>; - reset-names = "reset"; - status = "disabled"; - }; - - dcf: dcf@ff640000 { - compatible = "syscon"; - reg = <0x0 0xff640000 0x0 0x1000>; - }; - - rktimer: rktimer@ff700000 { - compatible = "rockchip,rk3288-timer"; - reg = <0x0 0xff700000 0x0 0x1000>; - interrupts = ; - clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; - clock-names = "pclk", "timer"; - }; - - wdt: watchdog@ff720000 { - compatible = "snps,dw-wdt"; - reg = <0x0 0xff720000 0x0 0x100>; - clocks = <&cru PCLK_WDT>; - interrupts = ; - status = "okay"; - }; - - i2s0: i2s@ff7e0000 { - compatible = "rockchip,rk1808-i2s-tdm"; - reg = <0x0 0xff7e0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru SCLK_I2S0_8CH_TX>, <&cru SCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - dmas = <&dmac 16>, <&dmac 17>; - dma-names = "tx", "rx"; - resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,cru = <&cru>; - rockchip,grf = <&grf>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_8ch_sclktx - &i2s0_8ch_sclkrx - &i2s0_8ch_lrcktx - &i2s0_8ch_lrckrx - &i2s0_8ch_sdi0 - &i2s0_8ch_sdi1 - &i2s0_8ch_sdi2 - &i2s0_8ch_sdi3 - &i2s0_8ch_sdo0 - &i2s0_8ch_sdo1 - &i2s0_8ch_sdo2 - &i2s0_8ch_sdo3 - &i2s0_8ch_mclk>; - status = "disabled"; - }; - - i2s1: i2s@ff7f0000 { - compatible = "rockchip,rk1808-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff7f0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac 18>, <&dmac 19>; - dma-names = "tx", "rx"; - resets = <&cru SRST_I2S1>, <&cru SRST_I2S1_H>; - reset-names = "reset-m", "reset-h"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_2ch_sclk - &i2s1_2ch_lrck - &i2s1_2ch_sdi - &i2s1_2ch_sdo>; - status = "disabled"; - }; - - pdm: pdm@ff800000 { - compatible = "rockchip,rk1808-pdm", "rockchip,pdm"; - reg = <0x0 0xff800000 0x0 0x1000>; - clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; - clock-names = "pdm_clk", "pdm_hclk"; - dmas = <&dmac 24>; - dma-names = "rx"; - resets = <&cru SRST_PDM>; - reset-names = "pdm-m"; - pinctrl-names = "default"; - pinctrl-0 = <&pdm_clk - &pdm_clk1 - &pdm_sdi0 - &pdm_sdi1 - &pdm_sdi2 - &pdm_sdi3>; - status = "disabled"; - }; - - vad: vad@ff810000 { - compatible = "rockchip,rk1808-vad"; - reg = <0x0 0xff810000 0x0 0x10000>; - reg-names = "vad"; - clocks = <&cru HCLK_VAD>; - clock-names = "hclk"; - interrupts = ; - rockchip,audio-sram = <&vad_sram>; - rockchip,audio-src = <0>; - rockchip,det-channel = <0>; - rockchip,mode = <1>; - status = "disabled"; - }; - - dfi: dfi@ff9c0000 { - reg = <0x00 0xff9c0000 0x00 0x400>; - compatible = "rockchip,rk1808-dfi"; - rockchip,pmugrf = <&pmugrf>; - status = "disabled"; - }; - - dmc: dmc { - compatible = "rockchip,rk1808-dmc"; - dcf_reg = <&dcf>; - interrupts = ; - interrupt-names = "complete_irq"; - devfreq-events = <&dfi>; - clocks = <&cru SCLK_DDRCLK>; - clock-names = "dmc_clk"; - operating-points-v2 = <&dmc_opp_table>; - ddr_timing = <&ddr_timing>; - upthreshold = <40>; - downdifferential = <20>; - system-status-freq = < - /*system status freq(KHz)*/ - SYS_STATUS_NORMAL 924000 - SYS_STATUS_REBOOT 450000 - SYS_STATUS_SUSPEND 328000 - SYS_STATUS_VIDEO_1080P 924000 - SYS_STATUS_BOOST 924000 - SYS_STATUS_ISP 924000 - SYS_STATUS_PERFORMANCE 924000 - >; - auto-min-freq = <328000>; - auto-freq-en = <0>; - #cooling-cells = <2>; - status = "disabled"; - }; - - dmc_opp_table: dmc-opp-table { - compatible = "operating-points-v2"; - - rockchip,max-volt = <950000>; - rockchip,evb-irdrop = <12500>; - nvmem-cells = <&logic_leakage>; - nvmem-cell-names = "leakage"; - rockchip,temp-hysteresis = <5000>; - rockchip,low-temp = <0>; - rockchip,low-temp-min-volt = <800000>; - - opp-192000000 { - opp-hz = /bits/ 64 <192000000>; - opp-microvolt = <800000>; - }; - opp-324000000 { - opp-hz = /bits/ 64 <324000000>; - opp-microvolt = <800000>; - }; - opp-450000000 { - opp-hz = /bits/ 64 <450000000>; - opp-microvolt = <800000>; - }; - opp-528000000 { - opp-hz = /bits/ 64 <528000000>; - opp-microvolt = <800000>; - }; - opp-664000000 { - opp-hz = /bits/ 64 <664000000>; - opp-microvolt = <800000>; - }; - opp-784000000 { - opp-hz = /bits/ 64 <784000000>; - opp-microvolt = <800000>; - }; - opp-924000000 { - opp-hz = /bits/ 64 <924000000>; - opp-microvolt = <800000>; - }; - /* 1066M is only for ddr4 */ - opp-1066000000 { - opp-hz = /bits/ 64 <1066000000>; - opp-microvolt = <800000>; - status = "disabled"; - }; - }; - - rk_rga: rk_rga@ffaf0000 { - compatible = "rockchip,rga2"; - dev_mode = <0>; - reg = <0x0 0xffaf0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; - clock-names = "aclk_rga", "hclk_rga", "clk_rga"; - power-domains = <&power RK1808_PD_VIO>; - status = "disabled"; - }; - - cif: cif@ffae0000 { - compatible = "rockchip,rk1808-cif"; - reg = <0x0 0xffae0000 0x0 0x200>; - reg-names = "cif_regs"; - interrupts = ; - interrupt-names = "cif-intr"; - clocks = <&cru ACLK_CIF>, <&cru DCLK_CIF>, - <&cru HCLK_CIF>, <&cru SCLK_CIF_OUT>; - clock-names = "aclk_cif", "dclk_cif", - "hclk_cif", "sclk_cif_out"; - resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, - <&cru SRST_CIF_I>, <&cru SRST_CIF_D>, - <&cru SRST_CIF_PCLKIN>; - reset-names = "rst_cif_a", "rst_cif_h", - "rst_cif_i", "rst_cif_d", - "rst_cif_pclkin"; - power-domains = <&power RK1808_PD_VIO>; - iommus = <&cif_mmu>; - status = "disabled"; - }; - - cif_mmu: iommu@ffae0800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xffae0800 0x0 0x100>; - interrupts = ; - interrupt-names = "cif_mmu"; - clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>; - clock-names = "aclk", "iface"; - power-domains = <&power RK1808_PD_VIO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - vop_lite: vop@ffb00000 { - compatible = "rockchip,rk1808-vop-lit"; - reg = <0x0 0xffb00000 0x0 0x200>; - reg-names = "regs"; - interrupts = ; - clocks = <&cru ACLK_VOPLITE>, <&cru DCLK_VOPLITE>, - <&cru HCLK_VOPLITE>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK1808_PD_VIO>; - iommus = <&vopl_mmu>; - status = "disabled"; - - vop_lite_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vop_lite_out_dsi: endpoint@0 { - reg = <0>; - remote-endpoint = <&dsi_in_vop_lite>; - }; - - vop_lite_out_rgb: endpoint@1 { - reg = <1>; - remote-endpoint = <&rgb_in_vop_lite>; - }; - }; - }; - - vopl_mmu: iommu@ffb00f00 { - compatible = "rockchip,iommu"; - reg = <0x0 0xffb00f00 0x0 0x100>; - interrupts = ; - interrupt-names = "vopl_mmu"; - clocks = <&cru ACLK_VOPLITE>, <&cru HCLK_VOPLITE>; - clock-names = "aclk", "iface"; - power-domains = <&power RK1808_PD_VIO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - mipi_csi2_hw: mipi-csi2-hw@ffb10000 { - compatible = "rockchip,rk1808-mipi-csi2-hw"; - reg = <0x0 0xffb10000 0x0 0x100>; - reg-names = "csihost_regs"; - interrupts = , - ; - interrupt-names = "csi-intr1", "csi-intr2"; - clocks = <&cru PCLK_CSI2HOST>; - clock-names = "pclk_csi2host"; - status = "disabled"; - }; - - csi_tx: csi@ffb20000 { - compatible = "rockchip,rk1808-mipi-csi"; - reg = <0x0 0xffb20000 0x0 0x500>; - reg-names = "csi_regs"; - interrupts = ; - clocks = <&cru PCLK_CSI_TX>, <&mipi_dphy>; - clock-names = "pclk", "hs_clk"; - resets = <&cru SRST_CSITX_P>, - <&cru SRST_CSITX_TXBYTEHS>, - <&cru SRST_CSITX_TXESC>, - <&cru SRST_CSITX_CAM>, - <&cru SRST_CSITX_I>; - reset-names = "tx_apb", "tx_bytehs", "tx_esc", "tx_cam", "tx_i"; - phys = <&mipi_dphy>; - phy-names = "mipi_dphy"; - power-domains = <&power RK1808_PD_VIO>; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - ports { - - port { - csi_in_vop_raw: endpoint { - remote-endpoint = <&vop_raw_out_csi>; - }; - }; - }; - }; - - dsi: dsi@ffb30000 { - compatible = "rockchip,rk1808-mipi-dsi"; - reg = <0x0 0xffb30000 0x0 0x500>; - interrupts = ; - clocks = <&cru PCLK_DSI_TX>, <&mipi_dphy>; - clock-names = "pclk", "hs_clk"; - resets = <&cru SRST_MIPIDSI_HOST_P>; - reset-names = "apb"; - phys = <&mipi_dphy>; - phy-names = "mipi_dphy"; - power-domains = <&power RK1808_PD_VIO>; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - ports { - port { - dsi_in_vop_lite: endpoint { - remote-endpoint = <&vop_lite_out_dsi>; - }; - }; - }; - }; - - vop_raw: vop@ffb40000 { - compatible = "rockchip,rk1808-vop-raw"; - reg = <0x0 0xffb40000 0x0 0x500>; - reg-names = "regs"; - interrupts = ; - clocks = <&cru ACLK_VOPRAW>, <&cru DCLK_VOPRAW>, - <&cru HCLK_VOPRAW>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - power-domains = <&power RK1808_PD_VIO>; - iommus = <&vopr_mmu>; - status = "disabled"; - - vop_raw_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vop_raw_out_csi: endpoint@0 { - reg = <0>; - remote-endpoint = <&csi_in_vop_raw>; - }; - }; - }; - - vopr_mmu: iommu@ffb40f00 { - compatible = "rockchip,iommu"; - reg = <0x0 0xffb40f00 0x0 0x100>; - interrupts = ; - interrupt-names = "vopr_mmu"; - clocks = <&cru ACLK_VOPRAW>, <&cru HCLK_VOPRAW>; - clock-names = "aclk", "iface"; - power-domains = <&power RK1808_PD_VIO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - rkisp1: rkisp1@ffb50000 { - compatible = "rockchip,rk1808-rkisp1"; - reg = <0x0 0xffb50000 0x0 0x8000>; - interrupts = , - , - ; - interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; - clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, - <&cru SCLK_ISP>, <&cru DCLK_CIF>; - clock-names = "aclk_isp", "hclk_isp", - "clk_isp", "pclk_isp"; - power-domains = <&power RK1808_PD_VIO>; - iommus = <&isp_mmu>; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - isp_mmu: iommu@ffb58000 { - compatible = "rockchip,iommu"; - reg = <0x0 0xffb58000 0x0 0x100>; - interrupts = ; - interrupt-names = "isp_mmu"; - clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, - <&cru SCLK_ISP>; - clock-names = "aclk", "iface", "sclk"; - power-domains = <&power RK1808_PD_VIO>; - rk_iommu,disable_reset_quirk; - #iommu-cells = <0>; - status = "disabled"; - }; - - vpu_service: vpu_service@ffb80000 { - compatible = "rockchip,vpu_service"; - reg = <0x0 0xffb80000 0x0 0x800>; - interrupts = , - ; - interrupt-names = "irq_enc", "irq_dec"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk_vcodec", "hclk_vcodec"; - power-domains = <&power RK1808_PD_VPU>; - resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>; - reset-names = "video_a", "video_h"; - iommus = <&vpu_mmu>; - iommu_enabled = <1>; - allocator = <1>; /* 0 means ion, 1 means drm */ - status = "disabled"; - }; - - vpu_mmu: iommu@ffb80800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xffb80800 0x0 0x100>; - interrupts = ; - interrupt-names = "vpu_mmu"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "iface"; - power-domains = <&power RK1808_PD_VPU>; - #iommu-cells = <0>; - status = "disabled"; - }; - - sdio: dwmmc@ffc60000 { - compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xffc60000 0x0 0x4000>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; - max-frequency = <150000000>; - fifo-depth = <0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; - status = "disabled"; - }; - - npu: npu@ffbc0000 { - compatible = "rockchip,npu"; - reg = <0x0 0xffbc0000 0x0 0x1000>; - clocks = <&cru SCLK_NPU>, <&cru ACLK_NPU>, <&cru HCLK_NPU>; - clock-names = "sclk_npu", "aclk_npu", "hclk_npu"; - assigned-clocks = <&cru SCLK_NPU>; - assigned-clock-rates = <800000000>; - interrupts = ; - power-domains = <&power RK1808_VD_NPU>; - operating-points-v2 = <&npu_opp_table>; - #cooling-cells = <2>; - status = "disabled"; - - npu_power_model: power-model { - compatible = "simple-power-model"; - ref-leakage = <31>; - static-coefficient = <100000>; - dynamic-coefficient = <3080>; - ts = <88610 303120 (-5000) 100>; - thermal-zone = "soc-thermal"; - }; - }; - - npu_opp_table: npu-opp-table { - compatible = "operating-points-v2"; - - rockchip,thermal-zone = "soc-thermal"; - rockchip,temp-hysteresis = <5000>; - rockchip,low-temp = <0>; - rockchip,low-temp-min-volt = <800000>; - rockchip,low-temp-adjust-volt = < - /* MHz MHz uV */ - 0 792 50000 - >; - - rockchip,max-volt = <880000>; - rockchip,evb-irdrop = <37500>; - nvmem-cells = <&npu_leakage>; - nvmem-cell-names = "leakage"; - - rockchip,pvtm-voltage-sel = < - 0 69000 0 - 69001 74000 1 - 74001 99999 2 - >; - rockchip,pvtm-ch = <0 0>; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <750000 750000 880000>; - }; - opp-297000000 { - opp-hz = /bits/ 64 <297000000>; - opp-microvolt = <750000 750000 880000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <750000 750000 880000>; - }; - opp-594000000 { - opp-hz = /bits/ 64 <594000000>; - opp-microvolt = <750000 750000 880000>; - }; - opp-792000000 { - opp-hz = /bits/ 64 <792000000>; - opp-microvolt = <850000 850000 880000>; - opp-microvolt-L0 = <850000 850000 880000>; - opp-microvolt-L1 = <825000 825000 880000>; - opp-microvolt-L2 = <800000 800000 880000>; - }; - }; - - sfc: sfc@ffc50000 { - compatible = "rockchip,sfc"; - reg = <0x0 0xffc50000 0x0 0x4000>; - interrupts = ; - clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; - clock-names = "clk_sfc", "hclk_sfc"; - assigned-clocks = <&cru SCLK_SFC>; - assigned-clock-rates = <100000000>; - status = "disabled"; - }; - - sdmmc: dwmmc@ffcf0000 { - compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xffcf0000 0x0 0x4000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; - max-frequency = <150000000>; - fifo-depth = <0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_detn>; - status = "disabled"; - }; - - emmc: dwmmc@ffd00000 { - compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xffd00000 0x0 0x4000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; - max-frequency = <150000000>; - fifo-depth = <0x100>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - status = "disabled"; - }; - - usb_host0_ehci: usb@ffd80000 { - compatible = "generic-ehci"; - reg = <0x0 0xffd80000 0x0 0x10000>; - interrupts = ; - clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, - <&u2phy>; - clock-names = "usbhost", "arbiter", "utmi"; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - power-domains = <&power RK1808_PD_PCIE>; - }; - - usb_host0_ohci: usb@ffd90000 { - compatible = "generic-ohci"; - reg = <0x0 0xffd90000 0x0 0x10000>; - interrupts = ; - clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, - <&u2phy>; - clock-names = "usbhost", "arbiter", "utmi"; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - power-domains = <&power RK1808_PD_PCIE>; - }; - - gmac: ethernet@ffdd0000 { - compatible = "rockchip,rk1808-gmac"; - reg = <0x0 0xffdd0000 0x0 0x10000>; - rockchip,grf = <&grf>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, - <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_GMAC_REF>, - <&cru SCLK_GMAC_REFOUT>, <&cru ACLK_GMAC>, - <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RGMII_SPEED>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "clk_mac_refout", "aclk_mac", - "pclk_mac", "clk_mac_speed"; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - resets = <&cru SRST_GAMC_A>; - reset-names = "stmmaceth"; - /* power-domains = <&power RK1808_PD_GMAC>; */ - status = "disabled"; - }; - - rockchip_system_monitor: rockchip-system-monitor { - compatible = "rockchip,system-monitor"; - - rockchip,thermal-zone = "soc-thermal"; - rockchip,polling-delay = <200>; /* milliseconds */ - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk1808-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio0@ff4c0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff4c0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0_PMU>, <&cru DBCLK_PMU_GPIO0>; - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@ff690000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff690000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@ff6a0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff6a0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@ff6b0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff6b0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio4@ff6c0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff6c0000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_2ma: pcfg-pull-none-2ma { - bias-disable; - drive-strength = <2>; - }; - - pcfg_pull_up_2ma: pcfg-pull-up-2ma { - bias-pull-up; - drive-strength = <2>; - }; - - pcfg_pull_up_4ma: pcfg-pull-up-4ma { - bias-pull-up; - drive-strength = <4>; - }; - - pcfg_pull_none_4ma: pcfg-pull-none-4ma { - bias-disable; - drive-strength = <4>; - }; - - pcfg_pull_down_4ma: pcfg-pull-down-4ma { - bias-pull-down; - drive-strength = <4>; - }; - - pcfg_pull_none_8ma: pcfg-pull-none-8ma { - bias-disable; - drive-strength = <8>; - }; - - pcfg_pull_up_8ma: pcfg-pull-up-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_pull_none_12ma: pcfg-pull-none-12ma { - bias-disable; - drive-strength = <12>; - }; - - pcfg_pull_up_12ma: pcfg-pull-up-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - pcfg_pull_none_smt: pcfg-pull-none-smt { - bias-disable; - input-schmitt-enable; - }; - - pcfg_pull_none_2ma_smt: pcfg-pull-none-2ma-smt { - bias-disable; - drive-strength = <2>; - input-schmitt-enable; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_input_high: pcfg-input-high { - bias-pull-up; - input-enable; - }; - - pcfg_input: pcfg-input { - input-enable; - }; - - pcfg_input_smt: pcfg-input-smt { - input-enable; - input-schmitt-enable; - }; - - cif-m0 { - cif_clkout_m0: cif-clkout-m0 { - rockchip,pins = - <2 RK_PB7 1 &pcfg_pull_none>; - }; - - cif_d12d15_m0: cif-d12d15-m0 { - rockchip,pins = - <2 RK_PA0 1 &pcfg_pull_none>,/* cif_d12 */ - <2 RK_PA1 1 &pcfg_pull_none>,/* cif_d13 */ - <2 RK_PA2 1 &pcfg_pull_none>,/* cif_d14 */ - <2 RK_PA3 1 &pcfg_pull_none>;/* cif_d15 */ - }; - - cif_d10d11_m0: cif-d10d11-m0 { - rockchip,pins = - <2 RK_PC2 1 &pcfg_pull_none>,/* cif_d10 */ - <2 RK_PC3 1 &pcfg_pull_none>;/* cif_d11 */ - }; - - cif_d2d9_m0: cif-d2d9-m0 { - rockchip,pins = - <2 RK_PA4 1 &pcfg_pull_none>,/* cif_d2 */ - <2 RK_PA5 1 &pcfg_pull_none>,/* cif_d3 */ - <2 RK_PA6 1 &pcfg_pull_none>,/* cif_d4 */ - <2 RK_PA7 1 &pcfg_pull_none>,/* cif_d5 */ - <2 RK_PB0 1 &pcfg_pull_none>,/* cif_d6 */ - <2 RK_PB1 1 &pcfg_pull_none>,/* cif_d7 */ - <2 RK_PB2 1 &pcfg_pull_none>,/* cif_d8 */ - <2 RK_PB3 1 &pcfg_pull_none>,/* cif_d9 */ - <2 RK_PB4 1 &pcfg_pull_none>,/* cif_vsync */ - <2 RK_PB5 1 &pcfg_pull_none>,/* cif_href */ - <2 RK_PB6 1 &pcfg_pull_none>;/* cif_clkin */ - }; - - cif_d0d1_m0: cif-d0d1-m0 { - rockchip,pins = - <2 RK_PC0 1 &pcfg_pull_none>,/* cif_d0 */ - <2 RK_PC1 1 &pcfg_pull_none>;/* cif_d1 */ - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = - /* emmc_clkout */ - <1 RK_PB1 1 &pcfg_pull_up_4ma>; - }; - - emmc_rstnout: emmc-rstnout { - rockchip,pins = - /* emmc_rstn */ - <1 RK_PB3 1 &pcfg_pull_none>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = - /* emmc_d0 */ - <1 RK_PA0 1 &pcfg_pull_up_4ma>, - /* emmc_d1 */ - <1 RK_PA1 1 &pcfg_pull_up_4ma>, - /* emmc_d2 */ - <1 RK_PA2 1 &pcfg_pull_up_4ma>, - /* emmc_d3 */ - <1 RK_PA3 1 &pcfg_pull_up_4ma>, - /* emmc_d4 */ - <1 RK_PA4 1 &pcfg_pull_up_4ma>, - /* emmc_d5 */ - <1 RK_PA5 1 &pcfg_pull_up_4ma>, - /* emmc_d6 */ - <1 RK_PA6 1 &pcfg_pull_up_4ma>, - /* emmc_d7 */ - <1 RK_PA7 1 &pcfg_pull_up_4ma>; - }; - - emmc_pwren: emmc-pwren { - rockchip,pins = - <1 RK_PB0 1 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = - <1 RK_PB2 1 &pcfg_pull_up_4ma>; - }; - }; - - gmac { - rgmii_pins: rgmii-pins { - rockchip,pins = - /* rgmii_txen */ - <2 RK_PA1 2 &pcfg_pull_none_4ma>, - /* rgmii_txd1 */ - <2 RK_PA2 2 &pcfg_pull_none_4ma>, - /* rgmii_txd0 */ - <2 RK_PA3 2 &pcfg_pull_none_4ma>, - /* rgmii_rxd0 */ - <2 RK_PA4 2 &pcfg_pull_none>, - /* rgmii_rxd1 */ - <2 RK_PA5 2 &pcfg_pull_none>, - /* rgmii_rxdv */ - <2 RK_PA7 2 &pcfg_pull_none>, - /* rgmii_mdio */ - <2 RK_PB0 2 &pcfg_pull_none_2ma>, - /* rgmii_mdc */ - <2 RK_PB2 2 &pcfg_pull_none_2ma>, - /* rgmii_txd3 */ - <2 RK_PB3 2 &pcfg_pull_none_4ma>, - /* rgmii_txd2 */ - <2 RK_PB4 2 &pcfg_pull_none_4ma>, - /* rgmii_rxd2 */ - <2 RK_PB5 2 &pcfg_pull_none>, - /* rgmii_rxd3 */ - <2 RK_PB6 2 &pcfg_pull_none>, - /* rgmii_clk */ - <2 RK_PB7 2 &pcfg_pull_none>, - /* rgmii_txclk */ - <2 RK_PC1 2 &pcfg_pull_none_4ma>, - /* rgmii_rxclk */ - <2 RK_PC2 2 &pcfg_pull_none>; - }; - - rmii_pins: rmii-pins { - rockchip,pins = - /* rmii_txen */ - <2 RK_PA1 2 &pcfg_pull_none_4ma>, - /* rmii_txd1 */ - <2 RK_PA2 2 &pcfg_pull_none_4ma>, - /* rmii_txd0 */ - <2 RK_PA3 2 &pcfg_pull_none_4ma>, - /* rmii_rxd0 */ - <2 RK_PA4 2 &pcfg_pull_none>, - /* rmii_rxd1 */ - <2 RK_PA5 2 &pcfg_pull_none>, - /* rmii_rxer */ - <2 RK_PA6 2 &pcfg_pull_none>, - /* rmii_rxdv */ - <2 RK_PA7 2 &pcfg_pull_none>, - /* rmii_mdio */ - <2 RK_PB0 2 &pcfg_pull_none_2ma>, - /* rmii_mdc */ - <2 RK_PB2 2 &pcfg_pull_none_2ma>, - /* rmii_clk */ - <2 RK_PB7 2 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = - /* i2c0_sda */ - <0 RK_PB1 1 &pcfg_pull_none_2ma_smt>, - /* i2c0_scl */ - <0 RK_PB0 1 &pcfg_pull_none_2ma_smt>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = - /* i2c1_sda */ - <0 RK_PC1 1 &pcfg_pull_none_2ma_smt>, - /* i2c1_scl */ - <0 RK_PC0 1 &pcfg_pull_none_2ma_smt>; - }; - }; - - i2c2m0 { - i2c2m0_xfer: i2c2m0-xfer { - rockchip,pins = - /* i2c2m0_sda */ - <3 RK_PB4 2 &pcfg_pull_none_2ma_smt>, - /* i2c2m0_scl */ - <3 RK_PB3 2 &pcfg_pull_none_2ma_smt>; - }; - }; - - i2c2m1 { - i2c2m1_xfer: i2c2m1-xfer { - rockchip,pins = - /* i2c2m1_sda */ - <1 RK_PB5 2 &pcfg_pull_none_2ma_smt>, - /* i2c2m1_scl */ - <1 RK_PB4 2 &pcfg_pull_none_2ma_smt>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = - /* i2c3_sda */ - <2 RK_PD1 1 &pcfg_pull_none_2ma_smt>, - /* i2c3_scl */ - <2 RK_PD0 1 &pcfg_pull_none_2ma_smt>; - }; - }; - - i2c4 { - i2c4_xfer: i2c4-xfer { - rockchip,pins = - /* i2c4_sda */ - <3 RK_PC3 3 &pcfg_pull_none_2ma_smt>, - /* i2c4_scl */ - <3 RK_PC2 3 &pcfg_pull_none_2ma_smt>; - }; - }; - - i2c5 { - i2c5_xfer: i2c5-xfer { - rockchip,pins = - /* i2c5_sda */ - <4 RK_PC2 1 &pcfg_pull_none_2ma_smt>, - /* i2c5_scl */ - <4 RK_PC1 1 &pcfg_pull_none_2ma_smt>; - }; - }; - - i2s1 { - i2s1_2ch_lrck: i2s1-2ch-lrck { - rockchip,pins = - <3 RK_PA0 1 &pcfg_pull_none_2ma>; - }; - i2s1_2ch_sclk: i2s1-2ch-sclk { - rockchip,pins = - <3 RK_PA1 1 &pcfg_pull_none_2ma>; - }; - i2s1_2ch_mclk: i2s1-2ch-mclk { - rockchip,pins = - <3 RK_PA2 1 &pcfg_pull_none_2ma>; - }; - i2s1_2ch_sdo: i2s1-2ch-sdo { - rockchip,pins = - <3 RK_PA3 1 &pcfg_pull_none_2ma>; - }; - i2s1_2ch_sdi: i2s1-2ch-sdi { - rockchip,pins = - <3 RK_PA4 1 &pcfg_pull_none_2ma>; - }; - }; - - i2s0 { - i2s0_8ch_sdi3: i2s0-8ch-sdi3 { - rockchip,pins = - <3 RK_PA5 1 &pcfg_pull_none_2ma>; - }; - i2s0_8ch_sdi2: i2s0-8ch-sdi2 { - rockchip,pins = - <3 RK_PA6 1 &pcfg_pull_none_2ma>; - }; - i2s0_8ch_sdi1: i2s0-8ch-sdi1 { - rockchip,pins = - <3 RK_PA7 1 &pcfg_pull_none_2ma>; - }; - i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { - rockchip,pins = - <3 RK_PB0 1 &pcfg_pull_none_2ma>; - }; - i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { - rockchip,pins = - <3 RK_PB1 1 &pcfg_pull_none_2ma>; - }; - i2s0_8ch_sdo3: i2s0-8ch-sdo3 { - rockchip,pins = - <3 RK_PB2 1 &pcfg_pull_none_2ma>; - }; - i2s0_8ch_sdo2: i2s0-8ch-sdo2 { - rockchip,pins = - <3 RK_PB3 1 &pcfg_pull_none_2ma>; - }; - i2s0_8ch_sdo1: i2s0-8ch-sdo1 { - rockchip,pins = - <3 RK_PB4 1 &pcfg_pull_none_2ma>; - }; - i2s0_8ch_mclk: i2s0-8ch-mclk { - rockchip,pins = - <3 RK_PB5 1 &pcfg_pull_none_2ma>; - }; - i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { - rockchip,pins = - <3 RK_PB6 1 &pcfg_pull_none_2ma>; - }; - i2s0_8ch_sclktx: i2s0-8ch-sclktx { - rockchip,pins = - <3 RK_PB7 1 &pcfg_pull_none_2ma>; - }; - i2s0_8ch_sdo0: i2s0-8ch-sdo0 { - rockchip,pins = - <3 RK_PC0 1 &pcfg_pull_none_2ma>; - }; - i2s0_8ch_sdi0: i2s0-8ch-sdi0 { - rockchip,pins = - <3 RK_PC1 1 &pcfg_pull_none_2ma>; - }; - }; - - lcdc { - lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { - rockchip,pins = - /* lcdc_clkm0 */ - <2 RK_PC6 3 &pcfg_pull_none>; - }; - - lcdc_rgb_den_pin: lcdc-rgb-den-pin { - rockchip,pins = - /* lcdc_denm0 */ - <2 RK_PC7 3 &pcfg_pull_none>; - }; - - lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { - rockchip,pins = - /* lcdc_hsyncm0 */ - <2 RK_PB2 3 &pcfg_pull_none>; - }; - - lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { - rockchip,pins = - /* lcdc_vsyncm0 */ - <2 RK_PB3 3 &pcfg_pull_none>; - }; - - lcdc_rgb_m1_hsync_pin: lcdc-rgb-m1-hsync-pin { - rockchip,pins = - /* lcdc_hsyncm1 */ - <3 RK_PB2 3 &pcfg_pull_none>; - }; - - lcdc_rgb_m1_vsync_pin: lcdc-rgb-m1-vsync-pin { - rockchip,pins = - /* lcdc_vsyncm1 */ - <3 RK_PB3 3 &pcfg_pull_none>; - }; - - lcdc_rgb666_data_pins: lcdc-rgb666-data-pins { - rockchip,pins = - /* lcdc_d0m0 */ - <2 RK_PA2 3 &pcfg_pull_none>, - /* lcdc_d1m0 */ - <2 RK_PA3 3 &pcfg_pull_none>, - /* lcdc_d2m0 */ - <2 RK_PC2 3 &pcfg_pull_none>, - /* lcdc_d3m0 */ - <2 RK_PC3 3 &pcfg_pull_none>, - /* lcdc_d4m0 */ - <2 RK_PC4 3 &pcfg_pull_none>, - /* lcdc_d5m0 */ - <2 RK_PC5 3 &pcfg_pull_none>, - /* lcdc_d6m0 */ - <2 RK_PA0 3 &pcfg_pull_none>, - /* lcdc_d7m0 */ - <2 RK_PA1 3 &pcfg_pull_none>, - /* lcdc_d8 */ - <3 RK_PC2 1 &pcfg_pull_none>, - /* lcdc_d9 */ - <3 RK_PC3 1 &pcfg_pull_none>, - /* lcdc_d10 */ - <3 RK_PC4 1 &pcfg_pull_none>, - /* lcdc_d11 */ - <3 RK_PC5 1 &pcfg_pull_none>, - /* lcdc_d12 */ - <3 RK_PC6 1 &pcfg_pull_none>, - /* lcdc_d13 */ - <3 RK_PC7 1 &pcfg_pull_none>, - /* lcdc_d14 */ - <3 RK_PD0 1 &pcfg_pull_none>, - /* lcdc_d15 */ - <3 RK_PD1 1 &pcfg_pull_none>, - /* lcdc_d16 */ - <3 RK_PD2 1 &pcfg_pull_none>, - /* lcdc_d17 */ - <3 RK_PD3 1 &pcfg_pull_none>; - }; - - lcdc_rgb565_data_pins: lcdc-rgb565-data-pins { - rockchip,pins = - /* lcdc_d0m0 */ - <2 RK_PA2 3 &pcfg_pull_none>, - /* lcdc_d1m0 */ - <2 RK_PA3 3 &pcfg_pull_none>, - /* lcdc_d2m0 */ - <2 RK_PC2 3 &pcfg_pull_none>, - /* lcdc_d3m0 */ - <2 RK_PC3 3 &pcfg_pull_none>, - /* lcdc_d4m0 */ - <2 RK_PC4 3 &pcfg_pull_none>, - /* lcdc_d5m0 */ - <2 RK_PC5 3 &pcfg_pull_none>, - /* lcdc_d6m0 */ - <2 RK_PA0 3 &pcfg_pull_none>, - /* lcdc_d7m0 */ - <2 RK_PA1 3 &pcfg_pull_none>, - /* lcdc_d8 */ - <3 RK_PC2 1 &pcfg_pull_none>, - /* lcdc_d9 */ - <3 RK_PC3 1 &pcfg_pull_none>, - /* lcdc_d10 */ - <3 RK_PC4 1 &pcfg_pull_none>, - /* lcdc_d11 */ - <3 RK_PC5 1 &pcfg_pull_none>, - /* lcdc_d12 */ - <3 RK_PC6 1 &pcfg_pull_none>, - /* lcdc_d13 */ - <3 RK_PC7 1 &pcfg_pull_none>, - /* lcdc_d14 */ - <3 RK_PD0 1 &pcfg_pull_none>, - /* lcdc_d15 */ - <3 RK_PD1 1 &pcfg_pull_none>; - }; - }; - - pciusb { - pciusb_pins: pciusb-pins { - rockchip,pins = - /* pciusb_debug0 */ - <4 RK_PB4 3 &pcfg_pull_none>, - /* pciusb_debug1 */ - <4 RK_PB5 3 &pcfg_pull_none>, - /* pciusb_debug2 */ - <4 RK_PB6 3 &pcfg_pull_none>, - /* pciusb_debug3 */ - <4 RK_PB7 3 &pcfg_pull_none>, - /* pciusb_debug4 */ - <4 RK_PC0 3 &pcfg_pull_none>, - /* pciusb_debug5 */ - <4 RK_PC1 3 &pcfg_pull_none>, - /* pciusb_debug6 */ - <4 RK_PC2 3 &pcfg_pull_none>, - /* pciusb_debug7 */ - <4 RK_PC3 3 &pcfg_pull_none>; - }; - - pcie_clkreq: pcie-clkreq { - rockchip,pins = - /* pcie_clkreqn_m1 */ - <0 RK_PC6 1 &pcfg_pull_none >; - }; - }; - - pdm { - pdm_clk: pdm-clk { - rockchip,pins = - /* pdm_clk0 */ - <3 RK_PB0 2 &pcfg_pull_none_2ma>; - }; - - pdm_sdi3: pdm-sdi3 { - rockchip,pins = - <3 RK_PA5 2 &pcfg_pull_none_2ma>; - }; - - pdm_sdi2: pdm-sdi2 { - rockchip,pins = - <3 RK_PA6 2 &pcfg_pull_none_2ma>; - }; - - pdm_sdi1: pdm-sdi1 { - rockchip,pins = - <3 RK_PA7 2 &pcfg_pull_none_2ma>; - }; - - pdm_clk1: pdm-clk1 { - rockchip,pins = - <3 RK_PB1 2 &pcfg_pull_none_2ma>; - }; - - pdm_sdi0: pdm-sdi0 { - rockchip,pins = - <3 RK_PC1 2 &pcfg_pull_none_2ma>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = - <0 RK_PB7 1 &pcfg_pull_none_2ma>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = - <0 RK_PC3 1 &pcfg_pull_none_2ma>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = - <0 RK_PC5 1 &pcfg_pull_none_2ma>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = - <0 RK_PC4 1 &pcfg_pull_none_2ma>; - }; - }; - - pwm4 { - pwm4_pin: pwm4-pin { - rockchip,pins = - <1 RK_PB6 2 &pcfg_pull_none_2ma>; - }; - }; - - pwm5 { - pwm5_pin: pwm5-pin { - rockchip,pins = - <1 RK_PB7 2 &pcfg_pull_none_2ma>; - }; - }; - pwm6 { - pwm6_pin: pwm6-pin { - rockchip,pins = - <3 RK_PA1 2 &pcfg_pull_none_2ma>; - }; - }; - - pwm7 { - pwm7_pin: pwm7-pin { - rockchip,pins = - <3 RK_PA2 2 &pcfg_pull_none_2ma>; - }; - }; - - pwm8 { - pwm8_pin: pwm8-pin { - rockchip,pins = - <3 RK_PD0 2 &pcfg_pull_none_2ma>; - }; - }; - - pwm9 { - pwm9_pin: pwm9-pin { - rockchip,pins = - <3 RK_PD1 2 &pcfg_pull_none_2ma>; - }; - }; - - pwm10 { - pwm10_pin: pwm10-pin { - rockchip,pins = - <3 RK_PD2 2 &pcfg_pull_none_2ma>; - }; - }; - - pwm11 { - pwm11_pin: pwm11-pin { - rockchip,pins = - <3 RK_PD3 2 &pcfg_pull_none_2ma>; - }; - }; - - sdmmc0 { - sdmmc0_bus4: sdmmc0-bus4 { - rockchip,pins = - /* sdmmc0_d0 */ - <4 RK_PA2 1 &pcfg_pull_up_8ma>, - /* sdmmc0_d1 */ - <4 RK_PA3 1 &pcfg_pull_up_8ma>, - /* sdmmc0_d2 */ - <4 RK_PA4 1 &pcfg_pull_up_8ma>, - /* sdmmc0_d3 */ - <4 RK_PA5 1 &pcfg_pull_up_8ma>; - }; - - sdmmc0_cmd: sdmmc0-cmd { - rockchip,pins = - <4 RK_PA0 1 &pcfg_pull_up_8ma>; - }; - - sdmmc0_clk: sdmmc0-clk { - rockchip,pins = - <4 RK_PA1 1 &pcfg_pull_up_8ma>; - }; - - sdmmc0_detn: sdmmc0-detn { - rockchip,pins = - <0 RK_PA3 1 &pcfg_pull_none>; - }; - }; - - sdmmc1 { - sdmmc1_bus4: sdmmc1-bus4 { - rockchip,pins = - /* sdmmc1_d0 */ - <4 RK_PB0 1 &pcfg_pull_up_4ma>, - /* sdmmc1_d1 */ - <4 RK_PB1 1 &pcfg_pull_up_4ma>, - /* sdmmc1_d2 */ - <4 RK_PB2 1 &pcfg_pull_up_4ma>, - /* sdmmc1_d3 */ - <4 RK_PB3 1 &pcfg_pull_up_4ma>; - }; - - sdmmc1_cmd: sdmmc1-cmd { - rockchip,pins = - <4 RK_PA6 1 &pcfg_pull_up_4ma>; - }; - - sdmmc1_clk: sdmmc1-clk { - rockchip,pins = - <4 RK_PA7 1 &pcfg_pull_up_4ma>; - }; - }; - - spi0 { - spi0_mosi: spi0-mosi { - rockchip,pins = - <1 RK_PB4 1 &pcfg_pull_up_2ma>; - }; - - spi0_miso: spi0-miso { - rockchip,pins = - <1 RK_PB5 1 &pcfg_pull_up_2ma>; - }; - - spi0_csn: spi0-csn { - rockchip,pins = - <1 RK_PB6 1 &pcfg_pull_up_2ma>; - }; - - spi0_clk: spi0-clk { - rockchip,pins = - <1 RK_PB7 1 &pcfg_pull_up_2ma>; - }; - - spi0_mosi_hs: spi0-mosi-hs { - rockchip,pins = - <1 RK_PB4 1 &pcfg_pull_up_2ma>; - }; - - spi0_miso_hs: spi0-miso-hs { - rockchip,pins = - <1 RK_PB5 1 &pcfg_pull_up_2ma>; - }; - - spi0_csn_hs: spi0-csn-hs { - rockchip,pins = - <1 RK_PB6 1 &pcfg_pull_up_2ma>; - }; - - spi0_clk_hs: spi0-clk-hs { - rockchip,pins = - <1 RK_PB7 1 &pcfg_pull_up_2ma>; - }; - }; - - spi1m0 { - spi1_clk: spi1-clk { - rockchip,pins = - <4 RK_PB4 2 &pcfg_pull_up_2ma>; - }; - - spi1_mosi: spi1-mosi { - rockchip,pins = - <4 RK_PB5 2 &pcfg_pull_up_2ma>; - }; - - spi1_csn0: spi1-csn0 { - rockchip,pins = - <4 RK_PB6 2 &pcfg_pull_up_2ma>; - }; - - spi1_miso: spi1-miso { - rockchip,pins = - <4 RK_PB7 2 &pcfg_pull_up_2ma>; - }; - - spi1_csn1: spi1-csn1 { - rockchip,pins = - <4 RK_PC0 2 &pcfg_pull_up_2ma>; - }; - - spi1_clk_hs: spi1-clk-hs { - rockchip,pins = - <4 RK_PB4 2 &pcfg_pull_up_2ma>; - }; - - spi1_mosi_hs: spi1-mosi-hs { - rockchip,pins = - <4 RK_PB5 2 &pcfg_pull_up_2ma>; - }; - - spi1_csn0_hs: spi1-csn0-hs { - rockchip,pins = - <4 RK_PB6 2 &pcfg_pull_up_2ma>; - }; - - spi1_miso_hs: spi1-miso-hs { - rockchip,pins = - <4 RK_PB7 2 &pcfg_pull_up_2ma>; - }; - - spi1_csn1_hs: spi1-csn1-hs { - rockchip,pins = - <4 RK_PC0 2 &pcfg_pull_up_2ma>; - }; - }; - - spi1m1 { - spi1m1_clk: spi1m1-clk { - rockchip,pins = - <3 RK_PC7 3 &pcfg_pull_up_2ma>; - }; - - spi1m1_mosi: spi1m1-mosi { - rockchip,pins = - <3 RK_PD0 3 &pcfg_pull_up_2ma>; - }; - - spi1m1_csn0: spi1m1-csn0 { - rockchip,pins = - <3 RK_PD1 3 &pcfg_pull_up_2ma>; - }; - - spi1m1_miso: spi1m1-miso { - rockchip,pins = - <3 RK_PD2 3 &pcfg_pull_up_2ma>; - }; - - spi1m1_csn1: spi1m1-csn1 { - rockchip,pins = - <3 RK_PD3 3 &pcfg_pull_up_2ma>; - }; - - spi1m1_clk_hs: spi1m1-clk-hs { - rockchip,pins = - <3 RK_PC7 3 &pcfg_pull_up_2ma>; - }; - - spi1m1_mosi_hs: spi1m1-mosi-hs { - rockchip,pins = - <3 RK_PD0 3 &pcfg_pull_up_2ma>; - }; - - spi1m1_csn0_hs: spi1m1-csn0-hs { - rockchip,pins = - <3 RK_PD1 3 &pcfg_pull_up_2ma>; - }; - - spi1m1_miso_hs: spi1m1-miso-hs { - rockchip,pins = - <3 RK_PD2 3 &pcfg_pull_up_2ma>; - }; - - spi1m1_csn1_hs: spi1m1-csn1-hs { - rockchip,pins = - <3 RK_PD3 3 &pcfg_pull_up_2ma>; - }; - }; - - spi2m0 { - spi2m0_miso: spi2m0-miso { - rockchip,pins = - <1 RK_PA6 2 &pcfg_pull_up_2ma>; - }; - - spi2m0_clk: spi2m0-clk { - rockchip,pins = - <1 RK_PA7 2 &pcfg_pull_up_2ma>; - }; - - spi2m0_mosi: spi2m0-mosi { - rockchip,pins = - <1 RK_PB0 2 &pcfg_pull_up_2ma>; - }; - - spi2m0_csn: spi2m0-csn { - rockchip,pins = - <1 RK_PB1 2 &pcfg_pull_up_2ma>; - }; - - spi2m0_miso_hs: spi2m0-miso-hs { - rockchip,pins = - <1 RK_PA6 2 &pcfg_pull_up_2ma>; - }; - - spi2m0_clk_hs: spi2m0-clk-hs { - rockchip,pins = - <1 RK_PA7 2 &pcfg_pull_up_2ma>; - }; - - spi2m0_mosi_hs: spi2m0-mosi-hs { - rockchip,pins = - <1 RK_PB0 2 &pcfg_pull_up_2ma>; - }; - - spi2m0_csn_hs: spi2m0-csn-hs { - rockchip,pins = - <1 RK_PB1 2 &pcfg_pull_up_2ma>; - }; - }; - - spi2m1 { - spi2m1_miso: spi2m1-miso { - rockchip,pins = - <2 RK_PA4 3 &pcfg_pull_up_2ma>; - }; - - spi2m1_clk: spi2m1-clk { - rockchip,pins = - <2 RK_PA5 3 &pcfg_pull_up_2ma>; - }; - - spi2m1_mosi: spi2m1-mosi { - rockchip,pins = - <2 RK_PA6 3 &pcfg_pull_up_2ma>; - }; - - spi2m1_csn: spi2m1-csn { - rockchip,pins = - <2 RK_PA7 3 &pcfg_pull_up_2ma>; - }; - - spi2m1_miso_hs: spi2m1-miso-hs { - rockchip,pins = - <2 RK_PA4 3 &pcfg_pull_up_2ma>; - }; - - spi2m1_clk_hs: spi2m1-clk-hs { - rockchip,pins = - <2 RK_PA5 3 &pcfg_pull_up_2ma>; - }; - - spi2m1_mosi_hs: spi2m1-mosi-hs { - rockchip,pins = - <2 RK_PA6 3 &pcfg_pull_up_2ma>; - }; - - spi2m1_csn_hs: spi2m1-csn-hs { - rockchip,pins = - <2 RK_PA7 3 &pcfg_pull_up_2ma>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = - /* uart0_rx */ - <0 RK_PB3 1 &pcfg_pull_up_2ma>, - /* uart0_tx */ - <0 RK_PB2 1 &pcfg_pull_up_2ma>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = - <0 RK_PB4 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = - <0 RK_PB5 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1m0_xfer: uart1m0-xfer { - rockchip,pins = - /* uart1_rxm0 */ - <4 RK_PB0 2 &pcfg_pull_up_2ma>, - /* uart1_txm0 */ - <4 RK_PB1 2 &pcfg_pull_up_2ma>; - }; - - uart1m1_xfer: uart1m1-xfer { - rockchip,pins = - /* uart1_rxm1 */ - <1 RK_PB4 3 &pcfg_pull_up_2ma>, - /* uart1_txm1 */ - <1 RK_PB5 3 &pcfg_pull_up_2ma>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = - <4 RK_PB2 2 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = - <4 RK_PB3 2 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = - /* uart2_rxm0 */ - <4 RK_PA3 2 &pcfg_pull_up_2ma>, - /* uart2_txm0 */ - <4 RK_PA2 2 &pcfg_pull_up_2ma>; - }; - - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = - /* uart2_rxm1 */ - <2 RK_PD1 2 &pcfg_pull_up_2ma>, - /* uart2_txm1 */ - <2 RK_PD0 2 &pcfg_pull_up_2ma>; - }; - - uart2m2_xfer: uart2m2-xfer { - rockchip,pins = - /* uart2_rxm2 */ - <3 RK_PA4 2 &pcfg_pull_up_2ma>, - /* uart2_txm2 */ - <3 RK_PA3 2 &pcfg_pull_up_2ma>; - }; - }; - - uart3 { - uart3m0_xfer: uart3m0-xfer { - rockchip,pins = - /* uart3_rxm0 */ - <0 RK_PC4 2 &pcfg_pull_up_2ma>, - /* uart3_txm0 */ - <0 RK_PC3 2 &pcfg_pull_up_2ma>; - }; - - uart3_ctsm0: uart3-ctsm0 { - rockchip,pins = - <0 RK_PC6 2 &pcfg_pull_none>; - }; - - uart3_rtsm0: uart3-rtsm0 { - rockchip,pins = - <0 RK_PC7 2 &pcfg_pull_none>; - }; - }; - - uart4 { - uart4_xfer: uart4-xfer { - rockchip,pins = - /* uart4_rx */ - <4 RK_PB4 1 &pcfg_pull_up_2ma>, - /* uart4_tx */ - <4 RK_PB5 1 &pcfg_pull_up_2ma>; - }; - - uart4_cts: uart4-cts { - rockchip,pins = - <4 RK_PB6 1 &pcfg_pull_none>; - }; - - uart4_rts: uart4-rts { - rockchip,pins = - <4 RK_PB7 1 &pcfg_pull_none>; - }; - }; - - uart5 { - uart5_xfer: uart5-xfer { - rockchip,pins = - /* uart5_rx */ - <3 RK_PC3 2 &pcfg_pull_up_2ma>, - /* uart5_tx */ - <3 RK_PC2 2 &pcfg_pull_up_2ma>; - }; - }; - - uart6 { - uart6_xfer: uart6-xfer { - rockchip,pins = - /* uart6_rx */ - <3 RK_PC5 2 &pcfg_pull_up_2ma>, - /* uart6_tx */ - <3 RK_PC4 2 &pcfg_pull_up_2ma>; - }; - }; - - uart7 { - uart7_xfer: uart7-xfer { - rockchip,pins = - /* uart7_rx */ - <3 RK_PC7 2 &pcfg_pull_up_2ma>, - /* uart7_tx */ - <3 RK_PC6 2 &pcfg_pull_up_2ma>; - }; - }; - - tsadc { - tsadc_otp_gpio: tsadc-otp-gpio { - rockchip,pins = - <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - tsadc_otp_out: tsadc-otp-out { - rockchip,pins = - <0 RK_PA6 2 &pcfg_pull_none>; - }; - }; - - xin32k { - clkin_32k: clkin-32k { - rockchip,pins = - <0 RK_PC2 1 &pcfg_pull_none>; - }; - - clkout_32k: clkout-32k { - rockchip,pins = - <0 RK_PC2 1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk1808k.dtsi b/arch/arm64/boot/dts/rockchip/rk1808k.dtsi deleted file mode 100644 index 78bd92e4c..000000000 --- a/arch/arm64/boot/dts/rockchip/rk1808k.dtsi +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd - */ - -&cpu0_opp_table { - rockchip,high-temp = <85000>; - rockchip,high-temp-max-freq = <1008000>; -}; - -&dmc { - status = "okay"; - center-supply = <&vdd_log>; - system-status-freq = < - /*system status freq(KHz)*/ - SYS_STATUS_NORMAL 924000 - SYS_STATUS_REBOOT 924000 - >; -}; - -&dmc_opp_table { - rockchip,high-temp = <85000>; - rockchip,high-temp-max-freq = <664000>; - rockchip,thermal-zone = "soc-thermal"; -}; - -&thermal_zones { - soc-thermal { - sustainable-power = <1224>; - k_pu = <27>; - k_po = <55>; - k_i = <0>; - - trips { - trip-point-0 { - temperature = <85000>; - }; - trip-point-1 { - temperature = <100000>; - }; - }; - /delete-node/ cooling-maps; - cooling-maps { - map0 { - trip = <&target>; - cooling-device = - <&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-amp.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-amp.dtsi deleted file mode 100644 index 8ee5ed109..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-amp.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Rockchip Electronics Co., Ltd. - */ - -/ { - rockchip_amp: rockchip-amp { - compatible = "rockchip,mcu-amp"; - clocks = <&cru HCLK_PMU_CM0_ROOT>, <&cru FCLK_PMU_CM0_CORE>, - <&cru CLK_PMU_CM0_RTC>, <&cru PCLK_PMUCM0_INTMUX>, - <&cru SCLK_UART5>, <&cru PCLK_UART5>, - <&cru PCLK_BUSTIMER1>, <&cru CLK_BUSTIMER10>, <&cru CLK_BUSTIMER11>; - - pinctrl-names = "default"; - pinctrl-0 = <&uart5m0_xfer>; - - status = "okay"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* mcu address */ - mcu_reserved: mcu@8200000 { - reg = <0x0 0x8200000 0x0 0x100000>; - no-map; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-android.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-android.dtsi deleted file mode 100644 index 8901a033e..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-android.dtsi +++ /dev/null @@ -1,143 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/ { - chosen: chosen { - bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 irqchip.gicv3_pseudo_nmi=0"; - }; - - cspmu: cspmu@fd10c000 { - compatible = "rockchip,cspmu"; - reg = <0x0 0xfd10c000 0x0 0x1000>, - <0x0 0xfd10d000 0x0 0x1000>, - <0x0 0xfd10e000 0x0 0x1000>, - <0x0 0xfd10f000 0x0 0x1000>, - <0x0 0xfd12c000 0x0 0x1000>, - <0x0 0xfd12d000 0x0 0x1000>, - <0x0 0xfd12e000 0x0 0x1000>, - <0x0 0xfd12f000 0x0 0x1000>; - }; - - debug: debug@fd104000 { - compatible = "rockchip,debug"; - reg = <0x0 0xfd104000 0x0 0x1000>, - <0x0 0xfd105000 0x0 0x1000>, - <0x0 0xfd106000 0x0 0x1000>, - <0x0 0xfd107000 0x0 0x1000>, - <0x0 0xfd124000 0x0 0x1000>, - <0x0 0xfd125000 0x0 0x1000>, - <0x0 0xfd126000 0x0 0x1000>, - <0x0 0xfd127000 0x0 0x1000>; - }; - - fiq_debugger: fiq-debugger { - compatible = "rockchip,fiq-debugger"; - rockchip,serial-id = <2>; - rockchip,wake-irq = <0>; - /* If enable uart uses irq instead of fiq */ - rockchip,irq-mode-enable = <1>; - rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; - }; - - firmware { - optee: optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; - - minidump: minidump { - compatible = "rockchip,minidump"; - smem-region = <&minidump_smem>; - minidump-region = <&minidump_mem>; - status = "disabled"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x0 (8 * 0x100000)>; - linux,cma-default; - }; - - drm_logo: drm-logo@00000000 { - compatible = "rockchip,drm-logo"; - reg = <0x0 0x0 0x0 0x0>; - }; - - drm_cubic_lut: drm-cubic-lut@00000000 { - compatible = "rockchip,drm-cubic-lut"; - reg = <0x0 0x0 0x0 0x0>; - }; - - vendor_storage_rm: vendor-storage-rm@00000000 { - compatible = "rockchip,vendor-storage-rm"; - reg = <0x0 0x0 0x0 0x0>; - }; - - ramoops: ramoops@110000 { - compatible = "ramoops"; - /* 0x110000 to 0x1f0000 is for ramoops */ - reg = <0x0 0x110000 0x0 0xe0000>; - boot-log-size = <0x8000>; /* do not change */ - boot-log-count = <0x1>; /* do not change */ - console-size = <0x80000>; - pmsg-size = <0x30000>; - ftrace-size = <0x00000>; - record-size = <0x14000>; - }; - - minidump_smem: minidump-smem@1f0000 { - reg = <0x0 0x1f0000 0x0 0x100>; /* do not change */ - no-map; - status = "disabled"; - }; - - minidump_mem: minidump-mem@c000000 { - reg = <0x0 0x0c000000 0x0 0x2000000>; /* changing according to your project */ - no-map; - status = "disabled"; - }; - }; - - vendor_storage: vendor-storage { - compatible = "rockchip,ram-vendor-storage"; - memory-region = <&vendor_storage_rm>; - status = "okay"; - }; -}; - -&display_subsystem { - memory-region = <&drm_logo>; - memory-region-names = "drm-logo"; -}; - -&dfi { - status = "okay"; -}; - -&dmc { - status = "okay"; - center-supply = <&vdd_ddr_s0>; - mem-supply = <&vdd_log_s0>; -}; - -&rng { - status = "okay"; -}; - -&vop { - support-multi-area; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-cpu-swap.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-cpu-swap.dtsi deleted file mode 100644 index a64ec7c7a..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-cpu-swap.dtsi +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. - */ - -/delete-node/ &cpu_l0; -/delete-node/ &cpu_l1; -/delete-node/ &cpu_l2; -/delete-node/ &cpu_l3; - -/ { - cpus { - cpu_l0: cpu@0000 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - operating-points-v2 = <&cluster0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l0>; - #cooling-cells = <2>; - dynamic-power-coefficient = <100>; - }; - - cpu_l1: cpu@0100 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - operating-points-v2 = <&cluster0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l1>; - }; - - cpu_l2: cpu@0200 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x200>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - operating-points-v2 = <&cluster0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l2>; - }; - - cpu_l3: cpu@0300 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x300>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - operating-points-v2 = <&cluster0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l3>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi deleted file mode 100644 index 14620a87b..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi +++ /dev/null @@ -1,1250 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - adc_keys: adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - vol-up-key { - label = "volume up"; - linux,code = ; - press-threshold-microvolt = <17000>; - }; - - vol-down-key { - label = "volume down"; - linux,code = ; - press-threshold-microvolt = <417000>; - }; - - menu-key { - label = "menu"; - linux,code = ; - press-threshold-microvolt = <890000>; - }; - - back-key { - label = "back"; - linux,code = ; - press-threshold-microvolt = <1235000>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - bt_sco: bt-sco { - status = "disabled"; - compatible = "delta,dfbmcs320"; - #sound-dai-cells = <1>; - }; - - bt_sound: bt-sound { - status = "disabled"; - compatible = "simple-audio-card"; - simple-audio-card,format = "dsp_a"; - simple-audio-card,bitclock-inversion = <0>; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "rockchip,bt"; - simple-audio-card,cpu { - sound-dai = <&i2s2_2ch>; - }; - simple-audio-card,codec { - sound-dai = <&bt_sco 1>; - }; - }; - - hdmi0_sound: hdmi0-sound { - status = "disabled"; - compatible = "rockchip,hdmi"; - rockchip,mclk-fs = <128>; - rockchip,card-name = "rockchip-hdmi0"; - rockchip,cpu = <&i2s5_8ch>; - rockchip,codec = <&hdmi0>; - rockchip,jack-det; - }; - - hdmi1_sound: hdmi1-sound { - status = "disabled"; - compatible = "rockchip,hdmi"; - rockchip,mclk-fs = <128>; - rockchip,card-name = "rockchip-hdmi1"; - rockchip,cpu = <&i2s6_8ch>; - rockchip,codec = <&hdmi1>; - rockchip,jack-det; - }; - - dp0_sound: dp0-sound { - status = "disabled"; - compatible = "rockchip,hdmi"; - rockchip,card-name= "rockchip-dp0"; - rockchip,mclk-fs = <512>; - rockchip,cpu = <&spdif_tx2>; - rockchip,codec = <&dp0 1>; - rockchip,jack-det; - }; - - dp1_sound: dp1-sound { - status = "disabled"; - compatible = "rockchip,hdmi"; - rockchip,card-name= "rockchip-dp1"; - rockchip,mclk-fs = <512>; - rockchip,cpu = <&spdif_tx5>; - rockchip,codec = <&dp1 1>; - rockchip,jack-det; - }; - - leds: leds { - compatible = "gpio-leds"; - work_led: work { - gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - spdif_tx0_dc: spdif-tx0-dc { - status = "disabled"; - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - spdif_tx0_sound: spdif-tx0-sound { - status = "disabled"; - compatible = "simple-audio-card"; - simple-audio-card,mclk-fs = <128>; - simple-audio-card,name = "rockchip,spdif-tx0"; - simple-audio-card,cpu { - sound-dai = <&spdif_tx0>; - }; - simple-audio-card,codec { - sound-dai = <&spdif_tx0_dc>; - }; - }; - - spdif_tx1_dc: spdif-tx1-dc { - status = "disabled"; - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - spdif_tx1_sound: spdif-tx1-sound { - status = "disabled"; - compatible = "simple-audio-card"; - simple-audio-card,mclk-fs = <128>; - simple-audio-card,name = "rockchip,spdif-tx1"; - simple-audio-card,cpu { - sound-dai = <&spdif_tx1>; - }; - simple-audio-card,codec { - sound-dai = <&spdif_tx1_dc>; - }; - }; - - test-power { - status = "okay"; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usbdcin: vcc5v0-usbdcin { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usbdcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usbdcin>; - }; -}; - -&av1d_mmu { - status = "okay"; -}; - -&avsd { - status = "okay"; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&dsi0 { - status = "disabled"; - //rockchip,lane-rate = <1000>; - dsi0_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight>; - reset-delay-ms = <10>; - enable-delay-ms = <10>; - prepare-delay-ms = <10>; - unprepare-delay-ms = <10>; - disable-delay-ms = <60>; - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | - MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - panel-init-sequence = [ - 23 00 02 FE 21 - 23 00 02 04 00 - 23 00 02 00 64 - 23 00 02 2A 00 - 23 00 02 26 64 - 23 00 02 54 00 - 23 00 02 50 64 - 23 00 02 7B 00 - 23 00 02 77 64 - 23 00 02 A2 00 - 23 00 02 9D 64 - 23 00 02 C9 00 - 23 00 02 C5 64 - 23 00 02 01 71 - 23 00 02 27 71 - 23 00 02 51 71 - 23 00 02 78 71 - 23 00 02 9E 71 - 23 00 02 C6 71 - 23 00 02 02 89 - 23 00 02 28 89 - 23 00 02 52 89 - 23 00 02 79 89 - 23 00 02 9F 89 - 23 00 02 C7 89 - 23 00 02 03 9E - 23 00 02 29 9E - 23 00 02 53 9E - 23 00 02 7A 9E - 23 00 02 A0 9E - 23 00 02 C8 9E - 23 00 02 09 00 - 23 00 02 05 B0 - 23 00 02 31 00 - 23 00 02 2B B0 - 23 00 02 5A 00 - 23 00 02 55 B0 - 23 00 02 80 00 - 23 00 02 7C B0 - 23 00 02 A7 00 - 23 00 02 A3 B0 - 23 00 02 CE 00 - 23 00 02 CA B0 - 23 00 02 06 C0 - 23 00 02 2D C0 - 23 00 02 56 C0 - 23 00 02 7D C0 - 23 00 02 A4 C0 - 23 00 02 CB C0 - 23 00 02 07 CF - 23 00 02 2F CF - 23 00 02 58 CF - 23 00 02 7E CF - 23 00 02 A5 CF - 23 00 02 CC CF - 23 00 02 08 DD - 23 00 02 30 DD - 23 00 02 59 DD - 23 00 02 7F DD - 23 00 02 A6 DD - 23 00 02 CD DD - 23 00 02 0E 15 - 23 00 02 0A E9 - 23 00 02 36 15 - 23 00 02 32 E9 - 23 00 02 5F 15 - 23 00 02 5B E9 - 23 00 02 85 15 - 23 00 02 81 E9 - 23 00 02 AD 15 - 23 00 02 A9 E9 - 23 00 02 D3 15 - 23 00 02 CF E9 - 23 00 02 0B 14 - 23 00 02 33 14 - 23 00 02 5C 14 - 23 00 02 82 14 - 23 00 02 AA 14 - 23 00 02 D0 14 - 23 00 02 0C 36 - 23 00 02 34 36 - 23 00 02 5D 36 - 23 00 02 83 36 - 23 00 02 AB 36 - 23 00 02 D1 36 - 23 00 02 0D 6B - 23 00 02 35 6B - 23 00 02 5E 6B - 23 00 02 84 6B - 23 00 02 AC 6B - 23 00 02 D2 6B - 23 00 02 13 5A - 23 00 02 0F 94 - 23 00 02 3B 5A - 23 00 02 37 94 - 23 00 02 64 5A - 23 00 02 60 94 - 23 00 02 8A 5A - 23 00 02 86 94 - 23 00 02 B2 5A - 23 00 02 AE 94 - 23 00 02 D8 5A - 23 00 02 D4 94 - 23 00 02 10 D1 - 23 00 02 38 D1 - 23 00 02 61 D1 - 23 00 02 87 D1 - 23 00 02 AF D1 - 23 00 02 D5 D1 - 23 00 02 11 04 - 23 00 02 39 04 - 23 00 02 62 04 - 23 00 02 88 04 - 23 00 02 B0 04 - 23 00 02 D6 04 - 23 00 02 12 05 - 23 00 02 3A 05 - 23 00 02 63 05 - 23 00 02 89 05 - 23 00 02 B1 05 - 23 00 02 D7 05 - 23 00 02 18 AA - 23 00 02 14 36 - 23 00 02 42 AA - 23 00 02 3D 36 - 23 00 02 69 AA - 23 00 02 65 36 - 23 00 02 8F AA - 23 00 02 8B 36 - 23 00 02 B7 AA - 23 00 02 B3 36 - 23 00 02 DD AA - 23 00 02 D9 36 - 23 00 02 15 74 - 23 00 02 3F 74 - 23 00 02 66 74 - 23 00 02 8C 74 - 23 00 02 B4 74 - 23 00 02 DA 74 - 23 00 02 16 9F - 23 00 02 40 9F - 23 00 02 67 9F - 23 00 02 8D 9F - 23 00 02 B5 9F - 23 00 02 DB 9F - 23 00 02 17 DC - 23 00 02 41 DC - 23 00 02 68 DC - 23 00 02 8E DC - 23 00 02 B6 DC - 23 00 02 DC DC - 23 00 02 1D FF - 23 00 02 19 03 - 23 00 02 47 FF - 23 00 02 43 03 - 23 00 02 6E FF - 23 00 02 6A 03 - 23 00 02 94 FF - 23 00 02 90 03 - 23 00 02 BC FF - 23 00 02 B8 03 - 23 00 02 E2 FF - 23 00 02 DE 03 - 23 00 02 1A 35 - 23 00 02 44 35 - 23 00 02 6B 35 - 23 00 02 91 35 - 23 00 02 B9 35 - 23 00 02 DF 35 - 23 00 02 1B 45 - 23 00 02 45 45 - 23 00 02 6C 45 - 23 00 02 92 45 - 23 00 02 BA 45 - 23 00 02 E0 45 - 23 00 02 1C 55 - 23 00 02 46 55 - 23 00 02 6D 55 - 23 00 02 93 55 - 23 00 02 BB 55 - 23 00 02 E1 55 - 23 00 02 22 FF - 23 00 02 1E 68 - 23 00 02 4C FF - 23 00 02 48 68 - 23 00 02 73 FF - 23 00 02 6F 68 - 23 00 02 99 FF - 23 00 02 95 68 - 23 00 02 C1 FF - 23 00 02 BD 68 - 23 00 02 E7 FF - 23 00 02 E3 68 - 23 00 02 1F 7E - 23 00 02 49 7E - 23 00 02 70 7E - 23 00 02 96 7E - 23 00 02 BE 7E - 23 00 02 E4 7E - 23 00 02 20 97 - 23 00 02 4A 97 - 23 00 02 71 97 - 23 00 02 97 97 - 23 00 02 BF 97 - 23 00 02 E5 97 - 23 00 02 21 B5 - 23 00 02 4B B5 - 23 00 02 72 B5 - 23 00 02 98 B5 - 23 00 02 C0 B5 - 23 00 02 E6 B5 - 23 00 02 25 F0 - 23 00 02 23 E8 - 23 00 02 4F F0 - 23 00 02 4D E8 - 23 00 02 76 F0 - 23 00 02 74 E8 - 23 00 02 9C F0 - 23 00 02 9A E8 - 23 00 02 C4 F0 - 23 00 02 C2 E8 - 23 00 02 EA F0 - 23 00 02 E8 E8 - 23 00 02 24 FF - 23 00 02 4E FF - 23 00 02 75 FF - 23 00 02 9B FF - 23 00 02 C3 FF - 23 00 02 E9 FF - 23 00 02 FE 3D - 23 00 02 00 04 - 23 00 02 FE 23 - 23 00 02 08 82 - 23 00 02 0A 00 - 23 00 02 0B 00 - 23 00 02 0C 01 - 23 00 02 16 00 - 23 00 02 18 02 - 23 00 02 1B 04 - 23 00 02 19 04 - 23 00 02 1C 81 - 23 00 02 1F 00 - 23 00 02 20 03 - 23 00 02 23 04 - 23 00 02 21 01 - 23 00 02 54 63 - 23 00 02 55 54 - 23 00 02 6E 45 - 23 00 02 6D 36 - 23 00 02 FE 3D - 23 00 02 55 78 - 23 00 02 FE 20 - 23 00 02 26 30 - 23 00 02 FE 3D - 23 00 02 20 71 - 23 00 02 50 8F - 23 00 02 51 8F - 23 00 02 FE 00 - 23 00 02 35 00 - 05 78 01 11 - 05 00 01 29 - ]; - - panel-exit-sequence = [ - 05 00 01 28 - 05 00 01 10 - ]; - - disp_timings0: display-timings { - native-mode = <&dsi0_timing0>; - dsi0_timing0: timing0 { - clock-frequency = <132000000>; - hactive = <1080>; - vactive = <1920>; - hfront-porch = <15>; - hsync-len = <4>; - hback-porch = <30>; - vfront-porch = <15>; - vsync-len = <2>; - vback-porch = <15>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - panel_in_dsi: endpoint { - remote-endpoint = <&dsi_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi>; - }; - }; - }; - -}; - -&dsi1 { - status = "disabled"; - //rockchip,lane-rate = <1000>; - dsi1_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight>; - reset-delay-ms = <10>; - enable-delay-ms = <10>; - prepare-delay-ms = <10>; - unprepare-delay-ms = <10>; - disable-delay-ms = <10>; - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | - MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - panel-init-sequence = [ - 23 00 02 FE 21 - 23 00 02 04 00 - 23 00 02 00 64 - 23 00 02 2A 00 - 23 00 02 26 64 - 23 00 02 54 00 - 23 00 02 50 64 - 23 00 02 7B 00 - 23 00 02 77 64 - 23 00 02 A2 00 - 23 00 02 9D 64 - 23 00 02 C9 00 - 23 00 02 C5 64 - 23 00 02 01 71 - 23 00 02 27 71 - 23 00 02 51 71 - 23 00 02 78 71 - 23 00 02 9E 71 - 23 00 02 C6 71 - 23 00 02 02 89 - 23 00 02 28 89 - 23 00 02 52 89 - 23 00 02 79 89 - 23 00 02 9F 89 - 23 00 02 C7 89 - 23 00 02 03 9E - 23 00 02 29 9E - 23 00 02 53 9E - 23 00 02 7A 9E - 23 00 02 A0 9E - 23 00 02 C8 9E - 23 00 02 09 00 - 23 00 02 05 B0 - 23 00 02 31 00 - 23 00 02 2B B0 - 23 00 02 5A 00 - 23 00 02 55 B0 - 23 00 02 80 00 - 23 00 02 7C B0 - 23 00 02 A7 00 - 23 00 02 A3 B0 - 23 00 02 CE 00 - 23 00 02 CA B0 - 23 00 02 06 C0 - 23 00 02 2D C0 - 23 00 02 56 C0 - 23 00 02 7D C0 - 23 00 02 A4 C0 - 23 00 02 CB C0 - 23 00 02 07 CF - 23 00 02 2F CF - 23 00 02 58 CF - 23 00 02 7E CF - 23 00 02 A5 CF - 23 00 02 CC CF - 23 00 02 08 DD - 23 00 02 30 DD - 23 00 02 59 DD - 23 00 02 7F DD - 23 00 02 A6 DD - 23 00 02 CD DD - 23 00 02 0E 15 - 23 00 02 0A E9 - 23 00 02 36 15 - 23 00 02 32 E9 - 23 00 02 5F 15 - 23 00 02 5B E9 - 23 00 02 85 15 - 23 00 02 81 E9 - 23 00 02 AD 15 - 23 00 02 A9 E9 - 23 00 02 D3 15 - 23 00 02 CF E9 - 23 00 02 0B 14 - 23 00 02 33 14 - 23 00 02 5C 14 - 23 00 02 82 14 - 23 00 02 AA 14 - 23 00 02 D0 14 - 23 00 02 0C 36 - 23 00 02 34 36 - 23 00 02 5D 36 - 23 00 02 83 36 - 23 00 02 AB 36 - 23 00 02 D1 36 - 23 00 02 0D 6B - 23 00 02 35 6B - 23 00 02 5E 6B - 23 00 02 84 6B - 23 00 02 AC 6B - 23 00 02 D2 6B - 23 00 02 13 5A - 23 00 02 0F 94 - 23 00 02 3B 5A - 23 00 02 37 94 - 23 00 02 64 5A - 23 00 02 60 94 - 23 00 02 8A 5A - 23 00 02 86 94 - 23 00 02 B2 5A - 23 00 02 AE 94 - 23 00 02 D8 5A - 23 00 02 D4 94 - 23 00 02 10 D1 - 23 00 02 38 D1 - 23 00 02 61 D1 - 23 00 02 87 D1 - 23 00 02 AF D1 - 23 00 02 D5 D1 - 23 00 02 11 04 - 23 00 02 39 04 - 23 00 02 62 04 - 23 00 02 88 04 - 23 00 02 B0 04 - 23 00 02 D6 04 - 23 00 02 12 05 - 23 00 02 3A 05 - 23 00 02 63 05 - 23 00 02 89 05 - 23 00 02 B1 05 - 23 00 02 D7 05 - 23 00 02 18 AA - 23 00 02 14 36 - 23 00 02 42 AA - 23 00 02 3D 36 - 23 00 02 69 AA - 23 00 02 65 36 - 23 00 02 8F AA - 23 00 02 8B 36 - 23 00 02 B7 AA - 23 00 02 B3 36 - 23 00 02 DD AA - 23 00 02 D9 36 - 23 00 02 15 74 - 23 00 02 3F 74 - 23 00 02 66 74 - 23 00 02 8C 74 - 23 00 02 B4 74 - 23 00 02 DA 74 - 23 00 02 16 9F - 23 00 02 40 9F - 23 00 02 67 9F - 23 00 02 8D 9F - 23 00 02 B5 9F - 23 00 02 DB 9F - 23 00 02 17 DC - 23 00 02 41 DC - 23 00 02 68 DC - 23 00 02 8E DC - 23 00 02 B6 DC - 23 00 02 DC DC - 23 00 02 1D FF - 23 00 02 19 03 - 23 00 02 47 FF - 23 00 02 43 03 - 23 00 02 6E FF - 23 00 02 6A 03 - 23 00 02 94 FF - 23 00 02 90 03 - 23 00 02 BC FF - 23 00 02 B8 03 - 23 00 02 E2 FF - 23 00 02 DE 03 - 23 00 02 1A 35 - 23 00 02 44 35 - 23 00 02 6B 35 - 23 00 02 91 35 - 23 00 02 B9 35 - 23 00 02 DF 35 - 23 00 02 1B 45 - 23 00 02 45 45 - 23 00 02 6C 45 - 23 00 02 92 45 - 23 00 02 BA 45 - 23 00 02 E0 45 - 23 00 02 1C 55 - 23 00 02 46 55 - 23 00 02 6D 55 - 23 00 02 93 55 - 23 00 02 BB 55 - 23 00 02 E1 55 - 23 00 02 22 FF - 23 00 02 1E 68 - 23 00 02 4C FF - 23 00 02 48 68 - 23 00 02 73 FF - 23 00 02 6F 68 - 23 00 02 99 FF - 23 00 02 95 68 - 23 00 02 C1 FF - 23 00 02 BD 68 - 23 00 02 E7 FF - 23 00 02 E3 68 - 23 00 02 1F 7E - 23 00 02 49 7E - 23 00 02 70 7E - 23 00 02 96 7E - 23 00 02 BE 7E - 23 00 02 E4 7E - 23 00 02 20 97 - 23 00 02 4A 97 - 23 00 02 71 97 - 23 00 02 97 97 - 23 00 02 BF 97 - 23 00 02 E5 97 - 23 00 02 21 B5 - 23 00 02 4B B5 - 23 00 02 72 B5 - 23 00 02 98 B5 - 23 00 02 C0 B5 - 23 00 02 E6 B5 - 23 00 02 25 F0 - 23 00 02 23 E8 - 23 00 02 4F F0 - 23 00 02 4D E8 - 23 00 02 76 F0 - 23 00 02 74 E8 - 23 00 02 9C F0 - 23 00 02 9A E8 - 23 00 02 C4 F0 - 23 00 02 C2 E8 - 23 00 02 EA F0 - 23 00 02 E8 E8 - 23 00 02 24 FF - 23 00 02 4E FF - 23 00 02 75 FF - 23 00 02 9B FF - 23 00 02 C3 FF - 23 00 02 E9 FF - 23 00 02 FE 3D - 23 00 02 00 04 - 23 00 02 FE 23 - 23 00 02 08 82 - 23 00 02 0A 00 - 23 00 02 0B 00 - 23 00 02 0C 01 - 23 00 02 16 00 - 23 00 02 18 02 - 23 00 02 1B 04 - 23 00 02 19 04 - 23 00 02 1C 81 - 23 00 02 1F 00 - 23 00 02 20 03 - 23 00 02 23 04 - 23 00 02 21 01 - 23 00 02 54 63 - 23 00 02 55 54 - 23 00 02 6E 45 - 23 00 02 6D 36 - 23 00 02 FE 3D - 23 00 02 55 78 - 23 00 02 FE 20 - 23 00 02 26 30 - 23 00 02 FE 3D - 23 00 02 20 71 - 23 00 02 50 8F - 23 00 02 51 8F - 23 00 02 FE 00 - 23 00 02 35 00 - 05 78 01 11 - 05 00 01 29 - ]; - - panel-exit-sequence = [ - 05 00 01 28 - 05 00 01 10 - ]; - - disp_timings1: display-timings { - native-mode = <&dsi1_timing0>; - dsi1_timing0: timing0 { - clock-frequency = <132000000>; - hactive = <1080>; - vactive = <1920>; - hfront-porch = <15>; - hsync-len = <4>; - hback-porch = <30>; - vfront-porch = <15>; - vsync-len = <2>; - vback-porch = <15>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - panel_in_dsi1: endpoint { - remote-endpoint = <&dsi1_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi1_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi1>; - }; - }; - }; - -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - mem-supply = <&vdd_gpu_mem_s0>; - status = "okay"; -}; - -&i2s0_8ch { - status = "okay"; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; -}; - -&i2s2_2ch { - pinctrl-0 = <&i2s2m1_lrck &i2s2m1_sclk &i2s2m1_sdi &i2s2m1_sdo>; - rockchip,bclk-fs = <32>; - status = "disabled"; -}; - -&iep { - status = "okay"; -}; - -&iep_mmu { - status = "okay"; -}; - -&jpegd { - status = "okay"; -}; - -&jpegd_mmu { - status = "okay"; -}; - -&jpege_ccu { - status = "okay"; -}; - -&jpege0 { - status = "okay"; -}; - -&jpege0_mmu { - status = "okay"; -}; - -&jpege1 { - status = "okay"; -}; - -&jpege1_mmu { - status = "okay"; -}; - -&jpege2 { - status = "okay"; -}; - -&jpege2_mmu { - status = "okay"; -}; - -&jpege3 { - status = "okay"; -}; - -&jpege3_mmu { - status = "okay"; -}; - -&mpp_srv { - status = "okay"; -}; - -&rga3_core0 { - status = "okay"; -}; - -&rga3_0_mmu { - status = "okay"; -}; - -&rga3_core1 { - status = "okay"; -}; - -&rga3_1_mmu { - status = "okay"; -}; - -&rga2 { - status = "okay"; -}; - -&rknpu { - rknpu-supply = <&vdd_npu_s0>; - mem-supply = <&vdd_npu_mem_s0>; - status = "okay"; -}; - -&rknpu_mmu { - status = "okay"; -}; - -&rkvdec_ccu { - status = "okay"; -}; - -&rkvdec0 { - status = "okay"; -}; - -&rkvdec0_mmu { - status = "okay"; -}; - -&rkvdec1 { - status = "okay"; -}; - -&rkvdec1_mmu { - status = "okay"; -}; - -&rkvenc_ccu { - status = "okay"; -}; - -&rkvenc0 { - venc-supply = <&vdd_vdenc_s0>; - mem-supply = <&vdd_vdenc_mem_s0>; - status = "okay"; -}; - -&rkvenc0_mmu { - status = "okay"; -}; - -&rkvenc1 { - venc-supply = <&vdd_vdenc_s0>; - mem-supply = <&vdd_vdenc_mem_s0>; - status = "okay"; -}; - -&rkvenc1_mmu { - status = "okay"; -}; - -&rockchip_suspend { - status = "okay"; - rockchip,sleep-debug-en = <1>; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc_1v8_s0>; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - max-frequency = <200000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - full-pwr-cycle-in-suspend; - status = "okay"; -}; - -&sdmmc { - max-frequency = <150000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - sd-uhs-sdr104; - vqmmc-supply = <&vccio_sd_s0>; - status = "disabled"; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy1 { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&u2phy1_otg { - status = "okay"; -}; - -&u2phy2_host { - status = "okay"; -}; - -&u2phy3_host { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdp_phy0 { - status = "okay"; -}; - -&usbdp_phy0_dp { - status = "okay"; -}; - -&usbdp_phy0_u3 { - status = "okay"; -}; - -&usbdp_phy1 { - status = "okay"; -}; - -&usbdp_phy1_dp { - status = "okay"; -}; - -&usbdp_phy1_u3 { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - status = "okay"; -}; - -&usbhost3_0 { - status = "okay"; -}; - -&usbhost_dwc3_0 { - status = "okay"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; -}; - -&vdpu { - status = "okay"; -}; - -&vdpu_mmu { - status = "okay"; -}; - -&vepu { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -/* vp0 & vp1 splice for 8K output */ -&vp0 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; - rockchip,primary-plane = ; -}; - -&vp1 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; - rockchip,primary-plane = ; -}; - -&vp2 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; - rockchip,primary-plane = ; -}; - -&vp3 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; - rockchip,primary-plane = ; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-cam-6x.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb1-cam-6x.dtsi deleted file mode 100644 index d8f174442..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-cam-6x.dtsi +++ /dev/null @@ -1,766 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -&csi2_dcphy0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_ucam0: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx464_out0>; - data-lanes = <1 2>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidcphy0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi0_csi2_input>; - }; - }; - }; -}; - -&csi2_dcphy1 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_ucam1: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx464_out1>; - data-lanes = <1 2>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidcphy1_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi1_csi2_input>; - }; - }; - }; -}; - -&csi2_dphy0_hw { - status = "okay"; -}; - -&csi2_dphy1_hw { - status = "okay"; -}; - -&csi2_dphy1 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_ucam2: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx464_out2>; - data-lanes = <1 2>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy1_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi2_csi2_input>; - }; - }; - }; -}; - -&csi2_dphy2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_ucam3: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx464_out3>; - data-lanes = <1 2>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy2_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi3_csi2_input>; - }; - }; - }; -}; - -&csi2_dphy4 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_ucam4: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx464_out4>; - data-lanes = <1 2>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy4_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi4_csi2_input>; - }; - }; - }; -}; - -&csi2_dphy5 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_ucam5: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx464_out5>; - data-lanes = <1 2>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy5_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi5_csi2_input>; - }; - }; - }; -}; - -&i2c3 { - status = "okay"; - - /* module 77/79 0x1a 78/80 0x36 */ - imx464_2: imx464-2@1a { - compatible = "sony,imx464"; - status = "okay"; - reg = <0x1a>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - pinctrl-names = "default"; - pinctrl-0 = <&mipim0_camera3_clk>; - avdd-supply = <&vcc_mipicsi0>; - pwdn-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT1980-PX1"; - rockchip,camera-module-lens-name = "SHG102"; - port { - imx464_out2: endpoint { - remote-endpoint = <&mipi_in_ucam2>; - data-lanes = <1 2>; - }; - }; - }; - - imx464_3: imx464-3@36 { - compatible = "sony,imx464"; - status = "okay"; - reg = <0x36>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - avdd-supply = <&vcc_mipicsi0>; - pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <3>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT1980-PX1"; - rockchip,camera-module-lens-name = "SHG102"; - port { - imx464_out3: endpoint { - remote-endpoint = <&mipi_in_ucam3>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&i2c4 { - status = "okay"; - pinctrl-0 = <&i2c4m3_xfer>; - - /* 77/79 0x1a 78/80 0x36 */ - imx464_4: imx464-4@1a { - compatible = "sony,imx464"; - status = "okay"; - reg = <0x1a>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - pinctrl-names = "default"; - pinctrl-0 = <&mipim0_camera4_clk>; - avdd-supply = <&vcc_mipicsi1>; - pwdn-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT1980-PX1"; - rockchip,camera-module-lens-name = "SHG102"; - port { - imx464_out4: endpoint { - remote-endpoint = <&mipi_in_ucam4>; - data-lanes = <1 2>; - }; - }; - }; - - imx464_5: imx464-5@36 { - compatible = "sony,imx464"; - status = "okay"; - reg = <0x36>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - avdd-supply = <&vcc_mipicsi1>; - pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT1980-PX1"; - rockchip,camera-module-lens-name = "SHG102"; - port { - imx464_out5: endpoint { - remote-endpoint = <&mipi_in_ucam5>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; - - /* 77/79 0x1a 78/80 0x36 */ - imx464_0: imx464-0@1a { - compatible = "sony,imx464"; - status = "okay"; - reg = <0x1a>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - pwdn-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipim0_camera1_clk>; - avdd-supply = <&vcc_mipidcphy0>; - rockchip,camera-module-index = <4>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT1980-PX1"; - rockchip,camera-module-lens-name = "SHG102"; - port { - imx464_out0: endpoint { - remote-endpoint = <&mipi_in_ucam0>; - data-lanes = <1 2>; - }; - }; - }; - - imx464_1: imx464-1@36 { - compatible = "sony,imx464"; - status = "okay"; - reg = <0x36>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - pinctrl-names = "default"; - pinctrl-0 = <&mipim0_camera2_clk>; - pwdn-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; - avdd-supply = <&vcc_mipidcphy0>; - rockchip,camera-module-index = <5>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT1980-PX1"; - rockchip,camera-module-lens-name = "SHG102"; - port { - imx464_out1: endpoint { - remote-endpoint = <&mipi_in_ucam1>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&mipi_dcphy1 { - status = "okay"; -}; - -&mipi0_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidcphy0_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in0>; - }; - }; - }; -}; - -&mipi1_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi1_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidcphy1_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi1_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in1>; - }; - }; - }; -}; - -&mipi2_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy1_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in2>; - }; - }; - }; -}; - -&mipi3_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi3_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy2_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi3_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in3>; - }; - }; - }; -}; - -&mipi4_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi4_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy4_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi4_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in4>; - }; - }; - }; -}; - -&mipi5_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi5_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy5_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi5_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in5>; - }; - }; - }; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds { - status = "okay"; - - port { - cif_mipi_in0: endpoint { - remote-endpoint = <&mipi0_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds_sditf { - status = "okay"; - - port { - mipi_lvds_sditf: endpoint { - remote-endpoint = <&isp0_vir0>; - }; - }; -}; - -&rkcif_mipi_lvds1 { - status = "okay"; - - port { - cif_mipi_in1: endpoint { - remote-endpoint = <&mipi1_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds1_sditf { - status = "okay"; - - port { - mipi1_lvds_sditf: endpoint { - remote-endpoint = <&isp1_vir0>; - }; - }; -}; - -&rkcif_mipi_lvds2 { - status = "okay"; - - port { - cif_mipi_in2: endpoint { - remote-endpoint = <&mipi2_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds2_sditf { - status = "okay"; - - port { - mipi2_lvds_sditf: endpoint { - remote-endpoint = <&isp0_vir1>; - }; - }; -}; - -&rkcif_mipi_lvds3 { - status = "okay"; - - port { - cif_mipi_in3: endpoint { - remote-endpoint = <&mipi3_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds3_sditf { - status = "okay"; - - port { - mipi3_lvds_sditf: endpoint { - remote-endpoint = <&isp1_vir1>; - }; - }; -}; - -&rkcif_mipi_lvds4 { - status = "okay"; - - port { - cif_mipi_in4: endpoint { - remote-endpoint = <&mipi4_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds4_sditf { - status = "okay"; - - port { - mipi4_lvds_sditf: endpoint { - remote-endpoint = <&isp0_vir2>; - }; - }; -}; - -&rkcif_mipi_lvds5 { - status = "okay"; - - port { - cif_mipi_in5: endpoint { - remote-endpoint = <&mipi5_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds5_sditf { - status = "okay"; - - port { - mipi5_lvds_sditf: endpoint { - remote-endpoint = <&isp1_vir2>; - }; - }; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp0 { - status = "okay"; -}; - -&isp0_mmu { - status = "okay"; -}; - -&rkisp0_vir0 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds_sditf>; - }; - }; -}; - -&rkisp0_vir1 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir1: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi2_lvds_sditf>; - }; - }; -}; - -&rkisp0_vir2 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir2: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi4_lvds_sditf>; - }; - }; -}; - -&rkisp1 { - status = "okay"; -}; - -&isp1_mmu { - status = "okay"; -}; - -&rkisp1_vir0 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp1_vir0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi1_lvds_sditf>; - }; - }; -}; - -&rkisp1_vir1 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp1_vir1: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi3_lvds_sditf>; - }; - }; -}; - - -&rkisp1_vir2 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp1_vir2: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi5_lvds_sditf>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-imx415.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb1-imx415.dtsi deleted file mode 100644 index abf2eb06a..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-imx415.dtsi +++ /dev/null @@ -1,158 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/ { - cam_ircut0: cam_ircut { - status = "okay"; - compatible = "rockchip,ircut"; - ircut-open-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; - ircut-close-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - }; -}; - -&csi2_dcphy0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_ucam0: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx415_out0>; - data-lanes = <1 2 3 4>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidcphy0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi0_csi2_input>; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; - - imx415: imx415@1a { - compatible = "sony,imx415"; - reg = <0x1a>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; - clock-names = "xvclk"; - pinctrl-names = "default"; - pinctrl-0 = <&mipim0_camera1_clk>; - power-domains = <&power RK3588_PD_VI>; - pwdn-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; - avdd-supply = <&vcc_mipidcphy0>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT2022-PX1"; - rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; - lens-focus = <&cam_ircut0>; - port { - imx415_out0: endpoint { - remote-endpoint = <&mipi_in_ucam0>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&mipi0_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidcphy0_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in0>; - }; - }; - }; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds { - status = "okay"; - - port { - cif_mipi_in0: endpoint { - remote-endpoint = <&mipi0_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds_sditf { - status = "okay"; - - port { - mipi_lvds_sditf: endpoint { - remote-endpoint = <&isp0_vir0>; - }; - }; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp0 { - status = "okay"; -}; - -&isp0_mmu { - status = "okay"; -}; - -&rkisp0_vir0 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds_sditf>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-dsi-dsc-MV2100UZ1.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-dsi-dsc-MV2100UZ1.dts deleted file mode 100644 index 4e48b928f..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-dsi-dsc-MV2100UZ1.dts +++ /dev/null @@ -1,200 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-evb1-lp4.dtsi" -#include "rk3588-evb1-imx415.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588 EVB1 LP4 V10 Board + DSI DSC PANEL MV2100UZ1 DISPLAY Ext Board"; - compatible = "rockchip,rk3588-evb1-lp4-v10-dsi-dsc-MV2100UZ1", "rockchip,rk3588"; -}; - -&backlight { - status = "okay"; - default-brightness-level = <20>; -}; - -&dsi0 { - status = "okay"; - rockchip,lane-rate = <1200000>; - - dsi0_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight>; - reset-delay-ms = <50>; - enable-delay-ms = <50>; - init-delay-ms = <20>; - prepare-delay-ms = <50>; - unprepare-delay-ms = <20>; - disable-delay-ms = <20>; - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST)>; - - dsi,format = ; - dsi,lanes = <4>; - - compressed-data; - slice-width = <1140>; - slice-height = <2280>; - version-major = <1>; - version-minor = <1>; - - panel-init-sequence = [ - /* PPS Setting */ - 0A 00 58 11 00 00 89 30 80 08 E8 08 E8 08 E8 04 74 04 74 02 00 03 C9 00 20 F7 C5 00 0F 00 0F 00 0E 00 06 18 00 10 F0 03 0C 20 00 06 0B 0B 33 0E 1C 2A 38 46 54 62 69 70 77 79 7B 7D 7E 01 02 01 00 09 40 09 BE 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6 2A F6 2B 34 2B 74 3B 74 6B F4 - 39 00 02 FF 20 - 39 00 02 E0 10 - 39 00 02 7A 07 - 39 00 02 7D 0C - 39 00 02 7E 0C - 39 00 02 FB 01 - - 39 00 02 FF E0 - 39 00 02 66 00 - 39 00 02 23 07 - 39 00 02 FB 01 - - /* CMD2 page 5 */ - 39 00 02 FF 25 - - /* OSC TRACE for MIPI H 4.748us */ - 39 00 02 2F 20 - 39 00 02 0D 07 - 39 00 02 0E 6B - 39 00 02 11 11 - 39 00 02 13 00 - 39 00 02 14 01 - 39 00 02 25 20 - 39 00 02 0F 09 - 39 00 02 10 A5 - 39 00 02 12 17 - 39 00 02 15 01 - 39 00 02 0C 01 - 39 00 02 09 10 - 39 00 02 38 03 - 39 00 02 0A 00 - 39 00 02 07 02 - - /* MIPI VFP */ - 39 00 02 BC FF - 39 00 02 BD FF - 39 00 02 BE FF - 39 00 02 BF FF - 39 00 02 C0 FF - 39 00 02 C1 FF - 39 00 02 C2 FF - 39 00 02 C3 FF - - 39 00 02 FB 01 - - 39 00 02 FF 10 - 39 00 05 2A 00 00 08 E7 - 39 00 05 2B 00 00 08 E7 - 39 00 02 03 01 - 39 00 02 BB 13 - 39 00 02 C0 03 - 39 00 11 C1 89 28 08 E8 F2 00 03 C9 F7 C5 00 0F 00 0E 00 06 - 39 00 03 C2 10 F0 - 39 00 02 35 00 - 39 00 03 44 00 00 - 39 00 02 51 FF - 39 00 02 53 24 - 39 00 02 FB 01 - - 15 64 01 11 - 15 14 01 29 - ]; - - panel-exit-sequence = [ - 05 00 01 28 - 05 00 01 10 - ]; - - disp_timings0: display-timings { - native-mode = <&dsi0_timing0>; - dsi0_timing0: timing0 { - clock-frequency = <506000000>; - hactive = <2280>; - vactive = <2280>; - hfront-porch = <52>; - hsync-len = <20>; - hback-porch = <52>; - vfront-porch = <44>; - vsync-len = <2>; - vback-porch = <14>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - panel_in_dsi: endpoint { - remote-endpoint = <&dsi_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi>; - }; - }; - }; -}; - -&dp0 { - status = "disabled"; -}; - -&dp1 { - status = "disabled"; -}; - -&dp0_in_vp2 { - status = "disabled"; -}; - -&dp1_in_vp2 { - status = "disabled"; -}; - -&dsi0_in_vp2 { - status = "okay"; -}; - -&dsi0_in_vp3 { - status = "disabled"; -}; - -&dsi1_in_vp2 { - status = "disabled"; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp2_out_dsi0>; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-ipc-6x-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-ipc-6x-linux.dts deleted file mode 100644 index 2dcef191f..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-ipc-6x-linux.dts +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-evb1-lp4.dtsi" -#include "rk3588-ipc.dtsi" -#include "rk3588-evb1-cam-6x.dtsi" - -/ { - model = "Rockchip RK3588 EVB1 LP4 V10 Board"; - compatible = "rockchip,rk3588-evb1-lp4-v10", "rockchip,rk3588"; -}; - -&backlight { - status = "disabled"; -}; - -&combphy0_ps { - status = "disabled"; -}; - -&combphy1_ps { - status = "disabled"; -}; - -&combphy2_psu { - status = "disabled"; -}; - -&dp0 { - status = "disabled"; -}; - -&dp0_in_vp2 { - status = "disabled"; -}; - -&dp1 { - status = "disabled"; -}; - -&dp1_in_vp2 { - status = "disabled"; -}; - -&dsi0 { - status = "disabled"; -}; - -&dsi0_in_vp3 { - status = "disabled"; -}; - -&dsi0_panel { - status = "disabled"; -}; - -&dsi1_panel { - status = "disabled"; -}; - ->1x { - status = "disabled"; -}; - -&hdmi1 { - status = "disabled"; -}; - -&hdmi1_in_vp1 { - status = "disabled"; -}; - -&hdmi1_sound { - status = "disabled"; -}; - -&hdptxphy_hdmi1 { - status = "disabled"; -}; - -&i2c6 { - status = "disabled"; -}; - -&i2s5_8ch { - status = "disabled"; -}; - -&i2s6_8ch { - status = "disabled"; -}; - -&jpegd { - status = "disabled"; -}; - -&jpegd_mmu { - status = "disabled"; -}; - -&leds { - status = "disabled"; -}; - -&pcie2x1l0 { - status = "disabled"; -}; - -&pcie2x1l1 { - status = "disabled"; -}; - -&pcie30phy { - status = "disabled"; -}; - -&pcie3x4 { - status = "disabled"; -}; - -&pwm2 { - status = "disabled"; -}; - -&rkvdec0 { - status = "disabled"; -}; - -&rkvdec0_mmu { - status = "disabled"; -}; - -&rkvdec1_mmu { - status = "disabled"; -}; - -&rkvdec_ccu { - status = "disabled"; -}; - -&rk_headset { - status = "disabled"; -}; - -&sata0 { - status = "disabled"; -}; - -&uart8 { - status = "disabled"; -}; - -&usbdp_phy1 { - status = "disabled"; -}; - -&usbdp_phy1_dp { - status = "disabled"; -}; - -&usbdp_phy1_u3 { - status = "disabled"; -}; - -&usbdrd3_1 { - status = "disabled"; -}; - -&usbdrd_dwc3_1 { - status = "disabled"; -}; - -&usb_host0_ehci { - status = "disabled"; -}; - -&usb_host0_ohci { - status = "disabled"; -}; - -&usb_host1_ehci { - status = "disabled"; -}; - -&usb_host1_ohci { - status = "disabled"; -}; - -&u2phy1 { - status = "disabled"; -}; - -&u2phy1_otg { - status = "disabled"; -}; - -&u2phy2 { - status = "disabled"; -}; - -&u2phy2_host { - status = "disabled"; -}; - -&u2phy3 { - status = "disabled"; -}; - -&u2phy3_host { - status = "disabled"; -}; - -&vdpu { - status = "disabled"; -}; - -&vdpu_mmu { - status = "disabled"; -}; - -&wireless_bluetooth { - status = "disabled"; -}; - -&wireless_wlan { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-linux-ipc.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-linux-ipc.dts deleted file mode 100644 index 20fe7f6b8..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-linux-ipc.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-evb1-lp4.dtsi" -#include "rk3588-evb1-imx415.dtsi" -#include "rk3588-ipc.dtsi" - -/ { - model = "Rockchip RK3588 EVB1 LP4 V10 Board"; - compatible = "rockchip,rk3588-evb1-lp4-v10-linux-ipc", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-linux.dts deleted file mode 100644 index 955fd53c3..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-linux.dts +++ /dev/null @@ -1,46 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-evb1-lp4.dtsi" -#include "rk3588-evb1-imx415.dtsi" -#include "rk3588-linux.dtsi" - -/ { - model = "Rockchip RK3588 EVB1 LP4 V10 Board"; - compatible = "rockchip,rk3588-evb1-lp4-v10", "rockchip,rk3588"; -}; - -&route_hdmi0 { - status = "okay"; - connect = <&vp0_out_hdmi0>; - /delete-property/ force-output; - /delete-node/ force_timing; -}; - -&route_hdmi1 { - status = "okay"; - connect = <&vp1_out_hdmi1>; - /delete-property/ force-output; - /delete-node/ force_timing; -}; - -&vcc_1v8_s0 { - /delete-property/ regulator-state-mem; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; -}; - -&vcc_3v3_s0 { - /delete-property/ regulator-state-mem; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-lt6911uxe.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-lt6911uxe.dts deleted file mode 100644 index d33e2bf44..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-lt6911uxe.dts +++ /dev/null @@ -1,277 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. - * - */ -/dts-v1/; - -#include "rk3588-evb1-lp4.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588 EVB1 LP4 V10 Board + Rockchip RK3588 EVB V10 Extboard"; - compatible = "rockchip,rk3588-evb1-lp4-v10-lt6911uxe", "rockchip,rk3588"; - - vcc_mipicsi0: vcc-mipicsi0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipicsi0_pwr>; - regulator-name = "vcc_mipicsi0"; - enable-active-high; - regulator-boot-on; - regulator-always-on; - }; - - vcc_mipidcphy0: vcc-mipidcphy0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipidcphy0_pwr>; - regulator-name = "vcc_mipidcphy0"; - enable-active-high; - regulator-boot-on; - regulator-always-on; - }; - - ext_cam_clk: external-camera-clock { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "CLK_CAMERA_24MHZ"; - #clock-cells = <0>; - }; -}; - -&csi2_dphy0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - hdmi_mipi2_in: endpoint@1 { - reg = <1>; - remote-endpoint = <<6911uxe_out1>; - data-lanes = <1 2 3 4>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi2_csi2_input>; - }; - }; - }; -}; - -&csi2_dphy0_hw { - status = "okay"; -}; - -&csi2_dcphy0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - hdmi_mipi0_in: endpoint@1 { - reg = <1>; - remote-endpoint = <<6911uxe_out0>; - data-lanes = <1 2 3 4>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidcphy0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi0_csi2_input>; - }; - }; - }; -}; - -&i2c3 { - status = "okay"; - - lt6911uxe_1: lt6911uxe_1@2b { - compatible = "lontium,lt6911uxe"; - status = "okay"; - reg = <0x2b>; - clocks = <&ext_cam_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - pinctrl-names = "default"; - pinctrl-0 = <<6911uxe_pin_1>; - interrupt-parent = <&gpio1>; - interrupts = ; - // reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; - // power-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; - plugin-det-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "HDMI-MIPI2"; - rockchip,camera-module-lens-name = "LT6911UXE-2"; - port { - lt6911uxe_out1: endpoint { - remote-endpoint = <&hdmi_mipi2_in>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; - - lt6911uxe: lt6911uxe@2b { - compatible = "lontium,lt6911uxe"; - status = "okay"; - reg = <0x2b>; - clocks = <&ext_cam_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - pinctrl-names = "default"; - pinctrl-0 = <<6911uxe_pin>; - interrupt-parent = <&gpio1>; - interrupts = ; - // reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; - // power-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; - // plugin-det-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>; - plugin-det-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "front"; - rockchip,camera-module-name = "HDMI-MIPI0"; - rockchip,camera-module-lens-name = "LT6911UXC-0"; - - port { - lt6911uxe_out0: endpoint { - remote-endpoint = <&hdmi_mipi0_in>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&mipi0_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidcphy0_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in0>; - }; - }; - }; -}; - -&mipi2_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy0_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in2>; - }; - }; - }; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds { - status = "okay"; - - port { - cif_mipi_in0: endpoint { - remote-endpoint = <&mipi0_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds2 { - status = "okay"; - - port { - cif_mipi_in2: endpoint { - remote-endpoint = <&mipi2_csi2_output>; - }; - }; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&pinctrl { - hdmiin { - lt6911uxe_pin: lt6911uxe-pin { - rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, - <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - lt6911uxe_pin_1: lt6911uxe-pin-1 { - rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, - <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10.dts deleted file mode 100644 index b053e9205..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-evb1-lp4.dtsi" -#include "rk3588-evb1-imx415.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588 EVB1 LP4 V10 Board"; - compatible = "rockchip,rk3588-evb1-lp4-v10", "rockchip,rk3588"; -}; - -&bt_sco { - status = "okay"; -}; - -&bt_sound { - status = "okay"; -}; - -&i2s2_2ch { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi deleted file mode 100644 index 431a5bbdb..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4.dtsi +++ /dev/null @@ -1,775 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include "dt-bindings/usb/pd.h" -#include "rk3588.dtsi" -#include "rk3588-evb.dtsi" -#include "rk3588-rk806-dual.dtsi" - -/ { - /* If hdmirx node is disabled, delete the reserved-memory node here. */ - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* Reserve 128MB memory for hdmirx-controller@fdee0000 */ - cma { - compatible = "shared-dma-pool"; - reusable; - reg = <0x0 (256 * 0x100000) 0x0 (128 * 0x100000)>; - linux,cma-default; - }; - }; - - es8388_sound: es8388-sound { - status = "okay"; - compatible = "rockchip,multicodecs-card"; - rockchip,card-name = "rockchip-es8388"; - hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; - io-channels = <&saradc 3>; - io-channel-names = "adc-detect"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - spk-con-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; - hp-con-gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - rockchip,format = "i2s"; - rockchip,mclk-fs = <256>; - rockchip,cpu = <&i2s0_8ch>; - rockchip,codec = <&es8388>; - rockchip,audio-routing = - "Headphone", "LOUT1", - "Headphone", "ROUT1", - "Speaker", "LOUT2", - "Speaker", "ROUT2", - "Headphone", "Headphone Power", - "Headphone", "Headphone Power", - "Speaker", "Speaker Power", - "Speaker", "Speaker Power", - "LINPUT1", "Main Mic", - "LINPUT2", "Main Mic", - "RINPUT1", "Headset Mic", - "RINPUT2", "Headset Mic"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - play-pause-key { - label = "playpause"; - linux,code = ; - press-threshold-microvolt = <2000>; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - pwms = <&pwm9 0 50000 0>; - cooling-levels = <0 50 100 150 200 255>; - rockchip,temp-trips = < - 50000 1 - 55000 2 - 60000 3 - 65000 4 - 70000 5 - >; - }; - - hdmiin-sound { - compatible = "rockchip,hdmi"; - rockchip,mclk-fs = <128>; - rockchip,format = "i2s"; - rockchip,bitclock-master = <&hdmirx_ctrler>; - rockchip,frame-master = <&hdmirx_ctrler>; - rockchip,card-name = "rockchip,hdmiin"; - rockchip,cpu = <&i2s7_8ch>; - rockchip,codec = <&hdmirx_ctrler 0>; - rockchip,jack-det; - }; - - pcie20_avdd0v85: pcie20-avdd0v85 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd0v85"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&avdd_0v85_s0>; - }; - - pcie20_avdd1v8: pcie20-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - pcie30_avdd0v75: pcie30-avdd0v75 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v75"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - vin-supply = <&avdd_0v75_s0>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - rk_headset: rk-headset { - status = "disabled"; - compatible = "rockchip_headset"; - headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - io-channels = <&saradc 3>; - }; - - vbus5v0_typec: vbus5v0-typec { - compatible = "regulator-fixed"; - regulator-name = "vbus5v0_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; - }; - - vcc3v3_lcd_n: vcc3v3-lcd0-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd0_n"; - regulator-boot-on; - enable-active-high; - gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc_1v8_s0>; - }; - - vcc3v3_pcie30: vcc3v3-pcie30 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_host: vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - }; - - vcc_mipicsi0: vcc-mipicsi0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipicsi0_pwr>; - regulator-name = "vcc_mipicsi0"; - enable-active-high; - }; - - vcc_mipicsi1: vcc-mipicsi1-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipicsi1_pwr>; - regulator-name = "vcc_mipicsi1"; - enable-active-high; - }; - - vcc_mipidcphy0: vcc-mipidcphy0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipidcphy0_pwr>; - regulator-name = "vcc_mipidcphy0"; - enable-active-high; - }; - - wireless_bluetooth: wireless-bluetooth { - compatible = "bluetooth-platdata"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "rts_gpio"; - pinctrl-0 = <&uart8m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; - pinctrl-1 = <&uart8_gpios>; - BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; - BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; - BT,wake_host_irq = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - wifi_chip_type = "ap6255"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; - WIFI,host_wake_irq = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; - WIFI,poweren_gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; -}; - -&backlight { - pwms = <&pwm2 0 25000 0>; - status = "okay"; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&dp0 { - status = "okay"; -}; - -&dp0_in_vp2 { - status = "okay"; -}; - -&dp0_sound{ - status = "okay"; -}; - -&dp1 { - pinctrl-names = "default"; - pinctrl-0 = <&dp1_hpd>; - hpd-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&dp1_in_vp2 { - status = "okay"; -}; - -/* - * mipi_dcphy0 needs to be enabled - * when dsi0 is enabled - */ -&dsi0 { - status = "okay"; -}; - -&dsi0_in_vp2 { - status = "disabled"; -}; - -&dsi0_in_vp3 { - status = "okay"; -}; - -&dsi0_panel { - power-supply = <&vcc3v3_lcd_n>; - reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rst_gpio>; -}; - -/* - * mipi_dcphy1 needs to be enabled - * when dsi1 is enabled - */ -&dsi1 { - status = "disabled"; -}; - -&dsi1_in_vp2 { - status = "disabled"; -}; - -&dsi1_in_vp3 { - status = "disabled"; -}; - -&dsi1_panel { - power-supply = <&vcc3v3_lcd_n>; - - /* - * because in hardware, the two screens share the reset pin, - * so reset-gpios need only in dsi1 enable and dsi0 disabled - * case. - */ - - //reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; - //pinctrl-names = "default"; - //pinctrl-0 = <&lcd_rst_gpio>; -}; - -&gmac0 { - /* Use rgmii-rxid mode to disable rx delay inside Soc */ - phy-mode = "rgmii-rxid"; - clock_in_out = "output"; - - snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - - tx_delay = <0x43>; - /* rx_delay = <0x3f>; */ - - phy-handle = <&rgmii_phy>; - status = "okay"; -}; - -&hdmi0 { - enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi0_in_vp0 { - status = "okay"; -}; - -&hdmi0_sound { - status = "okay"; -}; - -&hdmi1 { - enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi1_in_vp1 { - status = "okay"; -}; - -&hdmi1_sound { - status = "okay"; -}; - -/* Should work with at least 128MB cma reserved above. */ -&hdmirx_ctrler { - status = "okay"; - - #sound-dai-cells = <1>; - /* Effective level used to trigger HPD: 0-low, 1-high */ - hpd-trigger-level = <1>; - hdmirx-det-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmim1_rx &hdmirx_det>; -}; - -&hdptxphy_hdmi0 { - status = "okay"; -}; - -&hdptxphy_hdmi1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - usbc0: fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio3>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vbus5v0_typec>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - ; - source-pdos = - ; - - altmodes { - #address-cells = <1>; - #size-cells = <0>; - - altmode@0 { - reg = <0>; - svid = <0xff01>; - vdo = <0xffffffff>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; - }; - }; - - port@1 { - reg = <1>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; - }; - }; - }; - }; - }; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&i2c6 { - status = "okay"; - gt1x: gt1x@14 { - compatible = "goodix,gt1x"; - reg = <0x14>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_gpio>; - goodix,rst-gpio = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; - goodix,irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>; - power-supply = <&vcc3v3_lcd_n>; - }; -}; - -&i2c7 { - status = "okay"; - es8388: es8388@11 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "everest,es8388", "everest,es8323"; - reg = <0x11>; - clocks = <&mclkout_i2s0>; - clock-names = "mclk"; - assigned-clocks = <&mclkout_i2s0>; - assigned-clock-rates = <12288000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk>; - }; -}; - -&i2s5_8ch { - status = "okay"; -}; - -&i2s6_8ch { - status = "okay"; -}; - -&i2s7_8ch { - status = "okay"; -}; - -&mdio0 { - rgmii_phy: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - }; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&mipi_dcphy1 { - status = "disabled"; -}; - -&pcie2x1l0 { - reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - rockchip,skip-scan-in-resume; - status = "okay"; -}; - -&pcie2x1l1 { - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&rtl8111_isolate>; - status = "okay"; -}; - -&pcie30phy { - rockchip,pcie30-phymode = ; - status = "okay"; -}; - -&pcie3x4 { - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; -}; - -&pinctrl { - cam { - mipicsi0_pwr: mipicsi0-pwr { - rockchip,pins = - /* camera power en */ - <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - mipicsi1_pwr: mipicsi1-pwr { - rockchip,pins = - /* camera power en */ - <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - mipidcphy0_pwr: mipidcphy0-pwr { - rockchip,pins = - /* camera power en */ - <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - dp { - dp1_hpd: dp1-hpd { - rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi { - hdmirx_det: hdmirx-det { - rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - headphone { - hp_det: hp-det { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lcd { - lcd_rst_gpio: lcd-rst-gpio { - rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - rtl8111 { - rtl8111_isolate: rtl8111-isolate { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - touch { - touch_gpio: touch-gpio { - rockchip,pins = - <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>, - <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - usbc0_int: usbc0-int { - rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - typec5v_pwren: typec5v-pwren { - rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-bluetooth { - uart8_gpios: uart8-gpios { - rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reset_gpio: bt-reset-gpio { - rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_gpio: bt-wake-gpio { - rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_irq_gpio: bt-irq-gpio { - rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - wifi_poweren_gpio: wifi-poweren-gpio { - rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm9 { - pinctrl-0 = <&pwm9m1_pins>; - status = "okay"; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp3_out_dsi0>; -}; - -&route_dsi1 { - status = "disabled"; - connect = <&vp3_out_dsi1>; -}; - -&route_hdmi0 { - status = "okay"; - connect = <&vp0_out_hdmi0>; -}; - -&route_hdmi1 { - status = "okay"; - connect = <&vp1_out_hdmi1>; -}; - -&sata0 { - status = "okay"; -}; - -&spdif_tx2 { - status = "okay"; -}; - -&u2phy0_otg { - rockchip,typec-vbus-det; -}; - -&u2phy1_otg { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; -}; - -&uart8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>; -}; - -&usbdp_phy0 { - orientation-switch; - svid = <0xff01>; - sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - - port { - #address-cells = <1>; - #size-cells = <0>; - usbdp_phy0_orientation_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; - }; - - usbdp_phy0_dp_altmode_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&dp_altmode_mux>; - }; - }; -}; - -&usbdp_phy1 { - rockchip,dp-lane-mux = <2 3>; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - usb-role-switch; - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -&usbhost3_0 { - status = "disabled"; -}; - -&usbhost_dwc3_0 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-imx415.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb2-imx415.dtsi deleted file mode 100644 index acff4eab0..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb2-imx415.dtsi +++ /dev/null @@ -1,176 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/ { - cam_ircut0: cam_ircut { - status = "okay"; - compatible = "rockchip,ircut"; - ircut-open-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - ircut-close-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - }; - vcc_mipidphy0: vcc-mipidcphy0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipidphy0_pwr>; - regulator-name = "vcc_mipidphy0"; - enable-active-high; - }; -}; - -&csi2_dphy0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipidphy0_in_ucam0: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx415_out0>; - data-lanes = <1 2 3 4>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi2_csi2_input>; - }; - }; - }; -}; - -&csi2_dphy0_hw { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - - imx415: imx415@1a { - compatible = "sony,imx415"; - reg = <0x1a>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; - clock-names = "xvclk"; - pinctrl-names = "default"; - pinctrl-0 = <&mipim0_camera3_clk>; - power-domains = <&power RK3588_PD_VI>; - pwdn-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; - avdd-supply = <&vcc_mipidphy0>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT2022-PX1"; - rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; - lens-focus = <&cam_ircut0>; - port { - imx415_out0: endpoint { - remote-endpoint = <&mipidphy0_in_ucam0>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&mipi2_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy0_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi2_in0>; - }; - }; - }; -}; - -&pinctrl { - cam { - mipidphy0_pwr: mipidphy0-pwr { - rockchip,pins = - /* camera power en */ - <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds2 { - status = "okay"; - - port { - cif_mipi2_in0: endpoint { - remote-endpoint = <&mipi2_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds2_sditf { - status = "okay"; - - port { - mipi_lvds2_sditf: endpoint { - remote-endpoint = <&isp0_vir0>; - }; - }; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp0 { - status = "okay"; -}; - -&isp0_mmu { - status = "okay"; -}; - -&rkisp0_vir0 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds2_sditf>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4-v10-edp.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4-v10-edp.dts deleted file mode 100644 index a889cc325..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4-v10-edp.dts +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2021 Rockchip Electronics Co., Ltd. - -/dts-v1/; - -#include "rk3588-evb2-lp4.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588 EVB2 LP4 V10 eDP Board"; - compatible = "rockchip,rk3588-evb2-lp4-v10-edp", "rockchip,rk3588"; - - panel-edp1 { - compatible = "simple-panel"; - backlight = <&backlight>; - power-supply = <&vcc3v3_lcd>; - prepare-delay-ms = <120>; - enable-delay-ms = <120>; - unprepare-delay-ms = <120>; - disable-delay-ms = <120>; - width-mm = <129>; - height-mm = <171>; - - panel-timing { - clock-frequency = <200000000>; - hactive = <1536>; - vactive = <2048>; - hfront-porch = <12>; - hsync-len = <16>; - hback-porch = <48>; - vfront-porch = <8>; - vsync-len = <4>; - vback-porch = <8>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - panel_in_edp1: endpoint { - remote-endpoint = <&edp1_out_panel>; - }; - }; - }; - - vcc3v3_lcd: vcc3v3-lcd { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd"; - vin-supply = <&vcc_3v3_s0>; - }; -}; - -&backlight { - enable-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; -}; - -&dp0_in_vp0 { - status = "disabled"; -}; - -&dp0_in_vp1 { - status = "okay"; -}; - -&dp0_in_vp2 { - status = "disabled"; -}; - -&dp1_in_vp0 { - status = "disabled"; -}; - -&dp1_in_vp1 { - status = "okay"; -}; - -&dp1_in_vp2 { - status = "disabled"; -}; - -&dsi1 { - status = "disabled"; -}; - -&edp1 { - force-hpd; - status = "okay"; - - ports { - port@1 { - reg = <1>; - - edp1_out_panel: endpoint { - remote-endpoint = <&panel_in_edp1>; - }; - }; - }; -}; - -&edp1_in_vp0 { - status = "disabled"; -}; - -&edp1_in_vp1 { - status = "disabled"; -}; - -&edp1_in_vp2 { - status = "okay"; -}; - ->1x { - status = "disabled"; -}; - -&hdptxphy1 { - status = "okay"; -}; - -&i2c6 { - clock-frequency = <400000>; - status = "okay"; - - gsl3673@40 { - compatible = "GSL,GSL3673"; - reg = <0x40>; - screen_max_x = <1536>; - screen_max_y = <2048>; - irq_gpio_number = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>; - rst_gpio_number = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; - }; -}; - -&vcc3v3_lcd_n { - /delete-property/ gpio; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4-v10-edp2dp.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4-v10-edp2dp.dts deleted file mode 100644 index 83090d770..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4-v10-edp2dp.dts +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2021 Rockchip Electronics Co., Ltd. - -/dts-v1/; - -#include "rk3588-evb2-lp4.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588 EVB2 LP4 V10 eDP to DP Board"; - compatible = "rockchip,rk3588-evb2-lp4-v10-edp2dp", "rockchip,rk3588"; - - dp-con { - compatible = "dp-connector"; - status = "okay"; - - port { - dp_con_in_edp0: endpoint { - remote-endpoint = <&edp0_out_dp_con>; - }; - }; - }; - - edp0-sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "rockchip-edp-sound"; - - simple-audio-card,cpu { - sound-dai = <&spdif_tx3>; - }; - - simple-audio-card,codec { - sound-dai = <&edp0 1>; - }; - }; -}; - -&edp0 { - pinctrl-names = "default"; - pinctrl-0 = <&hdmim0_tx0_hpd>; - #sound-dai-cells = <1>; - status = "okay"; - - ports { - port@1 { - reg = <1>; - - edp0_out_dp_con: endpoint { - remote-endpoint = <&dp_con_in_edp0>; - }; - }; - }; -}; - -&edp0_in_vp2 { - status = "okay"; -}; - -&hdptxphy0 { - status = "okay"; -}; - -&hdptxphy_hdmi0 { - status = "disabled"; -}; - -&hdmi0 { - status = "disabled"; -}; - -&spdif_tx3 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4-v10-linux.dts deleted file mode 100644 index 6f2ba9347..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4-v10-linux.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-evb2-lp4.dtsi" -#include "rk3588-linux.dtsi" - -/ { - model = "Rockchip RK3588 EVB2 LP4 V10 Board"; - compatible = "rockchip,rk3588-evb2-lp4-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4-v10.dts deleted file mode 100644 index 56e944875..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4-v10.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-evb2-lp4.dtsi" -#include "rk3588-evb2-imx415.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588 EVB2 LP4 V10 Board"; - compatible = "rockchip,rk3588-evb2-lp4-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi deleted file mode 100644 index 03c9c36d0..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4.dtsi +++ /dev/null @@ -1,541 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include "rk3588.dtsi" -#include "rk3588-evb.dtsi" -#include "rk3588-rk806-dual.dtsi" - -/ { - es7202_sound_micarray: es7202-sound-micarray { - status = "okay"; - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip,sound-micarray"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,dai-link@0 { - format = "pdm"; - cpu { - sound-dai = <&pdm0>; - }; - codec { - sound-dai = <&es7202>; - }; - }; - }; - - es8388_sound: es8388-sound { - status = "okay"; - compatible = "rockchip,multicodecs-card"; - rockchip,card-name = "rockchip-es8388"; - hp-det-gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; - io-channels = <&saradc 3>; - io-channel-names = "adc-detect"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - spk-con-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; - hp-con-gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - rockchip,format = "i2s"; - rockchip,mclk-fs = <256>; - rockchip,cpu = <&i2s0_8ch>; - rockchip,codec = <&es8388>; - rockchip,audio-routing = - "Headphone", "LOUT1", - "Headphone", "ROUT1", - "Speaker", "LOUT2", - "Speaker", "ROUT2", - "Headphone", "Headphone Power", - "Headphone", "Headphone Power", - "Speaker", "Speaker Power", - "Speaker", "Speaker Power", - "LINPUT1", "Main Mic", - "LINPUT2", "Main Mic", - "RINPUT1", "Headset Mic", - "RINPUT2", "Headset Mic"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - play-pause-key { - label = "playpause"; - linux,code = ; - press-threshold-microvolt = <2000>; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - pwms = <&pwm9 0 50000 0>; - cooling-levels = <0 50 100 150 200 255>; - rockchip,temp-trips = < - 50000 1 - 55000 2 - 60000 3 - 65000 4 - 70000 5 - >; - }; - - pcie20_avdd0v85: pcie20-avdd0v85 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd0v85"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&avdd_0v85_s0>; - }; - - pcie20_avdd1v8: pcie20-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - pcie30_avdd0v75: pcie30-avdd0v75 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v75"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - vin-supply = <&avdd_0v75_s0>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - post-power-on-delay-ms = <200>; - reset-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_LOW>; - }; - - vcc3v3_lcd_n: vcc3v3-lcd0-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd0_n"; - regulator-boot-on; - enable-active-high; - gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc_1v8_s0>; - }; - - vcc3v3_pcie30: vcc3v3-pcie30 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_host: vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - }; - - wireless_bluetooth: wireless-bluetooth { - compatible = "bluetooth-platdata"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "rts_gpio"; - pinctrl-0 = <&uart9m0_rtsn>, <&bt_gpio>; - pinctrl-1 = <&uart9_gpios>; - BT,reset_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; - BT,wake_gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; - BT,wake_host_irq = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - wifi_chip_type = "ap6398s"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_irq>; - WIFI,host_wake_irq = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; - WIFI,poweren_gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; -}; - -&backlight { - pwms = <&pwm3 0 25000 0>; - status = "okay"; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&dp0 { - pinctrl-0 = <&dp0m2_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&dp0_in_vp2 { - status = "okay"; -}; - -&dp0_sound { - status = "okay"; -}; - -&dp1 { - pinctrl-0 = <&dp1m2_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&dp1_in_vp2 { - status = "okay"; -}; - -/* - * mipi_dcphy1 needs to be enabled - * when dsi1 is enabled - */ -&dsi1 { - status = "okay"; -}; - -&dsi1_in_vp2 { - status = "disabled"; -}; - -&dsi1_in_vp3 { - status = "okay"; -}; - -&dsi1_panel { - power-supply = <&vcc3v3_lcd_n>; - - reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rst_gpio>; -}; - -&gmac1 { - /* Use rgmii-rxid mode to disable rx delay inside Soc */ - phy-mode = "rgmii-rxid"; - clock_in_out = "output"; - - snps,reset-gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac1_miim - &gmac1_tx_bus2 - &gmac1_rx_bus2 - &gmac1_rgmii_clk - &gmac1_rgmii_bus>; - - tx_delay = <0x45>; - /* rx_delay = <0x3f>; */ - - phy-handle = <&rgmii_phy>; - status = "okay"; -}; - -&hdmi0 { - enable-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi0_in_vp0 { - status = "okay"; -}; - -&hdmi0_sound { - status = "okay"; -}; - -&hdptxphy_hdmi0 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&i2c6 { - status = "okay"; - gt1x: gt1x@14 { - compatible = "goodix,gt1x"; - reg = <0x14>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_gpio>; - goodix,rst-gpio = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; - goodix,irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>; - power-supply = <&vcc3v3_lcd_n>; - }; -}; - -&i2c7 { - status = "okay"; - - es8388: es8388@11 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "everest,es8388", "everest,es8323"; - reg = <0x11>; - clocks = <&mclkout_i2s0>; - clock-names = "mclk"; - assigned-clocks = <&mclkout_i2s0>; - assigned-clock-rates = <12288000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk>; - }; - - es7202: es7202@32 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "ES7202_PDM_ADC_1"; - power-supply = <&vcc_1v8_s0>; /* only 1v8 or 3v3, default is 3v3 */ - reg = <0x32>; - }; -}; - -&i2s2_2ch { - pinctrl-0 = <&i2s2m0_sclk &i2s2m0_lrck &i2s2m0_sdi &i2s2m0_sdo>; - status = "disabled"; -}; - -&i2s5_8ch { - status = "okay"; -}; - -&mdio1 { - rgmii_phy: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - }; -}; - -&mipi_dcphy1 { - status = "okay"; -}; - -&pcie2x1l0 { - reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x4 { - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; -}; - -&pdm0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pdm0m0_clk - &pdm0m0_sdi0>; -}; - -&pinctrl { - headphone { - hp_det: hp-det { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lcd { - lcd_rst_gpio: lcd-rst-gpio { - rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - touch { - touch_gpio: touch-gpio { - rockchip,pins = - <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>, - <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-bluetooth { - uart9_gpios: uart9-gpios { - rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_gpio: bt-gpio { - rockchip,pins = - <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, - <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>, - <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; - -&pwm3 { - status = "okay"; - pinctrl-0 = <&pwm3m1_pins>; -}; - -&pwm9 { - pinctrl-0 = <&pwm9m2_pins>; - status = "okay"; -}; - -&route_dsi1 { - status = "okay"; - connect = <&vp3_out_dsi1>; -}; - -&sata0 { - status = "okay"; -}; - -&sdio { - max-frequency = <150000000>; - no-sd; - no-mmc; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdiom0_pins>; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdmmc { - status = "okay"; - vmmc-supply = <&vcc_3v3_sd_s0>; -}; - -&spdif_tx2 { - status = "okay"; -}; - -&u2phy0_otg { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy1_otg { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; -}; - -&usbdp_phy0 { - rockchip,dp-lane-mux = <2 3>; -}; - -&usbdp_phy1 { - rockchip,dp-lane-mux = <2 3>; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - extcon = <&u2phy0>; - status = "okay"; -}; - -&uart9 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>; -}; - -&vcc3v3_lcd_n { - gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; - enable-active-high; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb3-imx415.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb3-imx415.dtsi deleted file mode 100644 index acff4eab0..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb3-imx415.dtsi +++ /dev/null @@ -1,176 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/ { - cam_ircut0: cam_ircut { - status = "okay"; - compatible = "rockchip,ircut"; - ircut-open-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - ircut-close-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - }; - vcc_mipidphy0: vcc-mipidcphy0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipidphy0_pwr>; - regulator-name = "vcc_mipidphy0"; - enable-active-high; - }; -}; - -&csi2_dphy0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipidphy0_in_ucam0: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx415_out0>; - data-lanes = <1 2 3 4>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi2_csi2_input>; - }; - }; - }; -}; - -&csi2_dphy0_hw { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - - imx415: imx415@1a { - compatible = "sony,imx415"; - reg = <0x1a>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; - clock-names = "xvclk"; - pinctrl-names = "default"; - pinctrl-0 = <&mipim0_camera3_clk>; - power-domains = <&power RK3588_PD_VI>; - pwdn-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; - avdd-supply = <&vcc_mipidphy0>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT2022-PX1"; - rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; - lens-focus = <&cam_ircut0>; - port { - imx415_out0: endpoint { - remote-endpoint = <&mipidphy0_in_ucam0>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&mipi2_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy0_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi2_in0>; - }; - }; - }; -}; - -&pinctrl { - cam { - mipidphy0_pwr: mipidphy0-pwr { - rockchip,pins = - /* camera power en */ - <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds2 { - status = "okay"; - - port { - cif_mipi2_in0: endpoint { - remote-endpoint = <&mipi2_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds2_sditf { - status = "okay"; - - port { - mipi_lvds2_sditf: endpoint { - remote-endpoint = <&isp0_vir0>; - }; - }; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp0 { - status = "okay"; -}; - -&isp0_mmu { - status = "okay"; -}; - -&rkisp0_vir0 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds2_sditf>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10-edp-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10-edp-linux.dts deleted file mode 100644 index 964efd902..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10-edp-linux.dts +++ /dev/null @@ -1,110 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2021 Rockchip Electronics Co., Ltd. - -/dts-v1/; - -#include "rk3588-evb3-lp5.dtsi" -#include "rk3588-linux.dtsi" - -/ { - model = "Rockchip RK3588 EVB3 LP5 V10 EDP Board"; - compatible = "rockchip,rk3588-evb3-lp5-v10-edp-linux", "rockchip,rk3588"; - - panel-edp0 { - compatible = "simple-panel"; - backlight = <&backlight>; - power-supply = <&vcc3v3_lcd>; - prepare-delay-ms = <120>; - enable-delay-ms = <120>; - unprepare-delay-ms = <120>; - disable-delay-ms = <120>; - width-mm = <129>; - height-mm = <171>; - - panel-timing { - clock-frequency = <200000000>; - hactive = <1536>; - vactive = <2048>; - hfront-porch = <12>; - hsync-len = <16>; - hback-porch = <48>; - vfront-porch = <8>; - vsync-len = <4>; - vback-porch = <8>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - panel_in_edp0: endpoint { - remote-endpoint = <&edp0_out_panel>; - }; - }; - }; - - vcc3v3_lcd: vcc3v3-lcd { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd"; - vin-supply = <&vcc_3v3_s0>; - }; -}; - -&backlight { - enable-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; -}; - -&dsi0 { - status = "disabled"; -}; - -&edp0 { - force-hpd; - status = "okay"; - - ports { - port@1 { - reg = <1>; - - edp0_out_panel: endpoint { - remote-endpoint = <&panel_in_edp0>; - }; - }; - }; -}; - -&edp0_in_vp2 { - status = "okay"; -}; - ->1x { - status = "disabled"; -}; - -&hdptxphy0 { - lane-polarity-invert = <0 1 0 0>; - status = "okay"; -}; - -&i2c5 { - clock-frequency = <400000>; - status = "okay"; - - gsl3673@40 { - compatible = "GSL,GSL3673"; - reg = <0x40>; - screen_max_x = <1536>; - screen_max_y = <2048>; - irq_gpio_number = <&gpio4 RK_PB1 IRQ_TYPE_LEVEL_LOW>; - rst_gpio_number = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - }; -}; - -&pwm15 { - pinctrl-0 = <&pwm15m1_pins>; -}; - -&vcc3v3_lcd_n { - /delete-property/ gpio; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10-edp.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10-edp.dts deleted file mode 100644 index 3890e1d26..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10-edp.dts +++ /dev/null @@ -1,110 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (c) 2021 Rockchip Electronics Co., Ltd. - -/dts-v1/; - -#include "rk3588-evb3-lp5.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588 EVB3 LP5 V10 EDP Board"; - compatible = "rockchip,rk3588-evb3-lp5-v10-edp", "rockchip,rk3588"; - - panel-edp0 { - compatible = "simple-panel"; - backlight = <&backlight>; - power-supply = <&vcc3v3_lcd>; - prepare-delay-ms = <120>; - enable-delay-ms = <120>; - unprepare-delay-ms = <120>; - disable-delay-ms = <120>; - width-mm = <129>; - height-mm = <171>; - - panel-timing { - clock-frequency = <200000000>; - hactive = <1536>; - vactive = <2048>; - hfront-porch = <12>; - hsync-len = <16>; - hback-porch = <48>; - vfront-porch = <8>; - vsync-len = <4>; - vback-porch = <8>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - panel_in_edp0: endpoint { - remote-endpoint = <&edp0_out_panel>; - }; - }; - }; - - vcc3v3_lcd: vcc3v3-lcd { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd"; - vin-supply = <&vcc_3v3_s0>; - }; -}; - -&backlight { - enable-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; -}; - -&dsi0 { - status = "disabled"; -}; - -&edp0 { - force-hpd; - status = "okay"; - - ports { - port@1 { - reg = <1>; - - edp0_out_panel: endpoint { - remote-endpoint = <&panel_in_edp0>; - }; - }; - }; -}; - -&edp0_in_vp2 { - status = "okay"; -}; - ->1x { - status = "disabled"; -}; - -&hdptxphy0 { - lane-polarity-invert = <0 1 0 0>; - status = "okay"; -}; - -&i2c5 { - clock-frequency = <400000>; - status = "okay"; - - gsl3673@40 { - compatible = "GSL,GSL3673"; - reg = <0x40>; - screen_max_x = <1536>; - screen_max_y = <2048>; - irq_gpio_number = <&gpio4 RK_PB1 IRQ_TYPE_LEVEL_LOW>; - rst_gpio_number = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - }; -}; - -&pwm15 { - pinctrl-0 = <&pwm15m1_pins>; -}; - -&vcc3v3_lcd_n { - /delete-property/ gpio; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10-linux.dts deleted file mode 100644 index 26d6a69a6..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10-linux.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-evb3-lp5.dtsi" -#include "rk3588-linux.dtsi" -#include "rk3588-evb3-imx415.dtsi" - -/ { - model = "Rockchip RK3588 EVB3 LP5 V10 Board"; - compatible = "rockchip,rk3588-evb3-lp5-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10.dts deleted file mode 100644 index 95f305758..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5-v10.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-evb3-lp5.dtsi" -#include "rk3588-android.dtsi" -#include "rk3588-evb3-imx415.dtsi" - -/ { - model = "Rockchip RK3588 EVB3 LP5 V10 Board"; - compatible = "rockchip,rk3588-evb3-lp5-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi deleted file mode 100644 index 4213e54ab..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi +++ /dev/null @@ -1,1232 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include "dt-bindings/usb/pd.h" -#include "rk3588.dtsi" -#include "rk3588-evb.dtsi" -#include "rk3588-rk806-dual.dtsi" - -/ { - es7202_sound_micarray: es7202-sound-micarray { - status = "okay"; - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip,sound-micarray"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,dai-link@0 { - format = "pdm"; - cpu { - sound-dai = <&pdm0>; - }; - codec { - sound-dai = <&es7202>; - }; - }; - }; - - es8388_sound: es8388-sound { - status = "okay"; - compatible = "rockchip,multicodecs-card"; - rockchip,card-name = "rockchip-es8388"; - hp-det-gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; - io-channels = <&saradc 3>; - io-channel-names = "adc-detect"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - spk-con-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; - hp-con-gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - rockchip,format = "i2s"; - rockchip,mclk-fs = <256>; - rockchip,cpu = <&i2s0_8ch>; - rockchip,codec = <&es8388>; - rockchip,audio-routing = - "Headphone", "LOUT1", - "Headphone", "ROUT1", - "Speaker", "LOUT2", - "Speaker", "ROUT2", - "Headphone", "Headphone Power", - "Headphone", "Headphone Power", - "Speaker", "Speaker Power", - "Speaker", "Speaker Power", - "LINPUT1", "Main Mic", - "LINPUT2", "Main Mic", - "RINPUT1", "Headset Mic", - "RINPUT2", "Headset Mic"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - play-pause-key { - label = "playpause"; - linux,code = ; - press-threshold-microvolt = <2000>; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - pwms = <&pwm6 0 50000 0>; - cooling-levels = <0 50 100 150 200 255>; - rockchip,temp-trips = < - 50000 1 - 55000 2 - 60000 3 - 65000 4 - 70000 5 - >; - }; - - hall_sensor: hall-mh248 { - compatible = "hall-mh248"; - pinctrl-names = "default"; - pinctrl-0 = <&mh248_irq_gpio>; - irq-gpio = <&gpio0 RK_PD2 IRQ_TYPE_EDGE_BOTH>; - hall-active = <1>; - status = "okay"; - }; - - pcie20_avdd0v85: pcie20-avdd0v85 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd0v85"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&avdd_0v85_s0>; - }; - - pcie20_avdd1v8: pcie20-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - pcie30_avdd0v75: pcie30-avdd0v75 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v75"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - vin-supply = <&avdd_0v75_s0>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - vbus5v0_typec: vbus5v0-typec { - compatible = "regulator-fixed"; - regulator-name = "vbus5v0_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; - }; - - vcc3v3_lcd_n: vcc3v3-lcd0-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd0_n"; - regulator-boot-on; - enable-active-high; - gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc_1v8_s0>; - }; - - vcc3v3_pcie30: vcc3v3-pcie30 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_host: vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - }; - - wireless_bluetooth: wireless-bluetooth { - compatible = "bluetooth-platdata"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "rts_gpio"; - pinctrl-0 = <&uart8m1_rtsn>; - pinctrl-1 = <&uart8_gpios>; - BT,reset_gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; - BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; - BT,wake_host_irq = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - wifi_chip_type = "ap6275p"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; - WIFI,host_wake_irq = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; - WIFI,poweren_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&backlight { - pwms = <&pwm15 0 25000 0>; - status = "okay"; -}; - -&dp0 { - status = "okay"; -}; - -&dp0_in_vp2 { - status = "okay"; -}; - -&dp1_sound { - status = "okay"; -}; - -&dp1 { - pinctrl-0 = <&dp1m2_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&dp1_in_vp2 { - status = "okay"; -}; - -/* - * mipi_dcphy0 needs to be enabled - * when dsi0 is enabled - */ -&dsi0 { - status = "okay"; -}; - -&dsi0_in_vp2 { - status = "disabled"; -}; - -&dsi0_in_vp3 { - status = "okay"; -}; - -&dsi0_panel { - power-supply = <&vcc3v3_lcd_n>; - reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rst_gpio>; -}; - -/* - * mipi_dcphy1 needs to be enabled - * when dsi1 is enabled - */ -&dsi1 { - status = "disabled"; -}; - -&dsi1_in_vp2 { - status = "disabled"; -}; - -&dsi1_in_vp3 { - status = "disabled"; -}; - -&dsi1_panel { - power-supply = <&vcc3v3_lcd_n>; - - /* - * because in hardware, the two screens share the reset pin, - * so reset-gpios need only in dsi1 enable and dsi0 disabled - * case. - */ - - //reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>; - //pinctrl-names = "default"; - //pinctrl-0 = <&lcd_rst_gpio>; - phy-c-option; - dsi,lanes = <3>; - - panel-init-sequence = [ - 23 00 02 FF 20 - 23 00 02 FB 01 - 23 00 02 05 D9 - /* VGH=17V */ - 23 00 02 07 78 - /* VGL=-14V */ - 23 00 02 08 5A - /* EN_VMODGATE2=1 */ - 23 00 02 0D 63 - /* VGH=16V */ - 23 00 02 0E 91 - /* VGL=-13V */ - 23 00 02 0F 73 - /* GVDD=5.2V */ - 23 00 02 95 EB - 23 00 02 96 EB - /* Disable VDDI LV */ - 23 00 02 30 11 - /* ISOP */ - 23 00 02 6D 66 - /* EN_GMACP */ - 23 00 02 75 A2 - /* V128 */ - 23 00 02 77 3B - /* R(+) */ - 29 00 11 B0 00 08 00 23 00 4D 00 6D 00 89 00 A1 00 B6 00 C9 - 29 00 11 B1 00 DA 01 13 01 3C 01 7E 01 AB 01 F7 02 2F 02 31 - 29 00 11 B2 02 67 02 A6 02 D1 03 08 03 2E 03 5B 03 6B 03 7B - 29 00 0D B3 03 8E 03 A2 03 B7 03 E7 03 FD 03 FF - /* G(+) */ - 29 00 11 B4 00 08 00 23 00 4D 00 6D 00 89 00 A1 00 B6 00 C9 - 29 00 11 B5 00 DA 01 13 01 3C 01 7E 01 AB 01 F7 02 2F 02 31 - 29 00 11 B6 02 67 02 A6 02 D1 03 08 03 2E 03 5B 03 6B 03 7B - 29 00 0D B7 03 8E 03 A2 03 B7 03 E7 03 FD 03 FF - /* B(+) */ - 29 00 11 B8 00 08 00 23 00 4D 00 6D 00 89 00 A1 00 B6 00 C9 - 29 00 11 B9 00 DA 01 13 01 3C 01 7E 01 AB 01 F7 02 2F 02 31 - 29 00 11 BA 02 67 02 A6 02 D1 03 08 03 2E 03 5B 03 6B 03 7B - 29 00 0D BB 03 8E 03 A2 03 B7 03 E7 03 FD 03 FF - /* CMD2_Page1 */ - 23 00 02 FF 21 - 23 00 02 FB 01 - /* R(-) */ - 29 00 11 B0 00 00 00 1B 00 45 00 65 00 81 00 99 00 AE 00 C1 - 29 00 11 B1 00 D2 01 0B 01 34 01 76 01 A3 01 EF 02 27 02 29 - 29 00 11 B2 02 5F 02 9E 02 C9 03 00 03 26 03 53 03 63 03 73 - 29 00 0D B3 03 86 03 9A 03 AF 03 DF 03 F5 03 F7 - /* G(-) */ - 29 00 11 B4 00 00 00 1B 00 45 00 65 00 81 00 99 00 AE 00 C1 - 29 00 11 B5 00 D2 01 0B 01 34 01 76 01 A3 01 EF 02 27 02 29 - 29 00 11 B6 02 5F 02 9E 02 C9 03 00 03 26 03 53 03 63 03 73 - 29 00 0D B7 03 86 03 9A 03 AF 03 DF 03 F5 03 F7 - /* B(-) */ - 29 00 11 B8 00 00 00 1B 00 45 00 65 00 81 00 99 00 AE 00 C1 - 29 00 11 B9 00 D2 01 0B 01 34 01 76 01 A3 01 EF 02 27 02 29 - 29 00 11 BA 02 5F 02 9E 02 C9 03 00 03 26 03 53 03 63 03 73 - 29 00 0D BB 03 86 03 9A 03 AF 03 DF 03 F5 03 F7 - - 29 00 02 FF 24 - 29 00 02 FB 01 - /* VGL */ - 29 00 02 00 00 - 29 00 02 01 00 - /* VDDO */ - 29 00 02 02 1C - 29 00 02 03 1C - /* VDDE */ - 29 00 02 04 1D - 29 00 02 05 1D - /* STV0 */ - 29 00 02 06 04 - 29 00 02 07 04 - /* CLK8 */ - 29 00 02 08 0F - 29 00 02 09 0F - /* CLK6 */ - 29 00 02 0A 0E - 29 00 02 0B 0E - /* CLK4 */ - 29 00 02 0C 0D - 29 00 02 0D 0D - /* CLK2 */ - 29 00 02 0E 0C - 29 00 02 0F 0C - /* STV2 */ - 29 00 02 10 08 - 29 00 02 11 08 - - 29 00 02 12 00 - 29 00 02 13 00 - 29 00 02 14 00 - 29 00 02 15 00 - /* VGL */ - 29 00 02 16 00 - 29 00 02 17 00 - /* VDDO */ - 29 00 02 18 1C - 29 00 02 19 1C - /* VDDE */ - 29 00 02 1A 1D - 29 00 02 1B 1D - /* STV0 */ - 29 00 02 1C 04 - 29 00 02 1D 04 - /* CLK7 */ - 29 00 02 1E 0F - 29 00 02 1F 0F - /* CLK5 */ - 29 00 02 20 0E - 29 00 02 21 0E - /* CLK3 */ - 29 00 02 22 0D - 29 00 02 23 0D - /* CLK1 */ - 29 00 02 24 0C - 29 00 02 25 0C - /* STV1 */ - 29 00 02 26 08 - 29 00 02 27 08 - - 29 00 02 28 00 - 29 00 02 29 00 - 29 00 02 2A 00 - 29 00 02 2B 00 - /* STV0 */ - 29 00 02 2D 20 - 29 00 02 2F 0A - 29 00 02 30 44 - 29 00 02 33 0C - 29 00 02 34 32 - - 29 00 02 37 44 - 29 00 02 38 40 - 29 00 02 39 00 - 29 00 02 3A 50 - 29 00 02 3B 50 - 29 00 02 3D 42 - /* STV */ - 29 00 02 3F 06 - 29 00 02 43 06 - - 29 00 02 47 66 - 29 00 02 4A 50 - 29 00 02 4B 50 - 29 00 02 4C 91 - /* GCK */ - 29 00 02 4D 21 - 29 00 02 4E 43 - 29 00 02 51 12 - 29 00 02 52 34 - 29 00 03 55 82 02 - 29 00 02 56 04 - 29 00 02 58 21 - 29 00 02 59 30 - 29 00 02 5A 50 - 29 00 02 5B 50 - 29 00 03 5E 00 06 - 29 00 02 5F 00 - /* EN_LFD_SOURCE=0 */ - 29 00 02 65 82 - /* VDDO, VDDE */ - 29 00 02 7E 20 - 29 00 02 7F 3C - 29 00 02 82 04 - 29 00 02 97 C0 - - 29 00 0D B6 05 00 05 00 00 00 00 00 05 05 00 00 - /* qclk=96/5 Mhz */ - 29 00 02 91 44 - 29 00 02 92 55 - 29 00 02 93 1A - 29 00 02 94 5F - /* SOG_HBP */ - 29 00 02 D7 55 - 29 00 02 DA 0A - 29 00 02 DE 08 - /* Normal */ - 29 00 02 DB 05 - 29 00 02 DC 55 - 29 00 02 DD 22 - /* Line N */ - 29 00 02 DF 05 - 29 00 02 E0 55 - /* Line N+1 */ - 29 00 02 E1 05 - 29 00 02 E2 55 - /* TP0 */ - 29 00 02 E3 05 - 29 00 02 E4 55 - /* TP3 */ - 29 00 02 E5 05 - 29 00 02 E6 55 - /* Gate EQ */ - 29 00 02 5C 00 - 29 00 02 5D 00 - /* TP3 */ - 29 00 02 8D 00 - 29 00 02 8E 00 - /* No Sync @ TP */ - 29 00 02 B5 90 - - 29 00 02 FF 25 - 29 00 02 FB 01 - /* disable auto_vbp_vfp */ - 29 00 02 05 00 - /* ESD_DET_ERR_SEL */ - 29 00 02 19 07 - /* DP_N_GCK */ - 29 00 02 1F 50 - 29 00 02 20 50 - /* DP_N_1_GCK */ - 29 00 02 26 50 - 29 00 02 27 50 - /* TP0_GCK */ - 29 00 02 33 50 - 29 00 02 34 50 - /* TP3 GCK/MUX=1 */ - 29 00 02 3F E0 - /* TP3_GCK_START_LINE */ - 29 00 02 40 00 - /* TP3_STV */ - 29 00 02 44 00 - 29 00 02 45 40 - /* TP3_GCK */ - 29 00 02 48 50 - 29 00 02 49 50 - /* LSTP0 */ - 29 00 02 5B 00 - 29 00 02 5C 00 - 29 00 02 5D 00 - 29 00 02 5E D0 - - 29 00 02 61 50 - 29 00 02 62 50 - /* en_vfp_addvsync */ - 29 00 02 F1 10 - /* CMD2,Page10 */ - 29 00 02 FF 2A - 29 00 02 FB 01 - /* PWRONOFF */ - /* STV */ - 29 00 02 64 16 - /* CLR */ - 29 00 02 67 16 - /* GCK */ - 29 00 02 6A 16 - /* POL */ - 29 00 02 70 30 - /* ABOFF */ - 29 00 02 A2 F3 - 29 00 02 A3 FF - 29 00 02 A4 FF - 29 00 02 A5 FF - /* Long_V_TIMING disable */ - 29 00 02 D6 08 - /* CMD2,Page6 */ - 29 00 02 FF 26 - 29 00 02 FB 01 - /* TPEN */ - 29 00 02 00 81 - /* 90Hz */ - 29 00 02 01 30 - - 29 00 02 02 31 - 29 00 02 0A F2 - //Table A (90Hz) - 29 00 02 04 28 - 29 00 02 06 3C - 29 00 02 0C 0B - 29 00 02 0D 0C - 29 00 02 0F 00 - 29 00 02 11 00 - 29 00 02 12 50 - 29 00 02 13 AE - 29 00 02 14 A6 - 29 00 02 16 10 - 29 00 02 19 08 - 29 00 02 1A FF - 29 00 02 1B 08 - 29 00 02 1C 80 - 29 00 02 22 00 - 29 00 02 23 00 - 29 00 02 2A 08 - 29 00 02 2B FF - - 29 00 02 1D 00 - 29 00 02 1E 55 - 29 00 02 1F 55 - 29 00 02 24 00 - 29 00 02 25 55 - 29 00 02 2F 05 - 29 00 02 30 55 - 29 00 02 31 05 - 29 00 02 32 6D - 29 00 02 39 00 - 29 00 02 3A 55 - /* Table B (60Hz,81*1+101*19=2000, Extra=20) */ - 29 00 02 8B 28 - 29 00 02 8C 13 - 29 00 02 8D 0A - 29 00 02 8F 0A - 29 00 02 91 00 - 29 00 02 92 50 - 29 00 02 93 51 - 29 00 02 94 65 - 29 00 02 96 10 - 29 00 02 99 0A - 29 00 02 9A 7F - 29 00 02 9B 0A - 29 00 02 9C 0C - 29 00 02 9D 0A - 29 00 02 9E 7F - - 29 00 02 3F 00 - 29 00 02 40 75 - 29 00 02 41 75 - 29 00 02 42 75 - 29 00 02 43 00 - 29 00 02 44 75 - 29 00 02 45 05 - 29 00 02 46 75 - 29 00 02 47 05 - 29 00 02 48 8D - 29 00 02 49 00 - 29 00 02 4A 75 - /* STV0 */ - 29 00 02 4D 5D - 29 00 02 4E 60 - /* STV */ - 29 00 02 4F 5D - 29 00 02 50 60 - /* GCK */ - 29 00 02 51 70 - 29 00 02 52 60 - /* DP_N_GCK */ - 29 00 02 56 70 - 29 00 02 58 60 - /* DP_N_1_GCK */ - 29 00 02 5B 70 - 29 00 02 5C 60 - /* TP0_GCK */ - 29 00 02 60 70 - 29 00 02 61 60 - /* TP3_GCK */ - 29 00 02 64 70 - 29 00 02 65 60 - /* LSTP0 */ - 29 00 02 72 70 - 29 00 02 73 60 - /* PRZ1 */ - 29 00 02 20 01 - /* PRZ3 */ - /* Rescan=3 */ - 29 00 02 33 11 - 29 00 02 34 78 - 29 00 02 35 16 - /* DLH */ - 29 00 02 C8 04 - 29 00 02 C9 80 - 29 00 02 CA 4E - 29 00 02 CB 00 - 29 00 02 A9 4C - 29 00 02 AA 47 - /* CMD2,Page7 */ - 29 00 02 FF 27 - 29 00 02 FB 01 - /* VPOR_DYNH_EN=1, VPOR_CNT_REV=1 */ - 29 00 02 56 06 - /* FR0(60Hz) */ - 29 00 02 58 80 - 29 00 02 59 53 - 29 00 02 5A 00 - 29 00 02 5B 14 - 29 00 02 5C 00 - 29 00 02 5D 01 - 29 00 02 5E 20 - 29 00 02 5F 10 - 29 00 02 60 00 - 29 00 02 61 1D - 29 00 02 62 00 - 29 00 02 63 01 - 29 00 02 64 24 - 29 00 02 65 1C - 29 00 02 66 00 - 29 00 02 67 01 - 29 00 02 68 25 - /* FR1(90Hz) */ - 29 00 02 78 80 - 29 00 02 79 73 - 29 00 02 7A 00 - 29 00 02 7B 14 - 29 00 02 7C 00 - 29 00 02 7D 02 - 29 00 02 7E 20 - 29 00 02 7F 21 - 29 00 02 80 00 - 29 00 02 81 2A - 29 00 02 82 00 - 29 00 02 83 01 - 29 00 02 84 1C - 29 00 02 85 28 - 29 00 02 86 00 - 29 00 02 87 01 - 29 00 02 88 1D - - 29 00 02 00 00 - 29 00 02 C3 00 - /* FTE output TE, FTE1 output TSVD, LEDPWM output TSHD */ - 29 00 02 D1 24 - 29 00 02 D2 53 - /* CMD2,Page10 */ - 29 00 02 FF 2A - 29 00 02 FB 01 - 29 00 02 01 05 - 29 00 02 02 55 - /* TP0 */ - 29 00 02 03 05 - 29 00 02 04 75 - /* TP3 */ - 29 00 02 05 05 - 29 00 02 06 75 - /* PEN_EN=1, UL_FREQ=0 */ - 29 00 02 22 2F - /* 90Hz */ - 29 00 02 23 11 - /* FR0 (60Hz) */ - 29 00 02 24 00 - 29 00 02 25 75 - 29 00 02 27 00 - 29 00 02 28 1A - 29 00 02 29 00 - 29 00 02 2A 1A - 29 00 02 2B 00 - 29 00 02 2D 1A - /* FR1 (90Hz) */ - 29 00 02 2F 00 - 29 00 02 30 55 - 29 00 02 32 00 - 29 00 02 33 1A - 29 00 02 34 00 - 29 00 02 35 1A - 29 00 02 36 00 - 29 00 02 37 1A - /* CMD2,Page3 */ - 29 00 02 FF 23 - 29 00 02 FB 01 - /* DBV=12 bit */ - 29 00 02 00 80 - /* PWM frequency */ - 29 00 02 07 00 - /* CMD3,PageA */ - 29 00 02 FF E0 - 29 00 02 FB 01 - /* VCOM Driving Ability */ - 29 00 02 14 60 - 29 00 02 16 C0 - /* CMD3,PageB */ - 29 00 02 FF F0 - 29 00 02 FB 01 - /* slave osc workaround */ - 29 00 02 3A 08 - /* CMD3,PageC */ - 29 00 02 FF D0 - 29 00 02 FB 01 - 29 00 02 1C 88 - 29 00 02 1D 08 - /* CMD1 */ - 29 00 02 FF 10 - 29 00 02 FB 01 - /* Only Write Slave */ - 29 00 02 B9 01 - /* CMD2,Page0 */ - 29 00 02 FF 20 - 29 00 02 FB 01 - 29 00 02 18 40 - /* CMD1 */ - 29 00 02 FF 10 - 29 00 02 FB 01 - /* Write Master & Slave */ - 29 00 02 B9 02 - 29 00 02 35 00 - 29 00 03 51 00 FF - 29 00 02 53 24 - 29 00 02 55 00 - 29 00 02 BB 13 - /* VBP+VFP=121 */ - 29 00 06 3B 03 5F 1A 04 04 - /* CMD2,Page5 */ - 29 00 02 FF 25 - /* FRM */ - 29 00 02 EC 00 - /* CMD1 */ - 29 00 02 FF 10 - 29 00 02 FB 01 - 05 FF 01 11 - 05 FF 01 29 - ]; - - panel-exit-sequence = [ - 05 00 01 28 - 05 00 01 10 - ]; - - disp_timings1: display-timings { - native-mode = <&dsi1_timing0>; - dsi1_timing0: timing0 { - clock-frequency = <241300000>; - hactive = <1200>; - vactive = <2000>; - hfront-porch = <31>; - hsync-len = <4>; - hback-porch = <32>; - vfront-porch = <26>; - vsync-len = <2>; - vback-porch = <93>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; -}; - -&hdmi1 { - enable-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi1_in_vp0 { - status = "okay"; -}; - -&hdmi1_sound { - status = "okay"; -}; - -&hdptxphy_hdmi1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - pinctrl-0 = <&i2c0m1_xfer>; - - ls_stk3332: light@47 { - compatible = "ls_stk3332"; - status = "okay"; - reg = <0x47>; - type = ; - irq_enable = <0>; - als_threshold_high = <100>; - als_threshold_low = <10>; - als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ - poll_delay_ms = <100>; - }; - - ps_stk3332: proximity@47 { - compatible = "ps_stk3332"; - status = "okay"; - reg = <0x47>; - type = ; - //pinctrl-names = "default"; - //pinctrl-0 = <&gpio2_b2>; - //irq-gpio = <&gpio2 RK_PB2 IRQ_TYPE_LEVEL_LOW>; - //irq_enable = <1>; - ps_threshold_high = <0x200>; - ps_threshold_low = <0x100>; - ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */ - ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/ - poll_delay_ms = <100>; - }; - - mpu6500_acc: mpu_acc@68 { - compatible = "mpu6500_acc"; - status = "okay"; - reg = <0x68>; - irq-gpio = <&gpio2 RK_PB5 IRQ_TYPE_EDGE_RISING>; - irq_enable = <0>; - poll_delay_ms = <30>; - type = ; - layout = <9>; - }; - - mpu6500_gyro: mpu_gyro@68 { - compatible = "mpu6500_gyro"; - status = "okay"; - reg = <0x68>; - irq_enable = <0>; - poll_delay_ms = <30>; - type = ; - layout = <9>; - }; -}; - -&i2c2 { - status = "okay"; - - usbc0: fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vbus5v0_typec>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - ; - source-pdos = - ; - - altmodes { - #address-cells = <1>; - #size-cells = <0>; - - altmode@0 { - reg = <0>; - svid = <0xff01>; - vdo = <0xffffffff>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; - }; - }; - - port@1 { - reg = <1>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; - }; - }; - - }; - }; - }; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5m4_xfer>; - - gt1x: gt1x@14 { - compatible = "goodix,gt1x"; - reg = <0x14>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_gpio>; - goodix,rst-gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - goodix,irq-gpio = <&gpio4 RK_PB1 IRQ_TYPE_LEVEL_LOW>; - power-supply = <&vcc3v3_lcd_n>; - }; -}; - -&i2c7 { - status = "okay"; - - es8388: es8388@11 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "everest,es8388", "everest,es8323"; - reg = <0x11>; - clocks = <&mclkout_i2s0>; - clock-names = "mclk"; - assigned-clocks = <&mclkout_i2s0>; - assigned-clock-rates = <12288000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk>; - }; - - es7202: es7202@32 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "ES7202_PDM_ADC_1"; - power-supply = <&vcc_1v8_s0>; /* only 1v8 or 3v3, default is 3v3 */ - reg = <0x32>; - }; -}; - -&i2s6_8ch { - status = "okay"; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - - -&mipi_dcphy1 { - status = "disabled"; -}; - -&pcie2x1l1 { - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&rtl8111_isolate>; - status = "okay"; -}; - -&pcie2x1l2 { - reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; - rockchip,skip-scan-in-resume; - status = "okay"; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x4 { - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; -}; - -&pdm0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pdm0m0_clk - &pdm0m0_sdi0>; -}; - -&pinctrl { - headphone { - hp_det: hp-det { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lcd { - lcd_rst_gpio: lcd-rst-gpio { - rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - rtl8111 { - rtl8111_isolate: rtl8111-isolate { - rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sensor { - mh248_irq_gpio: mh248-irq-gpio { - rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - mpu6500_irq_gpio: mpu6500_irq_gpio { - rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - touch { - touch_gpio: touch-gpio { - rockchip,pins = - <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, - <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - usbc0_int: usbc0-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - typec5v_pwren: typec5v-pwren { - rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-bluetooth { - uart8_gpios: uart8-gpios { - rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - wifi_poweren_gpio: wifi-poweren-gpio { - rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm6 { - pinctrl-0 = <&pwm6m1_pins>; - status = "okay"; -}; - -&pwm15 { - pinctrl-0 = <&pwm15m1_pins>; - status = "okay"; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp3_out_dsi0>; -}; - -&route_dsi1 { - status = "disabled"; - connect = <&vp3_out_dsi1>; -}; - -&sata1 { - status = "okay"; -}; - -&sdmmc { - status = "okay"; - vmmc-supply = <&vcc_3v3_sd_s0>; -}; - -&spdif_tx5 { - status = "okay"; -}; - -&u2phy0_otg { - rockchip,typec-vbus-det; -}; - -&u2phy1_otg { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; -}; - -&uart8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>; -}; - -&usbdp_phy0 { - orientation-switch; - svid = <0xff01>; - sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - - port { - #address-cells = <1>; - #size-cells = <0>; - usbdp_phy0_orientation_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; - }; - - usbdp_phy0_dp_altmode_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&dp_altmode_mux>; - }; - }; -}; - -&usbdp_phy1 { - rockchip,dp-lane-mux = <2 3>; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - usb-role-switch; - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -&usbhost3_0 { - status = "disabled"; -}; - -&usbhost_dwc3_0 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb4-lp4-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb4-lp4-v10-linux.dts deleted file mode 100644 index 1777ee8c4..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb4-lp4-v10-linux.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-evb4-lp4.dtsi" -#include "rk3588-linux.dtsi" - -/ { - model = "Rockchip RK3588 EVB4 LP4 V10 Board"; - compatible = "rockchip,rk3588-evb4-lp4-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb4-lp4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb4-lp4-v10.dts deleted file mode 100644 index 043e77e55..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb4-lp4-v10.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-evb4-lp4.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588 EVB4 LP4 V10 Board"; - compatible = "rockchip,rk3588-evb4-lp4-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb4-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb4-lp4.dtsi deleted file mode 100644 index ef5dd8997..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb4-lp4.dtsi +++ /dev/null @@ -1,495 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include "dt-bindings/usb/pd.h" -#include "rk3588.dtsi" -#include "rk3588-evb.dtsi" -#include "rk3588-rk806-single.dtsi" - -/ { - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - pwms = <&pwm14 0 50000 0>; - cooling-levels = <0 50 100 150 200 255>; - rockchip,temp-trips = < - 50000 1 - 55000 2 - 60000 3 - 65000 4 - 70000 5 - >; - }; - - pcie30_avdd1v8: pcie30-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - pcie30_avdd0v75: pcie30-avdd0v75 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v75"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - vin-supply = <&avdd_0v75_s0>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma_trans: dma-trans@3c000000 { - reg = <0x0 0x3c000000 0x0 0x04000000>; - }; - }; - - vbus5v0_typec: vbus5v0-typec { - compatible = "regulator-fixed"; - regulator-name = "vbus5v0_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_au5426: vcc3v3-au5426 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_au5426"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_lcd_n: vcc3v3-lcd0-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd0_n"; - regulator-boot-on; - enable-active-high; - gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc_1v8_s3>; - }; - - vcc5v0_host: vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - }; -}; - -&backlight { - pwms = <&pwm3 0 25000 0>; - status = "okay"; -}; - -&dp0 { - status = "okay"; -}; - -&dp0_in_vp2 { - status = "okay"; -}; - -/* - * mipi_dcphy0 needs to be enabled - * when dsi0 is enabled - */ -&dsi0 { - status = "okay"; -}; - -&dsi0_in_vp2 { - status = "disabled"; -}; - -&dsi0_in_vp3 { - status = "okay"; -}; - -&dsi0_panel { - power-supply = <&vcc3v3_lcd_n>; - reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rst_gpio>; -}; - -&gmac0 { - /* Use rgmii-rxid mode to disable rx delay inside Soc */ - phy-mode = "rgmii-rxid"; - clock_in_out = "output"; - - snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - - tx_delay = <0x44>; - /* rx_delay = <0x4f>; */ - - phy-handle = <&rgmii_phy0>; - status = "okay"; -}; - -&gmac1 { - /* Use rgmii-rxid mode to disable rx delay inside Soc */ - phy-mode = "rgmii-rxid"; - clock_in_out = "output"; - - snps,reset-gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac1_miim - &gmac1_tx_bus2 - &gmac1_rx_bus2 - &gmac1_rgmii_clk - &gmac1_rgmii_bus>; - - tx_delay = <0x44>; - /* rx_delay = <0x4f>; */ - - phy-handle = <&rgmii_phy1>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - - vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big0_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { - compatible = "rockchip,rk8603"; - reg = <0x43>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big1_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - - vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_npu_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c6 { - status = "okay"; - gt1x: gt1x@14 { - compatible = "goodix,gt1x"; - reg = <0x14>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_gpio>; - goodix,rst-gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; - goodix,irq-gpio = <&gpio0 RK_PC6 IRQ_TYPE_LEVEL_LOW>; - power-supply = <&vcc3v3_lcd_n>; - }; -}; - -&i2c8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8m3_xfer>; - - usbc0: fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vbus5v0_typec>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - ; - source-pdos = - ; - - altmodes { - #address-cells = <1>; - #size-cells = <0>; - - altmode@0 { - reg = <0>; - svid = <0xff01>; - vdo = <0xffffffff>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; - }; - }; - - port@1 { - reg = <1>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; - }; - }; - }; - }; - }; -}; - -&mdio0 { - rgmii_phy0: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - }; -}; - -&mdio1 { - rgmii_phy1: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - }; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x4 { - compatible = "rockchip,rk3588-pcie-ep"; - memory-region = <&dma_trans>; - busno = <1>; -}; - -&pinctrl { - lcd { - lcd_rst_gpio: lcd-rst-gpio { - rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - touch { - touch_gpio: touch-gpio { - rockchip,pins = - <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>, - <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - usbc0_int: usbc0-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - typec5v_pwren: typec5v-pwren { - rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm3 { - status = "okay"; -}; - -&pwm14 { - pinctrl-0 = <&pwm14m1_pins>; - status = "okay"; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp3_out_dsi0>; -}; - -&u2phy2 { - status = "disabled"; -}; - -&u2phy3 { - status = "disabled"; -}; - -&u2phy1_otg { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy2_host { - status = "disabled"; -}; - -&u2phy3_host { - status = "disabled"; -}; - -&usb_host0_ehci { - status = "disabled"; -}; - -&usb_host0_ohci { - status = "disabled"; -}; - -&usb_host1_ehci { - status = "disabled"; -}; - -&usb_host1_ohci { - status = "disabled"; -}; - -&usbdp_phy0 { - orientation-switch; - svid = <0xff01>; - sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - - port { - #address-cells = <1>; - #size-cells = <0>; - usbdp_phy0_orientation_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; - }; - - usbdp_phy0_dp_altmode_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&dp_altmode_mux>; - }; - }; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - usb-role-switch; - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -&usbhost3_0 { - status = "disabled"; -}; - -&usbhost_dwc3_0 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4-v10-linux.dts deleted file mode 100644 index 6900d3be5..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4-v10-linux.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-evb5-lp4.dtsi" -#include "rk3588-linux.dtsi" - -/ { - model = "Rockchip RK3588 EVB4 LP4 V10 Board"; - compatible = "rockchip,rk3588-evb5-lp4-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4-v10.dts deleted file mode 100644 index 70e780396..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4-v10.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-evb5-lp4.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588 EVB4 LP4 V10 Board"; - compatible = "rockchip,rk3588-evb4-lp4-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4.dtsi deleted file mode 100644 index 8e783a987..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb5-lp4.dtsi +++ /dev/null @@ -1,290 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include "rk3588.dtsi" -#include "rk3588-evb.dtsi" -#include "rk3588-rk806-dual.dtsi" - -/ { - dsm_sound: dsm-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "rockchip,dsm-sound"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - sndcpu: simple-audio-card,cpu { - sound-dai = <&i2s3_2ch>; - }; - sndcodec: simple-audio-card,codec { - sound-dai = <&acdcdig_dsm>; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - pwms = <&pwm9 0 50000 0>; - cooling-levels = <0 50 100 150 200 255>; - rockchip,temp-trips = < - 50000 1 - 55000 2 - 60000 3 - 65000 4 - 70000 5 - >; - }; - - hdmiin_dc: hdmiin-dc { - compatible = "rockchip,dummy-codec"; - #sound-dai-cells = <0>; - }; - - hdmiin-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip,hdmiin"; - simple-audio-card,bitclock-master = <&dailink0_master>; - simple-audio-card,frame-master = <&dailink0_master>; - status = "okay"; - simple-audio-card,cpu { - sound-dai = <&i2s7_8ch>; - }; - dailink0_master: simple-audio-card,codec { - sound-dai = <&hdmiin_dc>; - }; - }; - - pcie20_avdd0v85: pcie20-avdd0v85 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd0v85"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&avdd_0v85_s0>; - }; - - pcie20_avdd1v8: pcie20-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - pcie30_avdd0v75: pcie30-avdd0v75 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v75"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - vin-supply = <&avdd_0v75_s0>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - vcc3v3_pcie30: vcc3v3-pcie30 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - vin-supply = <&vcc12v_dcin>; - }; -}; - -&acdcdig_dsm { - status = "okay"; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -/* - * mipi_dcphy0 needs to be enabled - * when dsi0 is enabled - */ -&dsi0 { - status = "disabled"; -}; - -&dsi0_in_vp2 { - status = "disabled"; -}; - -&dsi0_in_vp3 { - status = "okay"; -}; - -/* - * mipi_dcphy1 needs to be enabled - * when dsi1 is enabled - */ -&dsi1 { - status = "disabled"; -}; - -&dsi1_in_vp2 { - status = "disabled"; -}; - -&dsi1_in_vp3 { - status = "disabled"; -}; - -&hdmi1 { - enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi1_in_vp0 { - status = "okay"; -}; - -&hdmi1_sound { - status = "okay"; -}; - -&hdptxphy_hdmi1 { - status = "okay"; -}; - -&i2s3_2ch { - status = "okay"; - /delete-property/ pinctrl-names; - /delete-property/ pinctrl-0; -}; - -&i2s6_8ch { - status = "okay"; -}; - -&i2s7_8ch { - status = "okay"; -}; - -&mipi_dcphy0 { - status = "disabled"; -}; - -&mipi_dcphy1 { - status = "disabled"; -}; - -&pcie2x1l0 { - reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; -}; - -&pcie2x1l1 { - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; -}; - -&pcie2x1l2 { - reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; -}; - -&pcie30phy { - rockchip,pcie30-phymode = ; - status = "okay"; -}; - -&pcie3x2 { - reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; -}; - -&pcie3x4 { - num-lanes = <2>; - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; -}; - -&pwm9 { - pinctrl-0 = <&pwm9m2_pins>; - status = "okay"; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp3_out_dsi0>; -}; - -&route_dsi1 { - status = "disabled"; - connect = <&vp3_out_dsi1>; -}; - -&spdif_tx1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif1m0_tx>; -}; - -&spdif_tx1_dc { - status = "okay"; -}; - -&spdif_tx1_sound { - status = "okay"; -}; - -&usbdp_phy0 { - status = "disabled"; -}; - -&usbdp_phy0_dp { - status = "disabled"; -}; - -&usbdp_phy0_u3 { - status = "disabled"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "peripheral"; - phys = <&u2phy0_otg>; - phy-names = "usb2-phy"; - maximum-speed = "high-speed"; -}; - -&usbhost3_0 { - status = "disabled"; -}; - -&usbhost_dwc3_0 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb6-lp4-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb6-lp4-v10-linux.dts deleted file mode 100644 index ab7a51b71..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb6-lp4-v10-linux.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-evb6-lp4.dtsi" -#include "rk3588-linux.dtsi" - -/ { - model = "Rockchip RK3588 EVB6 LP4 V10 Board"; - compatible = "rockchip,rk3588-evb6-lp4-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb6-lp4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb6-lp4-v10.dts deleted file mode 100644 index 1a846acb5..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb6-lp4-v10.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-evb6-lp4.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588 EVB6 LP4 V10 Board"; - compatible = "rockchip,rk3588-evb6-lp4-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb6-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb6-lp4.dtsi deleted file mode 100644 index 96b7406c9..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb6-lp4.dtsi +++ /dev/null @@ -1,518 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include "dt-bindings/usb/pd.h" -#include "rk3588.dtsi" -#include "rk3588-evb.dtsi" -#include "rk3588-rk806-dual.dtsi" - -/ { - pcie20_avdd0v85: pcie20-avdd0v85 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd0v85"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&avdd_0v85_s0>; - }; - - pcie20_avdd1v8: pcie20-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - pcie30_avdd0v75: pcie30-avdd0v75 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v75"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - vin-supply = <&avdd_0v75_s0>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - vbus5v0_typec: vbus5v0-typec { - compatible = "regulator-fixed"; - regulator-name = "vbus5v0_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; - }; - - vcc3v3_lcd_n: vcc3v3-lcd0-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd0_n"; - regulator-boot-on; - enable-active-high; - gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc_1v8_s0>; - }; - - vcc3v3_pcie30: vcc3v3-pcie30 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_host: vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - }; - - vcc_mipicsi0: vcc-mipicsi0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipicsi0_pwr>; - regulator-name = "vcc_mipicsi0"; - enable-active-high; - }; - - vcc_mipicsi1: vcc-mipicsi1-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipicsi1_pwr>; - regulator-name = "vcc_mipicsi1"; - enable-active-high; - }; - - vcc_mipidcphy0: vcc-mipidcphy0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipidcphy0_pwr>; - regulator-name = "vcc_mipidcphy0"; - enable-active-high; - }; -}; - -&backlight { - pwms = <&pwm2 0 25000 0>; - status = "okay"; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&dp0 { - status = "okay"; -}; - -&dp0_in_vp2 { - status = "okay"; -}; - -&dp1 { - pinctrl-names = "default"; - pinctrl-0 = <&dp1_hpd>; - hpd-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&dp1_in_vp2 { - status = "okay"; -}; - -/* - * mipi_dcphy0 needs to be enabled - * when dsi0 is enabled - */ -&dsi0 { - status = "okay"; -}; - -&dsi0_in_vp2 { - status = "disabled"; -}; - -&dsi0_in_vp3 { - status = "okay"; -}; - -&dsi0_panel { - power-supply = <&vcc3v3_lcd_n>; - reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rst_gpio>; -}; - -/* - * mipi_dcphy1 needs to be enabled - * when dsi1 is enabled - */ -&dsi1 { - status = "disabled"; -}; - -&dsi1_in_vp2 { - status = "disabled"; -}; - -&dsi1_in_vp3 { - status = "disabled"; -}; - -&dsi1_panel { - power-supply = <&vcc3v3_lcd_n>; - - /* - * because in hardware, the two screens share the reset pin, - * so reset-gpios need only in dsi1 enable and dsi0 disabled - * case. - */ - - //reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; - //pinctrl-names = "default"; - //pinctrl-0 = <&lcd_rst_gpio>; -}; - -&hdmi0 { - enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi0_in_vp0 { - status = "okay"; -}; - -&hdmi0_sound { - status = "okay"; -}; - -&hdmi1 { - enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi1_in_vp1 { - status = "okay"; -}; - -&hdmi1_sound { - status = "okay"; -}; - -&hdptxphy_hdmi0 { - status = "okay"; -}; - -&hdptxphy_hdmi1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - usbc0: fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio3>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vbus5v0_typec>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - ; - source-pdos = - ; - - altmodes { - #address-cells = <1>; - #size-cells = <0>; - - altmode@0 { - reg = <0>; - svid = <0xff01>; - vdo = <0xffffffff>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; - }; - }; - - port@1 { - reg = <1>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; - }; - }; - }; - }; - }; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&i2c6 { - status = "okay"; - gt1x: gt1x@14 { - compatible = "goodix,gt1x"; - reg = <0x14>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_gpio>; - goodix,rst-gpio = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; - goodix,irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>; - power-supply = <&vcc3v3_lcd_n>; - }; -}; - -&i2s5_8ch { - status = "okay"; -}; - -&i2s6_8ch { - status = "okay"; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&mipi_dcphy1 { - status = "disabled"; -}; - -&pcie2x1l0 { - reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pcie30phy { - rockchip,pcie30-phymode = ; - status = "okay"; -}; - -&pcie3x4 { - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; -}; - -&pinctrl { - cam { - mipicsi0_pwr: mipicsi0-pwr { - rockchip,pins = - /* camera power en */ - <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - mipicsi1_pwr: mipicsi1-pwr { - rockchip,pins = - /* camera power en */ - <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - mipidcphy0_pwr: mipidcphy0-pwr { - rockchip,pins = - /* camera power en */ - <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - dp { - dp1_hpd: dp1-hpd { - rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lcd { - lcd_rst_gpio: lcd-rst-gpio { - rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - touch { - touch_gpio: touch-gpio { - rockchip,pins = - <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>, - <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - usbc0_int: usbc0-int { - rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - typec5v_pwren: typec5v-pwren { - rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm2 { - status = "okay"; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp3_out_dsi0>; -}; - -&route_dsi1 { - status = "disabled"; - connect = <&vp3_out_dsi1>; -}; - -&sata0 { - status = "okay"; -}; - -&u2phy0_otg { - rockchip,typec-vbus-det; -}; - -&u2phy1_otg { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; -}; - -&usbdp_phy0 { - orientation-switch; - svid = <0xff01>; - sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - - port { - #address-cells = <1>; - #size-cells = <0>; - usbdp_phy0_orientation_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; - }; - - usbdp_phy0_dp_altmode_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&dp_altmode_mux>; - }; - }; -}; - -&usbdp_phy1 { - rockchip,dp-lane-mux = <2 3>; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - usb-role-switch; - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -&usbhost3_0 { - status = "disabled"; -}; - -&usbhost_dwc3_0 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb7-cam-8x.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb7-cam-8x.dtsi deleted file mode 100644 index 3923d71cd..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb7-cam-8x.dtsi +++ /dev/null @@ -1,1198 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. - * - */ - -#include -#define LINK_FREQ 700000000 - - -&mipi_dcphy0 { - status = "okay"; -}; - -&mipi_dcphy1 { - status = "okay"; -}; - -&csi2_dcphy0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - csidcphy0_in: endpoint@1 { - reg = <1>; - remote-endpoint = <&rk1608_dphy0_out>; - data-lanes = <1 2>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidcphy0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi0_csi2_input>; - }; - }; - }; -}; - -&csi2_dcphy1 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - csidcphy1_in: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx464_out>; - data-lanes = <1 2>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidcphy1_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi1_csi2_input>; - }; - }; - }; -}; - -&csi2_dphy0_hw { - status = "okay"; -}; - -&csi2_dphy1_hw { - status = "okay"; -}; - -&csi2_dphy1 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy1_in: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx464_out0>; - data-lanes = <1 2>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy1_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi2_csi2_input>; - }; - }; - }; -}; - -&csi2_dphy2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy2_in: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx464_out1>; - data-lanes = <1 2>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy2_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi3_csi2_input>; - }; - }; - }; -}; - -&csi2_dphy4 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy4_in: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx464_out2>; - data-lanes = <1 2>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy4_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi4_csi2_input>; - }; - }; - }; -}; - -&csi2_dphy5 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy5_in: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx464_out3>; - data-lanes = <1 2>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy5_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi5_csi2_input>; - }; - }; - }; -}; - -&mipi0_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidcphy0_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in0>; - }; - }; - }; -}; - -&mipi1_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi1_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidcphy1_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi1_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in1>; - }; - }; - }; -}; - -&mipi2_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy1_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in2>; - }; - }; - }; -}; - -&mipi3_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi3_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy2_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi3_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in3>; - }; - }; - }; -}; - -&mipi4_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi4_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy4_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi4_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in4>; - }; - }; - }; -}; - -&mipi5_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi5_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy5_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi5_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in5>; - }; - }; - }; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds { - status = "okay"; - - port { - cif_mipi_in0: endpoint { - remote-endpoint = <&mipi0_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds_sditf { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - rockchip,combine-index = <0>; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - mipi_lvds_sditf_in: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx464_out7>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - mipi_lvds_sditf: endpoint@0 { - reg = <0>; - remote-endpoint = <&isp0_vir0>; - }; - }; - }; -}; - -&rkcif_mipi_lvds_sditf_vir1 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - rockchip,combine-index = <1>; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - mipi_lvds_sditf_vir1_in: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx464_out6>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - mipi_lvds_sditf_vir1: endpoint@0 { - reg = <0>; - remote-endpoint = <&isp0_vir3>; - }; - }; - }; -}; - -&rkcif_mipi_lvds_sditf_vir2 { - address-cells = <1>; - #size-cells = <0>; - status = "okay"; - rockchip,combine-index = <2>; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - mipi_lvds_sditf_vir2_in: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx464_out5>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - mipi_lvds_sditf_vir2: endpoint { - remote-endpoint = <&isp1_vir3>; - }; - }; - }; -}; - -&rkcif_mipi_lvds1_sditf { - status = "okay"; - - port { - mipi1_lvds_sditf: endpoint { - remote-endpoint = <&isp1_vir0>; - }; - }; -}; - -&rkcif_mipi_lvds1 { - status = "okay"; - - port { - cif_mipi_in1: endpoint { - remote-endpoint = <&mipi1_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds2 { - status = "okay"; - - port { - cif_mipi_in2: endpoint { - remote-endpoint = <&mipi2_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds2_sditf { - status = "okay"; - - port { - mipi2_lvds_sditf: endpoint { - remote-endpoint = <&isp0_vir1>; - }; - }; -}; - -&rkcif_mipi_lvds3 { - status = "okay"; - - port { - cif_mipi_in3: endpoint { - remote-endpoint = <&mipi3_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds3_sditf { - status = "okay"; - - port { - mipi3_lvds_sditf: endpoint { - remote-endpoint = <&isp1_vir1>; - }; - }; -}; - -&rkcif_mipi_lvds4 { - status = "okay"; - - port { - cif_mipi_in4: endpoint { - remote-endpoint = <&mipi4_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds4_sditf { - status = "okay"; - - port { - mipi4_lvds_sditf: endpoint { - remote-endpoint = <&isp0_vir2>; - }; - }; -}; - -&rkcif_mipi_lvds5 { - status = "okay"; - - port { - cif_mipi_in5: endpoint { - remote-endpoint = <&mipi5_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds5_sditf { - status = "okay"; - - port { - mipi5_lvds_sditf: endpoint { - remote-endpoint = <&isp1_vir2>; - }; - }; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp0 { - status = "okay"; -}; - -&isp0_mmu { - status = "okay"; -}; - -&rkisp0_vir0 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds_sditf>; - }; - }; -}; - -&rkisp0_vir1 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir1: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi2_lvds_sditf>; - }; - }; -}; - -&rkisp0_vir2 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir2: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi4_lvds_sditf>; - }; - }; -}; - -&rkisp0_vir3 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir3: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds_sditf_vir1>; - }; - }; -}; - -&rkisp1 { - status = "okay"; -}; - -&isp1_mmu { - status = "okay"; -}; - -&rkisp1_vir0 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp1_vir0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi1_lvds_sditf>; - }; - }; -}; - -&rkisp1_vir1 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp1_vir1: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi3_lvds_sditf>; - }; - }; -}; - -&rkisp1_vir2 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp1_vir2: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi5_lvds_sditf>; - }; - }; -}; - -&rkisp1_vir3 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp1_vir3: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds_sditf_vir2>; - }; - }; -}; - -&pinctrl { - cam { - vcc_cam_2_3_pwr: vcc_cam_2_3_pwr { - rockchip,pins = - /* camera power en */ - <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - vcc_cam_4_5_pwr: vcc_cam_4_5_pwr { - rockchip,pins = - /* camera power en */ - <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - vcc_cam_8_9_pwr: vcc_cam_8_9_pwr { - rockchip,pins = - /* camera power en */ - <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - - -/ { - cam_ircut0: cam_ircut { - status = "okay"; - compatible = "rockchip,ircut"; - ircut-open-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; - ircut-close-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - }; - - vcc_cam_2_3: vcc-cam-2-3 { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_cam_2_3_pwr>; - regulator-name = "vcc_cam_2_3"; - enable-active-high; - }; - - vcc_cam_4_5: vcc-cam-4-5 { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_cam_4_5_pwr>; - regulator-name = "vcc_cam_4_5"; - enable-active-high; - }; - - vcc_cam_8_9: vcc-cam-8-9 { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_cam_8_9_pwr>; - regulator-name = "vcc_cam_8_9"; - enable-active-high; - }; -}; - -&i2c7 { - status = "okay"; - pinctrl-0 = <&i2c7m0_xfer>; - - /* hardware cam 1 */ - imx464: imx464@10 { - compatible = "sony,imx464"; - reg = <0x10>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; - clock-names = "xvclk"; - pinctrl-names = "default"; - pinctrl-0 = <&mipim0_camera2_clk>; - power-domains = <&power RK3588_PD_VI>; - pwdn-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - avdd-supply = <&vcc_mipicsi1>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT1980-PX1"; - rockchip,camera-module-lens-name = "SHG102"; - port { - imx464_out: endpoint { - remote-endpoint = <&csidcphy1_in>; - data-lanes = <1 2>; - }; - }; - }; - - /* hardware cam 2 */ - imx464_0: imx464-0@1a { - compatible = "sony,imx464"; - status = "okay"; - reg = <0x1a>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipim0_camera3_clk>; - avdd-supply = <&vcc_cam_2_3>; - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT1980-PX1"; - rockchip,camera-module-lens-name = "SHG102"; - port { - imx464_out0: endpoint { - remote-endpoint = <&csidphy1_in>; - data-lanes = <1 2>; - }; - }; - }; - - /* hardware cam 3 */ - imx464_1: imx464-1@36 { - compatible = "sony,imx464"; - status = "okay"; - reg = <0x36>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - //pinctrl-names = "default"; - //pinctrl-0 = <&mipim0_camera3_clk>; //same - pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; - avdd-supply = <&vcc_cam_2_3>; - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT1980-PX1"; - rockchip,camera-module-lens-name = "SHG102"; - port { - imx464_out1: endpoint { - remote-endpoint = <&csidphy2_in>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&i2c4 { - status = "okay"; - pinctrl-0 = <&i2c4m1_xfer>; - - /* hardware cam 4 */ - imx464_2: imx464-2@1a { - compatible = "sony,imx464"; - status = "okay"; - reg = <0x1a>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - pinctrl-names = "default"; - pinctrl-0 = <&mipim0_camera4_clk>; - avdd-supply = <&vcc_cam_4_5>; - pwdn-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <3>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT1980-PX1"; - rockchip,camera-module-lens-name = "SHG102"; - port { - imx464_out2: endpoint { - remote-endpoint = <&csidphy4_in>; - data-lanes = <1 2>; - }; - }; - }; - - /* hardware cam 5 */ - imx464_3: imx464-3@36 { - compatible = "sony,imx464"; - status = "okay"; - reg = <0x36>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - //pinctrl-names = "default"; - //pinctrl-0 = <&mipim0_camera4_clk>; - avdd-supply = <&vcc_cam_4_5>; - pwdn-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <4>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT1980-PX1"; - rockchip,camera-module-lens-name = "SHG102"; - port { - imx464_out3: endpoint { - remote-endpoint = <&csidphy5_in>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&i2c2 { - status = "okay"; - pinctrl-0 = <&i2c2m4_xfer>; - - /* hardware cam 6 */ - imx464_4: imx464-4@1a { - compatible = "sony,imx464"; - status = "disabled"; - reg = <0x1a>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - //pinctrl-names = "default"; - //pinctrl-0 = <&mipim0_camera1_clk>; - avdd-supply = <&vcc_mipicsi0>; - pwdn-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <8>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT1980-PX1"; - rockchip,camera-module-lens-name = "SHG102"; - port { - imx464_out4: endpoint { - //remote-endpoint = <&mipi_lvds_sditf_vir3>; - data-lanes = <1 2>; - }; - }; - }; - - /* hardware cam 7 */ - imx464_5: imx464-5@36 { - compatible = "sony,imx464"; - status = "okay"; - reg = <0x36>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - pinctrl-names = "default"; - pinctrl-0 = <&mipim0_camera1_clk>; - avdd-supply = <&vcc_mipicsi0>; - pwdn-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <7>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT1980-PX1"; - rockchip,camera-module-lens-name = "SHG102"; - port { - imx464_out5: endpoint { - remote-endpoint = <&mipi_lvds_sditf_vir2_in>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3m0_xfer>; - - /* hardware cam 8 */ - imx464_6: imx464-6@1a { - compatible = "sony,imx464"; - status = "okay"; - reg = <0x1a>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - //pinctrl-names = "default"; - //pinctrl-0 = <&mipim0_camera1_clk>; - avdd-supply = <&vcc_cam_8_9>; - pwdn-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <6>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT1980-PX1"; - rockchip,camera-module-lens-name = "SHG102"; - port { - imx464_out6: endpoint { - remote-endpoint = <&mipi_lvds_sditf_vir1_in>; - data-lanes = <1 2>; - }; - }; - }; - - /* hardware cam 9 */ - imx464_7: imx464-7@36 { - compatible = "sony,imx464"; - status = "okay"; - reg = <0x36>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - //pinctrl-names = "default"; - //pinctrl-0 = <&mipim0_camera1_clk>; - avdd-supply = <&vcc_cam_8_9>; - pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <5>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT1980-PX1"; - rockchip,camera-module-lens-name = "SHG102"; - port { - imx464_out7: endpoint { - remote-endpoint = <&mipi_lvds_sditf_in>; - data-lanes = <1 2>; - }; - }; - }; - - preisp_dmy: preisp_dmy@37 { - status = "okay"; - compatible = "pisp_dmy"; - reg = <0x37>; - - clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; - clock-names = "xvclk"; - - rockchip,camera-module-index = <10>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT1980-PX1"; - rockchip,camera-module-lens-name = "SHG102"; - port { - preisp_dmy_out0: endpoint { - remote-endpoint = <&rk1608_in0>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&spi4 { - status = "okay"; - //assigned-clocks = <&cru CLK_SPI0>; - //assigned-clock-rates = <100000000>; - //rx-sample-delay-ns = <10>; - //dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi4m1_cs0 &spi4m1_cs1 &spi4m1_pins>; - - spi_rk1608@0 { - compatible = "rockchip,rk1608"; - status = "okay"; - reg = <0>; - spi-max-frequency = <50000000>; - spi-min-frequency = <16000000>; - - clocks = <&cru CLK_SPI4>; - clock-names = "mclk"; - - firmware-names = "rk1608.rkl"; - - reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; - irq-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; - //wake-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - pwren-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&preisp_irq_gpios &preisp_pwren_gpios - &preisp_reset_gpios &refclk_pins>; - - /* regulator config */ - vdd-core-regulator = "vdd_preisp"; - vdd-core-microvolt = <1150000>; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <0>; - rk1608_out0: endpoint@0 { - reg = <0>; - remote-endpoint = <&rk1608_dphy0_in>; - }; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - rk1608_in0: endpoint@0 { - reg = <0>; - remote-endpoint = <&preisp_dmy_out0>; - }; - }; - }; - }; -}; - -&pinctrl { - rk1608_gpios { - preisp_irq_gpios: preisp-irq-gpios { - rockchip,pins = - <1 RK_PC4 0 &pcfg_pull_up>; - }; - preisp_reset_gpios: preisp-reset-gpios { - rockchip,pins = - <1 RK_PD5 0 &pcfg_output_low>; - }; - preisp_pwren_gpios: preisp-pwren-gpios { - rockchip,pins = - <1 RK_PC7 0 &pcfg_pull_up>; - }; - }; -}; - -/{ - mipidphy0: mipidphy0 { - compatible = "rockchip,rk1608-dphy"; - status = "okay"; - //rockchip,grf = <&grf>; - id = <0>; - - cam_nums = <1>; - in_mipi = <1>; - out_mipi = <0>; - link-freqs = /bits/ 64 ; - - /* rk1608 i2c mode */ - sensor_i2c_bus = <3>; - sensor_i2c_addr = <0x36>; - sensor-name = "IMX464"; - - rockchip,camera-module-index = <9>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "TongJu"; - rockchip,camera-module-lens-name = "CHT842-MD"; - - /* virtual-sensor mode */ - link-sensor = <&imx464_7>; - virtual-sub-sensor-config-0 { - id = <1>; - in_mipi = <2>; - out_mipi = <1>; - }; - virtual-sub-sensor-config-1 { - id = <2>; - in_mipi = <3>; - out_mipi = <1>; - }; - /* multi-sensor mode end */ - - format-config-0 { - data_type = <0x2b>; - mipi_lane = <2>; - mipi_lane_out = <4>; - field = <1>; - colorspace = <8>; - code = ; - width = <2712>; - height= <1538>; - hactive = <2712>; - vactive = <4614>; - htotal = <3616>; - vtotal = <4710>; - inch0-info = <2712 1538 0x2b 0x2b 1>; - outch0-info = <2712 4614 0x2b 0x2b 1>; - hcrop = <2560>; - vcrop = <1520>; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - rk1608_dphy0_in: endpoint { - remote-endpoint = <&rk1608_out0>; - data-lanes = <1 2 3 4>; - }; - }; - port@1 { - rk1608_dphy0_out: endpoint { - remote-endpoint = <&csidcphy0_in>; - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - clock-noncontinuous; - link-freqs = /bits/ 64 ; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb7-imx415.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb7-imx415.dtsi deleted file mode 100644 index f53898911..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb7-imx415.dtsi +++ /dev/null @@ -1,176 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. - * - */ - -/ { - cam_ircut0: cam_ircut { - status = "okay"; - compatible = "rockchip,ircut"; - ircut-open-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; - ircut-close-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - }; - vcc_mipidphy0: vcc-mipidcphy0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipidphy0_pwr>; - regulator-name = "vcc_mipidphy0"; - enable-active-high; - }; -}; - -&csi2_dphy0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipidphy0_in_ucam0: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx415_out0>; - data-lanes = <1 2 3 4>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi2_csi2_input>; - }; - }; - }; -}; - -&csi2_dphy0_hw { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - - imx415: imx415@1a { - compatible = "sony,imx415"; - reg = <0x1a>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; - clock-names = "xvclk"; - pinctrl-names = "default"; - pinctrl-0 = <&mipim0_camera3_clk>; - power-domains = <&power RK3588_PD_VI>; - pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; - avdd-supply = <&vcc_mipidphy0>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT2022-PX1"; - rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; - lens-focus = <&cam_ircut0>; - port { - imx415_out0: endpoint { - remote-endpoint = <&mipidphy0_in_ucam0>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&mipi2_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy0_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi2_in0>; - }; - }; - }; -}; - -&pinctrl { - cam { - mipidphy0_pwr: mipidphy0-pwr { - rockchip,pins = - /* camera power en */ - <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds2 { - status = "okay"; - - port { - cif_mipi2_in0: endpoint { - remote-endpoint = <&mipi2_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds2_sditf { - status = "okay"; - - port { - mipi_lvds2_sditf: endpoint { - remote-endpoint = <&isp0_vir0>; - }; - }; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp0 { - status = "okay"; -}; - -&isp0_mmu { - status = "okay"; -}; - -&rkisp0_vir0 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds2_sditf>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4-v10-linux.dts deleted file mode 100644 index 6d740f150..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4-v10-linux.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-evb7-lp4.dtsi" -#include "rk3588-evb7-imx415.dtsi" -#include "rk3588-linux.dtsi" - -/ { - model = "Rockchip RK3588 EVB7 LP4 V10 Board"; - compatible = "rockchip,rk3588-evb7-lp4-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4-v10-rk1608-ipc-8x-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4-v10-rk1608-ipc-8x-linux.dts deleted file mode 100644 index fc23e31ff..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4-v10-rk1608-ipc-8x-linux.dts +++ /dev/null @@ -1,192 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-evb7-lp4.dtsi" -#include "rk3588-ipc.dtsi" -#include "rk3588-evb7-cam-8x.dtsi" - -/ { - model = "Rockchip RK3588-RK1608 EVB7 LP4 V10 Board"; - compatible = "rk3588-evb7-lp4-v10-rk1608-ipc-8x-linux", "rockchip,rk3588"; -}; - -&backlight { - status = "disabled"; -}; - -&dp0 { - status = "disabled"; -}; - -&dp0_in_vp2 { - status = "disabled"; -}; - -&dp1 { - status = "disabled"; -}; - -&dp1_in_vp2 { - status = "disabled"; -}; - -&dsi0 { - status = "disabled"; -}; - -&dsi0_in_vp3 { - status = "disabled"; -}; - -&dsi0_panel { - status = "disabled"; -}; - -&dsi1_panel { - status = "disabled"; -}; - ->1x { - status = "disabled"; -}; - -&hdmi0 { - status = "disabled"; -}; - -&hdmi0_in_vp0 { - status = "disabled"; -}; - -&hdmi0_sound { - status = "disabled"; -}; - -&hdmi1 { - status = "disabled"; -}; - -&hdmi1_in_vp1 { - status = "disabled"; -}; - -&hdmi1_sound { - status = "disabled"; -}; - -&hdptxphy_hdmi0 { - status = "disabled"; -}; - -&hdptxphy_hdmi1 { - status = "disabled"; -}; - -&i2c6 { - status = "disabled"; -}; - -&i2s5_8ch { - status = "disabled"; -}; - -&i2s6_8ch { - status = "disabled"; -}; - -&jpegd { - status = "disabled"; -}; - -&jpegd_mmu { - status = "disabled"; -}; - -&leds { - status = "disabled"; -}; - -&pwm2 { - status = "disabled"; -}; - -&rkvdec0 { - status = "disabled"; -}; - -&rkvdec0_mmu { - status = "disabled"; -}; - -&rkvdec1_mmu { - status = "disabled"; -}; - -&rkvdec_ccu { - status = "disabled"; -}; - -&rk_headset { - status = "disabled"; -}; - -&sata0 { - status = "disabled"; -}; - -&uart8 { - status = "disabled"; -}; - -&vdpu { - status = "disabled"; -}; - -&vdpu_mmu { - status = "disabled"; -}; - -&wireless_bluetooth { - status = "disabled"; -}; - -&wireless_wlan { - status = "disabled"; -}; - -&es8388_sound { - status = "disabled"; -}; - -&hdmirx_ctrler { - status = "disabled"; -}; - -&gmac1 { - status = "disabled"; -}; - -&uart9 { - status = "disabled"; -}; - -&i2s0_8ch { - status = "disabled"; -}; - -&sdmmc { - status = "disabled"; -}; - -&sdio { - status = "disabled"; -}; - -&sdio_pwrseq { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4-v10.dts deleted file mode 100644 index a574681f9..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4-v10.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-evb7-lp4.dtsi" -#include "rk3588-evb7-imx415.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588 EVB7 LP4 V10 Board"; - compatible = "rockchip,rk3588-evb7-lp4-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4-v11-linux-ipc.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4-v11-linux-ipc.dts deleted file mode 100644 index 74cf867cd..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4-v11-linux-ipc.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-evb7-lp4.dtsi" -#include "rk3588-evb7-imx415.dtsi" -#include "rk3588-ipc.dtsi" - -/ { - model = "Rockchip RK3588 EVB7 LP4 V11 Board"; - compatible = "rockchip,rk3588-evb7-lp4-v11-linux-ipc", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi deleted file mode 100644 index 742d57254..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb7-lp4.dtsi +++ /dev/null @@ -1,846 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include "dt-bindings/usb/pd.h" -#include "rk3588.dtsi" -#include "rk3588-evb.dtsi" -#include "rk3588-rk806-single.dtsi" - -/ { - /* If hdmirx node is disabled, delete the reserved-memory node here. */ - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* Reserve 128MB memory for hdmirx-controller@fdee0000 */ - cma { - compatible = "shared-dma-pool"; - reusable; - reg = <0x0 (256 * 0x100000) 0x0 (128 * 0x100000)>; - linux,cma-default; - }; - }; - - es8388_sound: es8388-sound { - status = "okay"; - compatible = "rockchip,multicodecs-card"; - rockchip,card-name = "rockchip-es8388"; - hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; - io-channels = <&saradc 3>; - io-channel-names = "adc-detect"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - spk-con-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - hp-con-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - rockchip,format = "i2s"; - rockchip,mclk-fs = <256>; - rockchip,cpu = <&i2s0_8ch>; - rockchip,codec = <&es8388>; - rockchip,audio-routing = - "Headphone", "LOUT1", - "Headphone", "ROUT1", - "Speaker", "LOUT2", - "Speaker", "ROUT2", - "Headphone", "Headphone Power", - "Headphone", "Headphone Power", - "Speaker", "Speaker Power", - "Speaker", "Speaker Power", - "LINPUT1", "Main Mic", - "LINPUT2", "Main Mic", - "RINPUT1", "Headset Mic", - "RINPUT2", "Headset Mic"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - play-pause-key { - label = "playpause"; - linux,code = ; - press-threshold-microvolt = <2000>; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - pwms = <&pwm3 0 50000 0>; - cooling-levels = <0 50 100 150 200 255>; - rockchip,temp-trips = < - 50000 1 - 55000 2 - 60000 3 - 65000 4 - 70000 5 - >; - }; - - hdmiin-sound { - compatible = "rockchip,hdmi"; - rockchip,mclk-fs = <128>; - rockchip,format = "i2s"; - rockchip,bitclock-master = <&hdmirx_ctrler>; - rockchip,frame-master = <&hdmirx_ctrler>; - rockchip,card-name = "rockchip,hdmiin"; - rockchip,cpu = <&i2s7_8ch>; - rockchip,codec = <&hdmirx_ctrler 0>; - rockchip,jack-det; - }; - - pcie20_avdd0v85: pcie20-avdd0v85 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd0v85"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&vdd_0v85_s0>; - }; - - pcie20_avdd1v8: pcie20-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - pcie30_avdd0v75: pcie30-avdd0v75 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v75"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - vin-supply = <&avdd_0v75_s0>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - post-power-on-delay-ms = <200>; - reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; - }; - - rk_headset: rk-headset { - status = "disabled"; - compatible = "rockchip_headset"; - headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - io-channels = <&saradc 3>; - }; - - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_lcd_n: vcc3v3-lcd0-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd0_n"; - regulator-boot-on; - enable-active-high; - gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc_1v8_s0>; - }; - - vcc3v3_pcie30: vcc3v3-pcie30 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_host: vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - }; - - vcc_mipicsi0: vcc-mipicsi0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipicsi0_pwr>; - regulator-name = "vcc_mipicsi0"; - enable-active-high; - }; - - vcc_mipicsi1: vcc-mipicsi1-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipicsi1_pwr>; - regulator-name = "vcc_mipicsi1"; - enable-active-high; - }; - - vcc_mipidcphy0: vcc-mipidcphy0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipidcphy0_pwr>; - regulator-name = "vcc_mipidcphy0"; - enable-active-high; - }; - - vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sd_s0_pwr>; - regulator-name = "vcc_3v3_sd_s0"; - enable-active-high; - }; - - wireless_bluetooth: wireless-bluetooth { - compatible = "bluetooth-platdata"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "rts_gpio"; - pinctrl-0 = <&uart9m0_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; - pinctrl-1 = <&uart9_gpios>; - BT,reset_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - BT,wake_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - BT,wake_host_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - wifi_chip_type = "ap6398s"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_irq>; - WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; - WIFI,poweren_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; -}; - -&backlight { - pwms = <&pwm1 0 25000 0>; - status = "okay"; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&dp0 { - pinctrl-names = "default"; - pinctrl-0 = <&vga_hpdin_l>; - hpd-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&dp0_in_vp2 { - status = "okay"; -}; - -&dp1 { - pinctrl-names = "default"; - pinctrl-0 = <&dp1m0_pins>; - status = "okay"; -}; - -&dp1_in_vp2 { - status = "okay"; -}; - -/* - * mipi_dcphy0 needs to be enabled - * when dsi0 is enabled - */ -&dsi0 { - status = "okay"; -}; - -&dsi0_in_vp2 { - status = "disabled"; -}; - -&dsi0_in_vp3 { - status = "okay"; -}; - -&dsi0_panel { - power-supply = <&vcc3v3_lcd_n>; - reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rst_gpio>; -}; - -/* - * mipi_dcphy1 needs to be enabled - * when dsi1 is enabled - */ -&dsi1 { - status = "disabled"; -}; - -&dsi1_in_vp2 { - status = "disabled"; -}; - -&dsi1_in_vp3 { - status = "disabled"; -}; - -&dsi1_panel { - power-supply = <&vcc3v3_lcd_n>; - - /* - * because in hardware, the two screens share the reset pin, - * so reset-gpios need only in dsi1 enable and dsi0 disabled - * case. - */ - - //reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; - //pinctrl-names = "default"; - //pinctrl-0 = <&lcd_rst_gpio>; -}; - -&gmac1 { - /* Use rgmii-rxid mode to disable rx delay inside Soc */ - phy-mode = "rgmii-rxid"; - clock_in_out = "output"; - - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac1_miim - &gmac1_tx_bus2 - &gmac1_rx_bus2 - &gmac1_rgmii_clk - &gmac1_rgmii_bus>; - - tx_delay = <0x43>; - /* rx_delay = <0x3f>; */ - - phy-handle = <&rgmii_phy>; - status = "okay"; -}; - -&hdmi0 { - enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi0_in_vp0 { - status = "okay"; -}; - -&hdmi0_sound { - status = "okay"; -}; - -&hdmi1 { - enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi1_in_vp1 { - status = "okay"; -}; - -&hdmi1_sound { - status = "okay"; -}; - -/* Should work with at least 128MB cma reserved above. */ -&hdmirx_ctrler { - status = "okay"; - - #sound-dai-cells = <1>; - /* Effective level used to trigger HPD: 0-low, 1-high */ - hpd-trigger-level = <1>; - hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmim1_rx &hdmirx_det>; -}; - -&hdptxphy_hdmi0 { - status = "okay"; -}; - -&hdptxphy_hdmi1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - - vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big0_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { - compatible = "rockchip,rk8603"; - reg = <0x43>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big1_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1m2_xfer>; - - vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_npu_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c4 { - status = "okay"; - pinctrl-0 = <&i2c4m1_xfer>; - - ls_stk3332: light@47 { - compatible = "ls_stk3332"; - status = "disabled"; - reg = <0x47>; - type = ; - irq_enable = <0>; - als_threshold_high = <100>; - als_threshold_low = <10>; - als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ - poll_delay_ms = <100>; - }; - - ps_stk3332: proximity@47 { - compatible = "ps_stk3332"; - status = "disabled"; - reg = <0x47>; - type = ; - //pinctrl-names = "default"; - //pinctrl-0 = <&gpio3_c6>; - //irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>; - //irq_enable = <1>; - ps_threshold_high = <0x200>; - ps_threshold_low = <0x100>; - ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */ - ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/ - poll_delay_ms = <100>; - }; - - icm42607_acc: icm_acc@68 { - status = "okay"; - compatible = "icm42607_acc"; - reg = <0x68>; - irq-gpio = <&gpio4 RK_PC2 IRQ_TYPE_EDGE_RISING>; - irq_enable = <0>; - poll_delay_ms = <30>; - type = ; - layout = <0>; - }; - - icm42607_gyro: icm_gyro@68 { - status = "okay"; - compatible = "icm42607_gyro"; - reg = <0x68>; - poll_delay_ms = <30>; - type = ; - layout = <0>; - }; -}; - -&i2c5 { - status = "okay"; - gt1x: gt1x@14 { - compatible = "goodix,gt1x"; - reg = <0x14>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_gpio>; - goodix,rst-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; - goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>; - power-supply = <&vcc3v3_lcd_n>; - }; -}; - -&i2c6 { - status = "okay"; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&i2c7 { - status = "okay"; - es8388: es8388@11 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "everest,es8388", "everest,es8323"; - reg = <0x11>; - clocks = <&mclkout_i2s0>; - clock-names = "mclk"; - assigned-clocks = <&mclkout_i2s0>; - assigned-clock-rates = <12288000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk>; - }; -}; - -&i2s2_2ch { - pinctrl-0 = <&i2s2m0_sclk &i2s2m0_lrck &i2s2m0_sdi &i2s2m0_sdo>; - status = "disabled"; -}; - -&i2s5_8ch { - status = "okay"; -}; - -&i2s6_8ch { - status = "okay"; -}; - -&i2s7_8ch { - status = "okay"; -}; - -&mdio1 { - rgmii_phy: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - }; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&mipi_dcphy1 { - status = "disabled"; -}; - -&pcie2x1l0 { - reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pcie30phy { - rockchip,pcie30-phymode = ; - status = "okay"; -}; - -&pcie3x4 { - reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; -}; - -&pinctrl { - cam { - mipicsi0_pwr: mipicsi0-pwr { - rockchip,pins = - /* camera power en */ - <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - mipicsi1_pwr: mipicsi1-pwr { - rockchip,pins = - /* camera power en */ - <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - mipidcphy0_pwr: mipidcphy0-pwr { - rockchip,pins = - /* camera power en */ - <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - vga { - vga_hpdin_l: vga-hpdin-l { - rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi { - hdmirx_det: hdmirx-det { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - headphone { - hp_det: hp-det { - rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lcd { - lcd_rst_gpio: lcd-rst-gpio { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdmmc { - sd_s0_pwr: sd-s0-pwr { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - touch { - touch_gpio: touch-gpio { - rockchip,pins = - <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>, - <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - - wireless-bluetooth { - uart9_gpios: uart9-gpios { - rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reset_gpio: bt-reset-gpio { - rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_gpio: bt-wake-gpio { - rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_irq_gpio: bt-irq-gpio { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm3 { - pinctrl-0 = <&pwm3m1_pins>; - status = "okay"; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp3_out_dsi0>; -}; - -&route_dsi1 { - status = "disabled"; - connect = <&vp3_out_dsi1>; -}; - -&route_hdmi0 { - status = "okay"; -}; - -&route_hdmi1 { - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -&sdio { - max-frequency = <150000000>; - no-sd; - no-mmc; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdiom0_pins>; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdmmc { - status = "okay"; - vmmc-supply = <&vcc_3v3_sd_s0>; -}; - -&uart9 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&u2phy1_otg { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; -}; - -&usbdp_phy0 { - rockchip,dp-lane-mux = <2 3>; - status = "okay"; -}; - -&usbdp_phy0_dp { - status = "okay"; -}; - -&usbdp_phy0_u3 { - status = "okay"; -}; - -&usbdp_phy1 { - rockchip,dp-lane-mux = <3 2 1 0>; - status = "okay"; -}; - -&usbdp_phy1_dp { - status = "okay"; -}; - -&usbdp_phy1_u3 { - maximum-speed = "high-speed"; - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - extcon = <&u2phy0>; - status = "okay"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; - maximum-speed = "high-speed"; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11-imx415.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11-imx415.dtsi deleted file mode 100644 index d5772ebb9..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11-imx415.dtsi +++ /dev/null @@ -1,176 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Rockchip Electronics Co., Ltd. - * - */ - -/ { - cam_ircut0: cam_ircut { - status = "okay"; - compatible = "rockchip,ircut"; - ircut-open-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; - ircut-close-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - }; - vcc_mipidphy0: vcc-mipidcphy0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipidphy0_pwr>; - regulator-name = "vcc_mipidphy0"; - enable-active-high; - }; -}; - -&csi2_dphy0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipidphy0_in_ucam0: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx415_out0>; - data-lanes = <1 2 3 4>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi2_csi2_input>; - }; - }; - }; -}; - -&csi2_dphy0_hw { - status = "okay"; -}; - -&i2c3 { - status = "okay"; - - imx415: imx415@1a { - compatible = "sony,imx415"; - reg = <0x1a>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; - clock-names = "xvclk"; - pinctrl-names = "default"; - pinctrl-0 = <&mipim0_camera3_clk>; - power-domains = <&power RK3588_PD_VI>; - pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; - avdd-supply = <&vcc_mipidphy0>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT2022-PX1"; - rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; - lens-focus = <&cam_ircut0>; - port { - imx415_out0: endpoint { - remote-endpoint = <&mipidphy0_in_ucam0>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&mipi2_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy0_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi2_in0>; - }; - }; - }; -}; - -&pinctrl { - cam { - mipidphy0_pwr: mipidphy0-pwr { - rockchip,pins = - /* camera power en */ - <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds2 { - status = "okay"; - - port { - cif_mipi2_in0: endpoint { - remote-endpoint = <&mipi2_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds2_sditf { - status = "okay"; - - port { - mipi_lvds2_sditf: endpoint { - remote-endpoint = <&isp0_vir0>; - }; - }; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp0 { - status = "okay"; -}; - -&isp0_mmu { - status = "okay"; -}; - -&rkisp0_vir0 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds2_sditf>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11-linux.dts deleted file mode 100644 index f4051df93..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11-linux.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-evb7-v11.dtsi" -#include "rk3588-evb7-v11-imx415.dtsi" -#include "rk3588-linux.dtsi" - -/ { - model = "Rockchip RK3588 EVB7 V11 Board"; - compatible = "rockchip,rk3588-evb7-v11", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11.dts deleted file mode 100644 index 24ef507c8..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-evb7-v11.dtsi" -#include "rk3588-evb7-v11-imx415.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588 EVB7 V11 Board"; - compatible = "rockchip,rk3588-evb7-v11", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11.dtsi deleted file mode 100644 index 5bef2102f..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb7-v11.dtsi +++ /dev/null @@ -1,949 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. - * - */ - -#include "dt-bindings/usb/pd.h" -#include "rk3588.dtsi" -#include "rk3588-evb.dtsi" -#include "rk3588-rk806-single.dtsi" - -/ { - /* If hdmirx node is disabled, delete the reserved-memory node here. */ - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* Reserve 128MB memory for hdmirx-controller@fdee0000 */ - cma { - compatible = "shared-dma-pool"; - reusable; - reg = <0x0 (256 * 0x100000) 0x0 (128 * 0x100000)>; - linux,cma-default; - }; - }; - - es8388_sound: es8388-sound { - status = "okay"; - compatible = "rockchip,multicodecs-card"; - rockchip,card-name = "rockchip-es8388"; - hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; - io-channels = <&saradc 3>; - io-channel-names = "adc-detect"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - spk-con-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - hp-con-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - rockchip,format = "i2s"; - rockchip,mclk-fs = <256>; - rockchip,cpu = <&i2s0_8ch>; - rockchip,codec = <&es8388>; - rockchip,audio-routing = - "Headphone", "LOUT1", - "Headphone", "ROUT1", - "Speaker", "LOUT2", - "Speaker", "ROUT2", - "Headphone", "Headphone Power", - "Headphone", "Headphone Power", - "Speaker", "Speaker Power", - "Speaker", "Speaker Power", - "LINPUT1", "Main Mic", - "LINPUT2", "Main Mic", - "RINPUT1", "Headset Mic", - "RINPUT2", "Headset Mic"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - play-pause-key { - label = "playpause"; - linux,code = ; - press-threshold-microvolt = <2000>; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - pwms = <&pwm3 0 50000 0>; - cooling-levels = <0 50 100 150 200 255>; - rockchip,temp-trips = < - 50000 1 - 55000 2 - 60000 3 - 65000 4 - 70000 5 - >; - }; - - hdmiin-sound { - compatible = "rockchip,hdmi"; - rockchip,mclk-fs = <128>; - rockchip,format = "i2s"; - rockchip,bitclock-master = <&hdmirx_ctrler>; - rockchip,frame-master = <&hdmirx_ctrler>; - rockchip,card-name = "rockchip,hdmiin"; - rockchip,cpu = <&i2s7_8ch>; - rockchip,codec = <&hdmirx_ctrler 0>; - rockchip,jack-det; - }; - - pcie20_avdd0v85: pcie20-avdd0v85 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd0v85"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&vdd_0v85_s0>; - }; - - pcie20_avdd1v8: pcie20-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - pcie30_avdd0v75: pcie30-avdd0v75 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v75"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - vin-supply = <&avdd_0v75_s0>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - post-power-on-delay-ms = <200>; - reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; - }; - - rk_headset: rk-headset { - status = "disabled"; - compatible = "rockchip_headset"; - headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - io-channels = <&saradc 3>; - }; - - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; - - vbus5v0_typec: vbus5v0-typec { - compatible = "regulator-fixed"; - regulator-name = "vbus5v0_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; - }; - - vcc3v3_lcd_n: vcc3v3-lcd0-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd0_n"; - regulator-boot-on; - enable-active-high; - gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc_1v8_s0>; - }; - - vcc3v3_pcie30: vcc3v3-pcie30 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_host: vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - }; - - vcc_mipicsi0: vcc-mipicsi0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipicsi0_pwr>; - regulator-name = "vcc_mipicsi0"; - enable-active-high; - }; - - vcc_mipicsi1: vcc-mipicsi1-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipicsi1_pwr>; - regulator-name = "vcc_mipicsi1"; - enable-active-high; - }; - - vcc_mipidcphy0: vcc-mipidcphy0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipidcphy0_pwr>; - regulator-name = "vcc_mipidcphy0"; - enable-active-high; - }; - - vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sd_s0_pwr>; - regulator-name = "vcc_3v3_sd_s0"; - enable-active-high; - }; - - wireless_bluetooth: wireless-bluetooth { - compatible = "bluetooth-platdata"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "rts_gpio"; - pinctrl-0 = <&uart9m0_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; - pinctrl-1 = <&uart9_gpios>; - BT,reset_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - BT,wake_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - BT,wake_host_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - wifi_chip_type = "ap6398s"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_irq>; - WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; - WIFI,poweren_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; -}; - -&backlight { - pwms = <&pwm1 0 25000 0>; - status = "okay"; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&dp0 { - status = "okay"; -}; -&dp0_in_vp2 { - status = "okay"; -}; - -&dp0_sound{ - status = "okay"; -}; -&dp1 { - pinctrl-names = "default"; - pinctrl-0 = <&dp1m0_pins>; - status = "okay"; -}; - -&dp1_in_vp2 { - status = "okay"; -}; - -/* - * mipi_dcphy0 needs to be enabled - * when dsi0 is enabled - */ -&dsi0 { - status = "okay"; -}; - -&dsi0_in_vp2 { - status = "disabled"; -}; - -&dsi0_in_vp3 { - status = "okay"; -}; - -&dsi0_panel { - power-supply = <&vcc3v3_lcd_n>; - reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rst_gpio>; -}; - -/* - * mipi_dcphy1 needs to be enabled - * when dsi1 is enabled - */ -&dsi1 { - status = "disabled"; -}; - -&dsi1_in_vp2 { - status = "disabled"; -}; - -&dsi1_in_vp3 { - status = "disabled"; -}; - -&dsi1_panel { - power-supply = <&vcc3v3_lcd_n>; - - /* - * because in hardware, the two screens share the reset pin, - * so reset-gpios need only in dsi1 enable and dsi0 disabled - * case. - */ - - //reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; - //pinctrl-names = "default"; - //pinctrl-0 = <&lcd_rst_gpio>; -}; - -&gmac1 { - /* Use rgmii-rxid mode to disable rx delay inside Soc */ - phy-mode = "rgmii-rxid"; - clock_in_out = "output"; - - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac1_miim - &gmac1_tx_bus2 - &gmac1_rx_bus2 - &gmac1_rgmii_clk - &gmac1_rgmii_bus>; - - tx_delay = <0x43>; - /* rx_delay = <0x3f>; */ - - phy-handle = <&rgmii_phy>; - status = "okay"; -}; - -&hdmi0 { - enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi0_in_vp0 { - status = "okay"; -}; - -&hdmi0_sound { - status = "okay"; -}; - -&hdmi1 { - enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi1_in_vp1 { - status = "okay"; -}; - -&hdmi1_sound { - status = "okay"; -}; - -/* Should work with at least 128MB cma reserved above. */ -&hdmirx_ctrler { - status = "okay"; - - #sound-dai-cells = <1>; - /* Effective level used to trigger HPD: 0-low, 1-high */ - hpd-trigger-level = <1>; - hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmim1_rx &hdmirx_det>; -}; - -&hdptxphy_hdmi0 { - status = "okay"; -}; - -&hdptxphy_hdmi1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - - vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big0_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { - compatible = "rockchip,rk8603"; - reg = <0x43>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big1_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1m2_xfer>; - - vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_npu_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c4 { - status = "okay"; - pinctrl-0 = <&i2c4m1_xfer>; - - ls_stk3332: light@47 { - compatible = "ls_stk3332"; - status = "disabled"; - reg = <0x47>; - type = ; - irq_enable = <0>; - als_threshold_high = <100>; - als_threshold_low = <10>; - als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ - poll_delay_ms = <100>; - }; - - ps_stk3332: proximity@47 { - compatible = "ps_stk3332"; - status = "disabled"; - reg = <0x47>; - type = ; - //pinctrl-names = "default"; - //pinctrl-0 = <&gpio3_c6>; - //irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>; - //irq_enable = <1>; - ps_threshold_high = <0x200>; - ps_threshold_low = <0x100>; - ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */ - ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/ - poll_delay_ms = <100>; - }; - - icm42607_acc: icm_acc@68 { - status = "okay"; - compatible = "icm42607_acc"; - reg = <0x68>; - irq-gpio = <&gpio4 RK_PC2 IRQ_TYPE_EDGE_RISING>; - irq_enable = <0>; - poll_delay_ms = <30>; - type = ; - layout = <0>; - }; - - icm42607_gyro: icm_gyro@68 { - status = "okay"; - compatible = "icm42607_gyro"; - reg = <0x68>; - poll_delay_ms = <30>; - type = ; - layout = <0>; - }; -}; - -&i2c5 { - status = "okay"; - gt1x: gt1x@14 { - compatible = "goodix,gt1x"; - reg = <0x14>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_gpio>; - goodix,rst-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; - goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>; - power-supply = <&vcc3v3_lcd_n>; - }; -}; - -&i2c6 { - status = "okay"; - - usbc0: husb311@4e { - compatible = "hynetek,husb311"; - reg = <0x4e>; - interrupt-parent = <&gpio3>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vbus5v0_typec>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - ; - source-pdos = - ; - - altmodes { - #address-cells = <1>; - #size-cells = <0>; - - altmode@0 { - reg = <0>; - svid = <0xff01>; - vdo = <0xffffffff>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; - }; - }; - - port@1 { - reg = <1>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; - }; - }; - }; - }; - }; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&i2c7 { - status = "okay"; - es8388: es8388@11 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "everest,es8388", "everest,es8323"; - reg = <0x11>; - clocks = <&mclkout_i2s0>; - clock-names = "mclk"; - assigned-clocks = <&mclkout_i2s0>; - assigned-clock-rates = <12288000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk>; - }; -}; - -&i2s5_8ch { - status = "okay"; -}; - -&i2s6_8ch { - status = "okay"; -}; - -&i2s7_8ch { - status = "okay"; -}; - -&mdio1 { - rgmii_phy: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - }; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&mipi_dcphy1 { - status = "disabled"; -}; - -&pcie2x1l0 { - reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pcie30phy { - rockchip,pcie30-phymode = ; - status = "okay"; -}; - -&pcie3x4 { - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie20x1_0_clkreqn_m1>; - status = "okay"; -}; - -&pinctrl { - cam { - mipicsi0_pwr: mipicsi0-pwr { - rockchip,pins = - /* camera power en */ - <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - mipicsi1_pwr: mipicsi1-pwr { - rockchip,pins = - /* camera power en */ - <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - mipidcphy0_pwr: mipidcphy0-pwr { - rockchip,pins = - /* camera power en */ - <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - - hdmi { - hdmirx_det: hdmirx-det { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - headphone { - hp_det: hp-det { - rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lcd { - lcd_rst_gpio: lcd-rst-gpio { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - work_leds_gpio: work-leds-gpio { - rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdmmc { - sd_s0_pwr: sd-s0-pwr { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - touch { - touch_gpio: touch-gpio { - rockchip,pins = - <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>, - <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - usbc0_int: usbc0-int { - rockchip,pins = <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - typec5v_pwren: typec5v-pwren { - rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-bluetooth { - uart9_gpios: uart9-gpios { - rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reset_gpio: bt-reset-gpio { - rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_gpio: bt-wake-gpio { - rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_irq_gpio: bt-irq-gpio { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - pcie { - pcie20x1_0_clkreqn_m1: pcie20x1-0-clkreqn-m1 { - rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_output_low>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm3 { - pinctrl-0 = <&pwm3m1_pins>; - status = "okay"; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp3_out_dsi0>; -}; - -&route_dsi1 { - status = "disabled"; - connect = <&vp3_out_dsi1>; -}; - -&route_hdmi0 { - status = "okay"; -}; - -&route_hdmi1 { - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -&sdio { - max-frequency = <150000000>; - no-sd; - no-mmc; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdiom0_pins>; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdmmc { - status = "okay"; - vmmc-supply = <&vcc_3v3_sd_s0>; -}; - -&uart9 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>; -}; - -&u2phy0_otg { - rockchip,typec-vbus-det; -}; - -&u2phy1_otg { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; -}; - -&usbdp_phy0 { - orientation-switch; - svid = <0xff01>; - sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; - - port { - #address-cells = <1>; - #size-cells = <0>; - usbdp_phy0_orientation_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; - }; - - usbdp_phy0_dp_altmode_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&dp_altmode_mux>; - }; - }; -}; - -&usbdp_phy1 { - rockchip,dp-lane-mux = <0 1 2 3>; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - usb-role-switch; - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -&usbhost3_0 { - status = "disabled"; -}; - -&usbhost_dwc3_0 { - status = "disabled"; -}; - -&work_led { - gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&work_leds_gpio>; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-ipc.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-ipc.dtsi deleted file mode 100644 index 6882afa06..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-ipc.dtsi +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. - * - */ - -#include "rk3588-linux.dtsi" - -&CPU_SLEEP { - status = "disabled"; -}; - -&cluster0_opp_table { - /delete-node/ opp-408000000; - /delete-node/ opp-600000000; - /delete-node/ opp-816000000; - /delete-node/ opp-1008000000; -}; - -&cluster1_opp_table { - /delete-node/ opp-408000000; - /delete-node/ opp-600000000; - /delete-node/ opp-816000000; - /delete-node/ opp-1008000000; - /delete-node/ opp-2256000000; - /delete-node/ opp-2304000000; - /delete-node/ opp-2352000000; - /delete-node/ opp-2400000000; -}; - -&cluster2_opp_table { - /delete-node/ opp-408000000; - /delete-node/ opp-600000000; - /delete-node/ opp-816000000; - /delete-node/ opp-1008000000; - /delete-node/ opp-2256000000; - /delete-node/ opp-2304000000; - /delete-node/ opp-2352000000; - /delete-node/ opp-2400000000; -}; - -&dfi { - status = "disabled"; -}; - -&dmc { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5-v2.dts b/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5-v2.dts index bd4e33a70..3feb27a12 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5-v2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5-v2.dts @@ -50,6 +50,12 @@ disable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; }; +&&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer>; +} + &pinctrl { usb-typec { fusb302_int: fusb302-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5.dts b/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5.dts index 2411d4842..05fa79464 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5.dts @@ -38,7 +38,7 @@ // #include "rk3588-lubancat-5io-hdmirx.dtsi" /* Camera */ -#include "rk3588-lubancat-5-csi.dtsi" +//#include "rk3588-lubancat-5-csi.dtsi" // #include "rk3588-lubancat-5-cam0.dtsi" // #include "rk3588-lubancat-5-cam1.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo-v10-android.dts b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo-v10-android.dts deleted file mode 100644 index 217101b15..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo-v10-android.dts +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-nvr-demo.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588 NVR DEMO LP4 V10 Android Board"; - compatible = "rockchip,rk3588-nvr-demo-v10-android", "rockchip,rk3588"; -}; - -&avsd { - status = "okay"; -}; - -&dp0 { - status = "disabled"; -}; - -&dp1_in_vp0 { - status = "disabled"; -}; - -&dp1_in_vp1 { - status = "disabled"; -}; - -&hdmi0_in_vp1 { - status = "disabled"; -}; - -&hdmi0_in_vp2 { - status = "disabled"; -}; - -&hdmi1 { - status = "disabled"; -}; - -&hdmi1_in_vp0 { - status = "disabled"; -}; - -&hdmi1_in_vp2 { - status = "disabled"; -}; - -&hdmi1_sound { - status = "disabled"; -}; - -&hdptxphy_hdmi1 { - status = "disabled"; -}; - -&i2s6_8ch { - status = "disabled"; -}; - -&pcie30phy { - status = "disabled"; -}; - -&pcie3x4 { - status = "disabled"; -}; - -&route_dp0 { - status = "okay"; - connect = <&vp2_out_dp0>; - /delete-property/ force-output; - /delete-node/ force_timing; -}; - -&route_dp1 { - status = "disabled"; -}; - -&route_hdmi0 { - status = "okay"; - connect = <&vp0_out_hdmi0>; - /delete-property/ force-output; - /delete-node/ force_timing; -}; - -&route_hdmi1 { - status = "disabled"; -}; - -&sata0 { - status = "disabled"; -}; - -&sata1 { - status = "disabled"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - extcon = <&u2phy0>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo-v10-cam-4x.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo-v10-cam-4x.dtsi deleted file mode 100644 index 708a54b63..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo-v10-cam-4x.dtsi +++ /dev/null @@ -1,565 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ -/ { - vcc_mipicsi0: vcc-mipicsi0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipicsi0_pwr>; - regulator-name = "vcc_mipicsi0"; - enable-active-high; - }; - - vcc_mipicsi1: vcc-mipicsi1-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipicsi1_pwr>; - regulator-name = "vcc_mipicsi1"; - enable-active-high; - }; -}; - -&pinctrl { - cam { - mipicsi0_pwr: mipicsi0-pwr { - rockchip,pins = - <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - mipicsi1_pwr: mipicsi1-pwr { - rockchip,pins = - <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&csi2_dphy0_hw { - status = "okay"; -}; - -&csi2_dphy1_hw { - status = "okay"; -}; - -&csi2_dphy1 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_ucam2: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx464_out2>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy1_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi2_csi2_input>; - }; - }; - }; -}; - -&csi2_dphy2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_ucam3: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx464_out3>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy2_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi3_csi2_input>; - }; - }; - }; -}; - -&csi2_dphy4 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_ucam4: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx464_out4>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy4_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi4_csi2_input>; - }; - }; - }; -}; - -&csi2_dphy5 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_ucam5: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx464_out5>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy5_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi5_csi2_input>; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; - - pinctrl-0 = <&i2c5m3_xfer>; - /* module 77/79 0x1a 78/80 0x36 */ - imx464_2: imx464-2@1a { - compatible = "sony,imx464"; - status = "okay"; - reg = <0x1a>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - pinctrl-names = "default"; - pinctrl-0 = <&mipim0_camera3_clk>; - avdd-supply = <&vcc_mipicsi0>; - reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - pwdn-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-sync-mode = "internal_master"; - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT1980-PX1"; - rockchip,camera-module-lens-name = "SHG102"; - port { - imx464_out2: endpoint { - remote-endpoint = <&mipi_in_ucam2>; - data-lanes = <1 2>; - }; - }; - }; - - imx464_3: imx464-3@36 { - compatible = "sony,imx464"; - status = "okay"; - reg = <0x36>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - avdd-supply = <&vcc_mipicsi0>; - pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-sync-mode = "external_master"; - rockchip,camera-module-index = <3>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT1980-PX1"; - rockchip,camera-module-lens-name = "SHG102"; - port { - imx464_out3: endpoint { - remote-endpoint = <&mipi_in_ucam3>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&i2c4 { - status = "okay"; - - pinctrl-0 = <&i2c4m3_xfer>; - /* 77/79 0x1a 78/80 0x36 */ - imx464_4: imx464-4@1a { - compatible = "sony,imx464"; - status = "okay"; - reg = <0x1a>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - pinctrl-names = "default"; - pinctrl-0 = <&mipim0_camera4_clk>; - avdd-supply = <&vcc_mipicsi1>; - reset-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; - pwdn-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-sync-mode = "external_master"; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT1980-PX1"; - rockchip,camera-module-lens-name = "SHG102"; - port { - imx464_out4: endpoint { - remote-endpoint = <&mipi_in_ucam4>; - data-lanes = <1 2>; - }; - }; - }; - - imx464_5: imx464-5@36 { - compatible = "sony,imx464"; - status = "okay"; - reg = <0x36>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - avdd-supply = <&vcc_mipicsi1>; - pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-sync-mode = "external_master"; - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT1980-PX1"; - rockchip,camera-module-lens-name = "SHG102"; - port { - imx464_out5: endpoint { - remote-endpoint = <&mipi_in_ucam5>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&mipi2_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy1_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in2>; - }; - }; - }; -}; - -&mipi3_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi3_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy2_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi3_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in3>; - }; - }; - }; -}; - -&mipi4_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi4_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy4_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi4_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in4>; - }; - }; - }; -}; - -&mipi5_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi5_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy5_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi5_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in5>; - }; - }; - }; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds2 { - status = "okay"; - - port { - cif_mipi_in2: endpoint { - remote-endpoint = <&mipi2_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds2_sditf { - status = "okay"; - - port { - mipi2_lvds_sditf: endpoint { - remote-endpoint = <&isp0_vir0>; - }; - }; -}; - -&rkcif_mipi_lvds3 { - status = "okay"; - - port { - cif_mipi_in3: endpoint { - remote-endpoint = <&mipi3_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds3_sditf { - status = "okay"; - - port { - mipi3_lvds_sditf: endpoint { - remote-endpoint = <&isp1_vir0>; - }; - }; -}; - -&rkcif_mipi_lvds4 { - status = "okay"; - - port { - cif_mipi_in4: endpoint { - remote-endpoint = <&mipi4_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds4_sditf { - status = "okay"; - - port { - mipi4_lvds_sditf: endpoint { - remote-endpoint = <&isp0_vir1>; - }; - }; -}; - -&rkcif_mipi_lvds5 { - status = "okay"; - - port { - cif_mipi_in5: endpoint { - remote-endpoint = <&mipi5_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds5_sditf { - status = "okay"; - - port { - mipi5_lvds_sditf: endpoint { - remote-endpoint = <&isp1_vir1>; - }; - }; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp0 { - status = "okay"; -}; - -&isp0_mmu { - status = "okay"; -}; - -&rkisp0_vir0 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi2_lvds_sditf>; - }; - }; -}; - -&rkisp0_vir1 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir1: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi4_lvds_sditf>; - }; - }; -}; - -&rkisp1 { - status = "okay"; -}; - -&isp1_mmu { - status = "okay"; -}; - -&rkisp1_vir0 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp1_vir0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi3_lvds_sditf>; - }; - }; -}; - -&rkisp1_vir1 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp1_vir1: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi5_lvds_sditf>; - }; - }; -}; - diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo-v10-ipc-4x-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo-v10-ipc-4x-linux.dts deleted file mode 100644 index 00310c57a..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo-v10-ipc-4x-linux.dts +++ /dev/null @@ -1,213 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-nvr-demo.dtsi" -#include "rk3588-ipc.dtsi" -#include "rk3588-nvr-demo-v10-cam-4x.dtsi" - -/ { - model = "Rockchip RK3588 NVR DEMO LP4 V10 Board"; - compatible = "rockchip,rk3588-nvr-demo-v10-ipc-4x", - "rockchip,rk3588-nvr-demo-v10", "rockchip,rk3588"; -}; - -&combphy0_ps { - status = "disabled"; -}; - -&combphy1_ps { - status = "disabled"; -}; - -&combphy2_psu { - status = "disabled"; -}; - -&dp0 { - status = "disabled"; -}; - -&dp0_in_vp0 { - status = "disabled"; -}; - -&dp0_in_vp1 { - status = "disabled"; -}; - -&dp0_in_vp2 { - status = "disabled"; -}; - -&dp1 { - status = "disabled"; -}; - -&dp1_in_vp0 { - status = "disabled"; -}; - -&dp1_in_vp1 { - status = "disabled"; -}; - -&dp1_in_vp2 { - status = "disabled"; -}; - -&gmac1 { - status = "disabled"; -}; - -&hdmi0 { - status = "disabled"; -}; - -&hdmi0_in_vp0 { - status = "disabled"; -}; - -&hdmi0_in_vp1 { - status = "disabled"; -}; - -&hdmi0_in_vp2 { - status = "disabled"; -}; - -&hdmi0_sound { - status = "disabled"; -}; - -&hdmi1 { - status = "disabled"; -}; - -&hdmi0_in_vp0 { - status = "disabled"; -}; - -&hdmi0_in_vp1 { - status = "disabled"; -}; - -&hdmi0_in_vp2 { - status = "disabled"; -}; - -&hdmi1_sound { - status = "disabled"; -}; - -&hdptxphy_hdmi0 { - status = "disabled"; -}; - -&hdptxphy_hdmi1 { - status = "disabled"; -}; - -&i2s5_8ch { - status = "disabled"; -}; - -&pcie2x1l0 { - status = "disabled"; -}; - -&pcie2x1l1 { - status = "disabled"; -}; - -&pcie30phy { - status = "disabled"; -}; - -&pcie3x4 { - status = "disabled"; -}; - -&rkvdec_ccu { - status = "disabled"; -}; - -&rkvdec0 { - status = "disabled"; -}; - -&rkvdec0_mmu { - status = "disabled"; -}; - -&rkvdec1 { - status = "disabled"; -}; - -&rkvdec1_mmu { - status = "disabled"; -}; - -&sata0 { - status = "disabled"; -}; - -&sata1 { - status = "disabled"; -}; - -&usbdp_phy1 { - status = "disabled"; -}; - -&usbdrd3_1 { - status = "disabled"; -}; - -&usbdrd_dwc3_1 { - status = "disabled"; -}; - -&usb_host0_ehci { - status = "disabled"; -}; - -&usb_host0_ohci { - status = "disabled"; -}; - -&usb_host1_ehci { - status = "disabled"; -}; - -&usb_host1_ohci { - status = "disabled"; -}; - -&u2phy1 { - status = "disabled"; -}; - -&u2phy1_otg { - status = "disabled"; -}; - -&u2phy2 { - status = "disabled"; -}; - -&u2phy2_host { - status = "disabled"; -}; - -&u2phy3 { - status = "disabled"; -}; - -&u2phy3_host { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo-v10-spi-nand.dts b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo-v10-spi-nand.dts deleted file mode 100644 index 49d5fbe83..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo-v10-spi-nand.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-nvr-demo.dtsi" -#include "rk3588-linux.dtsi" - -/ { - model = "Rockchip RK3588 NVR DEMO LP4 SPI NAND Board"; - compatible = "rockchip,rk3588-nvr-demo-v10-spi-nand", "rockchip,rk3588"; - - chosen: chosen { - bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 clk_gate.always_on=1 pm_domains.always_on=1 ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs rw rootwait"; - }; -}; - -&sfc { - status = "okay"; - - flash@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <80000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo-v10.dts deleted file mode 100644 index 9a1dc1f7e..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo-v10.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-nvr-demo.dtsi" -#include "rk3588-linux.dtsi" - -/ { - model = "Rockchip RK3588 NVR DEMO LP4 V10 Board"; - compatible = "rockchip,rk3588-nvr-demo-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo.dtsi deleted file mode 100644 index 5c345b2cd..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo.dtsi +++ /dev/null @@ -1,840 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include "rk3588.dtsi" -#include "rk3588-nvr.dtsi" -#include "rk3588-rk806-single.dtsi" - -/ { - i2s0_sound: i2s0-sound { - status = "okay"; - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "rockchip,es8311"; - simple-audio-card,dai-link@0 { - format = "i2s"; - cpu { - sound-dai = <&i2s0_8ch>; - }; - codec { - sound-dai = <&es8311>; - }; - }; - }; - - leds: leds { - compatible = "gpio-leds"; - hdd_led: hdd-led { - gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - net_led: net-led { - gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - work_led: work-led { - gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - pcie30_avdd0v75: pcie30-avdd0v75 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v75"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - vin-supply = <&vdd_0v75_s0>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc3v3_pcie30: vcc3v3-pcie30 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; - startup-delay-us = <7500>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - }; - - vcc5v0_otg: vcc5v0-otg-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_otg_en>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&combphy0_ps { - pinctrl-names = "default"; - pinctrl-0 = <&sata0_pm_reset>; - status = "okay"; -}; - -&combphy1_ps { - pinctrl-names = "default"; - pinctrl-0 = <&sata1_pm_reset>; - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&dp0 { - pinctrl-0 = <&dp0m2_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&dp0_in_vp0 { - status = "okay"; -}; - -&dp0_in_vp1 { - status = "okay"; -}; - -&dp0_in_vp2 { - status = "okay"; -}; - -&dp1 { - pinctrl-0 = <&dp1m2_pins &dp1_hdmi_ctl>; - pinctrl-names = "default"; - status = "okay"; -}; - -&dp1_in_vp0 { - status = "okay"; -}; - -&dp1_in_vp1 { - status = "okay"; -}; - -&dp1_in_vp2 { - status = "okay"; -}; - -&dp1_sound { - status = "okay"; -}; - -&gmac0 { - /* Use rgmii-rxid mode to disable rx delay inside Soc */ - phy-mode = "rgmii-rxid"; - clock_in_out = "output"; - - snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - - tx_delay = <0x44>; - /* rx_delay = <0x4f>; */ - - phy-handle = <&rgmii_phy0>; - status = "okay"; -}; - -&gmac1 { - /* Use rgmii-rxid mode to disable rx delay inside Soc */ - phy-mode = "rgmii-rxid"; - clock_in_out = "output"; - - snps,reset-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac1_miim - &gmac1_tx_bus2 - &gmac1_rx_bus2 - &gmac1_rgmii_clk - &gmac1_rgmii_bus>; - - tx_delay = <0x42>; - /* rx_delay = <0x4f>; */ - - phy-handle = <&rgmii_phy1>; - status = "okay"; -}; - -&hdmi0 { - enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi0_in_vp0 { - status = "okay"; -}; - -&hdmi0_in_vp1 { - status = "okay"; -}; - -&hdmi0_in_vp2 { - status = "okay"; -}; - -&hdmi0_sound { - status = "okay"; -}; - -&hdmi1 { - enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi1_in_vp0 { - status = "okay"; -}; - -&hdmi1_in_vp1 { - status = "okay"; -}; - -&hdmi1_in_vp2 { - status = "okay"; -}; - -&hdmi1_sound { - status = "okay"; -}; - -&hdptxphy_hdmi0 { - status = "okay"; -}; - -&hdptxphy_hdmi1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - - vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big0_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { - compatible = "rockchip,rk8603"; - reg = <0x43>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big1_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - - vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_npu_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c3 { - status = "okay"; - es8311: es8311@18 { - status = "okay"; - compatible = "everest,es8311"; - reg = <0x18>; - #sound-dai-cells = <0>; - adc-pga-gain = <6>; /* 18dB */ - adc-volume = <0xbf>; /* 0dB */ - dac-volume = <0xbf>; /* 0dB */ - aec-mode = "adc left, adc right"; - clocks = <&mclkout_i2s0>; - clock-names = "mclk"; - assigned-clocks = <&mclkout_i2s0>; - assigned-clock-rates = <12288000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk>; - }; -}; - -&i2c4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4m3_xfer>; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&i2s0_8ch { - status = "okay"; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; -}; - -&i2s5_8ch { - status = "okay"; -}; - -&i2s6_8ch { - status = "okay"; -}; - -&mdio0 { - rgmii_phy0: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - }; -}; - -&mdio1 { - rgmii_phy1: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - }; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x4 { - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "okay"; -}; - -&pwm3 { - compatible = "rockchip,remotectl-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3m0_pins>; - remote_pwm_id = <3>; - handle_cpu_id = <1>; - remote_support_psci = <0>; - status = "okay"; - - ir_key1 { - rockchip,usercode = <0x4040>; - rockchip,key_table = - <0xf2 KEY_REPLY>, - <0xba KEY_BACK>, - <0xf4 KEY_UP>, - <0xf1 KEY_DOWN>, - <0xef KEY_LEFT>, - <0xee KEY_RIGHT>, - <0xbd KEY_HOME>, - <0xea KEY_VOLUMEUP>, - <0xe3 KEY_VOLUMEDOWN>, - <0xe2 KEY_SEARCH>, - <0xb2 KEY_POWER>, - <0xbc KEY_MUTE>, - <0xec KEY_MENU>, - <0xbf 0x190>, - <0xe0 0x191>, - <0xe1 0x192>, - <0xe9 183>, - <0xe6 248>, - <0xe8 185>, - <0xe7 186>, - <0xf0 388>, - <0xbe 0x175>; - }; - - ir_key2 { - rockchip,usercode = <0xff00>; - rockchip,key_table = - <0xf9 KEY_HOME>, - <0xbf KEY_BACK>, - <0xfb KEY_MENU>, - <0xaa KEY_REPLY>, - <0xb9 KEY_UP>, - <0xe9 KEY_DOWN>, - <0xb8 KEY_LEFT>, - <0xea KEY_RIGHT>, - <0xeb KEY_VOLUMEDOWN>, - <0xef KEY_VOLUMEUP>, - <0xf7 KEY_MUTE>, - <0xe7 KEY_POWER>, - <0xfc KEY_POWER>, - <0xa9 KEY_VOLUMEDOWN>, - <0xa8 KEY_PLAYPAUSE>, - <0xe0 KEY_VOLUMEDOWN>, - <0xa5 KEY_VOLUMEDOWN>, - <0xab 183>, - <0xb7 388>, - <0xe8 388>, - <0xf8 184>, - <0xaf 185>, - <0xed KEY_VOLUMEDOWN>, - <0xee 186>, - <0xb3 KEY_VOLUMEDOWN>, - <0xf1 KEY_VOLUMEDOWN>, - <0xf2 KEY_VOLUMEDOWN>, - <0xf3 KEY_SEARCH>, - <0xb4 KEY_VOLUMEDOWN>, - <0xa4 KEY_SETUP>, - <0xbe KEY_SEARCH>; - }; - - ir_key3 { - rockchip,usercode = <0x1dcc>; - rockchip,key_table = - <0xee KEY_REPLY>, - <0xf0 KEY_BACK>, - <0xf8 KEY_UP>, - <0xbb KEY_DOWN>, - <0xef KEY_LEFT>, - <0xed KEY_RIGHT>, - <0xfc KEY_HOME>, - <0xf1 KEY_VOLUMEUP>, - <0xfd KEY_VOLUMEDOWN>, - <0xb7 KEY_SEARCH>, - <0xff KEY_POWER>, - <0xf3 KEY_MUTE>, - <0xbf KEY_MENU>, - <0xf9 0x191>, - <0xf5 0x192>, - <0xb3 388>, - <0xbe KEY_1>, - <0xba KEY_2>, - <0xb2 KEY_3>, - <0xbd KEY_4>, - <0xf9 KEY_5>, - <0xb1 KEY_6>, - <0xfc KEY_7>, - <0xf8 KEY_8>, - <0xb0 KEY_9>, - <0xb6 KEY_0>, - <0xb5 KEY_BACKSPACE>; - }; -}; - -&rk806single { - pinctrl-names = "default", "pmic-power-off"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; - pinctrl-1 = <&rk806_dvs1_slp>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; - - regulators { - avcc_1v8_s0: PLDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "avcc_1v8_s0"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - }; -}; - -&rockchip_suspend { - status = "okay"; - rockchip,sleep-debug-en = <1>; - rockchip,virtual-poweroff = <1>; - rockchip,sleep-mode-config = < - (0 - | RKPM_SLP_ARMOFF_DDRPD - ) - >; - rockchip,wakeup-config = < - (0 - | RKPM_CPU0_WKUP_EN - | RKPM_GPIO_WKUP_EN - ) - >; -}; - -&route_dp0 { - status = "okay"; - force-output; - connect = <&vp2_out_dp0>; - - force_timing { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hfront-porch = <24>; - hsync-len = <136>; - hback-porch = <160>; - vfront-porch = <3>; - vsync-len = <6>; - vback-porch = <29>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - -}; - -&route_dp1 { - status = "okay"; - force-output; - connect = <&vp2_out_dp1>; - - force_timing { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hfront-porch = <24>; - hsync-len = <136>; - hback-porch = <160>; - vfront-porch = <3>; - vsync-len = <6>; - vback-porch = <29>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - -}; - -&route_hdmi0 { - status = "okay"; - force-output; - connect = <&vp2_out_hdmi0>; - - force_timing { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hfront-porch = <24>; - hsync-len = <136>; - hback-porch = <160>; - vfront-porch = <3>; - vsync-len = <6>; - vback-porch = <29>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - -}; - -&route_hdmi1 { - status = "okay"; - force-output; - connect = <&vp2_out_hdmi1>; - - force_timing { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hfront-porch = <24>; - hsync-len = <136>; - hback-porch = <160>; - vfront-porch = <3>; - vsync-len = <6>; - vback-porch = <29>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - -}; - -&sata0 { - status = "okay"; -}; - -&sata1 { - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - max-frequency = <200000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&spdif_tx5 { - status = "okay"; -}; - -&pinctrl { - dp { - dp1_hdmi_ctl: dp-hdmi-ctl { - rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>, - <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - rtc { - rtc_int: rtc-int { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_otg_en: vcc5v0-otg-en { - rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sata { - sata0_pm_reset: sata0-pm-reset { - rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_output_high>; - }; - sata1_pm_reset: sata1-pm-reset { - rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy1 { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy0_otg { - vbus-supply = <&vcc5v0_otg>; - status = "okay"; -}; - -&u2phy1_otg { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdp_phy0 { - rockchip,dp-lane-mux = < 2 3 >; - status = "okay"; -}; - -&usbdp_phy0_dp { - status = "okay"; -}; - -&usbdp_phy0_u3 { - status = "okay"; -}; - -&usbdp_phy1 { - rockchip,dp-lane-mux = < 0 1 2 3 >; - status = "okay"; -}; - -&usbdp_phy1_dp { - status = "okay"; -}; - -&usbdp_phy1_u3 { - maximum-speed = "high-speed"; - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; - maximum-speed = "high-speed"; - status = "okay"; -}; - -&usbhost3_0 { - status = "okay"; -}; - -&usbhost_dwc3_0 { - dr_mode = "host"; - status = "okay"; -}; - -&vdd_log_s0 { - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; -}; - -&vdd_vdenc_s0 { - regulator-init-microvolt = <750000>; -}; - diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo1-v21-android.dts b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo1-v21-android.dts deleted file mode 100644 index 9e83cb436..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo1-v21-android.dts +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-nvr-demo1-v21.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588 NVR DEMO1 LP4 V21 Android Board"; - compatible = "rockchip,rk3588-nvr-demo1-v21", "rockchip,rk3588"; -}; - -&dp0_in_vp0 { - status = "disabled"; -}; - -&dp0_in_vp2 { - status = "disabled"; -}; - -&dp1 { - status = "disabled"; -}; - -&dsi1 { - status = "disabled"; -}; - -&hdmi0_in_vp1 { - status = "disabled"; -}; - -&hdmi0_in_vp2 { - status = "disabled"; -}; - -&hdmi1 { - status = "disabled"; -}; - -&hdmi1_in_vp0 { - status = "disabled"; -}; - -&hdmi1_in_vp2 { - status = "disabled"; -}; - -&hdmi1_sound { - status = "disabled"; -}; - -&hdptxphy_hdmi1 { - status = "disabled"; -}; - -&mipi_dcphy1 { - status = "disabled"; -}; - -&i2s6_8ch { - status = "disabled"; -}; - -&pcie30phy { - status = "disabled"; -}; - -&pcie3x4 { - status = "disabled"; -}; - -&sata0 { - status = "disabled"; -}; - -&sata1 { - status = "disabled"; -}; - diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo1-v21.dts b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo1-v21.dts deleted file mode 100644 index 76826eba2..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo1-v21.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-nvr-demo1-v21.dtsi" -#include "rk3588-linux.dtsi" - -/ { - model = "Rockchip RK3588 NVR DEMO1 LP4 V21 Board"; - compatible = "rockchip,rk3588-nvr-demo1-v21", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo1-v21.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo1-v21.dtsi deleted file mode 100644 index b073e3842..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo1-v21.dtsi +++ /dev/null @@ -1,215 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ -#include "dt-bindings/usb/pd.h" -#include "rk3588-nvr-demo.dtsi" - - -/ { - ite_pwr_en: ite-pwr-en { - compatible = "regulator-fixed"; - regulator-name = "ITE-PWR_EN"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - enable-active-high; - gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; - }; -}; - -&dp0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "okay"; -}; - -&dp0_sound { - status = "okay"; -}; - -&dp1 { - pinctrl-0 = <&dp1m2_pins &dp1_hdmi_reset>; - pinctrl-names = "default"; - status = "okay"; -}; - -&dsi1 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi1_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi1>; - }; - }; - }; -}; - -&dsi1_in_vp2 { - status = "okay"; -}; - -&dsi1_in_vp3 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; - - it6161: it6161@6c { - status = "okay"; - compatible = "ite,it6161"; - #sound-dai-cells = <0>; - reg = <0x6c>; - it6161-addr-hdmi-tx = <0x4C>; - it6161-addr-cec = <0x4E>; - interrupt-parent = <&gpio0>; - interrupts = ; - enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in_dsi1: endpoint { - remote-endpoint = <&dsi1_out_panel>; - }; - }; - }; - }; - - usbc0: fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio1>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vcc5v0_otg>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - ; - source-pdos = - ; - - altmodes { - #address-cells = <1>; - #size-cells = <0>; - - altmode@0 { - reg = <0>; - svid = <0xff01>; - vdo = <0xffffffff>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; - }; - }; - - port@1 { - reg = <1>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; - }; - }; - }; - }; - }; -}; - -&mipi_dcphy1 { - status = "okay"; -}; - -&route_dp0 { - status = "disabled"; -}; - -&usbdp_phy0 { - status = "okay"; - orientation-switch; - svid = <0xff01>; - sbu1-dc-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; - - port { - #address-cells = <1>; - #size-cells = <0>; - usbdp_phy0_orientation_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; - }; - - usbdp_phy0_dp_altmode_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&dp_altmode_mux>; - }; - }; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - usb-role-switch; - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -&spdif_tx2 { - status = "okay"; -}; - -&pinctrl { - dp { - dp1_hdmi_reset: dp-hdmi-reset { - rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb-typec { - usbc0_int: usbc0-int { - rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo3-v10-android.dts b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo3-v10-android.dts deleted file mode 100644 index 246f0f0d7..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo3-v10-android.dts +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-nvr-demo3-v10.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588 NVR DEMO3 LP4 V10 Android Board"; - compatible = "rockchip,rk3588-nvr-demo3-v10", "rockchip,rk3588"; -}; - -&dp0_in_vp0 { - status = "disabled"; -}; - -&dp0_in_vp2 { - status = "disabled"; -}; - -&dp1 { - status = "disabled"; -}; - -&dsi1 { - status = "disabled"; -}; - -&hdmi0_in_vp1 { - status = "disabled"; -}; - -&hdmi0_in_vp2 { - status = "disabled"; -}; - -&hdmi1 { - status = "disabled"; -}; - -&hdmi1_in_vp0 { - status = "disabled"; -}; - -&hdmi1_in_vp2 { - status = "disabled"; -}; - -&hdmi1_sound { - status = "disabled"; -}; - -&hdptxphy_hdmi1 { - status = "disabled"; -}; - -&mipi_dcphy1 { - status = "disabled"; -}; - -&i2s6_8ch { - status = "disabled"; -}; - -&pcie30phy { - status = "disabled"; -}; - -&pcie3x4 { - status = "disabled"; -}; - -&sata0 { - status = "disabled"; -}; - -&sata1 { - status = "disabled"; -}; - diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo3-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo3-v10.dts deleted file mode 100644 index ef721676d..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo3-v10.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-nvr-demo3-v10.dtsi" -#include "rk3588-linux.dtsi" - -/ { - model = "Rockchip RK3588 NVR DEMO3 LP4 V10 Board"; - compatible = "rockchip,rk3588-nvr-demo3-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo3-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo3-v10.dtsi deleted file mode 100644 index 2f6821de4..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-nvr-demo3-v10.dtsi +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include "rk3588-nvr-demo1-v21.dtsi" - -&dsi1 { - status = "disabled"; -}; - -&i2c0 { - /delete-node/ rk8603@43; - - vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big0_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "disabled"; - /delete-node/ rk8602@42; -}; - -&rkvenc0 { - venc-supply = <&vdd_log_s0>; - mem-supply = <&vdd_log_s0>; - status = "okay"; -}; - -&rkvenc1 { - venc-supply = <&vdd_log_s0>; - mem-supply = <&vdd_log_s0>; - status = "okay"; -}; - -&spi2 { - rk806single@0 { - regulators { - /delete-node/ DCDC_REG4; - - vdd_npu_s0: vdd_npu_mem_s0: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-init-microvolt = <750000>; - regulator-ramp-delay = <2500>; - regulator-name = "vdd_npu_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nvr.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nvr.dtsi deleted file mode 100644 index 0301d6f31..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-nvr.dtsi +++ /dev/null @@ -1,336 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include "rk3588-cpu-swap.dtsi" - -/ { - adc_keys: adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - vol-up-key { - label = "volume up"; - linux,code = ; - press-threshold-microvolt = <1750>; - }; - }; - - dp0_sound: dp0-sound { - status = "disabled"; - compatible = "rockchip,hdmi"; - rockchip,card-name= "rockchip-dp0"; - rockchip,mclk-fs = <512>; - rockchip,cpu = <&spdif_tx2>; - rockchip,codec = <&dp0 1>; - rockchip,jack-det; - }; - - dp1_sound: dp1-sound { - status = "disabled"; - compatible = "rockchip,hdmi"; - rockchip,card-name= "rockchip-dp1"; - rockchip,mclk-fs = <512>; - rockchip,cpu = <&spdif_tx5>; - rockchip,codec = <&dp1 1>; - rockchip,jack-det; - }; - - hdmi0_sound: hdmi0-sound { - status = "disabled"; - compatible = "rockchip,hdmi"; - rockchip,mclk-fs = <128>; - rockchip,card-name = "rockchip-hdmi0"; - rockchip,cpu = <&i2s5_8ch>; - rockchip,codec = <&hdmi0>; - rockchip,jack-det; - }; - - hdmi1_sound: hdmi1-sound { - status = "disabled"; - compatible = "rockchip,hdmi"; - rockchip,mclk-fs = <128>; - rockchip,card-name = "rockchip-hdmi1"; - rockchip,cpu = <&i2s6_8ch>; - rockchip,codec = <&hdmi1>; - rockchip,jack-det; - }; - - test-power { - status = "okay"; - }; -}; - -&av1d_mmu { - status = "okay"; -}; - -&CPU_SLEEP { - status = "disabled"; -}; - -&cluster0_opp_table { - /delete-node/ opp-408000000; - /delete-node/ opp-600000000; - /delete-node/ opp-816000000; - /delete-node/ opp-1008000000; -}; - -&cluster1_opp_table { - /delete-node/ opp-408000000; - /delete-node/ opp-600000000; - /delete-node/ opp-816000000; - /delete-node/ opp-1008000000; - /delete-node/ opp-2256000000; - /delete-node/ opp-2304000000; - /delete-node/ opp-2352000000; - /delete-node/ opp-2400000000; -}; - -&cluster2_opp_table { - /delete-node/ opp-408000000; - /delete-node/ opp-600000000; - /delete-node/ opp-816000000; - /delete-node/ opp-1008000000; - /delete-node/ opp-2256000000; - /delete-node/ opp-2304000000; - /delete-node/ opp-2352000000; - /delete-node/ opp-2400000000; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&display_subsystem { - clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>; - clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; -}; - -&gpu_opp_table { - /delete-node/ opp-198000000; - /delete-node/ opp-297000000; - /delete-node/ opp-396000000; - /delete-node/ opp-500000000; - /delete-node/ opp-1000000000; - -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - mem-supply = <&vdd_gpu_mem_s0>; - status = "okay"; -}; - -&hdptxphy_hdmi_clk0 { - status = "okay"; -}; - -&hdptxphy_hdmi_clk1 { - status = "okay"; -}; - -&iep { - status = "okay"; -}; - -&iep_mmu { - status = "okay"; -}; - -&jpegd { - status = "okay"; -}; - -&jpegd_mmu { - status = "okay"; -}; - -&jpege_ccu { - status = "okay"; -}; - -&jpege0 { - status = "okay"; -}; - -&jpege0_mmu { - status = "okay"; -}; - -&jpege1 { - status = "okay"; -}; - -&jpege1_mmu { - status = "okay"; -}; - -&jpege2 { - status = "okay"; -}; - -&jpege2_mmu { - status = "okay"; -}; - -&jpege3 { - status = "okay"; -}; - -&jpege3_mmu { - status = "okay"; -}; - -&mpp_srv { - status = "okay"; -}; - -&rga3_core0 { - status = "okay"; -}; - -&rga3_0_mmu { - status = "okay"; -}; - -&rga3_core1 { - status = "okay"; -}; - -&rga3_1_mmu { - status = "okay"; -}; - -&rga2 { - status = "okay"; -}; - -&rknpu { - rknpu-supply = <&vdd_npu_s0>; - mem-supply = <&vdd_npu_mem_s0>; - status = "okay"; -}; - -&rknpu_mmu { - status = "okay"; -}; - -&rkvdec_ccu { - status = "okay"; -}; - -&rkvdec0 { - status = "okay"; -}; - -&rkvdec0_mmu { - status = "okay"; -}; - -&rkvdec1 { - status = "okay"; -}; - -&rkvdec1_mmu { - status = "okay"; -}; - -&rkvenc_ccu { - status = "okay"; -}; - -&rkvenc0 { - venc-supply = <&vdd_vdenc_s0>; - mem-supply = <&vdd_vdenc_mem_s0>; - status = "okay"; -}; - -&rkvenc0_mmu { - status = "okay"; -}; - -&rkvenc1 { - venc-supply = <&vdd_vdenc_s0>; - mem-supply = <&vdd_vdenc_mem_s0>; - status = "okay"; -}; - -&rkvenc1_mmu { - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&avcc_1v8_s0>; -}; - -&tsadc { - status = "okay"; -}; - -&vdpu { - status = "okay"; -}; - -&vdpu_mmu { - status = "okay"; -}; - -&vepu { - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru ACLK_VOP>; - assigned-clock-rates = <800000000>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -/* vp0 & vp1 splice for 8K output */ -&vp0 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; - rockchip,primary-plane = ; -}; - -&vp1 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; - rockchip,primary-plane = ; -}; - -&vp2 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; - rockchip,primary-plane = ; -}; - -&vp3 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; - rockchip,primary-plane = ; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-pc.dtsi deleted file mode 100644 index bd0c9b718..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-pc.dtsi +++ /dev/null @@ -1,351 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include - -/ { - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usbdcin: vcc5v0-usbdcin { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usbdcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&dfi { - status = "okay"; -}; - -&dmc { - center-supply = <&vdd_ddr_s0>; - mem-supply = <&vdd_log_s0>; - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - mem-supply = <&vdd_gpu_mem_s0>; - status = "okay"; -}; - -&gpu_opp_table { - /delete-node/ opp-198000000; - /delete-node/ opp-297000000; - /delete-node/ opp-396000000; - /delete-node/ opp-594000000; -}; - -&iep { - status = "okay"; -}; - -&iep_mmu { - status = "okay"; -}; - -&jpegd { - status = "okay"; -}; - -&jpegd_mmu { - status = "okay"; -}; - -&jpege_ccu { - status = "okay"; -}; - -&jpege0 { - status = "okay"; -}; - -&jpege0_mmu { - status = "okay"; -}; - -&jpege1 { - status = "okay"; -}; - -&jpege1_mmu { - status = "okay"; -}; - -&jpege2 { - status = "okay"; -}; - -&jpege2_mmu { - status = "okay"; -}; - -&jpege3 { - status = "okay"; -}; - -&jpege3_mmu { - status = "okay"; -}; - -&mpp_srv { - status = "okay"; -}; - -&rga2 { - status = "okay"; -}; - -&rga3_core0 { - status = "okay"; -}; - -&rga3_0_mmu { - status = "okay"; -}; - -&rga3_core1 { - status = "okay"; -}; - -&rga3_1_mmu { - status = "okay"; -}; - -&rknpu { - rknpu-supply = <&vdd_npu_s0>; - mem-supply = <&vdd_npu_mem_s0>; - status = "okay"; -}; - -&rknpu_mmu { - status = "okay"; -}; - -&rkvdec_ccu { - status = "okay"; -}; - -&rkvdec0 { - status = "okay"; -}; - -&rkvdec0_mmu { - status = "okay"; -}; - -&rkvdec1 { - status = "okay"; -}; - -&rkvdec1_mmu { - status = "okay"; -}; - -&rkvenc_ccu { - status = "okay"; -}; - -&rkvenc0 { - venc-supply = <&vdd_vdenc_s0>; - mem-supply = <&vdd_vdenc_mem_s0>; - status = "okay"; -}; - -&rkvenc0_mmu { - status = "okay"; -}; - -&rkvenc1 { - venc-supply = <&vdd_vdenc_s0>; - mem-supply = <&vdd_vdenc_mem_s0>; - status = "okay"; -}; - -&rkvenc1_mmu { - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc_1v8_s0>; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy1 { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdp_phy0 { - status = "okay"; -}; - -&usbdp_phy0_dp { - status = "okay"; -}; - -&usbdp_phy0_u3 { - status = "okay"; -}; - -&usbdp_phy1_dp { - status = "okay"; -}; - -&usbdp_phy1_u3 { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - status = "okay"; -}; - -&usbhost3_0 { - status = "okay"; -}; - -&usbhost_dwc3_0 { - status = "okay"; -}; - -&vdpu { - status = "okay"; -}; - -&vdpu_mmu { - status = "okay"; -}; - -&vepu { - status = "okay"; -}; - -&vop { - disable-win-move; - assigned-clocks = <&cru DCLK_VOP0_SRC>, - <&cru DCLK_VOP1_SRC>, - <&cru DCLK_VOP2_SRC>, - <&cru DCLK_VOP3>; - assigned-clock-parents = <0>, <0>, <&cru PLL_V0PLL>, <0>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-pcie-ep-demo-v11-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-pcie-ep-demo-v11-linux.dts deleted file mode 100644 index 4e160c2ec..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-pcie-ep-demo-v11-linux.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-pcie-ep-demo.dtsi" -#include "rk3588-linux.dtsi" - -/ { - model = "Rockchip RK3588 PCIE EP Demo V11 Board"; - compatible = "rockchip,rk3588-pcie-ep-demo-v11", "rockchip,rk3588"; -}; - -&hdmi1_in_vp2 { - status = "okay"; -}; - -&route_hdmi1 { - status = "okay"; - force-output; - connect = <&vp2_out_hdmi1>; - - force_timing { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hfront-porch = <24>; - hsync-len = <136>; - hback-porch = <160>; - vfront-porch = <3>; - vsync-len = <6>; - vback-porch = <29>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-pcie-ep-demo-v11.dts b/arch/arm64/boot/dts/rockchip/rk3588-pcie-ep-demo-v11.dts deleted file mode 100644 index eb5b4f8e4..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-pcie-ep-demo-v11.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-pcie-ep-demo.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588 PCIE EP Demo V11 Board"; - compatible = "rockchip,rk3588-pcie-ep-demo-v11", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-pcie-ep-demo.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-pcie-ep-demo.dtsi deleted file mode 100644 index f44fd9e15..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-pcie-ep-demo.dtsi +++ /dev/null @@ -1,641 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Rockchip Electronics Co., Ltd. - * - */ - -#include "dt-bindings/usb/pd.h" -#include "rk3588.dtsi" -#include -#include -#include -#include -#include -#include -#include "rk3588-rk806-single.dtsi" - -/ { - adc_keys: adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - vol-up-key { - label = "volume up"; - linux,code = ; - press-threshold-microvolt = <17000>; - }; - }; - - dp0_sound: dp0-sound { - status = "disabled"; - compatible = "rockchip,hdmi"; - rockchip,card-name= "rockchip-dp0"; - rockchip,mclk-fs = <512>; - rockchip,cpu = <&spdif_tx2>; - rockchip,codec = <&dp0 1>; - rockchip,jack-det; - }; - - hdmi1_sound: hdmi1-sound { - status = "disabled"; - compatible = "rockchip,hdmi"; - rockchip,mclk-fs = <128>; - rockchip,card-name = "rockchip-hdmi1"; - rockchip,cpu = <&i2s6_8ch>; - rockchip,codec = <&hdmi1>; - rockchip,jack-det; - }; - - leds: leds { - compatible = "gpio-leds"; - work_led: work { - gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - pcie30_avdd1v8: pcie30-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - pcie30_avdd0v75: pcie30-avdd0v75 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v75"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - vin-supply = <&avdd_0v75_s0>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - bar0_region: bar0-region@3c000000 { - reg = <0x0 0x3c000000 0x0 0x00400000>; - }; - bar2_region: bar2-region@40000000 { - reg = <0x0 0x40000000 0x0 0x04000000>; - }; - }; - - test-power { - status = "okay"; - }; - - vbus5v0_typec: vbus5v0-typec { - compatible = "regulator-fixed"; - regulator-name = "vbus5v0_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; -}; - -&av1d_mmu { - status = "okay"; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&dp0 { - status = "okay"; -}; - -&dp0_in_vp2 { - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - mem-supply = <&vdd_gpu_mem_s0>; - status = "okay"; -}; - -&hdmi1 { - enable-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmim2_tx1_cec &hdmim1_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda>; - status = "okay"; -}; - -&hdmi1_in_vp0 { - status = "okay"; -}; - -&hdmi1_sound { - status = "okay"; -}; - -&hdptxphy_hdmi1 { - status = "okay"; -}; - -&gmac0 { - /* Use rgmii-rxid mode to disable rx delay inside Soc */ - phy-mode = "rgmii-rxid"; - clock_in_out = "output"; - - snps,reset-gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus - ð0_pins>; - - tx_delay = <0x44>; - /* rx_delay = <0x4f>; */ - - phy-handle = <&rgmii_phy0>; - status = "okay"; -}; - -&iep { - status = "okay"; -}; - -&iep_mmu { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - - vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big0_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { - compatible = "rockchip,rk8603"; - reg = <0x43>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big1_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1m2_xfer>; - - vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_npu_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4m2_xfer>; - - usbc0: fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vbus5v0_typec>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - ; - source-pdos = - ; - - altmodes { - #address-cells = <1>; - #size-cells = <0>; - - altmode@0 { - reg = <0>; - svid = <0xff01>; - vdo = <0xffffffff>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; - }; - }; - - port@1 { - reg = <1>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; - }; - }; - }; - }; - }; -}; - -&i2s6_8ch { - status = "okay"; -}; - -&jpegd { - status = "okay"; -}; - -&jpegd_mmu { - status = "okay"; -}; - -&jpege_ccu { - status = "okay"; -}; - -&jpege0 { - status = "okay"; -}; - -&jpege0_mmu { - status = "okay"; -}; - -&jpege1 { - status = "okay"; -}; - -&jpege1_mmu { - status = "okay"; -}; - -&jpege2 { - status = "okay"; -}; - -&jpege2_mmu { - status = "okay"; -}; - -&jpege3 { - status = "okay"; -}; - -&jpege3_mmu { - status = "okay"; -}; - -&mdio0 { - rgmii_phy0: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - clocks = <&cru REFCLKO25M_ETH0_OUT>; - }; -}; - -&mpp_srv { - status = "okay"; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x4 { - compatible = "rockchip,rk3588-pcie-std-ep"; - memory-region = <&bar0_region>, <&bar2_region>; - memory-region-names = "bar0", "bar2"; - status = "okay"; -}; - -&rga3_core0 { - status = "okay"; -}; - -&rga3_0_mmu { - status = "okay"; -}; - -&rga3_core1 { - status = "okay"; -}; - -&rga3_1_mmu { - status = "okay"; -}; - -&rga2 { - status = "okay"; -}; - -&rknpu { - rknpu-supply = <&vdd_npu_s0>; - mem-supply = <&vdd_npu_mem_s0>; - status = "okay"; -}; - -&rknpu_mmu { - status = "okay"; -}; - -&rkvdec_ccu { - status = "okay"; -}; - -&rkvdec0 { - status = "okay"; -}; - -&rkvdec0_mmu { - status = "okay"; -}; - -&rkvdec1 { - status = "okay"; -}; - -&rkvdec1_mmu { - status = "okay"; -}; - -&rkvenc_ccu { - status = "okay"; -}; - -&rkvenc0 { - status = "okay"; -}; - -&rkvenc0_mmu { - status = "okay"; -}; - -&rkvenc1 { - status = "okay"; -}; - -&rkvenc1_mmu { - status = "okay"; -}; - -&rockchip_suspend { - status = "okay"; - rockchip,sleep-debug-en = <1>; -}; - -&route_hdmi1 { - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc_1v8_s0>; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - max-frequency = <200000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&usbdp_phy0_dp { - status = "okay"; -}; - -&usbdp_phy0_u3 { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdp_phy0 { - status = "okay"; - orientation-switch; - svid = <0xff01>; - sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - - port { - #address-cells = <1>; - #size-cells = <0>; - usbdp_phy0_orientation_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; - }; - - usbdp_phy0_dp_altmode_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&dp_altmode_mux>; - }; - }; -}; - -&usbdrd_dwc3_0 { - status = "okay"; - dr_mode = "otg"; - usb-role-switch; - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -&vdpu { - status = "okay"; -}; - -&vdpu_mmu { - status = "okay"; -}; - -&vepu { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -/* vp0 & vp1 splice for 8K output */ -&vp0 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; - rockchip,primary-plane = ; -}; - -&vp1 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; - rockchip,primary-plane = ; -}; - -&vp2 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; - rockchip,primary-plane = ; -}; - -&pinctrl { - - usb-typec { - usbc0_int: usbc0-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - typec5v_pwren: typec5v-pwren { - rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rk806-dual.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rk806-dual.dtsi deleted file mode 100644 index 431b037b1..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-rk806-dual.dtsi +++ /dev/null @@ -1,782 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include -#include - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - num-cs = <2>; - - rk806master: rk806master@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default", "pmic-power-off"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; - pinctrl-1 = <&rk806_dvs1_pwrdn>; - - /* 2800mv-3500mv */ - low_voltage_threshold = <3000>; - /* 2700mv-3400mv */ - shutdown_voltage_threshold = <2700>; - /* 140 160 */ - shutdown_temperture_threshold = <160>; - hotdie_temperture_threshold = <115>; - - /* 0: restart PMU; - * 1: reset all the power off reset registers, - * forcing the state to switch to ACTIVE mode; - * 2: Reset all the power off reset registers, - * forcing the state to switch to ACTIVE mode, - * and simultaneously pull down the RESETB PIN for 5mS before releasing - */ - pmic-reset-func = <1>; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - pwrkey { - status = "okay"; - }; - - pinctrl_rk806: pinctrl_rk806 { - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: rk806_dvs1_null { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs1_slp: rk806_dvs1_slp { - pins = "gpio_pwrctrl1"; - function = "pin_fun1"; - }; - - rk806_dvs1_pwrdn: rk806_dvs1_pwrdn { - pins = "gpio_pwrctrl1"; - function = "pin_fun2"; - }; - - rk806_dvs1_rst: rk806_dvs1_rst { - pins = "gpio_pwrctrl1"; - function = "pin_fun3"; - }; - - rk806_dvs2_null: rk806_dvs2_null { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_slp: rk806_dvs2_slp { - pins = "gpio_pwrctrl2"; - function = "pin_fun1"; - }; - - rk806_dvs2_pwrdn: rk806_dvs2_pwrdn { - pins = "gpio_pwrctrl2"; - function = "pin_fun2"; - }; - - rk806_dvs2_rst: rk806_dvs2_rst { - pins = "gpio_pwrctrl2"; - function = "pin_fun3"; - }; - - rk806_dvs2_dvs: rk806_dvs2_dvs { - pins = "gpio_pwrctrl2"; - function = "pin_fun4"; - }; - - rk806_dvs2_gpio: rk806_dvs2_gpio { - pins = "gpio_pwrctrl2"; - function = "pin_fun5"; - }; - - rk806_dvs3_null: rk806_dvs3_null { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - rk806_dvs3_slp: rk806_dvs3_slp { - pins = "gpio_pwrctrl3"; - function = "pin_fun1"; - }; - - rk806_dvs3_pwrdn: rk806_dvs3_pwrdn { - pins = "gpio_pwrctrl3"; - function = "pin_fun2"; - }; - - rk806_dvs3_rst: rk806_dvs3_rst { - pins = "gpio_pwrctrl3"; - function = "pin_fun3"; - }; - - rk806_dvs3_dvs: rk806_dvs3_dvs { - pins = "gpio_pwrctrl3"; - function = "pin_fun4"; - }; - - rk806_dvs3_gpio: rk806_dvs3_gpio { - pins = "gpio_pwrctrl3"; - function = "pin_fun5"; - }; - }; - - regulators { - vdd_gpu_s0: DCDC_REG1 { - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-enable-ramp-delay = <400>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_npu_s0: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_npu_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu_mem_s0: DCDC_REG5 { - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <400>; - regulator-name = "vdd_gpu_mem_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_npu_mem_s0: DCDC_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_npu_mem_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: DCDC_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_2v0_pldo_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vdd_vdenc_mem_s0: DCDC_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_mem_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd2_ddr_s3: DCDC_REG9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v1_nldo_s3: DCDC_REG10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1100000>; - }; - }; - - avcc_1v8_s0: PLDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "avcc_1v8_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd1_1v8_ddr_s3: PLDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd1_1v8_ddr_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_codec_s0: PLDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "avcc_1v8_codec_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s3: PLDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_sd_s0: PLDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vccio_sd_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_1v8_s3: PLDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "vccio_1v8_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: NLDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_0v75_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd2l_0v9_ddr_s3: NLDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdd2l_0v9_ddr_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vdd_0v75_hdmi_edp_s0: NLDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <837500>; - regulator-max-microvolt = <837500>; - regulator-name = "vdd_0v75_hdmi_edp_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd_0v75_s0: NLDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "avdd_0v75_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: NLDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_0v85_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - rk806slave: rk806slave@1 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x01>; - - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, <&rk806_slave_dvs3_null>; - - /* 0: restart PMU; - * 1: reset all the power off reset registers, - * forcing the state to switch to ACTIVE mode; - * 2: Reset all the power off reset registers, - * forcing the state to switch to ACTIVE mode, - * and simultaneously pull down the RESETB PIN for 5mS before releasing - */ - pmic-reset-func = <1>; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_2v0_pldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - pwrkey { - status = "disabled"; - }; - - pinctrl_slave_rk806: pinctrl_slave_rk806 { - gpio-controller; - #gpio-cells = <2>; - - rk806_slave_dvs1_null: rk806_slave_dvs1_null { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_slave_dvs1_slp: rk806_slave_dvs1_slp { - pins = "gpio_pwrctrl1"; - function = "pin_fun1"; - }; - - rk806_slave_dvs1_pwrdn: rk806_slave_dvs1_pwrdn { - pins = "gpio_pwrctrl1"; - function = "pin_fun2"; - }; - - rk806_slave_dvs1_rst: rk806_slave_dvs1_rst { - pins = "gpio_pwrctrl1"; - function = "pin_fun3"; - }; - - rk806_slave_dvs2_null: rk806_slave_dvs2_null { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_slave_dvs2_slp: rk806_slave_dvs2_slp { - pins = "gpio_pwrctrl2"; - function = "pin_fun1"; - }; - - rk806_slave_dvs2_pwrdn: rk806_slave_dvs2_pwrdn { - pins = "gpio_pwrctrl2"; - function = "pin_fun2"; - }; - - rk806_slave_dvs2_rst: rk806_slave_dvs2_rst { - pins = "gpio_pwrctrl2"; - function = "pin_fun3"; - }; - - rk806_slave_dvs2_dvs: rk806_slave_dvs2_dvs { - pins = "gpio_pwrctrl2"; - function = "pin_fun4"; - }; - - rk806_slave_dvs2_gpio: rk806_slave_dvs2_gpio { - pins = "gpio_pwrctrl2"; - function = "pin_fun5"; - }; - - rk806_slave_dvs3_null: rk806_slave_dvs3_null { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - rk806_slave_dvs3_slp: rk806_slave_dvs3_slp { - pins = "gpio_pwrctrl3"; - function = "pin_fun1"; - }; - - rk806_slave_dvs3_pwrdn: rk806_slave_dvs3_pwrdn { - pins = "gpio_pwrctrl3"; - function = "pin_fun2"; - }; - - rk806_slave_dvs3_rst: rk806_slave_dvs3_rst { - pins = "gpio_pwrctrl3"; - function = "pin_fun3"; - }; - - rk806_slave_dvs3_dvs: rk806_slave_dvs3_dvs { - pins = "gpio_pwrctrl3"; - function = "pin_fun4"; - }; - - rk806_slave_dvs3_gpio: rk806_slave_dvs3_gpio { - pins = "gpio_pwrctrl3"; - function = "pin_fun5"; - }; - }; - - regulators { - vdd_cpu_big1_s0: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big0_s0: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_mem_s0: DCDC_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_big1_mem_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - - vdd_cpu_big0_mem_s0: DCDC_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_big0_mem_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: DCDC_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_1v8_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_mem_s0: DCDC_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_mem_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vddq_ddr_s0: DCDC_REG9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: DCDC_REG10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_cam_s0: PLDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_1v8_cam_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd1v8_ddr_pll_s0: PLDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "avdd1v8_ddr_pll_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_1v8_pll_s0: PLDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_1v8_pll_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_sd_s0: PLDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_sd_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_2v8_cam_s0: PLDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_2v8_cam_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: PLDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_pll_s0: NLDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_0v75_pll_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_pll_s0: NLDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_ddr_pll_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd_0v85_s0: NLDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-ramp-delay = <12500>; - regulator-name = "avdd_0v85_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd_1v2_cam_s0: NLDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-ramp-delay = <12500>; - regulator-name = "avdd_1v2_cam_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd_1v2_s0: NLDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-ramp-delay = <12500>; - regulator-name = "avdd_1v2_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rk806-single.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rk806-single.dtsi deleted file mode 100644 index 62f340378..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-rk806-single.dtsi +++ /dev/null @@ -1,396 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include -#include - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - num-cs = <1>; - - rk806single: rk806single@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default", "pmic-power-off"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; - pinctrl-1 = <&rk806_dvs1_pwrdn>; - - /* 2800mv-3500mv */ - low_voltage_threshold = <3000>; - /* 2700mv-3400mv */ - shutdown_voltage_threshold = <2700>; - /* 140 160 */ - shutdown_temperture_threshold = <160>; - hotdie_temperture_threshold = <115>; - - /* 0: restart PMU; - * 1: reset all the power off reset registers, - * forcing the state to switch to ACTIVE mode; - * 2: Reset all the power off reset registers, - * forcing the state to switch to ACTIVE mode, - * and simultaneously pull down the RESETB PIN for 5mS before releasing - */ - pmic-reset-func = <1>; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - pwrkey { - status = "okay"; - }; - - pinctrl_rk806: pinctrl_rk806 { - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: rk806_dvs1_null { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs1_slp: rk806_dvs1_slp { - pins = "gpio_pwrctrl1"; - function = "pin_fun1"; - }; - - rk806_dvs1_pwrdn: rk806_dvs1_pwrdn { - pins = "gpio_pwrctrl1"; - function = "pin_fun2"; - }; - - rk806_dvs1_rst: rk806_dvs1_rst { - pins = "gpio_pwrctrl1"; - function = "pin_fun3"; - }; - - rk806_dvs2_null: rk806_dvs2_null { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_slp: rk806_dvs2_slp { - pins = "gpio_pwrctrl2"; - function = "pin_fun1"; - }; - - rk806_dvs2_pwrdn: rk806_dvs2_pwrdn { - pins = "gpio_pwrctrl2"; - function = "pin_fun2"; - }; - - rk806_dvs2_rst: rk806_dvs2_rst { - pins = "gpio_pwrctrl2"; - function = "pin_fun3"; - }; - - rk806_dvs2_dvs: rk806_dvs2_dvs { - pins = "gpio_pwrctrl2"; - function = "pin_fun4"; - }; - - rk806_dvs2_gpio: rk806_dvs2_gpio { - pins = "gpio_pwrctrl2"; - function = "pin_fun5"; - }; - - rk806_dvs3_null: rk806_dvs3_null { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - rk806_dvs3_slp: rk806_dvs3_slp { - pins = "gpio_pwrctrl3"; - function = "pin_fun1"; - }; - - rk806_dvs3_pwrdn: rk806_dvs3_pwrdn { - pins = "gpio_pwrctrl3"; - function = "pin_fun2"; - }; - - rk806_dvs3_rst: rk806_dvs3_rst { - pins = "gpio_pwrctrl3"; - function = "pin_fun3"; - }; - - rk806_dvs3_dvs: rk806_dvs3_dvs { - pins = "gpio_pwrctrl3"; - function = "pin_fun4"; - }; - - rk806_dvs3_gpio: rk806_dvs3_gpio { - pins = "gpio_pwrctrl3"; - function = "pin_fun5"; - }; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: DCDC_REG1 { - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-enable-ramp-delay = <400>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-init-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: DCDC_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: DCDC_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: DCDC_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-name = "vdd_2v0_pldo_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: DCDC_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_3v3_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: DCDC_REG9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: DCDC_REG10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: PLDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "avcc_1v8_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: PLDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s0"; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: PLDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "avdd_1v2_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s0: PLDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_3v3_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: PLDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: PLDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: NLDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_ddr_pll_s0: NLDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_ddr_pll_s0"; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: NLDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <837500>; - regulator-max-microvolt = <837500>; - regulator-name = "avdd_0v75_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: NLDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_0v85_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: NLDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-edp-x0.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-edp-x0.dtsi deleted file mode 100644 index 1dbb39cd3..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-edp-x0.dtsi +++ /dev/null @@ -1,770 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include "dt-bindings/usb/pd.h" -#include "rk3588.dtsi" -#include "rk3588-toybrick.dtsi" -#include "rk3588-rk806-single.dtsi" - -/ { - es8388_sound: es8388-sound { - status = "okay"; - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "rockchip,es8388-codec"; - simple-audio-card,dai-link@0 { - format = "i2s"; - cpu { - sound-dai = <&i2s0_8ch>; - }; - codec { - sound-dai = <&es8388>; - }; - }; - }; - - pcie20_avdd0v85: pcie20-avdd0v85 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd0v85"; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&vdd_0v85_s0>;//csq - }; - - pcie20_avdd1v8: pcie20-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd1v8"; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - pcie30_avdd0v75: pcie30-avdd0v75 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v75"; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - vin-supply = <&avdd_0v75_s0>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - rk_headset: rk-headset { - status = "okay"; - compatible = "rockchip_headset"; - headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - io-channels = <&saradc 3>; - }; - - vbus5v0_typec: vbus5v0-typec { - compatible = "regulator-fixed"; - regulator-name = "vbus5v0_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; - }; - - vcc3v3_lcd_n: vcc3v3-lcd0-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd0_n"; - regulator-boot-on; - enable-active-high; - gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc_1v8_s0>; - }; - - vcc3v3_pcie30: vcc3v3-pcie30 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_host: vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - }; - - vcc_mipicsi0: vcc-mipicsi0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipicsi0_pwr>; - regulator-name = "vcc_mipicsi0"; - enable-active-high; - }; - - vcc_mipicsi1: vcc-mipicsi1-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipicsi1_pwr>; - regulator-name = "vcc_mipicsi1"; - enable-active-high; - }; - - vcc_mipidcphy0: vcc-mipidcphy0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipidcphy0_pwr>; - regulator-name = "vcc_mipicsi1"; - enable-active-high; - }; - - wireless_bluetooth: wireless-bluetooth { - compatible = "bluetooth-platdata"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "rts_gpio"; - pinctrl-0 = <&uart8m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; - pinctrl-1 = <&uart8_gpios>; - BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; - BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; - BT,wake_host_irq = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - wifi_chip_type = "ap6255"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; - WIFI,host_wake_irq = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; - WIFI,poweren_gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - panel-edp { - compatible = "innolux,p120zdg-bf4", "simple-panel"; - backlight = <&backlight>; - power-supply = <&vcc3v3_lcd_edp>; - prepare-delay-ms = <120>; - enable-delay-ms = <120>; - unprepare-delay-ms = <500>; - disable-delay-ms = <120>; - width-mm = <254>; - height-mm = <169>; - panel-timing { - clock-frequency = <200000000>; - hactive = <1536>; - vactive = <2048>; - hfront-porch = <12>; - hsync-len = <16>; - hback-porch = <48>; - vfront-porch = <8>; - vsync-len = <4>; - vback-porch = <8>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - panel_in_edp: endpoint { - remote-endpoint = <&edp_out_panel>; - }; - }; - }; - - vcc3v3_lcd_edp: vcc3v3-lcd-edp { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd_edp"; - gpio = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vcc_3v3_s3>; - }; -}; - -&backlight { - pwms = <&pwm2 0 25000 0>; - status = "okay"; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&dp0 { - status = "disabled"; -}; - -&dp0_in_vp2 { - status = "disabled"; -}; - -&dp1 { - pinctrl-names = "default"; - pinctrl-0 = <&dp1_hpd>; - hpd-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; - status = "disabled"; -}; - -&dp1_in_vp2 { - status = "disabled"; -}; - -/* - * mipi_dcphy0 needs to be enabled - * when dsi0 is enabled - */ -&dsi0 { - status = "disabled"; -}; - -&dsi0_in_vp2 { - status = "disabled"; -}; - -&dsi0_in_vp3 { - status = "disabled"; -}; - -&edp1 { - force-hpd; - status = "okay"; - ports { - port@1 { - reg = <1>; - edp_out_panel: endpoint { - remote-endpoint = <&panel_in_edp>; - }; - }; - }; -}; - -&edp1_in_vp2 { - status = "okay"; -}; - -&hdptxphy1 { - status = "okay"; -}; - -&dsi0_panel { - power-supply = <&vcc3v3_lcd_n>; - reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rst_gpio>; -}; - -/* - * mipi_dcphy1 needs to be enabled - * when dsi1 is enabled - */ -&dsi1 { - status = "disabled"; -}; - -&dsi1_in_vp2 { - status = "disabled"; -}; - -&dsi1_in_vp3 { - status = "disabled"; -}; - -&dsi1_panel { - power-supply = <&vcc3v3_lcd_n>; - - /* - * because in hardware, the two screens share the reset pin, - * so reset-gpios need only in dsi1 enable and dsi0 disabled - * case. - */ - - //reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; - //pinctrl-names = "default"; - //pinctrl-0 = <&lcd_rst_gpio>; -}; - -&gmac0 { - /* Use rgmii-rxid mode to disable rx delay inside Soc */ - phy-mode = "rgmii-rxid"; - clock_in_out = "output"; - - snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - - tx_delay = <0x43>; - /* rx_delay = <0x3f>; */ - - phy-handle = <&rgmii_phy>; - status = "okay"; -}; - -&hdmi0 { - enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi0_in_vp0 { - status = "okay"; -}; - -&hdmi0_sound { - status = "okay"; -}; - -&hdptxphy_hdmi0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big0_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { - compatible = "rockchip,rk8603"; - reg = <0x43>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big1_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - - usbc0: fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio3>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vbus5v0_typec>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - ; - source-pdos = - ; - - altmodes { - #address-cells = <1>; - #size-cells = <0>; - - altmode@0 { - reg = <0>; - svid = <0xff01>; - vdo = <0xffffffff>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; - }; - }; - - port@1 { - reg = <1>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; - }; - }; - }; - }; - }; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - }; - - vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_npu_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c6 { - status = "okay"; - gt1x: gt1x@14 { - compatible = "goodix,gt1x"; - reg = <0x14>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_gpio>; - goodix,rst-gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; - goodix,irq-gpio = <&gpio0 RK_PB0 IRQ_TYPE_LEVEL_LOW>; - }; - - gsl3673: gsl3673@40 { - compatible = "GSL,GSL3673"; - reg = <0x40>; - screen_max_x = <1536>; - screen_max_y = <2048>; - irq_gpio_number = <&gpio1 RK_PA6 IRQ_TYPE_LEVEL_LOW>; - rst_gpio_number = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; - }; -}; - -&i2c7 { - status = "okay"; - es8388: es8388@11 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "everest,es8388", "everest,es8323"; - reg = <0x11>; - clocks = <&mclkout_i2s0>; - clock-names = "mclk"; - assigned-clocks = <&mclkout_i2s0>; - assigned-clock-rates = <12288000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk>; - spk-con-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; - hp-con-gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - extcon = <&rk_headset>; - }; -}; - -&hdmirx_ctrler { - status = "okay"; - hdmirx-det-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmim1_rx &hdmirx_det>; -}; - -&i2s5_8ch { - status = "okay"; -}; - -&mdio0 { - rgmii_phy: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - }; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&mipi_dcphy1 { - status = "disabled"; -}; - -&pcie2x1l0 { - reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pcie2x1l1 { - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&rtl8111_isolate>; - status = "okay"; -}; - -&pcie30phy { - rockchip,pcie30-phymode = ; - status = "okay"; -}; - -&pcie3x4 { - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - status = "disabled"; -}; - -&pinctrl { - cam { - mipicsi0_pwr: mipicsi0-pwr { - rockchip,pins = - /* camera power en */ - <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - mipicsi1_pwr: mipicsi1-pwr { - rockchip,pins = - /* camera power en */ - <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - mipidcphy0_pwr: mipidcphy0-pwr { - rockchip,pins = - /* camera power en */ - <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - dp { - dp1_hpd: dp1-hpd { - rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi { - hdmirx_det: hdmirx-det { - rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - headphone { - hp_det: hp-det { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lcd { - lcd_rst_gpio: lcd-rst-gpio { - rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - rtl8111 { - rtl8111_isolate: rtl8111-isolate { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - touch { - touch_gpio: touch-gpio { - rockchip,pins = - <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>, - <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - usbc0_int: usbc0-int { - rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - typec5v_pwren: typec5v-pwren { - rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-bluetooth { - uart8_gpios: uart8-gpios { - rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reset_gpio: bt-reset-gpio { - rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_gpio: bt-wake-gpio { - rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_irq_gpio: bt-irq-gpio { - rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - wifi_poweren_gpio: wifi-poweren-gpio { - rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm2 { - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -&u2phy1_otg { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; -}; - -&uart8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>; -}; - -&usbdp_phy0 { - orientation-switch; - svid = <0xff01>; - sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - - port { - #address-cells = <1>; - #size-cells = <0>; - usbdp_phy0_orientation_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; - }; - - usbdp_phy0_dp_altmode_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&dp_altmode_mux>; - }; - }; -}; - -&usbdp_phy1 { - rockchip,dp-lane-mux = <2 3>; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - usb-role-switch; - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -&usbhost3_0 { - status = "disabled"; -}; - -&usbhost_dwc3_0 { - status = "disabled"; -}; - diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-imx258.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-imx258.dtsi deleted file mode 100644 index 3f3c10e87..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-imx258.dtsi +++ /dev/null @@ -1,323 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ -&csi2_dphy0_hw { - status = "okay"; -}; - -&csi2_dphy0 { - status = "okay"; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - mipi_in_ucam0: endpoint@1 { - reg = <1>; - remote-endpoint = <&ucam_out0>; - data-lanes = <1 2 3 4>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - csidphy0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi2_csi2_input>; - }; - }; - }; -}; - -&i2c3 { - status = "okay"; - dw9714: dw9714@c { - compatible = "silicon touch,dw9714"; - status = "okay"; - reg = <0x0c>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,vcm-start-current = <20>; - rockchip,vcm-rated-current = <120>; - rockchip,vcm-step-mode = <13>; - }; - - imx258_eeprom: imx258_eeprom@50 { - compatible = "otp,imx258_eeprom"; - status = "okay"; - reg = <0x50>; - }; - - imx258: imx258@10 { - compatible = "sony,imx258"; - reg = <0x10>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; - clock-names = "xvclk"; - pinctrl-names = "default"; - pinctrl-0 = <&mipim0_camera3_clk>; - power-domains = <&power RK3588_PD_VI>; - avdd-supply = <&vcc_mipicsi0>; - pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "GEIR180089"; - rockchip,camera-module-lens-name = "LG500627G"; - eeprom-ctrl = <&imx258_eeprom>; - lens-focus = <&dw9714>; - port { - ucam_out0: endpoint { - remote-endpoint = <&mipi_in_ucam0>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&mipi2_csi2 { - status = "okay"; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - mipi2_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy0_out>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - mipi2_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in2>; - }; - }; - }; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds2 { - status = "okay"; - port { - cif_mipi_in2: endpoint { - remote-endpoint = <&mipi2_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds2_sditf { - status = "okay"; - port { - mipi_lvds_sditf: endpoint { - remote-endpoint = <&isp0_vir0>; - }; - }; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp0 { - status = "okay"; -}; - -&isp0_mmu { - status = "okay"; -}; - -&rkisp0_vir0 { - status = "okay"; - port { - #address-cells = <1>; - #size-cells = <0>; - isp0_vir0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds_sditf>; - }; - }; -}; - -&csi2_dcphy0 { - status = "okay"; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - mipi_in_1_ucam0: endpoint@1 { - reg = <1>; - remote-endpoint = <&imx258_1_out0>; - data-lanes = <1 2 3 4>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - csidcphy0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi0_csi2_input>; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; - dw9714_1: dw9714_1@c { - compatible = "silicon touch,dw9714"; - status = "okay"; - reg = <0x0c>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,vcm-start-current = <20>; - rockchip,vcm-rated-current = <120>; - rockchip,vcm-step-mode = <13>; - }; - - imx258_1_eeprom: imx258_1_eeprom@50 { - compatible = "otp,imx258_eeprom"; - status = "okay"; - reg = <0x50>; - }; - - imx258_1: imx258_1@1a { - compatible = "sony,imx258"; - reg = <0x1a>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; - clock-names = "xvclk"; - pinctrl-names = "default"; - pinctrl-0 = <&mipim0_camera1_clk>; - power-domains = <&power RK3588_PD_VI>; - avdd-supply = <&vcc_mipidcphy0>; - pwdn-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_LOW>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "GEIR180089"; - rockchip,camera-module-lens-name = "LG500627G"; - eeprom-ctrl = <&imx258_1_eeprom>; - lens-focus = <&dw9714_1>; - port { - imx258_1_out0: endpoint { - remote-endpoint = <&mipi_in_1_ucam0>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -// use dcphy0 isp1 -&mipi_dcphy0 { - status = "okay"; -}; - -&mipi0_csi2 { - status = "okay"; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - mipi0_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidcphy0_out>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - mipi0_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in0>; - }; - }; - }; -}; - -&rkcif_mipi_lvds { - status = "okay"; - port { - cif_mipi_in0: endpoint { - remote-endpoint = <&mipi0_csi2_output>; - }; - }; -}; - -#if 0 - -&rkcif_mipi_lvds_sditf { - status = "okay"; - port { - mipi_lvds_sditf_1: endpoint { - remote-endpoint = <&isp0_vir1>; - }; - }; -}; - -&rkisp0_vir1 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir1: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds_sditf_1>; - }; - }; -}; - -#endif - -&rkisp1 { - status = "okay"; -}; - -&isp1_mmu { - status = "okay"; -}; - -&rkcif_mipi_lvds_sditf { - status = "okay"; - - port { - mipi1_lvds_sditf: endpoint { - remote-endpoint = <&isp1_vir0>; - }; - }; -}; - -&rkisp1_vir0 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp1_vir0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi1_lvds_sditf>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0-android.dts b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0-android.dts deleted file mode 100644 index a7f7e398c..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0-android.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-toybrick-x0.dtsi" -#include "rk3588-android.dtsi" -#include "rk3588-toybrick-imx258.dtsi" - -/ { - model = "Rockchip RK3588 TOYBRICK LP4 X10 Board"; - compatible = "rockchip,rk3588-toybrick-x10-android", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0-linux.dts deleted file mode 100644 index e7f40c010..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0-linux.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-toybrick-x0.dtsi" -#include "rk3588-linux.dtsi" -//#include "rk3588-toybrick-imx258.dtsi" -/ { - model = "Rockchip RK3588 TOYBRICK X10 Board"; - compatible = "rockchip,rk3588-toybrick-x10-linux", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dtsi deleted file mode 100644 index b404fd139..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dtsi +++ /dev/null @@ -1,754 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include "dt-bindings/usb/pd.h" -#include "rk3588.dtsi" -#include "rk3588-toybrick.dtsi" -#include "rk3588-rk806-single.dtsi" - -/ { - /* If hdmirx node is disabled, delete the reserved-memory node here. */ - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* Reserve 128MB memory for hdmirx-controller@fdee0000 */ - cma { - compatible = "shared-dma-pool"; - reusable; - reg = <0x0 (256 * 0x100000) 0x0 (128 * 0x100000)>; - linux,cma-default; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - pwms = <&pwm9 0 50000 0>; - cooling-levels = <0 50 100 150 200 255>; - rockchip,temp-trips = < - 50000 1 - 55000 2 - 60000 3 - 65000 4 - 70000 5 - >; - }; - - hdmiin_dc: hdmiin-dc { - compatible = "rockchip,dummy-codec"; - #sound-dai-cells = <0>; - }; - - es8388_sound: es8388-sound { - status = "okay"; - compatible = "rockchip,multicodecs-card"; - rockchip,card-name = "rockchip,es8388"; - hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; - io-channels = <&saradc 3>; - io-channel-names = "adc-detect"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - spk-con-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; - hp-con-gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - rockchip,format = "i2s"; - rockchip,mclk-fs = <256>; - rockchip,cpu = <&i2s0_8ch>; - rockchip,codec = <&es8388>; - rockchip,audio-routing = - "Headphone", "LOUT1", - "Headphone", "ROUT1", - "Speaker", "LOUT2", - "Speaker", "ROUT2", - "Headphone", "Headphone Power", - "Headphone", "Headphone Power", - "Speaker", "Speaker Power", - "Speaker", "Speaker Power", - "LINPUT1", "Main Mic", - "LINPUT2", "Main Mic", - "RINPUT1", "Headset Mic", - "RINPUT2", "Headset Mic"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - play-pause-key { - label = "playpause"; - linux,code = ; - press-threshold-microvolt = <2000>; - }; - }; - - hdmiin-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip,hdmiin"; - simple-audio-card,bitclock-master = <&dailink0_master>; - simple-audio-card,frame-master = <&dailink0_master>; - status = "okay"; - simple-audio-card,cpu { - sound-dai = <&i2s7_8ch>; - }; - dailink0_master: simple-audio-card,codec { - sound-dai = <&hdmiin_dc>; - }; - }; - - pcie20_avdd0v85: pcie20-avdd0v85 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd0v85"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&vdd_0v85_s0>; - }; - - pcie20_avdd1v8: pcie20-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - pcie30_avdd0v75: pcie30-avdd0v75 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v75"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - vin-supply = <&avdd_0v75_s0>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - rk_headset: rk-headset { - status = "disabled"; - compatible = "rockchip_headset"; - headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - io-channels = <&saradc 3>; - }; - - vbus5v0_typec: vbus5v0-typec { - compatible = "regulator-fixed"; - regulator-name = "vbus5v0_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; - }; - - vcc3v3_lcd_n: vcc3v3-lcd0-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd0_n"; - regulator-boot-on; - enable-active-high; - gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc_1v8_s0>; - }; - - vcc3v3_pcie30: vcc3v3-pcie30 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_host: vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - }; - - vcc_mipicsi0: vcc-mipicsi0-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_mipicsi0"; - enable-active-high; - }; - - vcc_mipicsi1: vcc-mipicsi1-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_mipicsi1"; - enable-active-high; - }; - - vcc_mipidcphy0: vcc-mipidcphy0-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_mipicsi1"; - enable-active-high; - }; - - wireless_bluetooth: wireless-bluetooth { - compatible = "bluetooth-platdata"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "rts_gpio"; - pinctrl-0 = <&uart8m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; - pinctrl-1 = <&uart8_gpios>; - BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; - BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; - BT,wake_host_irq = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - wifi_chip_type = "ap6255"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; - WIFI,host_wake_irq = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; - WIFI,poweren_gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; -}; - -&backlight { - pwms = <&pwm2 0 25000 0>; - status = "okay"; -}; - -&can2 { - status = "okay"; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&dp0 { - status = "okay"; -}; - -&dp0_in_vp2 { - status = "okay"; -}; - -/* - * mipi_dcphy0 needs to be enabled - * when dsi0 is enabled - */ -&dsi0 { - status = "disabled"; -}; - -&dsi0_in_vp2 { - status = "disabled"; -}; - -&dsi0_in_vp3 { - status = "okay"; -}; - -&dsi0_panel { - power-supply = <&vcc3v3_lcd_n>; - reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rst_gpio>; -}; - -/* - * mipi_dcphy1 needs to be enabled - * when dsi1 is enabled - */ -&dsi1 { - status = "disabled"; -}; - -&dsi1_in_vp2 { - status = "disabled"; -}; - -&dsi1_in_vp3 { - status = "disabled"; -}; - -&dsi1_panel { - power-supply = <&vcc3v3_lcd_n>; - - /* - * because in hardware, the two screens share the reset pin, - * so reset-gpios need only in dsi1 enable and dsi0 disabled - * case. - */ - - //reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; - //pinctrl-names = "default"; - //pinctrl-0 = <&lcd_rst_gpio>; -}; - -&gmac0 { - /* Use rgmii-rxid mode to disable rx delay inside Soc */ - phy-mode = "rgmii-rxid"; - clock_in_out = "output"; - - snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - - tx_delay = <0x43>; - /* rx_delay = <0x3f>; */ - - phy-handle = <&rgmii_phy>; - status = "okay"; -}; - -&hdmi0 { - enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi0_in_vp0 { - status = "okay"; -}; - -&hdmi0_sound { - status = "okay"; -}; - -/* Should work with at least 128MB cma reserved above. */ -&hdmirx_ctrler { - status = "okay"; - - /* Effective level used to trigger HPD: 0-low, 1-high */ - hpd-trigger-level = <1>; - hdmirx-det-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmim1_rx &hdmirx_det>; -}; - -&hdptxphy_hdmi0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big0_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { - compatible = "rockchip,rk8603"; - reg = <0x43>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big1_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - clock-frequency = <400000>; - - usbc0: husb311@4e { - compatible = "hynetek,husb311"; - reg = <0x4e>; - interrupt-parent = <&gpio3>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vbus5v0_typec>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - ; - source-pdos = - ; - - altmodes { - #address-cells = <1>; - #size-cells = <0>; - - altmode@0 { - reg = <0>; - svid = <0xff01>; - vdo = <0xffffffff>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; - }; - }; - - port@1 { - reg = <1>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; - }; - }; - }; - }; - }; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - }; - - vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_npu_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c6 { - status = "disabled"; - gt1x: gt1x@14 { - compatible = "goodix,gt1x"; - reg = <0x14>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_gpio>; - goodix,rst-gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; - goodix,irq-gpio = <&gpio0 RK_PB0 IRQ_TYPE_LEVEL_LOW>; - power-supply = <&vcc3v3_lcd_n>; - }; - - gsl3673: gsl3673@40 { - compatible = "GSL,GSL3673"; - reg = <0x40>; - screen_max_x = <1536>; - screen_max_y = <2048>; - irq_gpio_number = <&gpio1 RK_PA6 IRQ_TYPE_LEVEL_LOW>; - rst_gpio_number = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; - }; -}; - -&i2c7 { - status = "okay"; - es8388: es8388@11 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "everest,es8388", "everest,es8323"; - reg = <0x11>; - clocks = <&mclkout_i2s0>; - clock-names = "mclk"; - assigned-clocks = <&mclkout_i2s0>; - assigned-clock-rates = <12288000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk>; - }; -}; - -&i2s5_8ch { - status = "okay"; -}; - -&i2s7_8ch { - status = "okay"; -}; - -&mdio0 { - rgmii_phy: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - }; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&mipi_dcphy1 { - status = "disabled"; -}; - -&pcie2x1l0 { - reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - rockchip,skip-scan-in-resume; - status = "okay"; -}; - -&pcie2x1l1 { - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&rtl8111_isolate>; - status = "okay"; -}; - -&pcie30phy { - rockchip,pcie30-phymode = ; - status = "okay"; -}; - -&pcie3x4 { - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - num-lanes=<2>; - status = "okay"; -}; - -&pinctrl { - hdmi { - hdmirx_det: hdmirx-det { - rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - headphone { - hp_det: hp-det { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lcd { - lcd_rst_gpio: lcd-rst-gpio { - rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - rtl8111 { - rtl8111_isolate: rtl8111-isolate { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - touch { - touch_gpio: touch-gpio { - rockchip,pins = - <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>, - <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - usbc0_int: usbc0-int { - rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - typec5v_pwren: typec5v-pwren { - rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-bluetooth { - uart8_gpios: uart8-gpios { - rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reset_gpio: bt-reset-gpio { - rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_gpio: bt-wake-gpio { - rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_irq_gpio: bt-irq-gpio { - rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - wifi_poweren_gpio: wifi-poweren-gpio { - rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm2 { - status = "okay"; -}; - -&pwm9 { - pinctrl-0 = <&pwm9m1_pins>; - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -&u2phy1_otg { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; -}; - -&uart8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>; -}; - -&usbdp_phy0 { - orientation-switch; - svid = <0xff01>; - sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - - port { - #address-cells = <1>; - #size-cells = <0>; - usbdp_phy0_orientation_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; - }; - - usbdp_phy0_dp_altmode_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&dp_altmode_mux>; - }; - }; -}; - -&usbdp_phy1 { - rockchip,dp-lane-mux = <2 3>; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - usb-role-switch; - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -&usbhost3_0 { - status = "disabled"; -}; - -&usbhost_dwc3_0 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-toybrick.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-toybrick.dtsi deleted file mode 100644 index a76bedcfc..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-toybrick.dtsi +++ /dev/null @@ -1,1267 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - adc_keys: adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - vol-up-key { - label = "volume up"; - linux,code = ; - press-threshold-microvolt = <17000>; - }; - - vol-down-key { - label = "volume down"; - linux,code = ; - press-threshold-microvolt = <417000>; - }; - - menu-key { - label = "menu"; - linux,code = ; - press-threshold-microvolt = <890000>; - }; - - back-key { - label = "back"; - linux,code = ; - press-threshold-microvolt = <1235000>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - dp0_sound: dp0-sound { - status = "disabled"; - compatible = "rockchip,hdmi"; - rockchip,card-name= "rockchip-dp0"; - rockchip,mclk-fs = <512>; - rockchip,cpu = <&spdif_tx2>; - rockchip,codec = <&dp0 1>; - rockchip,jack-det; - }; - - dp1_sound: dp1-sound { - status = "disabled"; - compatible = "rockchip,hdmi"; - rockchip,card-name= "rockchip-dp1"; - rockchip,mclk-fs = <512>; - rockchip,cpu = <&spdif_tx5>; - rockchip,codec = <&dp1 1>; - rockchip,jack-det; - }; - - hdmi0_sound: hdmi0-sound { - status = "disabled"; - compatible = "rockchip,hdmi"; - rockchip,mclk-fs = <128>; - rockchip,card-name = "rockchip-hdmi0"; - rockchip,cpu = <&i2s5_8ch>; - rockchip,codec = <&hdmi0>; - rockchip,jack-det; - }; - - hdmi1_sound: hdmi1-sound { - status = "disabled"; - compatible = "rockchip,hdmi"; - rockchip,mclk-fs = <128>; - rockchip,card-name = "rockchip-hdmi1"; - rockchip,cpu = <&i2s6_8ch>; - rockchip,codec = <&hdmi1>; - rockchip,jack-det; - }; - - leds: leds { - compatible = "gpio-leds"; - work_led: work { - gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - spdif_tx1_dc: spdif-tx1-dc { - status = "disabled"; - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - spdif_tx1_sound: spdif-tx1-sound { - status = "disabled"; - compatible = "simple-audio-card"; - simple-audio-card,name = "rockchip,spdif-tx1"; - simple-audio-card,mclk-fs = <128>; - simple-audio-card,cpu { - sound-dai = <&spdif_tx1>; - }; - simple-audio-card,codec { - sound-dai = <&spdif_tx1_dc>; - }; - }; - - test-power { - status = "okay"; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usbdcin: vcc5v0-usbdcin { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usbdcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usbdcin>; - }; - - /* - *in TB-RK3588 gpio0 RK_PB6 for MIPI dsi tp - */ - - spi2: spi@feb20000 { - compatible = "rockchip,rk3066-spi"; - reg = <0x0 0xfeb20000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac1 15>, <&dmac1 16>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - num-cs = <2>; - status = "okay"; - }; - - - /* - *just for rk3588s-evb4 in rk3588-rk806-single.dtsi - *in TB-RK3588 gpio1 RK_PA6 for edp tp - */ - vcc_1v2_cam_s0: vcc-1v2-cam-s0 { - status = "disabled"; - compatible = "regulator-fixed"; - regulator-name = "vcc_1v2_cam_s0"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vcc_3v3_s3>; - regulator-state-mem { - regulator-off-in-suspend; - }; - - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_3v3_sd_s0: vcc-3v3-sd-s0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_sd_s0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; - enable-active-low; - vin-supply = <&vcc_3v3_s3>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&av1d_mmu { - status = "okay"; -}; - -&dsi0 { - status = "disabled"; - //rockchip,lane-rate = <1000>; - dsi0_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight>; - reset-delay-ms = <60>; - enable-delay-ms = <60>; - prepare-delay-ms = <60>; - unprepare-delay-ms = <60>; - disable-delay-ms = <60>; - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | - MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - panel-init-sequence = [ - 23 00 02 FE 21 - 23 00 02 04 00 - 23 00 02 00 64 - 23 00 02 2A 00 - 23 00 02 26 64 - 23 00 02 54 00 - 23 00 02 50 64 - 23 00 02 7B 00 - 23 00 02 77 64 - 23 00 02 A2 00 - 23 00 02 9D 64 - 23 00 02 C9 00 - 23 00 02 C5 64 - 23 00 02 01 71 - 23 00 02 27 71 - 23 00 02 51 71 - 23 00 02 78 71 - 23 00 02 9E 71 - 23 00 02 C6 71 - 23 00 02 02 89 - 23 00 02 28 89 - 23 00 02 52 89 - 23 00 02 79 89 - 23 00 02 9F 89 - 23 00 02 C7 89 - 23 00 02 03 9E - 23 00 02 29 9E - 23 00 02 53 9E - 23 00 02 7A 9E - 23 00 02 A0 9E - 23 00 02 C8 9E - 23 00 02 09 00 - 23 00 02 05 B0 - 23 00 02 31 00 - 23 00 02 2B B0 - 23 00 02 5A 00 - 23 00 02 55 B0 - 23 00 02 80 00 - 23 00 02 7C B0 - 23 00 02 A7 00 - 23 00 02 A3 B0 - 23 00 02 CE 00 - 23 00 02 CA B0 - 23 00 02 06 C0 - 23 00 02 2D C0 - 23 00 02 56 C0 - 23 00 02 7D C0 - 23 00 02 A4 C0 - 23 00 02 CB C0 - 23 00 02 07 CF - 23 00 02 2F CF - 23 00 02 58 CF - 23 00 02 7E CF - 23 00 02 A5 CF - 23 00 02 CC CF - 23 00 02 08 DD - 23 00 02 30 DD - 23 00 02 59 DD - 23 00 02 7F DD - 23 00 02 A6 DD - 23 00 02 CD DD - 23 00 02 0E 15 - 23 00 02 0A E9 - 23 00 02 36 15 - 23 00 02 32 E9 - 23 00 02 5F 15 - 23 00 02 5B E9 - 23 00 02 85 15 - 23 00 02 81 E9 - 23 00 02 AD 15 - 23 00 02 A9 E9 - 23 00 02 D3 15 - 23 00 02 CF E9 - 23 00 02 0B 14 - 23 00 02 33 14 - 23 00 02 5C 14 - 23 00 02 82 14 - 23 00 02 AA 14 - 23 00 02 D0 14 - 23 00 02 0C 36 - 23 00 02 34 36 - 23 00 02 5D 36 - 23 00 02 83 36 - 23 00 02 AB 36 - 23 00 02 D1 36 - 23 00 02 0D 6B - 23 00 02 35 6B - 23 00 02 5E 6B - 23 00 02 84 6B - 23 00 02 AC 6B - 23 00 02 D2 6B - 23 00 02 13 5A - 23 00 02 0F 94 - 23 00 02 3B 5A - 23 00 02 37 94 - 23 00 02 64 5A - 23 00 02 60 94 - 23 00 02 8A 5A - 23 00 02 86 94 - 23 00 02 B2 5A - 23 00 02 AE 94 - 23 00 02 D8 5A - 23 00 02 D4 94 - 23 00 02 10 D1 - 23 00 02 38 D1 - 23 00 02 61 D1 - 23 00 02 87 D1 - 23 00 02 AF D1 - 23 00 02 D5 D1 - 23 00 02 11 04 - 23 00 02 39 04 - 23 00 02 62 04 - 23 00 02 88 04 - 23 00 02 B0 04 - 23 00 02 D6 04 - 23 00 02 12 05 - 23 00 02 3A 05 - 23 00 02 63 05 - 23 00 02 89 05 - 23 00 02 B1 05 - 23 00 02 D7 05 - 23 00 02 18 AA - 23 00 02 14 36 - 23 00 02 42 AA - 23 00 02 3D 36 - 23 00 02 69 AA - 23 00 02 65 36 - 23 00 02 8F AA - 23 00 02 8B 36 - 23 00 02 B7 AA - 23 00 02 B3 36 - 23 00 02 DD AA - 23 00 02 D9 36 - 23 00 02 15 74 - 23 00 02 3F 74 - 23 00 02 66 74 - 23 00 02 8C 74 - 23 00 02 B4 74 - 23 00 02 DA 74 - 23 00 02 16 9F - 23 00 02 40 9F - 23 00 02 67 9F - 23 00 02 8D 9F - 23 00 02 B5 9F - 23 00 02 DB 9F - 23 00 02 17 DC - 23 00 02 41 DC - 23 00 02 68 DC - 23 00 02 8E DC - 23 00 02 B6 DC - 23 00 02 DC DC - 23 00 02 1D FF - 23 00 02 19 03 - 23 00 02 47 FF - 23 00 02 43 03 - 23 00 02 6E FF - 23 00 02 6A 03 - 23 00 02 94 FF - 23 00 02 90 03 - 23 00 02 BC FF - 23 00 02 B8 03 - 23 00 02 E2 FF - 23 00 02 DE 03 - 23 00 02 1A 35 - 23 00 02 44 35 - 23 00 02 6B 35 - 23 00 02 91 35 - 23 00 02 B9 35 - 23 00 02 DF 35 - 23 00 02 1B 45 - 23 00 02 45 45 - 23 00 02 6C 45 - 23 00 02 92 45 - 23 00 02 BA 45 - 23 00 02 E0 45 - 23 00 02 1C 55 - 23 00 02 46 55 - 23 00 02 6D 55 - 23 00 02 93 55 - 23 00 02 BB 55 - 23 00 02 E1 55 - 23 00 02 22 FF - 23 00 02 1E 68 - 23 00 02 4C FF - 23 00 02 48 68 - 23 00 02 73 FF - 23 00 02 6F 68 - 23 00 02 99 FF - 23 00 02 95 68 - 23 00 02 C1 FF - 23 00 02 BD 68 - 23 00 02 E7 FF - 23 00 02 E3 68 - 23 00 02 1F 7E - 23 00 02 49 7E - 23 00 02 70 7E - 23 00 02 96 7E - 23 00 02 BE 7E - 23 00 02 E4 7E - 23 00 02 20 97 - 23 00 02 4A 97 - 23 00 02 71 97 - 23 00 02 97 97 - 23 00 02 BF 97 - 23 00 02 E5 97 - 23 00 02 21 B5 - 23 00 02 4B B5 - 23 00 02 72 B5 - 23 00 02 98 B5 - 23 00 02 C0 B5 - 23 00 02 E6 B5 - 23 00 02 25 F0 - 23 00 02 23 E8 - 23 00 02 4F F0 - 23 00 02 4D E8 - 23 00 02 76 F0 - 23 00 02 74 E8 - 23 00 02 9C F0 - 23 00 02 9A E8 - 23 00 02 C4 F0 - 23 00 02 C2 E8 - 23 00 02 EA F0 - 23 00 02 E8 E8 - 23 00 02 24 FF - 23 00 02 4E FF - 23 00 02 75 FF - 23 00 02 9B FF - 23 00 02 C3 FF - 23 00 02 E9 FF - 23 00 02 FE 3D - 23 00 02 00 04 - 23 00 02 FE 23 - 23 00 02 08 82 - 23 00 02 0A 00 - 23 00 02 0B 00 - 23 00 02 0C 01 - 23 00 02 16 00 - 23 00 02 18 02 - 23 00 02 1B 04 - 23 00 02 19 04 - 23 00 02 1C 81 - 23 00 02 1F 00 - 23 00 02 20 03 - 23 00 02 23 04 - 23 00 02 21 01 - 23 00 02 54 63 - 23 00 02 55 54 - 23 00 02 6E 45 - 23 00 02 6D 36 - 23 00 02 FE 3D - 23 00 02 55 78 - 23 00 02 FE 20 - 23 00 02 26 30 - 23 00 02 FE 3D - 23 00 02 20 71 - 23 00 02 50 8F - 23 00 02 51 8F - 23 00 02 FE 00 - 23 00 02 35 00 - 05 78 01 11 - 05 1E 01 29 - ]; - - panel-exit-sequence = [ - 05 00 01 28 - 05 00 01 10 - ]; - - disp_timings0: display-timings { - native-mode = <&dsi0_timing0>; - dsi0_timing0: timing0 { - clock-frequency = <132000000>; - hactive = <1080>; - vactive = <1920>; - hfront-porch = <15>; - hsync-len = <4>; - hback-porch = <30>; - vfront-porch = <15>; - vsync-len = <2>; - vback-porch = <15>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - panel_in_dsi: endpoint { - remote-endpoint = <&dsi_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi>; - }; - }; - }; - -}; - -&dsi1 { - status = "disabled"; - //rockchip,lane-rate = <1000>; - dsi1_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight>; - reset-delay-ms = <60>; - enable-delay-ms = <60>; - prepare-delay-ms = <60>; - unprepare-delay-ms = <60>; - disable-delay-ms = <60>; - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | - MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - panel-init-sequence = [ - 23 00 02 FE 21 - 23 00 02 04 00 - 23 00 02 00 64 - 23 00 02 2A 00 - 23 00 02 26 64 - 23 00 02 54 00 - 23 00 02 50 64 - 23 00 02 7B 00 - 23 00 02 77 64 - 23 00 02 A2 00 - 23 00 02 9D 64 - 23 00 02 C9 00 - 23 00 02 C5 64 - 23 00 02 01 71 - 23 00 02 27 71 - 23 00 02 51 71 - 23 00 02 78 71 - 23 00 02 9E 71 - 23 00 02 C6 71 - 23 00 02 02 89 - 23 00 02 28 89 - 23 00 02 52 89 - 23 00 02 79 89 - 23 00 02 9F 89 - 23 00 02 C7 89 - 23 00 02 03 9E - 23 00 02 29 9E - 23 00 02 53 9E - 23 00 02 7A 9E - 23 00 02 A0 9E - 23 00 02 C8 9E - 23 00 02 09 00 - 23 00 02 05 B0 - 23 00 02 31 00 - 23 00 02 2B B0 - 23 00 02 5A 00 - 23 00 02 55 B0 - 23 00 02 80 00 - 23 00 02 7C B0 - 23 00 02 A7 00 - 23 00 02 A3 B0 - 23 00 02 CE 00 - 23 00 02 CA B0 - 23 00 02 06 C0 - 23 00 02 2D C0 - 23 00 02 56 C0 - 23 00 02 7D C0 - 23 00 02 A4 C0 - 23 00 02 CB C0 - 23 00 02 07 CF - 23 00 02 2F CF - 23 00 02 58 CF - 23 00 02 7E CF - 23 00 02 A5 CF - 23 00 02 CC CF - 23 00 02 08 DD - 23 00 02 30 DD - 23 00 02 59 DD - 23 00 02 7F DD - 23 00 02 A6 DD - 23 00 02 CD DD - 23 00 02 0E 15 - 23 00 02 0A E9 - 23 00 02 36 15 - 23 00 02 32 E9 - 23 00 02 5F 15 - 23 00 02 5B E9 - 23 00 02 85 15 - 23 00 02 81 E9 - 23 00 02 AD 15 - 23 00 02 A9 E9 - 23 00 02 D3 15 - 23 00 02 CF E9 - 23 00 02 0B 14 - 23 00 02 33 14 - 23 00 02 5C 14 - 23 00 02 82 14 - 23 00 02 AA 14 - 23 00 02 D0 14 - 23 00 02 0C 36 - 23 00 02 34 36 - 23 00 02 5D 36 - 23 00 02 83 36 - 23 00 02 AB 36 - 23 00 02 D1 36 - 23 00 02 0D 6B - 23 00 02 35 6B - 23 00 02 5E 6B - 23 00 02 84 6B - 23 00 02 AC 6B - 23 00 02 D2 6B - 23 00 02 13 5A - 23 00 02 0F 94 - 23 00 02 3B 5A - 23 00 02 37 94 - 23 00 02 64 5A - 23 00 02 60 94 - 23 00 02 8A 5A - 23 00 02 86 94 - 23 00 02 B2 5A - 23 00 02 AE 94 - 23 00 02 D8 5A - 23 00 02 D4 94 - 23 00 02 10 D1 - 23 00 02 38 D1 - 23 00 02 61 D1 - 23 00 02 87 D1 - 23 00 02 AF D1 - 23 00 02 D5 D1 - 23 00 02 11 04 - 23 00 02 39 04 - 23 00 02 62 04 - 23 00 02 88 04 - 23 00 02 B0 04 - 23 00 02 D6 04 - 23 00 02 12 05 - 23 00 02 3A 05 - 23 00 02 63 05 - 23 00 02 89 05 - 23 00 02 B1 05 - 23 00 02 D7 05 - 23 00 02 18 AA - 23 00 02 14 36 - 23 00 02 42 AA - 23 00 02 3D 36 - 23 00 02 69 AA - 23 00 02 65 36 - 23 00 02 8F AA - 23 00 02 8B 36 - 23 00 02 B7 AA - 23 00 02 B3 36 - 23 00 02 DD AA - 23 00 02 D9 36 - 23 00 02 15 74 - 23 00 02 3F 74 - 23 00 02 66 74 - 23 00 02 8C 74 - 23 00 02 B4 74 - 23 00 02 DA 74 - 23 00 02 16 9F - 23 00 02 40 9F - 23 00 02 67 9F - 23 00 02 8D 9F - 23 00 02 B5 9F - 23 00 02 DB 9F - 23 00 02 17 DC - 23 00 02 41 DC - 23 00 02 68 DC - 23 00 02 8E DC - 23 00 02 B6 DC - 23 00 02 DC DC - 23 00 02 1D FF - 23 00 02 19 03 - 23 00 02 47 FF - 23 00 02 43 03 - 23 00 02 6E FF - 23 00 02 6A 03 - 23 00 02 94 FF - 23 00 02 90 03 - 23 00 02 BC FF - 23 00 02 B8 03 - 23 00 02 E2 FF - 23 00 02 DE 03 - 23 00 02 1A 35 - 23 00 02 44 35 - 23 00 02 6B 35 - 23 00 02 91 35 - 23 00 02 B9 35 - 23 00 02 DF 35 - 23 00 02 1B 45 - 23 00 02 45 45 - 23 00 02 6C 45 - 23 00 02 92 45 - 23 00 02 BA 45 - 23 00 02 E0 45 - 23 00 02 1C 55 - 23 00 02 46 55 - 23 00 02 6D 55 - 23 00 02 93 55 - 23 00 02 BB 55 - 23 00 02 E1 55 - 23 00 02 22 FF - 23 00 02 1E 68 - 23 00 02 4C FF - 23 00 02 48 68 - 23 00 02 73 FF - 23 00 02 6F 68 - 23 00 02 99 FF - 23 00 02 95 68 - 23 00 02 C1 FF - 23 00 02 BD 68 - 23 00 02 E7 FF - 23 00 02 E3 68 - 23 00 02 1F 7E - 23 00 02 49 7E - 23 00 02 70 7E - 23 00 02 96 7E - 23 00 02 BE 7E - 23 00 02 E4 7E - 23 00 02 20 97 - 23 00 02 4A 97 - 23 00 02 71 97 - 23 00 02 97 97 - 23 00 02 BF 97 - 23 00 02 E5 97 - 23 00 02 21 B5 - 23 00 02 4B B5 - 23 00 02 72 B5 - 23 00 02 98 B5 - 23 00 02 C0 B5 - 23 00 02 E6 B5 - 23 00 02 25 F0 - 23 00 02 23 E8 - 23 00 02 4F F0 - 23 00 02 4D E8 - 23 00 02 76 F0 - 23 00 02 74 E8 - 23 00 02 9C F0 - 23 00 02 9A E8 - 23 00 02 C4 F0 - 23 00 02 C2 E8 - 23 00 02 EA F0 - 23 00 02 E8 E8 - 23 00 02 24 FF - 23 00 02 4E FF - 23 00 02 75 FF - 23 00 02 9B FF - 23 00 02 C3 FF - 23 00 02 E9 FF - 23 00 02 FE 3D - 23 00 02 00 04 - 23 00 02 FE 23 - 23 00 02 08 82 - 23 00 02 0A 00 - 23 00 02 0B 00 - 23 00 02 0C 01 - 23 00 02 16 00 - 23 00 02 18 02 - 23 00 02 1B 04 - 23 00 02 19 04 - 23 00 02 1C 81 - 23 00 02 1F 00 - 23 00 02 20 03 - 23 00 02 23 04 - 23 00 02 21 01 - 23 00 02 54 63 - 23 00 02 55 54 - 23 00 02 6E 45 - 23 00 02 6D 36 - 23 00 02 FE 3D - 23 00 02 55 78 - 23 00 02 FE 20 - 23 00 02 26 30 - 23 00 02 FE 3D - 23 00 02 20 71 - 23 00 02 50 8F - 23 00 02 51 8F - 23 00 02 FE 00 - 23 00 02 35 00 - 05 78 01 11 - 05 1E 01 29 - ]; - - panel-exit-sequence = [ - 05 00 01 28 - 05 00 01 10 - ]; - - disp_timings1: display-timings { - native-mode = <&dsi1_timing0>; - dsi1_timing0: timing0 { - clock-frequency = <132000000>; - hactive = <1080>; - vactive = <1920>; - hfront-porch = <15>; - hsync-len = <4>; - hback-porch = <30>; - vfront-porch = <15>; - vsync-len = <2>; - vback-porch = <15>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - panel_in_dsi1: endpoint { - remote-endpoint = <&dsi1_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi1_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi1>; - }; - }; - }; - -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - mem-supply = <&vdd_gpu_mem_s0>; - status = "okay"; -}; - -&i2s0_8ch { - status = "okay"; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; -}; - -&iep { - status = "okay"; -}; - -&iep_mmu { - status = "okay"; -}; - -&jpegd { - status = "okay"; -}; - -&jpegd_mmu { - status = "okay"; -}; - -&jpege_ccu { - status = "okay"; -}; -&jpege0 { - status = "okay"; -}; - -&jpege0_mmu { - status = "okay"; -}; - -&jpege1 { - status = "okay"; -}; - -&jpege1_mmu { - status = "okay"; -}; - -&jpege2 { - status = "okay"; -}; - -&jpege2_mmu { - status = "okay"; -}; - -&jpege3 { - status = "okay"; -}; - -&jpege3_mmu { - status = "okay"; -}; - -&mpp_srv { - status = "okay"; -}; - -&rga3_core0 { - status = "okay"; -}; - -&rga3_0_mmu { - status = "okay"; -}; - -&rga3_core1 { - status = "okay"; -}; - -&rga3_1_mmu { - status = "okay"; -}; - -&rga2 { - status = "okay"; -}; - -&rknpu { - rknpu-supply = <&vdd_npu_s0>; - mem-supply = <&vdd_npu_mem_s0>; - status = "okay"; -}; - -&rknpu_mmu { - status = "okay"; -}; - -&rkvdec_ccu { - status = "okay"; -}; -&rkvdec0 { - status = "okay"; -}; - -&rkvdec0_mmu { - status = "okay"; -}; - -&rkvdec1 { - status = "okay"; -}; - -&rkvdec1_mmu { - status = "okay"; -}; - -&rkvenc_ccu { - status = "okay"; -}; - -&rkvenc0 { - venc-supply = <&vdd_vdenc_s0>; - mem-supply = <&vdd_vdenc_mem_s0>; - status = "okay"; -}; - -&rkvenc0_mmu { - status = "okay"; -}; - -&rkvenc1 { - venc-supply = <&vdd_vdenc_s0>; - mem-supply = <&vdd_vdenc_mem_s0>; - status = "okay"; -}; - -&rkvenc1_mmu { - status = "okay"; -}; - -&rockchip_suspend { - status = "okay"; - rockchip,sleep-debug-en = <1>; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc_1v8_s0>; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - max-frequency = <200000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&sdmmc { - max-frequency = <150000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_sd_s0>; - vqmmc-supply = <&vccio_sd_s0>; - status = "disabled"; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy1 { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy0_otg { - rockchip,typec-vbus-det; - status = "okay"; -}; - -&u2phy1_otg { - status = "okay"; -}; - -&u2phy2_host { - status = "okay"; -}; - -&u2phy3_host { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdp_phy0 { - status = "okay"; -}; - -&usbdp_phy0_dp { - status = "okay"; -}; - -&usbdp_phy0_u3 { - status = "okay"; -}; - -&usbdp_phy1 { - status = "okay"; -}; - -&usbdp_phy1_dp { - status = "okay"; -}; - -&usbdp_phy1_u3 { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbhost3_0 { - status = "okay"; -}; - -&usbhost_dwc3_0 { - status = "okay"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; -}; - -&vdpu { - status = "okay"; -}; - -&vdpu_mmu { - status = "okay"; -}; - -&vepu { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -/* vp0 & vp1 splice for 8K output */ -&vp0 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; - rockchip,primary-plane = ; -}; - -&vp1 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; - rockchip,primary-plane = ; -}; - -&vp2 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; - rockchip,primary-plane = ; -}; - -&vp3 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; - rockchip,primary-plane = ; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-image-reverse.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-image-reverse.dtsi deleted file mode 100644 index 9bcce7128..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-image-reverse.dtsi +++ /dev/null @@ -1,211 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. - * - */ - -/{ - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - drm_vehicle: drm-vehicle@20000000{ - compatible = "shared-dma-pool"; - inactive; - reusable; - reg = <0x0 (512 * 0x100000) 0x0 (256 * 0x100000)>;//512M ~ 512M+256M - linux,cma-default; - }; - }; - - gpio_det: gpio-det { - compatible = "gpio-detection"; - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&vehicle_gpios>; - - car-reverse { - car-reverse-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; - linux,debounce-ms = <5>; - label = "car-reverse"; - gpio,wakeup; - }; - - }; - - vehicle: vehicle { - compatible = "rockchip,vehicle"; - status = "okay"; - - // pinctrl-names = "default"; - // pinctrl-0 = <&mipim1_camera1_clk>; - - clocks = <&cru ACLK_VICAP>, - <&cru HCLK_VICAP>, - <&cru DCLK_VICAP>; - clock-names = "aclk_cif", - "hclk_cif", - "dclk_cif"; - resets = <&cru SRST_A_VICAP>, - <&cru SRST_H_VICAP>, - <&cru SRST_D_VICAP>; - reset-names = "rst_cif_a", - "rst_cif_h", - "rst_cif_d"; - assigned-clocks = <&cru DCLK_VICAP>; - assigned-clock-rates = <600000000>; - power-domains = <&power RK3588_PD_VI>; - cif,drop-frames = <4>; //frames to drop - cif,chip-id = <1>; /*0:rk3568 1:rk3588*/ - rockchip,grf = <&sys_grf>; - rockchip,cru = <&cru>; - rockchip,cif = <&rkcif>; - rockchip,gpio-det = <&gpio_det>; - rockchip,cif-sensor = <&cif_sensor>; - rockchip,cif-phy = <&cif_phy>; - ad,fix-format = <0>;//0:auto detect,1:pal;2:ntsc;3:720p50;4:720p30;5:720p25 - /*0:no, 1:90; 2:180; 4:270; 0x10:mirror-y; 0x20:mirror-x*/ - vehicle,rotate-mirror = <0x00>; - vehicle,crtc_name = "video_port3"; - vehicle,plane_name = "Esmart3-win0"; - }; - - cif_phy: cif_phy { - status = "okay"; - - csi2_dcphy0 { - status = "disabled"; - clocks = <&cru CLK_MIPI_CAMARAOUT_M1>, - <&cru PCLK_MIPI_DCPHY0>, - <&cru PCLK_CSI_HOST_0>, - <&cru ICLK_CSIHOST0>; - clock-names = "xvclk", - "pclk", - "pclk_csi2host", - "iclk_csi2host"; - resets = <&cru SRST_P_CSI_HOST_0>, - <&cru SRST_CSIHOST0_VICAP>; - reset-names = "srst_csihost_p", - "srst_csihost_vicap"; - csihost-idx = <0>; - rockchip,csi2 = <&mipi0_csi2>; - phys = <&mipi_dcphy0>; - phy-names = "dcphy"; - }; - csi2_dcphy1 { - status = "disabled"; - clocks = <&cru CLK_MIPI_CAMARAOUT_M2>, - <&cru PCLK_MIPI_DCPHY1>, - <&cru PCLK_CSI_HOST_1>, - <&cru ICLK_CSIHOST1>; - clock-names = "xvclk", - "pclk", - "pclk_csi2host", - "iclk_csi2host"; - resets = <&cru SRST_P_CSI_HOST_1>, - <&cru SRST_CSIHOST1_VICAP>; - reset-names = "srst_csihost_p", - "srst_csihost_vicap"; - csihost-idx = <1>; - rockchip,csi2 = <&mipi1_csi2>; - phys = <&mipi_dcphy1>; - phy-names = "dcphy"; - }; - csi2_dphy0 { - status = "okay"; - clocks = <&cru CLK_MIPI_CAMARAOUT_M2>, - <&cru PCLK_CSIPHY0>, - <&cru PCLK_CSI_HOST_2>; - clock-names = "xvclk", - "pclk", - "pclk_csi2host"; - resets = <&cru SRST_CSIPHY0>, - <&cru SRST_P_CSIPHY0>, - <&cru SRST_P_CSI_HOST_2>, - <&cru SRST_CSIHOST2_VICAP>; - reset-names = "srst_csiphy", - "srst_p_csiphy", - "srst_csihost_p", - "srst_csihost_vicap"; - csihost-idx = <2>; - rockchip,dphy-grf = <&mipidphy0_grf>; - rockchip,csi2-dphy = <&csi2_dphy0_hw>; - rockchip,csi2 = <&mipi2_csi2>; - }; - /* only rk3588 */ - csi2_dphy3 { - status = "disabled"; - clocks = <&cru CLK_MIPI_CAMARAOUT_M4>, - <&cru PCLK_CSIPHY1>, - <&cru PCLK_CSI_HOST_4>; - clock-names = "xvclk", - "pclk", - "pclk_csi2host"; - resets = <&cru SRST_CSIPHY1>, - <&cru SRST_P_CSIPHY1>, - <&cru SRST_P_CSI_HOST_4>, - <&cru SRST_CSIHOST4_VICAP>; - reset-names = "srst_csiphy", - "srst_p_csiphy", - "srst_csihost_p", - "srst_csihost_vicap"; - csihost-idx = <4>; - rockchip,dphy-grf = <&mipidphy1_grf>; - rockchip,csi2-dphy = <&csi2_dphy1_hw>; - rockchip,csi2 = <&mipi4_csi2>; - }; - rkcif_dvp { - status = "disabled"; - clocks = <&cru CLK_CIFOUT_OUT>; - clock-names = "xvclk"; - }; - }; - - cif_sensor: cif_sensor { - compatible = "rockchip,sensor"; - status = "okay"; - - nvp6188 { - is_front = <0>; - status = "okay"; - - /*dphy0*/ - powerdown-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; - pwdn_active = <1>; - mir = <0>; - flash_attach = <0>; - orientation = <90>; - i2c_add = <0x66>; - i2c_chl = <7>; - cif_chl = <0>; - ad_chl = <0>; - mclk_rate = <24>; - rockchip,camera-module-defrect0 = <1920 1080 0 0 1920 1080>; - rockchip,camera-module-interface0 = "bt601_8"; - rockchip,camera-module-defrect1 = <1280 720 0 0 1280 720>; - rockchip,camera-module-interface1 = "bt601_8"; - }; - }; -}; - -&display_subsystem { - memory-region = <&drm_logo>, <&drm_vehicle>; - memory-region-names = "drm-logo", "drm-vehicle"; -}; - -&i2c7 { - status = "okay"; -}; - -&pinctrl { - vehicle { - vehicle_gpios: vehicle-gpios { - /* gpios */ - rockchip,pins = - /* car-reverse */ - <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712.dtsi deleted file mode 100644 index 4daa67699..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712.dtsi +++ /dev/null @@ -1,157 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Rockchip Electronics Co., Ltd. - * - */ - -/ { - max96712_osc: oscillator { - compatible = "fixed-clock"; - #clock-cells = <1>; - clock-frequency = <25000000>; - clock-output-names = "max96712-osc"; - }; -}; - -&csi2_dphy1_hw { - status = "okay"; -}; - -&csi2_dphy3 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_dphy1_in_max96712: endpoint@1 { - reg = <1>; - remote-endpoint = <&max96712_out>; - data-lanes = <1 2 3 4>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy1_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi4_csi2_input>; - }; - }; - }; -}; - -&i2c6 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6m3_xfer>, <&max96712_errb>, <&max96712_int>; - - max96712: max96712@29 { - compatible = "max96712"; - status = "okay"; - reg = <0x29>; - clock-names = "xvclk"; - clocks = <&max96712_osc 0>; - power-domains = <&power RK3588_PD_VI>; - rockchip,grf = <&sys_grf>; - power-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - pocen-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; - //reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - lock-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; - auto-init-deskew-mask = <0x03>; - frame-sync-period = <0>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "max96712"; - rockchip,camera-module-lens-name = "max96712"; - - port { - max96712_out: endpoint { - remote-endpoint = <&mipi_dphy1_in_max96712>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&mipi4_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi4_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy1_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi4_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi2_in>; - }; - }; - }; -}; - -&rkcif_mipi_lvds4 { - status = "okay"; - /* parameters for do cif reset detecting: - * index0: monitor mode, - 0 for idle, - 1 for continue, - 2 for trigger, - 3 for hotplug (for nextchip) - * index1: the frame id to start timer, - min is 2 - * index2: frame num of monitoring cycle - * index3: err time for keep monitoring - after finding out err (ms) - * index4: csi2 err reference val for resetting - */ - rockchip,cif-monitor = <3 2 1 1000 5>; - - port { - cif_mipi2_in: endpoint { - remote-endpoint = <&mipi4_csi2_output>; - }; - }; -}; - -&rkcif { - status = "okay"; - rockchip,android-usb-camerahal-enable; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&pinctrl { - max96712 { - max96712_errb: max96712-errb { - rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - max96712_int: max96712-int { - rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-mipi-nvp6188.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-mipi-nvp6188.dtsi deleted file mode 100644 index 39104b4f0..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-mipi-nvp6188.dtsi +++ /dev/null @@ -1,135 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. - * - */ - -&csi2_dphy0_hw { - status = "okay"; -}; - -&csi2_dphy0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_dphy0_in_nvp6188: endpoint@1 { - reg = <1>; - remote-endpoint = <&nvp6188_out>; - data-lanes = <1 2 3 4>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi2_csi2_input>; - }; - }; - }; -}; - -&i2c7 { - status = "okay"; - - - nvp6188: nvp6188@31 { - compatible = "nvp6188"; - status = "okay"; - reg = <0x31>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - pinctrl-names = "default"; - pinctrl-0 = <&mipim1_camera1_clk>; - rockchip,grf = <&sys_grf>; - /*power-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;*/ - reset-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "nvp6188"; - rockchip,camera-module-lens-name = "nvp6188"; - - port { - nvp6188_out: endpoint { - remote-endpoint = <&mipi_dphy0_in_nvp6188>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&mipi2_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy0_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi2_in>; - }; - }; - }; -}; - -&rkcif_mipi_lvds2 { - status = "okay"; - /* parameters for do cif reset detecting: - * index0: monitor mode, - 0 for idle, - 1 for continue, - 2 for trigger, - 3 for hotplug (for nextchip) - * index1: the frame id to start timer, - min is 2 - * index2: frame num of monitoring cycle - * index3: err time for keep monitoring - after finding out err (ms) - * index4: csi2 err reference val for resetting - */ - rockchip,cif-monitor = <3 2 1 1000 5>; - - port { - cif_mipi2_in: endpoint { - remote-endpoint = <&mipi2_csi2_output>; - }; - }; -}; - -&rkcif { - status = "okay"; - rockchip,android-usb-camerahal-enable; - // memory-region = <&cif_reserved>; -}; - -&rkcif_mmu { - status = "okay"; -}; - diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-thine_thcv244.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-thine_thcv244.dtsi deleted file mode 100644 index a41675d9a..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-thine_thcv244.dtsi +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. - * - */ - -&mipi_dcphy0 { - status = "okay"; -}; - -&csi2_dcphy0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_dcphy0_in: endpoint@1 { - reg = <1>; - remote-endpoint = <&thcv244_out>; - data-lanes = <1 2 3 4>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidcphy0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi0_csi2_input>; - }; - }; - }; -}; - -&i2c8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8m2_xfer>; - - thcv244: thcv244@b { - compatible = "thine,thcv244"; - status = "okay"; - reg = <0xb>; - // clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; - // clock-names = "xvclk"; - // power-domains = <&power RK3588_PD_VI>; - // pinctrl-names = "default"; - // pinctrl-0 = <&mipim0_camera1_clk>; - // rockchip,grf = <&sys_grf>; - /*power-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;*/ - // reset-gpios = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "thcv244"; - rockchip,camera-module-lens-name = "thcv244"; - - port { - thcv244_out: endpoint { - remote-endpoint = <&mipi_dcphy0_in>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&mipi0_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidcphy0_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi0_in>; - }; - }; - }; -}; - -&rkcif_mipi_lvds { - status = "okay"; - /* parameters for do cif reset detecting: - * index0: monitor mode, - 0 for idle, - 1 for continue, - 2 for trigger, - 3 for hotplug (for nextchip) - * index1: the frame id to start timer, - min is 2 - * index2: frame num of monitoring cycle - * index3: err time for keep monitoring - after finding out err (ms) - * index4: csi2 err reference val for resetting - */ - rockchip,cif-monitor = <3 2 1 1000 5>; - - port { - cif_mipi0_in: endpoint { - remote-endpoint = <&mipi0_csi2_output>; - }; - }; -}; - -&rkcif { - status = "okay"; - rockchip,android-usb-camerahal-enable; -}; - -&rkcif_mmu { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v10.dts deleted file mode 100644 index 5f35db6bb..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v10.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-vehicle-evb.dtsi" -#include "rk3588-vehicle-evb-mipi-nvp6188.dtsi" -#include "rk3588-vehicle-evb-thine_thcv244.dtsi" -#include "rk3588-vehicle-evb-image-reverse.dtsi" -#include "rk3588-vehicle-serdes-display.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588 VEHICLE EVB V10 Board"; - compatible = "rockchip,rk3588-vehicle-evb-v10", "rockchip,rk3588"; - - bt-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "dsp_a"; - simple-audio-card,bitclock-inversion = <1>; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "rockchip,bt"; - simple-audio-card,cpu { - sound-dai = <&i2s2_2ch>; - }; - - simple-audio-card,codec { - sound-dai = <&bt_sco>; - }; - }; - - bt_sco: bt-sco { - compatible = "delta,dfbmcs320"; - #sound-dai-cells = <0>; - status = "okay"; - }; -}; - -&i2s2_2ch{ - pinctrl-0 = <&i2s2m0_lrck - &i2s2m0_sclk - &i2s2m0_sdi - &i2s2m0_sdo>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dts b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dts deleted file mode 100644 index 30b3560f3..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dts +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-vehicle-evb-v20.dtsi" -#include "rk3588-vehicle-evb-mipi-nvp6188.dtsi" -#include "rk3588-vehicle-evb-image-reverse.dtsi" -#include "rk3588-vehicle-serdes-display-v20.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588 VEHICLE EVB V20 Board"; - compatible = "rockchip,rk3588-vehicle-evb-v20", "rockchip,rk3588"; - - bt-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "dsp_a"; - simple-audio-card,bitclock-inversion = <1>; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "rockchip,bt"; - simple-audio-card,cpu { - sound-dai = <&i2s2_2ch>; - }; - - simple-audio-card,codec { - sound-dai = <&bt_sco>; - }; - }; - - bt_sco: bt-sco { - compatible = "delta,dfbmcs320"; - #sound-dai-cells = <0>; - status = "okay"; - }; - - nvp6188_osc: oscillator { - compatible = "fixed-clock"; - #clock-cells = <1>; - clock-frequency = <27000000>; - clock-output-names = "nvp6188-osc"; - }; -}; - -&cif_sensor { - nvp6188 { - powerdown-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - }; -}; - -&i2c7 { - status = "okay"; - /delete-node/ nvp6188@33; - nvp6188: nvp6188@31 { - compatible = "nvp6188"; - status = "okay"; - reg = <0x31>; - clocks = <&nvp6188_osc 0>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - rockchip,grf = <&sys_grf>; - /*power-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;*/ - reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "nvp6188"; - rockchip,camera-module-lens-name = "nvp6188"; - - port { - nvp6188_out: endpoint { - remote-endpoint = <&mipi_dphy0_in_nvp6188>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&i2s2_2ch { - pinctrl-0 = <&i2s2m1_lrck - &i2s2m1_sclk - &i2s2m1_sdi - &i2s2m1_sdo>; - status = "okay"; -}; - -&rockchip_suspend { - rockchip,sleep-mode-config = < - (0 - | RKPM_SLP_ARMOFF_DDRPD - | RKPM_SLP_PMU_PMUALIVE_32K - | RKPM_SLP_PMU_DIS_OSC - | RKPM_SLP_32K_EXT - ) - >; - rockchip,wakeup-config = < - (0 - | RKPM_GPIO_WKUP_EN - ) - >; - status = "okay"; -}; - -&vdd_log_s0 { - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <800000>; - }; -}; - -&vcc_3v3_s0 { - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; -}; - -&vcc_1v8_s0 { - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dtsi deleted file mode 100644 index e4e050ba5..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v20.dtsi +++ /dev/null @@ -1,383 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Rockchip Electronics Co., Ltd. - * - */ - -#include "dt-bindings/usb/pd.h" -#include "rk3588m.dtsi" -#include "rk3588-vehicle-v20.dtsi" -#include "rk3588-rk806-dual.dtsi" -/ { - pcie20_avdd0v85: pcie20-avdd0v85 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd0v85"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&vdd_0v85_s0>; - }; - - pcie20_avdd1v8: pcie20-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - pcie30_avdd0v75: pcie30-avdd0v75 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v75"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - vin-supply = <&avdd_0v75_s0>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - post-power-on-delay-ms = <10>; - reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - pwms = <&pwm8 0 50000 0>; - cooling-levels = <0 50 100 150 200 255>; - rockchip,temp-trips = < - 50000 1 - 55000 2 - 60000 3 - 65000 4 - 70000 5 - >; - }; - - vcc5v0_host: vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - }; - - wireless_bluetooth: wireless-bluetooth { - compatible = "bluetooth-platdata"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - uart_rts_gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "rts_gpio"; - pinctrl-0 = <&uart9m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; - pinctrl-1 = <&uart9_gpios>; - BT,reset_gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; - BT,wake_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; - BT,wake_host_irq = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - wifi_chip_type = "ap6398s"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_irq>; - WIFI,host_wake_irq = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - WIFI,poweren_gpio = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - dummy_codec: dummy-codec { - status = "okay"; - compatible = "rockchip,dummy-codec"; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&rk3308_reset>; - }; - - car_rk3308_sound: car-rk3308-sound { - status = "okay"; - compatible = "simple-audio-card"; - simple-audio-card,name = "rockchip,car-rk3308-sound"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,bitclock-master = <&codec_master>; - simple-audio-card,frame-master = <&codec_master>; - simple-audio-card,cpu { - sound-dai = <&i2s0_8ch>; - }; - codec_master: simple-audio-card,codec { - sound-dai = <&dummy_codec>; - }; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&gmac0 { - /* Use rgmii-rxid mode to disable rx delay inside Soc */ - phy-mode = "rgmii-rxid"; - clock_in_out = "output"; - snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - pinctrl-names = "phydisb"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus - &phydisb>; - tx_delay = <0x43>; - //rx_delay = <0x3f>; - phy-handle = <&rgmii_phy>; - status = "okay"; -}; - -&i2c4 { - status = "okay"; - pinctrl-0 = <&i2c4m2_xfer>; - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; - -}; - -&i2s0_8ch { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdi1 - &i2s0_sdo0 - &i2s0_sdo1 - &i2s0_sdo2 - &i2s0_sdo3>; -}; - -&mdio0 { - rgmii_phy: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - }; -}; - -&pcie2x1l0 { - reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - rockchip,skip-scan-in-resume; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - status = "disabled"; -}; - -&pcie2x1l2 { - reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - status = "disabled"; -}; - -&pinctrl { - gmac0 { - phydisb: phydisb { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - - wireless-bluetooth { - uart9_gpios: uart9-gpios { - rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reset_gpio: bt-reset-gpio { - rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_gpio: bt-wake-gpio { - rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_irq_gpio: bt-irq-gpio { - rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - rk3308 { - rk3308_reset: rk3308-reset { - rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm0 { - pinctrl-0 = <&pwm0m2_pins>; - status = "okay"; -}; - -&pwm1 { - pinctrl-0 = <&pwm1m2_pins>; - status = "okay"; -}; - -&pwm8 { - pinctrl-0 = <&pwm8m1_pins>; - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -&sdio { - max-frequency = <150000000>; - no-sd; - no-mmc; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdiom1_pins>; - status = "okay"; -}; - -&sdmmc { - status = "disabled"; -}; - -&uart9 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart9m1_xfer &uart9m1_ctsn>; -}; - -&u2phy1_otg { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; -}; - -&usbdp_phy0 { - rockchip,dp-lane-mux = <2 3>; - status = "okay"; -}; - -&usbdp_phy0_dp { - status = "okay"; -}; - -&usbdp_phy0_u3 { - status = "okay"; -}; - -&usbdp_phy1 { - rockchip,dp-lane-mux = <3 2 1 0>; - status = "okay"; -}; - -&usbdp_phy1_dp { - status = "okay"; -}; - -&usbdp_phy1_u3 { - maximum-speed = "high-speed"; - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "peripheral"; - maximum-speed = "high-speed"; - extcon = <&u2phy0>; - status = "okay"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; - maximum-speed = "high-speed"; - snps,dis_u2_susphy_quirk; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dts b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dts deleted file mode 100644 index ae86128d0..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dts +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588-vehicle-evb-v21.dtsi" -#include "rk3588-vehicle-evb-maxim-max96712.dtsi" -#include "rk3588-vehicle-serdes-display-v21.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588 VEHICLE EVB V21 Board"; - compatible = "rockchip,rk3588-vehicle-evb-v21", "rockchip,rk3588"; - - bt-sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "dsp_a"; - simple-audio-card,bitclock-inversion = <1>; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "rockchip,bt"; - simple-audio-card,cpu { - sound-dai = <&i2s2_2ch>; - }; - - simple-audio-card,codec { - sound-dai = <&bt_sco>; - }; - }; - - bt_sco: bt-sco { - compatible = "delta,dfbmcs320"; - #sound-dai-cells = <0>; - status = "okay"; - }; - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - reverse { - label = "GPIO Key Reverse"; - linux,code = ; - gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - - park { - label = "GPIO Key Park"; - linux,code = ; - gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - debounce-interval = <100>; - }; - }; -}; - -&i2s2_2ch { - pinctrl-0 = <&i2s2m1_lrck - &i2s2m1_sclk - &i2s2m1_sdi - &i2s2m1_sdo>; - status = "okay"; -}; - -&rockchip_suspend { - rockchip,sleep-mode-config = < - (0 - | RKPM_SLP_ARMOFF_DDRPD - | RKPM_SLP_PMU_PMUALIVE_32K - | RKPM_SLP_PMU_DIS_OSC - | RKPM_SLP_32K_EXT - ) - >; - rockchip,wakeup-config = < - (0 - | RKPM_CPU0_WKUP_EN - | RKPM_GPIO_WKUP_EN - ) - >; - status = "okay"; -}; - -&vdd_log_s0 { - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <800000>; - }; -}; - -&vcc_3v3_s0 { - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; -}; - -&vcc_1v8_s0 { - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; -}; - -&vdd_1v8_pll_s0 { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dtsi deleted file mode 100644 index 60bb056ee..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dtsi +++ /dev/null @@ -1,398 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Rockchip Electronics Co., Ltd. - * - */ - -#include "dt-bindings/usb/pd.h" -#include "rk3588m.dtsi" -#include "rk3588-vehicle-v20.dtsi" -#include "rk3588-rk806-dual.dtsi" -/ { - pcie20_avdd0v85: pcie20-avdd0v85 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd0v85"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&vdd_0v85_s0>; - }; - - pcie20_avdd1v8: pcie20-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - pcie30_avdd0v75: pcie30-avdd0v75 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v75"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - vin-supply = <&avdd_0v75_s0>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - vcc3v3_pcie_wifi: vcc3v3-pcie-wifi { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie_wifi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - //gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - vin-supply = <&vcc_3v3_s0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - post-power-on-delay-ms = <10>; - reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>; - status = "disabled"; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - pwms = <&pwm8 0 50000 0>; - cooling-levels = <0 50 100 150 200 255>; - rockchip,temp-trips = < - 50000 1 - 55000 2 - 60000 3 - 65000 4 - 70000 5 - >; - }; - - vcc5v0_host: vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - }; - - wireless_bluetooth: wireless-bluetooth { - compatible = "bluetooth-platdata"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - uart_rts_gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "rts_gpio"; - pinctrl-0 = <&uart9m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; - pinctrl-1 = <&uart9_gpios>; - BT,reset_gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; - BT,wake_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; - BT,wake_host_irq = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - wifi_chip_type = "ap6398s"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_poweren_gpio>, <&wifi_host_wake_irq>; - WIFI,host_wake_irq = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - WIFI,poweren_gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - dummy_codec: dummy-codec { - status = "okay"; - compatible = "rockchip,dummy-codec"; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&rk3308_reset>; - }; - - car_rk3308_sound: car-rk3308-sound { - status = "okay"; - compatible = "simple-audio-card"; - simple-audio-card,name = "rockchip,car-rk3308-sound"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,bitclock-master = <&codec_master>; - simple-audio-card,frame-master = <&codec_master>; - simple-audio-card,cpu { - sound-dai = <&i2s0_8ch>; - }; - codec_master: simple-audio-card,codec { - sound-dai = <&dummy_codec>; - }; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&gmac0 { - /* Use rgmii-rxid mode to disable rx delay inside Soc */ - phy-mode = "rgmii-rxid"; - clock_in_out = "output"; - snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - pinctrl-names = "phydisb"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus - &phydisb>; - tx_delay = <0x43>; - //rx_delay = <0x3f>; - phy-handle = <&rgmii_phy>; - status = "okay"; -}; - -&i2c4 { - status = "okay"; - pinctrl-0 = <&i2c4m2_xfer>; - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; - -}; - -&i2s0_8ch { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdi1 - &i2s0_sdo0 - &i2s0_sdo1 - &i2s0_sdo2 - &i2s0_sdo3>; -}; - -&mdio0 { - rgmii_phy: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - }; -}; - -&pcie2x1l0 { - reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - rockchip,perst-inactive-ms = <500>; - rockchip,skip-scan-in-resume; - vpcie3v3-supply = <&vcc3v3_pcie_wifi>; - status = "okay"; -}; - -&pcie2x1l2 { - reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - status = "disabled"; -}; - -&pinctrl { - gmac0 { - phydisb: phydisb { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_output_high>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - - wireless-bluetooth { - uart9_gpios: uart9-gpios { - rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reset_gpio: bt-reset-gpio { - rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_gpio: bt-wake-gpio { - rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_irq_gpio: bt-irq-gpio { - rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - wifi_poweren_gpio: wifi-power-gpio { - rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - rk3308 { - rk3308_reset: rk3308-reset { - rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm0 { - pinctrl-0 = <&pwm0m2_pins>; - status = "okay"; -}; - -&pwm1 { - pinctrl-0 = <&pwm1m2_pins>; - status = "okay"; -}; - -&pwm8 { - pinctrl-0 = <&pwm8m1_pins>; - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -&sdio { - max-frequency = <150000000>; - no-sd; - no-mmc; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdiom1_pins>; - status = "disabled"; -}; - -&sdmmc { - status = "disabled"; -}; - -&uart9 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart9m1_xfer &uart9m1_ctsn>; -}; - -&u2phy1_otg { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; -}; - -&usbdp_phy0 { - rockchip,dp-lane-mux = <2 3>; - status = "okay"; -}; - -&usbdp_phy0_dp { - status = "okay"; -}; - -&usbdp_phy0_u3 { - status = "okay"; -}; - -&usbdp_phy1 { - rockchip,dp-lane-mux = <3 2 1 0>; - status = "okay"; -}; - -&usbdp_phy1_dp { - status = "okay"; -}; - -&usbdp_phy1_u3 { - maximum-speed = "high-speed"; - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "peripheral"; - maximum-speed = "high-speed"; - extcon = <&u2phy0>; - status = "okay"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; - maximum-speed = "high-speed"; - snps,dis_u2_susphy_quirk; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb.dtsi deleted file mode 100644 index c63b5536c..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb.dtsi +++ /dev/null @@ -1,672 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include "dt-bindings/usb/pd.h" -#include "rk3588m.dtsi" -#include "rk3588-vehicle.dtsi" -#include "rk3588-rk806-single.dtsi" - -/ { - es8388_sound: es8388-sound { - status = "disabled"; - compatible = "rockchip,multicodecs-card"; - rockchip,card-name = "rockchip-es8388"; - hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; - io-channels = <&saradc 3>; - io-channel-names = "adc-detect"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - spk-con-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - hp-con-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - rockchip,format = "i2s"; - rockchip,mclk-fs = <256>; - rockchip,cpu = <&i2s0_8ch>; - rockchip,codec = <&es8388>; - rockchip,audio-routing = - "Headphone", "LOUT1", - "Headphone", "ROUT1", - "Speaker", "LOUT2", - "Speaker", "ROUT2", - "Headphone", "Headphone Power", - "Headphone", "Headphone Power", - "Speaker", "Speaker Power", - "Speaker", "Speaker Power", - "LINPUT1", "Main Mic", - "LINPUT2", "Main Mic", - "RINPUT1", "Headset Mic", - "RINPUT2", "Headset Mic"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - play-pause-key { - label = "playpause"; - linux,code = ; - press-threshold-microvolt = <2000>; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - pwms = <&pwm3 0 50000 0>; - cooling-levels = <0 50 100 150 200 255>; - rockchip,temp-trips = < - 50000 1 - 55000 2 - 60000 3 - 65000 4 - 70000 5 - >; - }; - - - pcie20_avdd0v85: pcie20-avdd0v85 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd0v85"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&vdd_0v85_s0>; - }; - - pcie20_avdd1v8: pcie20-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - pcie30_avdd0v75: pcie30-avdd0v75 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v75"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - vin-supply = <&avdd_0v75_s0>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - post-power-on-delay-ms = <200>; - reset-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>; - status = "disabled"; - }; - - rk_headset: rk-headset { - status = "disabled"; - compatible = "rockchip_headset"; - headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - io-channels = <&saradc 3>; - }; - - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_lcd_n: vcc3v3-lcd0-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd0_n"; - regulator-boot-on; - enable-active-high; - gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc_1v8_s0>; - }; - - vcc5v0_otg: vcc5v0-otg { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_otg"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_otg_en>; - }; - - vcc5v0_host: vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - }; - - wireless_bluetooth: wireless-bluetooth { - compatible = "bluetooth-platdata"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "rts_gpio"; - pinctrl-0 = <&uart9m0_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; - pinctrl-1 = <&uart9_gpios>; - BT,reset_gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; - BT,wake_gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; - BT,wake_host_irq = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - wifi_chip_type = "ap6398s"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_irq>; - WIFI,host_wake_irq = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; - WIFI,poweren_gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - dummy_codec: dummy-codec { - status = "okay"; - compatible = "rockchip,dummy-codec"; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&rk3308_reset>; - }; - - car_rk3308_sound: car-rk3308-sound { - status = "okay"; - compatible = "simple-audio-card"; - simple-audio-card,name = "rockchip,car-rk3308-sound"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,bitclock-master = <&codec_master>; - simple-audio-card,frame-master = <&codec_master>; - simple-audio-card,cpu { - sound-dai = <&i2s0_8ch>; - }; - codec_master: simple-audio-card,codec { - sound-dai = <&dummy_codec>; - }; - }; -}; - -&backlight { - pwms = <&pwm1 0 25000 0>; - status = "okay"; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy1_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&gmac1 { - /* Use rgmii-rxid mode to disable rx delay inside Soc */ - phy-mode = "rgmii-rxid"; - clock_in_out = "output"; - - snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac1_miim - &gmac1_tx_bus2 - &gmac1_rx_bus2 - &gmac1_rgmii_clk - &gmac1_rgmii_bus>; - - tx_delay = <0x43>; - /* rx_delay = <0x3f>; */ - - phy-handle = <&rgmii_phy>; - status = "disabled"; -}; - -&hdmi0 { - enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi0_in_vp0 { - status = "okay"; -}; - -&hdmi0_sound { - status = "okay"; -}; - -&hdmi1 { - enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi1_in_vp0 { - status = "okay"; -}; - -&hdmi1_sound { - status = "okay"; -}; - - -&hdptxphy_hdmi0 { - status = "okay"; -}; - -&hdptxphy_hdmi1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - - vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big0_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { - compatible = "rockchip,rk8603"; - reg = <0x43>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big1_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1m2_xfer>; - - vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_npu_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c4 { - status = "okay"; - pinctrl-0 = <&i2c4m2_xfer>; - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; - -}; - -&i2c5 { - status = "okay"; - -}; - -&i2c6 { - status = "okay"; - -}; - -&i2c7 { - status = "okay"; - es8388: es8388@11 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "everest,es8388", "everest,es8323"; - reg = <0x11>; - clocks = <&mclkout_i2s0>; - clock-names = "mclk"; - assigned-clocks = <&mclkout_i2s0>; - assigned-clock-rates = <12288000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk>; - }; -}; - -&i2s0_8ch { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdi1 - &i2s0_sdo0 - &i2s0_sdo1 - &i2s0_sdo2 - &i2s0_sdo3>; -}; - -&i2s5_8ch { - status = "okay"; -}; - -&i2s6_8ch { - status = "okay"; -}; - -&i2s7_8ch { - status = "okay"; -}; - -&mdio1 { - rgmii_phy: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - }; -}; - -&pcie2x1l0 { - reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - status = "disabled"; -}; - -&pcie2x1l2 { - reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; - rockchip,skip-scan-in-resume; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - status = "okay"; -}; - -&pcie30phy { - rockchip,pcie30-phymode = ; - status = "disabled"; -}; - -&pcie3x4 { - reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; - status = "disabled"; -}; - -&pinctrl { - cam { - mipicsi0_pwr: mipicsi0-pwr { - rockchip,pins = - /* camera power en */ - <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - mipicsi1_pwr: mipicsi1-pwr { - rockchip,pins = - /* camera power en */ - <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - mipidcphy0_pwr: mipidcphy0-pwr { - rockchip,pins = - /* camera power en */ - <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - headphone { - hp_det: hp-det { - rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lcd { - lcd_rst_gpio: lcd-rst-gpio { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - touch { - touch_gpio: touch-gpio { - rockchip,pins = - <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>, - <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_otg_en: vcc5v0-otg-en { - rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - - wireless-bluetooth { - uart9_gpios: uart9-gpios { - rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reset_gpio: bt-reset-gpio { - rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_gpio: bt-wake-gpio { - rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_irq_gpio: bt-irq-gpio { - rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - rk3308 { - rk3308_reset: rk3308-reset { - rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm3 { - pinctrl-0 = <&pwm3m1_pins>; - status = "okay"; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp3_out_dsi0>; -}; - -&route_dsi1 { - status = "disabled"; - connect = <&vp3_out_dsi1>; -}; - -&route_hdmi0 { - status = "okay"; -}; - -&route_hdmi1 { - status = "okay"; -}; - -&sata0 { - status = "okay"; -}; - -&sdio { - max-frequency = <150000000>; - no-sd; - no-mmc; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdiom0_pins>; - sd-uhs-sdr104; - status = "disabled"; -}; - -&sdmmc { - status = "disabled"; -}; - -&uart9 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&u2phy1_otg { - phy-supply = <&vcc5v0_otg>; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_otg>; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; -}; - -&usbdp_phy0 { - rockchip,dp-lane-mux = <2 3>; - status = "okay"; -}; - -&usbdp_phy0_dp { - status = "okay"; -}; - -&usbdp_phy0_u3 { - status = "okay"; -}; - -&usbdp_phy1 { - rockchip,dp-lane-mux = <3 2 1 0>; - status = "okay"; -}; - -&usbdp_phy1_dp { - status = "okay"; -}; - -&usbdp_phy1_u3 { - maximum-speed = "high-speed"; - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "peripheral"; - maximum-speed = "high-speed"; - extcon = <&u2phy0>; - status = "okay"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; - maximum-speed = "high-speed"; - snps,dis_u2_susphy_quirk; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-maxim-serdes.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-maxim-serdes.dtsi deleted file mode 100644 index 8b05614e3..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-maxim-serdes.dtsi +++ /dev/null @@ -1,864 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. - */ - -#include - -/ { - aliases { - pinctrl0 = &pinctrl; - }; - - backlight { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - i2c2_max96755f_backlight: backlight@0 { - compatible = "pwm-backlight"; - reg = <0>; - pwms = <&pwm6 0 1000000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - i2c3_max96745_backlight: backlight@1 { - compatible = "pwm-backlight"; - reg = <1>; - pwms = <&pwm10 0 1000000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - i2c5_max96745_backlight: backlight@2 { - compatible = "pwm-backlight"; - reg = <2>; - pwms = <&pwm12 0 1000000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - i2c6_max96755f_backlight: backlight@3 { - compatible = "pwm-backlight"; - reg = <3>; - pwms = <&pwm13 0 1000000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - i2c7_max96745_backlight: backlight@4 { - compatible = "pwm-backlight"; - reg = <4>; - pwms = <&pwm11 0 1000000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - - i2c8_max96745_backlight: backlight@5 { - compatible = "pwm-backlight"; - reg = <5>; - pwms = <&pwm14 0 1000000 0>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - }; -}; - -&dp0 { - split-mode; - force-hpd; - status = "okay"; -}; - -&dp0_in_vp0 { - status = "okay"; -}; - -&dp0_out { - link-frequencies = /bits/ 64 <2700000000>; - remote-endpoint = <&i2c3_max96745_in>; -}; - -&usbdp_phy0 { - rockchip,dp-lane-mux = <0 1 2 3>; - status = "okay"; -}; - -&usbdp_phy0_dp { - status = "okay"; -}; - -&route_dp0 { - connect = <&vp0_out_dp0>; - status = "okay"; -}; - -&dp1 { - force-hpd; - status = "okay"; -}; - -&dp1_out { - link-frequencies = /bits/ 64 <2700000000>; - remote-endpoint = <&i2c8_max96745_in>; -}; - -&usbdp_phy1 { - rockchip,dp-lane-mux = <0 1 2 3>; - status = "okay"; -}; - -&usbdp_phy1_dp { - status = "okay"; -}; - -&dsi0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - dsi0_out: endpoint { - remote-endpoint = <&i2c2_max96755f_in>; - }; - }; - }; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&dsi0_in_vp2 { - status = "okay"; -}; - -&route_dsi0 { - connect = <&vp2_out_dsi0>; - status = "okay"; -}; - -&dsi1 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - dsi1_out: endpoint { - remote-endpoint = <&i2c6_max96755f_in>; - }; - }; - }; -}; - -&mipi_dcphy1 { - status = "okay"; -}; - -&dsi1_in_vp3 { - status = "okay"; -}; - -&route_dsi1 { - connect = <&vp3_out_dsi1>; - status = "okay"; -}; - -&edp0 { - split-mode; - force-hpd; - status = "okay"; -}; - -&edp0_out { - link-frequencies = /bits/ 64 <2700000000>; - remote-endpoint = <&i2c5_max96745_in>; -}; - -&hdptxphy0 { - status = "okay"; -}; - -&edp0_in_vp1 { - status = "okay"; -}; - -&route_edp0 { - connect = <&vp1_out_edp0>; - status = "okay"; -}; - -&edp1 { - force-hpd; - status = "okay"; -}; - -&edp1_out { - link-frequencies = /bits/ 64 <2700000000>; - remote-endpoint = <&i2c7_max96745_in>; -}; - -&hdptxphy1 { - status = "okay"; -}; - -&i2c2 { - pinctrl-0 = <&i2c2m4_xfer>; - clock-frequency = <400000>; - status = "okay"; - - max96755f@40 { - compatible = "maxim,max96755f"; - reg = <0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_serdes_pins>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl { - compatible = "maxim,max96755f-pinctrl"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_max96755f_pinctrl_hog>; - - i2c2_max96755f_pinctrl_hog: hog { - i2c { - groups = "I2C"; - function = "I2C"; - }; - }; - - i2c2_max96755f_panel_pins: panel-pins { - bl-pwm { - pins = "MFP18"; - function = "GPIO_TX_0"; - }; - }; - }; - - bridge { - compatible = "maxim,max96755f-bridge"; - lock-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c2_max96755f_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - - i2c2_max96755f_out: endpoint { - remote-endpoint = <&i2c2_max96755f_panel_in>; - }; - }; - }; - }; - - gmsl@0 { - reg = <0>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - - panel@48 { - compatible = "boe,av156fht-l83"; - reg = <0x48>; - backlight = <&i2c2_max96755f_backlight>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_max96755f_panel_pins>; - - panel-timing { - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <20>; - hsync-len = <20>; - hback-porch = <20>; - vfront-porch = <250>; - vsync-len = <2>; - vback-porch = <8>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - i2c2_max96755f_panel_in: endpoint { - remote-endpoint = <&i2c2_max96755f_out>; - }; - }; - }; - }; - }; -}; - -&i2c3 { - pinctrl-0 = <&i2c3m2_xfer>; - clock-frequency = <400000>; - status = "okay"; - - max96745@42 { - compatible = "maxim,max96745"; - reg = <0x42>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_serdes_pins>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl { - compatible = "maxim,max96745-pinctrl"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_max96745_pinctrl_hog>; - - i2c3_max96745_pinctrl_hog: hog { - i2c { - groups = "I2C"; - function = "I2C"; - }; - }; - - i2c3_max96745_panel_pins: panel-pins { - bl-pwm { - pins = "MFP0"; - function = "GPIO_TX_A_0"; - }; - }; - }; - - bridge { - compatible = "maxim,max96745-bridge"; - lock-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c3_max96745_in: endpoint { - remote-endpoint = <&dp0_out>; - }; - }; - - port@1 { - reg = <1>; - - i2c3_max96745_out: endpoint { - remote-endpoint = <&i2c3_max96745_panel_in>; - }; - }; - }; - }; - - gmsl@0 { - reg = <0>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - - panel@48 { - compatible = "boe,av156fht-l83"; - reg = <0x48>; - backlight = <&i2c3_max96745_backlight>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_max96745_panel_pins>; - - panel-timing { - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <20>; - hsync-len = <20>; - hback-porch = <20>; - vfront-porch = <250>; - vsync-len = <2>; - vback-porch = <8>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - i2c3_max96745_panel_in: endpoint { - remote-endpoint = <&i2c3_max96745_out>; - }; - }; - }; - }; - }; -}; - -&i2c5 { - clock-frequency = <400000>; - status = "okay"; - - max96745@42 { - compatible = "maxim,max96745"; - reg = <0x42>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_serdes_pins>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl { - compatible = "maxim,max96745-pinctrl"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_max96745_pinctrl_hog>; - - i2c5_max96745_pinctrl_hog: hog { - i2c { - groups = "I2C"; - function = "I2C"; - }; - }; - - i2c5_max96745_panel_pins: panel-pins { - bl-pwm { - pins = "MFP0"; - function = "GPIO_TX_A_0"; - }; - }; - }; - - bridge { - compatible = "maxim,max96745-bridge"; - lock-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c5_max96745_in: endpoint { - remote-endpoint = <&edp0_out>; - }; - }; - - port@1 { - reg = <1>; - - i2c5_max96745_out: endpoint { - remote-endpoint = <&i2c5_max96745_panel_in>; - }; - }; - }; - }; - - gmsl@0 { - reg = <0>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - - panel@48 { - compatible = "boe,av156fht-l83"; - reg = <0x48>; - backlight = <&i2c5_max96745_backlight>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_max96745_panel_pins>; - - panel-timing { - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <20>; - hsync-len = <20>; - hback-porch = <20>; - vfront-porch = <250>; - vsync-len = <2>; - vback-porch = <8>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - i2c5_max96745_panel_in: endpoint { - remote-endpoint = <&i2c5_max96745_out>; - }; - }; - }; - }; - }; -}; - -&i2c6 { - pinctrl-0 = <&i2c6m3_xfer>; - clock-frequency = <400000>; - status = "okay"; - - max96755f@40 { - compatible = "maxim,max96755f"; - reg = <0x40>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_serdes_pins>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl { - compatible = "maxim,max96755f-pinctrl"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_max96755f_pinctrl_hog>; - - i2c6_max96755f_pinctrl_hog: hog { - i2c { - groups = "I2C"; - function = "I2C"; - }; - }; - - - i2c6_max96755f_panel_pins: panel-pins { - bl-pwm { - pins = "MFP18"; - function = "GPIO_TX_0"; - }; - }; - }; - - bridge { - compatible = "maxim,max96755f-bridge"; - lock-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c6_max96755f_in: endpoint { - remote-endpoint = <&dsi1_out>; - }; - }; - - port@1 { - reg = <1>; - - i2c6_max96755f_out: endpoint { - remote-endpoint = <&i2c6_max96755f_panel_in>; - }; - }; - }; - }; - - gmsl@0 { - reg = <0>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - - panel@48 { - compatible = "boe,av156fht-l83"; - reg = <0x48>; - backlight = <&i2c6_max96755f_backlight>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_max96755f_panel_pins>; - - panel-timing { - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <20>; - hsync-len = <20>; - hback-porch = <20>; - vfront-porch = <250>; - vsync-len = <2>; - vback-porch = <8>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - i2c6_max96755f_panel_in: endpoint { - remote-endpoint = <&i2c6_max96755f_out>; - }; - }; - }; - }; - }; -}; - -&i2c7 { - pinctrl-0 = <&i2c7m3_xfer>; - clock-frequency = <400000>; - status = "okay"; - - max96745@42 { - compatible = "maxim,max96745"; - reg = <0x42>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_serdes_pins>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl { - compatible = "maxim,max96745-pinctrl"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_max96745_pinctrl_hog>; - - i2c7_max96745_pinctrl_hog: hog { - i2c { - groups = "I2C"; - function = "I2C"; - }; - }; - - i2c7_max96745_panel_pins: panel-pins { - bl-pwm { - pins = "MFP0"; - function = "GPIO_TX_A_0"; - }; - }; - }; - - bridge { - compatible = "maxim,max96745-bridge"; - lock-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c7_max96745_in: endpoint { - remote-endpoint = <&edp1_out>; - }; - }; - - port@1 { - reg = <1>; - - i2c7_max96745_out: endpoint { - remote-endpoint = <&i2c7_max96745_panel_in>; - }; - }; - }; - }; - - gmsl@0 { - reg = <0>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - - panel@48 { - compatible = "boe,av156fht-l83"; - reg = <0x48>; - backlight = <&i2c7_max96745_backlight>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_max96745_panel_pins>; - - panel-timing { - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <20>; - hsync-len = <20>; - hback-porch = <20>; - vfront-porch = <250>; - vsync-len = <2>; - vback-porch = <8>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - i2c7_max96745_panel_in: endpoint { - remote-endpoint = <&i2c7_max96745_out>; - }; - }; - }; - }; - }; -}; - -&i2c8 { - pinctrl-0 = <&i2c8m2_xfer>; - clock-frequency = <400000>; - status = "okay"; - - max96745@42 { - compatible = "maxim,max96745"; - reg = <0x42>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8_serdes_pins>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl { - compatible = "maxim,max96745-pinctrl"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8_max96745_pinctrl_hog>; - - i2c8_max96745_pinctrl_hog: hog { - i2c { - groups = "I2C"; - function = "I2C"; - }; - }; - - i2c8_max96745_panel_pins: panel-pins { - bl-pwm { - pins = "MFP0"; - function = "GPIO_TX_A_0"; - }; - }; - }; - - bridge { - compatible = "maxim,max96745-bridge"; - lock-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c8_max96745_in: endpoint { - remote-endpoint = <&dp1_out>; - }; - }; - - port@1 { - reg = <1>; - - i2c8_max96745_out: endpoint { - remote-endpoint = <&i2c8_max96745_panel_in>; - }; - }; - }; - }; - - gmsl@0 { - reg = <0>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - - panel@48 { - compatible = "boe,av156fht-l83"; - reg = <0x48>; - backlight = <&i2c8_max96745_backlight>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8_max96745_panel_pins>; - - panel-timing { - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <20>; - hsync-len = <20>; - hback-porch = <20>; - vfront-porch = <250>; - vsync-len = <2>; - vback-porch = <8>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - i2c8_max96745_panel_in: endpoint { - remote-endpoint = <&i2c8_max96745_out>; - }; - }; - }; - }; - }; -}; - -&pinctrl { - serdes { - i2c2_serdes_pins: i2c2-serdes-pins { - rockchip,pins = - <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - i2c3_serdes_pins: i2c3-serdes-pins { - rockchip,pins = - <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - i2c5_serdes_pins: i2c5-serdes-pins { - rockchip,pins = - <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - i2c6_serdes_pins: i2c6-serdes-pins { - rockchip,pins = - <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - i2c7_serdes_pins: i2c7-serdes-pins { - rockchip,pins = - <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - i2c8_serdes_pins: i2c8-serdes-pins { - rockchip,pins = - <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm6 { - pinctrl-0 = <&pwm6m1_pins>; - status = "okay"; -}; - -&pwm10 { - pinctrl-0 = <&pwm10m2_pins>; - status = "okay"; -}; - -&pwm11 { - pinctrl-0 = <&pwm11m3_pins>; - status = "okay"; -}; - -&pwm12 { - pinctrl-0 = <&pwm12m1_pins>; - status = "okay"; -}; - -&pwm13 { - pinctrl-0 = <&pwm13m1_pins>; - status = "okay"; -}; - -&pwm14 { - pinctrl-0 = <&pwm14m0_pins>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v20.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v20.dtsi deleted file mode 100644 index b458efd4a..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v20.dtsi +++ /dev/null @@ -1,1943 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Rockchip Electronics Co., Ltd. - * - */ - -/ { - lt7911d { - compatible = "lontium,lt7911d-fb-notifier"; - reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_LOW>, - <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>, - <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>, - <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; - }; - - dsi2lvds_backlight1: dsi2lvds_backlight1 { - compatible = "pwm-backlight"; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - dp2lvds_backlight0: dp2lvds_backlight0 { - compatible = "pwm-backlight"; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - dp2lvds_backlight1: dp2lvds_backlight1 { - compatible = "pwm-backlight"; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - edp2lvds_backlight0: edp2lvds_backlight0 { - compatible = "pwm-backlight"; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - edp2lvds_backlight1: edp2lvds_backlight1 { - compatible = "pwm-backlight"; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - dsi2lvds_panel0 { - compatible = "simple-panel"; - backlight = <&backlight>; - - display-timings { - native-mode = <&dsi2lvds0>; - dsi2lvds0: timing0 { - clock-frequency = <88208000>; - hactive = <1920>; - vactive = <720>; - hfront-porch = <32>; - hsync-len = <10>; - hback-porch = <22>; - vfront-porch = <10>; - vsync-len = <4>; - vback-porch = <7>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - panel0_in_i2c2_bu18rl82: endpoint { - remote-endpoint = <&i2c2_bu18rl82_out_panel0>; - }; - }; - }; - }; - - dsi2lvds_panel1 { - compatible = "simple-panel"; - backlight = <&dsi2lvds_backlight1>; - - display-timings { - native-mode = <&dsi2lvds1>; - dsi2lvds1: timing0 { - clock-frequency = <88208000>; - hactive = <1920>; - vactive = <720>; - hfront-porch = <32>; - hsync-len = <10>; - hback-porch = <22>; - vfront-porch = <10>; - vsync-len = <4>; - vback-porch = <7>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - panel1_in_i2c6_bu18rl82: endpoint { - remote-endpoint = <&i2c6_bu18rl82_out_panel1>; - }; - }; - }; - }; - - dp2lvds_panel0 { - compatible = "simple-panel"; - backlight = <&dp2lvds_backlight0>; - status = "okay"; - - panel-timing { - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <140>; - hsync-len = <40>; - hback-porch = <100>; - vfront-porch = <15>; - vsync-len = <20>; - vback-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - panel0_in_i2c4_bu18rl82: endpoint { - remote-endpoint = <&i2c4_bu18rl82_out_panel0>; - }; - }; - }; - - dp2lvds_panel1 { - compatible = "simple-panel"; - backlight = <&dp2lvds_backlight1>; - status = "okay"; - - panel-timing { - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <140>; - hsync-len = <40>; - hback-porch = <100>; - vfront-porch = <15>; - vsync-len = <20>; - vback-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - panel1_in_i2c8_bu18rl82: endpoint { - remote-endpoint = <&i2c8_bu18rl82_out_panel1>; - }; - }; - }; - - edp2lvds_panel0 { - compatible = "simple-panel"; - backlight = <&edp2lvds_backlight0>; - status = "okay"; - - panel-timing { - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <140>; - hsync-len = <40>; - hback-porch = <100>; - vfront-porch = <15>; - vsync-len = <20>; - vback-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - panel0_in_i2c5_bu18rl82: endpoint { - remote-endpoint = <&i2c5_bu18rl82_out_panel0>; - }; - }; - }; - - edp2lvds_panel1 { - compatible = "simple-panel"; - backlight = <&edp2lvds_backlight1>; - status = "okay"; - - panel-timing { - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <140>; - hsync-len = <40>; - hback-porch = <100>; - vfront-porch = <15>; - vsync-len = <20>; - vback-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - panel1_in_i2c7_bu18rl82: endpoint { - remote-endpoint = <&i2c7_bu18rl82_out_panel1>; - }; - }; - }; -}; - -&backlight { - pwms = <&pwm0 0 25000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&bl0_enable_pin>; - enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&dsi2lvds_backlight1 { - pwms = <&pwm13 0 25000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&bl1_enable_pin>; - enable-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&dp0 { - split-mode; - force-hpd; - status = "okay"; - - ports { - port@1 { - reg = <1>; - - dp0_out_i2c4_bu18tl82: endpoint { - remote-endpoint = <&i2c4_bu18tl82_in_dp0>; - }; - }; - }; -}; - -&dp0_in_vp0 { - status = "okay"; -}; - -&dp0_in_vp1 { - status = "disabled"; -}; - -&dp0_in_vp2 { - status = "disabled"; -}; - -&dp1 { - force-hpd; - status = "okay"; - - ports { - port@1 { - reg = <1>; - - dp1_out_i2c8_bu18tl82: endpoint { - remote-endpoint = <&i2c8_bu18tl82_in_dp1>; - }; - }; - }; -}; - -&dp1_in_vp0 { - status = "okay"; -}; - -&dp1_in_vp1 { - status = "disabled"; -}; - -&dp1_in_vp2 { - status = "disabled"; -}; - -&dp2lvds_backlight0 { - pwms = <&pwm10 0 25000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&bl2_enable_pin>; - enable-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&dp2lvds_backlight1 { - pwms = <&pwm14 0 25000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&bl3_enable_pin>; - enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -/* - * mipi_dcphy0 needs to be enabled - * when dsi0 is enabled - */ -&dsi0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - dsi0_out_i2c2_bu18tl82: endpoint { - remote-endpoint = <&i2c2_bu18tl82_in_dsi0>; - }; - }; - }; -}; - -&dsi0_in_vp2 { - status = "okay"; -}; - -&dsi0_in_vp3 { - status = "disabled"; -}; - -/* - * mipi_dcphy1 needs to be enabled - * when dsi1 is enabled - */ -&dsi1 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - dsi1_out_i2c6_bu18tl82: endpoint { - remote-endpoint = <&i2c6_bu18tl82_in_dsi1>; - }; - }; - }; -}; - -&dsi1_in_vp2 { - status = "disabled"; -}; - -&dsi1_in_vp3 { - status = "okay"; -}; - -&edp0 { - split-mode; - force-hpd; - status = "okay"; - - ports { - port@1 { - reg = <1>; - - edp0_out_i2c5_bu18tl82: endpoint { - remote-endpoint = <&i2c5_bu18tl82_in_edp0>; - }; - }; - }; -}; - -&edp0_in_vp0 { - status = "disabled"; -}; - -&edp0_in_vp1 { - status = "okay"; -}; - -&edp0_in_vp2 { - status = "disabled"; -}; - -&edp1 { - force-hpd; - status = "okay"; - - ports { - port@1 { - reg = <1>; - - edp1_out_i2c7_bu18tl82: endpoint { - remote-endpoint = <&i2c7_bu18tl82_in_edp1>; - }; - }; - }; -}; - -&edp1_in_vp0 { - status = "disabled"; -}; - -&edp1_in_vp1 { - status = "okay"; -}; - -&edp1_in_vp2 { - status = "disabled"; -}; - -&edp2lvds_backlight0 { - pwms = <&pwm7 0 25000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&bl4_enable_pin>; - enable-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&edp2lvds_backlight1 { - pwms = <&pwm11 0 25000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&bl5_enable_pin>; - enable-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi0 { - status = "disabled"; -}; - -&hdmi1 { - status = "disabled"; -}; - -&hdptxphy0 { - status = "okay"; -}; - -&hdptxphy1 { - status = "okay"; -}; - -&hdptxphy_hdmi0 { - status = "disabled"; -}; - -&hdptxphy_hdmi1 { - status = "disabled"; -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2m4_xfer>; - clock-frequency = <400000>; - - bu18tl82: bu18tl82@10 { - compatible = "rohm,bu18tl82"; - reg = <0x10>; - pinctrl-names = "default"; - pinctrl-0 = <&ser0_rst_pin>; - reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; - sel-mipi; - status = "okay"; - - serdes-init-sequence = [ - 0021 0008 - 0022 0008 - 0023 0009 - 0024 000a - 0013 0010 - 0014 0010 - 002a 0018 - 002d 0018 - 0030 0018 - 0033 0018 - 02a7 0002 - 02a8 0003 - 02a9 0004 - 02aa 0005 - 0045 0080 - 0046 0007 - 0047 0080 - 0048 0007 - 004b 00d0 - 004c 0002 - 004d 00d0 - 004e 0002 - 0051 0080 - 0052 0007 - 0053 0000 - 0054 00c0 - 022b 0076 - 022c 0062 - 022d 0037 - 024d 0061 - 0252 0005 - 0253 0000 - 0258 0000 - 025c 0000 - 025f 0000 - 0274 0030 - 0275 0020 - 032b 002f - 032c 00a1 - 032d 001d - 034d 0060 - 0353 0000 - 0358 0000 - 035c 0000 - 035f 0000 - 0018 00a5 - 0019 0069 - 0267 003d - 0268 002c - 0269 002c - 026a 002c - 026b 002c - 0367 003d - 0368 002c - 0369 002c - 036a 002c - 036b 002c - 0013 0019 - 0014 0001 - 022e 0080 - 0296 0004 - 0297 000d - 032e 0080 - 038e 0000 - 0396 0004 - 0397 000a - 0060 0001 - 0061 0001 - 0018 0000 - 0019 0000 - /* TL82 Pattern Gen Set 1 - * Horizontal Gray Scale 256 steps - */ - 040A 0010 - 040B 0080 - 040C 0080 - 040D 0080 - 0444 0019 - 0445 0020 - 0446 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c2_bu18tl82_in_dsi0: endpoint { - remote-endpoint = <&dsi0_out_i2c2_bu18tl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c2_bu18tl82_out_i2c2_bu18rl82: endpoint { - remote-endpoint = <&i2c2_bu18rl82_in_i2c2_bu18tl82>; - }; - }; - }; - }; - - bu18rl82: bu18rl82@30 { - compatible = "rohm,bu18rl82"; - reg = <0x30>; - status = "okay"; - serdes-init-sequence = [ - 0011 000b - 0012 0002 - 0013 0001 - 001d 0008 - 001f 0006 - 0020 0006 - 0057 0000 - 0058 0002 - 005a 0000 - 005b 0003 - 005d 0000 - 005e 0001 - 0060 0000 - 0061 0005 - 0073 0080 - 0074 0007 - 0075 0080 - 0076 0007 - 0079 0009 - 007b 00d0 - 007c 0002 - 007d 00d0 - 007e 0002 - 0081 0003 - 0082 000a - 0084 001e - 0086 0001 - 0087 0003 - 0088 0005 - 0089 0014 - 008b 0028 - 008d 0002 - 008e 0004 - 008f 000f - 0090 0001 - 0091 0003 - 0423 00ab - 0424 00aa - 0425 001a - 0429 000a - 045d 0001 - 0523 0097 - 0524 00d0 - 0525 000e - 0529 000a - 055d 0001 - 0426 0080 - 0526 0080 - /* RL82 Pattern Gen Set - * Vertical Gray Scale Color Bar - */ - 060A 00B0 - 060B 00FF - 060C 00FF - 060D 00FF - 0644 0019 - 0645 0020 - 0646 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c2_bu18rl82_in_i2c2_bu18tl82: endpoint { - remote-endpoint = <&i2c2_bu18tl82_out_i2c2_bu18rl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c2_bu18rl82_out_panel0: endpoint { - remote-endpoint = <&panel0_in_i2c2_bu18rl82>; - }; - }; - }; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4m2_xfer>; - clock-frequency = <400000>; - status = "okay"; - - bu18tl82@10 { - compatible = "rohm,bu18tl82"; - reg = <0x10>; - status = "okay"; - - serdes-init-sequence = [ - 0013 001a - 0014 000a - 0021 0008 - 0023 0009 - 0024 0009 - 002a 0018 - 002d 0018 - 0030 0018 - 0033 0018 - 0045 0080 - 0046 0007 - 004b 0038 - 004c 0004 - 0053 0064 - 022b 0062 - 022c 0027 - 022d 002e - 0274 0030 - 0275 0020 - 0296 0004 - 0297 000d - 02b2 00c8 - 02b4 0001 - 02b8 00ff - 02b9 000f - 02ba 00ff - 02bb 000f - 02be 00ff - 02bf 001f - 02c2 00ff - 02c3 001f - 0396 0004 - 0397 000d - 03b2 00c8 - 03b4 0001 - 03b8 00ff - 03b9 000f - 03ba 00ff - 03bb 000f - 03be 00ff - 03bf 001f - 03c2 00ff - 03c3 001f - 0060 0001 - 0061 0003 - 022e 0080 - 032e 0080 - /* TL82 Pattern Gen Set 1 - * Horizontal Gray Scale 256 steps - */ - 040A 0010 - 040B 0080 - 040C 0080 - 040D 0080 - 0444 0019 - 0445 0020 - 0446 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c4_bu18tl82_in_dp0: endpoint { - remote-endpoint = <&dp0_out_i2c4_bu18tl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c4_bu18tl82_out_i2c4_bu18rl82: endpoint { - remote-endpoint = <&i2c4_bu18rl82_in_i2c4_bu18tl82>; - }; - }; - }; - }; - - bu18rl82@30 { - compatible = "rohm,bu18rl82"; - reg = <0x30>; - status = "okay"; - serdes-init-sequence = [ - 0011 000b - 0012 0003 - 0013 0001 - 001d 0008 - 001f 0002 - 0020 0002 - 0057 0000 - 0058 0002 - 005a 0000 - 005b 0003 - 005d 0000 - 005e 0004 - 0060 0000 - 0061 0005 - 0073 0080 - 0074 0007 - 0079 000a - 007b 0038 - 007c 0004 - 0081 0003 - 0082 0010 - 0084 0020 - 0086 0002 - 0087 0002 - 0088 0010 - 0089 0010 - 008b 0020 - 008d 0002 - 008e 0002 - 008f 0010 - 00d0 0040 - 00d8 0042 - 00d9 0004 - 0423 0002 - 0424 00ec - 0425 0027 - 0429 000a - 045d 0001 - 0529 000a - 055d 0003 - 0090 0001 - 0091 0003 - 0426 0080 - /* RL82 Pattern Gen Set - * Vertical Gray Scale Color Bar - */ - 060A 00B0 - 060B 00FF - 060C 00FF - 060D 00FF - 0644 0019 - 0645 0020 - 0646 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c4_bu18rl82_in_i2c4_bu18tl82: endpoint { - remote-endpoint = <&i2c4_bu18tl82_out_i2c4_bu18rl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c4_bu18rl82_out_panel0: endpoint { - remote-endpoint = <&panel0_in_i2c4_bu18rl82>; - }; - }; - }; - }; -}; - -&i2c5 { - clock-frequency = <400000>; - status = "okay"; - - bu18tl82@10 { - compatible = "rohm,bu18tl82"; - reg = <0x10>; - status = "okay"; - - serdes-init-sequence = [ - 0013 001a - 0014 000a - 0021 0008 - 0023 0009 - 0024 0009 - 002a 0018 - 002e 0004 - 002d 0018 - 0030 0000 - 0033 0018 - 027c 0041 - 027d 0041 - 0045 0080 - 0046 0007 - 004b 0038 - 004c 0004 - 0053 0064 - 022b 0062 - 022c 0027 - 022d 002e - 0274 0030 - 0275 0020 - 0296 0004 - 0297 000d - 02b2 00c8 - 02b4 0001 - 02b8 00ff - 02b9 000f - 02ba 00ff - 02bb 000f - 02be 00ff - 02bf 001f - 02c2 00ff - 02c3 001f - 0396 0004 - 0397 000d - 03b2 00c8 - 03b4 0001 - 03b8 00ff - 03b9 000f - 03ba 00ff - 03bb 000f - 03be 00ff - 03bf 001f - 03c2 00ff - 03c3 001f - 0060 0001 - 0061 0003 - 022e 0080 - 032e 0080 - /* TL82 Pattern Gen Set 1 - * Horizontal Gray Scale 256 steps - */ - 040A 0010 - 040B 0080 - 040C 0080 - 040D 0080 - 0444 0019 - 0445 0020 - 0446 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c5_bu18tl82_in_edp0: endpoint { - remote-endpoint = <&edp0_out_i2c5_bu18tl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c5_bu18tl82_out_i2c5_bu18rl82: endpoint { - remote-endpoint = <&i2c5_bu18rl82_in_i2c5_bu18tl82>; - }; - }; - }; - }; - - bu18rl82@30 { - compatible = "rohm,bu18rl82"; - reg = <0x30>; - status = "okay"; - serdes-init-sequence = [ - 0011 000b - 0012 0003 - 0013 0001 - 001d 0008 - 001f 0002 - 0020 0002 - 0031 0041 - 0032 0041 - 0057 0000 - 0058 0002 - 005a 0000 - 005b 0003 - 005d 0008 - 005e 0004 - 0060 0000 - 0061 0005 - 0073 0080 - 0074 0007 - 0079 000a - 007b 0038 - 007c 0004 - 0081 0003 - 0082 0010 - 0084 0020 - 0086 0002 - 0087 0002 - 0088 0010 - 0089 0010 - 008b 0020 - 008d 0002 - 008e 0002 - 008f 0010 - 00d0 0040 - 00d8 0042 - 00d9 0004 - 0423 0002 - 0424 00ec - 0425 0027 - 0429 000a - 045d 0001 - 0529 000a - 055d 0003 - 0090 0001 - 0091 0003 - 0426 0080 - 042d 0004 - /* RL82 Pattern Gen Set - * Vertical Gray Scale Color Bar - */ - 060A 00B0 - 060B 00FF - 060C 00FF - 060D 00FF - 0644 0019 - 0645 0020 - 0646 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c5_bu18rl82_in_i2c5_bu18tl82: endpoint { - remote-endpoint = <&i2c5_bu18tl82_out_i2c5_bu18rl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c5_bu18rl82_out_panel0: endpoint { - remote-endpoint = <&panel0_in_i2c5_bu18rl82>; - }; - }; - }; - }; - - ilitek@41 { - compatible = "ilitek,ili251x"; - reg = <0x41>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&touch_pin>; - reset-gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; - ilitek,name = "ilitek_i2c"; - }; -}; - -&i2c6 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6m3_xfer>; - clock-frequency = <400000>; - - bu18tl82@10 { - compatible = "rohm,bu18tl82"; - reg = <0x10>; - pinctrl-names = "default"; - pinctrl-0 = <&ser1_rst_pin>; - reset-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; - sel-mipi; - status = "okay"; - serdes-init-sequence = [ - 0021 0008 - 0022 0008 - 0023 0009 - 0024 000a - 0013 0010 - 0014 0010 - 002a 0018 - 002d 0018 - 0030 0018 - 0033 0018 - 027c 0070 - 027d 0070 - 02a7 0002 - 02a8 0003 - 02a9 0004 - 02aa 0005 - 0045 0080 - 0046 0007 - 0047 0080 - 0048 0007 - 004b 00d0 - 004c 0002 - 004d 00d0 - 004e 0002 - 0051 0080 - 0052 0007 - 0053 0000 - 0054 00c0 - 022b 0076 - 022c 0062 - 022d 0037 - 024d 0061 - 0252 0005 - 0253 0000 - 0258 0000 - 025c 0000 - 025f 0000 - 0274 0030 - 0275 0020 - 032b 002f - 032c 00a1 - 032d 001d - 034d 0060 - 0353 0000 - 0358 0000 - 035c 0000 - 035f 0000 - 0018 00a5 - 0019 0069 - 0267 003d - 0268 002c - 0269 002c - 026a 002c - 026b 002c - 0367 003d - 0368 002c - 0369 002c - 036a 002c - 036b 002c - 0013 0019 - 0014 0001 - 022e 0080 - 0296 0004 - 0297 000d - 032e 0080 - 038e 0000 - 0396 0004 - 0397 000a - 0060 0001 - 0061 0001 - 0018 0000 - 0019 0000 - /* TL82 Pattern Gen Set 1 - * Horizontal Gray Scale 256 steps - */ - 040A 0010 - 040B 0080 - 040C 0080 - 040D 0080 - 0444 0019 - 0445 0020 - 0446 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c6_bu18tl82_in_dsi1: endpoint { - remote-endpoint = <&dsi1_out_i2c6_bu18tl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c6_bu18tl82_out_i2c6_bu18rl82: endpoint { - remote-endpoint = <&i2c6_bu18rl82_in_i2c6_bu18tl82>; - }; - }; - }; - }; - - bu18rl82@30 { - compatible = "rohm,bu18rl82"; - reg = <0x30>; - status = "okay"; - serdes-init-sequence = [ - 0011 000b - 0012 0002 - 0013 0001 - 001d 0008 - 001f 0006 - 0020 0006 - 0031 0070 - 0032 0038 - 0057 0000 - 0058 0002 - 005a 0000 - 005b 0003 - 005d 0000 - 005e 0001 - 0060 0000 - 0061 0005 - 0073 0080 - 0074 0007 - 0075 0080 - 0076 0007 - 0079 0009 - 007b 00d0 - 007c 0002 - 007d 00d0 - 007e 0002 - 0081 0003 - 0082 000a - 0084 001e - 0086 0001 - 0087 0003 - 0088 0005 - 0089 0014 - 008b 0028 - 008d 0002 - 008e 0004 - 008f 000f - 0090 0001 - 0091 0003 - 0423 00ab - 0424 00aa - 0425 001a - 0429 000a - 045d 0001 - 0523 0097 - 0524 00d0 - 0525 000e - 0529 000a - 055d 0001 - 0426 0080 - 0526 0080 - /* RL82 Pattern Gen Set - * Vertical Gray Scale Color Bar - */ - 060A 00B0 - 060B 00FF - 060C 00FF - 060D 00FF - 0644 0019 - 0645 0020 - 0646 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c6_bu18rl82_in_i2c6_bu18tl82: endpoint { - remote-endpoint = <&i2c6_bu18tl82_out_i2c6_bu18rl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c6_bu18rl82_out_panel1: endpoint { - remote-endpoint = <&panel1_in_i2c6_bu18rl82>; - }; - }; - }; - }; -}; - -&i2c7 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c7m3_xfer>; - clock-frequency = <400000>; - status = "okay"; - - bu18tl82@10 { - compatible = "rohm,bu18tl82"; - reg = <0x10>; - status = "okay"; - - serdes-init-sequence = [ - 0013 001a - 0014 000a - 0021 0008 - 0023 0009 - 0024 0009 - 002a 0018 - 002d 0018 - 0030 0018 - 0033 0018 - 0045 0080 - 0046 0007 - 004b 0038 - 004c 0004 - 0053 0064 - 022b 0062 - 022c 0027 - 022d 002e - 0274 0030 - 0275 0020 - 0296 0004 - 0297 000d - 02b2 00c8 - 02b4 0001 - 02b8 00ff - 02b9 000f - 02ba 00ff - 02bb 000f - 02be 00ff - 02bf 001f - 02c2 00ff - 02c3 001f - 0396 0004 - 0397 000d - 03b2 00c8 - 03b4 0001 - 03b8 00ff - 03b9 000f - 03ba 00ff - 03bb 000f - 03be 00ff - 03bf 001f - 03c2 00ff - 03c3 001f - 0060 0001 - 0061 0003 - 022e 0080 - 032e 0080 - /* TL82 Pattern Gen Set 1 - * Horizontal Gray Scale 256 steps - */ - 040A 0010 - 040B 0080 - 040C 0080 - 040D 0080 - 0444 0019 - 0445 0020 - 0446 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c7_bu18tl82_in_edp1: endpoint { - remote-endpoint = <&edp1_out_i2c7_bu18tl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c7_bu18tl82_out_i2c7_bu18rl82: endpoint { - remote-endpoint = <&i2c7_bu18rl82_in_i2c7_bu18tl82>; - }; - }; - }; - }; - - bu18rl82@30 { - compatible = "rohm,bu18rl82"; - reg = <0x30>; - status = "okay"; - serdes-init-sequence = [ - 0011 000b - 0012 0003 - 0013 0001 - 001d 0008 - 001f 0002 - 0020 0002 - 0057 0000 - 0058 0002 - 005a 0000 - 005b 0003 - 005d 0000 - 005e 0004 - 0060 0000 - 0061 0005 - 0073 0080 - 0074 0007 - 0079 000a - 007b 0038 - 007c 0004 - 0081 0003 - 0082 0010 - 0084 0020 - 0086 0002 - 0087 0002 - 0088 0010 - 0089 0010 - 008b 0020 - 008d 0002 - 008e 0002 - 008f 0010 - 00d0 0040 - 00d8 0042 - 00d9 0004 - 0423 0002 - 0424 00ec - 0425 0027 - 0429 000a - 045d 0001 - 0529 000a - 055d 0003 - 0090 0001 - 0091 0003 - 0426 0080 - /* RL82 Pattern Gen Set - * Vertical Gray Scale Color Bar - */ - 060A 00B0 - 060B 00FF - 060C 00FF - 060D 00FF - 0644 0019 - 0645 0020 - 0646 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c7_bu18rl82_in_i2c7_bu18tl82: endpoint { - remote-endpoint = <&i2c7_bu18tl82_out_i2c7_bu18rl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c7_bu18rl82_out_panel1: endpoint { - remote-endpoint = <&panel1_in_i2c7_bu18rl82>; - }; - }; - }; - }; -}; - -&i2c8 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c8m2_xfer>; - clock-frequency = <400000>; - status = "okay"; - - bu18tl82@10 { - compatible = "rohm,bu18tl82"; - reg = <0x10>; - status = "okay"; - - serdes-init-sequence = [ - 0013 001a - 0014 000a - 0021 0008 - 0023 0009 - 0024 0009 - 002a 0018 - 002d 0018 - 0030 0018 - 0033 0018 - 0045 0080 - 0046 0007 - 004b 0038 - 004c 0004 - 0053 0064 - 022b 0062 - 022c 0027 - 022d 002e - 0274 0030 - 0275 0020 - 0296 0004 - 0297 000d - 02b2 00c8 - 02b4 0001 - 02b8 00ff - 02b9 000f - 02ba 00ff - 02bb 000f - 02be 00ff - 02bf 001f - 02c2 00ff - 02c3 001f - 0396 0004 - 0397 000d - 03b2 00c8 - 03b4 0001 - 03b8 00ff - 03b9 000f - 03ba 00ff - 03bb 000f - 03be 00ff - 03bf 001f - 03c2 00ff - 03c3 001f - 0060 0001 - 0061 0003 - 022e 0080 - 032e 0080 - /* TL82 Pattern Gen Set 1 - * Horizontal Gray Scale 256 steps - */ - 040A 0010 - 040B 0080 - 040C 0080 - 040D 0080 - 0444 0019 - 0445 0020 - 0446 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c8_bu18tl82_in_dp1: endpoint { - remote-endpoint = <&dp1_out_i2c8_bu18tl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c8_bu18tl82_out_i2c8_bu18rl82: endpoint { - remote-endpoint = <&i2c8_bu18rl82_in_i2c8_bu18tl82>; - }; - }; - }; - }; - - bu18rl82@30 { - compatible = "rohm,bu18rl82"; - reg = <0x30>; - status = "okay"; - serdes-init-sequence = [ - 0011 000b - 0012 0003 - 0013 0001 - 001d 0008 - 001f 0002 - 0020 0002 - 0057 0000 - 0058 0002 - 005a 0000 - 005b 0003 - 005d 0000 - 005e 0004 - 0060 0000 - 0061 0005 - 0073 0080 - 0074 0007 - 0079 000a - 007b 0038 - 007c 0004 - 0081 0003 - 0082 0010 - 0084 0020 - 0086 0002 - 0087 0002 - 0088 0010 - 0089 0010 - 008b 0020 - 008d 0002 - 008e 0002 - 008f 0010 - 00d0 0040 - 00d8 0042 - 00d9 0004 - 0423 0002 - 0424 00ec - 0425 0027 - 0429 000a - 045d 0001 - 0529 000a - 055d 0003 - 0090 0001 - 0091 0003 - 0426 0080 - /* RL82 Pattern Gen Set - * Vertical Gray Scale Color Bar - */ - 060A 00B0 - 060B 00FF - 060C 00FF - 060D 00FF - 0644 0019 - 0645 0020 - 0646 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c8_bu18rl82_in_i2c8_bu18tl82: endpoint { - remote-endpoint = <&i2c8_bu18tl82_out_i2c8_bu18rl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c8_bu18rl82_out_panel1: endpoint { - remote-endpoint = <&panel1_in_i2c8_bu18rl82>; - }; - }; - }; - }; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&mipi_dcphy1 { - status = "okay"; -}; - - -&pinctrl { - - bl { - bl0_enable_pin: bl0-enable-pin { - rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bl1_enable_pin: bl1-enable-pin { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bl2_enable_pin: bl2-enable-pin { - rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bl3_enable_pin: bl3-enable-pin { - rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bl4_enable_pin: bl4-enable-pin { - rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bl5_enable_pin: bl5-enable-pin { - rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - serdes { - //dsi0 - ser0_rst_pin: ser0-rst-pin { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - //dsi1 - ser1_rst_pin: ser1-rst-pin { - rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - touch { - touch_pin: touch-pin { - rockchip,pins = - <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>, //INT - <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; //RST - }; - }; -}; - -/* dsi0->serdes->lvds_panel */ -&pwm0 { - status = "okay"; - pinctrl-0 = <&pwm0m2_pins>; -}; - -/* dp0->serdes->lvds_panel */ -&pwm10 { - pinctrl-0 = <&pwm10m2_pins>; - status = "okay"; -}; - -/* edp1->serdes->lvds_panel */ -&pwm11 { - pinctrl-0 = <&pwm11m3_pins>; - status = "okay"; -}; - -/* edp0->serdes->lvds_panel */ -&pwm7 { - pinctrl-0 = <&pwm7m0_pins>; - status = "okay"; -}; - -/* dsi1->serdes->lvds_panel */ -&pwm13 { - status = "okay"; - pinctrl-0 = <&pwm13m1_pins>; -}; - -/* dp1->serdes->lvds_panel */ -&pwm14 { - pinctrl-0 = <&pwm14m0_pins>; - status = "okay"; -}; - -&route_dp0 { - status = "disabled"; - connect = <&vp0_out_dp0>; - logo,uboot = "logo34.bmp"; - logo,kernel = "logo34.bmp"; -}; - -&route_dp1 { - status = "disabled"; - connect = <&vp0_out_dp1>; - logo,uboot = "logo34.bmp"; - logo,kernel = "logo34.bmp"; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp2_out_dsi0>; - logo,uboot = "logo1.bmp"; - logo,kernel = "logo1.bmp"; -}; - -&route_dsi1 { - status = "okay"; - connect = <&vp3_out_dsi1>; - logo,uboot = "logo2.bmp"; - logo,kernel = "logo2.bmp"; -}; - -&route_edp0 { - status = "disabled"; - connect = <&vp1_out_edp0>; - logo,uboot = "logo56.bmp"; - logo,kernel = "logo56.bmp"; -}; - -&route_edp1 { - status = "disabled"; - connect = <&vp1_out_edp1>; - logo,uboot = "logo56.bmp"; - logo,kernel = "logo56.bmp"; -}; - -&usbdp_phy0 { - rockchip,dp-lane-mux = <0 1 2 3>; - status = "okay"; -}; - -&usbdp_phy1 { - rockchip,dp-lane-mux = <0 1 2 3>; - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru PLL_V0PLL>; - assigned-clock-rates = <1152000000>; -}; - -&vp0 { - assigned-clocks = <&cru DCLK_VOP0_SRC>; - assigned-clock-parents = <&cru PLL_V0PLL>; -}; - -&vp1 { - assigned-clocks = <&cru DCLK_VOP1_SRC>; - assigned-clock-parents = <&cru PLL_GPLL>; -}; - -&vp2 { - assigned-clocks = <&cru DCLK_VOP2_SRC>; - assigned-clock-parents = <&cru PLL_V0PLL>; -}; - -&vp3 { - assigned-clocks = <&cru DCLK_VOP3>; - assigned-clock-parents = <&cru PLL_V0PLL>; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v21.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v21.dtsi deleted file mode 100644 index eb927ddb0..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display-v21.dtsi +++ /dev/null @@ -1,2095 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Rockchip Electronics Co., Ltd. - * - */ - -/ { - dsi2lvds_backlight1: dsi2lvds_backlight1 { - compatible = "pwm-backlight"; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - dp2lvds_backlight0: dp2lvds_backlight0 { - compatible = "pwm-backlight"; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - dp2lvds_backlight1: dp2lvds_backlight1 { - compatible = "pwm-backlight"; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - edp2lvds_backlight0: edp2lvds_backlight0 { - compatible = "pwm-backlight"; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - edp2lvds_backlight1: edp2lvds_backlight1 { - compatible = "pwm-backlight"; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - dsi2lvds_panel0 { - compatible = "simple-panel"; - backlight = <&backlight>; - - display-timings { - native-mode = <&dsi2lvds0>; - dsi2lvds0: timing0 { - clock-frequency = <115200000>;//115200000/105573600 - hactive = <1920>; - vactive = <720>; - hfront-porch = <56>; - hsync-len = <32>; - hback-porch = <56>; - vfront-porch = <200>; - vsync-len = <2>; - vback-porch = <8>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - panel0_in_i2c2_bu18rl82: endpoint { - remote-endpoint = <&i2c2_bu18rl82_out_panel0>; - }; - }; - }; - }; - - dsi2lvds_panel1 { - compatible = "simple-panel"; - backlight = <&dsi2lvds_backlight1>; - - display-timings { - native-mode = <&dsi2lvds1>; - dsi2lvds1: timing0 { - clock-frequency = <115200000>; - hactive = <1920>; - vactive = <720>; - hfront-porch = <56>; - hsync-len = <32>; - hback-porch = <56>; - vfront-porch = <200>; - vsync-len = <2>; - vback-porch = <8>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - panel1_in_i2c6_bu18rl82: endpoint { - remote-endpoint = <&i2c6_bu18rl82_out_panel1>; - }; - }; - }; - }; - - dp2lvds_panel0 { - compatible = "simple-panel"; - backlight = <&dp2lvds_backlight0>; - status = "okay"; - - panel-timing { - clock-frequency = <115200000>; - hactive = <1920>; - vactive = <720>; - hfront-porch = <56>; - hsync-len = <32>; - hback-porch = <56>; - vfront-porch = <200>; - vsync-len = <2>; - vback-porch = <8>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - panel0_in_i2c4_bu18rl82: endpoint { - remote-endpoint = <&i2c4_bu18rl82_out_panel0>; - }; - }; - }; - - dp2lvds_panel1 { - compatible = "simple-panel"; - backlight = <&dp2lvds_backlight1>; - status = "disabled"; - - panel-timing { - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <140>; - hsync-len = <40>; - hback-porch = <100>; - vfront-porch = <15>; - vsync-len = <20>; - vback-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - panel1_in_i2c8_bu18rl82: endpoint { - remote-endpoint = <&i2c8_bu18rl82_out_panel1>; - }; - }; - }; - - edp2lvds_panel0 { - compatible = "simple-panel"; - backlight = <&edp2lvds_backlight0>; - status = "okay"; - - panel-timing { - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <140>; - hsync-len = <40>; - hback-porch = <100>; - vfront-porch = <15>; - vsync-len = <20>; - vback-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - panel0_in_i2c5_bu18rl82: endpoint { - remote-endpoint = <&i2c5_bu18rl82_out_panel0>; - }; - }; - }; - - edp2lvds_panel1 { - compatible = "simple-panel"; - backlight = <&edp2lvds_backlight1>; - status = "disabled"; - - panel-timing { - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <140>; - hsync-len = <40>; - hback-porch = <100>; - vfront-porch = <15>; - vsync-len = <20>; - vback-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - panel1_in_i2c7_bu18rl82: endpoint { - remote-endpoint = <&i2c7_bu18rl82_out_panel1>; - }; - }; - }; -}; - -&backlight { - pwms = <&pwm0 0 25000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&bl0_enable_pin>; - enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&dsi2lvds_backlight1 { - pwms = <&pwm13 0 25000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&bl1_enable_pin>; - enable-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&dp0 { - //split-mode; - force-hpd; - status = "okay"; - - ports { - port@1 { - reg = <1>; - - dp0_out_i2c4_bu18tl82: endpoint { - remote-endpoint = <&i2c4_bu18tl82_in_dp0>; - }; - }; - }; -}; - -&dp0_in_vp0 { - status = "okay"; -}; - -&dp0_in_vp1 { - status = "disabled"; -}; - -&dp0_in_vp2 { - status = "disabled"; -}; - -&dp1 { - force-hpd; - status = "disabled"; - - ports { - port@1 { - reg = <1>; - - dp1_out_i2c8_bu18tl82: endpoint { - remote-endpoint = <&i2c8_bu18tl82_in_dp1>; - }; - }; - }; -}; - -&dp1_in_vp0 { - status = "okay"; -}; - -&dp1_in_vp1 { - status = "disabled"; -}; - -&dp1_in_vp2 { - status = "disabled"; -}; - -&dp2lvds_backlight0 { - pwms = <&pwm10 0 25000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&bl2_enable_pin>; - enable-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&dp2lvds_backlight1 { - pwms = <&pwm14 0 25000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&bl3_enable_pin>; - enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -/* - * mipi_dcphy0 needs to be enabled - * when dsi0 is enabled - */ -&dsi0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - dsi0_out_i2c2_bu18tl82: endpoint { - remote-endpoint = <&i2c2_bu18tl82_in_dsi0>; - }; - }; - }; -}; - -&dsi0_in_vp2 { - status = "okay"; -}; - -&dsi0_in_vp3 { - status = "disabled"; -}; - -/* - * mipi_dcphy1 needs to be enabled - * when dsi1 is enabled - */ -&dsi1 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - dsi1_out_i2c6_bu18tl82: endpoint { - remote-endpoint = <&i2c6_bu18tl82_in_dsi1>; - }; - }; - }; -}; - -&dsi1_in_vp2 { - status = "disabled"; -}; - -&dsi1_in_vp3 { - status = "okay"; -}; - -&edp0 { - //split-mode; - force-hpd; - status = "okay"; - - ports { - port@1 { - reg = <1>; - - edp0_out_i2c5_bu18tl82: endpoint { - remote-endpoint = <&i2c5_bu18tl82_in_edp0>; - }; - }; - }; -}; - -&edp0_in_vp0 { - status = "disabled"; -}; - -&edp0_in_vp1 { - status = "okay"; -}; - -&edp0_in_vp2 { - status = "disabled"; -}; - -&edp1 { - force-hpd; - status = "disabled"; - - ports { - port@1 { - reg = <1>; - - edp1_out_i2c7_bu18tl82: endpoint { - remote-endpoint = <&i2c7_bu18tl82_in_edp1>; - }; - }; - }; -}; - -&edp1_in_vp0 { - status = "disabled"; -}; - -&edp1_in_vp1 { - status = "okay"; -}; - -&edp1_in_vp2 { - status = "disabled"; -}; - -&edp2lvds_backlight0 { - pwms = <&pwm7 0 25000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&bl4_enable_pin>; - enable-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&edp2lvds_backlight1 { - pwms = <&pwm11 0 25000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&bl5_enable_pin>; - enable-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi0 { - status = "disabled"; -}; - -&hdmi1 { - status = "disabled"; -}; - -&hdptxphy0 { - status = "okay"; -}; - -&hdptxphy1 { - status = "okay"; -}; - -&hdptxphy_hdmi0 { - status = "disabled"; -}; - -&hdptxphy_hdmi1 { - status = "disabled"; -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2m4_xfer>; - clock-frequency = <400000>; - - bu18tl82: bu18tl82@10 { - compatible = "rohm,bu18tl82"; - reg = <0x10>; - pinctrl-names = "default"; - pinctrl-0 = <&ser0_rst_pin>; - reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; - sel-mipi; - status = "okay"; - - serdes-init-sequence = [ - 0013 0019 - 0014 0008 //014h[3]-lane1 enable - 0021 0008 - 0023 0009 - 0024 0009 - 022b 0038 - 022c 0072 - 022d 0023 //VPLL=75MHZS - //022b 00d8 - //022c 0089 - //022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M - 022e 0080 - 027c 0048 - 027d 0048 //i2c addr 0x48 - 0296 0004 - 0297 0009 //CLLTX0_PLL_GAIN 297h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane - //0297 000d //CLLTX0_PLL_GAIN 297h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane - 0018 00a5 - 0019 0069 - 0267 003d - 0268 002c - 0269 002c - 026a 002c - 026b 002c - 0367 003d - 0368 002c - 0369 002c - 036a 002c - 036b 002c - 0018 0000 - 0019 0000 - 002a 0018 //gpio0 input lcd_bl_pwm - 002d 0018 //gpio1 input lcd_pwr_en - - 0030 0018 //gpio2 input lcd_rst - 0033 0018 //gpio3 input tp_rst - 0034 0005 //bypass des gpio3 - 0036 0000 //gpio4 output tp_int - 0037 0006 //bypass des gpio4 - - 02a7 0002 - 02a8 0003 - 02a9 0004 - 02aa 0005 - 0045 0080 - 0046 0007 //1920 - 004b 00d0 - 004c 0002 //720 - 004d 00d0 - 004e 0002 //720 - 0051 0080 - 0052 0007 //1920 - 0053 0024 //CLLCH2_EN 53h[5] 0:1 Clock Tx lane/1:2 Clock Tx lanes - 0054 0080 - 024d 0061 - 0252 0005 - 0274 0030 //I2C slave address of BU18RL82 for accessing via BU18TL82 - 0275 0020 - 0396 0004 - 0397 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.31 Gbps/lane - //0397 000d //CLLTX0_PLL_GAIN 397h[3:2] 1101 2'b11: 2.2~3.60 Gbps/lane - 0061 0003 //CLLTX0 enable CLLTX1 enable - 0060 0003 //CLLTX0/1 RGB data output Enable - /* TL82 Pattern Gen Set 1 - * Horizontal Gray Scale 256 steps - */ - 040A 0010 - 040B 0080 - 040C 0080 - 040D 0080 - 0444 0090 - 0446 00d2 - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c2_bu18tl82_in_dsi0: endpoint { - remote-endpoint = <&dsi0_out_i2c2_bu18tl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c2_bu18tl82_out_i2c2_bu18rl82: endpoint { - remote-endpoint = <&i2c2_bu18rl82_in_i2c2_bu18tl82>; - }; - }; - }; - }; - - bu18rl82: bu18rl82@30 { - compatible = "rohm,bu18rl82"; - reg = <0x30>; - status = "okay"; - serdes-init-sequence = [ - 0011 0003 //Clockless Link Receiver Lane-0+ LVDS portA - 0012 0003 //Clockless Link Receiver Lane-1+ LVDS portB - 0013 0000 - 001d 0008 - 001f 0002 //LVDSTX0_REFSEL - 0020 0002 //LVDSTX1_REFSEL - 0031 0048 - 0032 0048 //i2c addr 0x48 - 0423 0000 - 0424 0000 - 0425 0020 - 0426 0080 - 0057 0000 - 0058 0002 - 0057 0000 //rl gpio0 output lcd_bl_pwm - 0058 0002 //bypass ser gpio0 - 005a 0000 //rl gpio1 output lcd_pwr_en - 005b 0003 //bypass ser gpio1 - 005d 0000 //rl gpio2 output lcd_rst - 005e 0004 //bypass ser gpio2 - 0060 0000 //rl gpio3 output tp-rst - 0061 0005 //bypass ser gpio3 - 0063 0018 //rl gpio4 input tp-int - 0064 0006 //bypass ser gpio4 - 0066 0000 //rl gpio5 output - 0067 0001 //set gpio5 high - - 0073 0080 - 0074 0007 //0x0780 = 1920 - 0075 0080 - 0076 0007 //0x0780 = 1920 - 0079 000a //h[3]: dual lvds mode h[1] single lane / dual lane - 007b 00d0 - 007c 0002 //0x02d0 = 720 - 007d 00d0 - 007e 0002 //0x02d0 = 720 - 0081 0003 //01---> Sync OFF - 0082 0010 //Hsync=16clk - 0084 001c //HBP=28clk - 0086 0002 //Vsync=2lines - 0087 0008 //VBP=8lines - 0088 0000 //VSYNC_CHG=0CLK - 0089 0010 //Hsync = 16? - 008b 001c //HFP=28clk? - 008d 0002 //Vsync=2lines? - 008e 0008 //VFP=8line? - 008f 0000 //VSYNC_CHG=0CLK? - 00d0 0040 //[3]FixHtotalEN - 00d8 00c0 - 00d9 0003 //DE=960 - 0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz - 045d 0001 - 0529 000a //LVDSTX1_PLLGAIN 2'b10: 30 MHz ~ 80 MHz - 055d 0001 - 0091 0003 - 0090 0001 - /* RL82 Pattern Gen Set - * Vertical Gray Scale Color Bar - */ - 060A 00B0 - 060B 00FF - 060C 00FF - 060D 00FF - 0644 0090 - 0646 00d2 - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c2_bu18rl82_in_i2c2_bu18tl82: endpoint { - remote-endpoint = <&i2c2_bu18tl82_out_i2c2_bu18rl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c2_bu18rl82_out_panel0: endpoint { - remote-endpoint = <&panel0_in_i2c2_bu18rl82>; - }; - }; - }; - }; - - himax@48 { - compatible = "himax,hxcommon"; - reg = <0x48>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&touch_gpio_dsi0>; - pinctrl-1 = <&touch_gpio_dsi0>; - himax,location = "himax-touch-dsi0"; - //himax,irq-gpio = <&gpio1 RK_PB0 IRQ_TYPE_EDGE_FALLING>; - himax,panel-coords = <0 1920 0 720>; - himax,display-coords = <0 1920 0 720>; - status = "okay"; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4m2_xfer>; - clock-frequency = <400000>; - status = "okay"; - - bu18tl82@10 { - compatible = "rohm,bu18tl82"; - reg = <0x10>; - status = "okay"; - - serdes-init-sequence = [ - 0013 001a //013h[3]1-lane1 enable 013h[3] 1-LVDS Receiver Port-A - 0014 000a //014h[3]1-lane1 enable 014h[3] 1-LVDS Receiver Port-B - 0021 0008 - 0023 0009 - 0024 0009 - 022b 0038 - 022c 0072 - 022d 0023 //VPLL=75MHZS - //022b 00d8 - //022c 0089 - //022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M - 022e 0080 - 027c 0048 - 027d 0048 //i2c addr 0x48 - 0296 0004 - 0297 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.31 Gbps/lane - //0297 000d //CLLTX0_PLL_GAIN 297h[3:2] 1101 2'b11: 2.2~3.60 Gbps/lane - 0018 00a5 - 0019 0069 - 0267 003d - 0268 002c - 0269 002c - 026a 002c - 026b 002c - 0367 003d - 0368 002c - 0369 002c - 036a 002c - 036b 002c - 0018 0000 - 0019 0000 - 002a 0018 //gpio0 input lcd_bl_pwm - 002d 0018 //gpio1 input lcd_pwr_en - - 0030 0018 //gpio2 input lcd_rst - 0033 0018 //gpio3 input tp_rst - 0034 0005 //bypass des gpio3 - 0036 0000 //gpio4 output tp_int - 0037 0006 //bypass des gpio4 - - 02a7 0002 - 02a8 0003 - 02a9 0004 - 02aa 0005 - 0045 0080 - 0046 0007 //1920 - 004b 00d0 - 004c 0002 //720 - 004d 00d0 - 004e 0002 //720 - 0051 0080 - 0052 0007 //1920 - 0053 0064 //0053h[6]1:2 Rx ports CLLCH2_EN 53h[5] 1:2 Clock Tx lanes - 024d 0061 - 0252 0005 - 0274 0030 - 0275 0020 - 0396 0004 - 0397 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane - //0397 000d //CLLTX0_PLL_GAIN 397h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane - 0061 0003 //CLLTX0 enable CLLTX1 enable - 0060 0003 //CLLTX0/1 RGB data output Enable - /* TL82 Pattern Gen Set 1 - * Horizontal Gray Scale 256 steps - */ - 040A 0010 - 040B 0080 - 040C 0080 - 040D 0080 - 0444 0090 //h_blank=144 - 0446 00d2 //v_blank=210 - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c4_bu18tl82_in_dp0: endpoint { - remote-endpoint = <&dp0_out_i2c4_bu18tl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c4_bu18tl82_out_i2c4_bu18rl82: endpoint { - remote-endpoint = <&i2c4_bu18rl82_in_i2c4_bu18tl82>; - }; - }; - }; - }; - - bu18rl82@30 { - compatible = "rohm,bu18rl82"; - reg = <0x30>; - status = "okay"; - serdes-init-sequence = [ - 0011 0003 //Clockless Link Receiver Lane-0+ LVDS portA - 0012 0003 //Clockless Link Receiver Lane-1+ LVDS portB - 0013 0000 - 001d 0008 - 001f 0002 //LVDSTX0_REFSEL - 0020 0002 //LVDSTX1_REFSEL - 0031 0048 - 0032 0048 //i2c addr 0x48 - 0423 0000 - 0424 0000 - 0425 0020 - 0426 0080 - 0057 0000 - 0058 0002 - 0057 0000 //rl gpio0 output lcd_bl_pwm - 0058 0002 //bypass ser gpio0 - 005a 0000 //rl gpio1 output lcd_pwr_en - 005b 0003 //bypass ser gpio1 - 005d 0000 //rl gpio2 output lcd_rst - 005e 0004 //bypass ser gpio2 - 0060 0000 //rl gpio3 output tp-rst - 0061 0005 //bypass ser gpio3 - 0063 0018 //rl gpio4 input tp-int - 0064 0006 //bypass ser gpio4 - 0066 0000 //rl gpio5 output - 0067 0001 //set gpio5 high - - 0073 0080 - 0074 0007 //0x0780 = 1920 - 0075 0080 - 0076 0007 //0x0780 = 1920 - 0079 000a //h[3]: dual lvds mode h[1] single lane / dual lane - 007b 00d0 - 007c 0002 //0x02d0 = 720 - 007d 00d0 - 007e 0002 //0x02d0 = 720 - 0081 0003 //01---> Sync OFF - 0082 0010 //Hsync=16clk - 0084 001c //HBP=28clk - 0086 0002 //Vsync=2lines - 0087 0008 //VBP=8lines - 0088 0000 //VSYNC_CHG=0CLK - 0089 0010 //Hsync = 16? - 008b 001c //HFP=28clk? - 008d 0002 //Vsync=2lines? - 008e 0008 //VFP=8line? - 008f 0000 //VSYNC_CHG=0CLK? - 00d0 0040 //[3]FixHtotalEN - 00d8 00c0 - 00d9 0003 //DE=960 - 0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz - 045d 0001 - 0529 000a //LVDSTX1_PLLGAIN 2'b10: 30 MHz ~ 80 MHz - 055d 0001 - 0091 0003 - 0090 0001 - /* RL82 Pattern Gen Set - * Vertical Gray Scale Color Bar - */ - 060A 00B0 - 060B 00FF - 060C 00FF - 060D 00FF - 0644 0090 - 0646 00d2 - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c4_bu18rl82_in_i2c4_bu18tl82: endpoint { - remote-endpoint = <&i2c4_bu18tl82_out_i2c4_bu18rl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c4_bu18rl82_out_panel0: endpoint { - remote-endpoint = <&panel0_in_i2c4_bu18rl82>; - }; - }; - }; - }; - - himax@48 { - compatible = "himax,hxcommon"; - reg = <0x48>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&touch_gpio_dp0>; - pinctrl-1 = <&touch_gpio_dp0>; - himax,location = "himax-touch-dp0"; - himax,irq-gpio = <&gpio0 RK_PC0 IRQ_TYPE_EDGE_FALLING>; - himax,panel-coords = <0 1920 0 720>; - himax,display-coords = <0 1920 0 720>; - status = "okay"; - }; - - lt7911d@2b { - compatible = "lontium,lt7911d"; - reg = <0x2b>; - reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; - status = "okay"; - }; -}; - -&i2c5 { - clock-frequency = <400000>; - status = "okay"; - - bu18tl82@10 { - compatible = "rohm,bu18tl82"; - reg = <0x10>; - status = "okay"; - - serdes-init-sequence = [ - 0013 001a - 0014 000a - 0021 0008 - 0023 0009 - 0024 0009 - 002a 0018 //gpio0 input lcd_bl_pwm - 002d 0018 //gpio1 input lcd_pwr_en - - 0030 0018 //gpio2 input lcd_rst - 0033 0000 //gpio3 output tp_int - 0034 0005 //bypass des gpio3 - 0036 0018 //gpio4 input tp_rst - 0037 0006 //bypass des gpio4 - 027c 0041 - 027d 0041 - 0045 0080 - 0046 0007 - 004b 0038 - 004c 0004 - 0053 0064 - 022b 0062 - 022c 0027 - 022d 002e - 0274 0030 - 0275 0020 - 0296 0004 - 0297 000d - 02b2 00c8 - 02b4 0001 - 02b8 00ff - 02b9 000f - 02ba 00ff - 02bb 000f - 02be 00ff - 02bf 001f - 02c2 00ff - 02c3 001f - 0396 0004 - 0397 000d - 03b2 00c8 - 03b4 0001 - 03b8 00ff - 03b9 000f - 03ba 00ff - 03bb 000f - 03be 00ff - 03bf 001f - 03c2 00ff - 03c3 001f - 0060 0001 - 0061 0003 - 022e 0080 - 032e 0080 - /* TL82 Pattern Gen Set 1 - * Horizontal Gray Scale 256 steps - */ - 040A 0010 - 040B 0080 - 040C 0080 - 040D 0080 - 0444 0019 - 0445 0020 - 0446 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c5_bu18tl82_in_edp0: endpoint { - remote-endpoint = <&edp0_out_i2c5_bu18tl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c5_bu18tl82_out_i2c5_bu18rl82: endpoint { - remote-endpoint = <&i2c5_bu18rl82_in_i2c5_bu18tl82>; - }; - }; - }; - }; - - bu18rl82@30 { - compatible = "rohm,bu18rl82"; - reg = <0x30>; - status = "okay"; - serdes-init-sequence = [ - 0011 000b - 0012 0003 - 0013 0001 - 001d 0008 - 001f 0002 - 0020 0002 - 0031 0041 //i2c addr 0x41 - 0032 0041 //i2c addr 0x41 - 0057 0000 //rl gpio0 output lcd_bl_pwm - 0058 0002 //bypass ser gpio0 - 005a 0000 //rl gpio1 output lcd_pwr_en - 005b 0001 //bypass ser gpio1 - 005d 0000 //rl gpio2 output lcd_rst - 005e 0004 //bypass ser gpio2 - 0060 0018 //rl gpio3 input tp-int - 042e 0005 //bypass ser gpio3 - 0061 0005 //bypass ser gpio3 - 0063 0000 //rl gpio4 output tp-rst - 042f 0006 //bypass ser gpio4 - 0064 0006 //bypass ser gpio4 - 0066 0000 //rl gpio5 output - 0067 0007 //bypass ser gpio5 - 0073 0080 - 0074 0007 - 0079 000a - 007b 0038 - 007c 0004 - 0081 0003 - 0082 0010 - 0084 0020 - 0086 0002 - 0087 0002 - 0088 0010 - 0089 0010 - 008b 0020 - 008d 0002 - 008e 0002 - 008f 0010 - 00d0 0040 - 00d8 0042 - 00d9 0004 - 0423 0002 - 0424 00ec - 0425 0027 - 0429 000a - 045d 0001 - 0529 000a - 055d 0003 - 0090 0001 - 0091 0003 - 0426 0080 - 042d 0004 - /* RL82 Pattern Gen Set - * Vertical Gray Scale Color Bar - */ - 060A 00B0 - 060B 00FF - 060C 00FF - 060D 00FF - 0644 0019 - 0645 0020 - 0646 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c5_bu18rl82_in_i2c5_bu18tl82: endpoint { - remote-endpoint = <&i2c5_bu18tl82_out_i2c5_bu18rl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c5_bu18rl82_out_panel0: endpoint { - remote-endpoint = <&panel0_in_i2c5_bu18rl82>; - }; - }; - }; - }; - - ilitek@41 { - compatible = "ilitek,ili251x"; - reg = <0x41>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&touch_gpio_edp0>; - reset-gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_LOW>; - ilitek,name = "ilitek_i2c"; - status = "okay"; - }; - - lt7911d@2b { - compatible = "lontium,lt7911d"; - reg = <0x2b>; - reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_LOW>; - status = "okay"; - }; -}; - -&i2c6 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6m3_xfer>; - clock-frequency = <400000>; - - bu18tl82@10 { - compatible = "rohm,bu18tl82"; - reg = <0x10>; - pinctrl-names = "default"; - pinctrl-0 = <&ser1_rst_pin>; - reset-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; - sel-mipi; - status = "okay"; - serdes-init-sequence = [ - 0013 0019 - 0014 0008 //014h[3]-lane1 enable - 0021 0008 - 0023 0009 - 0024 0009 - 022b 0038 - 022c 0072 - 022d 0023 //VPLL=75MHZS - //022b 00d8 - //022c 0089 - //022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M - 022e 0080 - 027c 0048 - 027d 0048 //i2c addr 0x48 - 0296 0004 - 0297 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane - //0297 000d //CLLTX0_PLL_GAIN 297h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane - 0018 00a5 - 0019 0069 - 0267 003d - 0268 002c - 0269 002c - 026a 002c - 026b 002c - 0367 003d - 0368 002c - 0369 002c - 036a 002c - 036b 002c - 0018 0000 - 0019 0000 - 002a 0018 //gpio0 input lcd_bl_pwm - 002d 0018 //gpio1 input lcd_pwr_en - - 0030 0018 //gpio2 input lcd_rst - 0033 0018 //gpio3 input tp_rst - 0034 0005 //bypass des gpio3 - 0036 0000 //gpio4 output tp_int - 0037 0006 //bypass des gpio4 - - 02a7 0002 - 02a8 0003 - 02a9 0004 - 02aa 0005 - 0045 0080 - 0046 0007 //1920 - 004b 00d0 - 004c 0002 //720 - 004d 00d0 - 004e 0002 //720 - 0051 0080 - 0052 0007 //1920 - 0053 0024 //CLLCH2_EN 53h[5] 0:1 Clock Tx lane/1:2 Clock Tx lanes - 0054 0080 - 024d 0061 - 0252 0005 - 0274 0030 - 0275 0020 - 0396 0004 - 0397 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane - //0397 000d //CLLTX0_PLL_GAIN 397h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane - 0061 0003 //CLLTX0 enable CLLTX1 enable - 0060 0003 //CLLTX0/1 RGB data output Enable - /* TL82 Pattern Gen Set 1 - * Horizontal Gray Scale 256 steps - */ - 040A 0010 - 040B 0080 - 040C 0080 - 040D 0080 - 0444 0090 //h_blank=144 - 0446 00d2 //v_blank=210 - - - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c6_bu18tl82_in_dsi1: endpoint { - remote-endpoint = <&dsi1_out_i2c6_bu18tl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c6_bu18tl82_out_i2c6_bu18rl82: endpoint { - remote-endpoint = <&i2c6_bu18rl82_in_i2c6_bu18tl82>; - }; - }; - }; - }; - - bu18rl82@30 { - compatible = "rohm,bu18rl82"; - reg = <0x30>; - status = "okay"; - serdes-init-sequence = [ - 0011 0003 //Clockless Link Receiver Lane-0+ LVDS portA - 0012 0003 //Clockless Link Receiver Lane-1+ LVDS portB - 0013 0000 - 001d 0008 - 001f 0002 //LVDSTX0_REFSEL - 0020 0002 //LVDSTX1_REFSEL - 0031 0048 - 0032 0048 //i2c addr 0x48 - 0423 0000 - 0424 0000 - 0425 0020 - 0426 0080 - 0057 0000 - 0058 0002 - 0057 0000 //rl gpio0 output lcd_bl_pwm - 0058 0002 //bypass ser gpio0 - 005a 0000 //rl gpio1 output lcd_pwr_en - 005b 0003 //bypass ser gpio1 - 005d 0000 //rl gpio2 output lcd_rst - 005e 0004 //bypass ser gpio2 - 0060 0000 //rl gpio3 output tp-rst - 0061 0005 //bypass ser gpio3 - 0063 0018 //rl gpio4 input tp-int - 0064 0006 //bypass ser gpio4 - 0066 0000 //rl gpio5 output - 0067 0001 //set gpio5 high - - 0073 0080 - 0074 0007 //0x0780 = 1920 - 0075 0080 - 0076 0007 //0x0780 = 1920 - 0079 000a //h[3]: dual lvds mode h[1] single lane / dual lane - 007b 00d0 - 007c 0002 //0x02d0 = 720 - 007d 00d0 - 007e 0002 //0x02d0 = 720 - 0081 0003 //01---> Sync OFF - 0082 0010 //Hsync=16clk - 0084 001c //HBP=28clk - 0086 0002 //Vsync=2lines - 0087 0008 //VBP=8lines - 0088 0000 //VSYNC_CHG=0CLK - 0089 0010 //Hsync = 16? - 008b 001c //HFP=28clk? - 008d 0002 //Vsync=2lines? - 008e 0008 //VFP=8line? - 008f 0000 //VSYNC_CHG=0CLK? - 00d0 0040 //[3]FixHtotalEN - 00d8 00c0 - 00d9 0003 //DE=960 - 0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz - 045d 0001 - 0529 000a //LVDSTX1_PLLGAIN 2'b10: 30 MHz ~ 80 MHz - 055d 0001 - 0091 0003 - 0090 0001 - /* RL82 Pattern Gen Set - * Vertical Gray Scale Color Bar - */ - 060A 00B0 - 060B 00FF - 060C 00FF - 060D 00FF - 0644 0090 - 0646 00d2 - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c6_bu18rl82_in_i2c6_bu18tl82: endpoint { - remote-endpoint = <&i2c6_bu18tl82_out_i2c6_bu18rl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c6_bu18rl82_out_panel1: endpoint { - remote-endpoint = <&panel1_in_i2c6_bu18rl82>; - }; - }; - }; - }; - - himax@48 { - compatible = "himax,hxcommon"; - reg = <0x48>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&touch_gpio_dsi1>; - pinctrl-1 = <&touch_gpio_dsi1>; - himax,location = "himax-touch-dsi1"; - himax,irq-gpio = <&gpio1 RK_PB1 IRQ_TYPE_EDGE_FALLING>; - himax,panel-coords = <0 1920 0 720>; - himax,display-coords = <0 1920 0 720>; - status = "okay"; - }; -}; - -&i2c7 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c7m3_xfer>; - clock-frequency = <400000>; - status = "disabled"; - - bu18tl82@10 { - compatible = "rohm,bu18tl82"; - reg = <0x10>; - status = "okay"; - - serdes-init-sequence = [ - 0013 001a - 0014 000a - 0021 0008 - 0023 0009 - 0024 0009 - 002a 0018 //gpio0 input lcd_bl_pwm - 002d 0018 //gpio1 input lcd_pwr_en - - 0030 0018 //gpio2 input lcd_rst - 0033 0000 //gpio3 output tp_int - 0034 0005 //bypass des gpio3 - 0036 0018 //gpio4 input tp_rst - 0037 0006 //bypass des gpio4 - 027c 0041 - 027d 0041 - 0045 0080 - 0046 0007 - 004b 0038 - 004c 0004 - 0053 0064 - 022b 0062 - 022c 0027 - 022d 002e - 0274 0030 - 0275 0020 - 0296 0004 - 0297 000d - 02b2 00c8 - 02b4 0001 - 02b8 00ff - 02b9 000f - 02ba 00ff - 02bb 000f - 02be 00ff - 02bf 001f - 02c2 00ff - 02c3 001f - 0396 0004 - 0397 000d - 03b2 00c8 - 03b4 0001 - 03b8 00ff - 03b9 000f - 03ba 00ff - 03bb 000f - 03be 00ff - 03bf 001f - 03c2 00ff - 03c3 001f - 0060 0001 - 0061 0003 - 022e 0080 - 032e 0080 - /* TL82 Pattern Gen Set 1 - * Horizontal Gray Scale 256 steps - */ - 040A 0010 - 040B 0080 - 040C 0080 - 040D 0080 - 0444 0019 - 0445 0020 - 0446 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c7_bu18tl82_in_edp1: endpoint { - remote-endpoint = <&edp1_out_i2c7_bu18tl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c7_bu18tl82_out_i2c7_bu18rl82: endpoint { - remote-endpoint = <&i2c7_bu18rl82_in_i2c7_bu18tl82>; - }; - }; - }; - }; - - bu18rl82@30 { - compatible = "rohm,bu18rl82"; - reg = <0x30>; - status = "okay"; - serdes-init-sequence = [ - 0011 000b - 0012 0003 - 0013 0001 - 001d 0008 - 001f 0002 - 0020 0002 - 0031 0041 //i2c addr 0x41 - 0032 0041 //i2c addr 0x41 - 0057 0000 //rl gpio0 output lcd_bl_pwm - 0058 0002 //bypass ser gpio0 - 005a 0000 //rl gpio1 output lcd_pwr_en - 005b 0001 //bypass ser gpio1 - 005d 0000 //rl gpio2 output lcd_rst - 005e 0004 //bypass ser gpio2 - 0060 0018 //rl gpio3 input tp-int - 042e 0005 //bypass ser gpio3 - 0061 0005 //bypass ser gpio3 - 0063 0000 //rl gpio4 output tp-rst - 0064 0006 //bypass ser gpio4 - 0066 0000 //rl gpio5 output - 0067 0007 //bypass ser gpio5 - 0073 0080 - 0074 0007 - 0079 000a - 007b 0038 - 007c 0004 - 0081 0003 - 0082 0010 - 0084 0020 - 0086 0002 - 0087 0002 - 0088 0010 - 0089 0010 - 008b 0020 - 008d 0002 - 008e 0002 - 008f 0010 - 00d0 0040 - 00d8 0042 - 00d9 0004 - 0423 0002 - 0424 00ec - 0425 0027 - 0429 000a - 045d 0001 - 0529 000a - 055d 0003 - 0090 0001 - 0091 0003 - 0426 0080 - 042d 0004 - /* RL82 Pattern Gen Set - * Vertical Gray Scale Color Bar - */ - 060A 00B0 - 060B 00FF - 060C 00FF - 060D 00FF - 0644 0019 - 0645 0020 - 0646 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c7_bu18rl82_in_i2c7_bu18tl82: endpoint { - remote-endpoint = <&i2c7_bu18tl82_out_i2c7_bu18rl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c7_bu18rl82_out_panel1: endpoint { - remote-endpoint = <&panel1_in_i2c7_bu18rl82>; - }; - }; - }; - }; - - lt7911d@2b { - compatible = "lontium,lt7911d"; - reg = <0x2b>; - reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>; - status = "okay"; - }; -}; - -&i2c8 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c8m2_xfer>; - clock-frequency = <400000>; - status = "disabled"; - - bu18tl82@10 { - compatible = "rohm,bu18tl82"; - reg = <0x10>; - status = "okay"; - - serdes-init-sequence = [ - 0013 001a //013h[3]1-lane1 enable 013h[3] 1-LVDS Receiver Port-A - 0014 000a //014h[3]1-lane1 enable 014h[3] 1-LVDS Receiver Port-B - 0021 0008 - 0023 0009 - 0024 0009 - 022b 0038 - 022c 0072 - 022d 0023 //VPLL=75MHZS - //022b 00d8 - //022c 0089 - //022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M - 022e 0080 - 027c 0048 - 027d 0048 //i2c addr 0x48 - 0296 0004 - 0297 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane - //0297 000d //CLLTX0_PLL_GAIN 297h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane - 0018 00a5 - 0019 0069 - 0267 003d - 0268 002c - 0269 002c - 026a 002c - 026b 002c - 0367 003d - 0368 002c - 0369 002c - 036a 002c - 036b 002c - 0018 0000 - 0019 0000 - 002a 0018 //gpio0 input lcd_bl_pwm - 002d 0018 //gpio1 input lcd_pwr_en - - 0030 0018 //gpio2 input lcd_rst - 0033 0018 //gpio3 input tp_rst - 0034 0005 //bypass des gpio3 - 0036 0000 //gpio4 output tp_int - 0037 0006 //bypass des gpio4 - - 02a7 0002 - 02a8 0003 - 02a9 0004 - 02aa 0005 - 0045 0080 - 0046 0007 //1920 - 004b 00d0 - 004c 0002 //720 - 004d 00d0 - 004e 0002 //720 - 0051 0080 - 0052 0007 //1920 - 0053 0064 //0053h[6]1:2 Rx ports CLLCH2_EN 53h[5] 1:2 Clock Tx lanes - 024d 0061 - 0252 0005 - 0274 0030 - 0275 0020 - 0396 0004 - 0397 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane - //0397 000d //CLLTX0_PLL_GAIN 397h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane - 0061 0003 //CLLTX0 enable CLLTX1 enable - 0060 0003 //CLLTX0/1 RGB data output Enable - /* TL82 Pattern Gen Set 1 - * Horizontal Gray Scale 256 steps - */ - 040A 0010 - 040B 0080 - 040C 0080 - 040D 0080 - 0444 0090 //h_blank=144 - 0446 00d2 //v_blank=210 - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c8_bu18tl82_in_dp1: endpoint { - remote-endpoint = <&dp1_out_i2c8_bu18tl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c8_bu18tl82_out_i2c8_bu18rl82: endpoint { - remote-endpoint = <&i2c8_bu18rl82_in_i2c8_bu18tl82>; - }; - }; - }; - }; - - bu18rl82@30 { - compatible = "rohm,bu18rl82"; - reg = <0x30>; - status = "okay"; - serdes-init-sequence = [ - 0011 0003 //Clockless Link Receiver Lane-0+ LVDS portA - 0012 0003 //Clockless Link Receiver Lane-1+ LVDS portB - 0013 0000 - 001d 0008 - 001f 0002 //LVDSTX0_REFSEL - 0020 0002 //LVDSTX1_REFSEL - 0031 0048 - 0032 0048 //i2c addr 0x48 - 0423 0000 - 0424 0000 - 0425 0020 - 0426 0080 - 0057 0000 - 0058 0002 - 0057 0000 //rl gpio0 output lcd_bl_pwm - 0058 0002 //bypass ser gpio0 - 005a 0000 //rl gpio1 output lcd_pwr_en - 005b 0003 //bypass ser gpio1 - 005d 0000 //rl gpio2 output lcd_rst - 005e 0004 //bypass ser gpio2 - 0060 0000 //rl gpio3 output tp-rst - 0061 0005 //bypass ser gpio3 - 0063 0018 //rl gpio4 input tp-int - 0064 0006 //bypass ser gpio4 - 0066 0000 //rl gpio5 output - 0067 0001 //set gpio5 high - - 0073 0080 - 0074 0007 //0x0780 = 1920 - 0075 0080 - 0076 0007 //0x0780 = 1920 - 0079 000a //h[3]: dual lvds mode h[1] single lane / dual lane - 007b 00d0 - 007c 0002 //0x02d0 = 720 - 007d 00d0 - 007e 0002 //0x02d0 = 720 - 0081 0003 //01---> Sync OFF - 0082 0010 //Hsync=16clk - 0084 001c //HBP=28clk - 0086 0002 //Vsync=2lines - 0087 0008 //VBP=8lines - 0088 0000 //VSYNC_CHG=0CLK - 0089 0010 //Hsync = 16? - 008b 001c //HFP=28clk? - 008d 0002 //Vsync=2lines? - 008e 0008 //VFP=8line? - 008f 0000 //VSYNC_CHG=0CLK? - 00d0 0040 //[3]FixHtotalEN - 00d8 00c0 - 00d9 0003 //DE=960 - 0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz - 045d 0001 - 0529 000a //LVDSTX1_PLLGAIN 2'b10: 30 MHz ~ 80 MHz - 055d 0001 - 0091 0003 - 0090 0001 - /* RL82 Pattern Gen Set - * Vertical Gray Scale Color Bar - */ - 060A 00B0 - 060B 00FF - 060C 00FF - 060D 00FF - 0644 0090 - 0646 00d2 - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c8_bu18rl82_in_i2c8_bu18tl82: endpoint { - remote-endpoint = <&i2c8_bu18tl82_out_i2c8_bu18rl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c8_bu18rl82_out_panel1: endpoint { - remote-endpoint = <&panel1_in_i2c8_bu18rl82>; - }; - }; - }; - }; - - lt7911d@2b { - compatible = "lontium,lt7911d"; - reg = <0x2b>; - reset-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; - status = "okay"; - }; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&mipi_dcphy1 { - status = "okay"; -}; - - -&pinctrl { - - bl { - bl0_enable_pin: bl0-enable-pin { - rockchip,pins = - <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, - <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, - <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - - }; - - bl1_enable_pin: bl1-enable-pin { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bl2_enable_pin: bl2-enable-pin { - rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bl3_enable_pin: bl3-enable-pin { - rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bl4_enable_pin: bl4-enable-pin { - rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bl5_enable_pin: bl5-enable-pin { - rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - serdes { - //dsi0 - ser0_rst_pin: ser0-rst-pin { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - //dsi1 - ser1_rst_pin: ser1-rst-pin { - rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - touch { - //dsi0-i2c2 - touch_gpio_dsi0: touch-gpio-dsi0 { - rockchip,pins = - //<1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, //INT - <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; //RST - }; - //dsi1-i2c6 - touch_gpio_dsi1: touch-gpio-dsi1 { - rockchip,pins = - <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>, //INT - <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; //RST - }; - //dp0-i2c4 - touch_gpio_dp0: touch-gpio-dp0 { - rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - //edp0-i2c5 - touch_gpio_edp0: touch-gpio-edp0 { - rockchip,pins = - <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>, //INT - <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; //RST - }; - }; -}; - -/* dsi0->serdes->lvds_panel */ -&pwm0 { - status = "okay"; - pinctrl-0 = <&pwm0m2_pins>; -}; - -/* dp0->serdes->lvds_panel */ -&pwm10 { - pinctrl-0 = <&pwm10m2_pins>; - status = "okay"; -}; - -/* edp1->serdes->lvds_panel */ -&pwm11 { - pinctrl-0 = <&pwm11m3_pins>; - status = "okay"; -}; - -/* edp0->serdes->lvds_panel */ -&pwm7 { - pinctrl-0 = <&pwm7m0_pins>; - status = "okay"; -}; - -/* dsi1->serdes->lvds_panel */ -&pwm13 { - status = "okay"; - pinctrl-0 = <&pwm13m1_pins>; -}; - -/* dp1->serdes->lvds_panel */ -&pwm14 { - pinctrl-0 = <&pwm14m0_pins>; - status = "okay"; -}; - -&route_dp0 { - status = "disabled"; - connect = <&vp0_out_dp0>; - logo,uboot = "logo34.bmp"; - logo,kernel = "logo34.bmp"; -}; - -&route_dp1 { - status = "disabled"; - connect = <&vp0_out_dp1>; - logo,uboot = "logo34.bmp"; - logo,kernel = "logo34.bmp"; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp2_out_dsi0>; - logo,uboot = "logo1.bmp"; - logo,kernel = "logo1.bmp"; -}; - -&route_dsi1 { - status = "okay"; - connect = <&vp3_out_dsi1>; - logo,uboot = "logo2.bmp"; - logo,kernel = "logo2.bmp"; -}; - -&route_edp0 { - status = "disabled"; - connect = <&vp1_out_edp0>; - logo,uboot = "logo56.bmp"; - logo,kernel = "logo56.bmp"; -}; - -&route_edp1 { - status = "disabled"; - connect = <&vp1_out_edp1>; - logo,uboot = "logo56.bmp"; - logo,kernel = "logo56.bmp"; -}; - -&usbdp_phy0 { - rockchip,dp-lane-mux = <0 1 2 3>; - status = "okay"; -}; - -&usbdp_phy1 { - rockchip,dp-lane-mux = <0 1 2 3>; - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru PLL_V0PLL>; - assigned-clock-rates = <1152000000>; -}; - -&vp0 { - assigned-clocks = <&cru DCLK_VOP0_SRC>; - assigned-clock-parents = <&cru PLL_V0PLL>; -}; - -&vp1 { - assigned-clocks = <&cru DCLK_VOP1_SRC>; - assigned-clock-parents = <&cru PLL_GPLL>; -}; - -&vp2 { - assigned-clocks = <&cru DCLK_VOP2_SRC>; - assigned-clock-parents = <&cru PLL_V0PLL>; -}; - -&vp3 { - assigned-clocks = <&cru DCLK_VOP3>; - assigned-clock-parents = <&cru PLL_V0PLL>; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display.dtsi deleted file mode 100644 index 7ee1d48a6..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-serdes-display.dtsi +++ /dev/null @@ -1,1943 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Rockchip Electronics Co., Ltd. - * - */ - -/ { - lt7911d { - compatible = "lontium,lt7911d-fb-notifier"; - reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>, - <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>, - <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>, - <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; - }; - - dsi2lvds_backlight1: dsi2lvds_backlight1 { - compatible = "pwm-backlight"; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - dp2lvds_backlight0: dp2lvds_backlight0 { - compatible = "pwm-backlight"; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - dp2lvds_backlight1: dp2lvds_backlight1 { - compatible = "pwm-backlight"; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - edp2lvds_backlight0: edp2lvds_backlight0 { - compatible = "pwm-backlight"; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - edp2lvds_backlight1: edp2lvds_backlight1 { - compatible = "pwm-backlight"; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - dsi2lvds_panel0 { - compatible = "simple-panel"; - backlight = <&backlight>; - - display-timings { - native-mode = <&dsi2lvds0>; - dsi2lvds0: timing0 { - clock-frequency = <88208000>; - hactive = <1920>; - vactive = <720>; - hfront-porch = <32>; - hsync-len = <10>; - hback-porch = <22>; - vfront-porch = <10>; - vsync-len = <4>; - vback-porch = <7>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - panel0_in_i2c2_bu18rl82: endpoint { - remote-endpoint = <&i2c2_bu18rl82_out_panel0>; - }; - }; - }; - }; - - dsi2lvds_panel1 { - compatible = "simple-panel"; - backlight = <&dsi2lvds_backlight1>; - - display-timings { - native-mode = <&dsi2lvds1>; - dsi2lvds1: timing0 { - clock-frequency = <88208000>; - hactive = <1920>; - vactive = <720>; - hfront-porch = <32>; - hsync-len = <10>; - hback-porch = <22>; - vfront-porch = <10>; - vsync-len = <4>; - vback-porch = <7>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - panel1_in_i2c6_bu18rl82: endpoint { - remote-endpoint = <&i2c6_bu18rl82_out_panel1>; - }; - }; - }; - }; - - dp2lvds_panel0 { - compatible = "simple-panel"; - backlight = <&dp2lvds_backlight0>; - status = "okay"; - - panel-timing { - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <140>; - hsync-len = <40>; - hback-porch = <100>; - vfront-porch = <15>; - vsync-len = <20>; - vback-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - panel0_in_i2c3_bu18rl82: endpoint { - remote-endpoint = <&i2c3_bu18rl82_out_panel0>; - }; - }; - }; - - dp2lvds_panel1 { - compatible = "simple-panel"; - backlight = <&dp2lvds_backlight1>; - status = "okay"; - - panel-timing { - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <140>; - hsync-len = <40>; - hback-porch = <100>; - vfront-porch = <15>; - vsync-len = <20>; - vback-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - panel1_in_i2c8_bu18rl82: endpoint { - remote-endpoint = <&i2c8_bu18rl82_out_panel1>; - }; - }; - }; - - edp2lvds_panel0 { - compatible = "simple-panel"; - backlight = <&edp2lvds_backlight0>; - status = "okay"; - - panel-timing { - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <140>; - hsync-len = <40>; - hback-porch = <100>; - vfront-porch = <15>; - vsync-len = <20>; - vback-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - panel0_in_i2c5_bu18rl82: endpoint { - remote-endpoint = <&i2c5_bu18rl82_out_panel0>; - }; - }; - }; - - edp2lvds_panel1 { - compatible = "simple-panel"; - backlight = <&edp2lvds_backlight1>; - status = "okay"; - - panel-timing { - clock-frequency = <148500000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <140>; - hsync-len = <40>; - hback-porch = <100>; - vfront-porch = <15>; - vsync-len = <20>; - vback-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - panel1_in_i2c7_bu18rl82: endpoint { - remote-endpoint = <&i2c7_bu18rl82_out_panel1>; - }; - }; - }; -}; - -&backlight { - pwms = <&pwm6 0 25000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&bl0_enable_pin>; - enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&dsi2lvds_backlight1 { - pwms = <&pwm13 0 25000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&bl1_enable_pin>; - enable-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&dp0 { - split-mode; - force-hpd; - status = "okay"; - - ports { - port@1 { - reg = <1>; - - dp0_out_i2c3_bu18tl82: endpoint { - remote-endpoint = <&i2c3_bu18tl82_in_dp0>; - }; - }; - }; -}; - -&dp0_in_vp0 { - status = "okay"; -}; - -&dp0_in_vp1 { - status = "disabled"; -}; - -&dp0_in_vp2 { - status = "disabled"; -}; - -&dp1 { - force-hpd; - status = "okay"; - - ports { - port@1 { - reg = <1>; - - dp1_out_i2c8_bu18tl82: endpoint { - remote-endpoint = <&i2c8_bu18tl82_in_dp1>; - }; - }; - }; -}; - -&dp1_in_vp0 { - status = "okay"; -}; - -&dp1_in_vp1 { - status = "disabled"; -}; - -&dp1_in_vp2 { - status = "disabled"; -}; - -&dp2lvds_backlight0 { - pwms = <&pwm10 0 25000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&bl2_enable_pin>; - enable-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&dp2lvds_backlight1 { - pwms = <&pwm14 0 25000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&bl3_enable_pin>; - enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -/* - * mipi_dcphy0 needs to be enabled - * when dsi0 is enabled - */ -&dsi0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - dsi0_out_i2c2_bu18tl82: endpoint { - remote-endpoint = <&i2c2_bu18tl82_in_dsi0>; - }; - }; - }; -}; - -&dsi0_in_vp2 { - status = "okay"; -}; - -&dsi0_in_vp3 { - status = "disabled"; -}; - -/* - * mipi_dcphy1 needs to be enabled - * when dsi1 is enabled - */ -&dsi1 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - dsi1_out_i2c6_bu18tl82: endpoint { - remote-endpoint = <&i2c6_bu18tl82_in_dsi1>; - }; - }; - }; -}; - -&dsi1_in_vp2 { - status = "disabled"; -}; - -&dsi1_in_vp3 { - status = "okay"; -}; - -&edp0 { - split-mode; - force-hpd; - status = "okay"; - - ports { - port@1 { - reg = <1>; - - edp0_out_i2c5_bu18tl82: endpoint { - remote-endpoint = <&i2c5_bu18tl82_in_edp0>; - }; - }; - }; -}; - -&edp0_in_vp0 { - status = "disabled"; -}; - -&edp0_in_vp1 { - status = "okay"; -}; - -&edp0_in_vp2 { - status = "disabled"; -}; - -&edp1 { - force-hpd; - status = "okay"; - - ports { - port@1 { - reg = <1>; - - edp1_out_i2c7_bu18tl82: endpoint { - remote-endpoint = <&i2c7_bu18tl82_in_edp1>; - }; - }; - }; -}; - -&edp1_in_vp0 { - status = "disabled"; -}; - -&edp1_in_vp1 { - status = "okay"; -}; - -&edp1_in_vp2 { - status = "disabled"; -}; - -&edp2lvds_backlight0 { - pwms = <&pwm12 0 25000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&bl4_enable_pin>; - enable-gpios = <&gpio4 RK_PB7 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&edp2lvds_backlight1 { - pwms = <&pwm11 0 25000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&bl5_enable_pin>; - enable-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi0 { - status = "disabled"; -}; - -&hdmi1 { - status = "disabled"; -}; - -&hdptxphy0 { - status = "okay"; -}; - -&hdptxphy1 { - status = "okay"; -}; - -&hdptxphy_hdmi0 { - status = "disabled"; -}; - -&hdptxphy_hdmi1 { - status = "disabled"; -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2m4_xfer>; - clock-frequency = <400000>; - - bu18tl82: bu18tl82@10 { - compatible = "rohm,bu18tl82"; - reg = <0x10>; - pinctrl-names = "default"; - pinctrl-0 = <&ser0_rst_pin>; - reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; - sel-mipi; - status = "okay"; - - serdes-init-sequence = [ - 0021 0008 - 0022 0008 - 0023 0009 - 0024 000a - 0013 0010 - 0014 0010 - 002a 0018 - 002d 0018 - 0030 0018 - 0033 0018 - 02a7 0002 - 02a8 0003 - 02a9 0004 - 02aa 0005 - 0045 0080 - 0046 0007 - 0047 0080 - 0048 0007 - 004b 00d0 - 004c 0002 - 004d 00d0 - 004e 0002 - 0051 0080 - 0052 0007 - 0053 0000 - 0054 00c0 - 022b 0076 - 022c 0062 - 022d 0037 - 024d 0061 - 0252 0005 - 0253 0000 - 0258 0000 - 025c 0000 - 025f 0000 - 0274 0030 - 0275 0020 - 032b 002f - 032c 00a1 - 032d 001d - 034d 0060 - 0353 0000 - 0358 0000 - 035c 0000 - 035f 0000 - 0018 00a5 - 0019 0069 - 0267 003d - 0268 002c - 0269 002c - 026a 002c - 026b 002c - 0367 003d - 0368 002c - 0369 002c - 036a 002c - 036b 002c - 0013 0019 - 0014 0001 - 022e 0080 - 0296 0004 - 0297 000d - 032e 0080 - 038e 0000 - 0396 0004 - 0397 000a - 0060 0001 - 0061 0001 - 0018 0000 - 0019 0000 - /* TL82 Pattern Gen Set 1 - * Horizontal Gray Scale 256 steps - */ - 040A 0010 - 040B 0080 - 040C 0080 - 040D 0080 - 0444 0019 - 0445 0020 - 0446 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c2_bu18tl82_in_dsi0: endpoint { - remote-endpoint = <&dsi0_out_i2c2_bu18tl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c2_bu18tl82_out_i2c2_bu18rl82: endpoint { - remote-endpoint = <&i2c2_bu18rl82_in_i2c2_bu18tl82>; - }; - }; - }; - }; - - bu18rl82: bu18rl82@30 { - compatible = "rohm,bu18rl82"; - reg = <0x30>; - status = "okay"; - serdes-init-sequence = [ - 0011 000b - 0012 0002 - 0013 0001 - 001d 0008 - 001f 0006 - 0020 0006 - 0057 0000 - 0058 0002 - 005a 0000 - 005b 0003 - 005d 0000 - 005e 0001 - 0060 0000 - 0061 0005 - 0073 0080 - 0074 0007 - 0075 0080 - 0076 0007 - 0079 0009 - 007b 00d0 - 007c 0002 - 007d 00d0 - 007e 0002 - 0081 0003 - 0082 000a - 0084 001e - 0086 0001 - 0087 0003 - 0088 0005 - 0089 0014 - 008b 0028 - 008d 0002 - 008e 0004 - 008f 000f - 0090 0001 - 0091 0003 - 0423 00ab - 0424 00aa - 0425 001a - 0429 000a - 045d 0001 - 0523 0097 - 0524 00d0 - 0525 000e - 0529 000a - 055d 0001 - 0426 0080 - 0526 0080 - /* RL82 Pattern Gen Set - * Vertical Gray Scale Color Bar - */ - 060A 00B0 - 060B 00FF - 060C 00FF - 060D 00FF - 0644 0019 - 0645 0020 - 0646 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c2_bu18rl82_in_i2c2_bu18tl82: endpoint { - remote-endpoint = <&i2c2_bu18tl82_out_i2c2_bu18rl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c2_bu18rl82_out_panel0: endpoint { - remote-endpoint = <&panel0_in_i2c2_bu18rl82>; - }; - }; - }; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3m2_xfer>; - clock-frequency = <400000>; - status = "okay"; - - bu18tl82@10 { - compatible = "rohm,bu18tl82"; - reg = <0x10>; - status = "okay"; - - serdes-init-sequence = [ - 0013 001a - 0014 000a - 0021 0008 - 0023 0009 - 0024 0009 - 002a 0018 - 002d 0018 - 0030 0018 - 0033 0018 - 0045 0080 - 0046 0007 - 004b 0038 - 004c 0004 - 0053 0064 - 022b 0062 - 022c 0027 - 022d 002e - 0274 0030 - 0275 0020 - 0296 0004 - 0297 000d - 02b2 00c8 - 02b4 0001 - 02b8 00ff - 02b9 000f - 02ba 00ff - 02bb 000f - 02be 00ff - 02bf 001f - 02c2 00ff - 02c3 001f - 0396 0004 - 0397 000d - 03b2 00c8 - 03b4 0001 - 03b8 00ff - 03b9 000f - 03ba 00ff - 03bb 000f - 03be 00ff - 03bf 001f - 03c2 00ff - 03c3 001f - 0060 0001 - 0061 0003 - 022e 0080 - 032e 0080 - /* TL82 Pattern Gen Set 1 - * Horizontal Gray Scale 256 steps - */ - 040A 0010 - 040B 0080 - 040C 0080 - 040D 0080 - 0444 0019 - 0445 0020 - 0446 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c3_bu18tl82_in_dp0: endpoint { - remote-endpoint = <&dp0_out_i2c3_bu18tl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c3_bu18tl82_out_i2c3_bu18rl82: endpoint { - remote-endpoint = <&i2c3_bu18rl82_in_i2c3_bu18tl82>; - }; - }; - }; - }; - - bu18rl82@30 { - compatible = "rohm,bu18rl82"; - reg = <0x30>; - status = "okay"; - serdes-init-sequence = [ - 0011 000b - 0012 0003 - 0013 0001 - 001d 0008 - 001f 0002 - 0020 0002 - 0057 0000 - 0058 0002 - 005a 0000 - 005b 0003 - 005d 0000 - 005e 0004 - 0060 0000 - 0061 0005 - 0073 0080 - 0074 0007 - 0079 000a - 007b 0038 - 007c 0004 - 0081 0003 - 0082 0010 - 0084 0020 - 0086 0002 - 0087 0002 - 0088 0010 - 0089 0010 - 008b 0020 - 008d 0002 - 008e 0002 - 008f 0010 - 00d0 0040 - 00d8 0042 - 00d9 0004 - 0423 0002 - 0424 00ec - 0425 0027 - 0429 000a - 045d 0001 - 0529 000a - 055d 0003 - 0090 0001 - 0091 0003 - 0426 0080 - /* RL82 Pattern Gen Set - * Vertical Gray Scale Color Bar - */ - 060A 00B0 - 060B 00FF - 060C 00FF - 060D 00FF - 0644 0019 - 0645 0020 - 0646 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c3_bu18rl82_in_i2c3_bu18tl82: endpoint { - remote-endpoint = <&i2c3_bu18tl82_out_i2c3_bu18rl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c3_bu18rl82_out_panel0: endpoint { - remote-endpoint = <&panel0_in_i2c3_bu18rl82>; - }; - }; - }; - }; -}; - -&i2c5 { - clock-frequency = <400000>; - status = "okay"; - - bu18tl82@10 { - compatible = "rohm,bu18tl82"; - reg = <0x10>; - status = "okay"; - - serdes-init-sequence = [ - 0013 001a - 0014 000a - 0021 0008 - 0023 0009 - 0024 0009 - 002a 0018 - 002e 0004 - 002d 0018 - 0030 0000 - 0033 0018 - 027c 0041 - 027d 0041 - 0045 0080 - 0046 0007 - 004b 0038 - 004c 0004 - 0053 0064 - 022b 0062 - 022c 0027 - 022d 002e - 0274 0030 - 0275 0020 - 0296 0004 - 0297 000d - 02b2 00c8 - 02b4 0001 - 02b8 00ff - 02b9 000f - 02ba 00ff - 02bb 000f - 02be 00ff - 02bf 001f - 02c2 00ff - 02c3 001f - 0396 0004 - 0397 000d - 03b2 00c8 - 03b4 0001 - 03b8 00ff - 03b9 000f - 03ba 00ff - 03bb 000f - 03be 00ff - 03bf 001f - 03c2 00ff - 03c3 001f - 0060 0001 - 0061 0003 - 022e 0080 - 032e 0080 - /* TL82 Pattern Gen Set 1 - * Horizontal Gray Scale 256 steps - */ - 040A 0010 - 040B 0080 - 040C 0080 - 040D 0080 - 0444 0019 - 0445 0020 - 0446 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c5_bu18tl82_in_edp0: endpoint { - remote-endpoint = <&edp0_out_i2c5_bu18tl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c5_bu18tl82_out_i2c5_bu18rl82: endpoint { - remote-endpoint = <&i2c5_bu18rl82_in_i2c5_bu18tl82>; - }; - }; - }; - }; - - bu18rl82@30 { - compatible = "rohm,bu18rl82"; - reg = <0x30>; - status = "okay"; - serdes-init-sequence = [ - 0011 000b - 0012 0003 - 0013 0001 - 001d 0008 - 001f 0002 - 0020 0002 - 0031 0041 - 0032 0041 - 0057 0000 - 0058 0002 - 005a 0000 - 005b 0003 - 005d 0008 - 005e 0004 - 0060 0000 - 0061 0005 - 0073 0080 - 0074 0007 - 0079 000a - 007b 0038 - 007c 0004 - 0081 0003 - 0082 0010 - 0084 0020 - 0086 0002 - 0087 0002 - 0088 0010 - 0089 0010 - 008b 0020 - 008d 0002 - 008e 0002 - 008f 0010 - 00d0 0040 - 00d8 0042 - 00d9 0004 - 0423 0002 - 0424 00ec - 0425 0027 - 0429 000a - 045d 0001 - 0529 000a - 055d 0003 - 0090 0001 - 0091 0003 - 0426 0080 - 042d 0004 - /* RL82 Pattern Gen Set - * Vertical Gray Scale Color Bar - */ - 060A 00B0 - 060B 00FF - 060C 00FF - 060D 00FF - 0644 0019 - 0645 0020 - 0646 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c5_bu18rl82_in_i2c5_bu18tl82: endpoint { - remote-endpoint = <&i2c5_bu18tl82_out_i2c5_bu18rl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c5_bu18rl82_out_panel0: endpoint { - remote-endpoint = <&panel0_in_i2c5_bu18rl82>; - }; - }; - }; - }; - - ilitek@41 { - compatible = "ilitek,ili251x"; - reg = <0x41>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&touch_pin>; - reset-gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; - ilitek,name = "ilitek_i2c"; - }; -}; - -&i2c6 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6m3_xfer>; - clock-frequency = <400000>; - - bu18tl82@10 { - compatible = "rohm,bu18tl82"; - reg = <0x10>; - pinctrl-names = "default"; - pinctrl-0 = <&ser1_rst_pin>; - reset-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; - sel-mipi; - status = "okay"; - serdes-init-sequence = [ - 0021 0008 - 0022 0008 - 0023 0009 - 0024 000a - 0013 0010 - 0014 0010 - 002a 0018 - 002d 0018 - 0030 0018 - 0033 0018 - 027c 0070 - 027d 0070 - 02a7 0002 - 02a8 0003 - 02a9 0004 - 02aa 0005 - 0045 0080 - 0046 0007 - 0047 0080 - 0048 0007 - 004b 00d0 - 004c 0002 - 004d 00d0 - 004e 0002 - 0051 0080 - 0052 0007 - 0053 0000 - 0054 00c0 - 022b 0076 - 022c 0062 - 022d 0037 - 024d 0061 - 0252 0005 - 0253 0000 - 0258 0000 - 025c 0000 - 025f 0000 - 0274 0030 - 0275 0020 - 032b 002f - 032c 00a1 - 032d 001d - 034d 0060 - 0353 0000 - 0358 0000 - 035c 0000 - 035f 0000 - 0018 00a5 - 0019 0069 - 0267 003d - 0268 002c - 0269 002c - 026a 002c - 026b 002c - 0367 003d - 0368 002c - 0369 002c - 036a 002c - 036b 002c - 0013 0019 - 0014 0001 - 022e 0080 - 0296 0004 - 0297 000d - 032e 0080 - 038e 0000 - 0396 0004 - 0397 000a - 0060 0001 - 0061 0001 - 0018 0000 - 0019 0000 - /* TL82 Pattern Gen Set 1 - * Horizontal Gray Scale 256 steps - */ - 040A 0010 - 040B 0080 - 040C 0080 - 040D 0080 - 0444 0019 - 0445 0020 - 0446 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c6_bu18tl82_in_dsi1: endpoint { - remote-endpoint = <&dsi1_out_i2c6_bu18tl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c6_bu18tl82_out_i2c6_bu18rl82: endpoint { - remote-endpoint = <&i2c6_bu18rl82_in_i2c6_bu18tl82>; - }; - }; - }; - }; - - bu18rl82@30 { - compatible = "rohm,bu18rl82"; - reg = <0x30>; - status = "okay"; - serdes-init-sequence = [ - 0011 000b - 0012 0002 - 0013 0001 - 001d 0008 - 001f 0006 - 0020 0006 - 0031 0070 - 0032 0038 - 0057 0000 - 0058 0002 - 005a 0000 - 005b 0003 - 005d 0000 - 005e 0001 - 0060 0000 - 0061 0005 - 0073 0080 - 0074 0007 - 0075 0080 - 0076 0007 - 0079 0009 - 007b 00d0 - 007c 0002 - 007d 00d0 - 007e 0002 - 0081 0003 - 0082 000a - 0084 001e - 0086 0001 - 0087 0003 - 0088 0005 - 0089 0014 - 008b 0028 - 008d 0002 - 008e 0004 - 008f 000f - 0090 0001 - 0091 0003 - 0423 00ab - 0424 00aa - 0425 001a - 0429 000a - 045d 0001 - 0523 0097 - 0524 00d0 - 0525 000e - 0529 000a - 055d 0001 - 0426 0080 - 0526 0080 - /* RL82 Pattern Gen Set - * Vertical Gray Scale Color Bar - */ - 060A 00B0 - 060B 00FF - 060C 00FF - 060D 00FF - 0644 0019 - 0645 0020 - 0646 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c6_bu18rl82_in_i2c6_bu18tl82: endpoint { - remote-endpoint = <&i2c6_bu18tl82_out_i2c6_bu18rl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c6_bu18rl82_out_panel1: endpoint { - remote-endpoint = <&panel1_in_i2c6_bu18rl82>; - }; - }; - }; - }; -}; - -&i2c7 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c7m3_xfer>; - clock-frequency = <400000>; - status = "okay"; - - bu18tl82@10 { - compatible = "rohm,bu18tl82"; - reg = <0x10>; - status = "okay"; - - serdes-init-sequence = [ - 0013 001a - 0014 000a - 0021 0008 - 0023 0009 - 0024 0009 - 002a 0018 - 002d 0018 - 0030 0018 - 0033 0018 - 0045 0080 - 0046 0007 - 004b 0038 - 004c 0004 - 0053 0064 - 022b 0062 - 022c 0027 - 022d 002e - 0274 0030 - 0275 0020 - 0296 0004 - 0297 000d - 02b2 00c8 - 02b4 0001 - 02b8 00ff - 02b9 000f - 02ba 00ff - 02bb 000f - 02be 00ff - 02bf 001f - 02c2 00ff - 02c3 001f - 0396 0004 - 0397 000d - 03b2 00c8 - 03b4 0001 - 03b8 00ff - 03b9 000f - 03ba 00ff - 03bb 000f - 03be 00ff - 03bf 001f - 03c2 00ff - 03c3 001f - 0060 0001 - 0061 0003 - 022e 0080 - 032e 0080 - /* TL82 Pattern Gen Set 1 - * Horizontal Gray Scale 256 steps - */ - 040A 0010 - 040B 0080 - 040C 0080 - 040D 0080 - 0444 0019 - 0445 0020 - 0446 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c7_bu18tl82_in_edp1: endpoint { - remote-endpoint = <&edp1_out_i2c7_bu18tl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c7_bu18tl82_out_i2c7_bu18rl82: endpoint { - remote-endpoint = <&i2c7_bu18rl82_in_i2c7_bu18tl82>; - }; - }; - }; - }; - - bu18rl82@30 { - compatible = "rohm,bu18rl82"; - reg = <0x30>; - status = "okay"; - serdes-init-sequence = [ - 0011 000b - 0012 0003 - 0013 0001 - 001d 0008 - 001f 0002 - 0020 0002 - 0057 0000 - 0058 0002 - 005a 0000 - 005b 0003 - 005d 0000 - 005e 0004 - 0060 0000 - 0061 0005 - 0073 0080 - 0074 0007 - 0079 000a - 007b 0038 - 007c 0004 - 0081 0003 - 0082 0010 - 0084 0020 - 0086 0002 - 0087 0002 - 0088 0010 - 0089 0010 - 008b 0020 - 008d 0002 - 008e 0002 - 008f 0010 - 00d0 0040 - 00d8 0042 - 00d9 0004 - 0423 0002 - 0424 00ec - 0425 0027 - 0429 000a - 045d 0001 - 0529 000a - 055d 0003 - 0090 0001 - 0091 0003 - 0426 0080 - /* RL82 Pattern Gen Set - * Vertical Gray Scale Color Bar - */ - 060A 00B0 - 060B 00FF - 060C 00FF - 060D 00FF - 0644 0019 - 0645 0020 - 0646 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c7_bu18rl82_in_i2c7_bu18tl82: endpoint { - remote-endpoint = <&i2c7_bu18tl82_out_i2c7_bu18rl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c7_bu18rl82_out_panel1: endpoint { - remote-endpoint = <&panel1_in_i2c7_bu18rl82>; - }; - }; - }; - }; -}; - -&i2c8 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c8m2_xfer>; - clock-frequency = <400000>; - status = "okay"; - - bu18tl82@10 { - compatible = "rohm,bu18tl82"; - reg = <0x10>; - status = "okay"; - - serdes-init-sequence = [ - 0013 001a - 0014 000a - 0021 0008 - 0023 0009 - 0024 0009 - 002a 0018 - 002d 0018 - 0030 0018 - 0033 0018 - 0045 0080 - 0046 0007 - 004b 0038 - 004c 0004 - 0053 0064 - 022b 0062 - 022c 0027 - 022d 002e - 0274 0030 - 0275 0020 - 0296 0004 - 0297 000d - 02b2 00c8 - 02b4 0001 - 02b8 00ff - 02b9 000f - 02ba 00ff - 02bb 000f - 02be 00ff - 02bf 001f - 02c2 00ff - 02c3 001f - 0396 0004 - 0397 000d - 03b2 00c8 - 03b4 0001 - 03b8 00ff - 03b9 000f - 03ba 00ff - 03bb 000f - 03be 00ff - 03bf 001f - 03c2 00ff - 03c3 001f - 0060 0001 - 0061 0003 - 022e 0080 - 032e 0080 - /* TL82 Pattern Gen Set 1 - * Horizontal Gray Scale 256 steps - */ - 040A 0010 - 040B 0080 - 040C 0080 - 040D 0080 - 0444 0019 - 0445 0020 - 0446 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c8_bu18tl82_in_dp1: endpoint { - remote-endpoint = <&dp1_out_i2c8_bu18tl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c8_bu18tl82_out_i2c8_bu18rl82: endpoint { - remote-endpoint = <&i2c8_bu18rl82_in_i2c8_bu18tl82>; - }; - }; - }; - }; - - bu18rl82@30 { - compatible = "rohm,bu18rl82"; - reg = <0x30>; - status = "okay"; - serdes-init-sequence = [ - 0011 000b - 0012 0003 - 0013 0001 - 001d 0008 - 001f 0002 - 0020 0002 - 0057 0000 - 0058 0002 - 005a 0000 - 005b 0003 - 005d 0000 - 005e 0004 - 0060 0000 - 0061 0005 - 0073 0080 - 0074 0007 - 0079 000a - 007b 0038 - 007c 0004 - 0081 0003 - 0082 0010 - 0084 0020 - 0086 0002 - 0087 0002 - 0088 0010 - 0089 0010 - 008b 0020 - 008d 0002 - 008e 0002 - 008f 0010 - 00d0 0040 - 00d8 0042 - 00d9 0004 - 0423 0002 - 0424 00ec - 0425 0027 - 0429 000a - 045d 0001 - 0529 000a - 055d 0003 - 0090 0001 - 0091 0003 - 0426 0080 - /* RL82 Pattern Gen Set - * Vertical Gray Scale Color Bar - */ - 060A 00B0 - 060B 00FF - 060C 00FF - 060D 00FF - 0644 0019 - 0645 0020 - 0646 001f - ]; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2c8_bu18rl82_in_i2c8_bu18tl82: endpoint { - remote-endpoint = <&i2c8_bu18tl82_out_i2c8_bu18rl82>; - }; - }; - - port@1 { - reg = <1>; - - i2c8_bu18rl82_out_panel1: endpoint { - remote-endpoint = <&panel1_in_i2c8_bu18rl82>; - }; - }; - }; - }; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&mipi_dcphy1 { - status = "okay"; -}; - - -&pinctrl { - - bl { - bl0_enable_pin: bl0-enable-pin { - rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bl1_enable_pin: bl1-enable-pin { - rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bl2_enable_pin: bl2-enable-pin { - rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bl3_enable_pin: bl3-enable-pin { - rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bl4_enable_pin: bl4-enable-pin { - rockchip,pins = <4 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bl5_enable_pin: bl5-enable-pin { - rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - serdes { - //dsi0 - ser0_rst_pin: ser0-rst-pin { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - //dsi1 - ser1_rst_pin: ser1-rst-pin { - rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - touch { - touch_pin: touch-pin { - rockchip,pins = - <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, //INT - <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; //RST - }; - }; -}; - -/* dsi0->serdes->lvds_panel */ -&pwm6 { - status = "okay"; - pinctrl-0 = <&pwm6m1_pins>; -}; - -/* dp0->serdes->lvds_panel */ -&pwm10 { - pinctrl-0 = <&pwm10m2_pins>; - status = "okay"; -}; - -/* edp1->serdes->lvds_panel */ -&pwm11 { - pinctrl-0 = <&pwm11m3_pins>; - status = "okay"; -}; - -/* edp0->serdes->lvds_panel */ -&pwm12 { - pinctrl-0 = <&pwm12m1_pins>; - status = "okay"; -}; - -/* dsi1->serdes->lvds_panel */ -&pwm13 { - status = "okay"; - pinctrl-0 = <&pwm13m1_pins>; -}; - -/* dp1->serdes->lvds_panel */ -&pwm14 { - pinctrl-0 = <&pwm14m0_pins>; - status = "okay"; -}; - -&route_dp0 { - status = "disabled"; - connect = <&vp0_out_dp0>; - logo,uboot = "logo34.bmp"; - logo,kernel = "logo34.bmp"; -}; - -&route_dp1 { - status = "disabled"; - connect = <&vp0_out_dp1>; - logo,uboot = "logo34.bmp"; - logo,kernel = "logo34.bmp"; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp2_out_dsi0>; - logo,uboot = "logo1.bmp"; - logo,kernel = "logo1.bmp"; -}; - -&route_dsi1 { - status = "okay"; - connect = <&vp3_out_dsi1>; - logo,uboot = "logo2.bmp"; - logo,kernel = "logo2.bmp"; -}; - -&route_edp0 { - status = "disabled"; - connect = <&vp1_out_edp0>; - logo,uboot = "logo56.bmp"; - logo,kernel = "logo56.bmp"; -}; - -&route_edp1 { - status = "disabled"; - connect = <&vp1_out_edp1>; - logo,uboot = "logo56.bmp"; - logo,kernel = "logo56.bmp"; -}; - -&usbdp_phy0 { - rockchip,dp-lane-mux = <0 1 2 3>; - status = "okay"; -}; - -&usbdp_phy1 { - rockchip,dp-lane-mux = <0 1 2 3>; - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru PLL_V0PLL>; - assigned-clock-rates = <1152000000>; -}; - -&vp0 { - assigned-clocks = <&cru DCLK_VOP0_SRC>; - assigned-clock-parents = <&cru PLL_V0PLL>; -}; - -&vp1 { - assigned-clocks = <&cru DCLK_VOP1_SRC>; - assigned-clock-parents = <&cru PLL_GPLL>; -}; - -&vp2 { - assigned-clocks = <&cru DCLK_VOP2_SRC>; - assigned-clock-parents = <&cru PLL_V0PLL>; -}; - -&vp3 { - assigned-clocks = <&cru DCLK_VOP3>; - assigned-clock-parents = <&cru PLL_V0PLL>; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-v20.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-v20.dtsi deleted file mode 100644 index 91d6ecb67..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-v20.dtsi +++ /dev/null @@ -1,458 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2023 Rockchip Electronics Co., Ltd. - * - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - adc_keys: adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - vol-up-key { - label = "volume up"; - linux,code = ; - press-threshold-microvolt = <17821>; //17000 - }; - - vol-down-key { - label = "volume down"; - linux,code = ; - press-threshold-microvolt = <415384>;//417000 - }; - - menu-key { - label = "menu"; - linux,code = ; - press-threshold-microvolt = <728574>;//890000 - }; - - }; - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - test-power { - status = "okay"; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usbdcin: vcc5v0-usbdcin { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usbdcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usbdcin>; - }; -}; - -&av1d_mmu { - status = "okay"; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - mem-supply = <&vdd_gpu_mem_s0>; - status = "okay"; -}; - -&i2s0_8ch { - status = "okay"; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; -}; - -&iep { - status = "okay"; -}; - -&iep_mmu { - status = "okay"; -}; - -&jpegd { - status = "okay"; -}; - -&jpegd_mmu { - status = "okay"; -}; - -&jpege_ccu { - status = "okay"; -}; - -&jpege0 { - status = "okay"; -}; - -&jpege0_mmu { - status = "okay"; -}; - -&jpege1 { - status = "okay"; -}; - -&jpege1_mmu { - status = "okay"; -}; - -&jpege2 { - status = "okay"; -}; - -&jpege2_mmu { - status = "okay"; -}; - -&jpege3 { - status = "okay"; -}; - -&jpege3_mmu { - status = "okay"; -}; - -&mpp_srv { - status = "okay"; -}; - -&rga3_core0 { - status = "okay"; -}; - -&rga3_0_mmu { - status = "okay"; -}; - -&rga3_core1 { - status = "okay"; -}; - -&rga3_1_mmu { - status = "okay"; -}; - -&rga2 { - status = "okay"; -}; - -&rknpu { - rknpu-supply = <&vdd_npu_s0>; - mem-supply = <&vdd_npu_mem_s0>; - status = "okay"; -}; - -&rknpu_mmu { - status = "okay"; -}; - -&rkvdec_ccu { - status = "okay"; -}; - -&rkvdec0 { - status = "okay"; -}; - -&rkvdec0_mmu { - status = "okay"; -}; - -&rkvdec1 { - status = "okay"; -}; - -&rkvdec1_mmu { - status = "okay"; -}; - -&rkvenc_ccu { - status = "okay"; -}; - -&rkvenc0 { - status = "okay"; -}; - -&rkvenc0_mmu { - status = "okay"; -}; - -&rkvenc1 { - status = "okay"; -}; - -&rkvenc1_mmu { - status = "okay"; -}; - -&rockchip_suspend { - status = "okay"; - rockchip,sleep-debug-en = <1>; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc_1v8_s0>; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - max-frequency = <200000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&sdmmc { - max-frequency = <150000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - sd-uhs-sdr104; - vqmmc-supply = <&vccio_sd_s0>; - status = "disabled"; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy1 { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&u2phy1_otg { - status = "okay"; -}; - -&u2phy2_host { - status = "okay"; -}; - -&u2phy3_host { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdp_phy0 { - status = "okay"; -}; - -&usbdp_phy0_dp { - status = "okay"; -}; - -&usbdp_phy0_u3 { - status = "okay"; -}; - -&usbdp_phy1 { - status = "okay"; -}; - -&usbdp_phy1_dp { - status = "okay"; -}; - -&usbdp_phy1_u3 { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - status = "okay"; -}; - -&usbhost3_0 { - status = "okay"; -}; - -&usbhost_dwc3_0 { - status = "okay"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; -}; - -&vdpu { - status = "okay"; -}; - -&vdpu_mmu { - status = "okay"; -}; - -&vepu { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -/* vp0 & vp1 splice for 8K output */ -&vp0 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; - rockchip,primary-plane = ; -}; - -&vp1 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; - rockchip,primary-plane = ; -}; - -&vp2 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; - rockchip,primary-plane = ; -}; - -&vp3 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; - rockchip,primary-plane = ; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle.dtsi deleted file mode 100644 index f4498cdd2..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle.dtsi +++ /dev/null @@ -1,535 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - adc_keys: adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - vol-up-key { - label = "volume up"; - linux,code = ; - press-threshold-microvolt = <17000>; - }; - - vol-down-key { - label = "volume down"; - linux,code = ; - press-threshold-microvolt = <417000>; - }; - - menu-key { - label = "menu"; - linux,code = ; - press-threshold-microvolt = <890000>; - }; - - back-key { - label = "back"; - linux,code = ; - press-threshold-microvolt = <1235000>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - hdmi0_sound: hdmi0-sound { - status = "disabled"; - compatible = "rockchip,hdmi"; - rockchip,mclk-fs = <128>; - rockchip,card-name = "rockchip-hdmi0"; - rockchip,cpu = <&i2s5_8ch>; - rockchip,codec = <&hdmi0>; - rockchip,jack-det; - }; - - hdmi1_sound: hdmi1-sound { - status = "disabled"; - compatible = "rockchip,hdmi"; - rockchip,mclk-fs = <128>; - rockchip,card-name = "rockchip-hdmi1"; - rockchip,cpu = <&i2s6_8ch>; - rockchip,codec = <&hdmi1>; - rockchip,jack-det; - }; - - dp0_sound: dp0-sound { - status = "disabled"; - compatible = "rockchip,hdmi"; - rockchip,card-name= "rockchip-dp0"; - rockchip,mclk-fs = <512>; - rockchip,cpu = <&spdif_tx2>; - rockchip,codec = <&dp0 1>; - rockchip,jack-det; - }; - - dp1_sound: dp1-sound { - status = "disabled"; - compatible = "rockchip,hdmi"; - rockchip,card-name= "rockchip-dp1"; - rockchip,mclk-fs = <512>; - rockchip,cpu = <&spdif_tx5>; - rockchip,codec = <&dp1 1>; - rockchip,jack-det; - }; - - leds: leds { - compatible = "gpio-leds"; - work_led: work { - gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - spdif_tx1_dc: spdif-tx1-dc { - status = "disabled"; - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - spdif_tx1_sound: spdif-tx1-sound { - status = "disabled"; - compatible = "simple-audio-card"; - simple-audio-card,name = "rockchip,spdif-tx1"; - simple-audio-card,mclk-fs = <128>; - simple-audio-card,cpu { - sound-dai = <&spdif_tx1>; - }; - simple-audio-card,codec { - sound-dai = <&spdif_tx1_dc>; - }; - }; - - test-power { - status = "okay"; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usbdcin: vcc5v0-usbdcin { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usbdcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usbdcin>; - }; -}; - -&av1d_mmu { - status = "okay"; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - mem-supply = <&vdd_gpu_mem_s0>; - status = "okay"; -}; - -&i2s0_8ch { - status = "okay"; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; -}; - -&iep { - status = "okay"; -}; - -&iep_mmu { - status = "okay"; -}; - -&jpegd { - status = "okay"; -}; - -&jpegd_mmu { - status = "okay"; -}; - -&jpege_ccu { - status = "okay"; -}; - -&jpege0 { - status = "okay"; -}; - -&jpege0_mmu { - status = "okay"; -}; - -&jpege1 { - status = "okay"; -}; - -&jpege1_mmu { - status = "okay"; -}; - -&jpege2 { - status = "okay"; -}; - -&jpege2_mmu { - status = "okay"; -}; - -&jpege3 { - status = "okay"; -}; - -&jpege3_mmu { - status = "okay"; -}; - -&mpp_srv { - status = "okay"; -}; - -&rga3_core0 { - status = "okay"; -}; - -&rga3_0_mmu { - status = "okay"; -}; - -&rga3_core1 { - status = "okay"; -}; - -&rga3_1_mmu { - status = "okay"; -}; - -&rga2 { - status = "okay"; -}; - -&rknpu { - rknpu-supply = <&vdd_npu_s0>; - mem-supply = <&vdd_npu_mem_s0>; - status = "okay"; -}; - -&rknpu_mmu { - status = "okay"; -}; - -&rkvdec_ccu { - status = "okay"; -}; - -&rkvdec0 { - status = "okay"; -}; - -&rkvdec0_mmu { - status = "okay"; -}; - -&rkvdec1 { - status = "okay"; -}; - -&rkvdec1_mmu { - status = "okay"; -}; - -&rkvenc_ccu { - status = "okay"; -}; - -&rkvenc0 { - venc-supply = <&vdd_vdenc_s0>; - mem-supply = <&vdd_vdenc_mem_s0>; - status = "okay"; -}; - -&rkvenc0_mmu { - status = "okay"; -}; - -&rkvenc1 { - venc-supply = <&vdd_vdenc_s0>; - mem-supply = <&vdd_vdenc_mem_s0>; - status = "okay"; -}; - -&rkvenc1_mmu { - status = "okay"; -}; - -&rockchip_suspend { - status = "okay"; - rockchip,sleep-debug-en = <1>; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc_1v8_s0>; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - max-frequency = <200000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&sdmmc { - max-frequency = <150000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - sd-uhs-sdr104; - vqmmc-supply = <&vccio_sd_s0>; - status = "disabled"; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy1 { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&u2phy1_otg { - status = "okay"; -}; - -&u2phy2_host { - status = "okay"; -}; - -&u2phy3_host { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdp_phy0 { - status = "okay"; -}; - -&usbdp_phy0_dp { - status = "okay"; -}; - -&usbdp_phy0_u3 { - status = "okay"; -}; - -&usbdp_phy1 { - status = "okay"; -}; - -&usbdp_phy1_dp { - status = "okay"; -}; - -&usbdp_phy1_u3 { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - status = "okay"; -}; - -&usbhost3_0 { - status = "okay"; -}; - -&usbhost_dwc3_0 { - status = "okay"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - status = "okay"; -}; - -&vdpu { - status = "okay"; -}; - -&vdpu_mmu { - status = "okay"; -}; - -&vepu { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -/* vp0 & vp1 splice for 8K output */ -&vp0 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; - rockchip,primary-plane = ; -}; - -&vp1 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; - rockchip,primary-plane = ; -}; - -&vp2 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; - rockchip,primary-plane = ; -}; - -&vp3 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; - rockchip,primary-plane = ; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588m.dtsi b/arch/arm64/boot/dts/rockchip/rk3588m.dtsi deleted file mode 100644 index 1a30a0375..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588m.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. - * - */ - -#include "rk3588.dtsi" - -&cluster0_opp_table { - /delete-node/ opp-1800000000; -}; - -&cluster1_opp_table { - /delete-node/ opp-2208000000; - /delete-node/ opp-2256000000; - /delete-node/ opp-2304000000; - /delete-node/ opp-2352000000; - /delete-node/ opp-2400000000; -}; - -&cluster2_opp_table { - /delete-node/ opp-2208000000; - /delete-node/ opp-2256000000; - /delete-node/ opp-2304000000; - /delete-node/ opp-2352000000; - /delete-node/ opp-2400000000; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi deleted file mode 100644 index 586c62774..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb.dtsi +++ /dev/null @@ -1,1153 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - adc_keys: adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - vol-up-key { - label = "volume up"; - linux,code = ; - press-threshold-microvolt = <17000>; - }; - - vol-down-key { - label = "volume down"; - linux,code = ; - press-threshold-microvolt = <417000>; - }; - - menu-key { - label = "menu"; - linux,code = ; - press-threshold-microvolt = <890000>; - }; - - back-key { - label = "back"; - linux,code = ; - press-threshold-microvolt = <1235000>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - dp0_sound: dp0-sound { - status = "disabled"; - compatible = "rockchip,hdmi"; - rockchip,card-name= "rockchip-dp0"; - rockchip,mclk-fs = <512>; - rockchip,cpu = <&spdif_tx2>; - rockchip,codec = <&dp0 1>; - rockchip,jack-det; - }; - - hdmi0_sound: hdmi0-sound { - status = "disabled"; - compatible = "rockchip,hdmi"; - rockchip,mclk-fs = <128>; - rockchip,card-name = "rockchip-hdmi0"; - rockchip,cpu = <&i2s5_8ch>; - rockchip,codec = <&hdmi0>; - rockchip,jack-det; - }; - - spdif_tx1_dc: spdif-tx1-dc { - status = "disabled"; - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - spdif_tx1_sound: spdif-tx1-sound { - status = "disabled"; - compatible = "simple-audio-card"; - simple-audio-card,name = "rockchip,spdif-tx1"; - simple-audio-card,mclk-fs = <128>; - simple-audio-card,cpu { - sound-dai = <&spdif_tx1>; - }; - simple-audio-card,codec { - sound-dai = <&spdif_tx1_dc>; - }; - }; - - test-power { - status = "okay"; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usbdcin: vcc5v0-usbdcin { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usbdcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usbdcin>; - }; -}; - -&av1d_mmu { - status = "okay"; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&dsi0 { - status = "disabled"; - //rockchip,lane-rate = <1000>; - dsi0_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight>; - reset-delay-ms = <60>; - enable-delay-ms = <60>; - prepare-delay-ms = <60>; - unprepare-delay-ms = <60>; - disable-delay-ms = <60>; - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | - MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - panel-init-sequence = [ - 23 00 02 FE 21 - 23 00 02 04 00 - 23 00 02 00 64 - 23 00 02 2A 00 - 23 00 02 26 64 - 23 00 02 54 00 - 23 00 02 50 64 - 23 00 02 7B 00 - 23 00 02 77 64 - 23 00 02 A2 00 - 23 00 02 9D 64 - 23 00 02 C9 00 - 23 00 02 C5 64 - 23 00 02 01 71 - 23 00 02 27 71 - 23 00 02 51 71 - 23 00 02 78 71 - 23 00 02 9E 71 - 23 00 02 C6 71 - 23 00 02 02 89 - 23 00 02 28 89 - 23 00 02 52 89 - 23 00 02 79 89 - 23 00 02 9F 89 - 23 00 02 C7 89 - 23 00 02 03 9E - 23 00 02 29 9E - 23 00 02 53 9E - 23 00 02 7A 9E - 23 00 02 A0 9E - 23 00 02 C8 9E - 23 00 02 09 00 - 23 00 02 05 B0 - 23 00 02 31 00 - 23 00 02 2B B0 - 23 00 02 5A 00 - 23 00 02 55 B0 - 23 00 02 80 00 - 23 00 02 7C B0 - 23 00 02 A7 00 - 23 00 02 A3 B0 - 23 00 02 CE 00 - 23 00 02 CA B0 - 23 00 02 06 C0 - 23 00 02 2D C0 - 23 00 02 56 C0 - 23 00 02 7D C0 - 23 00 02 A4 C0 - 23 00 02 CB C0 - 23 00 02 07 CF - 23 00 02 2F CF - 23 00 02 58 CF - 23 00 02 7E CF - 23 00 02 A5 CF - 23 00 02 CC CF - 23 00 02 08 DD - 23 00 02 30 DD - 23 00 02 59 DD - 23 00 02 7F DD - 23 00 02 A6 DD - 23 00 02 CD DD - 23 00 02 0E 15 - 23 00 02 0A E9 - 23 00 02 36 15 - 23 00 02 32 E9 - 23 00 02 5F 15 - 23 00 02 5B E9 - 23 00 02 85 15 - 23 00 02 81 E9 - 23 00 02 AD 15 - 23 00 02 A9 E9 - 23 00 02 D3 15 - 23 00 02 CF E9 - 23 00 02 0B 14 - 23 00 02 33 14 - 23 00 02 5C 14 - 23 00 02 82 14 - 23 00 02 AA 14 - 23 00 02 D0 14 - 23 00 02 0C 36 - 23 00 02 34 36 - 23 00 02 5D 36 - 23 00 02 83 36 - 23 00 02 AB 36 - 23 00 02 D1 36 - 23 00 02 0D 6B - 23 00 02 35 6B - 23 00 02 5E 6B - 23 00 02 84 6B - 23 00 02 AC 6B - 23 00 02 D2 6B - 23 00 02 13 5A - 23 00 02 0F 94 - 23 00 02 3B 5A - 23 00 02 37 94 - 23 00 02 64 5A - 23 00 02 60 94 - 23 00 02 8A 5A - 23 00 02 86 94 - 23 00 02 B2 5A - 23 00 02 AE 94 - 23 00 02 D8 5A - 23 00 02 D4 94 - 23 00 02 10 D1 - 23 00 02 38 D1 - 23 00 02 61 D1 - 23 00 02 87 D1 - 23 00 02 AF D1 - 23 00 02 D5 D1 - 23 00 02 11 04 - 23 00 02 39 04 - 23 00 02 62 04 - 23 00 02 88 04 - 23 00 02 B0 04 - 23 00 02 D6 04 - 23 00 02 12 05 - 23 00 02 3A 05 - 23 00 02 63 05 - 23 00 02 89 05 - 23 00 02 B1 05 - 23 00 02 D7 05 - 23 00 02 18 AA - 23 00 02 14 36 - 23 00 02 42 AA - 23 00 02 3D 36 - 23 00 02 69 AA - 23 00 02 65 36 - 23 00 02 8F AA - 23 00 02 8B 36 - 23 00 02 B7 AA - 23 00 02 B3 36 - 23 00 02 DD AA - 23 00 02 D9 36 - 23 00 02 15 74 - 23 00 02 3F 74 - 23 00 02 66 74 - 23 00 02 8C 74 - 23 00 02 B4 74 - 23 00 02 DA 74 - 23 00 02 16 9F - 23 00 02 40 9F - 23 00 02 67 9F - 23 00 02 8D 9F - 23 00 02 B5 9F - 23 00 02 DB 9F - 23 00 02 17 DC - 23 00 02 41 DC - 23 00 02 68 DC - 23 00 02 8E DC - 23 00 02 B6 DC - 23 00 02 DC DC - 23 00 02 1D FF - 23 00 02 19 03 - 23 00 02 47 FF - 23 00 02 43 03 - 23 00 02 6E FF - 23 00 02 6A 03 - 23 00 02 94 FF - 23 00 02 90 03 - 23 00 02 BC FF - 23 00 02 B8 03 - 23 00 02 E2 FF - 23 00 02 DE 03 - 23 00 02 1A 35 - 23 00 02 44 35 - 23 00 02 6B 35 - 23 00 02 91 35 - 23 00 02 B9 35 - 23 00 02 DF 35 - 23 00 02 1B 45 - 23 00 02 45 45 - 23 00 02 6C 45 - 23 00 02 92 45 - 23 00 02 BA 45 - 23 00 02 E0 45 - 23 00 02 1C 55 - 23 00 02 46 55 - 23 00 02 6D 55 - 23 00 02 93 55 - 23 00 02 BB 55 - 23 00 02 E1 55 - 23 00 02 22 FF - 23 00 02 1E 68 - 23 00 02 4C FF - 23 00 02 48 68 - 23 00 02 73 FF - 23 00 02 6F 68 - 23 00 02 99 FF - 23 00 02 95 68 - 23 00 02 C1 FF - 23 00 02 BD 68 - 23 00 02 E7 FF - 23 00 02 E3 68 - 23 00 02 1F 7E - 23 00 02 49 7E - 23 00 02 70 7E - 23 00 02 96 7E - 23 00 02 BE 7E - 23 00 02 E4 7E - 23 00 02 20 97 - 23 00 02 4A 97 - 23 00 02 71 97 - 23 00 02 97 97 - 23 00 02 BF 97 - 23 00 02 E5 97 - 23 00 02 21 B5 - 23 00 02 4B B5 - 23 00 02 72 B5 - 23 00 02 98 B5 - 23 00 02 C0 B5 - 23 00 02 E6 B5 - 23 00 02 25 F0 - 23 00 02 23 E8 - 23 00 02 4F F0 - 23 00 02 4D E8 - 23 00 02 76 F0 - 23 00 02 74 E8 - 23 00 02 9C F0 - 23 00 02 9A E8 - 23 00 02 C4 F0 - 23 00 02 C2 E8 - 23 00 02 EA F0 - 23 00 02 E8 E8 - 23 00 02 24 FF - 23 00 02 4E FF - 23 00 02 75 FF - 23 00 02 9B FF - 23 00 02 C3 FF - 23 00 02 E9 FF - 23 00 02 FE 3D - 23 00 02 00 04 - 23 00 02 FE 23 - 23 00 02 08 82 - 23 00 02 0A 00 - 23 00 02 0B 00 - 23 00 02 0C 01 - 23 00 02 16 00 - 23 00 02 18 02 - 23 00 02 1B 04 - 23 00 02 19 04 - 23 00 02 1C 81 - 23 00 02 1F 00 - 23 00 02 20 03 - 23 00 02 23 04 - 23 00 02 21 01 - 23 00 02 54 63 - 23 00 02 55 54 - 23 00 02 6E 45 - 23 00 02 6D 36 - 23 00 02 FE 3D - 23 00 02 55 78 - 23 00 02 FE 20 - 23 00 02 26 30 - 23 00 02 FE 3D - 23 00 02 20 71 - 23 00 02 50 8F - 23 00 02 51 8F - 23 00 02 FE 00 - 23 00 02 35 00 - 05 78 01 11 - 05 1E 01 29 - ]; - - panel-exit-sequence = [ - 05 00 01 28 - 05 00 01 10 - ]; - - disp_timings0: display-timings { - native-mode = <&dsi0_timing0>; - dsi0_timing0: timing0 { - clock-frequency = <132000000>; - hactive = <1080>; - vactive = <1920>; - hfront-porch = <15>; - hsync-len = <4>; - hback-porch = <30>; - vfront-porch = <15>; - vsync-len = <2>; - vback-porch = <15>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - panel_in_dsi: endpoint { - remote-endpoint = <&dsi_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi>; - }; - }; - }; - -}; - -&dsi1 { - status = "disabled"; - //rockchip,lane-rate = <1000>; - dsi1_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight>; - reset-delay-ms = <60>; - enable-delay-ms = <60>; - prepare-delay-ms = <60>; - unprepare-delay-ms = <60>; - disable-delay-ms = <60>; - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | - MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - panel-init-sequence = [ - 23 00 02 FE 21 - 23 00 02 04 00 - 23 00 02 00 64 - 23 00 02 2A 00 - 23 00 02 26 64 - 23 00 02 54 00 - 23 00 02 50 64 - 23 00 02 7B 00 - 23 00 02 77 64 - 23 00 02 A2 00 - 23 00 02 9D 64 - 23 00 02 C9 00 - 23 00 02 C5 64 - 23 00 02 01 71 - 23 00 02 27 71 - 23 00 02 51 71 - 23 00 02 78 71 - 23 00 02 9E 71 - 23 00 02 C6 71 - 23 00 02 02 89 - 23 00 02 28 89 - 23 00 02 52 89 - 23 00 02 79 89 - 23 00 02 9F 89 - 23 00 02 C7 89 - 23 00 02 03 9E - 23 00 02 29 9E - 23 00 02 53 9E - 23 00 02 7A 9E - 23 00 02 A0 9E - 23 00 02 C8 9E - 23 00 02 09 00 - 23 00 02 05 B0 - 23 00 02 31 00 - 23 00 02 2B B0 - 23 00 02 5A 00 - 23 00 02 55 B0 - 23 00 02 80 00 - 23 00 02 7C B0 - 23 00 02 A7 00 - 23 00 02 A3 B0 - 23 00 02 CE 00 - 23 00 02 CA B0 - 23 00 02 06 C0 - 23 00 02 2D C0 - 23 00 02 56 C0 - 23 00 02 7D C0 - 23 00 02 A4 C0 - 23 00 02 CB C0 - 23 00 02 07 CF - 23 00 02 2F CF - 23 00 02 58 CF - 23 00 02 7E CF - 23 00 02 A5 CF - 23 00 02 CC CF - 23 00 02 08 DD - 23 00 02 30 DD - 23 00 02 59 DD - 23 00 02 7F DD - 23 00 02 A6 DD - 23 00 02 CD DD - 23 00 02 0E 15 - 23 00 02 0A E9 - 23 00 02 36 15 - 23 00 02 32 E9 - 23 00 02 5F 15 - 23 00 02 5B E9 - 23 00 02 85 15 - 23 00 02 81 E9 - 23 00 02 AD 15 - 23 00 02 A9 E9 - 23 00 02 D3 15 - 23 00 02 CF E9 - 23 00 02 0B 14 - 23 00 02 33 14 - 23 00 02 5C 14 - 23 00 02 82 14 - 23 00 02 AA 14 - 23 00 02 D0 14 - 23 00 02 0C 36 - 23 00 02 34 36 - 23 00 02 5D 36 - 23 00 02 83 36 - 23 00 02 AB 36 - 23 00 02 D1 36 - 23 00 02 0D 6B - 23 00 02 35 6B - 23 00 02 5E 6B - 23 00 02 84 6B - 23 00 02 AC 6B - 23 00 02 D2 6B - 23 00 02 13 5A - 23 00 02 0F 94 - 23 00 02 3B 5A - 23 00 02 37 94 - 23 00 02 64 5A - 23 00 02 60 94 - 23 00 02 8A 5A - 23 00 02 86 94 - 23 00 02 B2 5A - 23 00 02 AE 94 - 23 00 02 D8 5A - 23 00 02 D4 94 - 23 00 02 10 D1 - 23 00 02 38 D1 - 23 00 02 61 D1 - 23 00 02 87 D1 - 23 00 02 AF D1 - 23 00 02 D5 D1 - 23 00 02 11 04 - 23 00 02 39 04 - 23 00 02 62 04 - 23 00 02 88 04 - 23 00 02 B0 04 - 23 00 02 D6 04 - 23 00 02 12 05 - 23 00 02 3A 05 - 23 00 02 63 05 - 23 00 02 89 05 - 23 00 02 B1 05 - 23 00 02 D7 05 - 23 00 02 18 AA - 23 00 02 14 36 - 23 00 02 42 AA - 23 00 02 3D 36 - 23 00 02 69 AA - 23 00 02 65 36 - 23 00 02 8F AA - 23 00 02 8B 36 - 23 00 02 B7 AA - 23 00 02 B3 36 - 23 00 02 DD AA - 23 00 02 D9 36 - 23 00 02 15 74 - 23 00 02 3F 74 - 23 00 02 66 74 - 23 00 02 8C 74 - 23 00 02 B4 74 - 23 00 02 DA 74 - 23 00 02 16 9F - 23 00 02 40 9F - 23 00 02 67 9F - 23 00 02 8D 9F - 23 00 02 B5 9F - 23 00 02 DB 9F - 23 00 02 17 DC - 23 00 02 41 DC - 23 00 02 68 DC - 23 00 02 8E DC - 23 00 02 B6 DC - 23 00 02 DC DC - 23 00 02 1D FF - 23 00 02 19 03 - 23 00 02 47 FF - 23 00 02 43 03 - 23 00 02 6E FF - 23 00 02 6A 03 - 23 00 02 94 FF - 23 00 02 90 03 - 23 00 02 BC FF - 23 00 02 B8 03 - 23 00 02 E2 FF - 23 00 02 DE 03 - 23 00 02 1A 35 - 23 00 02 44 35 - 23 00 02 6B 35 - 23 00 02 91 35 - 23 00 02 B9 35 - 23 00 02 DF 35 - 23 00 02 1B 45 - 23 00 02 45 45 - 23 00 02 6C 45 - 23 00 02 92 45 - 23 00 02 BA 45 - 23 00 02 E0 45 - 23 00 02 1C 55 - 23 00 02 46 55 - 23 00 02 6D 55 - 23 00 02 93 55 - 23 00 02 BB 55 - 23 00 02 E1 55 - 23 00 02 22 FF - 23 00 02 1E 68 - 23 00 02 4C FF - 23 00 02 48 68 - 23 00 02 73 FF - 23 00 02 6F 68 - 23 00 02 99 FF - 23 00 02 95 68 - 23 00 02 C1 FF - 23 00 02 BD 68 - 23 00 02 E7 FF - 23 00 02 E3 68 - 23 00 02 1F 7E - 23 00 02 49 7E - 23 00 02 70 7E - 23 00 02 96 7E - 23 00 02 BE 7E - 23 00 02 E4 7E - 23 00 02 20 97 - 23 00 02 4A 97 - 23 00 02 71 97 - 23 00 02 97 97 - 23 00 02 BF 97 - 23 00 02 E5 97 - 23 00 02 21 B5 - 23 00 02 4B B5 - 23 00 02 72 B5 - 23 00 02 98 B5 - 23 00 02 C0 B5 - 23 00 02 E6 B5 - 23 00 02 25 F0 - 23 00 02 23 E8 - 23 00 02 4F F0 - 23 00 02 4D E8 - 23 00 02 76 F0 - 23 00 02 74 E8 - 23 00 02 9C F0 - 23 00 02 9A E8 - 23 00 02 C4 F0 - 23 00 02 C2 E8 - 23 00 02 EA F0 - 23 00 02 E8 E8 - 23 00 02 24 FF - 23 00 02 4E FF - 23 00 02 75 FF - 23 00 02 9B FF - 23 00 02 C3 FF - 23 00 02 E9 FF - 23 00 02 FE 3D - 23 00 02 00 04 - 23 00 02 FE 23 - 23 00 02 08 82 - 23 00 02 0A 00 - 23 00 02 0B 00 - 23 00 02 0C 01 - 23 00 02 16 00 - 23 00 02 18 02 - 23 00 02 1B 04 - 23 00 02 19 04 - 23 00 02 1C 81 - 23 00 02 1F 00 - 23 00 02 20 03 - 23 00 02 23 04 - 23 00 02 21 01 - 23 00 02 54 63 - 23 00 02 55 54 - 23 00 02 6E 45 - 23 00 02 6D 36 - 23 00 02 FE 3D - 23 00 02 55 78 - 23 00 02 FE 20 - 23 00 02 26 30 - 23 00 02 FE 3D - 23 00 02 20 71 - 23 00 02 50 8F - 23 00 02 51 8F - 23 00 02 FE 00 - 23 00 02 35 00 - 05 78 01 11 - 05 1E 01 29 - ]; - - panel-exit-sequence = [ - 05 00 01 28 - 05 00 01 10 - ]; - - disp_timings1: display-timings { - native-mode = <&dsi1_timing0>; - dsi1_timing0: timing0 { - clock-frequency = <132000000>; - hactive = <1080>; - vactive = <1920>; - hfront-porch = <15>; - hsync-len = <4>; - hback-porch = <30>; - vfront-porch = <15>; - vsync-len = <2>; - vback-porch = <15>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - panel_in_dsi1: endpoint { - remote-endpoint = <&dsi1_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi1_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi1>; - }; - }; - }; - -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - mem-supply = <&vdd_gpu_mem_s0>; - status = "okay"; -}; - -&i2s0_8ch { - status = "okay"; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; -}; - -&iep { - status = "okay"; -}; - -&iep_mmu { - status = "okay"; -}; - -&jpegd { - status = "okay"; -}; - -&jpegd_mmu { - status = "okay"; -}; - -&jpege_ccu { - status = "okay"; -}; - -&jpege0 { - status = "okay"; -}; - -&jpege0_mmu { - status = "okay"; -}; - -&jpege1 { - status = "okay"; -}; - -&jpege1_mmu { - status = "okay"; -}; - -&jpege2 { - status = "okay"; -}; - -&jpege2_mmu { - status = "okay"; -}; - -&jpege3 { - status = "okay"; -}; - -&jpege3_mmu { - status = "okay"; -}; - -&mpp_srv { - status = "okay"; -}; - -&rga3_core0 { - status = "okay"; -}; - -&rga3_0_mmu { - status = "okay"; -}; - -&rga3_core1 { - status = "okay"; -}; - -&rga3_1_mmu { - status = "okay"; -}; - -&rga2 { - status = "okay"; -}; - -&rknpu { - rknpu-supply = <&vdd_npu_s0>; - mem-supply = <&vdd_npu_mem_s0>; - status = "okay"; -}; - -&rknpu_mmu { - status = "okay"; -}; - -&rkvdec_ccu { - status = "okay"; -}; - -&rkvdec0 { - status = "okay"; -}; - -&rkvdec0_mmu { - status = "okay"; -}; - -&rkvdec1 { - status = "okay"; -}; - -&rkvdec1_mmu { - status = "okay"; -}; - -&rkvenc_ccu { - status = "okay"; -}; - -&rkvenc0 { - venc-supply = <&vdd_vdenc_s0>; - mem-supply = <&vdd_vdenc_mem_s0>; - status = "okay"; -}; - -&rkvenc0_mmu { - status = "okay"; -}; - -&rkvenc1 { - venc-supply = <&vdd_vdenc_s0>; - mem-supply = <&vdd_vdenc_mem_s0>; - status = "okay"; -}; - -&rkvenc1_mmu { - status = "okay"; -}; - -&rockchip_suspend { - status = "okay"; - rockchip,sleep-debug-en = <1>; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc_1v8_s0>; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - max-frequency = <200000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - full-pwr-cycle-in-suspend; - status = "okay"; -}; - -&sdmmc { - max-frequency = <150000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_sd_s0>; - vqmmc-supply = <&vccio_sd_s0>; - status = "disabled"; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&u2phy2_host { - status = "okay"; -}; - -&u2phy3_host { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usbdp_phy0 { - status = "okay"; -}; - -&usbdp_phy0_dp { - status = "okay"; -}; - -&usbdp_phy0_u3 { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - status = "okay"; -}; - -&usbhost3_0 { - status = "okay"; -}; - -&usbhost_dwc3_0 { - status = "okay"; -}; - -&vdpu { - status = "okay"; -}; - -&vdpu_mmu { - status = "okay"; -}; - -&vepu { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -/* vp0 & vp1 splice for 8K output */ -&vp0 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; - rockchip,primary-plane = ; -}; - -&vp1 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; - rockchip,primary-plane = ; -}; - -&vp2 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; - rockchip,primary-plane = ; -}; - -&vp3 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; - rockchip,primary-plane = ; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x-v10-camera.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x-v10-camera.dtsi deleted file mode 100644 index 086eee3c7..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x-v10-camera.dtsi +++ /dev/null @@ -1,345 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -&csi2_dcphy0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dp_mipi_in: endpoint@1 { - reg = <1>; - remote-endpoint = <<7911d_out>; - data-lanes = <1 2 3 4>; - }; - mipi_in_dcphy0: endpoint@2 { - reg = <2>; - remote-endpoint = <&ov50c40_out0>; - data-lanes = <1 2 3 4>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidcphy0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi0_csi2_input>; - }; - }; - }; -}; - -&csi2_dcphy1 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_dcphy1: endpoint@1 { - reg = <1>; - remote-endpoint = <&ov50c40_out1>; - data-lanes = <1 2 3 4>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidcphy1_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi1_csi2_input>; - }; - }; - }; -}; - -&i2c6 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6m4_xfer>; - - aw8601: aw8601@c { - compatible = "awinic,aw8601"; - status = "okay"; - reg = <0x0c>; - rockchip,vcm-start-current = <56>; - rockchip,vcm-rated-current = <96>; - rockchip,vcm-step-mode = <4>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - }; - - lt7911d: lt7911d@2b { - compatible = "lontium,lt7911d"; - status = "okay"; - reg = <0x2b>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; - clock-names = "xvclk"; - interrupt-parent = <&gpio3>; - interrupts = ; - power-domains = <&power RK3588_PD_VI>; - pinctrl-names = "default"; - pinctrl-0 = <&mipim1_camera1_clk>; - reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; - power-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; - // hpd-ctl-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; - // plugin-det-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "LT7911D"; - rockchip,camera-module-lens-name = "NC"; - port { - lt7911d_out: endpoint { - remote-endpoint = <&dp_mipi_in>; - data-lanes = <1 2 3 4>; - }; - }; - }; - - ov50c40: ov50c40@36 { - compatible = "ovti,ov50c40"; - status = "okay"; - reg = <0x36>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - pinctrl-names = "default"; - pinctrl-0 = <&mipim1_camera1_clk>; - rockchip,grf = <&sys_grf>; - reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; - pwdn-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "HZGA06"; - rockchip,camera-module-lens-name = "ZE0082C1"; - eeprom-ctrl = <&otp_eeprom>; - lens-focus = <&aw8601>; - port { - ov50c40_out0: endpoint { - remote-endpoint = <&mipi_in_dcphy0>; - data-lanes = <1 2 3 4>; - }; - }; - }; - - otp_eeprom: otp_eeprom@50 { - compatible = "rk,otp_eeprom"; - status = "okay"; - reg = <0x50>; - }; -}; - -&i2c7 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7m2_xfer>; - - aw8601b: aw8601b@c { - compatible = "awinic,aw8601"; - status = "okay"; - reg = <0x0c>; - rockchip,vcm-start-current = <56>; - rockchip,vcm-rated-current = <96>; - rockchip,vcm-step-mode = <4>; - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - }; - - ov50c40b: ov50c40b@36 { - compatible = "ovti,ov50c40"; - status = "okay"; - reg = <0x36>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - pinctrl-names = "default"; - pinctrl-0 = <&mipim1_camera2_clk>; - rockchip,grf = <&sys_grf>; - reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>; - pwdn-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "HZGA06"; - rockchip,camera-module-lens-name = "ZE0082C1"; - eeprom-ctrl = <&otp_eeprom_b>; - lens-focus = <&aw8601b>; - port { - ov50c40_out1: endpoint { - remote-endpoint = <&mipi_in_dcphy1>; - data-lanes = <1 2 3 4>; - }; - }; - }; - - otp_eeprom_b: otp_eeprom_b@50 { - compatible = "rk,otp_eeprom"; - status = "okay"; - reg = <0x50>; - }; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&mipi_dcphy1 { - status = "okay"; -}; - -&mipi0_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidcphy0_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in0>; - }; - }; - }; -}; - -&mipi1_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi1_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidcphy1_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi1_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in1>; - }; - }; - }; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds { - status = "okay"; - - port { - cif_mipi_in0: endpoint { - remote-endpoint = <&mipi0_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds_sditf { - status = "okay"; - - port { - mipi_lvds_sditf: endpoint { - remote-endpoint = <&isp1_in1>; - }; - }; -}; - -&rkcif_mipi_lvds1 { - status = "okay"; - - port { - cif_mipi_in1: endpoint { - remote-endpoint = <&mipi1_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds1_sditf { - status = "okay"; - - port { - mipi1_lvds_sditf: endpoint { - remote-endpoint = <&isp1_in2>; - }; - }; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp_unite { - status = "okay"; - -}; - -&rkisp_unite_mmu { - status = "okay"; -}; - -&rkisp0_vir0 { - status = "okay"; - /* - * dual isp process image case - * other rkisp hw and virtual nodes should disabled - */ - rockchip,hw = <&rkisp_unite>; - port { - #address-cells = <1>; - #size-cells = <0>; - - isp1_in1: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds_sditf>; - }; - isp1_in2: endpoint@1 { - reg = <1>; - remote-endpoint = <&mipi1_lvds_sditf>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x-v10-linux.dts deleted file mode 100644 index 4d8157bcc..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x-v10-linux.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588s-evb1-lp4x.dtsi" -#include "rk3588s-evb1-lp4x-v10-camera.dtsi" -#include "rk3588-linux.dtsi" - -/ { - model = "Rockchip RK3588S EVB1 LP4X V10 Board"; - compatible = "rockchip,rk3588s-evb1-lp4x-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x-v10.dts deleted file mode 100644 index ec195f6a9..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x-v10.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588s-evb1-lp4x.dtsi" -#include "rk3588s-evb1-lp4x-v10-camera.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588S EVB1 LP4X V10 Board"; - compatible = "rockchip,rk3588s-evb1-lp4x-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x.dtsi deleted file mode 100644 index 68f17eec6..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x.dtsi +++ /dev/null @@ -1,870 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include "dt-bindings/usb/pd.h" -#include "rk3588s.dtsi" -#include "rk3588s-evb.dtsi" -#include "rk3588s-rk806-dual.dtsi" - -/ { - aw883xx_sound: aw883x-sound { - status = "disabled"; - compatible = "rockchip,multicodecs-card"; - rockchip,card-name = "rockchip-aw883xx"; - rockchip,format = "i2s"; - rockchip,mclk-fs = <256>; - rockchip,cpu = <&i2s0_8ch>; - rockchip,codec = <&aw883xx_1 &aw883xx_2 &aw883xx_3 &aw883xx_4>; - }; - - combophy_avdd0v85: combophy-avdd0v85 { - compatible = "regulator-fixed"; - regulator-name = "combophy_avdd0v85"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&vdd_0v85_s0>; - }; - - combophy_avdd1v8: combophy-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "combophy_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - es7202_sound_micarray: es7202-sound-micarray { - status = "okay"; - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip,sound-micarray"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,dai-link@0 { - format = "pdm"; - cpu { - sound-dai = <&pdm0>; - }; - codec { - sound-dai = <&es7202>; - }; - }; - }; - - es8326_sound: es8326-sound { - status = "disabled"; - compatible = "rockchip,multicodecs-card"; - rockchip,card-name = "rockchip-es8326"; - rockchip,format = "i2s"; - rockchip,mclk-fs = <256>; - rockchip,cpu = <&i2s1_8ch>; - rockchip,codec = <&es8326>; - rockchip,audio-routing = - "Headphone", "HPOL", - "Headphone", "HPOR", - "Headphone", "Headphone Power", - "Headphone", "Headphone Power", - "MIC1", "Headset Mic", - "MIC2", "Main Mic"; - }; - - es8388_sound: es8388-sound { - status = "okay"; - compatible = "rockchip,multicodecs-card"; - rockchip,card-name = "rockchip-es8388"; - hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; - io-channels = <&saradc 3>; - io-channel-names = "adc-detect"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - spk-con-gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - hp-con-gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; - rockchip,format = "i2s"; - rockchip,mclk-fs = <256>; - rockchip,cpu = <&i2s0_8ch>; - rockchip,codec = <&es8388>; - rockchip,audio-routing = - "Headphone", "LOUT1", - "Headphone", "ROUT1", - "Speaker", "LOUT2", - "Speaker", "ROUT2", - "Headphone", "Headphone Power", - "Headphone", "Headphone Power", - "Speaker", "Speaker Power", - "Speaker", "Speaker Power", - "LINPUT1", "Main Mic", - "LINPUT2", "Main Mic", - "RINPUT1", "Headset Mic", - "RINPUT2", "Headset Mic"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - play-pause-key { - label = "playpause"; - linux,code = ; - press-threshold-microvolt = <2000>; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - pwms = <&pwm11 0 50000 0>; - cooling-levels = <0 50 100 150 200 255>; - rockchip,temp-trips = < - 50000 1 - 55000 2 - 60000 3 - 65000 4 - 70000 5 - >; - }; - - hall_sensor: hall-mh248 { - compatible = "hall-mh248"; - pinctrl-names = "default"; - pinctrl-0 = <&mh248_irq_gpio>; - irq-gpio = <&gpio0 RK_PD4 IRQ_TYPE_EDGE_BOTH>; - hall-active = <1>; - status = "okay"; - }; - - panel-edp { - compatible = "simple-panel"; - backlight = <&backlight>; - power-supply = <&vcc3v3_lcd_edp>; - prepare-delay-ms = <120>; - enable-delay-ms = <120>; - unprepare-delay-ms = <120>; - disable-delay-ms = <120>; - width-mm = <129>; - height-mm = <171>; - - panel-timing { - clock-frequency = <200000000>; - hactive = <1536>; - vactive = <2048>; - hfront-porch = <12>; - hsync-len = <16>; - hback-porch = <48>; - vfront-porch = <8>; - vsync-len = <4>; - vback-porch = <8>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - panel_in_edp: endpoint { - remote-endpoint = <&edp_out_panel>; - }; - }; - }; - - vbus5v0_typec: vbus5v0-typec { - compatible = "regulator-fixed"; - regulator-name = "vbus5v0_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; - }; - - vcc3v3_lcd_edp: vcc3v3-lcd-edp { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd_edp"; - gpio = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc3v3_pcie20: vcc3v3-pcie20 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie20"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_host: vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - }; - - wireless_bluetooth: wireless-bluetooth { - compatible = "bluetooth-platdata"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "rts_gpio"; - pinctrl-0 = <&uart8m1_rtsn>, <&bt_gpio>; - pinctrl-1 = <&uart8_gpios>; - BT,reset_gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; - BT,wake_gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; - BT,wake_host_irq = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - wifi_chip_type = "ap6275p"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; - WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - WIFI,poweren_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; -}; - -&backlight { - pwms = <&pwm12 0 25000 0>; - power-supply = <&vcc3v3_lcd_edp>; - status = "okay"; -}; - -&combphy0_ps { - status = "okay"; -}; - -&dp0 { - status = "okay"; -}; - -&dp0_in_vp1 { - status = "okay"; -}; - -&dp0_sound{ - status = "okay"; -}; - -&edp0 { - force-hpd; - status = "okay"; - - ports { - port@1 { - reg = <1>; - - edp_out_panel: endpoint { - remote-endpoint = <&panel_in_edp>; - }; - }; - }; -}; - -&edp0_in_vp2 { - status = "okay"; -}; - -&hdptxphy0 { - /* Single Vdiff Training Table for power reduction (optional) */ - training-table = /bits/ 8 < - /* voltage swing 0, pre-emphasis 0->3 */ - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - /* voltage swing 1, pre-emphasis 0->2 */ - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - /* voltage swing 2, pre-emphasis 0->1 */ - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - /* voltage swing 3, pre-emphasis 0 */ - 0x0d 0x00 0x00 0x00 0x00 0x00 - >; - status = "okay"; -}; - -&i2c3 { - status = "okay"; - - es8388: es8388@11 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "everest,es8388", "everest,es8323"; - reg = <0x11>; - clocks = <&mclkout_i2s0>; - clock-names = "mclk"; - assigned-clocks = <&mclkout_i2s0>; - assigned-clock-rates = <12288000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk>; - }; - - es8326: es8326@18 { - status = "disabled"; - #sound-dai-cells = <0>; - compatible = "everest,es8326"; - reg = <0x18>; - clocks = <&mclkout_i2s1>; - clock-names = "mclk"; - assigned-clocks = <&mclkout_i2s1>; - assigned-clock-rates = <12288000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_mclk>; - mclk-rate = <12288000>; - mic1-src = [22]; - mic2-src = [44]; - jack-pol = [0e]; - }; - - es7202: es7202@32 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "ES7202_PDM_ADC_1"; - power-supply = <&vcc_1v8_s0>; /* only 1v8 or 3v3, default is 3v3 */ - reg = <0x32>; - }; - - aw883xx_1: aw883xx@34 { - compatible = "awinic,aw883xx_smartpa"; - reg = <0x34>; - #sound-dai-cells = <0>; - reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&aw_rst1_gpio>; - pinctrl-names = "default"; - sound-channel = <0>; - re-min = <1000>; - re-max= <40000>; - status = "disabled"; - }; - - aw883xx_2: aw883xx@35 { - compatible = "awinic,aw883xx_smartpa"; - reg = <0x35>; - #sound-dai-cells = <0>; - reset-gpio = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&aw_rst2_gpio>; - pinctrl-names = "default"; - sound-channel = <1>; - re-min = <1000>; - re-max= <40000>; - status = "disabled"; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4m3_xfer>; - status = "okay"; - - aw883xx_3: aw883xx@34 { - compatible = "awinic,aw883xx_smartpa"; - reg = <0x34>; - #sound-dai-cells = <0>; - reset-gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&aw_rst3_gpio>; - pinctrl-names = "default"; - sound-channel = <2>; - re-min = <1000>; - re-max= <40000>; - status = "disabled"; - }; - - aw883xx_4: aw883xx@35 { - compatible = "awinic,aw883xx_smartpa"; - reg = <0x35>; - #sound-dai-cells = <0>; - reset-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&aw_rst4_gpio>; - pinctrl-names = "default"; - sound-channel = <3>; - re-min = <1000>; - re-max= <40000>; - status = "disabled"; - }; - - gsl3673@40 { - compatible = "GSL,GSL3673"; - reg = <0x40>; - screen_max_x = <1536>; - screen_max_y = <2048>; - irq_gpio_number = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>; - rst_gpio_number = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - }; -}; - -&i2c5 { - status = "okay"; - - ls_stk3332: light@47 { - compatible = "ls_stk3332"; - status = "disabled"; - reg = <0x47>; - type = ; - irq_enable = <0>; - als_threshold_high = <100>; - als_threshold_low = <10>; - als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ - poll_delay_ms = <100>; - }; - - ps_stk3332: proximity@47 { - compatible = "ps_stk3332"; - status = "disabled"; - reg = <0x47>; - type = ; - //pinctrl-names = "default"; - //pinctrl-0 = <&gpio3_c6>; - //irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>; - //irq_enable = <1>; - ps_threshold_high = <0x200>; - ps_threshold_low = <0x100>; - ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */ - ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/ - poll_delay_ms = <100>; - }; - - mpu6500_acc: mpu_acc@68 { - compatible = "mpu6500_acc"; - reg = <0x68>; - irq-gpio = <&gpio3 RK_PB4 IRQ_TYPE_EDGE_RISING>; - irq_enable = <0>; - poll_delay_ms = <30>; - type = ; - layout = <5>; - }; - - mpu6500_gyro: mpu_gyro@68 { - compatible = "mpu6500_gyro"; - reg = <0x68>; - poll_delay_ms = <30>; - type = ; - layout = <5>; - }; -}; - -&i2c8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8m2_xfer>; - - usbc0: fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vbus5v0_typec>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - ; - source-pdos = - ; - - altmodes { - #address-cells = <1>; - #size-cells = <0>; - - altmode@0 { - reg = <0>; - svid = <0xff01>; - vdo = <0xffffffff>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; - }; - }; - - port@1 { - reg = <1>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; - }; - }; - }; - }; - }; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&pcie2x1l1 { - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie20>; - status = "okay"; -}; - -&pcie2x1l2 { - reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; - rockchip,skip-scan-in-resume; - status = "okay"; -}; - -&pdm0 { - status = "okay"; -}; - -&pinctrl { - headphone { - hp_det: hp-det { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lcd { - lcd_rst_gpio: lcd-rst-gpio { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - aw883x { - aw_rst1_gpio: aw-rst1-gpio { - rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - aw_rst2_gpio: aw-rst2-gpio { - rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - aw_rst3_gpio: aw-rst3-gpio { - rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - aw_rst4_gpio: aw-rst4-gpio { - rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sensor { - mh248_irq_gpio: mh248_irq_gpio { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - mpu6500_irq_gpio: mpu6500_irq_gpio { - rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - usbc0_int: usbc0-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - typec5v_pwren: typec5v-pwren { - rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-bluetooth { - uart8_gpios: uart8-gpios { - rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_gpio: bt-gpio { - rockchip,pins = - <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, - <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>, - <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - wifi_poweren_gpio: wifi-poweren-gpio { - rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm3 { - compatible = "rockchip,remotectl-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3m3_pins>; - remote_pwm_id = <3>; - handle_cpu_id = <1>; - remote_support_psci = <0>; - status = "okay"; - - ir_key1 { - rockchip,usercode = <0x4040>; - rockchip,key_table = - <0xf2 KEY_REPLY>, - <0xba KEY_BACK>, - <0xf4 KEY_UP>, - <0xf1 KEY_DOWN>, - <0xef KEY_LEFT>, - <0xee KEY_RIGHT>, - <0xbd KEY_HOME>, - <0xea KEY_VOLUMEUP>, - <0xe3 KEY_VOLUMEDOWN>, - <0xe2 KEY_SEARCH>, - <0xb2 KEY_POWER>, - <0xbc KEY_MUTE>, - <0xec KEY_MENU>, - <0xbf 0x190>, - <0xe0 0x191>, - <0xe1 0x192>, - <0xe9 183>, - <0xe6 248>, - <0xe8 185>, - <0xe7 186>, - <0xf0 388>, - <0xbe 0x175>; - }; - - ir_key2 { - rockchip,usercode = <0xff00>; - rockchip,key_table = - <0xf9 KEY_HOME>, - <0xbf KEY_BACK>, - <0xfb KEY_MENU>, - <0xaa KEY_REPLY>, - <0xb9 KEY_UP>, - <0xe9 KEY_DOWN>, - <0xb8 KEY_LEFT>, - <0xea KEY_RIGHT>, - <0xeb KEY_VOLUMEDOWN>, - <0xef KEY_VOLUMEUP>, - <0xf7 KEY_MUTE>, - <0xe7 KEY_POWER>, - <0xfc KEY_POWER>, - <0xa9 KEY_VOLUMEDOWN>, - <0xa8 KEY_PLAYPAUSE>, - <0xe0 KEY_VOLUMEDOWN>, - <0xa5 KEY_VOLUMEDOWN>, - <0xab 183>, - <0xb7 388>, - <0xe8 388>, - <0xf8 184>, - <0xaf 185>, - <0xed KEY_VOLUMEDOWN>, - <0xee 186>, - <0xb3 KEY_VOLUMEDOWN>, - <0xf1 KEY_VOLUMEDOWN>, - <0xf2 KEY_VOLUMEDOWN>, - <0xf3 KEY_SEARCH>, - <0xb4 KEY_VOLUMEDOWN>, - <0xa4 KEY_SETUP>, - <0xbe KEY_SEARCH>; - }; - - ir_key3 { - rockchip,usercode = <0x1dcc>; - rockchip,key_table = - <0xee KEY_REPLY>, - <0xf0 KEY_BACK>, - <0xf8 KEY_UP>, - <0xbb KEY_DOWN>, - <0xef KEY_LEFT>, - <0xed KEY_RIGHT>, - <0xfc KEY_HOME>, - <0xf1 KEY_VOLUMEUP>, - <0xfd KEY_VOLUMEDOWN>, - <0xb7 KEY_SEARCH>, - <0xff KEY_POWER>, - <0xf3 KEY_MUTE>, - <0xbf KEY_MENU>, - <0xf9 0x191>, - <0xf5 0x192>, - <0xb3 388>, - <0xbe KEY_1>, - <0xba KEY_2>, - <0xb2 KEY_3>, - <0xbd KEY_4>, - <0xf9 KEY_5>, - <0xb1 KEY_6>, - <0xfc KEY_7>, - <0xf8 KEY_8>, - <0xb0 KEY_9>, - <0xb6 KEY_0>, - <0xb5 KEY_BACKSPACE>; - }; -}; - -&pwm11 { - pinctrl-0 = <&pwm11m1_pins>; - status = "okay"; -}; - -&pwm12 { - pinctrl-0 = <&pwm12m1_pins>; - status = "okay"; -}; - -&route_edp0 { - connect = <&vp2_out_edp0>; - status = "okay"; -}; - -&sdmmc { - status = "okay"; -}; - -&spdif_tx1 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif1m1_tx>; -}; - -&spdif_tx1_dc { - status = "okay"; -}; - -&spdif_tx1_sound { - status = "okay"; -}; - -&spdif_tx2 { - status = "okay"; -}; - -&u2phy0_otg { - rockchip,typec-vbus-det; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; -}; - -&uart8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>; -}; - -&usbdp_phy0 { - orientation-switch; - svid = <0xff01>; - sbu1-dc-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>; - - port { - #address-cells = <1>; - #size-cells = <0>; - usbdp_phy0_orientation_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; - }; - - usbdp_phy0_dp_altmode_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&dp_altmode_mux>; - }; - }; -}; - -&usbdrd_dwc3_0 { - usb-role-switch; - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -&usbhost3_0 { - status = "disabled"; -}; - -&usbhost_dwc3_0 { - status = "disabled"; -}; - -/* vp0 & vp3 are not used on this board */ -&vp0 { - /delete-property/ rockchip,plane-mask; - /delete-property/ rockchip,primary-plane; -}; - -&vp1 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | - 1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; - rockchip,primary-plane = ; -}; - -&vp2 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2 | - 1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; - rockchip,primary-plane = ; -}; - -&vp3 { - /delete-property/ rockchip,plane-mask; - /delete-property/ rockchip,primary-plane; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5-v10-linux.dts deleted file mode 100644 index 2dcd6a6b1..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5-v10-linux.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588s-evb2-lp5.dtsi" -#include "rk3588-linux.dtsi" - -/ { - model = "Rockchip RK3588S EVB2 LP5 V10 Board"; - compatible = "rockchip,rk3588s-evb2-lp5-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5-v10.dts deleted file mode 100644 index b34c15e58..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5-v10.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588s-evb2-lp5.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588S EVB2 LP5 V10 Board"; - compatible = "rockchip,rk3588s-evb2-lp5-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5.dtsi deleted file mode 100644 index d2a17c411..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb2-lp5.dtsi +++ /dev/null @@ -1,952 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include "rk3588s.dtsi" -#include "rk3588s-evb.dtsi" -#include "rk3588s-rk806-dual.dtsi" - -/ { - es7202_sound_micarray: es7202-sound-micarray { - status = "okay"; - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip,sound-micarray"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,dai-link@0 { - format = "pdm"; - cpu { - sound-dai = <&pdm0>; - }; - codec { - sound-dai = <&es7202>; - }; - }; - }; - - es8388_sound: es8388-sound { - status = "okay"; - compatible = "rockchip,multicodecs-card"; - rockchip,card-name = "rockchip-es8388"; - hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; - io-channels = <&saradc 3>; - io-channel-names = "adc-detect"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - spk-con-gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - hp-con-gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; - rockchip,format = "i2s"; - rockchip,mclk-fs = <256>; - rockchip,cpu = <&i2s0_8ch>; - rockchip,codec = <&es8388>; - rockchip,audio-routing = - "Headphone", "LOUT1", - "Headphone", "ROUT1", - "Speaker", "LOUT2", - "Speaker", "ROUT2", - "Headphone", "Headphone Power", - "Headphone", "Headphone Power", - "Speaker", "Speaker Power", - "Speaker", "Speaker Power", - "LINPUT1", "Main Mic", - "LINPUT2", "Main Mic", - "RINPUT1", "Headset Mic", - "RINPUT2", "Headset Mic"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - play-pause-key { - label = "playpause"; - linux,code = ; - press-threshold-microvolt = <2000>; - }; - }; - - vbus5v0_typec: vbus5v0-typec { - compatible = "regulator-fixed"; - regulator-name = "vbus5v0_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; - }; - - vcc3v3_lcd_n: vcc3v3-lcd0-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd0_n"; - regulator-boot-on; - enable-active-high; - gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc_1v8_s0>; - }; - - vcc5v0_u2host: vcc5v0-u2host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_u2host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_u2host_en>; - }; - - vcc5v0_u3host: vcc5v0-u3host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_u3host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_u3host_en>; - }; -}; - -&backlight { - pwms = <&pwm7 0 25000 0>; - status = "okay"; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&dp0 { - pinctrl-0 = <&dp0m2_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&dp0_in_vp2 { - status = "okay"; -}; - -/* - * mipi_dcphy0 needs to be enabled - * when dsi0 is enabled - */ -&dsi0 { - status = "disabled"; -}; - -&dsi0_in_vp2 { - status = "disabled"; -}; - -&dsi0_in_vp3 { - status = "disabled"; -}; - -&dsi0_panel { - power-supply = <&vcc3v3_lcd_n>; - - /* - * because in hardware, the two screens share the reset pin, - * so reset-gpios need only in dsi0 enable and dsi1 disabled - * case. - */ - //reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; - //pinctrl-names = "default"; - //pinctrl-0 = <&lcd_rst_gpio>; - phy-c-option; - dsi,lanes = <3>; - - panel-init-sequence = [ - 23 00 02 FF 20 - 23 00 02 FB 01 - 23 00 02 05 D9 - /* VGH=17V */ - 23 00 02 07 78 - /* VGL=-14V */ - 23 00 02 08 5A - /* EN_VMODGATE2=1 */ - 23 00 02 0D 63 - /* VGH=16V */ - 23 00 02 0E 91 - /* VGL=-13V */ - 23 00 02 0F 73 - /* GVDD=5.2V */ - 23 00 02 95 EB - 23 00 02 96 EB - /* Disable VDDI LV */ - 23 00 02 30 11 - /* ISOP */ - 23 00 02 6D 66 - /* EN_GMACP */ - 23 00 02 75 A2 - /* V128 */ - 23 00 02 77 3B - /* R(+) */ - 29 00 11 B0 00 08 00 23 00 4D 00 6D 00 89 00 A1 00 B6 00 C9 - 29 00 11 B1 00 DA 01 13 01 3C 01 7E 01 AB 01 F7 02 2F 02 31 - 29 00 11 B2 02 67 02 A6 02 D1 03 08 03 2E 03 5B 03 6B 03 7B - 29 00 0D B3 03 8E 03 A2 03 B7 03 E7 03 FD 03 FF - /* G(+) */ - 29 00 11 B4 00 08 00 23 00 4D 00 6D 00 89 00 A1 00 B6 00 C9 - 29 00 11 B5 00 DA 01 13 01 3C 01 7E 01 AB 01 F7 02 2F 02 31 - 29 00 11 B6 02 67 02 A6 02 D1 03 08 03 2E 03 5B 03 6B 03 7B - 29 00 0D B7 03 8E 03 A2 03 B7 03 E7 03 FD 03 FF - /* B(+) */ - 29 00 11 B8 00 08 00 23 00 4D 00 6D 00 89 00 A1 00 B6 00 C9 - 29 00 11 B9 00 DA 01 13 01 3C 01 7E 01 AB 01 F7 02 2F 02 31 - 29 00 11 BA 02 67 02 A6 02 D1 03 08 03 2E 03 5B 03 6B 03 7B - 29 00 0D BB 03 8E 03 A2 03 B7 03 E7 03 FD 03 FF - /* CMD2_Page1 */ - 23 00 02 FF 21 - 23 00 02 FB 01 - /* R(-) */ - 29 00 11 B0 00 00 00 1B 00 45 00 65 00 81 00 99 00 AE 00 C1 - 29 00 11 B1 00 D2 01 0B 01 34 01 76 01 A3 01 EF 02 27 02 29 - 29 00 11 B2 02 5F 02 9E 02 C9 03 00 03 26 03 53 03 63 03 73 - 29 00 0D B3 03 86 03 9A 03 AF 03 DF 03 F5 03 F7 - /* G(-) */ - 29 00 11 B4 00 00 00 1B 00 45 00 65 00 81 00 99 00 AE 00 C1 - 29 00 11 B5 00 D2 01 0B 01 34 01 76 01 A3 01 EF 02 27 02 29 - 29 00 11 B6 02 5F 02 9E 02 C9 03 00 03 26 03 53 03 63 03 73 - 29 00 0D B7 03 86 03 9A 03 AF 03 DF 03 F5 03 F7 - /* B(-) */ - 29 00 11 B8 00 00 00 1B 00 45 00 65 00 81 00 99 00 AE 00 C1 - 29 00 11 B9 00 D2 01 0B 01 34 01 76 01 A3 01 EF 02 27 02 29 - 29 00 11 BA 02 5F 02 9E 02 C9 03 00 03 26 03 53 03 63 03 73 - 29 00 0D BB 03 86 03 9A 03 AF 03 DF 03 F5 03 F7 - - 29 00 02 FF 24 - 29 00 02 FB 01 - /* VGL */ - 29 00 02 00 00 - 29 00 02 01 00 - /* VDDO */ - 29 00 02 02 1C - 29 00 02 03 1C - /* VDDE */ - 29 00 02 04 1D - 29 00 02 05 1D - /* STV0 */ - 29 00 02 06 04 - 29 00 02 07 04 - /* CLK8 */ - 29 00 02 08 0F - 29 00 02 09 0F - /* CLK6 */ - 29 00 02 0A 0E - 29 00 02 0B 0E - /* CLK4 */ - 29 00 02 0C 0D - 29 00 02 0D 0D - /* CLK2 */ - 29 00 02 0E 0C - 29 00 02 0F 0C - /* STV2 */ - 29 00 02 10 08 - 29 00 02 11 08 - - 29 00 02 12 00 - 29 00 02 13 00 - 29 00 02 14 00 - 29 00 02 15 00 - /* VGL */ - 29 00 02 16 00 - 29 00 02 17 00 - /* VDDO */ - 29 00 02 18 1C - 29 00 02 19 1C - /* VDDE */ - 29 00 02 1A 1D - 29 00 02 1B 1D - /* STV0 */ - 29 00 02 1C 04 - 29 00 02 1D 04 - /* CLK7 */ - 29 00 02 1E 0F - 29 00 02 1F 0F - /* CLK5 */ - 29 00 02 20 0E - 29 00 02 21 0E - /* CLK3 */ - 29 00 02 22 0D - 29 00 02 23 0D - /* CLK1 */ - 29 00 02 24 0C - 29 00 02 25 0C - /* STV1 */ - 29 00 02 26 08 - 29 00 02 27 08 - - 29 00 02 28 00 - 29 00 02 29 00 - 29 00 02 2A 00 - 29 00 02 2B 00 - /* STV0 */ - 29 00 02 2D 20 - 29 00 02 2F 0A - 29 00 02 30 44 - 29 00 02 33 0C - 29 00 02 34 32 - - 29 00 02 37 44 - 29 00 02 38 40 - 29 00 02 39 00 - 29 00 02 3A 50 - 29 00 02 3B 50 - 29 00 02 3D 42 - /* STV */ - 29 00 02 3F 06 - 29 00 02 43 06 - - 29 00 02 47 66 - 29 00 02 4A 50 - 29 00 02 4B 50 - 29 00 02 4C 91 - /* GCK */ - 29 00 02 4D 21 - 29 00 02 4E 43 - 29 00 02 51 12 - 29 00 02 52 34 - 29 00 03 55 82 02 - 29 00 02 56 04 - 29 00 02 58 21 - 29 00 02 59 30 - 29 00 02 5A 50 - 29 00 02 5B 50 - 29 00 03 5E 00 06 - 29 00 02 5F 00 - /* EN_LFD_SOURCE=0 */ - 29 00 02 65 82 - /* VDDO, VDDE */ - 29 00 02 7E 20 - 29 00 02 7F 3C - 29 00 02 82 04 - 29 00 02 97 C0 - - 29 00 0D B6 05 00 05 00 00 00 00 00 05 05 00 00 - /* qclk=96/5 Mhz */ - 29 00 02 91 44 - 29 00 02 92 55 - 29 00 02 93 1A - 29 00 02 94 5F - /* SOG_HBP */ - 29 00 02 D7 55 - 29 00 02 DA 0A - 29 00 02 DE 08 - /* Normal */ - 29 00 02 DB 05 - 29 00 02 DC 55 - 29 00 02 DD 22 - /* Line N */ - 29 00 02 DF 05 - 29 00 02 E0 55 - /* Line N+1 */ - 29 00 02 E1 05 - 29 00 02 E2 55 - /* TP0 */ - 29 00 02 E3 05 - 29 00 02 E4 55 - /* TP3 */ - 29 00 02 E5 05 - 29 00 02 E6 55 - /* Gate EQ */ - 29 00 02 5C 00 - 29 00 02 5D 00 - /* TP3 */ - 29 00 02 8D 00 - 29 00 02 8E 00 - /* No Sync @ TP */ - 29 00 02 B5 90 - - 29 00 02 FF 25 - 29 00 02 FB 01 - /* disable auto_vbp_vfp */ - 29 00 02 05 00 - /* ESD_DET_ERR_SEL */ - 29 00 02 19 07 - /* DP_N_GCK */ - 29 00 02 1F 50 - 29 00 02 20 50 - /* DP_N_1_GCK */ - 29 00 02 26 50 - 29 00 02 27 50 - /* TP0_GCK */ - 29 00 02 33 50 - 29 00 02 34 50 - /* TP3 GCK/MUX=1 */ - 29 00 02 3F E0 - /* TP3_GCK_START_LINE */ - 29 00 02 40 00 - /* TP3_STV */ - 29 00 02 44 00 - 29 00 02 45 40 - /* TP3_GCK */ - 29 00 02 48 50 - 29 00 02 49 50 - /* LSTP0 */ - 29 00 02 5B 00 - 29 00 02 5C 00 - 29 00 02 5D 00 - 29 00 02 5E D0 - - 29 00 02 61 50 - 29 00 02 62 50 - /* en_vfp_addvsync */ - 29 00 02 F1 10 - /* CMD2,Page10 */ - 29 00 02 FF 2A - 29 00 02 FB 01 - /* PWRONOFF */ - /* STV */ - 29 00 02 64 16 - /* CLR */ - 29 00 02 67 16 - /* GCK */ - 29 00 02 6A 16 - /* POL */ - 29 00 02 70 30 - /* ABOFF */ - 29 00 02 A2 F3 - 29 00 02 A3 FF - 29 00 02 A4 FF - 29 00 02 A5 FF - /* Long_V_TIMING disable */ - 29 00 02 D6 08 - /* CMD2,Page6 */ - 29 00 02 FF 26 - 29 00 02 FB 01 - /* TPEN */ - 29 00 02 00 81 - /* 90Hz */ - 29 00 02 01 30 - - 29 00 02 02 31 - 29 00 02 0A F2 - //Table A (90Hz) - 29 00 02 04 28 - 29 00 02 06 3C - 29 00 02 0C 0B - 29 00 02 0D 0C - 29 00 02 0F 00 - 29 00 02 11 00 - 29 00 02 12 50 - 29 00 02 13 AE - 29 00 02 14 A6 - 29 00 02 16 10 - 29 00 02 19 08 - 29 00 02 1A FF - 29 00 02 1B 08 - 29 00 02 1C 80 - 29 00 02 22 00 - 29 00 02 23 00 - 29 00 02 2A 08 - 29 00 02 2B FF - - 29 00 02 1D 00 - 29 00 02 1E 55 - 29 00 02 1F 55 - 29 00 02 24 00 - 29 00 02 25 55 - 29 00 02 2F 05 - 29 00 02 30 55 - 29 00 02 31 05 - 29 00 02 32 6D - 29 00 02 39 00 - 29 00 02 3A 55 - /* Table B (60Hz,81*1+101*19=2000, Extra=20) */ - 29 00 02 8B 28 - 29 00 02 8C 13 - 29 00 02 8D 0A - 29 00 02 8F 0A - 29 00 02 91 00 - 29 00 02 92 50 - 29 00 02 93 51 - 29 00 02 94 65 - 29 00 02 96 10 - 29 00 02 99 0A - 29 00 02 9A 7F - 29 00 02 9B 0A - 29 00 02 9C 0C - 29 00 02 9D 0A - 29 00 02 9E 7F - - 29 00 02 3F 00 - 29 00 02 40 75 - 29 00 02 41 75 - 29 00 02 42 75 - 29 00 02 43 00 - 29 00 02 44 75 - 29 00 02 45 05 - 29 00 02 46 75 - 29 00 02 47 05 - 29 00 02 48 8D - 29 00 02 49 00 - 29 00 02 4A 75 - /* STV0 */ - 29 00 02 4D 5D - 29 00 02 4E 60 - /* STV */ - 29 00 02 4F 5D - 29 00 02 50 60 - /* GCK */ - 29 00 02 51 70 - 29 00 02 52 60 - /* DP_N_GCK */ - 29 00 02 56 70 - 29 00 02 58 60 - /* DP_N_1_GCK */ - 29 00 02 5B 70 - 29 00 02 5C 60 - /* TP0_GCK */ - 29 00 02 60 70 - 29 00 02 61 60 - /* TP3_GCK */ - 29 00 02 64 70 - 29 00 02 65 60 - /* LSTP0 */ - 29 00 02 72 70 - 29 00 02 73 60 - /* PRZ1 */ - 29 00 02 20 01 - /* PRZ3 */ - /* Rescan=3 */ - 29 00 02 33 11 - 29 00 02 34 78 - 29 00 02 35 16 - /* DLH */ - 29 00 02 C8 04 - 29 00 02 C9 80 - 29 00 02 CA 4E - 29 00 02 CB 00 - 29 00 02 A9 4C - 29 00 02 AA 47 - /* CMD2,Page7 */ - 29 00 02 FF 27 - 29 00 02 FB 01 - /* VPOR_DYNH_EN=1, VPOR_CNT_REV=1 */ - 29 00 02 56 06 - /* FR0(60Hz) */ - 29 00 02 58 80 - 29 00 02 59 53 - 29 00 02 5A 00 - 29 00 02 5B 14 - 29 00 02 5C 00 - 29 00 02 5D 01 - 29 00 02 5E 20 - 29 00 02 5F 10 - 29 00 02 60 00 - 29 00 02 61 1D - 29 00 02 62 00 - 29 00 02 63 01 - 29 00 02 64 24 - 29 00 02 65 1C - 29 00 02 66 00 - 29 00 02 67 01 - 29 00 02 68 25 - /* FR1(90Hz) */ - 29 00 02 78 80 - 29 00 02 79 73 - 29 00 02 7A 00 - 29 00 02 7B 14 - 29 00 02 7C 00 - 29 00 02 7D 02 - 29 00 02 7E 20 - 29 00 02 7F 21 - 29 00 02 80 00 - 29 00 02 81 2A - 29 00 02 82 00 - 29 00 02 83 01 - 29 00 02 84 1C - 29 00 02 85 28 - 29 00 02 86 00 - 29 00 02 87 01 - 29 00 02 88 1D - - 29 00 02 00 00 - 29 00 02 C3 00 - /* FTE output TE, FTE1 output TSVD, LEDPWM output TSHD */ - 29 00 02 D1 24 - 29 00 02 D2 53 - /* CMD2,Page10 */ - 29 00 02 FF 2A - 29 00 02 FB 01 - 29 00 02 01 05 - 29 00 02 02 55 - /* TP0 */ - 29 00 02 03 05 - 29 00 02 04 75 - /* TP3 */ - 29 00 02 05 05 - 29 00 02 06 75 - /* PEN_EN=1, UL_FREQ=0 */ - 29 00 02 22 2F - /* 90Hz */ - 29 00 02 23 11 - /* FR0 (60Hz) */ - 29 00 02 24 00 - 29 00 02 25 75 - 29 00 02 27 00 - 29 00 02 28 1A - 29 00 02 29 00 - 29 00 02 2A 1A - 29 00 02 2B 00 - 29 00 02 2D 1A - /* FR1 (90Hz) */ - 29 00 02 2F 00 - 29 00 02 30 55 - 29 00 02 32 00 - 29 00 02 33 1A - 29 00 02 34 00 - 29 00 02 35 1A - 29 00 02 36 00 - 29 00 02 37 1A - /* CMD2,Page3 */ - 29 00 02 FF 23 - 29 00 02 FB 01 - /* DBV=12 bit */ - 29 00 02 00 80 - /* PWM frequency */ - 29 00 02 07 00 - /* CMD3,PageA */ - 29 00 02 FF E0 - 29 00 02 FB 01 - /* VCOM Driving Ability */ - 29 00 02 14 60 - 29 00 02 16 C0 - /* CMD3,PageB */ - 29 00 02 FF F0 - 29 00 02 FB 01 - /* slave osc workaround */ - 29 00 02 3A 08 - /* CMD3,PageC */ - 29 00 02 FF D0 - 29 00 02 FB 01 - 29 00 02 1C 88 - 29 00 02 1D 08 - /* CMD1 */ - 29 00 02 FF 10 - 29 00 02 FB 01 - /* Only Write Slave */ - 29 00 02 B9 01 - /* CMD2,Page0 */ - 29 00 02 FF 20 - 29 00 02 FB 01 - 29 00 02 18 40 - /* CMD1 */ - 29 00 02 FF 10 - 29 00 02 FB 01 - /* Write Master & Slave */ - 29 00 02 B9 02 - 29 00 02 35 00 - 29 00 03 51 00 FF - 29 00 02 53 24 - 29 00 02 55 00 - 29 00 02 BB 13 - /* VBP+VFP=121 */ - 29 00 06 3B 03 5F 1A 04 04 - /* CMD2,Page5 */ - 29 00 02 FF 25 - /* FRM */ - 29 00 02 EC 00 - /* CMD1 */ - 29 00 02 FF 10 - 29 00 02 FB 01 - 05 FF 01 11 - 05 FF 01 29 - ]; - - panel-exit-sequence = [ - 05 00 01 28 - 05 00 01 10 - ]; - - disp_timings0: display-timings { - native-mode = <&dsi0_timing0>; - dsi0_timing0: timing0 { - clock-frequency = <241300000>; - hactive = <1200>; - vactive = <2000>; - hfront-porch = <31>; - hsync-len = <4>; - hback-porch = <32>; - vfront-porch = <26>; - vsync-len = <2>; - vback-porch = <93>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; -}; - -/* - * mipi_dcphy1 needs to be enabled - * when dsi1 is enabled - */ -&dsi1 { - status = "okay"; -}; - -&dsi1_in_vp2 { - status = "disabled"; -}; - -&dsi1_in_vp3 { - status = "okay"; -}; - -&dsi1_panel { - power-supply = <&vcc3v3_lcd_n>; - - reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rst_gpio>; -}; - -&hdmi0 { - enable-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&hdmi0_in_vp0 { - status = "okay"; -}; - -&hdmi0_sound { - status = "okay"; -}; - -&hdptxphy_hdmi0 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&i2c5 { - status = "okay"; - - ls_stk3332: light@47 { - compatible = "ls_stk3332"; - status = "disabled"; - reg = <0x47>; - type = ; - irq_enable = <0>; - als_threshold_high = <100>; - als_threshold_low = <10>; - als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ - poll_delay_ms = <100>; - }; - - ps_stk3332: proximity@47 { - compatible = "ps_stk3332"; - status = "disabled"; - reg = <0x47>; - type = ; - //pinctrl-names = "default"; - //pinctrl-0 = <&gpio3_c6>; - //irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>; - //irq_enable = <1>; - ps_threshold_high = <0x200>; - ps_threshold_low = <0x100>; - ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */ - ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/ - poll_delay_ms = <100>; - }; - - mpu6500_acc: mpu_acc@68 { - compatible = "mpu6500_acc"; - reg = <0x68>; - irq-gpio = <&gpio3 RK_PB4 IRQ_TYPE_EDGE_RISING>; - irq_enable = <0>; - poll_delay_ms = <30>; - type = ; - layout = <8>; - }; - - mpu6500_gyro: mpu_gyro@68 { - compatible = "mpu6500_gyro"; - reg = <0x68>; - irq_enable = <0>; - poll_delay_ms = <30>; - type = ; - layout = <8>; - }; -}; - -&i2c6 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6m3_xfer>; - - gt1x: gt1x@14 { - compatible = "goodix,gt1x"; - reg = <0x14>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_gpio>; - goodix,rst-gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - goodix,irq-gpio = <&gpio4 RK_PB4 IRQ_TYPE_LEVEL_LOW>; - power-supply = <&vcc3v3_lcd_n>; - }; -}; - -&i2c3 { - status = "okay"; - - es8388: es8388@11 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "everest,es8388", "everest,es8323"; - reg = <0x11>; - clocks = <&mclkout_i2s0>; - clock-names = "mclk"; - assigned-clocks = <&mclkout_i2s0>; - assigned-clock-rates = <12288000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk>; - }; - - es7202: es7202@32 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "ES7202_PDM_ADC_1"; - power-supply = <&vcc_1v8_s0>; /* only 1v8 or 3v3, default is 3v3 */ - reg = <0x32>; - }; -}; - -&i2s5_8ch { - status = "okay"; -}; - -&mipi_dcphy0 { - status = "disabled"; -}; - -&mipi_dcphy1 { - status = "okay"; -}; - -&sdmmc { - status = "okay"; - vmmc-supply = <&vcc_3v3_sd_s0>; -}; - -&pdm0 { - status = "okay"; -}; - -&pinctrl { - headphone { - hp_det: hp-det { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lcd { - lcd_rst_gpio: lcd-rst-gpio { - rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sensor { - mpu6500_irq_gpio: mpu6500_irq_gpio { - rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - touch { - touch_gpio: touch-gpio { - rockchip,pins = - <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, - <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - typec5v_pwren: typec5v-pwren { - rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_u2host_en: vcc5v0-u2host-en { - rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_u3host_en: vcc5v0-u3host-en { - rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm7 { - status = "okay"; -}; - -&route_dsi0 { - status = "disabled"; - connect = <&vp3_out_dsi0>; -}; - -&route_dsi1 { - status = "okay"; - connect = <&vp3_out_dsi1>; -}; - -&sata0 { - status = "okay"; -}; - -&u2phy0_otg { - vbus-supply = <&vbus5v0_typec>; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_u2host>; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_u3host>; -}; - -&usbdp_phy0 { - rockchip,dp-lane-mux = <0 1 2 3>; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - phys = <&u2phy0_otg>; - phy-names = "usb2-phy"; - maximum-speed = "high-speed"; - extcon = <&u2phy0>; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x-v10-linux.dts deleted file mode 100644 index 2db625042..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x-v10-linux.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588s-evb3-lp4x.dtsi" -#include "rk3588-linux.dtsi" - -/ { - model = "Rockchip RK3588S EVB3 LP4X V10 Board"; - compatible = "rockchip,rk3588s-evb3-lp4x-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x-v10-nvp6158-ahd-to-bt1120.dts b/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x-v10-nvp6158-ahd-to-bt1120.dts deleted file mode 100644 index abd332a83..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x-v10-nvp6158-ahd-to-bt1120.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include -#include "rk3588s-evb3-lp4x.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588S EVB3 LP4 V10 Board + Rockchip RK3588S EVB V10 Extboard"; - compatible = "rockchip,rk3588s-evb3-lp4x-v10-nvp6158-ahd-to-bt1120", "rockchip,rk3588"; -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2m4_xfer>; - - nvp6158: nvp6158@30 { - compatible = "nvp6158-v4l2"; - status = "okay"; - reg = <0x30>; - clocks = <&cru CLK_CIFOUT_OUT>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - pinctrl-names = "default"; - pinctrl-0 = <&cif_clk &cif_dvp_clk &cif_dvp_bus8 &cif_dvp_bus16>; - // pwr-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; - pwr2-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; - rst-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - // rst2-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; - // pwdn-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - // pwdn2-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "default"; - rockchip,camera-module-lens-name = "default"; - rockchip,dvp_mode = "BT1120"; //BT656 or BT1120 or BT656_TEST - rockchip,channel_nums = <4>; //channel nums, 1/2/4 - rockchip,dual_edge = <1>; // pclk dual edge, 0/1 - rockchip,default_rect= <1920 1080>; // default resolution - port { - nvp6158_out: endpoint { - remote-endpoint = <&dvp_in_bcam1>; - }; - }; - }; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_dvp { - status = "okay"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - /* Parallel bus endpoint */ - dvp_in_bcam1: endpoint@1 { - reg = <1>; - remote-endpoint = <&nvp6158_out>; - bus-width = <16>; - }; - }; - }; -}; - -&rkcif_mmu { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x-v10-rk630-bt656-to-cvbs.dts b/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x-v10-rk630-bt656-to-cvbs.dts deleted file mode 100644 index 5d6a840d8..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x-v10-rk630-bt656-to-cvbs.dts +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include -#include "rk3588s-evb3-lp4x.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588S EVB3 LP4 V10 Board + Rockchip RK3588S EVB V10 Extboard1"; - compatible = "rockchip,rk3588s-evb3-lp4x-v10-rk630-bt656-to-cvbs", "rockchip,rk3588"; -}; - -&dsi0_in_vp3 { - status = "disabled"; -}; - -&i2c4 { - status = "okay"; - clock-frequency = <100000>; - - rk630: rk630@50 { - compatible = "rockchip,rk630"; - reg = <0x50>; - reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>; - status = "okay"; - - rk630_tve: rk630-tve { - compatible = "rockchip,rk630-tve"; - status = "okay"; - - ports { - port { - rk630_tve_in_rgb: endpoint { - remote-endpoint = <&rgb_out_rk630_tve>; - }; - }; - }; - }; - }; -}; - -&rgb { - pinctrl-names = "default"; - pinctrl-0 = <&bt656_pins>; - status = "okay"; - - ports { - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - rgb_out_rk630_tve: endpoint@0 { - reg = <0>; - remote-endpoint = <&rk630_tve_in_rgb>; - }; - }; - }; -}; - -&rgb_in_vp3 { - status = "okay"; -}; - -&vop { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x-v10-sii9022-bt1120-to-hdmi.dts b/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x-v10-sii9022-bt1120-to-hdmi.dts deleted file mode 100644 index e2d5f25d5..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x-v10-sii9022-bt1120-to-hdmi.dts +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include -#include "rk3588s-evb3-lp4x.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588S EVB3 LP4 V10 Board + Rockchip RK3588S EVB V10 Extboard2"; - compatible = "rockchip,rk3588s-evb3-lp4x-v10-sii9022-bt1120-to-hdmi", "rockchip,rk3588"; -}; - -&dsi0_in_vp3 { - status = "disabled"; -}; - -&i2c4 { - clock-frequency = <400000>; - status = "okay"; - - sii9022: sii9022@39 { - compatible = "sil,sii9022"; - reg = <0x39>; - pinctrl-names = "default"; - pinctrl-0 = <&sii902x_hdmi_int>; - interrupt-parent = <&gpio3>; - interrupts = ; - reset-gpio = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>; - enable-gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; - bus-format = ; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sii9022_in_rgb: endpoint { - remote-endpoint = <&rgb_out_sii9022>; - }; - }; - }; - }; -}; - -&pinctrl { - sii902x { - sii902x_hdmi_int: sii902x-hdmi-int { - rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&rgb { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&bt1120_pins>; - - ports { - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - rgb_out_sii9022: endpoint@0 { - reg = <0>; - remote-endpoint = <&sii9022_in_rgb>; - }; - }; - }; -}; - -&rgb_in_vp3 { - status = "okay"; -}; - -&vop { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x-v10.dts deleted file mode 100644 index 8f42839cf..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x-v10.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588s-evb3-lp4x.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588S EVB3 LP4X V10 Board"; - compatible = "rockchip,rk3588s-evb3-lp4x-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x.dtsi deleted file mode 100644 index cfdbcae8c..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb3-lp4x.dtsi +++ /dev/null @@ -1,367 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include "dt-bindings/usb/pd.h" -#include "rk3588s.dtsi" -#include "rk3588s-evb.dtsi" -#include "rk3588s-rk806-dual.dtsi" - -/ { - combophy_avdd0v85: combophy-avdd0v85 { - compatible = "regulator-fixed"; - regulator-name = "combophy_avdd0v85"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&vdd_0v85_s0>; - }; - - combophy_avdd1v8: combophy-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "combophy_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - pwms = <&pwm7 0 50000 0>; - cooling-levels = <0 50 100 150 200 255>; - rockchip,temp-trips = < - 50000 1 - 55000 2 - 60000 3 - 65000 4 - 70000 5 - >; - }; - - vcc3v3_lcd_n: vcc3v3-lcd0-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd0_n"; - regulator-boot-on; - enable-active-high; - gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc_1v8_s0>; - }; - - vcc3v3_pcie20: vcc3v3-pcie20 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie20"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - vin-supply = <&vcc12v_dcin>; - }; - - vbus5v0_typec: vbus5v0-typec { - compatible = "regulator-fixed"; - regulator-name = "vbus5v0_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&dp0 { - status = "okay"; -}; - -&dp0_in_vp2 { - status = "okay"; -}; - -/* - * mipi_dcphy0 needs to be enabled - * when dsi0 is enabled - */ -&dsi0 { - status = "disabled"; -}; - -&dsi0_in_vp2 { - status = "disabled"; -}; - -&dsi0_in_vp3 { - status = "okay"; -}; - -/* - * mipi_dcphy1 needs to be enabled - * when dsi1 is enabled - */ -&dsi1 { - status = "disabled"; -}; - -&dsi1_in_vp2 { - status = "disabled"; -}; - -&dsi1_in_vp3 { - status = "disabled"; -}; - -&i2c2 { - status = "okay"; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&i2c4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4m3_xfer>; - - gt1x: gt1x@14 { - compatible = "goodix,gt1x"; - reg = <0x14>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_gpio>; - goodix,rst-gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - goodix,irq-gpio = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>; - power-supply = <&vcc3v3_lcd_n>; - }; -}; - -&i2c8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8m2_xfer>; - - usbc0: fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vbus5v0_typec>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - ; - source-pdos = - ; - - altmodes { - #address-cells = <1>; - #size-cells = <0>; - - altmode@0 { - reg = <0>; - svid = <0xff01>; - vdo = <0xffffffff>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; - }; - }; - - port@1 { - reg = <1>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; - }; - }; - }; - }; - }; -}; - -&mipi_dcphy0 { - status = "disabled"; -}; - -&mipi_dcphy1 { - status = "disabled"; -}; - -&pcie2x1l2 { - reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie20>; - status = "okay"; -}; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - touch { - touch_gpio: touch-gpio { - rockchip,pins = - <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb-typec { - usbc0_int: usbc0-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - typec5v_pwren: typec5v-pwren { - rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm11 { - status = "okay"; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp3_out_dsi0>; -}; - -&route_dsi1 { - status = "disabled"; - connect = <&vp3_out_dsi1>; -}; - -&sdmmc { - status = "okay"; - vmmc-supply = <&vcc_3v3_sd_s0>; -}; - -&sata2 { - status = "okay"; -}; - -&u2phy0_otg { - rockchip,typec-vbus-det; -}; - -&u2phy2 { - status = "disabled"; -}; - -&u2phy3 { - status = "disabled"; -}; - -&u2phy2_host { - status = "disabled"; -}; - -&u2phy3_host { - status = "disabled"; -}; - -&usb_host0_ehci { - status = "disabled"; -}; - -&usb_host0_ohci { - status = "disabled"; -}; - -&usb_host1_ehci { - status = "disabled"; -}; - -&usb_host1_ohci { - status = "disabled"; -}; - -&usbdp_phy0 { - orientation-switch; - svid = <0xff01>; - sbu1-dc-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>; - - port { - #address-cells = <1>; - #size-cells = <0>; - usbdp_phy0_orientation_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; - }; - - usbdp_phy0_dp_altmode_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&dp_altmode_mux>; - }; - }; -}; - -&usbdrd_dwc3_0 { - usb-role-switch; - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -&usbhost3_0 { - status = "disabled"; -}; - -&usbhost_dwc3_0 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x-v10-linux.dts deleted file mode 100644 index cf1d3241d..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x-v10-linux.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588s-evb4-lp4x.dtsi" -#include "rk3588-linux.dtsi" - -/ { - model = "Rockchip RK3588S EVB4 LP4X V10 Board"; - compatible = "rockchip,rk3588s-evb4-lp4x-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x-v10.dts deleted file mode 100644 index d3f9264d1..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x-v10.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588s-evb4-lp4x.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588S EVB4 LP4X V10 Board"; - compatible = "rockchip,rk3588s-evb4-lp4x-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x.dtsi deleted file mode 100644 index ee707d482..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb4-lp4x.dtsi +++ /dev/null @@ -1,946 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include "dt-bindings/usb/pd.h" -#include "rk3588s.dtsi" -#include "rk3588s-evb.dtsi" -#include "rk3588-rk806-single.dtsi" - -/ { - combophy_avdd0v85: combophy-avdd0v85 { - compatible = "regulator-fixed"; - regulator-name = "combophy_avdd0v85"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&vdd_0v85_s0>; - }; - - combophy_avdd1v8: combophy-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "combophy_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - es7202_sound_micarray: es7202-sound-micarray { - status = "okay"; - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip,sound-micarray"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,dai-link@0 { - format = "pdm"; - cpu { - sound-dai = <&pdm0>; - }; - codec { - sound-dai = <&es7202>; - }; - }; - }; - - es8388_sound: es8388-sound { - status = "okay"; - compatible = "rockchip,multicodecs-card"; - rockchip,card-name = "rockchip-es8388"; - hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; - io-channels = <&saradc 3>; - io-channel-names = "adc-detect"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - spk-con-gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - hp-con-gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; - rockchip,format = "i2s"; - rockchip,mclk-fs = <256>; - rockchip,cpu = <&i2s0_8ch>; - rockchip,codec = <&es8388>; - rockchip,audio-routing = - "Headphone", "LOUT1", - "Headphone", "ROUT1", - "Speaker", "LOUT2", - "Speaker", "ROUT2", - "Headphone", "Headphone Power", - "Headphone", "Headphone Power", - "Speaker", "Speaker Power", - "Speaker", "Speaker Power", - "LINPUT1", "Main Mic", - "LINPUT2", "Main Mic", - "RINPUT1", "Headset Mic", - "RINPUT2", "Headset Mic"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - play-pause-key { - label = "playpause"; - linux,code = ; - press-threshold-microvolt = <2000>; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - pwms = <&pwm11 0 50000 0>; - cooling-levels = <0 50 100 150 200 255>; - rockchip,temp-trips = < - 50000 1 - 55000 2 - 60000 3 - 65000 4 - 70000 5 - >; - }; - - vbus5v0_typec: vbus5v0-typec { - compatible = "regulator-fixed"; - regulator-name = "vbus5v0_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; - }; - - vcc3v3_lcd_n: vcc3v3-lcd0-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd0_n"; - regulator-boot-on; - enable-active-high; - gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc_3v3_s0>; - }; - - vcc3v3_pcie20: vcc3v3-pcie20 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie20"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_host: vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_1v2_cam_s0: vcc-1v2-cam-s0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v2_cam_s0"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vcc_3v3_s3>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_cam_s0: vcc-1v8-cam-s0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v8_cam_s0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc_2v8_cam_s0: vcc-2v8-cam-s0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_2v8_cam_s0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc_3v3_sd_s0: vcc-3v3-sd-s0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_sd_s0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; - enable-active-low; - vin-supply = <&vcc_3v3_s3>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - wireless_bluetooth: wireless-bluetooth { - compatible = "bluetooth-platdata"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "rts_gpio"; - pinctrl-0 = <&uart8m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_wake_host_irq>; - pinctrl-1 = <&uart8_gpios>; - BT,reset_gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; - BT,wake_gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; - BT,wake_host_irq = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - wifi_chip_type = "ap6255"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; - WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - WIFI,poweren_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; -}; - -&backlight { - pwms = <&pwm13 0 25000 0>; - status = "okay"; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&dp0 { - status = "okay"; -}; - -&dp0_in_vp2 { - status = "okay"; -}; - -/* - * mipi_dcphy0 needs to be enabled - * when dsi0 is enabled - */ -&dsi0 { - status = "okay"; -}; - -&dsi0_in_vp2 { - status = "disabled"; -}; - -&dsi0_in_vp3 { - status = "okay"; -}; - -&dsi0_panel { - power-supply = <&vcc3v3_lcd_n>; - reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rst_gpio>; -}; - -/* - * mipi_dcphy1 needs to be enabled - * when dsi1 is enabled - */ -&dsi1 { - //rockchip,lane-rate = <650>; - pinctrl-names = "default"; - pinctrl-0 = <&mipi_te1>; - status = "disabled"; -}; - -&dsi1_in_vp2 { - status = "disabled"; -}; - -&dsi1_in_vp3 { - status = "disabled"; -}; - -&dsi1_panel { - power-supply = <&vcc3v3_lcd_n>; - compressed-data; - /* - * because in hardware, the two screens share the reset pin, - * so reset-gpios need only in dsi1 enable and dsi0 disabled - * case. - */ - - //reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; - //pinctrl-names = "default"; - //pinctrl-0 = <&lcd_rst_gpio>; - - dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - - slice-width = <720>; - slice-height = <65>; - version-major = <1>; - version-minor = <1>; - - panel-init-sequence = [ - 29 10 03 f0 5a 5a - /* Dsc Setting */ - /* Compression Enable */ - 07 10 01 01 - /* Scaler Disable */ - 15 10 02 c3 00 - /* PPS Setting */ - 0a 31 59 10 00 00 89 30 80 0c 30 05 a0 00 41 02 d0 02 d0 02 00 02 c2 00 20 06 58 00 0a 00 0f 01 e0 01 2d 18 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a 78 1a b6 2a b6 2a f4 2a f4 4b 34 63 74 00 - 29 10 03 f0 a5 a5 - /** Sleep Out */ - 05 00 01 11 - /* 4. Common Setting */ - /* 4.1 TE(Vync) ON/OFF */ - 15 00 02 35 00 - /* 4.2 CASET/PASET Setting */ - 39 00 05 2a 00 00 05 9F - 39 00 05 2b 00 00 0c 2f - /* 4.3 TSP SYNC Setting */ - 39 00 03 f0 5a 5a - 39 00 0a B9 01 c0 3c 0b 00 00 00 11 03 - 39 00 03 f0 a5 a5 - /* FD(Fast Discharge) Setting */ - 39 00 03 f0 5a 5a - 15 00 02 b0 45 - 15 00 02 b5 48 - 39 00 03 f0 a5 a5 - /* 4.6 FFC Setting (MIPI CLK 529MHz) */ - 39 00 03 f0 5a 5a - 39 00 03 fc 5a 5a - 15 00 02 b0 1E - 39 00 06 c5 09 10 b4 24 fb - 39 00 03 f0 a5 a5 - 39 00 03 fc a5 a5 - /* OSC Spread Setting */ - 39 00 03 f0 5a 5a - 39 00 03 fc 5a 5a - 15 00 02 b0 37 - /* FFC Setting; 0x04 : Disable */ - 39 00 06 c5 04 ff 00 01 64 - 39 00 03 f0 a5 a5 - 39 00 03 fc a5 a5 - /* Dither IP Setting */ - 39 00 03 FC 5A 5A - 15 00 02 b0 86 - 15 00 02 eb 01 - 39 00 03 FC a5 a5 - /* 5 Brightness Control */ - /* 5.1 Dimming Setting */ - 39 10 03 f0 5a 5a - 15 10 02 b0 05 - 15 10 02 b1 01 - 15 10 02 b0 02 - 15 10 02 b5 d3 - 15 10 02 53 20 - 39 10 03 f0 a5 a5 - 39 10 03 51 02 ff - 05 32 01 29 - ]; - - panel-exit-sequence = [ - /* Display off */ - 05 14 01 28 - /* Sleep In */ - 05 00 01 10 - /* VCI stabilization setting */ - 39 00 03 f0 5a 5a - 15 00 02 b0 05 - 15 00 02 f4 01 - 39 a0 03 f0 a5 a5 - ]; - - disp_timings1: display-timings { - native-mode = <&dsi1_timing0>; - dsi1_timing0: timing0 { - clock-frequency = <280000000>; - hactive = <1140>; - vactive = <3120>; - hfront-porch = <16>; - hsync-len = <8>; - hback-porch = <8>; - vfront-porch = <4>; - vsync-len = <2>; - vback-porch = <16>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - - vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big0_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { - compatible = "rockchip,rk8603"; - reg = <0x43>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big1_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - - vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_npu_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c3 { - status = "okay"; - - es8388: es8388@11 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "everest,es8388", "everest,es8323"; - reg = <0x11>; - clocks = <&mclkout_i2s0>; - clock-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk>; - }; - - es7202: es7202@32 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "ES7202_PDM_ADC_1"; - power-supply = <&vcc_1v8_s0>; /* only 1v8 or 3v3, default is 3v3 */ - reg = <0x32>; - }; -}; - -&i2c4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4m3_xfer>; - - gt1x: gt1x@14 { - compatible = "goodix,gt1x"; - reg = <0x14>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_gpio>; - goodix,rst-gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - goodix,irq-gpio = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>; - power-supply = <&vcc3v3_lcd_n>; - }; -}; - -&i2c5 { - status = "okay"; - - ls_stk3332: light@47 { - compatible = "ls_stk3332"; - status = "disabled"; - reg = <0x47>; - type = ; - irq_enable = <0>; - als_threshold_high = <100>; - als_threshold_low = <10>; - als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ - poll_delay_ms = <100>; - }; - - ps_stk3332: proximity@47 { - compatible = "ps_stk3332"; - status = "disabled"; - reg = <0x47>; - type = ; - //pinctrl-names = "default"; - //pinctrl-0 = <&gpio3_c6>; - //irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>; - //irq_enable = <1>; - ps_threshold_high = <0x200>; - ps_threshold_low = <0x100>; - ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */ - ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/ - poll_delay_ms = <100>; - }; - - mpu6500_acc: mpu_acc@68 { - compatible = "mpu6500_acc"; - reg = <0x68>; - irq-gpio = <&gpio3 RK_PB4 IRQ_TYPE_EDGE_RISING>; - irq_enable = <0>; - poll_delay_ms = <30>; - type = ; - layout = <8>; - }; - - mpu6500_gyro: mpu_gyro@68 { - compatible = "mpu6500_gyro"; - reg = <0x68>; - irq_enable = <0>; - poll_delay_ms = <30>; - type = ; - layout = <8>; - }; -}; - -&i2c8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8m2_xfer>; - - usbc0: fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vbus5v0_typec>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - ; - source-pdos = - ; - - altmodes { - #address-cells = <1>; - #size-cells = <0>; - - altmode@0 { - reg = <0>; - svid = <0xff01>; - vdo = <0xffffffff>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; - }; - }; - - port@1 { - reg = <1>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; - }; - }; - }; - }; - }; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - status = "okay"; - }; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&mipi_dcphy1 { - status = "disabled"; -}; - -&pdm0 { - status = "okay"; -}; - -&pcie2x1l1 { - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie20>; - status = "okay"; -}; - -&pcie2x1l2 { - reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; - rockchip,skip-scan-in-resume; - status = "okay"; -}; - -&pinctrl { - headphone { - hp_det: hp-det { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lcd { - lcd_rst_gpio: lcd-rst-gpio { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sensor { - mpu6500_irq_gpio: mpu6500_irq_gpio { - rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - touch { - touch_gpio: touch-gpio { - rockchip,pins = - <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - usbc0_int: usbc0-int { - rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - typec5v_pwren: typec5v-pwren { - rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-bluetooth { - uart8_gpios: uart8-gpios { - rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reset_gpio: bt-reset-gpio { - rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_gpio: bt-wake-gpio { - rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_host_irq: bt-wake-host-irq { - rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - wifi_poweren_gpio: wifi-poweren-gpio { - rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm11 { - pinctrl-0 = <&pwm11m1_pins>; - status = "okay"; -}; - -&pwm13 { - status = "okay"; - pinctrl-names = "active"; - pinctrl-0 = <&pwm13m1_pins>; -}; - -&pwm15 { - compatible = "rockchip,remotectl-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm15m0_pins>; - remote_pwm_id = <3>; - handle_cpu_id = <1>; - remote_support_psci = <0>; - status = "okay"; - - ir_key1 { - rockchip,usercode = <0x4040>; - rockchip,key_table = - <0xf2 KEY_REPLY>, - <0xba KEY_BACK>, - <0xf4 KEY_UP>, - <0xf1 KEY_DOWN>, - <0xef KEY_LEFT>, - <0xee KEY_RIGHT>, - <0xbd KEY_HOME>, - <0xea KEY_VOLUMEUP>, - <0xe3 KEY_VOLUMEDOWN>, - <0xe2 KEY_SEARCH>, - <0xb2 KEY_POWER>, - <0xbc KEY_MUTE>, - <0xec KEY_MENU>, - <0xbf 0x190>, - <0xe0 0x191>, - <0xe1 0x192>, - <0xe9 183>, - <0xe6 248>, - <0xe8 185>, - <0xe7 186>, - <0xf0 388>, - <0xbe 0x175>; - }; - - ir_key2 { - rockchip,usercode = <0xff00>; - rockchip,key_table = - <0xf9 KEY_HOME>, - <0xbf KEY_BACK>, - <0xfb KEY_MENU>, - <0xaa KEY_REPLY>, - <0xb9 KEY_UP>, - <0xe9 KEY_DOWN>, - <0xb8 KEY_LEFT>, - <0xea KEY_RIGHT>, - <0xeb KEY_VOLUMEDOWN>, - <0xef KEY_VOLUMEUP>, - <0xf7 KEY_MUTE>, - <0xe7 KEY_POWER>, - <0xfc KEY_POWER>, - <0xa9 KEY_VOLUMEDOWN>, - <0xa8 KEY_PLAYPAUSE>, - <0xe0 KEY_VOLUMEDOWN>, - <0xa5 KEY_VOLUMEDOWN>, - <0xab 183>, - <0xb7 388>, - <0xe8 388>, - <0xf8 184>, - <0xaf 185>, - <0xed KEY_VOLUMEDOWN>, - <0xee 186>, - <0xb3 KEY_VOLUMEDOWN>, - <0xf1 KEY_VOLUMEDOWN>, - <0xf2 KEY_VOLUMEDOWN>, - <0xf3 KEY_SEARCH>, - <0xb4 KEY_VOLUMEDOWN>, - <0xa4 KEY_SETUP>, - <0xbe KEY_SEARCH>; - }; - - ir_key3 { - rockchip,usercode = <0x1dcc>; - rockchip,key_table = - <0xee KEY_REPLY>, - <0xf0 KEY_BACK>, - <0xf8 KEY_UP>, - <0xbb KEY_DOWN>, - <0xef KEY_LEFT>, - <0xed KEY_RIGHT>, - <0xfc KEY_HOME>, - <0xf1 KEY_VOLUMEUP>, - <0xfd KEY_VOLUMEDOWN>, - <0xb7 KEY_SEARCH>, - <0xff KEY_POWER>, - <0xf3 KEY_MUTE>, - <0xbf KEY_MENU>, - <0xf9 0x191>, - <0xf5 0x192>, - <0xb3 388>, - <0xbe KEY_1>, - <0xba KEY_2>, - <0xb2 KEY_3>, - <0xbd KEY_4>, - <0xf9 KEY_5>, - <0xb1 KEY_6>, - <0xfc KEY_7>, - <0xf8 KEY_8>, - <0xb0 KEY_9>, - <0xb6 KEY_0>, - <0xb5 KEY_BACKSPACE>; - }; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp3_out_dsi0>; -}; - -&route_dsi1 { - status = "disabled"; - connect = <&vp3_out_dsi1>; -}; - -&sdmmc { - status = "okay"; - vmmc-supply = <&vcc_3v3_sd_s0>; -}; - -&spdif_tx1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif1m1_tx>; -}; - -&spdif_tx1_dc { - status = "okay"; -}; - -&spdif_tx1_sound { - status = "okay"; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - num-cs = <1>; -}; - -&u2phy0_otg { - rockchip,typec-vbus-det; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; -}; - -&uart8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>; -}; - -&usbdp_phy0 { - orientation-switch; - svid = <0xff01>; - sbu1-dc-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>; - - port { - #address-cells = <1>; - #size-cells = <0>; - usbdp_phy0_orientation_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; - }; - - usbdp_phy0_dp_altmode_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&dp_altmode_mux>; - }; - }; -}; - -&usbdrd_dwc3_0 { - usb-role-switch; - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -&usbhost3_0 { - status = "disabled"; -}; - -&usbhost_dwc3_0 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb8-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588s-evb8-lp4x-v10.dts deleted file mode 100644 index 300553e90..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb8-lp4x-v10.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588s-evb8-lp4x.dtsi" -#include "rk3588s-evb1-lp4x-v10-camera.dtsi" -#include "rk3588-android.dtsi" - -/ { - model = "Rockchip RK3588S EVB8 LP4X V10 Board"; - compatible = "rockchip,rk3588s-evb8-lp4x-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb8-lp4x.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-evb8-lp4x.dtsi deleted file mode 100644 index 4e0cc72ff..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb8-lp4x.dtsi +++ /dev/null @@ -1,831 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include "dt-bindings/usb/pd.h" -#include "rk3588s.dtsi" -#include "rk3588s-evb.dtsi" -#include "rk3588-rk806-single.dtsi" - -/ { - combophy_avdd0v85: combophy-avdd0v85 { - compatible = "regulator-fixed"; - regulator-name = "combophy_avdd0v85"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&vdd_0v85_s0>; - }; - - combophy_avdd1v8: combophy-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "combophy_avdd1v8"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - es7202_sound_micarray: es7202-sound-micarray { - status = "okay"; - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip,sound-micarray"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,dai-link@0 { - format = "pdm"; - cpu { - sound-dai = <&pdm0>; - }; - codec { - sound-dai = <&es7202>; - }; - }; - }; - - es8388_sound: es8388-sound { - status = "okay"; - compatible = "rockchip,multicodecs-card"; - rockchip,card-name = "rockchip-es8388"; - hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; - io-channels = <&saradc 3>; - io-channel-names = "adc-detect"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - spk-con-gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - hp-con-gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; - rockchip,format = "i2s"; - rockchip,mclk-fs = <256>; - rockchip,cpu = <&i2s0_8ch>; - rockchip,codec = <&es8388>; - rockchip,audio-routing = - "Headphone", "LOUT1", - "Headphone", "ROUT1", - "Speaker", "LOUT2", - "Speaker", "ROUT2", - "Headphone", "Headphone Power", - "Headphone", "Headphone Power", - "Speaker", "Speaker Power", - "Speaker", "Speaker Power", - "LINPUT1", "Main Mic", - "LINPUT2", "Main Mic", - "RINPUT1", "Headset Mic", - "RINPUT2", "Headset Mic"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - play-pause-key { - label = "playpause"; - linux,code = ; - press-threshold-microvolt = <2000>; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - pwms = <&pwm11 0 50000 0>; - cooling-levels = <0 50 100 150 200 255>; - rockchip,temp-trips = < - 50000 1 - 55000 2 - 60000 3 - 65000 4 - 70000 5 - >; - }; - - panel-edp { - compatible = "simple-panel"; - backlight = <&backlight>; - power-supply = <&vcc3v3_lcd_edp>; - prepare-delay-ms = <120>; - enable-delay-ms = <120>; - unprepare-delay-ms = <120>; - disable-delay-ms = <120>; - width-mm = <129>; - height-mm = <171>; - - panel-timing { - clock-frequency = <200000000>; - hactive = <1536>; - vactive = <2048>; - hfront-porch = <12>; - hsync-len = <16>; - hback-porch = <48>; - vfront-porch = <8>; - vsync-len = <4>; - vback-porch = <8>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - panel_in_edp: endpoint { - remote-endpoint = <&edp_out_panel>; - }; - }; - }; - - vbus5v0_typec: vbus5v0-typec { - compatible = "regulator-fixed"; - regulator-name = "vbus5v0_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_lcd_edp: vcc3v3-lcd-edp { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd_edp"; - gpio = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc3v3_pcie20: vcc3v3-pcie20 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie20"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sd_s0_pwr>; - regulator-name = "vcc_3v3_sd_s0"; - enable-active-high; - }; - - vcc5v0_host: vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - }; - - wireless_bluetooth: wireless-bluetooth { - compatible = "bluetooth-platdata"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "rts_gpio"; - pinctrl-0 = <&uart8m1_rtsn>, <&bt_gpio>; - pinctrl-1 = <&uart8_gpios>; - BT,reset_gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; - BT,wake_gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; - BT,wake_host_irq = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - wifi_chip_type = "ap6275p"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; - WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - WIFI,poweren_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; -}; - -&backlight { - pwms = <&pwm12 0 25000 0>; - power-supply = <&vcc3v3_lcd_edp>; - status = "okay"; -}; - -&combphy0_ps { - status = "okay"; -}; - -&dp0 { - status = "okay"; -}; - -&dp0_in_vp1 { - status = "okay"; -}; - -&dp0_sound{ - status = "okay"; -}; - -&edp0 { - force-hpd; - status = "okay"; - - ports { - port@1 { - reg = <1>; - - edp_out_panel: endpoint { - remote-endpoint = <&panel_in_edp>; - }; - }; - }; -}; - -&edp0_in_vp2 { - status = "okay"; -}; - -&hdptxphy0 { - /* Single Vdiff Training Table for power reduction (optional) */ - training-table = /bits/ 8 < - /* voltage swing 0, pre-emphasis 0->3 */ - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - /* voltage swing 1, pre-emphasis 0->2 */ - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - /* voltage swing 2, pre-emphasis 0->1 */ - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - /* voltage swing 3, pre-emphasis 0 */ - 0x0d 0x00 0x00 0x00 0x00 0x00 - >; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - - vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big0_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { - compatible = "rockchip,rk8603"; - reg = <0x43>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big1_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - - vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_npu_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c3 { - status = "okay"; - - es8388: es8388@11 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "everest,es8388", "everest,es8323"; - reg = <0x11>; - clocks = <&mclkout_i2s0>; - clock-names = "mclk"; - assigned-clocks = <&mclkout_i2s0>; - assigned-clock-rates = <12288000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk>; - }; - - es7202: es7202@32 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "ES7202_PDM_ADC_1"; - power-supply = <&vcc_1v8_s0>; /* only 1v8 or 3v3, default is 3v3 */ - reg = <0x32>; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4m3_xfer>; - status = "okay"; - - gsl3673@40 { - compatible = "GSL,GSL3673"; - reg = <0x40>; - screen_max_x = <1536>; - screen_max_y = <2048>; - irq_gpio_number = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>; - rst_gpio_number = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - }; -}; - -&i2c5 { - status = "okay"; - - ls_stk3332: light@47 { - compatible = "ls_stk3332"; - status = "disabled"; - reg = <0x47>; - type = ; - irq_enable = <0>; - als_threshold_high = <100>; - als_threshold_low = <10>; - als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ - poll_delay_ms = <100>; - }; - - ps_stk3332: proximity@47 { - compatible = "ps_stk3332"; - status = "disabled"; - reg = <0x47>; - type = ; - //pinctrl-names = "default"; - //pinctrl-0 = <&gpio3_c6>; - //irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>; - //irq_enable = <1>; - ps_threshold_high = <0x200>; - ps_threshold_low = <0x100>; - ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */ - ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/ - poll_delay_ms = <100>; - }; - - mpu6500_acc: mpu_acc@68 { - compatible = "mpu6500_acc"; - reg = <0x68>; - irq-gpio = <&gpio3 RK_PB4 IRQ_TYPE_EDGE_RISING>; - irq_enable = <0>; - poll_delay_ms = <30>; - type = ; - layout = <5>; - }; - - mpu6500_gyro: mpu_gyro@68 { - compatible = "mpu6500_gyro"; - reg = <0x68>; - poll_delay_ms = <30>; - type = ; - layout = <5>; - }; -}; - -&i2c8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8m2_xfer>; - - usbc0: fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vbus5v0_typec>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - ; - source-pdos = - ; - - altmodes { - #address-cells = <1>; - #size-cells = <0>; - - altmode@0 { - reg = <0>; - svid = <0xff01>; - vdo = <0xffffffff>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; - }; - }; - - port@1 { - reg = <1>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; - }; - }; - }; - }; - }; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; -}; - -&pcie2x1l1 { - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie20>; - status = "okay"; -}; - -&pcie2x1l2 { - reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; - rockchip,skip-scan-in-resume; - status = "okay"; -}; - -&pdm0 { - status = "okay"; -}; - -&pinctrl { - headphone { - hp_det: hp-det { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lcd { - lcd_rst_gpio: lcd-rst-gpio { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sdmmc { - sd_s0_pwr: sd-s0-pwr { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sensor { - mpu6500_irq_gpio: mpu6500_irq_gpio { - rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - usbc0_int: usbc0-int { - rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - typec5v_pwren: typec5v-pwren { - rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wireless-bluetooth { - uart8_gpios: uart8-gpios { - rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_gpio: bt-gpio { - rockchip,pins = - <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, - <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>, - <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - wifi_poweren_gpio: wifi-poweren-gpio { - rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm3 { - compatible = "rockchip,remotectl-pwm"; - remote_pwm_id = <3>; - handle_cpu_id = <1>; - remote_support_psci = <0>; - status = "okay"; - - ir_key1 { - rockchip,usercode = <0x4040>; - rockchip,key_table = - <0xf2 KEY_REPLY>, - <0xba KEY_BACK>, - <0xf4 KEY_UP>, - <0xf1 KEY_DOWN>, - <0xef KEY_LEFT>, - <0xee KEY_RIGHT>, - <0xbd KEY_HOME>, - <0xea KEY_VOLUMEUP>, - <0xe3 KEY_VOLUMEDOWN>, - <0xe2 KEY_SEARCH>, - <0xb2 KEY_POWER>, - <0xbc KEY_MUTE>, - <0xec KEY_MENU>, - <0xbf 0x190>, - <0xe0 0x191>, - <0xe1 0x192>, - <0xe9 183>, - <0xe6 248>, - <0xe8 185>, - <0xe7 186>, - <0xf0 388>, - <0xbe 0x175>; - }; - - ir_key2 { - rockchip,usercode = <0xff00>; - rockchip,key_table = - <0xf9 KEY_HOME>, - <0xbf KEY_BACK>, - <0xfb KEY_MENU>, - <0xaa KEY_REPLY>, - <0xb9 KEY_UP>, - <0xe9 KEY_DOWN>, - <0xb8 KEY_LEFT>, - <0xea KEY_RIGHT>, - <0xeb KEY_VOLUMEDOWN>, - <0xef KEY_VOLUMEUP>, - <0xf7 KEY_MUTE>, - <0xe7 KEY_POWER>, - <0xfc KEY_POWER>, - <0xa9 KEY_VOLUMEDOWN>, - <0xa8 KEY_PLAYPAUSE>, - <0xe0 KEY_VOLUMEDOWN>, - <0xa5 KEY_VOLUMEDOWN>, - <0xab 183>, - <0xb7 388>, - <0xe8 388>, - <0xf8 184>, - <0xaf 185>, - <0xed KEY_VOLUMEDOWN>, - <0xee 186>, - <0xb3 KEY_VOLUMEDOWN>, - <0xf1 KEY_VOLUMEDOWN>, - <0xf2 KEY_VOLUMEDOWN>, - <0xf3 KEY_SEARCH>, - <0xb4 KEY_VOLUMEDOWN>, - <0xa4 KEY_SETUP>, - <0xbe KEY_SEARCH>; - }; - - ir_key3 { - rockchip,usercode = <0x1dcc>; - rockchip,key_table = - <0xee KEY_REPLY>, - <0xf0 KEY_BACK>, - <0xf8 KEY_UP>, - <0xbb KEY_DOWN>, - <0xef KEY_LEFT>, - <0xed KEY_RIGHT>, - <0xfc KEY_HOME>, - <0xf1 KEY_VOLUMEUP>, - <0xfd KEY_VOLUMEDOWN>, - <0xb7 KEY_SEARCH>, - <0xff KEY_POWER>, - <0xf3 KEY_MUTE>, - <0xbf KEY_MENU>, - <0xf9 0x191>, - <0xf5 0x192>, - <0xb3 388>, - <0xbe KEY_1>, - <0xba KEY_2>, - <0xb2 KEY_3>, - <0xbd KEY_4>, - <0xf9 KEY_5>, - <0xb1 KEY_6>, - <0xfc KEY_7>, - <0xf8 KEY_8>, - <0xb0 KEY_9>, - <0xb6 KEY_0>, - <0xb5 KEY_BACKSPACE>; - }; -}; - -&pwm11 { - pinctrl-0 = <&pwm11m1_pins>; - status = "okay"; -}; - -&pwm12 { - pinctrl-0 = <&pwm12m1_pins>; - status = "okay"; -}; - -&route_edp0 { - connect = <&vp2_out_edp0>; - status = "okay"; -}; - -&sdmmc { - status = "okay"; - vmmc-supply = <&vcc_3v3_sd_s0>; -}; - -&spdif_tx1 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif1m1_tx>; -}; - -&spdif_tx1_dc { - status = "okay"; -}; - -&spdif_tx1_sound { - status = "okay"; -}; - -&spdif_tx2 { - status = "okay"; -}; - -&u2phy0_otg { - rockchip,typec-vbus-det; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host>; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; -}; - -&uart8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>; -}; - -&usbdp_phy0 { - orientation-switch; - svid = <0xff01>; - sbu1-dc-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>; - - port { - #address-cells = <1>; - #size-cells = <0>; - usbdp_phy0_orientation_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; - }; - - usbdp_phy0_dp_altmode_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&dp_altmode_mux>; - }; - }; -}; - -&usbdrd_dwc3_0 { - usb-role-switch; - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -&usbhost3_0 { - status = "disabled"; -}; - -&usbhost_dwc3_0 { - status = "disabled"; -}; - -/* vp0 & vp3 are not used on this board */ -&vp0 { - /delete-property/ rockchip,plane-mask; - /delete-property/ rockchip,primary-plane; -}; - -&vp1 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | - 1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; - rockchip,primary-plane = ; -}; - -&vp2 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2 | - 1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; - rockchip,primary-plane = ; -}; - -&vp3 { - /delete-property/ rockchip,plane-mask; - /delete-property/ rockchip,primary-plane; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rk806-dual.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-rk806-dual.dtsi deleted file mode 100644 index 04337382f..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rk806-dual.dtsi +++ /dev/null @@ -1,777 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include -#include - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - num-cs = <2>; - - rk806master: rk806master@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default", "pmic-power-off"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; - pinctrl-1 = <&rk806_dvs1_pwrdn>; - - /* 2800mv-3500mv */ - low_voltage_threshold = <3000>; - /* 2700mv-3400mv */ - shutdown_voltage_threshold = <2700>; - /* 140 160 */ - shutdown_temperture_threshold = <160>; - hotdie_temperture_threshold = <115>; - - /* 0: restart PMU; - * 1: reset all the power off reset registers, - * forcing the state to switch to ACTIVE mode; - * 2: Reset all the power off reset registers, - * forcing the state to switch to ACTIVE mode, - * and simultaneously pull down the RESETB PIN for 5mS before releasing - */ - pmic-reset-func = <1>; - - /* PWRON_ON_TIME: 0:500mS; 1:20mS */ - pwron-on-time-20ms; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc5v0_sys>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - pwrkey { - status = "okay"; - }; - - pinctrl_rk806: pinctrl_rk806 { - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: rk806_dvs1_null { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs1_slp: rk806_dvs1_slp { - pins = "gpio_pwrctrl1"; - function = "pin_fun1"; - }; - - rk806_dvs1_pwrdn: rk806_dvs1_pwrdn { - pins = "gpio_pwrctrl1"; - function = "pin_fun2"; - }; - - rk806_dvs1_rst: rk806_dvs1_rst { - pins = "gpio_pwrctrl1"; - function = "pin_fun3"; - }; - - rk806_dvs2_null: rk806_dvs2_null { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_slp: rk806_dvs2_slp { - pins = "gpio_pwrctrl2"; - function = "pin_fun1"; - }; - - rk806_dvs2_pwrdn: rk806_dvs2_pwrdn { - pins = "gpio_pwrctrl2"; - function = "pin_fun2"; - }; - - rk806_dvs2_rst: rk806_dvs2_rst { - pins = "gpio_pwrctrl2"; - function = "pin_fun3"; - }; - - rk806_dvs2_dvs: rk806_dvs2_dvs { - pins = "gpio_pwrctrl2"; - function = "pin_fun4"; - }; - - rk806_dvs2_gpio: rk806_dvs2_gpio { - pins = "gpio_pwrctrl2"; - function = "pin_fun5"; - }; - - rk806_dvs3_null: rk806_dvs3_null { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - rk806_dvs3_slp: rk806_dvs3_slp { - pins = "gpio_pwrctrl3"; - function = "pin_fun1"; - }; - - rk806_dvs3_pwrdn: rk806_dvs3_pwrdn { - pins = "gpio_pwrctrl3"; - function = "pin_fun2"; - }; - - rk806_dvs3_rst: rk806_dvs3_rst { - pins = "gpio_pwrctrl3"; - function = "pin_fun3"; - }; - - rk806_dvs3_dvs: rk806_dvs3_dvs { - pins = "gpio_pwrctrl3"; - function = "pin_fun4"; - }; - - rk806_dvs3_gpio: rk806_dvs3_gpio { - pins = "gpio_pwrctrl3"; - function = "pin_fun5"; - }; - }; - - regulators { - vdd_gpu_s0: DCDC_REG1 { - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <400>; - regulator-name = "vdd_gpu_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_npu_s0: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_npu_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu_mem_s0: DCDC_REG5 { - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-enable-ramp-delay = <400>; - regulator-name = "vdd_gpu_mem_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_npu_mem_s0: DCDC_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_npu_mem_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: DCDC_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_2v0_pldo_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vdd_vdenc_mem_s0: DCDC_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_mem_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd2_ddr_s3: DCDC_REG9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v1_nldo_s3: DCDC_REG10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1100000>; - }; - }; - - avcc_1v8_s0: PLDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "avcc_1v8_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd1_1v8_ddr_s3: PLDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd1_1v8_ddr_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_1v8_s3: PLDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_1v8_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_3v3_s0: PLDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: PLDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vccio_sd_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - master_pldo6_s3: PLDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "master_pldo6_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: NLDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_0v75_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd2l_0v9_ddr_s3: NLDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdd2l_0v9_ddr_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - master_nldo3: NLDO_REG3 { - regulator-name = "master_nldo3"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd_0v75_s0: NLDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "avdd_0v75_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v85_s0: NLDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_0v85_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; - - rk806slave: rk806slave@1 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x01>; - - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default", "pmic-sleep"; - pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, <&rk806_slave_dvs3_null>; - pinctrl-1 = <&rk806_slave_dvs1_slp>, <&rk806_slave_dvs2_null>, <&rk806_slave_dvs3_null>; - - /* 0: restart PMU; - * 1: reset all the power off reset registers, - * forcing the state to switch to ACTIVE mode; - * 2: Reset all the power off reset registers, - * forcing the state to switch to ACTIVE mode, - * and simultaneously pull down the RESETB PIN for 5mS before releasing - */ - pmic-reset-func = <1>; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_2v0_pldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - pwrkey { - status = "disabled"; - }; - - pinctrl_slave_rk806: pinctrl_slave_rk806 { - gpio-controller; - #gpio-cells = <2>; - - rk806_slave_dvs1_null: rk806_slave_dvs1_null { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_slave_dvs1_slp: rk806_slave_dvs1_slp { - pins = "gpio_pwrctrl1"; - function = "pin_fun1"; - }; - - rk806_slave_dvs1_pwrdn: rk806_slave_dvs1_pwrdn { - pins = "gpio_pwrctrl1"; - function = "pin_fun2"; - }; - - rk806_slave_dvs1_rst: rk806_slave_dvs1_rst { - pins = "gpio_pwrctrl1"; - function = "pin_fun3"; - }; - - rk806_slave_dvs2_null: rk806_slave_dvs2_null { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_slave_dvs2_slp: rk806_slave_dvs2_slp { - pins = "gpio_pwrctrl2"; - function = "pin_fun1"; - }; - - rk806_slave_dvs2_pwrdn: rk806_slave_dvs2_pwrdn { - pins = "gpio_pwrctrl2"; - function = "pin_fun2"; - }; - - rk806_slave_dvs2_rst: rk806_slave_dvs2_rst { - pins = "gpio_pwrctrl2"; - function = "pin_fun3"; - }; - - rk806_slave_dvs2_dvs: rk806_slave_dvs2_dvs { - pins = "gpio_pwrctrl2"; - function = "pin_fun4"; - }; - - rk806_slave_dvs2_gpio: rk806_slave_dvs2_gpio { - pins = "gpio_pwrctrl2"; - function = "pin_fun5"; - }; - - rk806_slave_dvs3_null: rk806_slave_dvs3_null { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - rk806_slave_dvs3_slp: rk806_slave_dvs3_slp { - pins = "gpio_pwrctrl3"; - function = "pin_fun1"; - }; - - rk806_slave_dvs3_pwrdn: rk806_slave_dvs3_pwrdn { - pins = "gpio_pwrctrl3"; - function = "pin_fun2"; - }; - - rk806_slave_dvs3_rst: rk806_slave_dvs3_rst { - pins = "gpio_pwrctrl3"; - function = "pin_fun3"; - }; - - rk806_slave_dvs3_dvs: rk806_slave_dvs3_dvs { - pins = "gpio_pwrctrl3"; - function = "pin_fun4"; - }; - - rk806_slave_dvs3_gpio: rk806_slave_dvs3_gpio { - pins = "gpio_pwrctrl3"; - function = "pin_fun5"; - }; - }; - - regulators { - vdd_cpu_big1_s0: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_big1_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big0_s0: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_big0_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_s3: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vdd_cpu_big1_mem_s0: DCDC_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_big1_mem_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - - vdd_cpu_big0_mem_s0: DCDC_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_big0_mem_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s0: DCDC_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_1v8_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_mem_s0: DCDC_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_mem_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vddq_ddr_s0: DCDC_REG9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: DCDC_REG10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_cam_s0: PLDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_1v8_cam_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd1v8_ddr_pll_s0: PLDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "avdd1v8_ddr_pll_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_1v8_pll_s0: PLDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_1v8_pll_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3_sd_s0: PLDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_3v3_sd_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_2v8_cam_s0: PLDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-ramp-delay = <12500>; - regulator-name = "vcc_2v8_cam_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: PLDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_pll_s0: NLDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_0v75_pll_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_pll_s0: NLDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "vdd_ddr_pll_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - slave_nldo3: NLDO_REG3 { - regulator-name = "slave_nldo3"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd_1v2_cam_s0: NLDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-ramp-delay = <12500>; - regulator-name = "avdd_1v2_cam_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd_1v2_s0: NLDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-ramp-delay = <12500>; - regulator-name = "avdd_1v2_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-tablet-rk806-single-camera.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-tablet-rk806-single-camera.dtsi deleted file mode 100644 index dd1bae11b..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-tablet-rk806-single-camera.dtsi +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. - * - */ -/ { - vcc_mipidcphy0: vcc-mipidcphy0-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipidcphy0_pwr>; - regulator-name = "vcc_mipidcphy0"; - enable-active-high; - regulator-boot-on; - regulator-always-on; - }; -}; - -&csi2_dcphy0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_ucam0: endpoint@1 { - reg = <1>; - remote-endpoint = <&s5k3l6_out0>; - data-lanes = <1 2 3 4>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidcphy0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi0_csi2_input>; - }; - }; - }; -}; - -&i2c6 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6m4_xfer>; - - fp5510: fp5510@c { - compatible = "fitipower,fp5510"; - status = "okay"; - reg = <0x0c>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - }; - - s5k3l6: s5k3l6@10 { - compatible = "samsung,s5k3l6xx"; - reg = <0x10>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - pinctrl-names = "default"; - pinctrl-0 = <&mipim1_camera1_clk>; - // power-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - //pwdn-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "default"; - rockchip,camera-module-lens-name = "default"; - lens-focus = <&fp5510>; - port { - s5k3l6_out0: endpoint { - remote-endpoint = <&mipi_in_ucam0>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&mipi0_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidcphy0_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in0>; - }; - }; - }; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds { - status = "okay"; - - port { - cif_mipi_in0: endpoint { - remote-endpoint = <&mipi0_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds_sditf { - status = "okay"; - - port { - mipi_lvds_sditf: endpoint { - remote-endpoint = <&isp0_vir0>; - }; - }; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp0 { - status = "okay"; -}; - -&isp0_mmu { - status = "okay"; -}; - -&rkisp0_vir0 { - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds_sditf>; - }; - }; -}; - -&pinctrl { - cam { - mipidcphy0_pwr: mipidcphy0-pwr { - rockchip,pins = - /* camera power en */ - <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-tablet-rk806-single-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588s-tablet-rk806-single-v10.dts deleted file mode 100644 index 23332374c..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-tablet-rk806-single-v10.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588s-tablet-rk806-single.dtsi" -#include "rk3588s-tablet-rk806-single-camera.dtsi" - -/ { - model = "Rockchip RK3588S TABLET RK806 SINGLE Board"; - compatible = "rockchip,rk3588s-tablet-rk806-single-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-tablet-rk806-single.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-tablet-rk806-single.dtsi deleted file mode 100644 index 450a913b7..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-tablet-rk806-single.dtsi +++ /dev/null @@ -1,1674 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "rk3588s.dtsi" -#include "rk3588-android.dtsi" -#include "rk3588-rk806-single.dtsi" - -/ { - adc_keys: adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - vol-up-key { - label = "volume up"; - linux,code = ; - press-threshold-microvolt = <17000>; - }; - - vol-down-key { - label = "volume down"; - linux,code = ; - press-threshold-microvolt = <890000>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm13 0 25000 0>; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - combophy_avdd0v85: combophy-avdd0v85 { - compatible = "regulator-fixed"; - regulator-name = "combophy_avdd0v85"; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&vdd_0v85_s0>; - }; - - combophy_avdd1v8: combophy-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "combophy_avdd1v8"; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - charge-animation { - compatible = "rockchip,uboot-charge"; - rockchip,uboot-charge-on = <0>; - rockchip,android-charge-on = <1>; - rockchip,uboot-low-power-voltage = <3350>; - rockchip,screen-on-voltage = <3400>; - status = "okay"; - }; - - es8388_sound: es8388-sound { - status = "okay"; - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "rockchip,es8388-codec"; - simple-audio-card,aux-devs = <&aw87xxx_pa1 &aw87xxx_pa2>; - simple-audio-card,dai-link@0 { - format = "i2s"; - cpu { - sound-dai = <&i2s0_8ch>; - }; - codec { - sound-dai = <&es8388>; - }; - }; - }; - - vcc3v3_lcd_n: vcc3v3-lcd0-n { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd0_n"; - regulator-boot-on; - enable-active-high; - gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc_3v3_s0>; - }; - - VDD5V8_LCD: vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; - /*vin-supply = <&vcc5v0_usb>;*/ - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - }; - - VEE5V8_LCD: vcc5v0-host1 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host1"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; - /*vin-supply = <&vcc5v0_usb>;*/ - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en1>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; - - wireless_bluetooth: wireless-bluetooth { - compatible = "bluetooth-platdata"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "rts_gpio"; - pinctrl-0 = <&uart8m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_wake_host_irq>; - pinctrl-1 = <&uart8_gpios>; - BT,reset_gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; - BT,wake_gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; - BT,wake_host_irq = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - wifi_chip_type = "ap6255"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; - WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - WIFI,poweren_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; -}; - -&combphy0_ps { - status = "okay"; -}; - -&combphy2_psu { - status = "okay"; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&dmc { - system-status-level = < - /*system status freq level*/ - SYS_STATUS_NORMAL DMC_FREQ_LEVEL_MID_HIGH - SYS_STATUS_REBOOT DMC_FREQ_LEVEL_HIGH - SYS_STATUS_SUSPEND DMC_FREQ_LEVEL_LOW - SYS_STATUS_BOOST DMC_FREQ_LEVEL_HIGH - SYS_STATUS_ISP DMC_FREQ_LEVEL_HIGH - SYS_STATUS_PERFORMANCE DMC_FREQ_LEVEL_HIGH - SYS_STATUS_DUALVIEW DMC_FREQ_LEVEL_HIGH - >; -}; - -&dp0 { - status = "disabled"; -}; - -&dp0_in_vp1 { - status = "okay"; -}; - -&dsi0_in_vp2 { - status = "okay"; -}; - -&dsi0_in_vp3 { - status = "disabled"; -}; - -/* - * mipi_dcphy0 needs to be enabled - * when dsi0 is enabled - */ -&dsi0 { - status = "okay"; - rockchip,dual-channel = <&dsi1>; - //rockchip,lane-rate = <1000>; - dsi0_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight>; - reset-delay-ms = <60>; - enable-delay-ms = <60>; - prepare-delay-ms = <60>; - unprepare-delay-ms = <60>; - disable-delay-ms = <60>; - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | - MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - panel-init-sequence = [ - 23 00 02 FE 21 - 23 00 02 04 00 - 23 00 02 00 64 - 23 00 02 2A 00 - 23 00 02 26 64 - 23 00 02 54 00 - 23 00 02 50 64 - 23 00 02 7B 00 - 23 00 02 77 64 - 23 00 02 A2 00 - 23 00 02 9D 64 - 23 00 02 C9 00 - 23 00 02 C5 64 - 23 00 02 01 71 - 23 00 02 27 71 - 23 00 02 51 71 - 23 00 02 78 71 - 23 00 02 9E 71 - 23 00 02 C6 71 - 23 00 02 02 89 - 23 00 02 28 89 - 23 00 02 52 89 - 23 00 02 79 89 - 23 00 02 9F 89 - 23 00 02 C7 89 - 23 00 02 03 9E - 23 00 02 29 9E - 23 00 02 53 9E - 23 00 02 7A 9E - 23 00 02 A0 9E - 23 00 02 C8 9E - 23 00 02 09 00 - 23 00 02 05 B0 - 23 00 02 31 00 - 23 00 02 2B B0 - 23 00 02 5A 00 - 23 00 02 55 B0 - 23 00 02 80 00 - 23 00 02 7C B0 - 23 00 02 A7 00 - 23 00 02 A3 B0 - 23 00 02 CE 00 - 23 00 02 CA B0 - 23 00 02 06 C0 - 23 00 02 2D C0 - 23 00 02 56 C0 - 23 00 02 7D C0 - 23 00 02 A4 C0 - 23 00 02 CB C0 - 23 00 02 07 CF - 23 00 02 2F CF - 23 00 02 58 CF - 23 00 02 7E CF - 23 00 02 A5 CF - 23 00 02 CC CF - 23 00 02 08 DD - 23 00 02 30 DD - 23 00 02 59 DD - 23 00 02 7F DD - 23 00 02 A6 DD - 23 00 02 CD DD - 23 00 02 0E 15 - 23 00 02 0A E9 - 23 00 02 36 15 - 23 00 02 32 E9 - 23 00 02 5F 15 - 23 00 02 5B E9 - 23 00 02 85 15 - 23 00 02 81 E9 - 23 00 02 AD 15 - 23 00 02 A9 E9 - 23 00 02 D3 15 - 23 00 02 CF E9 - 23 00 02 0B 14 - 23 00 02 33 14 - 23 00 02 5C 14 - 23 00 02 82 14 - 23 00 02 AA 14 - 23 00 02 D0 14 - 23 00 02 0C 36 - 23 00 02 34 36 - 23 00 02 5D 36 - 23 00 02 83 36 - 23 00 02 AB 36 - 23 00 02 D1 36 - 23 00 02 0D 6B - 23 00 02 35 6B - 23 00 02 5E 6B - 23 00 02 84 6B - 23 00 02 AC 6B - 23 00 02 D2 6B - 23 00 02 13 5A - 23 00 02 0F 94 - 23 00 02 3B 5A - 23 00 02 37 94 - 23 00 02 64 5A - 23 00 02 60 94 - 23 00 02 8A 5A - 23 00 02 86 94 - 23 00 02 B2 5A - 23 00 02 AE 94 - 23 00 02 D8 5A - 23 00 02 D4 94 - 23 00 02 10 D1 - 23 00 02 38 D1 - 23 00 02 61 D1 - 23 00 02 87 D1 - 23 00 02 AF D1 - 23 00 02 D5 D1 - 23 00 02 11 04 - 23 00 02 39 04 - 23 00 02 62 04 - 23 00 02 88 04 - 23 00 02 B0 04 - 23 00 02 D6 04 - 23 00 02 12 05 - 23 00 02 3A 05 - 23 00 02 63 05 - 23 00 02 89 05 - 23 00 02 B1 05 - 23 00 02 D7 05 - 23 00 02 18 AA - 23 00 02 14 36 - 23 00 02 42 AA - 23 00 02 3D 36 - 23 00 02 69 AA - 23 00 02 65 36 - 23 00 02 8F AA - 23 00 02 8B 36 - 23 00 02 B7 AA - 23 00 02 B3 36 - 23 00 02 DD AA - 23 00 02 D9 36 - 23 00 02 15 74 - 23 00 02 3F 74 - 23 00 02 66 74 - 23 00 02 8C 74 - 23 00 02 B4 74 - 23 00 02 DA 74 - 23 00 02 16 9F - 23 00 02 40 9F - 23 00 02 67 9F - 23 00 02 8D 9F - 23 00 02 B5 9F - 23 00 02 DB 9F - 23 00 02 17 DC - 23 00 02 41 DC - 23 00 02 68 DC - 23 00 02 8E DC - 23 00 02 B6 DC - 23 00 02 DC DC - 23 00 02 1D FF - 23 00 02 19 03 - 23 00 02 47 FF - 23 00 02 43 03 - 23 00 02 6E FF - 23 00 02 6A 03 - 23 00 02 94 FF - 23 00 02 90 03 - 23 00 02 BC FF - 23 00 02 B8 03 - 23 00 02 E2 FF - 23 00 02 DE 03 - 23 00 02 1A 35 - 23 00 02 44 35 - 23 00 02 6B 35 - 23 00 02 91 35 - 23 00 02 B9 35 - 23 00 02 DF 35 - 23 00 02 1B 45 - 23 00 02 45 45 - 23 00 02 6C 45 - 23 00 02 92 45 - 23 00 02 BA 45 - 23 00 02 E0 45 - 23 00 02 1C 55 - 23 00 02 46 55 - 23 00 02 6D 55 - 23 00 02 93 55 - 23 00 02 BB 55 - 23 00 02 E1 55 - 23 00 02 22 FF - 23 00 02 1E 68 - 23 00 02 4C FF - 23 00 02 48 68 - 23 00 02 73 FF - 23 00 02 6F 68 - 23 00 02 99 FF - 23 00 02 95 68 - 23 00 02 C1 FF - 23 00 02 BD 68 - 23 00 02 E7 FF - 23 00 02 E3 68 - 23 00 02 1F 7E - 23 00 02 49 7E - 23 00 02 70 7E - 23 00 02 96 7E - 23 00 02 BE 7E - 23 00 02 E4 7E - 23 00 02 20 97 - 23 00 02 4A 97 - 23 00 02 71 97 - 23 00 02 97 97 - 23 00 02 BF 97 - 23 00 02 E5 97 - 23 00 02 21 B5 - 23 00 02 4B B5 - 23 00 02 72 B5 - 23 00 02 98 B5 - 23 00 02 C0 B5 - 23 00 02 E6 B5 - 23 00 02 25 F0 - 23 00 02 23 E8 - 23 00 02 4F F0 - 23 00 02 4D E8 - 23 00 02 76 F0 - 23 00 02 74 E8 - 23 00 02 9C F0 - 23 00 02 9A E8 - 23 00 02 C4 F0 - 23 00 02 C2 E8 - 23 00 02 EA F0 - 23 00 02 E8 E8 - 23 00 02 24 FF - 23 00 02 4E FF - 23 00 02 75 FF - 23 00 02 9B FF - 23 00 02 C3 FF - 23 00 02 E9 FF - 23 00 02 FE 3D - 23 00 02 00 04 - 23 00 02 FE 23 - 23 00 02 08 82 - 23 00 02 0A 00 - 23 00 02 0B 00 - 23 00 02 0C 01 - 23 00 02 16 00 - 23 00 02 18 02 - 23 00 02 1B 04 - 23 00 02 19 04 - 23 00 02 1C 81 - 23 00 02 1F 00 - 23 00 02 20 03 - 23 00 02 23 04 - 23 00 02 21 01 - 23 00 02 54 63 - 23 00 02 55 54 - 23 00 02 6E 45 - 23 00 02 6D 36 - 23 00 02 FE 3D - 23 00 02 55 78 - 23 00 02 FE 20 - 23 00 02 26 30 - 23 00 02 FE 3D - 23 00 02 20 71 - 23 00 02 50 8F - 23 00 02 51 8F - 23 00 02 FE 00 - 23 00 02 35 00 - 05 78 01 11 - 05 1E 01 29 - ]; - - panel-exit-sequence = [ - 05 00 01 28 - 05 00 01 10 - ]; - - disp_timings0: display-timings { - native-mode = <&dsi0_timing0>; - dsi0_timing0: timing0 { - clock-frequency = <132000000>; - hactive = <1080>; - vactive = <1920>; - hfront-porch = <15>; - hsync-len = <4>; - hback-porch = <30>; - vfront-porch = <15>; - vsync-len = <2>; - vback-porch = <15>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - panel_in_dsi: endpoint { - remote-endpoint = <&dsi_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi>; - }; - }; - }; - -}; - -&dsi1 { - status = "okay"; - //rockchip,lane-rate = <1000>; - dsi1_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight>; - reset-delay-ms = <60>; - enable-delay-ms = <60>; - prepare-delay-ms = <60>; - unprepare-delay-ms = <60>; - disable-delay-ms = <60>; - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | - MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - panel-init-sequence = [ - 23 00 02 FE 21 - 23 00 02 04 00 - 23 00 02 00 64 - 23 00 02 2A 00 - 23 00 02 26 64 - 23 00 02 54 00 - 23 00 02 50 64 - 23 00 02 7B 00 - 23 00 02 77 64 - 23 00 02 A2 00 - 23 00 02 9D 64 - 23 00 02 C9 00 - 23 00 02 C5 64 - 23 00 02 01 71 - 23 00 02 27 71 - 23 00 02 51 71 - 23 00 02 78 71 - 23 00 02 9E 71 - 23 00 02 C6 71 - 23 00 02 02 89 - 23 00 02 28 89 - 23 00 02 52 89 - 23 00 02 79 89 - 23 00 02 9F 89 - 23 00 02 C7 89 - 23 00 02 03 9E - 23 00 02 29 9E - 23 00 02 53 9E - 23 00 02 7A 9E - 23 00 02 A0 9E - 23 00 02 C8 9E - 23 00 02 09 00 - 23 00 02 05 B0 - 23 00 02 31 00 - 23 00 02 2B B0 - 23 00 02 5A 00 - 23 00 02 55 B0 - 23 00 02 80 00 - 23 00 02 7C B0 - 23 00 02 A7 00 - 23 00 02 A3 B0 - 23 00 02 CE 00 - 23 00 02 CA B0 - 23 00 02 06 C0 - 23 00 02 2D C0 - 23 00 02 56 C0 - 23 00 02 7D C0 - 23 00 02 A4 C0 - 23 00 02 CB C0 - 23 00 02 07 CF - 23 00 02 2F CF - 23 00 02 58 CF - 23 00 02 7E CF - 23 00 02 A5 CF - 23 00 02 CC CF - 23 00 02 08 DD - 23 00 02 30 DD - 23 00 02 59 DD - 23 00 02 7F DD - 23 00 02 A6 DD - 23 00 02 CD DD - 23 00 02 0E 15 - 23 00 02 0A E9 - 23 00 02 36 15 - 23 00 02 32 E9 - 23 00 02 5F 15 - 23 00 02 5B E9 - 23 00 02 85 15 - 23 00 02 81 E9 - 23 00 02 AD 15 - 23 00 02 A9 E9 - 23 00 02 D3 15 - 23 00 02 CF E9 - 23 00 02 0B 14 - 23 00 02 33 14 - 23 00 02 5C 14 - 23 00 02 82 14 - 23 00 02 AA 14 - 23 00 02 D0 14 - 23 00 02 0C 36 - 23 00 02 34 36 - 23 00 02 5D 36 - 23 00 02 83 36 - 23 00 02 AB 36 - 23 00 02 D1 36 - 23 00 02 0D 6B - 23 00 02 35 6B - 23 00 02 5E 6B - 23 00 02 84 6B - 23 00 02 AC 6B - 23 00 02 D2 6B - 23 00 02 13 5A - 23 00 02 0F 94 - 23 00 02 3B 5A - 23 00 02 37 94 - 23 00 02 64 5A - 23 00 02 60 94 - 23 00 02 8A 5A - 23 00 02 86 94 - 23 00 02 B2 5A - 23 00 02 AE 94 - 23 00 02 D8 5A - 23 00 02 D4 94 - 23 00 02 10 D1 - 23 00 02 38 D1 - 23 00 02 61 D1 - 23 00 02 87 D1 - 23 00 02 AF D1 - 23 00 02 D5 D1 - 23 00 02 11 04 - 23 00 02 39 04 - 23 00 02 62 04 - 23 00 02 88 04 - 23 00 02 B0 04 - 23 00 02 D6 04 - 23 00 02 12 05 - 23 00 02 3A 05 - 23 00 02 63 05 - 23 00 02 89 05 - 23 00 02 B1 05 - 23 00 02 D7 05 - 23 00 02 18 AA - 23 00 02 14 36 - 23 00 02 42 AA - 23 00 02 3D 36 - 23 00 02 69 AA - 23 00 02 65 36 - 23 00 02 8F AA - 23 00 02 8B 36 - 23 00 02 B7 AA - 23 00 02 B3 36 - 23 00 02 DD AA - 23 00 02 D9 36 - 23 00 02 15 74 - 23 00 02 3F 74 - 23 00 02 66 74 - 23 00 02 8C 74 - 23 00 02 B4 74 - 23 00 02 DA 74 - 23 00 02 16 9F - 23 00 02 40 9F - 23 00 02 67 9F - 23 00 02 8D 9F - 23 00 02 B5 9F - 23 00 02 DB 9F - 23 00 02 17 DC - 23 00 02 41 DC - 23 00 02 68 DC - 23 00 02 8E DC - 23 00 02 B6 DC - 23 00 02 DC DC - 23 00 02 1D FF - 23 00 02 19 03 - 23 00 02 47 FF - 23 00 02 43 03 - 23 00 02 6E FF - 23 00 02 6A 03 - 23 00 02 94 FF - 23 00 02 90 03 - 23 00 02 BC FF - 23 00 02 B8 03 - 23 00 02 E2 FF - 23 00 02 DE 03 - 23 00 02 1A 35 - 23 00 02 44 35 - 23 00 02 6B 35 - 23 00 02 91 35 - 23 00 02 B9 35 - 23 00 02 DF 35 - 23 00 02 1B 45 - 23 00 02 45 45 - 23 00 02 6C 45 - 23 00 02 92 45 - 23 00 02 BA 45 - 23 00 02 E0 45 - 23 00 02 1C 55 - 23 00 02 46 55 - 23 00 02 6D 55 - 23 00 02 93 55 - 23 00 02 BB 55 - 23 00 02 E1 55 - 23 00 02 22 FF - 23 00 02 1E 68 - 23 00 02 4C FF - 23 00 02 48 68 - 23 00 02 73 FF - 23 00 02 6F 68 - 23 00 02 99 FF - 23 00 02 95 68 - 23 00 02 C1 FF - 23 00 02 BD 68 - 23 00 02 E7 FF - 23 00 02 E3 68 - 23 00 02 1F 7E - 23 00 02 49 7E - 23 00 02 70 7E - 23 00 02 96 7E - 23 00 02 BE 7E - 23 00 02 E4 7E - 23 00 02 20 97 - 23 00 02 4A 97 - 23 00 02 71 97 - 23 00 02 97 97 - 23 00 02 BF 97 - 23 00 02 E5 97 - 23 00 02 21 B5 - 23 00 02 4B B5 - 23 00 02 72 B5 - 23 00 02 98 B5 - 23 00 02 C0 B5 - 23 00 02 E6 B5 - 23 00 02 25 F0 - 23 00 02 23 E8 - 23 00 02 4F F0 - 23 00 02 4D E8 - 23 00 02 76 F0 - 23 00 02 74 E8 - 23 00 02 9C F0 - 23 00 02 9A E8 - 23 00 02 C4 F0 - 23 00 02 C2 E8 - 23 00 02 EA F0 - 23 00 02 E8 E8 - 23 00 02 24 FF - 23 00 02 4E FF - 23 00 02 75 FF - 23 00 02 9B FF - 23 00 02 C3 FF - 23 00 02 E9 FF - 23 00 02 FE 3D - 23 00 02 00 04 - 23 00 02 FE 23 - 23 00 02 08 82 - 23 00 02 0A 00 - 23 00 02 0B 00 - 23 00 02 0C 01 - 23 00 02 16 00 - 23 00 02 18 02 - 23 00 02 1B 04 - 23 00 02 19 04 - 23 00 02 1C 81 - 23 00 02 1F 00 - 23 00 02 20 03 - 23 00 02 23 04 - 23 00 02 21 01 - 23 00 02 54 63 - 23 00 02 55 54 - 23 00 02 6E 45 - 23 00 02 6D 36 - 23 00 02 FE 3D - 23 00 02 55 78 - 23 00 02 FE 20 - 23 00 02 26 30 - 23 00 02 FE 3D - 23 00 02 20 71 - 23 00 02 50 8F - 23 00 02 51 8F - 23 00 02 FE 00 - 23 00 02 35 00 - 05 78 01 11 - 05 1E 01 29 - ]; - - panel-exit-sequence = [ - 05 00 01 28 - 05 00 01 10 - ]; - - disp_timings1: display-timings { - native-mode = <&dsi1_timing0>; - dsi1_timing0: timing0 { - clock-frequency = <132000000>; - hactive = <1080>; - vactive = <1920>; - hfront-porch = <15>; - hsync-len = <4>; - hback-porch = <30>; - vfront-porch = <15>; - vsync-len = <2>; - vback-porch = <15>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - panel_in_dsi1: endpoint { - remote-endpoint = <&dsi1_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi1_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi1>; - }; - }; - }; - -}; - -&dsi0_panel { - power-supply = <&vcc3v3_lcd_n>; - reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_rst_gpio>; - dsi,lanes = <8>; - panel-init-sequence = [ - 29 02 02 00 00 - 29 02 03 99 95 27 - 05 78 01 11 - 05 01 01 29 - 29 00 02 00 00 - 29 01 03 99 00 00 - ]; - - panel-exit-sequence = [ - 29 00 02 00 00 - 29 00 03 99 95 27 - 05 01 01 28 - 05 01 01 10 - ]; - - disp_timings0: display-timings { - native-mode = <&dsi0_timing0>; - dsi0_timing0: timing0 { - clock-frequency = <246000000>; - hactive = <1600>; - vactive = <2176>; - hfront-porch = <18>; - hsync-len = <8>; - hback-porch = <32>; - vfront-porch = <255>; - vsync-len = <6>; - vback-porch = <34>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; -}; - -&dsi1_in_vp2 { - status = "disabled"; -}; - -&dsi1_in_vp3 { - status = "disabled"; -}; - -&dsi1_panel { - power-supply = <&vcc3v3_lcd_n>; - compressed-data; - /* - * because in hardware, the two screens share the reset pin, - * so reset-gpios need only in dsi1 enable and dsi0 disabled - * case. - */ - - //reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; - //pinctrl-names = "default"; - //pinctrl-0 = <&lcd_rst_gpio>; - - dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - - slice-width = <720>; - slice-height = <65>; - version-major = <1>; - version-minor = <1>; - - panel-init-sequence = [ - 29 10 03 f0 5a 5a - /* Dsc Setting */ - /* Compression Enable */ - 07 10 01 01 - /* Scaler Disable */ - 15 10 02 c3 00 - /* PPS Setting */ - 0a 31 59 10 00 00 89 30 80 0c 30 05 a0 00 41 02 d0 02 d0 02 00 02 c2 00 20 06 58 00 0a 00 0f 01 e0 01 2d 18 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a 78 1a b6 2a b6 2a f4 2a f4 4b 34 63 74 00 - 29 10 03 f0 a5 a5 - /** Sleep Out */ - 05 00 01 11 - /* 4. Common Setting */ - /* 4.1 TE(Vync) ON/OFF */ - 15 00 02 35 00 - /* 4.2 CASET/PASET Setting */ - 39 00 05 2a 00 00 05 9F - 39 00 05 2b 00 00 0c 2f - /* 4.3 TSP SYNC Setting */ - 39 00 03 f0 5a 5a - 39 00 0a B9 01 c0 3c 0b 00 00 00 11 03 - 39 00 03 f0 a5 a5 - /* FD(Fast Discharge) Setting */ - 39 00 03 f0 5a 5a - 15 00 02 b0 45 - 15 00 02 b5 48 - 39 00 03 f0 a5 a5 - /* 4.6 FFC Setting (MIPI CLK 529MHz) */ - 39 00 03 f0 5a 5a - 39 00 03 fc 5a 5a - 15 00 02 b0 1E - 39 00 06 c5 09 10 b4 24 fb - 39 00 03 f0 a5 a5 - 39 00 03 fc a5 a5 - /* OSC Spread Setting */ - 39 00 03 f0 5a 5a - 39 00 03 fc 5a 5a - 15 00 02 b0 37 - /* FFC Setting; 0x04 : Disable */ - 39 00 06 c5 04 ff 00 01 64 - 39 00 03 f0 a5 a5 - 39 00 03 fc a5 a5 - /* Dither IP Setting */ - 39 00 03 FC 5A 5A - 15 00 02 b0 86 - 15 00 02 eb 01 - 39 00 03 FC a5 a5 - /* 5 Brightness Control */ - /* 5.1 Dimming Setting */ - 39 10 03 f0 5a 5a - 15 10 02 b0 05 - 15 10 02 b1 01 - 15 10 02 b0 02 - 15 10 02 b5 d3 - 15 10 02 53 20 - 39 10 03 f0 a5 a5 - 39 10 03 51 02 ff - 05 32 01 29 - ]; - - panel-exit-sequence = [ - /* Display off */ - 05 14 01 28 - /* Sleep In */ - 05 00 01 10 - /* VCI stabilization setting */ - 39 00 03 f0 5a 5a - 15 00 02 b0 05 - 15 00 02 f4 01 - 39 a0 03 f0 a5 a5 - ]; - - disp_timings1: display-timings { - native-mode = <&dsi1_timing0>; - dsi1_timing0: timing0 { - clock-frequency = <280000000>; - hactive = <1140>; - vactive = <3120>; - hfront-porch = <16>; - hsync-len = <8>; - hback-porch = <8>; - vfront-porch = <4>; - vsync-len = <2>; - vback-porch = <16>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - mem-supply = <&vdd_gpu_mem_s0>; - upthreshold = <60>; - downdifferential = <30>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - - vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big0_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { - compatible = "rockchip,rk8603"; - reg = <0x43>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big1_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - - cw2015@62 { - status = "okay"; - compatible = "cellwise,cw2015"; - reg = <0x62>; - cellwise,battery-profile = /bits/ 8 - <0x17 0x67 0x6C 0x66 0x65 0x64 0x61 0x5B - 0x5F 0x75 0x49 0x52 0x50 0x51 0x48 0x3D - 0x34 0x2C 0x29 0x21 0x23 0x2D 0x40 0x49 - 0x25 0x5C 0x0B 0x85 0x10 0x1F 0x31 0x49 - 0x58 0x5E 0x63 0x6C 0x3E 0x1D 0x9A 0x35 - 0x0A 0x33 0x15 0x3B 0x70 0x99 0xAB 0x17 - 0x40 0x75 0x99 0xC4 0x80 0xB5 0xDE 0xCB - 0x2F 0x00 0x64 0xA5 0xB5 0x00 0xF8 0x39>; - cellwise,monitor-interval-ms = <5000>; - power-supplies = <&bq25895>; - }; - - bq25895: charger@6a { - compatible = "ti,bq25895", "ti,bq25890"; - reg = <0x6a>; - pinctrl-names = "default"; - pinctrl-0 = <&charger_ok>; - interrupt-parent = <&gpio3>; - interrupts = ; - otg-mode-en-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; - ti,usb-charger-detection = <&usbc0>; - - ti,battery-regulation-voltage = <4400000>; /* 4.4V */ - ti,charge-current = <1600000>; /* 1.6A */ - ti,termination-current = <66000>; /* 66mA */ - ti,precharge-current = <130000>; /* 130mA */ - ti,minimum-sys-voltage = <3000000>; /* 3V */ - ti,boost-voltage = <5000000>; /* 5V */ - ti,boost-max-current = <1600000>; /* 1600mA */ - regulators { - vbus5v0_typec: vbus5v0-typec { - regulator-compatible = "otg-vbus"; - regulator-name = "vbus5v0_typec"; - }; - }; - }; - - vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_npu_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c3 { - status = "okay"; - - es8388: es8388@11 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "everest,es8388", "everest,es8323"; - reg = <0x11>; - clocks = <&mclkout_i2s0>; - clock-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk>; - }; - - aw87xxx_pa1: aw87xxx_pa1@58 { - compatible = "awinic,aw87xxx_pa"; - #sound-dai-cells = <0>; - reg = <0x58>; - dev_index = < 0 >; - status = "okay"; - }; - - aw87xxx_pa2: aw87xxx_pa2@59 { - compatible = "awinic,aw87xxx_pa"; - #sound-dai-cells = <0>; - reg = <0x59>; - dev_index = < 1 >; - status = "okay"; - }; -}; - -&i2c4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4m3_xfer>; - - focaltech: focaltech@38 { - status = "okay"; - compatible = "focaltech,fts"; - reg = <0x38>; - power-supply = <&vcc3v3_lcd_n>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_gpio>; - focaltech,irq-gpio = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>; - focaltech,reset-gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - focaltech,have-key = <0>; - focaltech,key-number = <3>; - focaltech,keys = <256 1068 64 64 128 1068 64 64 192 1068 64 64>; - focaltech,key-x-coord = <1600>; - focaltech,key-y-coord = <2176>; - focaltech,max-touch-number = <5>; - }; -}; - -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - //pinctrl-0 = <&i2c5m3_xfer>; - pinctrl-0 = <&i2c5m0_xfer>; - - ls_ucs14620: light@38 { - compatible = "ls_ucs14620"; - status = "okay"; - reg = <0x38>; - type = ; - irq_enable = <0>; - als_threshold_high = <100>; - als_threshold_low = <10>; - als_ctrl_gain = <3>;/* 0:x1 1:x4 2:x16 3:x64 */ - als_ctrl_time = <0x9f>; - poll_delay_ms = <100>; - }; - - ps_ucs14620: proximity@38 { - status = "okay"; - compatible = "ps_ucs14620"; - reg = <0x38>; - type = ; - //pinctrl-names = "default"; - //pinctrl-0 = <&gpio3_c6>; - irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>; - irq_enable = <0>; - ps_threshold_high = <0x20>; - ps_threshold_low = <0x1d>; - ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */ - ps_led_current = <3>; /* 0:12.5mA 1:100mA 2:150mA 3:200mA*/ - poll_delay_ms = <100>; - }; - - regulator@3e { - compatible = "tps65132"; - reg = <0x3e>; - - outp { - regulator-name = "LCD_AVDD"; //P - vin-supply = <&vcc5v0_sys>; - /*pinctrl-names = "default";*/ - /*pinctrl-0 = <&pinctrl_dsibiasen>;*/ - /*enable = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;*/ - /*enable-active-high;*/ - }; - - outn { - regulator-name = "LCD_AVEE"; - vin-supply = <&vcc5v0_sys>; - /*enable = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>;*/ - }; - }; -}; - -&i2c8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8m2_xfer>; - - usbc0: fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio0>; - interrupts = ; - int-n-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vbus5v0_typec>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - ; - source-pdos = - ; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&u2phy0_orientation_switch>; - }; - }; - }; - - }; - }; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - status = "okay"; - }; -}; - -&i2s0_8ch { - status = "okay"; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; -}; - -&iep { - status = "okay"; -}; - -&iep_mmu { - status = "okay"; -}; - -&jpegd { - status = "okay"; -}; - -&jpegd_mmu { - status = "okay"; -}; - -&jpege0 { - status = "okay"; -}; - -&jpege0_mmu { - status = "okay"; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&mipi_dcphy1 { - status = "okay"; -}; - -&mpp_srv { - status = "okay"; -}; - -&pcie2x1l2 { - reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; - rockchip,skip-scan-in-resume; - status = "okay"; -}; - -&pdm0 { - status = "okay"; -}; - -&pinctrl { - charger { - charger_ok: charger_ok { - rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>, - <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - lcd { - lcd_rst_gpio: lcd-rst-gpio { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - touch { - touch_gpio: touch-gpio { - rockchip,pins = - <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_host_en1: vcc5v0-host-en1 { - rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - usbc0_int: usbc0-int { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - /* - *typec5v_pwren: typec5v-pwren { - * rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - *}; - */ - }; - - wireless-bluetooth { - uart8_gpios: uart8-gpios { - rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reset_gpio: bt-reset-gpio { - rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_gpio: bt-wake-gpio { - rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_host_irq: bt-wake-host-irq { - rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - wifi_poweren_gpio: wifi-poweren-gpio { - rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm13 { - status = "okay"; - pinctrl-names = "active"; - pinctrl-0 = <&pwm13m1_pins>; -}; - -&rga2 { - status = "okay"; -}; - -&rga3_core0 { - status = "okay"; -}; - -&rga3_0_mmu { - status = "okay"; -}; - -&rga3_core1 { - status = "okay"; -}; - -&rga3_1_mmu { - status = "okay"; -}; - -&rkvdec_ccu { - status = "okay"; -}; - -&rkvdec0 { - status = "okay"; -}; - -&rkvdec0_mmu { - status = "okay"; -}; - -&rkvenc0 { - venc-supply = <&vdd_vdenc_s0>; - mem-supply = <&vdd_vdenc_mem_s0>; - status = "okay"; -}; - -&rkvenc0_mmu { - status = "okay"; -}; - -&rockchip_suspend { - status = "okay"; - rockchip,sleep-debug-en = <1>; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp2_out_dsi0>; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc_1v8_s0>; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - max-frequency = <200000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&spi2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - num-cs = <1>; -}; - -&tsadc { - status = "okay"; -}; - -&uart8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>; -}; - -&u2phy0 { - orientation-switch; - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - u2phy0_orientation_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; - }; - }; -}; - -&u2phy0_otg { - rockchip,sel-pipe-phystatus; - rockchip,typec-vbus-det; - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - status = "okay"; - - maximum-speed = "high-speed"; - phys = <&u2phy0_otg>; - phy-names = "usb2-phy"; - usb-role-switch; - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -&vdpu { - status = "okay"; -}; - -&vdpu_mmu { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp1 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | - 1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; - rockchip,primary-plane = ; -}; - -&vp2 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2 | - 1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; - rockchip,primary-plane = ; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-tablet-single.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-tablet-single.dtsi deleted file mode 100644 index 1d60dcae0..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-tablet-single.dtsi +++ /dev/null @@ -1,1393 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "rk3588s.dtsi" -#include "rk3588-android.dtsi" -#include "rk3588-rk806-single.dtsi" - -/ { - adc_keys: adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - vol-up-key { - label = "volume up"; - linux,code = ; - press-threshold-microvolt = <17000>; - }; - - vol-down-key { - label = "volume down"; - linux,code = ; - press-threshold-microvolt = <417000>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm14 0 25000 0>; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - charge-animation { - compatible = "rockchip,uboot-charge"; - rockchip,uboot-charge-on = <1>; - rockchip,android-charge-on = <0>; - rockchip,uboot-low-power-voltage = <6800>; - rockchip,screen-on-voltage = <6900>; - rockchip,uboot-exit-charge-level = <2>; - rockchip,uboot-exit-charge-auto = <0>; - rockchip,system-suspend = <1>; - regulator-on-in-mem = <&vdd_log_s0>, <&vcc_2v0_pldo_s3>, - <&vdd2_ddr_s3>, <&vcc_1v8_s3>, <&avcc_1v8_s0>, - <&vcc_1v8_s0>, <&vdd_0v75_s3>, <&pldo6_s3>, - <&vcc_3v3_s3>; - - regulator-off-in-mem = <&vdd_gpu_s0>, <&vdd_npu_s0>, - <&vdd_vdenc_s0>, <&vdd_gpu_mem_s0>, <&vdd_npu_mem_s0>, - <&vdd_vdenc_mem_s0>, <&vcc_3v3_s0>, - <&vccio_sd_s0>, <&avdd_0v75_s0>, <&vdd_0v85_s0>, - <&vdd_cpu_big1_s0>, <&vdd_cpu_big0_s0>, <&vdd_cpu_lit_s0>, - <&vdd_cpu_big1_mem_s0>, <&vdd_cpu_big0_mem_s0>, <&vdd_cpu_lit_mem_s0>, - <&vddq_ddr_s0>, <&vdd_ddr_s0>, <&vdd_ddr_pll_s0>, - <&avdd_1v2_s0>, <&vdd_0v75_s0>; - status = "okay"; - }; - - es7202_sound_micarray: es7202-sound-micarray { - status = "okay"; - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip,sound-micarray"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,dai-link@0 { - format = "pdm"; - cpu { - sound-dai = <&pdm0>; - }; - codec { - sound-dai = <&es7202>; - }; - }; - }; - - es8388_sound: es8388-sound { - status = "okay"; - compatible = "rockchip,multicodecs-card"; - rockchip,card-name = "rockchip,es8388-codec"; - hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; - io-channels = <&saradc 3>; - io-channel-names = "adc-detect"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - spk-con-gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - hp-con-gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; - rockchip,format = "i2s"; - rockchip,mclk-fs = <256>; - rockchip,cpu = <&i2s0_8ch>; - rockchip,codec = <&es8388>; - rockchip,audio-routing = - "Headphone", "LOUT1", - "Headphone", "ROUT1", - "Speaker", "LOUT2", - "Speaker", "ROUT2", - "Headphone", "Headphone Power", - "Headphone", "Headphone Power", - "Speaker", "Speaker Power", - "Speaker", "Speaker Power", - "LINPUT1", "Main Mic", - "LINPUT2", "Main Mic", - "RINPUT1", "Headset Mic", - "RINPUT2", "Headset Mic"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - play-pause-key { - label = "playpause"; - linux,code = ; - press-threshold-microvolt = <2000>; - }; - }; - - hall_sensor: hall-mh248 { - compatible = "hall-mh248"; - pinctrl-names = "default"; - pinctrl-0 = <&mh248_irq_gpio>; - irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_EDGE_BOTH>; - hall-active = <1>; - status = "okay"; - }; - - panel-edp { - compatible = "innolux,p120zdg-bf4", "simple-panel"; - backlight = <&backlight>; - power-supply = <&vcc3v3_lcd_edp>; - prepare-delay-ms = <120>; - enable-delay-ms = <120>; - unprepare-delay-ms = <500>; - disable-delay-ms = <120>; - width-mm = <254>; - height-mm = <169>; - - panel-timing { - clock-frequency = <206000000>; - hactive = <2160>; - vactive = <1440>; - hfront-porch = <48>; - hsync-len = <32>; - hback-porch = <80>; - vfront-porch = <3>; - vsync-len = <10>; - vback-porch = <27>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - panel_in_edp: endpoint { - remote-endpoint = <&edp_out_panel>; - }; - }; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_enable_h>; - /* - * On the module itself this is one of these (depending - * on the actual card populated): - * - SDIO_RESET_L_WL_REG_ON - * - PDN (power down when low) - */ - post-power-on-delay-ms = <200>; - reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_en>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc3v3_lcd_edp: vcc3v3-lcd-edp { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd_edp"; - regulator-boot-on; - gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sd_s0_pwr>; - regulator-always-on; - regulator-max-microvolt = <3000000>; - regulator-min-microvolt = <3000000>; - regulator-name = "vcc_3v3_sd_s0"; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc5v0_host: vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - }; - - vcc_mipidcphy: vcc-mipidcphy-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipidcphy_pwr>; - regulator-name = "vcc_mipidcphy"; - enable-active-high; - regulator-boot-on; - }; - - wireless_bluetooth: wireless-bluetooth { - compatible = "bluetooth-platdata"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - uart_rts_gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "rts_gpio"; - pinctrl-0 = <&uart7m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; - pinctrl-1 = <&uart7_gpios>; - BT,reset_gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - BT,wake_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - BT,wake_host_irq = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - wifi_chip_type = "ap6398s"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_irq>; - WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - WIFI,poweren_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; -}; - -&av1d_mmu { - status = "okay"; -}; - -&combphy0_ps { - status = "okay"; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&csi2_dcphy0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_ov50c40: endpoint@1 { - reg = <1>; - remote-endpoint = <&ov50c40_out>; - data-lanes = <1 2 3 4>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidcphy0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi0_csi2_input>; - }; - }; - }; -}; - -&csi2_dcphy1 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_ucam1: endpoint@1 { - reg = <1>; - remote-endpoint = <&ov13855_out>; - data-lanes = <1 2 3 4>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidcphy1_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi1_csi2_input>; - }; - }; - }; -}; - -&dp0 { - status = "okay"; -}; - -&dp0_in_vp1 { - status = "okay"; -}; - -&edp0 { - support-psr; - force-hpd; - status = "okay"; - - ports { - port@1 { - reg = <1>; - - edp_out_panel: endpoint { - remote-endpoint = <&panel_in_edp>; - }; - }; - }; -}; - -&edp0_in_vp2 { - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - mem-supply = <&vdd_gpu_mem_s0>; - upthreshold = <60>; - downdifferential = <30>; - status = "okay"; -}; - -&hdptxphy0 { - /* Single Vdiff Training Table for power reduction (optional) */ - training-table = /bits/ 8 < - /* voltage swing 0, pre-emphasis 0->3 */ - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - /* voltage swing 1, pre-emphasis 0->2 */ - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - /* voltage swing 2, pre-emphasis 0->1 */ - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - /* voltage swing 3, pre-emphasis 0 */ - 0x0d 0x00 0x00 0x00 0x00 0x00 - >; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - - vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big0_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { - compatible = "rockchip,rk8603"; - reg = <0x43>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big1_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c2 { - status = "okay"; - - vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_npu_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c3 { - status = "okay"; - - es8388: es8388@11 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "everest,es8388", "everest,es8323"; - reg = <0x11>; - clocks = <&mclkout_i2s0>; - clock-names = "mclk"; - assigned-clocks = <&mclkout_i2s0>; - assigned-clock-rates = <12288000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk>; - }; - - es7202: es7202@32 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "ES7202_PDM_ADC_1"; - power-supply = <&avcc_1v8_s0>; /* only 1v8 or 3v3, default is 3v3 */ - reg = <0x32>; - }; -}; - -&i2c4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4m3_xfer>; - - elan_touch: elan_ktf@10 { - status = "okay"; - compatible = "elan,ektf"; - reg = <0x10>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_gpio>; - elan,rst-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; - elan,irq-gpio = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>; - chip_type = <0x01>; /* 1:HID IIC, 0: NORMAL IIC */ - report_type = <0x01>; /* 1:B protocol, 0:A protocol */ - }; -}; - -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5m2_xfer>; - - mpu6500_acc: mpu_acc@68 { - status = "okay"; - compatible = "mpu6500_acc"; - reg = <0x68>; - irq-gpio = <&gpio1 RK_PD3 IRQ_TYPE_EDGE_RISING>; - irq_enable = <0>; - poll_delay_ms = <30>; - type = ; - layout = <5>; - }; - - mpu6500_gyro: mpu_gyro@68 { - status = "okay"; - compatible = "mpu6500_gyro"; - reg = <0x68>; - poll_delay_ms = <30>; - type = ; - layout = <5>; - }; -}; - -&i2c6 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6m3_xfer>; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; - - cw2015@62 { - status = "okay"; - compatible = "cellwise,cw2015"; - reg = <0x62>; - cellwise,battery-profile = /bits/ 8 - <0x17 0x67 0x6C 0x66 0x65 0x64 0x61 0x5B - 0x5F 0x75 0x49 0x52 0x50 0x51 0x48 0x3D - 0x34 0x2C 0x29 0x21 0x23 0x2D 0x40 0x49 - 0x25 0x5C 0x0B 0x85 0x10 0x1F 0x31 0x49 - 0x58 0x5E 0x63 0x6C 0x3E 0x1D 0x9A 0x35 - 0x0A 0x33 0x15 0x3B 0x70 0x99 0xAB 0x17 - 0x40 0x75 0x99 0xC4 0x80 0xB5 0xDE 0xCB - 0x2F 0x00 0x64 0xA5 0xB5 0x00 0xF8 0x39>; - cellwise,dual-cell = <1>; - cellwise,monitor-interval-ms = <5000>; - power-supplies = <&bq25703>; - }; - - bq25703: bq25703@6b { - status = "okay"; - compatible = "ti,bq25703"; - reg = <0x6b>; - ti,usb-charger-detection = <&usbc0>; - - interrupt-parent = <&gpio0>; - interrupts = ; - otg-mode-en-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&charger_ok>; - extcon = <&u2phy0>; - ti,charge-current = <2500000>; - ti,max-input-voltage = <20000000>; - ti,max-input-current = <6000000>; - ti,max-charge-voltage = <8750000>; - ti,input-current = <500000>; - ti,input-current-sdp = <500000>; - ti,input-current-dcp = <2000000>; - ti,input-current-cdp = <2000000>; - ti,minimum-sys-voltage = <7400000>; - ti,otg-voltage = <5000000>; - ti,otg-current = <1500000>; - pd-charge-only = <0>; - regulators { - vbus5v0_typec: vbus5v0-typec { - regulator-compatible = "otg-vbus"; - regulator-name = "vbus5v0_typec"; - }; - }; - }; -}; - -&i2c7 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7m2_xfer>; - - aw8601: aw8601@c { - compatible = "awinic,aw8601"; - status = "okay"; - reg = <0x0c>; - rockchip,vcm-start-current = <56>; - rockchip,vcm-rated-current = <96>; - rockchip,vcm-step-mode = <4>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - }; - - ov13855: ov13855@10 { - compatible = "ovti,ov13855"; - status = "okay"; - reg = <0x10>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - pinctrl-names = "default"; - pinctrl-0 = <&mipim1_camera4_clk>; - rockchip,grf = <&sys_grf>; - reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; - pwdn-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; - avdd-supply = <&vcc_mipidcphy>; - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "front"; - rockchip,camera-module-name = "CMK-OT2016-FV1"; - rockchip,camera-module-lens-name = "default"; - port { - ov13855_out: endpoint { - remote-endpoint = <&mipi_in_ucam1>; - data-lanes = <1 2 3 4>; - }; - }; - }; - - ov50c40: ov50c40@36 { - compatible = "ovti,ov50c40"; - status = "okay"; - reg = <0x36>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - pinctrl-names = "default"; - pinctrl-0 = <&mipim1_camera1_clk>; - rockchip,grf = <&sys_grf>; - reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>; - pwdn-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; - avdd-supply = <&vcc_mipidcphy>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "HZGA06"; - rockchip,camera-module-lens-name = "ZE0082C1"; - eeprom-ctrl = <&otp_eeprom>; - lens-focus = <&aw8601>; - port { - ov50c40_out: endpoint { - remote-endpoint = <&mipi_in_ov50c40>; - data-lanes = <1 2 3 4>; - }; - }; - }; - - otp_eeprom: otp_eeprom@50 { - compatible = "rk,otp_eeprom"; - status = "okay"; - reg = <0x50>; - }; -}; - -&i2c8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8m2_xfer>; - - usbc0: fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio0>; - interrupts = ; - int-n-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vbus5v0_typec>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - ; - source-pdos = - ; - - altmodes { - #address-cells = <1>; - #size-cells = <0>; - - altmode@0 { - reg = <0>; - svid = <0xff01>; - vdo = <0xffffffff>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; - }; - }; - - port@1 { - reg = <1>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; - }; - }; - }; - }; - }; -}; - -&i2s0_8ch { - status = "okay"; - rockchip,clk-trcm = <1>; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; -}; - -&iep { - status = "okay"; -}; - -&iep_mmu { - status = "okay"; -}; - -&jpegd { - status = "okay"; -}; - -&jpegd_mmu { - status = "okay"; -}; - -&jpege_ccu { - status = "okay"; -}; - -&jpege0 { - status = "okay"; -}; - -&jpege0_mmu { - status = "okay"; -}; - -&jpege1 { - status = "okay"; -}; - -&jpege1_mmu { - status = "okay"; -}; - -&jpege2 { - status = "okay"; -}; - -&jpege2_mmu { - status = "okay"; -}; - -&jpege3 { - status = "okay"; -}; - -&jpege3_mmu { - status = "okay"; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&mipi_dcphy1 { - status = "okay"; -}; - -&mipi0_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidcphy0_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in0>; - }; - }; - }; -}; - -&mipi1_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi1_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidcphy1_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi1_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in1>; - }; - }; - }; -}; - -&mpp_srv { - status = "okay"; -}; - -&pdm0 { - rockchip,path-map = <2 0 1 3>; - status = "okay"; -}; - -&pinctrl { - cam { - mipidcphy_pwr: mipidcphy-pwr { - rockchip,pins = - /* camera power en */ - <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - charger { - charger_ok: charger_ok { - rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - headphone { - hp_det: hp-det { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - rtc_int: rtc-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdmmc { - sd_s0_pwr: sd-s0-pwr { - rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sensor { - mpu6500_irq_gpio: mpu6500-irq-gpio { - rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - mh248_irq_gpio: mh248-irq-gpio { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - touch { - touch_gpio: touch-gpio { - rockchip,pins = - <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - vcc5v0_usb_en: vcc5v0-usb-en { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - usbc0_int: usbc0-int { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - wireless-bluetooth { - uart7_gpios: uart7-gpios { - rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reset_gpio: bt-reset-gpio { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_gpio: bt-wake-gpio { - rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_irq_gpio: bt-irq-gpio { - rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - wifi_poweren_gpio: wifi-poweren-gpio { - rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm14 { - pinctrl-0 = <&pwm14m1_pins>; - status = "okay"; -}; - -&rga3_core0 { - status = "okay"; -}; - -&rga3_0_mmu { - status = "okay"; -}; - -&rga3_core1 { - status = "okay"; -}; - -&rga3_1_mmu { - status = "okay"; -}; - -&rga2 { - status = "okay"; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds { - status = "okay"; - - port { - cif_mipi_in0: endpoint { - remote-endpoint = <&mipi0_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds_sditf { - status = "okay"; - - port { - mipi_lvds_sditf: endpoint { - remote-endpoint = <&isp1_in1>; - }; - }; -}; - -&rkcif_mipi_lvds1 { - status = "okay"; - - port { - cif_mipi_in1: endpoint { - remote-endpoint = <&mipi1_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds1_sditf { - status = "okay"; - - port { - mipi1_lvds_sditf: endpoint { - remote-endpoint = <&isp1_in2>; - }; - }; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp_unite { - status = "okay"; - -}; - -&rkisp_unite_mmu { - status = "okay"; -}; - -&rkisp0_vir0 { - status = "okay"; - /* - * dual isp process image case - * other rkisp hw and virtual nodes should disabled - */ - rockchip,hw = <&rkisp_unite>; - port { - #address-cells = <1>; - #size-cells = <0>; - - isp1_in1: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds_sditf>; - }; - isp1_in2: endpoint@1 { - reg = <1>; - remote-endpoint = <&mipi1_lvds_sditf>; - }; - }; -}; - -&rknpu { - rknpu-supply = <&vdd_npu_s0>; - mem-supply = <&vdd_npu_mem_s0>; - status = "okay"; -}; - -&rknpu_mmu { - status = "okay"; -}; - -&rkvdec_ccu { - status = "okay"; -}; - -&rkvdec0 { - status = "okay"; -}; - -&rkvdec0_mmu { - status = "okay"; -}; - -&rkvdec1 { - status = "okay"; -}; - -&rkvdec1_mmu { - status = "okay"; -}; - -&vepu { - status = "okay"; -}; - -&rkvenc_ccu { - status = "okay"; -}; - -&rkvenc0 { - venc-supply = <&vdd_vdenc_s0>; - mem-supply = <&vdd_vdenc_mem_s0>; - status = "okay"; -}; - -&rkvenc0_mmu { - status = "okay"; -}; - -&rkvenc1 { - venc-supply = <&vdd_vdenc_s0>; - mem-supply = <&vdd_vdenc_mem_s0>; - status = "okay"; -}; - -&rkvenc1_mmu { - status = "okay"; -}; - -&rockchip_suspend { - status = "okay"; - rockchip,sleep-debug-en = <1>; -}; - -&route_edp0 { - connect = <&vp2_out_edp0>; - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&vcc_1v8_s0>; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - max-frequency = <200000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&sdio { - max-frequency = <150000000>; - no-sd; - no-mmc; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdiom1_pins>; - sd-uhs-sdr104; - status = "okay"; -}; - -&sdmmc { - max-frequency = <150000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_sd_s0>; - vqmmc-supply = <&vccio_sd_s0>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; - status = "okay"; -}; - -&tsadc { - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7m1_xfer &uart7m1_ctsn>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy0_otg { - rockchip,typec-vbus-det; - status = "okay"; -}; - -&u2phy2_host { - status = "okay"; - phy-supply = <&vcc5v0_host>; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usbdp_phy0 { - orientation-switch; - svid = <0xff01>; - sbu1-dc-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>; - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - usbdp_phy0_orientation_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; - }; - - usbdp_phy0_dp_altmode_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&dp_altmode_mux>; - }; - }; -}; - -&usbdp_phy0_dp { - status = "okay"; -}; - -&usbdp_phy0_u3 { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - status = "okay"; - - usb-role-switch; - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -&usbhost3_0 { - status = "disabled"; -}; - -&usbhost_dwc3_0 { - status = "disabled"; -}; - -&vdpu { - status = "okay"; -}; - -&vdpu_mmu { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp1 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | - 1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; - rockchip,primary-plane = ; -}; - -&vp2 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2 | - 1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; - rockchip,primary-plane = ; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-tablet-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588s-tablet-v10.dts deleted file mode 100644 index 0394d8e15..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-tablet-v10.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588s-tablet.dtsi" - -/ { - model = "Rockchip RK3588S TABLET V10 Board"; - compatible = "rockchip,rk3588s-tablet-v10", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-tablet-v11.dts b/arch/arm64/boot/dts/rockchip/rk3588s-tablet-v11.dts deleted file mode 100644 index 0cdfd47a2..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-tablet-v11.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -/dts-v1/; - -#include "rk3588s-tablet-single.dtsi" - -/ { - model = "Rockchip RK3588S TABLET V11 Board"; - compatible = "rockchip,rk3588s-tablet-v11", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi deleted file mode 100644 index 008ff6fb4..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi +++ /dev/null @@ -1,1320 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "rk3588s.dtsi" -#include "rk3588-android.dtsi" -#include "rk3588s-rk806-dual.dtsi" - -/ { - adc_keys: adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - vol-up-key { - label = "volume up"; - linux,code = ; - press-threshold-microvolt = <17000>; - }; - - vol-down-key { - label = "volume down"; - linux,code = ; - press-threshold-microvolt = <417000>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm12 0 25000 0>; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - battery: battery { - compatible = "simple-battery"; - charge-full-design-microamp-hours = <4500000>; - }; - - bt_sco: bt-sco { - status = "disabled"; - compatible = "delta,dfbmcs320"; - #sound-dai-cells = <1>; - }; - - bt_sound: bt-sound { - status = "disabled"; - compatible = "simple-audio-card"; - simple-audio-card,format = "dsp_a"; - simple-audio-card,bitclock-inversion = <0>; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "rockchip,bt"; - simple-audio-card,cpu { - sound-dai = <&i2s2_2ch>; - }; - simple-audio-card,codec { - sound-dai = <&bt_sco 1>; - }; - }; - - charge-animation { - compatible = "rockchip,uboot-charge"; - rockchip,uboot-charge-on = <1>; - rockchip,android-charge-on = <0>; - rockchip,uboot-low-power-voltage = <6800>; - rockchip,screen-on-voltage = <6900>; - rockchip,uboot-exit-charge-level = <2>; - rockchip,uboot-exit-charge-auto = <0>; - rockchip,system-suspend = <1>; - regulator-on-in-mem = <&vdd_log_s0>, <&vcc_2v0_pldo_s3>, - <&vdd2_ddr_s3>, <&vcc_1v1_nldo_s3>, - <&vdd1_1v8_ddr_s3>, <&vcc_1v8_s3>, - <&master_pldo6_s3>, <&vdd_0v75_s3>, - <&vdd2l_0v9_ddr_s3>, <&vdd_1v8_pll_s0>, <&pldo6_s3>; - - regulator-off-in-mem = <&vdd_gpu_s0>, <&vdd_npu_s0>, - <&vdd_vdenc_s0>, <&vdd_gpu_mem_s0>, <&vdd_npu_mem_s0>, - <&vdd_vdenc_mem_s0>, <&avcc_1v8_s0>, <&vcc_3v3_s0>, - <&vccio_sd_s0>, <&master_nldo3>, <&avdd_0v75_s0>, - <&vdd_0v85_s0>, <&vdd_cpu_big1_s0>, <&vdd_cpu_big0_s0>, - <&vdd_cpu_lit_s0>, <&vdd_cpu_big1_mem_s0>, <&vdd_cpu_big0_mem_s0>, - <&vcc_1v8_s0>, <&vdd_cpu_lit_mem_s0>, <&vddq_ddr_s0>, - <&vdd_ddr_s0>, <&vcc_1v8_cam_s0>, <&avdd1v8_ddr_pll_s0>, - <&vcc_3v3_sd_s0>, <&vcc_2v8_cam_s0>, <&vdd_0v75_pll_s0>, - <&vdd_ddr_pll_s0>, <&slave_nldo3>, <&avdd_1v2_cam_s0>, - <&avdd_1v2_s0>, <&vcc_3v3_s3>; - status = "okay"; - }; - - dp0_sound: dp0-sound { - status = "okay"; - compatible = "rockchip,hdmi"; - rockchip,card-name= "rockchip-dp0"; - rockchip,mclk-fs = <512>; - rockchip,cpu = <&spdif_tx2>; - rockchip,codec = <&dp0 1>; - rockchip,jack-det; - }; - - es7202_sound_micarray: es7202-sound-micarray { - status = "okay"; - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rockchip,sound-micarray"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,dai-link@0 { - format = "pdm"; - cpu { - sound-dai = <&pdm0>; - }; - codec { - sound-dai = <&es7202>; - }; - }; - }; - - es8388_sound: es8388-sound { - status = "okay"; - compatible = "rockchip,multicodecs-card"; - rockchip,card-name = "rockchip,es8388-codec"; - hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; - io-channels = <&saradc 3>; - io-channel-names = "adc-detect"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - spk-con-gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - hp-con-gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; - rockchip,format = "i2s"; - rockchip,mclk-fs = <256>; - rockchip,cpu = <&i2s0_8ch>; - rockchip,codec = <&es8388>; - rockchip,audio-routing = - "Headphone", "LOUT1", - "Headphone", "ROUT1", - "Speaker", "LOUT2", - "Speaker", "ROUT2", - "Headphone", "Headphone Power", - "Headphone", "Headphone Power", - "Speaker", "Speaker Power", - "Speaker", "Speaker Power", - "LINPUT1", "Main Mic", - "LINPUT2", "Main Mic", - "RINPUT1", "Headset Mic", - "RINPUT2", "Headset Mic"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - play-pause-key { - label = "playpause"; - linux,code = ; - press-threshold-microvolt = <2000>; - }; - }; - - hall_sensor: hall-mh248 { - compatible = "hall-mh248"; - pinctrl-names = "default"; - pinctrl-0 = <&mh248_irq_gpio>; - irq-gpio = <&gpio1 RK_PA1 IRQ_TYPE_EDGE_BOTH>; - hall-active = <1>; - status = "okay"; - }; - - panel-edp { - compatible = "innolux,p120zdg-bf4", "simple-panel"; - backlight = <&backlight>; - power-supply = <&vcc3v3_lcd_edp>; - prepare-delay-ms = <120>; - enable-delay-ms = <120>; - unprepare-delay-ms = <500>; - disable-delay-ms = <120>; - width-mm = <254>; - height-mm = <169>; - - panel-timing { - clock-frequency = <206000000>; - hactive = <2160>; - vactive = <1440>; - hfront-porch = <48>; - hsync-len = <32>; - hback-porch = <80>; - vfront-porch = <3>; - vsync-len = <10>; - vback-porch = <27>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - - port { - panel_in_edp: endpoint { - remote-endpoint = <&edp0_out>; - }; - }; - }; - - vcc3v3_lcd_edp: vcc3v3-lcd-edp { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_lcd_edp"; - regulator-boot-on; - gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc5v0_host: vcc5v0-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc_mipidcphy1: vcc-mipidcphy1-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mipidcphy1_pwr>; - regulator-name = "vcc_mipidcphy1"; - enable-active-high; - regulator-always-on; - regulator-boot-on; - }; - - wireless_bluetooth: wireless-bluetooth { - compatible = "bluetooth-platdata"; - clocks = <&hym8563>; - clock-names = "ext_clock"; - uart_rts_gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "rts_gpio"; - pinctrl-0 = <&uart7m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; - pinctrl-1 = <&uart7_gpios>; - BT,reset_gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - BT,wake_gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; - BT,wake_host_irq = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - wireless_wlan: wireless-wlan { - compatible = "wlan-platdata"; - wifi_chip_type = "ap6275p"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; - WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - WIFI,poweren_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; -}; - -&av1d_mmu { - status = "okay"; -}; - -&avdd_1v2_cam_s0 { - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <12500>; -}; - -&combphy0_ps { - status = "okay"; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&dp0 { - status = "okay"; -}; - -&dp0_out { - link-frequencies = /bits/ 64 <5400000000>; -}; - -&dp0_in_vp1 { - status = "okay"; -}; - -&edp0 { - support-psr; - force-hpd; - status = "okay"; -}; - -&edp0_in_vp2 { - status = "okay"; -}; - -&edp0_out { - remote-endpoint = <&panel_in_edp>; -}; - -&fiq_debugger { - pinctrl-0 = <&uart2m1_xfer>; -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - mem-supply = <&vdd_gpu_mem_s0>; - status = "okay"; -}; - -&hdptxphy0 { - /* Single Vdiff Training Table for power reduction (optional) */ - training-table = /bits/ 8 < - /* voltage swing 0, pre-emphasis 0->3 */ - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - /* voltage swing 1, pre-emphasis 0->2 */ - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - /* voltage swing 2, pre-emphasis 0->1 */ - 0x0d 0x00 0x00 0x00 0x00 0x00 - 0x0d 0x00 0x00 0x00 0x00 0x00 - /* voltage swing 3, pre-emphasis 0 */ - 0x0d 0x00 0x00 0x00 0x00 0x00 - >; - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_int>; - - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; - - cw2015@62 { - status = "okay"; - compatible = "cellwise,cw2015"; - reg = <0x62>; - cellwise,battery-profile = /bits/ 8 - <0x17 0x67 0x6C 0x66 0x65 0x64 0x61 0x5B - 0x5F 0x75 0x49 0x52 0x50 0x51 0x48 0x3D - 0x34 0x2C 0x29 0x21 0x23 0x2D 0x40 0x49 - 0x25 0x5C 0x0B 0x85 0x10 0x1F 0x31 0x49 - 0x58 0x5E 0x63 0x6C 0x3E 0x1D 0x9A 0x35 - 0x0A 0x33 0x15 0x3B 0x70 0x99 0xAB 0x17 - 0x40 0x75 0x99 0xC4 0x80 0xB5 0xDE 0xCB - 0x2F 0x00 0x64 0xA5 0xB5 0x00 0xF8 0x39>; - cellwise,dual-cell = <1>; - cellwise,monitor-interval-ms = <5000>; - monitored-battery = <&battery>; - power-supplies = <&bq25703>; - }; - - bq25703: bq25703@6b { - status = "okay"; - compatible = "ti,bq25703"; - reg = <0x6b>; - ti,usb-charger-detection = <&usbc0>; - - interrupt-parent = <&gpio0>; - interrupts = ; - otg-mode-en-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&charger_ok>; - extcon = <&u2phy0>; - ti,charge-current = <2500000>; - ti,max-input-voltage = <20000000>; - ti,max-input-current = <6000000>; - ti,max-charge-voltage = <8750000>; - ti,input-current = <500000>; - ti,input-current-sdp = <500000>; - ti,input-current-dcp = <2000000>; - ti,input-current-cdp = <2000000>; - ti,minimum-sys-voltage = <7400000>; - ti,otg-voltage = <5000000>; - ti,otg-current = <1500000>; - pd-charge-only = <0>; - regulators { - vbus5v0_typec: vbus5v0-typec { - regulator-compatible = "otg-vbus"; - regulator-name = "vbus5v0_typec"; - }; - }; - }; -}; - -&i2c3 { - status = "okay"; - - es8388: es8388@11 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "everest,es8388", "everest,es8323"; - reg = <0x11>; - clocks = <&mclkout_i2s0>; - clock-names = "mclk"; - assigned-clocks = <&mclkout_i2s0>; - assigned-clock-rates = <12288000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk>; - }; - - es7202: es7202@32 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "ES7202_PDM_ADC_1"; - power-supply = <&vcc_1v8_s0>; /* only 1v8 or 3v3, default is 3v3 */ - reg = <0x32>; - }; -}; - -&i2c4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4m3_xfer>; - - elan_touch: elan_ktf@10 { - status = "okay"; - compatible = "elan,ektf"; - reg = <0x10>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_gpio>; - elan,rst-gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; - elan,irq-gpio = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>; - chip_type = <0x01>; /* 1:HID IIC, 0: NORMAL IIC */ - report_type = <0x01>; /* 1:B protocol, 0:A protocol */ - }; -}; - -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5m0_xfer>; - - mpu6500_acc: mpu_acc@68 { - status = "okay"; - compatible = "mpu6500_acc"; - reg = <0x68>; - irq-gpio = <&gpio3 RK_PB4 IRQ_TYPE_EDGE_RISING>; - irq_enable = <0>; - poll_delay_ms = <30>; - type = ; - layout = <5>; - }; - - mpu6500_gyro: mpu_gyro@68 { - status = "okay"; - compatible = "mpu6500_gyro"; - reg = <0x68>; - poll_delay_ms = <30>; - type = ; - layout = <5>; - }; -}; - -&i2c6 { - status = "disabled"; -}; - -&i2c7 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7m2_xfer>; - - aw8601: aw8601@c { - compatible = "awinic,aw8601"; - status = "okay"; - reg = <0x0c>; - rockchip,vcm-start-current = <56>; - rockchip,vcm-rated-current = <96>; - rockchip,vcm-step-mode = <4>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - }; - - ov13855: ov13855@10 { - compatible = "ovti,ov13855"; - status = "okay"; - reg = <0x10>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - pinctrl-names = "default"; - pinctrl-0 = <&mipim1_camera2_clk>; - rockchip,grf = <&sys_grf>; - reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; - pwdn-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "front"; - rockchip,camera-module-name = "CMK-OT2016-FV1"; - rockchip,camera-module-lens-name = "default"; - port { - ov13855_out: endpoint { - remote-endpoint = <&mipi_in_ucam1>; - data-lanes = <1 2 3 4>; - }; - }; - }; - - ov50c40: ov50c40@36 { - compatible = "ovti,ov50c40"; - status = "okay"; - reg = <0x36>; - clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - pinctrl-names = "default"; - pinctrl-0 = <&mipim1_camera1_clk>; - rockchip,grf = <&sys_grf>; - reset-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; - pwdn-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "HZGA06"; - rockchip,camera-module-lens-name = "ZE0082C1"; - eeprom-ctrl = <&otp_eeprom>; - lens-focus = <&aw8601>; - port { - ov50c40_out: endpoint { - remote-endpoint = <&mipi_in_ov50c40>; - data-lanes = <1 2 3 4>; - }; - }; - }; - - otp_eeprom: otp_eeprom@50 { - compatible = "rk,otp_eeprom"; - status = "okay"; - reg = <0x50>; - }; -}; - -&csi2_dcphy0 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_ov50c40: endpoint@1 { - reg = <1>; - remote-endpoint = <&ov50c40_out>; - data-lanes = <1 2 3 4>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidcphy0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi0_csi2_input>; - }; - }; - }; -}; - -&csi2_dcphy1 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi_in_ucam1: endpoint@1 { - reg = <1>; - remote-endpoint = <&ov13855_out>; - data-lanes = <1 2 3 4>; - }; - }; - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidcphy1_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi1_csi2_input>; - }; - }; - }; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&mipi_dcphy1 { - status = "okay"; -}; - -&mipi0_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidcphy0_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in0>; - }; - }; - }; -}; - -&mipi1_csi2 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi1_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidcphy1_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi1_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in1>; - }; - }; - }; -}; - -&i2c8 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8m2_xfer>; - - usbc0: fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio0>; - interrupts = ; - int-n-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vbus5v0_typec>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - ; - source-pdos = - ; - - altmodes { - #address-cells = <1>; - #size-cells = <0>; - - altmode@0 { - reg = <0>; - svid = <0xff01>; - vdo = <0xffffffff>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; - }; - }; - - port@1 { - reg = <1>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; - }; - }; - }; - }; - }; -}; - -&i2s0_8ch { - status = "okay"; - rockchip,clk-trcm = <1>; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; -}; - -&i2s2_2ch { - pinctrl-0 = <&i2s2m1_lrck &i2s2m1_sclk &i2s2m1_sdi &i2s2m1_sdo>; - rockchip,bclk-fs = <32>; - status = "disabled"; -}; - -&iep { - status = "okay"; -}; - -&iep_mmu { - status = "okay"; -}; - -&jpegd { - status = "okay"; -}; - -&jpegd_mmu { - status = "okay"; -}; - -&jpege_ccu { - status = "okay"; -}; - -&jpege0 { - status = "okay"; -}; - -&jpege0_mmu { - status = "okay"; -}; - -&jpege1 { - status = "okay"; -}; - -&jpege1_mmu { - status = "okay"; -}; - -&jpege2 { - status = "okay"; -}; - -&jpege2_mmu { - status = "okay"; -}; - -&jpege3 { - status = "okay"; -}; - -&jpege3_mmu { - status = "okay"; -}; - -&mpp_srv { - status = "okay"; -}; - -&pcie2x1l2 { - reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; - rockchip,skip-scan-in-resume; - status = "okay"; -}; - -&pdm0 { - rockchip,path-map = <2 0 1 3>; - status = "okay"; -}; - -&pinctrl { - cam { - mipidcphy1_pwr: mipidcphy1-pwr { - rockchip,pins = - /* camera power en */ - <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - charger { - charger_ok: charger_ok { - rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - headphone { - hp_det: hp-det { - rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hym8563 { - rtc_int: rtc-int { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sensor { - mpu6500_irq_gpio: mpu6500-irq-gpio { - rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - mh248_irq_gpio: mh248-irq-gpio { - rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - touch { - touch_gpio: touch-gpio { - rockchip,pins = - <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - usbc0_int: usbc0-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - wireless-bluetooth { - uart7_gpios: uart7-gpios { - rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_reset_gpio: bt-reset-gpio { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_wake_gpio: bt-wake-gpio { - rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - bt_irq_gpio: bt-irq-gpio { - rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - wireless-wlan { - wifi_host_wake_irq: wifi-host-wake-irq { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; - }; - - wifi_poweren_gpio: wifi-poweren-gpio { - rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; - -&pwm12 { - pinctrl-0 = <&pwm12m1_pins>; - status = "okay"; -}; - -&rga3_core0 { - status = "okay"; -}; - -&rga3_0_mmu { - status = "okay"; -}; - -&rga3_core1 { - status = "okay"; -}; - -&rga3_1_mmu { - status = "okay"; -}; - -&rga2 { - status = "okay"; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds { - status = "okay"; - - port { - cif_mipi_in0: endpoint { - remote-endpoint = <&mipi0_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds_sditf { - status = "okay"; - - port { - mipi_lvds_sditf: endpoint { - remote-endpoint = <&isp1_in1>; - }; - }; -}; - -&rkcif_mipi_lvds1 { - status = "okay"; - - port { - cif_mipi_in1: endpoint { - remote-endpoint = <&mipi1_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds1_sditf { - status = "okay"; - - port { - mipi1_lvds_sditf: endpoint { - remote-endpoint = <&isp1_in2>; - }; - }; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp_unite { - status = "okay"; - -}; - -&rkisp_unite_mmu { - status = "okay"; -}; - -&rkisp0_vir0 { - status = "okay"; - /* - * dual isp process image case - * other rkisp hw and virtual nodes should disabled - */ - rockchip,hw = <&rkisp_unite>; - port { - #address-cells = <1>; - #size-cells = <0>; - - isp1_in1: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds_sditf>; - }; - isp1_in2: endpoint@1 { - reg = <1>; - remote-endpoint = <&mipi1_lvds_sditf>; - }; - }; -}; - -&rknpu { - rknpu-supply = <&vdd_npu_s0>; - mem-supply = <&vdd_npu_mem_s0>; - status = "okay"; -}; - -&rknpu_mmu { - status = "okay"; -}; - -&rkvdec_ccu { - status = "okay"; -}; - -&rkvdec0 { - status = "okay"; -}; - -&rkvdec0_mmu { - status = "okay"; -}; - -&rkvdec1 { - status = "okay"; -}; - -&rkvdec1_mmu { - status = "okay"; -}; - -&rkvenc_ccu { - status = "okay"; -}; - -&rkvenc0 { - venc-supply = <&vdd_vdenc_s0>; - mem-supply = <&vdd_vdenc_mem_s0>; - status = "okay"; -}; - -&rkvenc0_mmu { - status = "okay"; -}; - -&rkvenc1 { - venc-supply = <&vdd_vdenc_s0>; - mem-supply = <&vdd_vdenc_mem_s0>; - status = "okay"; -}; - -&rkvenc1_mmu { - status = "okay"; -}; - -&rockchip_suspend { - status = "okay"; - rockchip,sleep-debug-en = <1>; -}; - -&route_edp0 { - connect = <&vp2_out_edp0>; - status = "okay"; -}; - -&saradc { - status = "okay"; - vref-supply = <&avcc_1v8_s0>; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - max-frequency = <200000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - status = "okay"; -}; - -&sdmmc { - max-frequency = <150000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_sd_s0>; - vqmmc-supply = <&vccio_sd_s0>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; - status = "okay"; -}; - -&spdif_tx2 { - status = "okay"; -}; - -&tsadc { - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7m1_xfer &uart7m1_ctsn>; - status = "okay"; -}; - -&u2phy0 { - status = "okay"; -}; - -&u2phy2 { - status = "okay"; -}; - -&u2phy0_otg { - rockchip,typec-vbus-det; - status = "okay"; -}; - -&u2phy2_host { - status = "okay"; - phy-supply = <&vcc5v0_host>; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usbdp_phy0 { - orientation-switch; - svid = <0xff01>; - sbu1-dc-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>; - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - usbdp_phy0_orientation_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; - }; - - usbdp_phy0_dp_altmode_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&dp_altmode_mux>; - }; - }; -}; - -&usbdp_phy0_dp { - status = "okay"; -}; - -&usbdp_phy0_u3 { - status = "okay"; -}; - -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - status = "okay"; - - usb-role-switch; - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -&usbhost3_0 { - status = "disabled"; -}; - -&usbhost_dwc3_0 { - status = "disabled"; -}; - -&vdpu { - status = "okay"; -}; - -&vdpu_mmu { - status = "okay"; -}; - -&vepu { - status = "okay"; -}; - -&vop { - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp1 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | - 1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; - rockchip,primary-plane = ; -}; - -&vp2 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2 | - 1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; - rockchip,primary-plane = ; -}; diff --git a/arch/arm64/boot/dts/socionext/Makefile b/arch/arm64/boot/dts/socionext/Makefile deleted file mode 100644 index dda3da336..000000000 --- a/arch/arm64/boot/dts/socionext/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_UNIPHIER) += \ - uniphier-ld11-global.dtb \ - uniphier-ld11-ref.dtb \ - uniphier-ld20-akebi96.dtb \ - uniphier-ld20-global.dtb \ - uniphier-ld20-ref.dtb \ - uniphier-pxs3-ref.dtb diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts deleted file mode 100644 index da44a15a8..000000000 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts +++ /dev/null @@ -1,171 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier LD11 Global Board -// -// Copyright (C) 2016-2017 Socionext Inc. -// Author: Masahiro Yamada -// Kunihiko Hayashi - -/dts-v1/; -#include -#include "uniphier-ld11.dtsi" - -/ { - model = "UniPhier LD11 Global Board (REF_LD11_GP)"; - compatible = "socionext,uniphier-ld11-global", - "socionext,uniphier-ld11"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - ethernet0 = ð - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; - - dvdd_reg: reg-fixed { - compatible = "regulator-fixed"; - regulator-name = "DVDD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - amp_vcc_reg: reg-fixed { - compatible = "regulator-fixed"; - regulator-name = "AMP_VCC"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - }; - - sound { - compatible = "audio-graph-card"; - label = "UniPhier LD11"; - widgets = "Headphone", "Headphones"; - dais = <&i2s_port2 - &i2s_port3 - &i2s_port4 - &spdif_port0 - &comp_spdif_port0>; - hp-det-gpio = <&gpio UNIPHIER_GPIO_IRQ(0) GPIO_ACTIVE_LOW>; - }; - - spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - - port@0 { - spdif_tx: endpoint { - remote-endpoint = <&spdif_hiecout1>; - }; - }; - }; - - comp-spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - - port@0 { - comp_spdif_tx: endpoint { - remote-endpoint = <&comp_spdif_hiecout1>; - }; - }; - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&i2s_hpcmout1 { - dai-format = "i2s"; - remote-endpoint = <&tas_speaker>; -}; - -&spdif_hiecout1 { - remote-endpoint = <&spdif_tx>; -}; - -&comp_spdif_hiecout1 { - remote-endpoint = <&comp_spdif_tx>; -}; - -&i2c0 { - status = "okay"; - - tas5707a@1d { - compatible = "ti,tas5711"; - reg = <0x1d>; - reset-gpios = <&gpio UNIPHIER_GPIO_PORT(23, 4) GPIO_ACTIVE_LOW>; - pdn-gpios = <&gpio UNIPHIER_GPIO_PORT(23, 5) GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - AVDD-supply = <&dvdd_reg>; - DVDD-supply = <&dvdd_reg>; - PVDD_A-supply = <&_vcc_reg>; - PVDD_B-supply = <&_vcc_reg>; - PVDD_C-supply = <&_vcc_reg>; - PVDD_D-supply = <&_vcc_reg>; - - port@0 { - tas_speaker: endpoint { - dai-format = "i2s"; - remote-endpoint = <&i2s_hpcmout1>; - }; - }; - }; - - eeprom@50 { - compatible = "st,24c64", "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -ð { - status = "okay"; - phy-handle = <ðphy>; -}; - -&mdio { - ethphy: ethernet-phy@1 { - reg = <1>; - }; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - }; -}; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts deleted file mode 100644 index 617d2b1e9..000000000 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier LD11 Reference Board -// -// Copyright (C) 2016 Socionext Inc. -// Author: Masahiro Yamada - -/dts-v1/; -#include "uniphier-ld11.dtsi" -#include "uniphier-ref-daughter.dtsi" -#include "uniphier-support-card.dtsi" - -/ { - model = "UniPhier LD11 Reference Board"; - compatible = "socionext,uniphier-ld11-ref", "socionext,uniphier-ld11"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serialsc; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - ethernet0 = ð - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; -}; - -ðsc { - interrupts = <0 8>; -}; - -&serialsc { - interrupts = <0 8>; -}; - -&serial0 { - status = "okay"; -}; - -&gpio { - xirq0 { - gpio-hog; - gpios = ; - input; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -ð { - status = "okay"; - phy-handle = <ðphy>; -}; - -&mdio { - ethphy: ethernet-phy@1 { - reg = <1>; - }; -}; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi deleted file mode 100644 index 15dcfc259..000000000 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ /dev/null @@ -1,663 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier LD11 SoC -// -// Copyright (C) 2016 Socionext Inc. -// Author: Masahiro Yamada - -#include -#include - -/ { - compatible = "socionext,uniphier-ld11"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 0x000>; - clocks = <&sys_clk 33>; - enable-method = "psci"; - operating-points-v2 = <&cluster0_opp>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 0x001>; - clocks = <&sys_clk 33>; - enable-method = "psci"; - operating-points-v2 = <&cluster0_opp>; - }; - }; - - cluster0_opp: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-245000000 { - opp-hz = /bits/ 64 <245000000>; - clock-latency-ns = <300>; - }; - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - clock-latency-ns = <300>; - }; - opp-490000000 { - opp-hz = /bits/ 64 <490000000>; - clock-latency-ns = <300>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - clock-latency-ns = <300>; - }; - opp-653334000 { - opp-hz = /bits/ 64 <653334000>; - clock-latency-ns = <300>; - }; - opp-666667000 { - opp-hz = /bits/ 64 <666667000>; - clock-latency-ns = <300>; - }; - opp-980000000 { - opp-hz = /bits/ 64 <980000000>; - clock-latency-ns = <300>; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - clocks { - refclk: ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 4>, - <1 14 4>, - <1 11 4>, - <1 10 4>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure-memory@81000000 { - reg = <0x0 0x81000000 0x0 0x01000000>; - no-map; - }; - }; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - - spi0: spi@54006000 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 39 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - spi1: spi@54006100 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006100 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 216 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&peri_clk 12>; - resets = <&peri_rst 12>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&peri_clk 0>; - resets = <&peri_rst 0>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&peri_clk 1>; - resets = <&peri_rst 1>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&peri_clk 2>; - resets = <&peri_rst 2>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = <0 177 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&peri_clk 3>; - resets = <&peri_rst 3>; - }; - - gpio: gpio@55000000 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000000 0x200>; - interrupt-parent = <&aidet>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 0>, - <&pinctrl 43 0 0>, - <&pinctrl 51 0 0>, - <&pinctrl 96 0 0>, - <&pinctrl 160 0 0>, - <&pinctrl 184 0 0>; - gpio-ranges-group-names = "gpio_range0", - "gpio_range1", - "gpio_range2", - "gpio_range3", - "gpio_range4", - "gpio_range5"; - ngpios = <200>; - socionext,interrupt-ranges = <0 48 16>, <16 154 5>, - <21 217 3>; - }; - - audio@56000000 { - compatible = "socionext,uniphier-ld11-aio"; - reg = <0x56000000 0x80000>; - interrupts = <0 144 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aout1>, - <&pinctrl_aoutiec1>; - clock-names = "aio"; - clocks = <&sys_clk 40>; - reset-names = "aio"; - resets = <&sys_rst 40>; - #sound-dai-cells = <1>; - socionext,syscon = <&soc_glue>; - - i2s_port0: port@0 { - i2s_hdmi: endpoint { - }; - }; - - i2s_port1: port@1 { - i2s_pcmin2: endpoint { - }; - }; - - i2s_port2: port@2 { - i2s_line: endpoint { - dai-format = "i2s"; - remote-endpoint = <&evea_line>; - }; - }; - - i2s_port3: port@3 { - i2s_hpcmout1: endpoint { - }; - }; - - i2s_port4: port@4 { - i2s_hp: endpoint { - dai-format = "i2s"; - remote-endpoint = <&evea_hp>; - }; - }; - - spdif_port0: port@5 { - spdif_hiecout1: endpoint { - }; - }; - - src_port0: port@6 { - i2s_epcmout2: endpoint { - }; - }; - - src_port1: port@7 { - i2s_epcmout3: endpoint { - }; - }; - - comp_spdif_port0: port@8 { - comp_spdif_hiecout1: endpoint { - }; - }; - }; - - codec@57900000 { - compatible = "socionext,uniphier-evea"; - reg = <0x57900000 0x1000>; - clock-names = "evea", "exiv"; - clocks = <&sys_clk 41>, <&sys_clk 42>; - reset-names = "evea", "exiv", "adamv"; - resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>; - #sound-dai-cells = <1>; - - port@0 { - evea_line: endpoint { - remote-endpoint = <&i2s_line>; - }; - }; - - port@1 { - evea_hp: endpoint { - remote-endpoint = <&i2s_hp>; - }; - }; - }; - - adamv@57920000 { - compatible = "socionext,uniphier-ld11-adamv", - "simple-mfd", "syscon"; - reg = <0x57920000 0x1000>; - - adamv_rst: reset { - compatible = "socionext,uniphier-ld11-adamv-reset"; - #reset-cells = <1>; - }; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - resets = <&peri_rst 4>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - resets = <&peri_rst 5>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - clocks = <&peri_clk 6>; - resets = <&peri_rst 6>; - clock-frequency = <400000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - resets = <&peri_rst 7>; - clock-frequency = <100000>; - }; - - i2c4: i2c@58784000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58784000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 45 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - clocks = <&peri_clk 8>; - resets = <&peri_rst 8>; - clock-frequency = <100000>; - }; - - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&peri_clk 9>; - resets = <&peri_rst 9>; - clock-frequency = <400000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_system_bus>; - }; - - smpctrl@59801000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - sdctrl@59810000 { - compatible = "socionext,uniphier-ld11-sdctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x400>; - - sd_rst: reset { - compatible = "socionext,uniphier-ld11-sd-reset"; - #reset-cells = <1>; - }; - }; - - perictrl@59820000 { - compatible = "socionext,uniphier-ld11-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - peri_clk: clock { - compatible = "socionext,uniphier-ld11-peri-clock"; - #clock-cells = <1>; - }; - - peri_rst: reset { - compatible = "socionext,uniphier-ld11-peri-reset"; - #reset-cells = <1>; - }; - }; - - emmc: mmc@5a000000 { - compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; - reg = <0x5a000000 0x400>; - interrupts = <0 78 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc>; - clocks = <&sys_clk 4>; - resets = <&sys_rst 4>; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-pwrseq = <&emmc_pwrseq>; - cdns,phy-input-delay-legacy = <9>; - cdns,phy-input-delay-mmc-highspeed = <2>; - cdns,phy-input-delay-mmc-ddr = <3>; - cdns,phy-dll-delay-sdclk = <21>; - cdns,phy-dll-delay-sdclk-hsmmc = <21>; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 243 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, - <&mio_clk 12>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, - <&mio_rst 12>; - phy-names = "usb"; - phys = <&usb_phy0>; - has-transaction-translator; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 244 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, - <&mio_clk 13>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, - <&mio_rst 13>; - phy-names = "usb"; - phys = <&usb_phy1>; - has-transaction-translator; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 245 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, - <&mio_clk 14>; - resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, - <&mio_rst 14>; - phy-names = "usb"; - phys = <&usb_phy2>; - has-transaction-translator; - }; - - mioctrl@5b3e0000 { - compatible = "socionext,uniphier-ld11-mioctrl", - "simple-mfd", "syscon"; - reg = <0x5b3e0000 0x800>; - - mio_clk: clock { - compatible = "socionext,uniphier-ld11-mio-clock"; - #clock-cells = <1>; - }; - - mio_rst: reset { - compatible = "socionext,uniphier-ld11-mio-reset"; - #reset-cells = <1>; - resets = <&sys_rst 7>; - }; - }; - - soc_glue: soc-glue@5f800000 { - compatible = "socionext,uniphier-ld11-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-ld11-pinctrl"; - }; - - usb-phy { - compatible = "socionext,uniphier-ld11-usb2-phy"; - #address-cells = <1>; - #size-cells = <0>; - - usb_phy0: phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - - usb_phy1: phy@1 { - reg = <1>; - #phy-cells = <0>; - }; - - usb_phy2: phy@2 { - reg = <2>; - #phy-cells = <0>; - }; - }; - }; - - soc-glue@5f900000 { - compatible = "socionext,uniphier-ld11-soc-glue-debug", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5f900000 0x2000>; - - efuse@100 { - compatible = "socionext,uniphier-efuse"; - reg = <0x100 0x28>; - }; - - efuse@200 { - compatible = "socionext,uniphier-efuse"; - reg = <0x200 0x68>; - }; - }; - - xdmac: dma-controller@5fc10000 { - compatible = "socionext,uniphier-xdmac"; - reg = <0x5fc10000 0x5300>; - interrupts = <0 188 4>; - dma-channels = <16>; - #dma-cells = <2>; - }; - - aidet: interrupt-controller@5fc20000 { - compatible = "socionext,uniphier-ld11-aidet"; - reg = <0x5fc20000 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gic: interrupt-controller@5fe00000 { - compatible = "arm,gic-v3"; - reg = <0x5fe00000 0x10000>, /* GICD */ - <0x5fe40000 0x80000>; /* GICR */ - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <1 9 4>; - }; - - sysctrl@61840000 { - compatible = "socionext,uniphier-ld11-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x10000>; - - sys_clk: clock { - compatible = "socionext,uniphier-ld11-clock"; - #clock-cells = <1>; - }; - - sys_rst: reset { - compatible = "socionext,uniphier-ld11-reset"; - #reset-cells = <1>; - }; - - watchdog { - compatible = "socionext,uniphier-wdt"; - }; - }; - - eth: ethernet@65000000 { - compatible = "socionext,uniphier-ld11-ave4"; - status = "disabled"; - reg = <0x65000000 0x8500>; - interrupts = <0 66 4>; - clock-names = "ether"; - clocks = <&sys_clk 6>; - reset-names = "ether"; - resets = <&sys_rst 6>; - phy-mode = "internal"; - local-mac-address = [00 00 00 00 00 00]; - socionext,syscon-phy-mode = <&soc_glue 0>; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - nand: nand-controller@68000000 { - compatible = "socionext,uniphier-denali-nand-v5b"; - status = "disabled"; - reg-names = "nand_data", "denali_reg"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 65 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - clock-names = "nand", "nand_x", "ecc"; - clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; - reset-names = "nand", "reg"; - resets = <&sys_rst 2>, <&sys_rst 2>; - }; - }; -}; - -#include "uniphier-pinctrl.dtsi" - -&pinctrl_aoutiec1 { - drive-strength = <4>; /* default: 4mA */ - - ao1arc { - pins = "AO1ARC"; - drive-strength = <8>; /* 8mA */ - }; -}; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts deleted file mode 100644 index aa159a112..000000000 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts +++ /dev/null @@ -1,189 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for Akebi96 Development Board -// -// Derived from uniphier-ld20-global.dts. -// -// Copyright (C) 2015-2017 Socionext Inc. -// Copyright (C) 2019-2020 Linaro Ltd. - -/dts-v1/; -#include -#include "uniphier-ld20.dtsi" - -/ { - model = "Akebi96"; - compatible = "socionext,uniphier-ld20-akebi96", - "socionext,uniphier-ld20"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - ethernet0 = ð - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0xc0000000>; - }; - - framebuffer@c0000000 { - compatible = "simple-framebuffer"; - reg = <0 0xc0000000 0 0x02000000>; - width = <1920>; - height = <1080>; - stride = <7680>; - format = "a8r8g8b8"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - memory@c0000000 { - reg = <0 0xc0000000 0 0x02000000>; - no-map; - }; - }; - - sound { - compatible = "audio-graph-card"; - label = "UniPhier LD20"; - dais = <&spdif_port0 - &comp_spdif_port0>; - }; - - spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - - port@0 { - spdif_tx: endpoint { - remote-endpoint = <&spdif_hiecout1>; - }; - }; - }; - - comp-spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - - port@0 { - comp_spdif_tx: endpoint { - remote-endpoint = <&comp_spdif_hiecout1>; - }; - }; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; -}; - -&spi3 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - usb-over-spi@0 { - compatible = "maxim,max3421-udc"; - reg = <0>; - spi-max-frequency = <12500000>; - interrupt-parent = <&gpio>; - interrupt-names = "udc"; - interrupts = <0 2>; - }; -}; - -&serial0 { - /* Onboard USB-UART */ - status = "okay"; -}; - -&serial2 { - /* LS connector UART1 */ - status = "okay"; -}; - -&serial3 { - /* LS connector UART0 */ - status = "okay"; -}; - -&spdif_hiecout1 { - remote-endpoint = <&spdif_tx>; -}; - -&comp_spdif_hiecout1 { - remote-endpoint = <&comp_spdif_tx>; -}; - -&i2c0 { - /* LS connector I2C0 */ - status = "okay"; -}; - -&i2c1 { - /* LS connector I2C1 */ - status = "okay"; -}; - -ð { - status = "okay"; - phy-handle = <ðphy>; -}; - -&mdio { - ethphy: ethernet-phy@0 { - reg = <0>; - }; -}; - -&usb { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&gpio { - /* IRQs for Max3421 */ - xirq0 { - gpio-hog; - gpios = ; - input; - }; - xirq10 { - gpio-hog; - gpios = ; - input; - }; -}; - -&pinctrl_aout1 { - groups = "aout1b"; -}; - -&pinctrl_uart3 { - groups = "uart3", "uart3_ctsrts"; -}; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts deleted file mode 100644 index a01579cb3..000000000 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts +++ /dev/null @@ -1,155 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier LD20 Global Board -// -// Copyright (C) 2015-2017 Socionext Inc. -// Author: Masahiro Yamada -// Kunihiko Hayashi - -/dts-v1/; -#include -#include "uniphier-ld20.dtsi" - -/ { - model = "UniPhier LD20 Global Board (REF_LD20_GP)"; - compatible = "socionext,uniphier-ld20-global", - "socionext,uniphier-ld20"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - ethernet0 = ð - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0xc0000000>; - }; - - dvdd_reg: reg-fixed { - compatible = "regulator-fixed"; - regulator-name = "DVDD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - amp_vcc_reg: reg-fixed { - compatible = "regulator-fixed"; - regulator-name = "AMP_VCC"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - sound { - compatible = "audio-graph-card"; - label = "UniPhier LD20"; - widgets = "Headphone", "Headphones"; - dais = <&i2s_port2 - &i2s_port3 - &i2s_port4 - &spdif_port0 - &comp_spdif_port0>; - hp-det-gpio = <&gpio UNIPHIER_GPIO_IRQ(0) GPIO_ACTIVE_LOW>; - }; - - spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - - port@0 { - spdif_tx: endpoint { - remote-endpoint = <&spdif_hiecout1>; - }; - }; - }; - - comp-spdif-out { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - - port@0 { - comp_spdif_tx: endpoint { - remote-endpoint = <&comp_spdif_hiecout1>; - }; - }; - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&i2s_hpcmout1 { - dai-format = "i2s"; - remote-endpoint = <&tas_speaker>; -}; - -&spdif_hiecout1 { - remote-endpoint = <&spdif_tx>; -}; - -&comp_spdif_hiecout1 { - remote-endpoint = <&comp_spdif_tx>; -}; - -&i2c0 { - status = "okay"; - - tas5707@1b { - compatible = "ti,tas5711"; - reg = <0x1b>; - reset-gpios = <&gpio UNIPHIER_GPIO_PORT(0, 0) GPIO_ACTIVE_LOW>; - pdn-gpios = <&gpio UNIPHIER_GPIO_PORT(0, 1) GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - AVDD-supply = <&dvdd_reg>; - DVDD-supply = <&dvdd_reg>; - PVDD_A-supply = <&_vcc_reg>; - PVDD_B-supply = <&_vcc_reg>; - PVDD_C-supply = <&_vcc_reg>; - PVDD_D-supply = <&_vcc_reg>; - - port@0 { - tas_speaker: endpoint { - dai-format = "i2s"; - remote-endpoint = <&i2s_hpcmout1>; - }; - }; - }; -}; - -ð { - status = "okay"; - phy-mode = "rmii"; - pinctrl-0 = <&pinctrl_ether_rmii>; - phy-handle = <ðphy>; -}; - -&mdio { - ethphy: ethernet-phy@1 { - reg = <1>; - }; -}; - -&usb { - status = "okay"; -}; - -&nand { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts deleted file mode 100644 index 39ee279a1..000000000 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier LD20 Reference Board -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -/dts-v1/; -#include "uniphier-ld20.dtsi" -#include "uniphier-ref-daughter.dtsi" -#include "uniphier-support-card.dtsi" - -/ { - model = "UniPhier LD20 Reference Board"; - compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serialsc; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - ethernet0 = ð - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0xc0000000>; - }; -}; - -ðsc { - interrupts = <0 8>; -}; - -&serialsc { - interrupts = <0 8>; -}; - -&serial0 { - status = "okay"; -}; - -&gpio { - xirq0 { - gpio-hog; - gpios = ; - input; - }; -}; - -&i2c0 { - status = "okay"; -}; - -ð { - status = "okay"; - phy-handle = <ðphy>; -}; - -&mdio { - ethphy: ethernet-phy@0 { - reg = <0>; - }; -}; - -&pinctrl_ether_rgmii { - tx { - pins = "RGMII_TXCLK", "RGMII_TXD0", "RGMII_TXD1", - "RGMII_TXD2", "RGMII_TXD3", "RGMII_TXCTL"; - drive-strength = <9>; - }; -}; - -&usb { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi deleted file mode 100644 index 8f2c1c1e2..000000000 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ /dev/null @@ -1,982 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier LD20 SoC -// -// Copyright (C) 2015-2016 Socionext Inc. -// Author: Masahiro Yamada - -#include -#include -#include - -/ { - compatible = "socionext,uniphier-ld20"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu2>; - }; - core1 { - cpu = <&cpu3>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0 0x000>; - clocks = <&sys_clk 32>; - enable-method = "psci"; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a72"; - reg = <0 0x001>; - clocks = <&sys_clk 32>; - enable-method = "psci"; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - }; - - cpu2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 0x100>; - clocks = <&sys_clk 33>; - enable-method = "psci"; - operating-points-v2 = <&cluster1_opp>; - #cooling-cells = <2>; - }; - - cpu3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 0x101>; - clocks = <&sys_clk 33>; - enable-method = "psci"; - operating-points-v2 = <&cluster1_opp>; - #cooling-cells = <2>; - }; - }; - - cluster0_opp: opp-table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - clock-latency-ns = <300>; - }; - opp-275000000 { - opp-hz = /bits/ 64 <275000000>; - clock-latency-ns = <300>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - clock-latency-ns = <300>; - }; - opp-550000000 { - opp-hz = /bits/ 64 <550000000>; - clock-latency-ns = <300>; - }; - opp-666667000 { - opp-hz = /bits/ 64 <666667000>; - clock-latency-ns = <300>; - }; - opp-733334000 { - opp-hz = /bits/ 64 <733334000>; - clock-latency-ns = <300>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - clock-latency-ns = <300>; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - clock-latency-ns = <300>; - }; - }; - - cluster1_opp: opp-table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - clock-latency-ns = <300>; - }; - opp-275000000 { - opp-hz = /bits/ 64 <275000000>; - clock-latency-ns = <300>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - clock-latency-ns = <300>; - }; - opp-550000000 { - opp-hz = /bits/ 64 <550000000>; - clock-latency-ns = <300>; - }; - opp-666667000 { - opp-hz = /bits/ 64 <666667000>; - clock-latency-ns = <300>; - }; - opp-733334000 { - opp-hz = /bits/ 64 <733334000>; - clock-latency-ns = <300>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - clock-latency-ns = <300>; - }; - opp-1100000000 { - opp-hz = /bits/ 64 <1100000000>; - clock-latency-ns = <300>; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - clocks { - refclk: ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 4>, - <1 14 4>, - <1 11 4>, - <1 10 4>; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; /* 250ms */ - polling-delay = <1000>; /* 1000ms */ - thermal-sensors = <&pvtctl>; - - trips { - cpu_crit: cpu-crit { - temperature = <110000>; /* 110C */ - hysteresis = <2000>; - type = "critical"; - }; - cpu_alert: cpu-alert { - temperature = <100000>; /* 100C */ - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure-memory@81000000 { - reg = <0x0 0x81000000 0x0 0x01000000>; - no-map; - }; - }; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - - spi0: spi@54006000 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 39 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - spi1: spi@54006100 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006100 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 216 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&peri_clk 12>; - resets = <&peri_rst 12>; - }; - - spi2: spi@54006200 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006200 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 229 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2>; - clocks = <&peri_clk 13>; - resets = <&peri_rst 13>; - }; - - spi3: spi@54006300 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006300 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 230 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi3>; - clocks = <&peri_clk 14>; - resets = <&peri_rst 14>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&peri_clk 0>; - resets = <&peri_rst 0>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&peri_clk 1>; - resets = <&peri_rst 1>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&peri_clk 2>; - resets = <&peri_rst 2>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = <0 177 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&peri_clk 3>; - resets = <&peri_rst 3>; - }; - - gpio: gpio@55000000 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000000 0x200>; - interrupt-parent = <&aidet>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 0>, - <&pinctrl 96 0 0>, - <&pinctrl 160 0 0>; - gpio-ranges-group-names = "gpio_range0", - "gpio_range1", - "gpio_range2"; - ngpios = <205>; - socionext,interrupt-ranges = <0 48 16>, <16 154 5>, - <21 217 3>; - }; - - audio@56000000 { - compatible = "socionext,uniphier-ld20-aio"; - reg = <0x56000000 0x80000>; - interrupts = <0 144 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aout1>, - <&pinctrl_aoutiec1>; - clock-names = "aio"; - clocks = <&sys_clk 40>; - reset-names = "aio"; - resets = <&sys_rst 40>; - #sound-dai-cells = <1>; - socionext,syscon = <&soc_glue>; - - i2s_port0: port@0 { - i2s_hdmi: endpoint { - }; - }; - - i2s_port1: port@1 { - i2s_pcmin2: endpoint { - }; - }; - - i2s_port2: port@2 { - i2s_line: endpoint { - dai-format = "i2s"; - remote-endpoint = <&evea_line>; - }; - }; - - i2s_port3: port@3 { - i2s_hpcmout1: endpoint { - }; - }; - - i2s_port4: port@4 { - i2s_hp: endpoint { - dai-format = "i2s"; - remote-endpoint = <&evea_hp>; - }; - }; - - spdif_port0: port@5 { - spdif_hiecout1: endpoint { - }; - }; - - src_port0: port@6 { - i2s_epcmout2: endpoint { - }; - }; - - src_port1: port@7 { - i2s_epcmout3: endpoint { - }; - }; - - comp_spdif_port0: port@8 { - comp_spdif_hiecout1: endpoint { - }; - }; - }; - - codec@57900000 { - compatible = "socionext,uniphier-evea"; - reg = <0x57900000 0x1000>; - clock-names = "evea", "exiv"; - clocks = <&sys_clk 41>, <&sys_clk 42>; - reset-names = "evea", "exiv", "adamv"; - resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>; - #sound-dai-cells = <1>; - - port@0 { - evea_line: endpoint { - remote-endpoint = <&i2s_line>; - }; - }; - - port@1 { - evea_hp: endpoint { - remote-endpoint = <&i2s_hp>; - }; - }; - }; - - adamv@57920000 { - compatible = "socionext,uniphier-ld20-adamv", - "simple-mfd", "syscon"; - reg = <0x57920000 0x1000>; - - adamv_rst: reset { - compatible = "socionext,uniphier-ld20-adamv-reset"; - #reset-cells = <1>; - }; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - resets = <&peri_rst 4>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - resets = <&peri_rst 5>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - clocks = <&peri_clk 6>; - resets = <&peri_rst 6>; - clock-frequency = <400000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - resets = <&peri_rst 7>; - clock-frequency = <100000>; - }; - - i2c4: i2c@58784000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58784000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 45 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - clocks = <&peri_clk 8>; - resets = <&peri_rst 8>; - clock-frequency = <100000>; - }; - - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&peri_clk 9>; - resets = <&peri_rst 9>; - clock-frequency = <400000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_system_bus>; - }; - - smpctrl@59801000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - sdctrl@59810000 { - compatible = "socionext,uniphier-ld20-sdctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x400>; - - sd_clk: clock { - compatible = "socionext,uniphier-ld20-sd-clock"; - #clock-cells = <1>; - }; - - sd_rst: reset { - compatible = "socionext,uniphier-ld20-sd-reset"; - #reset-cells = <1>; - }; - }; - - perictrl@59820000 { - compatible = "socionext,uniphier-ld20-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - peri_clk: clock { - compatible = "socionext,uniphier-ld20-peri-clock"; - #clock-cells = <1>; - }; - - peri_rst: reset { - compatible = "socionext,uniphier-ld20-peri-reset"; - #reset-cells = <1>; - }; - }; - - emmc: mmc@5a000000 { - compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; - reg = <0x5a000000 0x400>; - interrupts = <0 78 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc>; - clocks = <&sys_clk 4>; - resets = <&sys_rst 4>; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-pwrseq = <&emmc_pwrseq>; - cdns,phy-input-delay-legacy = <9>; - cdns,phy-input-delay-mmc-highspeed = <2>; - cdns,phy-input-delay-mmc-ddr = <3>; - cdns,phy-dll-delay-sdclk = <21>; - cdns,phy-dll-delay-sdclk-hsmmc = <21>; - }; - - sd: mmc@5a400000 { - compatible = "socionext,uniphier-sd-v3.1.1"; - status = "disabled"; - reg = <0x5a400000 0x800>; - interrupts = <0 76 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd>; - clocks = <&sd_clk 0>; - reset-names = "host"; - resets = <&sd_rst 0>; - bus-width = <4>; - cap-sd-highspeed; - }; - - soc_glue: soc-glue@5f800000 { - compatible = "socionext,uniphier-ld20-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-ld20-pinctrl"; - }; - }; - - soc-glue@5f900000 { - compatible = "socionext,uniphier-ld20-soc-glue-debug", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5f900000 0x2000>; - - efuse@100 { - compatible = "socionext,uniphier-efuse"; - reg = <0x100 0x28>; - }; - - efuse@200 { - compatible = "socionext,uniphier-efuse"; - reg = <0x200 0x68>; - #address-cells = <1>; - #size-cells = <1>; - - /* USB cells */ - usb_rterm0: trim@54,4 { - reg = <0x54 1>; - bits = <4 2>; - }; - usb_rterm1: trim@55,4 { - reg = <0x55 1>; - bits = <4 2>; - }; - usb_rterm2: trim@58,4 { - reg = <0x58 1>; - bits = <4 2>; - }; - usb_rterm3: trim@59,4 { - reg = <0x59 1>; - bits = <4 2>; - }; - usb_sel_t0: trim@54,0 { - reg = <0x54 1>; - bits = <0 4>; - }; - usb_sel_t1: trim@55,0 { - reg = <0x55 1>; - bits = <0 4>; - }; - usb_sel_t2: trim@58,0 { - reg = <0x58 1>; - bits = <0 4>; - }; - usb_sel_t3: trim@59,0 { - reg = <0x59 1>; - bits = <0 4>; - }; - usb_hs_i0: trim@56,0 { - reg = <0x56 1>; - bits = <0 4>; - }; - usb_hs_i2: trim@5a,0 { - reg = <0x5a 1>; - bits = <0 4>; - }; - }; - }; - - xdmac: dma-controller@5fc10000 { - compatible = "socionext,uniphier-xdmac"; - reg = <0x5fc10000 0x5300>; - interrupts = <0 188 4>; - dma-channels = <16>; - #dma-cells = <2>; - }; - - aidet: interrupt-controller@5fc20000 { - compatible = "socionext,uniphier-ld20-aidet"; - reg = <0x5fc20000 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gic: interrupt-controller@5fe00000 { - compatible = "arm,gic-v3"; - reg = <0x5fe00000 0x10000>, /* GICD */ - <0x5fe80000 0x80000>; /* GICR */ - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <1 9 4>; - }; - - sysctrl@61840000 { - compatible = "socionext,uniphier-ld20-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x10000>; - - sys_clk: clock { - compatible = "socionext,uniphier-ld20-clock"; - #clock-cells = <1>; - }; - - sys_rst: reset { - compatible = "socionext,uniphier-ld20-reset"; - #reset-cells = <1>; - }; - - watchdog { - compatible = "socionext,uniphier-wdt"; - }; - - pvtctl: pvtctl { - compatible = "socionext,uniphier-ld20-thermal"; - interrupts = <0 3 4>; - #thermal-sensor-cells = <0>; - socionext,tmod-calibration = <0x0f22 0x68ee>; - }; - }; - - eth: ethernet@65000000 { - compatible = "socionext,uniphier-ld20-ave4"; - status = "disabled"; - reg = <0x65000000 0x8500>; - interrupts = <0 66 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ether_rgmii>; - clock-names = "ether"; - clocks = <&sys_clk 6>; - reset-names = "ether"; - resets = <&sys_rst 6>; - phy-mode = "rgmii-id"; - local-mac-address = [00 00 00 00 00 00]; - socionext,syscon-phy-mode = <&soc_glue 0>; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - usb: usb@65a00000 { - compatible = "socionext,uniphier-dwc3", "snps,dwc3"; - status = "disabled"; - reg = <0x65a00000 0xcd00>; - interrupt-names = "host"; - interrupts = <0 134 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>, - <&pinctrl_usb2>, <&pinctrl_usb3>; - clock-names = "ref", "bus_early", "suspend"; - clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>; - resets = <&usb_rst 15>; - phys = <&usb_hsphy0>, <&usb_hsphy1>, - <&usb_hsphy2>, <&usb_hsphy3>, - <&usb_ssphy0>, <&usb_ssphy1>; - dr_mode = "host"; - }; - - usb-glue@65b00000 { - compatible = "socionext,uniphier-ld20-dwc3-glue", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65b00000 0x400>; - - usb_rst: reset@0 { - compatible = "socionext,uniphier-ld20-usb3-reset"; - reg = <0x0 0x4>; - #reset-cells = <1>; - clock-names = "link"; - clocks = <&sys_clk 14>; - reset-names = "link"; - resets = <&sys_rst 14>; - }; - - usb_vbus0: regulator@100 { - compatible = "socionext,uniphier-ld20-usb3-regulator"; - reg = <0x100 0x10>; - clock-names = "link"; - clocks = <&sys_clk 14>; - reset-names = "link"; - resets = <&sys_rst 14>; - }; - - usb_vbus1: regulator@110 { - compatible = "socionext,uniphier-ld20-usb3-regulator"; - reg = <0x110 0x10>; - clock-names = "link"; - clocks = <&sys_clk 14>; - reset-names = "link"; - resets = <&sys_rst 14>; - }; - - usb_vbus2: regulator@120 { - compatible = "socionext,uniphier-ld20-usb3-regulator"; - reg = <0x120 0x10>; - clock-names = "link"; - clocks = <&sys_clk 14>; - reset-names = "link"; - resets = <&sys_rst 14>; - }; - - usb_vbus3: regulator@130 { - compatible = "socionext,uniphier-ld20-usb3-regulator"; - reg = <0x130 0x10>; - clock-names = "link"; - clocks = <&sys_clk 14>; - reset-names = "link"; - resets = <&sys_rst 14>; - }; - - usb_hsphy0: hs-phy@200 { - compatible = "socionext,uniphier-ld20-usb3-hsphy"; - reg = <0x200 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 16>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 16>; - vbus-supply = <&usb_vbus0>; - nvmem-cell-names = "rterm", "sel_t", "hs_i"; - nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, - <&usb_hs_i0>; - }; - - usb_hsphy1: hs-phy@210 { - compatible = "socionext,uniphier-ld20-usb3-hsphy"; - reg = <0x210 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 16>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 16>; - vbus-supply = <&usb_vbus1>; - nvmem-cell-names = "rterm", "sel_t", "hs_i"; - nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, - <&usb_hs_i0>; - }; - - usb_hsphy2: hs-phy@220 { - compatible = "socionext,uniphier-ld20-usb3-hsphy"; - reg = <0x220 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 17>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 17>; - vbus-supply = <&usb_vbus2>; - nvmem-cell-names = "rterm", "sel_t", "hs_i"; - nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, - <&usb_hs_i2>; - }; - - usb_hsphy3: hs-phy@230 { - compatible = "socionext,uniphier-ld20-usb3-hsphy"; - reg = <0x230 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 17>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 17>; - vbus-supply = <&usb_vbus3>; - nvmem-cell-names = "rterm", "sel_t", "hs_i"; - nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, - <&usb_hs_i2>; - }; - - usb_ssphy0: ss-phy@300 { - compatible = "socionext,uniphier-ld20-usb3-ssphy"; - reg = <0x300 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 18>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 18>; - vbus-supply = <&usb_vbus0>; - }; - - usb_ssphy1: ss-phy@310 { - compatible = "socionext,uniphier-ld20-usb3-ssphy"; - reg = <0x310 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 19>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 19>; - vbus-supply = <&usb_vbus1>; - }; - }; - - pcie: pcie@66000000 { - compatible = "socionext,uniphier-pcie", "snps,dw-pcie"; - status = "disabled"; - reg-names = "dbi", "link", "config"; - reg = <0x66000000 0x1000>, <0x66010000 0x10000>, - <0x2fff0000 0x10000>; - #address-cells = <3>; - #size-cells = <2>; - clocks = <&sys_clk 24>; - resets = <&sys_rst 24>; - num-lanes = <1>; - num-viewport = <1>; - bus-range = <0x0 0xff>; - device_type = "pci"; - ranges = - /* downstream I/O */ - <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>, - /* non-prefetchable memory */ - <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>; - #interrupt-cells = <1>; - interrupt-names = "dma", "msi"; - interrupts = <0 224 4>, <0 225 4>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ - <0 0 0 2 &pcie_intc 1>, /* INTB */ - <0 0 0 3 &pcie_intc 2>, /* INTC */ - <0 0 0 4 &pcie_intc 3>; /* INTD */ - phy-names = "pcie-phy"; - phys = <&pcie_phy>; - - pcie_intc: legacy-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = <0 226 4>; - }; - }; - - pcie_phy: phy@66038000 { - compatible = "socionext,uniphier-ld20-pcie-phy"; - reg = <0x66038000 0x4000>; - #phy-cells = <0>; - clock-names = "link"; - clocks = <&sys_clk 24>; - reset-names = "link"; - resets = <&sys_rst 24>; - socionext,syscon = <&soc_glue>; - }; - - nand: nand-controller@68000000 { - compatible = "socionext,uniphier-denali-nand-v5b"; - status = "disabled"; - reg-names = "nand_data", "denali_reg"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 65 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - clock-names = "nand", "nand_x", "ecc"; - clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; - reset-names = "nand", "reg"; - resets = <&sys_rst 2>, <&sys_rst 2>; - }; - }; -}; - -#include "uniphier-pinctrl.dtsi" - -&pinctrl_aout1 { - drive-strength = <4>; /* default: 3.5mA */ - - ao1dacck { - pins = "AO1DACCK"; - drive-strength = <5>; /* 5mA */ - }; -}; - -&pinctrl_aoutiec1 { - drive-strength = <4>; /* default: 3.5mA */ - - ao1arc { - pins = "AO1ARC"; - drive-strength = <11>; /* 11mA */ - }; -}; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi deleted file mode 100644 index 9caabbb8b..000000000 --- a/arch/arm64/boot/dts/socionext/uniphier-pinctrl.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts deleted file mode 100644 index 086040306..000000000 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts +++ /dev/null @@ -1,154 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier PXs3 Reference Board -// -// Copyright (C) 2017 Socionext Inc. -// Author: Masahiro Yamada - -/dts-v1/; -#include "uniphier-pxs3.dtsi" -#include "uniphier-support-card.dtsi" - -/ { - model = "UniPhier PXs3 Reference Board"; - compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serialsc; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c6 = &i2c6; - spi0 = &spi0; - spi1 = &spi1; - ethernet0 = ð0; - ethernet1 = ð1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0xa0000000>; - }; -}; - -ðsc { - interrupts = <4 8>; -}; - -&serialsc { - interrupts = <4 8>; -}; - -&spi0 { - status = "okay"; -}; - -&spi1 { - status = "okay"; -}; - -&serial0 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&gpio { - xirq4 { - gpio-hog; - gpios = ; - input; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&sd { - status = "okay"; -}; - -ð0 { - status = "okay"; - phy-handle = <ðphy0>; -}; - -&mdio0 { - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -ð1 { - status = "okay"; - phy-handle = <ðphy1>; -}; - -&mdio1 { - ethphy1: ethernet-phy@0 { - reg = <0>; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&nand { - status = "okay"; - - nand@0 { - reg = <0>; - }; -}; - -&pinctrl_ether_rgmii { - tx { - pins = "RGMII0_TXCLK", "RGMII0_TXD0", "RGMII0_TXD1", - "RGMII0_TXD2", "RGMII0_TXD3", "RGMII0_TXCTL"; - drive-strength = <9>; - }; -}; - -&pinctrl_ether1_rgmii { - tx { - pins = "RGMII1_TXCLK", "RGMII1_TXD0", "RGMII1_TXD1", - "RGMII1_TXD2", "RGMII1_TXD3", "RGMII1_TXCTL"; - drive-strength = <9>; - }; -}; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi deleted file mode 100644 index be97da132..000000000 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ /dev/null @@ -1,861 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -// -// Device Tree Source for UniPhier PXs3 SoC -// -// Copyright (C) 2017 Socionext Inc. -// Author: Masahiro Yamada - -#include -#include -#include - -/ { - compatible = "socionext,uniphier-pxs3"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 0x000>; - clocks = <&sys_clk 33>; - enable-method = "psci"; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 0x001>; - clocks = <&sys_clk 33>; - enable-method = "psci"; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 0x002>; - clocks = <&sys_clk 33>; - enable-method = "psci"; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 0x003>; - clocks = <&sys_clk 33>; - enable-method = "psci"; - operating-points-v2 = <&cluster0_opp>; - #cooling-cells = <2>; - }; - }; - - cluster0_opp: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - clock-latency-ns = <300>; - }; - opp-325000000 { - opp-hz = /bits/ 64 <325000000>; - clock-latency-ns = <300>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - clock-latency-ns = <300>; - }; - opp-650000000 { - opp-hz = /bits/ 64 <650000000>; - clock-latency-ns = <300>; - }; - opp-666667000 { - opp-hz = /bits/ 64 <666667000>; - clock-latency-ns = <300>; - }; - opp-866667000 { - opp-hz = /bits/ 64 <866667000>; - clock-latency-ns = <300>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - clock-latency-ns = <300>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - clock-latency-ns = <300>; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - clocks { - refclk: ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 4>, - <1 14 4>, - <1 11 4>, - <1 10 4>; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; /* 250ms */ - polling-delay = <1000>; /* 1000ms */ - thermal-sensors = <&pvtctl>; - - trips { - cpu_crit: cpu-crit { - temperature = <110000>; /* 110C */ - hysteresis = <2000>; - type = "critical"; - }; - cpu_alert: cpu-alert { - temperature = <100000>; /* 100C */ - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure-memory@81000000 { - reg = <0x0 0x81000000 0x0 0x01000000>; - no-map; - }; - }; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - - spi0: spi@54006000 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 39 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; - }; - - spi1: spi@54006100 { - compatible = "socionext,uniphier-scssi"; - status = "disabled"; - reg = <0x54006100 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 216 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; - clocks = <&peri_clk 12>; - resets = <&peri_rst 12>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - clocks = <&peri_clk 0>; - resets = <&peri_rst 0>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&peri_clk 1>; - resets = <&peri_rst 1>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - clocks = <&peri_clk 2>; - resets = <&peri_rst 2>; - }; - - serial3: serial@54006b00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006b00 0x40>; - interrupts = <0 177 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - clocks = <&peri_clk 3>; - resets = <&peri_rst 3>; - }; - - gpio: gpio@55000000 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000000 0x200>; - interrupt-parent = <&aidet>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 0>, - <&pinctrl 104 0 0>, - <&pinctrl 168 0 0>; - gpio-ranges-group-names = "gpio_range0", - "gpio_range1", - "gpio_range2"; - ngpios = <286>; - socionext,interrupt-ranges = <0 48 16>, <16 154 5>, - <21 217 3>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&peri_clk 4>; - resets = <&peri_rst 4>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&peri_clk 5>; - resets = <&peri_rst 5>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&peri_clk 6>; - resets = <&peri_rst 6>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&peri_clk 7>; - resets = <&peri_rst 7>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&peri_clk 10>; - resets = <&peri_rst 10>; - clock-frequency = <400000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_system_bus>; - }; - - smpctrl@59801000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - sdctrl@59810000 { - compatible = "socionext,uniphier-pxs3-sdctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x400>; - - sd_clk: clock { - compatible = "socionext,uniphier-pxs3-sd-clock"; - #clock-cells = <1>; - }; - - sd_rst: reset { - compatible = "socionext,uniphier-pxs3-sd-reset"; - #reset-cells = <1>; - }; - }; - - perictrl@59820000 { - compatible = "socionext,uniphier-pxs3-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - peri_clk: clock { - compatible = "socionext,uniphier-pxs3-peri-clock"; - #clock-cells = <1>; - }; - - peri_rst: reset { - compatible = "socionext,uniphier-pxs3-peri-reset"; - #reset-cells = <1>; - }; - }; - - emmc: mmc@5a000000 { - compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; - reg = <0x5a000000 0x400>; - interrupts = <0 78 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emmc>; - clocks = <&sys_clk 4>; - resets = <&sys_rst 4>; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-pwrseq = <&emmc_pwrseq>; - cdns,phy-input-delay-legacy = <9>; - cdns,phy-input-delay-mmc-highspeed = <2>; - cdns,phy-input-delay-mmc-ddr = <3>; - cdns,phy-dll-delay-sdclk = <21>; - cdns,phy-dll-delay-sdclk-hsmmc = <21>; - }; - - sd: mmc@5a400000 { - compatible = "socionext,uniphier-sd-v3.1.1"; - status = "disabled"; - reg = <0x5a400000 0x800>; - interrupts = <0 76 4>; - pinctrl-names = "default", "uhs"; - pinctrl-0 = <&pinctrl_sd>; - pinctrl-1 = <&pinctrl_sd_uhs>; - clocks = <&sd_clk 0>; - reset-names = "host"; - resets = <&sd_rst 0>; - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - }; - - soc_glue: soc-glue@5f800000 { - compatible = "socionext,uniphier-pxs3-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-pxs3-pinctrl"; - }; - }; - - soc-glue@5f900000 { - compatible = "socionext,uniphier-pxs3-soc-glue-debug", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5f900000 0x2000>; - - efuse@100 { - compatible = "socionext,uniphier-efuse"; - reg = <0x100 0x28>; - }; - - efuse@200 { - compatible = "socionext,uniphier-efuse"; - reg = <0x200 0x68>; - #address-cells = <1>; - #size-cells = <1>; - - /* USB cells */ - usb_rterm0: trim@54,4 { - reg = <0x54 1>; - bits = <4 2>; - }; - usb_rterm1: trim@55,4 { - reg = <0x55 1>; - bits = <4 2>; - }; - usb_rterm2: trim@58,4 { - reg = <0x58 1>; - bits = <4 2>; - }; - usb_rterm3: trim@59,4 { - reg = <0x59 1>; - bits = <4 2>; - }; - usb_sel_t0: trim@54,0 { - reg = <0x54 1>; - bits = <0 4>; - }; - usb_sel_t1: trim@55,0 { - reg = <0x55 1>; - bits = <0 4>; - }; - usb_sel_t2: trim@58,0 { - reg = <0x58 1>; - bits = <0 4>; - }; - usb_sel_t3: trim@59,0 { - reg = <0x59 1>; - bits = <0 4>; - }; - usb_hs_i0: trim@56,0 { - reg = <0x56 1>; - bits = <0 4>; - }; - usb_hs_i2: trim@5a,0 { - reg = <0x5a 1>; - bits = <0 4>; - }; - }; - }; - - xdmac: dma-controller@5fc10000 { - compatible = "socionext,uniphier-xdmac"; - reg = <0x5fc10000 0x5300>; - interrupts = <0 188 4>; - dma-channels = <16>; - #dma-cells = <2>; - }; - - aidet: interrupt-controller@5fc20000 { - compatible = "socionext,uniphier-pxs3-aidet"; - reg = <0x5fc20000 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gic: interrupt-controller@5fe00000 { - compatible = "arm,gic-v3"; - reg = <0x5fe00000 0x10000>, /* GICD */ - <0x5fe80000 0x80000>; /* GICR */ - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <1 9 4>; - }; - - sysctrl@61840000 { - compatible = "socionext,uniphier-pxs3-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x10000>; - - sys_clk: clock { - compatible = "socionext,uniphier-pxs3-clock"; - #clock-cells = <1>; - }; - - sys_rst: reset { - compatible = "socionext,uniphier-pxs3-reset"; - #reset-cells = <1>; - }; - - watchdog { - compatible = "socionext,uniphier-wdt"; - }; - - pvtctl: pvtctl { - compatible = "socionext,uniphier-pxs3-thermal"; - interrupts = <0 3 4>; - #thermal-sensor-cells = <0>; - socionext,tmod-calibration = <0x0f22 0x68ee>; - }; - }; - - eth0: ethernet@65000000 { - compatible = "socionext,uniphier-pxs3-ave4"; - status = "disabled"; - reg = <0x65000000 0x8500>; - interrupts = <0 66 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ether_rgmii>; - clock-names = "ether"; - clocks = <&sys_clk 6>; - reset-names = "ether"; - resets = <&sys_rst 6>; - phy-mode = "rgmii-id"; - local-mac-address = [00 00 00 00 00 00]; - socionext,syscon-phy-mode = <&soc_glue 0>; - - mdio0: mdio { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - eth1: ethernet@65200000 { - compatible = "socionext,uniphier-pxs3-ave4"; - status = "disabled"; - reg = <0x65200000 0x8500>; - interrupts = <0 67 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ether1_rgmii>; - clock-names = "ether"; - clocks = <&sys_clk 7>; - reset-names = "ether"; - resets = <&sys_rst 7>; - phy-mode = "rgmii-id"; - local-mac-address = [00 00 00 00 00 00]; - socionext,syscon-phy-mode = <&soc_glue 1>; - - mdio1: mdio { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - usb0: usb@65a00000 { - compatible = "socionext,uniphier-dwc3", "snps,dwc3"; - status = "disabled"; - reg = <0x65a00000 0xcd00>; - interrupt-names = "host", "peripheral"; - interrupts = <0 134 4>, <0 135 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; - clock-names = "ref", "bus_early", "suspend"; - clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; - resets = <&usb0_rst 15>; - phys = <&usb0_hsphy0>, <&usb0_hsphy1>, - <&usb0_ssphy0>, <&usb0_ssphy1>; - dr_mode = "host"; - }; - - usb-glue@65b00000 { - compatible = "socionext,uniphier-pxs3-dwc3-glue", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65b00000 0x400>; - - usb0_rst: reset@0 { - compatible = "socionext,uniphier-pxs3-usb3-reset"; - reg = <0x0 0x4>; - #reset-cells = <1>; - clock-names = "link"; - clocks = <&sys_clk 12>; - reset-names = "link"; - resets = <&sys_rst 12>; - }; - - usb0_vbus0: regulator@100 { - compatible = "socionext,uniphier-pxs3-usb3-regulator"; - reg = <0x100 0x10>; - clock-names = "link"; - clocks = <&sys_clk 12>; - reset-names = "link"; - resets = <&sys_rst 12>; - }; - - usb0_vbus1: regulator@110 { - compatible = "socionext,uniphier-pxs3-usb3-regulator"; - reg = <0x110 0x10>; - clock-names = "link"; - clocks = <&sys_clk 12>; - reset-names = "link"; - resets = <&sys_rst 12>; - }; - - usb0_hsphy0: hs-phy@200 { - compatible = "socionext,uniphier-pxs3-usb3-hsphy"; - reg = <0x200 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 12>, <&sys_clk 16>; - reset-names = "link", "phy"; - resets = <&sys_rst 12>, <&sys_rst 16>; - vbus-supply = <&usb0_vbus0>; - nvmem-cell-names = "rterm", "sel_t", "hs_i"; - nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, - <&usb_hs_i0>; - }; - - usb0_hsphy1: hs-phy@210 { - compatible = "socionext,uniphier-pxs3-usb3-hsphy"; - reg = <0x210 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 12>, <&sys_clk 16>; - reset-names = "link", "phy"; - resets = <&sys_rst 12>, <&sys_rst 16>; - vbus-supply = <&usb0_vbus1>; - nvmem-cell-names = "rterm", "sel_t", "hs_i"; - nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, - <&usb_hs_i0>; - }; - - usb0_ssphy0: ss-phy@300 { - compatible = "socionext,uniphier-pxs3-usb3-ssphy"; - reg = <0x300 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 12>, <&sys_clk 17>; - reset-names = "link", "phy"; - resets = <&sys_rst 12>, <&sys_rst 17>; - vbus-supply = <&usb0_vbus0>; - }; - - usb0_ssphy1: ss-phy@310 { - compatible = "socionext,uniphier-pxs3-usb3-ssphy"; - reg = <0x310 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 12>, <&sys_clk 18>; - reset-names = "link", "phy"; - resets = <&sys_rst 12>, <&sys_rst 18>; - vbus-supply = <&usb0_vbus1>; - }; - }; - - usb1: usb@65c00000 { - compatible = "socionext,uniphier-dwc3", "snps,dwc3"; - status = "disabled"; - reg = <0x65c00000 0xcd00>; - interrupt-names = "host", "peripheral"; - interrupts = <0 137 4>, <0 138 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; - clock-names = "ref", "bus_early", "suspend"; - clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>; - resets = <&usb1_rst 15>; - phys = <&usb1_hsphy0>, <&usb1_hsphy1>, - <&usb1_ssphy0>; - dr_mode = "host"; - }; - - usb-glue@65d00000 { - compatible = "socionext,uniphier-pxs3-dwc3-glue", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65d00000 0x400>; - - usb1_rst: reset@0 { - compatible = "socionext,uniphier-pxs3-usb3-reset"; - reg = <0x0 0x4>; - #reset-cells = <1>; - clock-names = "link"; - clocks = <&sys_clk 13>; - reset-names = "link"; - resets = <&sys_rst 13>; - }; - - usb1_vbus0: regulator@100 { - compatible = "socionext,uniphier-pxs3-usb3-regulator"; - reg = <0x100 0x10>; - clock-names = "link"; - clocks = <&sys_clk 13>; - reset-names = "link"; - resets = <&sys_rst 13>; - }; - - usb1_vbus1: regulator@110 { - compatible = "socionext,uniphier-pxs3-usb3-regulator"; - reg = <0x110 0x10>; - clock-names = "link"; - clocks = <&sys_clk 13>; - reset-names = "link"; - resets = <&sys_rst 13>; - }; - - usb1_hsphy0: hs-phy@200 { - compatible = "socionext,uniphier-pxs3-usb3-hsphy"; - reg = <0x200 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy", "phy-ext"; - clocks = <&sys_clk 13>, <&sys_clk 20>, - <&sys_clk 14>; - reset-names = "link", "phy"; - resets = <&sys_rst 13>, <&sys_rst 20>; - vbus-supply = <&usb1_vbus0>; - nvmem-cell-names = "rterm", "sel_t", "hs_i"; - nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, - <&usb_hs_i2>; - }; - - usb1_hsphy1: hs-phy@210 { - compatible = "socionext,uniphier-pxs3-usb3-hsphy"; - reg = <0x210 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy", "phy-ext"; - clocks = <&sys_clk 13>, <&sys_clk 20>, - <&sys_clk 14>; - reset-names = "link", "phy"; - resets = <&sys_rst 13>, <&sys_rst 20>; - vbus-supply = <&usb1_vbus1>; - nvmem-cell-names = "rterm", "sel_t", "hs_i"; - nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, - <&usb_hs_i2>; - }; - - usb1_ssphy0: ss-phy@300 { - compatible = "socionext,uniphier-pxs3-usb3-ssphy"; - reg = <0x300 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy", "phy-ext"; - clocks = <&sys_clk 13>, <&sys_clk 21>, - <&sys_clk 14>; - reset-names = "link", "phy"; - resets = <&sys_rst 13>, <&sys_rst 21>; - vbus-supply = <&usb1_vbus0>; - }; - }; - - pcie: pcie@66000000 { - compatible = "socionext,uniphier-pcie", "snps,dw-pcie"; - status = "disabled"; - reg-names = "dbi", "link", "config"; - reg = <0x66000000 0x1000>, <0x66010000 0x10000>, - <0x2fff0000 0x10000>; - #address-cells = <3>; - #size-cells = <2>; - clocks = <&sys_clk 24>; - resets = <&sys_rst 24>; - num-lanes = <1>; - num-viewport = <1>; - bus-range = <0x0 0xff>; - device_type = "pci"; - ranges = - /* downstream I/O */ - <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>, - /* non-prefetchable memory */ - <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>; - #interrupt-cells = <1>; - interrupt-names = "dma", "msi"; - interrupts = <0 224 4>, <0 225 4>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ - <0 0 0 2 &pcie_intc 1>, /* INTB */ - <0 0 0 3 &pcie_intc 2>, /* INTC */ - <0 0 0 4 &pcie_intc 3>; /* INTD */ - phy-names = "pcie-phy"; - phys = <&pcie_phy>; - - pcie_intc: legacy-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = <0 226 4>; - }; - }; - - pcie_phy: phy@66038000 { - compatible = "socionext,uniphier-pxs3-pcie-phy"; - reg = <0x66038000 0x4000>; - #phy-cells = <0>; - clock-names = "link"; - clocks = <&sys_clk 24>; - reset-names = "link"; - resets = <&sys_rst 24>; - socionext,syscon = <&soc_glue>; - }; - - nand: nand-controller@68000000 { - compatible = "socionext,uniphier-denali-nand-v5b"; - status = "disabled"; - reg-names = "nand_data", "denali_reg"; - reg = <0x68000000 0x20>, <0x68100000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 65 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - clock-names = "nand", "nand_x", "ecc"; - clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; - reset-names = "nand", "reg"; - resets = <&sys_rst 2>, <&sys_rst 2>; - }; - }; -}; - -#include "uniphier-pinctrl.dtsi" diff --git a/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi deleted file mode 100644 index e66d999d9..000000000 --- a/arch/arm64/boot/dts/socionext/uniphier-ref-daughter.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi b/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi deleted file mode 100644 index 28c5b4ed1..000000000 --- a/arch/arm64/boot/dts/socionext/uniphier-support-card.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/arm64/boot/dts/sprd/Makefile b/arch/arm64/boot/dts/sprd/Makefile deleted file mode 100644 index f4f1f5148..000000000 --- a/arch/arm64/boot/dts/sprd/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb \ - sp9860g-1h10.dtb \ - sp9863a-1h10.dtb diff --git a/arch/arm64/boot/dts/sprd/sc2731.dtsi b/arch/arm64/boot/dts/sprd/sc2731.dtsi deleted file mode 100644 index e15409f55..000000000 --- a/arch/arm64/boot/dts/sprd/sc2731.dtsi +++ /dev/null @@ -1,258 +0,0 @@ -/* - * Spreadtrum SC2731 PMIC dts file - * - * Copyright (C) 2018, Spreadtrum Communications Inc. - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -&adi_bus { - sc2731_pmic: pmic@0 { - compatible = "sprd,sc2731"; - reg = <0>; - spi-max-frequency = <26000000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - charger@0 { - compatible = "sprd,sc2731-charger"; - reg = <0x0>; - monitored-battery = <&bat>; - }; - - led-controller@200 { - compatible = "sprd,sc2731-bltc"; - reg = <0x200>; - #address-cells = <1>; - #size-cells = <0>; - - led@0 { - label = "red"; - reg = <0x0>; - }; - - led@1 { - label = "green"; - reg = <0x1>; - }; - - led@2 { - label = "blue"; - reg = <0x2>; - }; - }; - - rtc@280 { - compatible = "sprd,sc2731-rtc"; - reg = <0x280>; - interrupt-parent = <&sc2731_pmic>; - interrupts = <2>; - }; - - pmic_eic: gpio@300 { - compatible = "sprd,sc2731-eic"; - reg = <0x300>; - interrupt-parent = <&sc2731_pmic>; - interrupts = <5>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - efuse@380 { - compatible = "sprd,sc2731-efuse"; - reg = <0x380>; - #address-cells = <1>; - #size-cells = <1>; - hwlocks = <&hwlock 12>; - - fgu_calib: calib@6 { - reg = <0x6 0x2>; - bits = <0 9>; - }; - - adc_big_scale: calib@24 { - reg = <0x24 0x2>; - }; - - adc_small_scale: calib@26 { - reg = <0x26 0x2>; - }; - }; - - pmic_adc: adc@480 { - compatible = "sprd,sc2731-adc"; - reg = <0x480>; - interrupt-parent = <&sc2731_pmic>; - interrupts = <0>; - #io-channel-cells = <1>; - hwlocks = <&hwlock 4>; - nvmem-cell-names = "big_scale_calib", "small_scale_calib"; - nvmem-cells = <&adc_big_scale>, <&adc_small_scale>; - }; - - fgu@a00 { - compatible = "sprd,sc2731-fgu"; - reg = <0xa00>; - bat-detect-gpio = <&pmic_eic 9 GPIO_ACTIVE_HIGH>; - io-channels = <&pmic_adc 3>, <&pmic_adc 6>; - io-channel-names = "bat-temp", "charge-vol"; - monitored-battery = <&bat>; - nvmem-cell-names = "fgu_calib"; - nvmem-cells = <&fgu_calib>; - interrupt-parent = <&sc2731_pmic>; - interrupts = <4>; - }; - - vibrator@ec8 { - compatible = "sprd,sc2731-vibrator"; - reg = <0xec8>; - }; - - regulators { - compatible = "sprd,sc2731-regulator"; - - vddarm0: BUCK_CPU0 { - regulator-name = "vddarm0"; - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1996875>; - regulator-ramp-delay = <25000>; - regulator-always-on; - }; - - vddarm1: BUCK_CPU1 { - regulator-name = "vddarm1"; - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1996875>; - regulator-ramp-delay = <25000>; - regulator-always-on; - }; - - dcdcrf: BUCK_RF { - regulator-name = "dcdcrf"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2196875>; - regulator-ramp-delay = <25000>; - regulator-enable-ramp-delay = <100>; - regulator-always-on; - }; - - vddcama0: LDO_CAMA0 { - regulator-name = "vddcama0"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3750000>; - regulator-enable-ramp-delay = <100>; - }; - - vddcama1: LDO_CAMA1 { - regulator-name = "vddcama1"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3750000>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - }; - - vddcammot: LDO_CAMMOT { - regulator-name = "vddcammot"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3750000>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - }; - - vddvldo: LDO_VLDO { - regulator-name = "vddvldo"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3750000>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - }; - - vddemmccore: LDO_EMMCCORE { - regulator-name = "vddemmccore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3750000>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - regulator-boot-on; - }; - - vddsdcore: LDO_SDCORE { - regulator-name = "vddsdcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3750000>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - }; - - vddsdio: LDO_SDIO { - regulator-name = "vddsdio"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3750000>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - }; - - vddwifipa: LDO_WIFIPA { - regulator-name = "vddwifipa"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3750000>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - }; - - vddusb33: LDO_USB33 { - regulator-name = "vddusb33"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3750000>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - }; - - vddcamd0: LDO_CAMD0 { - regulator-name = "vddcamd0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1793750>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - }; - - vddcamd1: LDO_CAMD1 { - regulator-name = "vddcamd1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1793750>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - }; - - vddcon: LDO_CON { - regulator-name = "vddcon"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1793750>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - }; - - vddcamio: LDO_CAMIO { - regulator-name = "vddcamio"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1793750>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - }; - - vddsram: LDO_SRAM { - regulator-name = "vddsram"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1793750>; - regulator-enable-ramp-delay = <100>; - regulator-ramp-delay = <25000>; - regulator-always-on; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/sprd/sc9836-openphone.dts b/arch/arm64/boot/dts/sprd/sc9836-openphone.dts deleted file mode 100644 index e5657c35c..000000000 --- a/arch/arm64/boot/dts/sprd/sc9836-openphone.dts +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Spreadtrum SC9836 openphone board DTS file - * - * Copyright (C) 2014, Spreadtrum Communications Inc. - * - * This file is licensed under a dual GPLv2 or X11 license. - */ - -/dts-v1/; - -#include "sc9836.dtsi" - -/ { - model = "Spreadtrum SC9836 Openphone Board"; - - compatible = "sprd,sc9836-openphone", "sprd,sc9836"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0 0x80000000 0 0x20000000>; - }; - - chosen { - stdout-path = "serial1:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/sprd/sc9836.dtsi b/arch/arm64/boot/dts/sprd/sc9836.dtsi deleted file mode 100644 index 231436be0..000000000 --- a/arch/arm64/boot/dts/sprd/sc9836.dtsi +++ /dev/null @@ -1,224 +0,0 @@ -/* - * Spreadtrum SC9836 SoC DTS file - * - * Copyright (C) 2014, Spreadtrum Communications Inc. - * - * This file is licensed under a dual GPLv2 or X11 license. - */ - -#include "sharkl64.dtsi" -#include - -/ { - compatible = "sprd,sc9836"; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - etf@10003000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x10003000 0 0x1000>; - clocks = <&clk26mhz>; - clock-names = "apb_pclk"; - in-ports { - port { - etf_in: endpoint { - remote-endpoint = <&funnel_out_port0>; - }; - }; - }; - }; - - funnel@10001000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x10001000 0 0x1000>; - clocks = <&clk26mhz>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel_out_port0: endpoint { - remote-endpoint = <&etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_in_port0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - funnel_in_port1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - - port@2 { - reg = <2>; - funnel_in_port2: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - - port@3 { - reg = <3>; - funnel_in_port3: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - - port@4 { - reg = <4>; - funnel_in_port4: endpoint { - remote-endpoint = <&stm_out>; - }; - }; - /* Other input ports aren't connected to anyone */ - }; - }; - - etm@10440000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x10440000 0 0x1000>; - - cpu = <&cpu0>; - clocks = <&clk26mhz>; - clock-names = "apb_pclk"; - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = <&funnel_in_port0>; - }; - }; - }; - }; - - etm@10540000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x10540000 0 0x1000>; - - cpu = <&cpu1>; - clocks = <&clk26mhz>; - clock-names = "apb_pclk"; - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = <&funnel_in_port1>; - }; - }; - }; - }; - - etm@10640000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x10640000 0 0x1000>; - - cpu = <&cpu2>; - clocks = <&clk26mhz>; - clock-names = "apb_pclk"; - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = <&funnel_in_port2>; - }; - }; - }; - }; - - etm@10740000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x10740000 0 0x1000>; - - cpu = <&cpu3>; - clocks = <&clk26mhz>; - clock-names = "apb_pclk"; - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = <&funnel_in_port3>; - }; - }; - }; - }; - - stm@10006000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0 0x10006000 0 0x1000>, - <0 0x01000000 0 0x180000>; - reg-names = "stm-base", "stm-stimulus-base"; - clocks = <&clk26mhz>; - clock-names = "apb_pclk"; - out-ports { - port { - stm_out: endpoint { - remote-endpoint = <&funnel_in_port4>; - }; - }; - }; - }; - - gic: interrupt-controller@12001000 { - compatible = "arm,gic-400"; - reg = <0 0x12001000 0 0x1000>, - <0 0x12002000 0 0x2000>, - <0 0x12004000 0 0x2000>, - <0 0x12006000 0 0x2000>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - }; - - psci { - compatible = "arm,psci"; - method = "smc"; - cpu_on = <0xc4000003>; - cpu_off = <0x84000002>; - cpu_suspend = <0xc4000001>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; -}; diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi deleted file mode 100644 index e27eb3ed1..000000000 --- a/arch/arm64/boot/dts/sprd/sc9860.dtsi +++ /dev/null @@ -1,716 +0,0 @@ -/* - * Spreadtrum SC9860 SoC - * - * Copyright (C) 2016, Spreadtrum Communications Inc. - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -#include -#include -#include -#include "whale2.dtsi" - -/ { - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - core2 { - cpu = <&CPU2>; - }; - core3 { - cpu = <&CPU3>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU4>; - }; - core1 { - cpu = <&CPU5>; - }; - core2 { - cpu = <&CPU6>; - }; - core3 { - cpu = <&CPU7>; - }; - }; - }; - - CPU0: cpu@530000 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x530000>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD &CLUSTER_PD>; - }; - - CPU1: cpu@530001 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x530001>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD &CLUSTER_PD>; - }; - - CPU2: cpu@530002 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x530002>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD &CLUSTER_PD>; - }; - - CPU3: cpu@530003 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x530003>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD &CLUSTER_PD>; - }; - - CPU4: cpu@530100 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x530100>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD &CLUSTER_PD>; - }; - - CPU5: cpu@530101 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x530101>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD &CLUSTER_PD>; - }; - - CPU6: cpu@530102 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x530102>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD &CLUSTER_PD>; - }; - - CPU7: cpu@530103 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x530103>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD &CLUSTER_PD>; - }; - }; - - idle-states{ - entry-method = "psci"; - - CORE_PD: core_pd { - compatible = "arm,idle-state"; - entry-latency-us = <1000>; - exit-latency-us = <700>; - min-residency-us = <2500>; - local-timer-stop; - arm,psci-suspend-param = <0x00010002>; - }; - - CLUSTER_PD: cluster_pd { - compatible = "arm,idle-state"; - entry-latency-us = <1000>; - exit-latency-us = <1000>; - min-residency-us = <3000>; - local-timer-stop; - arm,psci-suspend-param = <0x01010003>; - }; - }; - - gic: interrupt-controller@12001000 { - compatible = "arm,gic-400"; - reg = <0 0x12001000 0 0x1000>, - <0 0x12002000 0 0x2000>, - <0 0x12004000 0 0x2000>, - <0 0x12006000 0 0x2000>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; - interrupts = , - , - , - , - , - , - , - ; - interrupt-affinity = <&CPU0>, - <&CPU1>, - <&CPU2>, - <&CPU3>, - <&CPU4>, - <&CPU5>, - <&CPU6>, - <&CPU7>; - }; - - soc { - pmu_gate: pmu-gate { - compatible = "sprd,sc9860-pmu-gate"; - sprd,syscon = <&pmu_regs>; /* 0x402b0000 */ - clocks = <&ext_26m>; - #clock-cells = <1>; - }; - - pll: pll { - compatible = "sprd,sc9860-pll"; - sprd,syscon = <&ana_regs>; /* 0x40400000 */ - clocks = <&pmu_gate 0>; - #clock-cells = <1>; - }; - - ap_clk: clock-controller@20000000 { - compatible = "sprd,sc9860-ap-clk"; - reg = <0 0x20000000 0 0x400>; - clocks = <&ext_26m>, <&pll 0>, - <&pmu_gate 0>; - #clock-cells = <1>; - }; - - aon_prediv: aon-prediv { - compatible = "sprd,sc9860-aon-prediv"; - reg = <0 0x402d0000 0 0x400>; - clocks = <&ext_26m>, <&pll 0>, - <&pmu_gate 0>; - #clock-cells = <1>; - }; - - apahb_gate: apahb-gate { - compatible = "sprd,sc9860-apahb-gate"; - sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */ - clocks = <&aon_prediv 0>; - #clock-cells = <1>; - }; - - aon_gate: aon-gate { - compatible = "sprd,sc9860-aon-gate"; - sprd,syscon = <&aon_regs>; /* 0x402e0000 */ - clocks = <&aon_prediv 0>; - #clock-cells = <1>; - }; - - aonsecure_clk: clock-controller@40880000 { - compatible = "sprd,sc9860-aonsecure-clk"; - reg = <0 0x40880000 0 0x400>; - clocks = <&ext_26m>, <&pll 0>; - #clock-cells = <1>; - }; - - agcp_gate: agcp-gate { - compatible = "sprd,sc9860-agcp-gate"; - sprd,syscon = <&agcp_regs>; /* 0x415e0000 */ - clocks = <&aon_prediv 0>; - #clock-cells = <1>; - }; - - gpu_clk: clock-controller@60200000 { - compatible = "sprd,sc9860-gpu-clk"; - reg = <0 0x60200000 0 0x400>; - clocks = <&pll 0>; - #clock-cells = <1>; - }; - - vsp_clk: clock-controller@61000000 { - compatible = "sprd,sc9860-vsp-clk"; - reg = <0 0x61000000 0 0x400>; - clocks = <&ext_26m>, <&pll 0>; - #clock-cells = <1>; - }; - - vsp_gate: vsp-gate { - compatible = "sprd,sc9860-vsp-gate"; - sprd,syscon = <&vsp_regs>; /* 0x61100000 */ - clocks = <&vsp_clk 0>; - #clock-cells = <1>; - }; - - cam_clk: clock-controller@62000000 { - compatible = "sprd,sc9860-cam-clk"; - reg = <0 0x62000000 0 0x4000>; - clocks = <&ext_26m>, <&pll 0>; - #clock-cells = <1>; - }; - - cam_gate: cam-gate { - compatible = "sprd,sc9860-cam-gate"; - sprd,syscon = <&cam_regs>; /* 0x62100000 */ - clocks = <&cam_clk 0>; - #clock-cells = <1>; - }; - - disp_clk: clock-controller@63000000 { - compatible = "sprd,sc9860-disp-clk"; - reg = <0 0x63000000 0 0x400>; - clocks = <&ext_26m>, <&pll 0>; - #clock-cells = <1>; - }; - - disp_gate: disp-gate { - compatible = "sprd,sc9860-disp-gate"; - sprd,syscon = <&disp_regs>; /* 0x63100000 */ - clocks = <&disp_clk 0>; - #clock-cells = <1>; - }; - - apapb_gate: apapb-gate { - compatible = "sprd,sc9860-apapb-gate"; - sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */ - clocks = <&ap_clk 0>; - #clock-cells = <1>; - }; - - funnel@10001000 { /* SoC Funnel */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x10001000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - out-ports { - port { - soc_funnel_out_port: endpoint { - remote-endpoint = <&etb_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - soc_funnel_in_port0: endpoint { - remote-endpoint = - <&main_funnel_out_port>; - }; - }; - - port@4 { - reg = <4>; - soc_funnel_in_port1: endpoint { - remote-endpoint = - <&stm_out_port>; - }; - }; - }; - }; - - etb@10003000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x10003000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - out-ports { - port { - etb_in: endpoint { - remote-endpoint = - <&soc_funnel_out_port>; - }; - }; - }; - }; - - stm@10006000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0 0x10006000 0 0x1000>, - <0 0x01000000 0 0x180000>; - reg-names = "stm-base", "stm-stimulus-base"; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - out-ports { - port { - stm_out_port: endpoint { - remote-endpoint = - <&soc_funnel_in_port1>; - }; - }; - }; - }; - - funnel@11001000 { /* Cluster0 Funnel */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x11001000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - out-ports { - port { - cluster0_funnel_out_port: endpoint { - remote-endpoint = - <&cluster0_etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - cluster0_funnel_in_port0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - cluster0_funnel_in_port1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - - port@2 { - reg = <2>; - cluster0_funnel_in_port2: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - - port@4 { - reg = <4>; - cluster0_funnel_in_port3: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - }; - }; - - funnel@11002000 { /* Cluster1 Funnel */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x11002000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - out-ports { - port { - cluster1_funnel_out_port: endpoint { - remote-endpoint = - <&cluster1_etf_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - cluster1_funnel_in_port0: endpoint { - remote-endpoint = <&etm4_out>; - }; - }; - - port@1 { - reg = <1>; - cluster1_funnel_in_port1: endpoint { - remote-endpoint = <&etm5_out>; - }; - }; - - port@2 { - reg = <2>; - cluster1_funnel_in_port2: endpoint { - remote-endpoint = <&etm6_out>; - }; - }; - - port@3 { - reg = <3>; - cluster1_funnel_in_port3: endpoint { - remote-endpoint = <&etm7_out>; - }; - }; - }; - }; - - etf@11003000 { /* ETF on Cluster0 */ - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x11003000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - cluster0_etf_out: endpoint { - remote-endpoint = - <&main_funnel_in_port0>; - }; - }; - }; - - in-ports { - port { - cluster0_etf_in: endpoint { - remote-endpoint = - <&cluster0_funnel_out_port>; - }; - }; - }; - }; - - etf@11004000 { /* ETF on Cluster1 */ - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x11004000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - cluster1_etf_out: endpoint { - remote-endpoint = - <&main_funnel_in_port1>; - }; - }; - }; - - in-ports { - port { - cluster1_etf_in: endpoint { - remote-endpoint = - <&cluster1_funnel_out_port>; - }; - }; - }; - }; - - funnel@11005000 { /* Main Funnel */ - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x11005000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - main_funnel_out_port: endpoint { - remote-endpoint = - <&soc_funnel_in_port0>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - main_funnel_in_port0: endpoint { - remote-endpoint = - <&cluster0_etf_out>; - }; - }; - - port@1 { - reg = <1>; - main_funnel_in_port1: endpoint { - remote-endpoint = - <&cluster1_etf_out>; - }; - }; - }; - }; - - etm@11440000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x11440000 0 0x1000>; - cpu = <&CPU0>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = - <&cluster0_funnel_in_port0>; - }; - }; - }; - }; - - etm@11540000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x11540000 0 0x1000>; - cpu = <&CPU1>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = - <&cluster0_funnel_in_port1>; - }; - }; - }; - }; - - etm@11640000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x11640000 0 0x1000>; - cpu = <&CPU2>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = - <&cluster0_funnel_in_port2>; - }; - }; - }; - }; - - etm@11740000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x11740000 0 0x1000>; - cpu = <&CPU3>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = - <&cluster0_funnel_in_port3>; - }; - }; - }; - }; - - etm@11840000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x11840000 0 0x1000>; - cpu = <&CPU4>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm4_out: endpoint { - remote-endpoint = - <&cluster1_funnel_in_port0>; - }; - }; - }; - }; - - etm@11940000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x11940000 0 0x1000>; - cpu = <&CPU5>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm5_out: endpoint { - remote-endpoint = - <&cluster1_funnel_in_port1>; - }; - }; - }; - }; - - etm@11a40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x11a40000 0 0x1000>; - cpu = <&CPU6>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm6_out: endpoint { - remote-endpoint = - <&cluster1_funnel_in_port2>; - }; - }; - }; - }; - - etm@11b40000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x11b40000 0 0x1000>; - cpu = <&CPU7>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm7_out: endpoint { - remote-endpoint = - <&cluster1_funnel_in_port3>; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-volumedown { - label = "Volume Down Key"; - linux,code = ; - gpios = <&eic_debounce 2 GPIO_ACTIVE_LOW>; - debounce-interval = <2>; - wakeup-source; - }; - - key-volumeup { - label = "Volume Up Key"; - linux,code = ; - gpios = <&pmic_eic 10 GPIO_ACTIVE_HIGH>; - debounce-interval = <2>; - wakeup-source; - }; - - key-power { - label = "Power Key"; - linux,code = ; - gpios = <&pmic_eic 1 GPIO_ACTIVE_HIGH>; - debounce-interval = <2>; - wakeup-source; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/sprd/sc9863a.dtsi b/arch/arm64/boot/dts/sprd/sc9863a.dtsi deleted file mode 100644 index 8cf4a6575..000000000 --- a/arch/arm64/boot/dts/sprd/sc9863a.dtsi +++ /dev/null @@ -1,589 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Unisoc SC9863A SoC DTS file - * - * Copyright (C) 2019, Unisoc Inc. - */ - -#include -#include -#include "sharkl3.dtsi" - -/ { - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - core1 { - cpu = <&CPU1>; - }; - core2 { - cpu = <&CPU2>; - }; - core3 { - cpu = <&CPU3>; - }; - core4 { - cpu = <&CPU4>; - }; - core5 { - cpu = <&CPU5>; - }; - core6 { - cpu = <&CPU6>; - }; - core7 { - cpu = <&CPU7>; - }; - }; - }; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x0>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD>; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x100>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD>; - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x200>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD>; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x300>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD>; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x400>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD>; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x500>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD>; - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x600>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD>; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x700>; - enable-method = "psci"; - cpu-idle-states = <&CORE_PD>; - }; - }; - - idle-states { - entry-method = "psci"; - CORE_PD: core-pd { - compatible = "arm,idle-state"; - entry-latency-us = <4000>; - exit-latency-us = <4000>; - min-residency-us = <10000>; - local-timer-stop; - arm,psci-suspend-param = <0x00010000>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , /* Physical Secure PPI */ - , /* Physical Non-Secure PPI */ - , /* Virtual PPI */ - ; /* Hipervisor PPI */ - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = , - , - , - , - , - , - , - ; - }; - - soc { - gic: interrupt-controller@14000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - redistributor-stride = <0x0 0x20000>; /* 128KB stride */ - #redistributor-regions = <1>; - interrupt-controller; - reg = <0x0 0x14000000 0 0x20000>, /* GICD */ - <0x0 0x14040000 0 0x100000>; /* GICR */ - interrupts = ; - }; - - ap_clk: clock-controller@21500000 { - compatible = "sprd,sc9863a-ap-clk"; - reg = <0 0x21500000 0 0x1000>; - clocks = <&ext_32k>, <&ext_26m>; - clock-names = "ext-32k", "ext-26m"; - #clock-cells = <1>; - }; - - aon_clk: clock-controller@402d0000 { - compatible = "sprd,sc9863a-aon-clk"; - reg = <0 0x402d0000 0 0x1000>; - clocks = <&ext_26m>, <&rco_100m>, - <&ext_32k>, <&ext_4m>; - clock-names = "ext-26m", "rco-100m", - "ext-32k", "ext-4m"; - #clock-cells = <1>; - }; - - mm_clk: clock-controller@60900000 { - compatible = "sprd,sc9863a-mm-clk"; - reg = <0 0x60900000 0 0x1000>; - #clock-cells = <1>; - }; - - funnel@10001000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x10001000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel_soc_out_port: endpoint { - remote-endpoint = <&etb_in>; - }; - }; - }; - - in-ports { - port { - funnel_soc_in_port: endpoint { - remote-endpoint = - <&funnel_ca55_out_port>; - }; - }; - }; - }; - - etb@10003000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x10003000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - in-ports { - port { - etb_in: endpoint { - remote-endpoint = - <&funnel_soc_out_port>; - }; - }; - }; - }; - - funnel@12001000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x12001000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel_little_out_port: endpoint { - remote-endpoint = - <&etf_little_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_little_in_port0: endpoint { - remote-endpoint = <&etm0_out>; - }; - }; - - port@1 { - reg = <1>; - funnel_little_in_port1: endpoint { - remote-endpoint = <&etm1_out>; - }; - }; - - port@2 { - reg = <2>; - funnel_little_in_port2: endpoint { - remote-endpoint = <&etm2_out>; - }; - }; - - port@3 { - reg = <3>; - funnel_little_in_port3: endpoint { - remote-endpoint = <&etm3_out>; - }; - }; - }; - }; - - etf@12002000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x12002000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etf_little_out: endpoint { - remote-endpoint = - <&funnel_ca55_in_port0>; - }; - }; - }; - - in-port { - port { - etf_little_in: endpoint { - remote-endpoint = - <&funnel_little_out_port>; - }; - }; - }; - }; - - etf@12003000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0 0x12003000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etf_big_out: endpoint { - remote-endpoint = - <&funnel_ca55_in_port1>; - }; - }; - }; - - in-ports { - port { - etf_big_in: endpoint { - remote-endpoint = - <&funnel_big_out_port>; - }; - }; - }; - }; - - funnel@12004000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x12004000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel_ca55_out_port: endpoint { - remote-endpoint = - <&funnel_soc_in_port>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_ca55_in_port0: endpoint { - remote-endpoint = - <&etf_little_out>; - }; - }; - - port@1 { - reg = <1>; - funnel_ca55_in_port1: endpoint { - remote-endpoint = - <&etf_big_out>; - }; - }; - }; - }; - - funnel@12005000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0 0x12005000 0 0x1000>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - funnel_big_out_port: endpoint { - remote-endpoint = - <&etf_big_in>; - }; - }; - }; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_big_in_port0: endpoint { - remote-endpoint = <&etm4_out>; - }; - }; - - port@1 { - reg = <1>; - funnel_big_in_port1: endpoint { - remote-endpoint = <&etm5_out>; - }; - }; - - port@2 { - reg = <2>; - funnel_big_in_port2: endpoint { - remote-endpoint = <&etm6_out>; - }; - }; - - port@3 { - reg = <3>; - funnel_big_in_port3: endpoint { - remote-endpoint = <&etm7_out>; - }; - }; - }; - }; - - etm@13040000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x13040000 0 0x1000>; - cpu = <&CPU0>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm0_out: endpoint { - remote-endpoint = - <&funnel_little_in_port0>; - }; - }; - }; - }; - - etm@13140000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x13140000 0 0x1000>; - cpu = <&CPU1>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm1_out: endpoint { - remote-endpoint = - <&funnel_little_in_port1>; - }; - }; - }; - }; - - etm@13240000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x13240000 0 0x1000>; - cpu = <&CPU2>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm2_out: endpoint { - remote-endpoint = - <&funnel_little_in_port2>; - }; - }; - }; - }; - - etm@13340000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x13340000 0 0x1000>; - cpu = <&CPU3>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm3_out: endpoint { - remote-endpoint = - <&funnel_little_in_port3>; - }; - }; - }; - }; - - etm@13440000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x13440000 0 0x1000>; - cpu = <&CPU4>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm4_out: endpoint { - remote-endpoint = - <&funnel_big_in_port0>; - }; - }; - }; - }; - - etm@13540000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x13540000 0 0x1000>; - cpu = <&CPU5>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm5_out: endpoint { - remote-endpoint = - <&funnel_big_in_port1>; - }; - }; - }; - }; - - etm@13640000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x13640000 0 0x1000>; - cpu = <&CPU6>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm6_out: endpoint { - remote-endpoint = - <&funnel_big_in_port2>; - }; - }; - }; - }; - - etm@13740000 { - compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0 0x13740000 0 0x1000>; - cpu = <&CPU7>; - clocks = <&ext_26m>; - clock-names = "apb_pclk"; - - out-ports { - port { - etm7_out: endpoint { - remote-endpoint = - <&funnel_big_in_port3>; - }; - }; - }; - }; - - ap-ahb { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - sdio0: sdio@20300000 { - compatible = "sprd,sdhci-r11"; - reg = <0 0x20300000 0 0x1000>; - interrupts = ; - - clock-names = "sdio", "enable"; - clocks = <&aon_clk CLK_SDIO0_2X>, - <&apahb_gate CLK_SDIO0_EB>; - assigned-clocks = <&aon_clk CLK_SDIO0_2X>; - assigned-clock-parents = <&rpll CLK_RPLL_390M>; - - bus-width = <4>; - no-sdio; - no-mmc; - }; - - sdio3: sdio@20600000 { - compatible = "sprd,sdhci-r11"; - reg = <0 0x20600000 0 0x1000>; - interrupts = ; - - clock-names = "sdio", "enable"; - clocks = <&aon_clk CLK_EMMC_2X>, - <&apahb_gate CLK_EMMC_EB>; - assigned-clocks = <&aon_clk CLK_EMMC_2X>; - assigned-clock-parents = <&rpll CLK_RPLL_390M>; - - bus-width = <8>; - non-removable; - no-sdio; - no-sd; - cap-mmc-hw-reset; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/sprd/sharkl3.dtsi b/arch/arm64/boot/dts/sprd/sharkl3.dtsi deleted file mode 100644 index 206a4afda..000000000 --- a/arch/arm64/boot/dts/sprd/sharkl3.dtsi +++ /dev/null @@ -1,242 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Unisoc Sharkl3 platform DTS file - * - * Copyright (C) 2019, Unisoc Inc. - */ - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ap_ahb_regs: syscon@20e00000 { - compatible = "sprd,sc9863a-glbregs", "syscon", - "simple-mfd"; - reg = <0 0x20e00000 0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x20e00000 0x4000>; - - apahb_gate: apahb-gate { - compatible = "sprd,sc9863a-apahb-gate"; - reg = <0x0 0x1020>; - #clock-cells = <1>; - }; - }; - - pmu_regs: syscon@402b0000 { - compatible = "sprd,sc9863a-glbregs", "syscon", - "simple-mfd"; - reg = <0 0x402b0000 0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x402b0000 0x4000>; - - pmu_gate: pmu-gate { - compatible = "sprd,sc9863a-pmu-gate"; - reg = <0 0x1200>; - clocks = <&ext_26m>; - clock-names = "ext-26m"; - #clock-cells = <1>; - }; - }; - - aon_apb_regs: syscon@402e0000 { - compatible = "sprd,sc9863a-glbregs", "syscon", - "simple-mfd"; - reg = <0 0x402e0000 0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x402e0000 0x4000>; - - aonapb_gate: aonapb-gate { - compatible = "sprd,sc9863a-aonapb-gate"; - reg = <0 0x1100>; - #clock-cells = <1>; - }; - }; - - anlg_phy_g2_regs: syscon@40353000 { - compatible = "sprd,sc9863a-glbregs", "syscon", - "simple-mfd"; - reg = <0 0x40353000 0 0x3000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x40353000 0x3000>; - - pll: pll { - compatible = "sprd,sc9863a-pll"; - reg = <0 0x100>; - clocks = <&ext_26m>; - clock-names = "ext-26m"; - #clock-cells = <1>; - }; - }; - - anlg_phy_g4_regs: syscon@40359000 { - compatible = "sprd,sc9863a-glbregs", "syscon", - "simple-mfd"; - reg = <0 0x40359000 0 0x3000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x40359000 0x3000>; - - mpll: mpll { - compatible = "sprd,sc9863a-mpll"; - reg = <0 0x100>; - #clock-cells = <1>; - }; - }; - - anlg_phy_g5_regs: syscon@4035c000 { - compatible = "sprd,sc9863a-glbregs", "syscon", - "simple-mfd"; - reg = <0 0x4035c000 0 0x3000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x4035c000 0x3000>; - - rpll: rpll { - compatible = "sprd,sc9863a-rpll"; - reg = <0 0x100>; - clocks = <&ext_26m>; - clock-names = "ext-26m"; - #clock-cells = <1>; - }; - }; - - anlg_phy_g7_regs: syscon@40363000 { - compatible = "sprd,sc9863a-glbregs", "syscon", - "simple-mfd"; - reg = <0 0x40363000 0 0x3000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x40363000 0x3000>; - - dpll: dpll { - compatible = "sprd,sc9863a-dpll"; - reg = <0 0x100>; - #clock-cells = <1>; - }; - }; - - mm_ahb_regs: syscon@60800000 { - compatible = "sprd,sc9863a-glbregs", "syscon", - "simple-mfd"; - reg = <0 0x60800000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x60800000 0x3000>; - - mm_gate: mm-gate { - compatible = "sprd,sc9863a-mm-gate"; - reg = <0 0x1100>; - #clock-cells = <1>; - }; - }; - - ap_apb_regs: syscon@71300000 { - compatible = "sprd,sc9863a-glbregs", "syscon", - "simple-mfd"; - reg = <0 0x71300000 0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x71300000 0x4000>; - - apapb_gate: apapb-gate { - compatible = "sprd,sc9863a-apapb-gate"; - reg = <0 0x1000>; - clocks = <&ext_26m>; - clock-names = "ext-26m"; - #clock-cells = <1>; - }; - }; - - apb@70000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x70000000 0x10000000>; - - uart0: serial@0 { - compatible = "sprd,sc9863a-uart", - "sprd,sc9836-uart"; - reg = <0x0 0x100>; - interrupts = ; - clocks = <&ext_26m>; - status = "disabled"; - }; - - uart1: serial@100000 { - compatible = "sprd,sc9863a-uart", - "sprd,sc9836-uart"; - reg = <0x100000 0x100>; - interrupts = ; - clocks = <&ext_26m>; - status = "disabled"; - }; - - uart2: serial@200000 { - compatible = "sprd,sc9863a-uart", - "sprd,sc9836-uart"; - reg = <0x200000 0x100>; - interrupts = ; - clocks = <&ext_26m>; - status = "disabled"; - }; - - uart3: serial@300000 { - compatible = "sprd,sc9863a-uart", - "sprd,sc9836-uart"; - reg = <0x300000 0x100>; - interrupts = ; - clocks = <&ext_26m>; - status = "disabled"; - }; - - uart4: serial@400000 { - compatible = "sprd,sc9863a-uart", - "sprd,sc9836-uart"; - reg = <0x400000 0x100>; - interrupts = ; - clocks = <&ext_26m>; - status = "disabled"; - }; - }; - }; - - ext_26m: ext-26m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "ext-26m"; - }; - - ext_32k: ext-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ext-32k"; - }; - - ext_4m: ext-4m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <4000000>; - clock-output-names = "ext-4m"; - }; - - rco_100m: rco-100m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "rco-100m"; - }; -}; diff --git a/arch/arm64/boot/dts/sprd/sharkl64.dtsi b/arch/arm64/boot/dts/sprd/sharkl64.dtsi deleted file mode 100644 index 69f64e7fc..000000000 --- a/arch/arm64/boot/dts/sprd/sharkl64.dtsi +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Spreadtrum Sharkl64 platform DTS file - * - * Copyright (C) 2014, Spreadtrum Communications Inc. - * - * This file is licensed under a dual GPLv2 or X11 license. - */ - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ap-apb { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - uart0: serial@70000000 { - compatible = "sprd,sc9836-uart"; - reg = <0 0x70000000 0 0x100>; - interrupts = <0 2 0xf04>; - clocks = <&clk26mhz>; - status = "disabled"; - }; - - uart1: serial@70100000 { - compatible = "sprd,sc9836-uart"; - reg = <0 0x70100000 0 0x100>; - interrupts = <0 3 0xf04>; - clocks = <&clk26mhz>; - status = "disabled"; - }; - - uart2: serial@70200000 { - compatible = "sprd,sc9836-uart"; - reg = <0 0x70200000 0 0x100>; - interrupts = <0 4 0xf04>; - clocks = <&clk26mhz>; - status = "disabled"; - }; - - uart3: serial@70300000 { - compatible = "sprd,sc9836-uart"; - reg = <0 0x70300000 0 0x100>; - interrupts = <0 5 0xf04>; - clocks = <&clk26mhz>; - status = "disabled"; - }; - }; - }; - - clk26mhz: clk26mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; -}; diff --git a/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts deleted file mode 100644 index 6b95fd94c..000000000 --- a/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Spreadtrum SP9860g board - * - * Copyright (C) 2017, Spreadtrum Communications Inc. - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -/dts-v1/; - -#include "sc9860.dtsi" -#include "sc2731.dtsi" - -/ { - model = "Spreadtrum SP9860G 3GFHD Board"; - - compatible = "sprd,sp9860g-1h10", "sprd,sc9860"; - - aliases { - serial0 = &uart0; /* for Bluetooth */ - serial1 = &uart1; /* UART console */ - serial2 = &uart2; /* Reserved */ - serial3 = &uart3; /* for GPS */ - spi0 = &adi_bus; - }; - - memory{ - device_type = "memory"; - reg = <0x0 0x80000000 0 0x60000000>, - <0x1 0x80000000 0 0x60000000>; - }; - - chosen { - stdout-path = "serial1:115200n8"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - }; - - bat: battery { - compatible = "simple-battery"; - charge-full-design-microamp-hours = <1900000>; - charge-term-current-microamp = <120000>; - constant_charge_voltage_max_microvolt = <4350000>; - internal-resistance-micro-ohms = <250000>; - ocv-capacity-celsius = <20>; - ocv-capacity-table-0 = <4185000 100>, <4113000 95>, <4066000 90>, - <4022000 85>, <3983000 80>, <3949000 75>, - <3917000 70>, <3889000 65>, <3864000 60>, - <3835000 55>, <3805000 50>, <3787000 45>, - <3777000 40>, <3773000 35>, <3770000 30>, - <3765000 25>, <3752000 20>, <3724000 15>, - <3680000 10>, <3605000 5>, <3400000 0>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/sprd/sp9863a-1h10.dts b/arch/arm64/boot/dts/sprd/sp9863a-1h10.dts deleted file mode 100644 index 5c32c1596..000000000 --- a/arch/arm64/boot/dts/sprd/sp9863a-1h10.dts +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Unisoc SP9863A-1h10 boards DTS file - * - * Copyright (C) 2019, Unisoc Inc. - */ - -/dts-v1/; - -#include "sc9863a.dtsi" - -/ { - model = "Spreadtrum SP9863A-1H10 Board"; - - compatible = "sprd,sp9863a-1h10", "sprd,sc9863a"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - chosen { - stdout-path = "serial1:115200n8"; - bootargs = "earlycon"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi deleted file mode 100644 index 79b9591c3..000000000 --- a/arch/arm64/boot/dts/sprd/whale2.dtsi +++ /dev/null @@ -1,310 +0,0 @@ -/* - * Spreadtrum Whale2 platform peripherals - * - * Copyright (C) 2016, Spreadtrum Communications Inc. - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -#include - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ap_ahb_regs: syscon@20210000 { - compatible = "syscon"; - reg = <0 0x20210000 0 0x10000>; - }; - - pmu_regs: syscon@402b0000 { - compatible = "syscon"; - reg = <0 0x402b0000 0 0x10000>; - }; - - aon_regs: syscon@402e0000 { - compatible = "syscon"; - reg = <0 0x402e0000 0 0x10000>; - }; - - ana_regs: syscon@40400000 { - compatible = "syscon"; - reg = <0 0x40400000 0 0x10000>; - }; - - agcp_regs: syscon@415e0000 { - compatible = "syscon"; - reg = <0 0x415e0000 0 0x1000000>; - }; - - vsp_regs: syscon@61100000 { - compatible = "syscon"; - reg = <0 0x61100000 0 0x10000>; - }; - - cam_regs: syscon@62100000 { - compatible = "syscon"; - reg = <0 0x62100000 0 0x10000>; - }; - - disp_regs: syscon@63100000 { - compatible = "syscon"; - reg = <0 0x63100000 0 0x10000>; - }; - - ap_apb_regs: syscon@70b00000 { - compatible = "syscon"; - reg = <0 0x70b00000 0 0x40000>; - }; - - ap-apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x70000000 0x10000000>; - - uart0: serial@0 { - compatible = "sprd,sc9860-uart", - "sprd,sc9836-uart"; - reg = <0x0 0x100>; - interrupts = ; - clock-names = "enable", "uart", "source"; - clocks = <&apapb_gate CLK_UART0_EB>, - <&ap_clk CLK_UART0>, <&ext_26m>; - status = "disabled"; - }; - - uart1: serial@100000 { - compatible = "sprd,sc9860-uart", - "sprd,sc9836-uart"; - reg = <0x100000 0x100>; - interrupts = ; - clock-names = "enable", "uart", "source"; - clocks = <&apapb_gate CLK_UART1_EB>, - <&ap_clk CLK_UART1>, <&ext_26m>; - status = "disabled"; - }; - - uart2: serial@200000 { - compatible = "sprd,sc9860-uart", - "sprd,sc9836-uart"; - reg = <0x200000 0x100>; - interrupts = ; - clock-names = "enable", "uart", "source"; - clocks = <&apapb_gate CLK_UART2_EB>, - <&ap_clk CLK_UART2>, <&ext_26m>; - status = "disabled"; - }; - - uart3: serial@300000 { - compatible = "sprd,sc9860-uart", - "sprd,sc9836-uart"; - reg = <0x300000 0x100>; - interrupts = ; - clock-names = "enable", "uart", "source"; - clocks = <&apapb_gate CLK_UART3_EB>, - <&ap_clk CLK_UART3>, <&ext_26m>; - status = "disabled"; - }; - }; - - ap-ahb { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ap_dma: dma-controller@20100000 { - compatible = "sprd,sc9860-dma"; - reg = <0 0x20100000 0 0x4000>; - interrupts = ; - #dma-cells = <1>; - #dma-channels = <32>; - clock-names = "enable"; - clocks = <&apahb_gate CLK_DMA_EB>; - }; - - sdio3: sdio@50430000 { - compatible = "sprd,sdhci-r11"; - reg = <0 0x50430000 0 0x1000>; - interrupts = ; - - clock-names = "sdio", "enable", "2x_enable"; - clocks = <&aon_prediv CLK_EMMC_2X>, - <&apahb_gate CLK_EMMC_EB>, - <&aon_gate CLK_EMMC_2X_EN>; - assigned-clocks = <&aon_prediv CLK_EMMC_2X>; - assigned-clock-parents = <&clk_l0_409m6>; - - sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>; - sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>; - sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>; - sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 0x2e 0x2e>; - vmmc-supply = <&vddemmccore>; - bus-width = <8>; - non-removable; - no-sdio; - no-sd; - cap-mmc-hw-reset; - mmc-hs400-enhanced-strobe; - mmc-hs400-1_8v; - mmc-hs200-1_8v; - mmc-ddr-1_8v; - }; - }; - - aon { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - adi_bus: spi@40030000 { - compatible = "sprd,sc9860-adi"; - reg = <0 0x40030000 0 0x10000>; - hwlocks = <&hwlock 0>; - hwlock-names = "adi"; - #address-cells = <1>; - #size-cells = <0>; - }; - - timer@40050000 { - compatible = "sprd,sc9860-timer"; - reg = <0 0x40050000 0 0x20>; - interrupts = ; - clocks = <&ext_32k>; - }; - - timer@40050020 { - compatible = "sprd,sc9860-suspend-timer"; - reg = <0 0x40050020 0 0x20>; - clocks = <&ext_32k>; - }; - - hwlock: hwspinlock@40500000 { - compatible = "sprd,hwspinlock-r3p0"; - reg = <0 0x40500000 0 0x1000>; - #hwlock-cells = <1>; - clock-names = "enable"; - clocks = <&aon_gate CLK_SPLK_EB>; - }; - - eic_debounce: gpio@40210000 { - compatible = "sprd,sc9860-eic-debounce"; - reg = <0 0x40210000 0 0x80>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - eic_latch: gpio@40210080 { - compatible = "sprd,sc9860-eic-latch"; - reg = <0 0x40210080 0 0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - eic_async: gpio@402100a0 { - compatible = "sprd,sc9860-eic-async"; - reg = <0 0x402100a0 0 0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - eic_sync: gpio@402100c0 { - compatible = "sprd,sc9860-eic-sync"; - reg = <0 0x402100c0 0 0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - ap_gpio: gpio@40280000 { - compatible = "sprd,sc9860-gpio"; - reg = <0 0x40280000 0 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - pin_controller: pinctrl@402a0000 { - compatible = "sprd,sc9860-pinctrl"; - reg = <0 0x402a0000 0 0x10000>; - }; - - watchdog@40310000 { - compatible = "sprd,sp9860-wdt"; - reg = <0 0x40310000 0 0x1000>; - interrupts = ; - timeout-sec = <12>; - clock-names = "enable", "rtc_enable"; - clocks = <&aon_gate CLK_APCPU_WDG_EB>, - <&aon_gate CLK_AP_WDG_RTC_EB>; - }; - }; - - agcp { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - agcp_dma: dma-controller@41580000 { - compatible = "sprd,sc9860-dma"; - reg = <0 0x41580000 0 0x4000>; - #dma-cells = <1>; - #dma-channels = <32>; - clock-names = "enable", "ashb_eb"; - clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>, - <&agcp_gate CLK_AGCP_AP_ASHB_EB>; - }; - }; - }; - - ext_32k: ext_32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ext-32k"; - }; - - ext_26m: ext_26m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <26000000>; - clock-output-names = "ext-26m"; - }; - - ext_rco_100m: ext_rco_100m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "ext-rco-100m"; - }; - - clk_l0_409m6: clk_l0_409m6 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <409600000>; - clock-output-names = "ext-409m6"; - }; -}; diff --git a/arch/arm64/boot/dts/synaptics/Makefile b/arch/arm64/boot/dts/synaptics/Makefile deleted file mode 100644 index de71ddda6..000000000 --- a/arch/arm64/boot/dts/synaptics/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# Berlin SoC Family -dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-dmp.dtb -dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-stb.dtb diff --git a/arch/arm64/boot/dts/synaptics/as370.dtsi b/arch/arm64/boot/dts/synaptics/as370.dtsi deleted file mode 100644 index addeb0efc..000000000 --- a/arch/arm64/boot/dts/synaptics/as370.dtsi +++ /dev/null @@ -1,173 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2018 Synaptics Incorporated - * - * Author: Jisheng Zhang - */ - -#include - -/ { - compatible = "syna,as370"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - l2: cache { - compatible = "cache"; - }; - - idle-states { - entry-method = "psci"; - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <75>; - exit-latency-us = <155>; - min-residency-us = <1000>; - }; - }; - }; - - osc: osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - soc@f7000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xf7000000 0x1000000>; - - gic: interrupt-controller@901000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x901000 0x1000>, - <0x902000 0x2000>, - <0x904000 0x2000>, - <0x906000 0x2000>; - interrupts = ; - }; - - apb@e80000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xe80000 0x10000>; - - uart0: serial@c00 { - compatible = "snps,dw-apb-uart"; - reg = <0xc00 0x100>; - interrupts = ; - clocks = <&osc>; - reg-shift = <2>; - status = "disabled"; - }; - - gpio0: gpio@1800 { - compatible = "snps,dw-apb-gpio"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-port@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - }; - - gpio1: gpio@2000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x2000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portb: gpio-port@1 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/synaptics/berlin4ct-dmp.dts b/arch/arm64/boot/dts/synaptics/berlin4ct-dmp.dts deleted file mode 100644 index c64a179eb..000000000 --- a/arch/arm64/boot/dts/synaptics/berlin4ct-dmp.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2015 Marvell Technology Group Ltd. - * - * Author: Jisheng Zhang - */ - -/dts-v1/; - -#include "berlin4ct.dtsi" - -/ { - model = "Marvell BG4CT DMP board"; - compatible = "marvell,berlin4ct-dmp", "marvell,berlin4ct", "marvell,berlin"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@1000000 { - device_type = "memory"; - /* the first 16MB is for firmwares' usage */ - reg = <0 0x01000000 0 0x7f000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/synaptics/berlin4ct-stb.dts b/arch/arm64/boot/dts/synaptics/berlin4ct-stb.dts deleted file mode 100644 index 277dccfa0..000000000 --- a/arch/arm64/boot/dts/synaptics/berlin4ct-stb.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2015 Marvell Technology Group Ltd. - * - * Author: Jisheng Zhang - */ - -/dts-v1/; - -#include "berlin4ct.dtsi" - -/ { - model = "Marvell BG4CT STB board"; - compatible = "marvell,berlin4ct-stb", "marvell,berlin4ct", "marvell,berlin"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@1000000 { - device_type = "memory"; - /* the first 16MB is for firmwares' usage */ - reg = <0 0x01000000 0 0x7f000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi deleted file mode 100644 index 15625b99e..000000000 --- a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi +++ /dev/null @@ -1,314 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2015 Marvell Technology Group Ltd. - * - * Author: Jisheng Zhang - */ - -#include - -/ { - compatible = "marvell,berlin4ct", "marvell,berlin"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &uart0; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - l2: cache { - compatible = "cache"; - }; - - idle-states { - entry-method = "psci"; - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <75>; - exit-latency-us = <155>; - min-residency-us = <1000>; - }; - }; - }; - - osc: osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - pmu { - compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - soc@f7000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xf7000000 0x1000000>; - - gic: interrupt-controller@901000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x901000 0x1000>, - <0x902000 0x2000>, - <0x904000 0x2000>, - <0x906000 0x2000>; - interrupts = ; - }; - - apb@e80000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0 0xe80000 0x10000>; - interrupt-parent = <&aic>; - - gpio0: gpio@400 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-port@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0>; - }; - }; - - gpio1: gpio@800 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portb: gpio-port@1 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <1>; - }; - }; - - gpio2: gpio@c00 { - compatible = "snps,dw-apb-gpio"; - reg = <0x0c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portc: gpio-port@2 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <2>; - }; - }; - - gpio3: gpio@1000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x1000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portd: gpio-port@3 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <3>; - }; - }; - - aic: interrupt-controller@3800 { - compatible = "snps,dw-apb-ictl"; - reg = <0x3800 0x30>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - soc_pinctrl: pin-controller@ea8000 { - compatible = "marvell,berlin4ct-soc-pinctrl"; - reg = <0xea8000 0x14>; - }; - - avio_pinctrl: pin-controller@ea8400 { - compatible = "marvell,berlin4ct-avio-pinctrl"; - reg = <0xea8400 0x8>; - }; - - apb@fc0000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xfc0000 0x10000>; - interrupt-parent = <&sic>; - - sic: interrupt-controller@1000 { - compatible = "snps,dw-apb-ictl"; - reg = <0x1000 0x30>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - - wdt0: watchdog@3000 { - compatible = "snps,dw-wdt"; - reg = <0x3000 0x100>; - clocks = <&osc>; - interrupts = <0>; - }; - - wdt1: watchdog@4000 { - compatible = "snps,dw-wdt"; - reg = <0x4000 0x100>; - clocks = <&osc>; - interrupts = <1>; - }; - - wdt2: watchdog@5000 { - compatible = "snps,dw-wdt"; - reg = <0x5000 0x100>; - clocks = <&osc>; - interrupts = <2>; - }; - - sm_gpio0: gpio@8000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x8000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porte: gpio-port@4 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - }; - }; - - sm_gpio1: gpio@9000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x9000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portf: gpio-port@5 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <32>; - reg = <0>; - }; - }; - - uart0: uart@d000 { - compatible = "snps,dw-apb-uart"; - reg = <0xd000 0x100>; - interrupts = <8>; - clocks = <&osc>; - reg-shift = <2>; - status = "disabled"; - pinctrl-0 = <&uart0_pmux>; - pinctrl-names = "default"; - }; - }; - - system_pinctrl: pin-controller@fe2200 { - compatible = "marvell,berlin4ct-system-pinctrl"; - reg = <0xfe2200 0xc>; - - uart0_pmux: uart0-pmux { - groups = "SM_URT0_TXD", "SM_URT0_RXD"; - function = "uart0"; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile deleted file mode 100644 index 65506f21b..000000000 --- a/arch/arm64/boot/dts/ti/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Make file to build device tree binaries for boards based on -# Texas Instruments Inc processors -# -# Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ -# - -dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb - -dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb - -dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi deleted file mode 100644 index d04189771..000000000 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ /dev/null @@ -1,934 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM6 SoC Family Main Domain peripherals - * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ - */ -#include - -&cbass_main { - msmc_ram: sram@70000000 { - compatible = "mmio-sram"; - reg = <0x0 0x70000000 0x0 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x70000000 0x200000>; - - atf-sram@0 { - reg = <0x0 0x20000>; - }; - - sysfw-sram@f0000 { - reg = <0xf0000 0x10000>; - }; - - l3cache-sram@100000 { - reg = <0x100000 0x100000>; - }; - }; - - gic500: interrupt-controller@1800000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01880000 0x00 0x90000>, /* GICR */ - <0x00 0x6f000000 0x00 0x2000>, /* GICC */ - <0x00 0x6f010000 0x00 0x1000>, /* GICH */ - <0x00 0x6f020000 0x00 0x2000>; /* GICV */ - /* - * vcpumntirq: - * virtual CPU interface maintenance interrupt - */ - interrupts = ; - - gic_its: msi-controller@1820000 { - compatible = "arm,gic-v3-its"; - reg = <0x00 0x01820000 0x00 0x10000>; - socionext,synquacer-pre-its = <0x1000000 0x400000>; - msi-controller; - #msi-cells = <1>; - }; - }; - - serdes0: serdes@900000 { - compatible = "ti,phy-am654-serdes"; - reg = <0x0 0x900000 0x0 0x2000>; - reg-names = "serdes"; - #phy-cells = <2>; - power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>; - clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk"; - assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; - assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; - ti,serdes-clk = <&serdes0_clk>; - #clock-cells = <1>; - mux-controls = <&serdes_mux 0>; - }; - - serdes1: serdes@910000 { - compatible = "ti,phy-am654-serdes"; - reg = <0x0 0x910000 0x0 0x2000>; - reg-names = "serdes"; - #phy-cells = <2>; - power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; - clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>; - clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk"; - assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>; - assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; - ti,serdes-clk = <&serdes1_clk>; - #clock-cells = <1>; - mux-controls = <&serdes_mux 1>; - }; - - main_uart0: serial@2800000 { - compatible = "ti,am654-uart"; - reg = <0x00 0x02800000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; - }; - - main_uart1: serial@2810000 { - compatible = "ti,am654-uart"; - reg = <0x00 0x02810000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; - }; - - main_uart2: serial@2820000 { - compatible = "ti,am654-uart"; - reg = <0x00 0x02820000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; - }; - - crypto: crypto@4e00000 { - compatible = "ti,am654-sa2ul"; - reg = <0x0 0x4e00000 0x0 0x1200>; - power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; - status = "okay"; - - dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, - <&main_udmap 0x4001>; - dma-names = "tx", "rx1", "rx2"; - dma-coherent; - - rng: rng@4e10000 { - compatible = "inside-secure,safexcel-eip76"; - reg = <0x0 0x4e10000 0x0 0x7d>; - interrupts = ; - clocks = <&k3_clks 136 1>; - }; - }; - - main_pmx0: pinctrl@11c000 { - compatible = "pinctrl-single"; - reg = <0x0 0x11c000 0x0 0x2e4>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - main_pmx1: pinctrl@11c2e8 { - compatible = "pinctrl-single"; - reg = <0x0 0x11c2e8 0x0 0x24>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - main_i2c0: i2c@2000000 { - compatible = "ti,am654-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2000000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 110 1>; - power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c1: i2c@2010000 { - compatible = "ti,am654-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2010000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 111 1>; - power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c2: i2c@2020000 { - compatible = "ti,am654-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2020000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 112 1>; - power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c3: i2c@2030000 { - compatible = "ti,am654-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2030000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 113 1>; - power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; - }; - - ecap0: pwm@3100000 { - compatible = "ti,am654-ecap", "ti,am3352-ecap"; - #pwm-cells = <3>; - reg = <0x0 0x03100000 0x0 0x60>; - power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 39 0>; - clock-names = "fck"; - }; - - main_spi0: spi@2100000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x2100000 0x0 0x400>; - interrupts = ; - clocks = <&k3_clks 137 1>; - power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; - dma-names = "tx0", "rx0"; - }; - - main_spi1: spi@2110000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x2110000 0x0 0x400>; - interrupts = ; - clocks = <&k3_clks 138 1>; - power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - assigned-clocks = <&k3_clks 137 1>; - assigned-clock-rates = <48000000>; - }; - - main_spi2: spi@2120000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x2120000 0x0 0x400>; - interrupts = ; - clocks = <&k3_clks 139 1>; - power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - }; - - main_spi3: spi@2130000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x2130000 0x0 0x400>; - interrupts = ; - clocks = <&k3_clks 140 1>; - power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - }; - - main_spi4: spi@2140000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x2140000 0x0 0x400>; - interrupts = ; - clocks = <&k3_clks 141 1>; - power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sdhci0: sdhci@4f80000 { - compatible = "ti,am654-sdhci-5.1"; - reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; - power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 47 0>, <&k3_clks 47 1>; - clock-names = "clk_ahb", "clk_xin"; - interrupts = ; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0x0>; - ti,otap-del-sel-sdr25 = <0x0>; - ti,otap-del-sel-sdr50 = <0x8>; - ti,otap-del-sel-sdr104 = <0x7>; - ti,otap-del-sel-ddr50 = <0x5>; - ti,otap-del-sel-ddr52 = <0x5>; - ti,otap-del-sel-hs200 = <0x5>; - ti,otap-del-sel-hs400 = <0x0>; - ti,trm-icp = <0x8>; - dma-coherent; - }; - - sdhci1: sdhci@4fa0000 { - compatible = "ti,am654-sdhci-5.1"; - reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>; - power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 48 0>, <&k3_clks 48 1>; - clock-names = "clk_ahb", "clk_xin"; - interrupts = ; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0x0>; - ti,otap-del-sel-sdr25 = <0x0>; - ti,otap-del-sel-sdr50 = <0x8>; - ti,otap-del-sel-sdr104 = <0x7>; - ti,otap-del-sel-ddr50 = <0x4>; - ti,otap-del-sel-ddr52 = <0x4>; - ti,otap-del-sel-hs200 = <0x7>; - ti,clkbuf-sel = <0x7>; - ti,otap-del-sel = <0x2>; - ti,trm-icp = <0x8>; - dma-coherent; - no-1-8-v; - }; - - scm_conf: scm-conf@100000 { - compatible = "syscon", "simple-mfd"; - reg = <0 0x00100000 0 0x1c000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x00100000 0x1c000>; - - pcie0_mode: pcie-mode@4060 { - compatible = "syscon"; - reg = <0x00004060 0x4>; - }; - - pcie1_mode: pcie-mode@4070 { - compatible = "syscon"; - reg = <0x00004070 0x4>; - }; - - pcie_devid: pcie-devid@210 { - compatible = "syscon"; - reg = <0x00000210 0x4>; - }; - - serdes0_clk: clock@4080 { - compatible = "syscon"; - reg = <0x00004080 0x4>; - }; - - serdes1_clk: clock@4090 { - compatible = "syscon"; - reg = <0x00004090 0x4>; - }; - - serdes_mux: mux-controller { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */ - <0x4090 0x3>; /* SERDES1 lane select */ - }; - - dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 { - compatible = "syscon"; - reg = <0x0000041e0 0x14>; - }; - - ehrpwm_tbclk: clock@4140 { - compatible = "ti,am654-ehrpwm-tbclk", "syscon"; - reg = <0x4140 0x18>; - #clock-cells = <1>; - }; - }; - - dwc3_0: dwc3@4000000 { - compatible = "ti,am654-dwc3"; - reg = <0x0 0x4000000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x4000000 0x20000>; - interrupts = ; - dma-coherent; - power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; - assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; - assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ - <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ - - usb0: usb@10000 { - compatible = "snps,dwc3"; - reg = <0x10000 0x10000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - phys = <&usb0_phy>; - phy-names = "usb2-phy"; - snps,dis_u3_susphy_quirk; - }; - }; - - usb0_phy: phy@4100000 { - compatible = "ti,am654-usb2", "ti,omap-usb2"; - reg = <0x0 0x4100000 0x0 0x54>; - syscon-phy-power = <&scm_conf 0x4000>; - clocks = <&k3_clks 151 0>, <&k3_clks 151 1>; - clock-names = "wkupclk", "refclk"; - #phy-cells = <0>; - }; - - dwc3_1: dwc3@4020000 { - compatible = "ti,am654-dwc3"; - reg = <0x0 0x4020000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x4020000 0x20000>; - interrupts = ; - dma-coherent; - power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 152 2>; - assigned-clocks = <&k3_clks 152 2>; - assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ - - usb1: usb@10000 { - compatible = "snps,dwc3"; - reg = <0x10000 0x10000>; - interrupts = , - , - ; - interrupt-names = "peripheral", - "host", - "otg"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - phys = <&usb1_phy>; - phy-names = "usb2-phy"; - }; - }; - - usb1_phy: phy@4110000 { - compatible = "ti,am654-usb2", "ti,omap-usb2"; - reg = <0x0 0x4110000 0x0 0x54>; - syscon-phy-power = <&scm_conf 0x4020>; - clocks = <&k3_clks 152 0>, <&k3_clks 152 1>; - clock-names = "wkupclk", "refclk"; - #phy-cells = <0>; - }; - - intr_main_gpio: interrupt-controller0 { - compatible = "ti,sci-intr"; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <100>; - ti,interrupt-ranges = <0 392 32>; - }; - - main-navss { - compatible = "simple-mfd"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-coherent; - dma-ranges; - - ti,sci-dev-id = <118>; - - intr_main_navss: interrupt-controller1 { - compatible = "ti,sci-intr"; - ti,intr-trigger-type = <4>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <182>; - ti,interrupt-ranges = <0 64 64>, - <64 448 64>; - }; - - inta_main_udmass: interrupt-controller@33d00000 { - compatible = "ti,sci-inta"; - reg = <0x0 0x33d00000 0x0 0x100000>; - interrupt-controller; - interrupt-parent = <&intr_main_navss>; - msi-controller; - ti,sci = <&dmsc>; - ti,sci-dev-id = <179>; - ti,interrupt-ranges = <0 0 256>; - }; - - secure_proxy_main: mailbox@32c00000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x32c00000 0x00 0x100000>, - <0x00 0x32400000 0x00 0x100000>, - <0x00 0x32800000 0x00 0x100000>; - interrupt-names = "rx_011"; - interrupts = ; - }; - - hwspinlock: spinlock@30e00000 { - compatible = "ti,am654-hwspinlock"; - reg = <0x00 0x30e00000 0x00 0x1000>; - #hwlock-cells = <1>; - }; - - mailbox0_cluster0: mailbox@31f80000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f80000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - mailbox0_cluster1: mailbox@31f81000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f81000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - mailbox0_cluster2: mailbox@31f82000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f82000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - mailbox0_cluster3: mailbox@31f83000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f83000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - mailbox0_cluster4: mailbox@31f84000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f84000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - mailbox0_cluster5: mailbox@31f85000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f85000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - mailbox0_cluster6: mailbox@31f86000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f86000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - mailbox0_cluster7: mailbox@31f87000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f87000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - mailbox0_cluster8: mailbox@31f88000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f88000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - mailbox0_cluster9: mailbox@31f89000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f89000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - mailbox0_cluster10: mailbox@31f8a000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8a000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - mailbox0_cluster11: mailbox@31f8b000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8b000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&intr_main_navss>; - }; - - ringacc: ringacc@3c000000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x3c000000 0x0 0x400000>, - <0x0 0x38000000 0x0 0x400000>, - <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; - ti,num-rings = <818>; - ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,dma-ring-reset-quirk; - ti,sci = <&dmsc>; - ti,sci-dev-id = <187>; - msi-parent = <&inta_main_udmass>; - }; - - main_udmap: dma-controller@31150000 { - compatible = "ti,am654-navss-main-udmap"; - reg = <0x0 0x31150000 0x0 0x100>, - <0x0 0x34000000 0x0 0x100000>, - <0x0 0x35000000 0x0 0x100000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&inta_main_udmass>; - #dma-cells = <1>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <188>; - ti,ringacc = <&ringacc>; - - ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ - <0xd>; /* TX_CHAN */ - ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ - <0xa>; /* RX_CHAN */ - ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ - }; - - cpts@310d0000 { - compatible = "ti,am65-cpts"; - reg = <0x0 0x310d0000 0x0 0x400>; - reg-names = "cpts"; - clocks = <&main_cpts_mux>; - clock-names = "cpts"; - interrupts-extended = <&intr_main_navss 391>; - interrupt-names = "cpts"; - ti,cpts-periodic-outputs = <6>; - ti,cpts-ext-ts-inputs = <8>; - - main_cpts_mux: refclk-mux { - #clock-cells = <0>; - clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, - <&k3_clks 118 6>, <&k3_clks 118 3>, - <&k3_clks 118 8>, <&k3_clks 118 14>, - <&k3_clks 120 3>, <&k3_clks 121 3>; - assigned-clocks = <&main_cpts_mux>; - assigned-clock-parents = <&k3_clks 118 5>; - }; - }; - }; - - main_gpio0: gpio@600000 { - compatible = "ti,am654-gpio", "ti,keystone-gpio"; - reg = <0x0 0x600000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&intr_main_gpio>; - interrupts = <192>, <193>, <194>, <195>, <196>, <197>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <96>; - ti,davinci-gpio-unbanked = <0>; - clocks = <&k3_clks 57 0>; - clock-names = "gpio"; - }; - - main_gpio1: gpio@601000 { - compatible = "ti,am654-gpio", "ti,keystone-gpio"; - reg = <0x0 0x601000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&intr_main_gpio>; - interrupts = <200>, <201>, <202>, <203>, <204>, <205>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <90>; - ti,davinci-gpio-unbanked = <0>; - clocks = <&k3_clks 58 0>; - clock-names = "gpio"; - }; - - pcie0_rc: pcie@5500000 { - compatible = "ti,am654-pcie-rc"; - reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; - reg-names = "app", "dbics", "config", "atu"; - power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000 - 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; - ti,syscon-pcie-id = <&pcie_devid>; - ti,syscon-pcie-mode = <&pcie0_mode>; - bus-range = <0x0 0xff>; - num-viewport = <16>; - max-link-speed = <2>; - dma-coherent; - interrupts = ; - msi-map = <0x0 &gic_its 0x0 0x10000>; - }; - - pcie0_ep: pcie-ep@5500000 { - compatible = "ti,am654-pcie-ep"; - reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; - reg-names = "app", "dbics", "addr_space", "atu"; - power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; - ti,syscon-pcie-mode = <&pcie0_mode>; - num-ib-windows = <16>; - num-ob-windows = <16>; - max-link-speed = <2>; - dma-coherent; - interrupts = ; - }; - - pcie1_rc: pcie@5600000 { - compatible = "ti,am654-pcie-rc"; - reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; - reg-names = "app", "dbics", "config", "atu"; - power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000 - 0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; - ti,syscon-pcie-id = <&pcie_devid>; - ti,syscon-pcie-mode = <&pcie1_mode>; - bus-range = <0x0 0xff>; - num-viewport = <16>; - max-link-speed = <2>; - dma-coherent; - interrupts = ; - msi-map = <0x0 &gic_its 0x10000 0x10000>; - }; - - pcie1_ep: pcie-ep@5600000 { - compatible = "ti,am654-pcie-ep"; - reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; - reg-names = "app", "dbics", "addr_space", "atu"; - power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; - ti,syscon-pcie-mode = <&pcie1_mode>; - num-ib-windows = <16>; - num-ob-windows = <16>; - max-link-speed = <2>; - dma-coherent; - interrupts = ; - }; - - mcasp0: mcasp@2b00000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b00000 0x0 0x2000>, - <0x0 0x02b08000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 104 0>; - clock-names = "fck"; - power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp1: mcasp@2b10000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b10000 0x0 0x2000>, - <0x0 0x02b18000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 105 0>; - clock-names = "fck"; - power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp2: mcasp@2b20000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b20000 0x0 0x2000>, - <0x0 0x02b28000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 106 0>; - clock-names = "fck"; - power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - cal: cal@6f03000 { - compatible = "ti,am654-cal"; - reg = <0x0 0x06f03000 0x0 0x400>, - <0x0 0x06f03800 0x0 0x40>; - reg-names = "cal_top", - "cal_rx_core0"; - interrupts = ; - ti,camerrx-control = <&scm_conf 0x40c0>; - clock-names = "fck"; - clocks = <&k3_clks 2 0>; - power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - csi2_0: port@0 { - reg = <0>; - }; - }; - }; - - dss: dss@4a00000 { - compatible = "ti,am65x-dss"; - reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ - <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ - <0x0 0x04a06000 0x0 0x1000>, /* vid */ - <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ - <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ - <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ - <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ - reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; - - ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; - - power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; - - clocks = <&k3_clks 67 1>, - <&k3_clks 216 1>, - <&k3_clks 67 2>; - clock-names = "fck", "vp1", "vp2"; - - /* - * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via - * DIV1. See "Figure 12-3365. DSS Integration" - * in AM65x TRM for details. - */ - assigned-clocks = <&k3_clks 67 2>; - assigned-clock-parents = <&k3_clks 67 5>; - - interrupts = ; - - status = "disabled"; - - dma-coherent; - - dss_ports: ports { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - ehrpwm0: pwm@3000000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x0 0x3000000 0x0 0x100>; - power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>; - clock-names = "tbclk", "fck"; - }; - - ehrpwm1: pwm@3010000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x0 0x3010000 0x0 0x100>; - power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>; - clock-names = "tbclk", "fck"; - }; - - ehrpwm2: pwm@3020000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x0 0x3020000 0x0 0x100>; - power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>; - clock-names = "tbclk", "fck"; - }; - - ehrpwm3: pwm@3030000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x0 0x3030000 0x0 0x100>; - power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>; - clock-names = "tbclk", "fck"; - }; - - ehrpwm4: pwm@3040000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x0 0x3040000 0x0 0x100>; - power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>; - clock-names = "tbclk", "fck"; - }; - - ehrpwm5: pwm@3050000 { - compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; - #pwm-cells = <3>; - reg = <0x0 0x3050000 0x0 0x100>; - power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; - clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>; - clock-names = "tbclk", "fck"; - }; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi deleted file mode 100644 index 29aaf8dca..000000000 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ /dev/null @@ -1,272 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM6 SoC Family MCU Domain peripherals - * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_mcu { - mcu_conf: scm-conf@40f00000 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0x40f00000 0x0 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x40f00000 0x20000>; - - phy_gmii_sel: phy@4040 { - compatible = "ti,am654-phy-gmii-sel"; - reg = <0x4040 0x4>; - #phy-cells = <1>; - }; - }; - - mcu_uart0: serial@40a00000 { - compatible = "ti,am654-uart"; - reg = <0x00 0x40a00000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <96000000>; - current-speed = <115200>; - power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; - }; - - mcu_ram: sram@41c00000 { - compatible = "mmio-sram"; - reg = <0x00 0x41c00000 0x00 0x80000>; - ranges = <0x0 0x00 0x41c00000 0x80000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - mcu_i2c0: i2c@40b00000 { - compatible = "ti,am654-i2c", "ti,omap4-i2c"; - reg = <0x0 0x40b00000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 114 1>; - power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; - }; - - mcu_spi0: spi@40300000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x40300000 0x0 0x400>; - interrupts = ; - clocks = <&k3_clks 142 1>; - power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - }; - - mcu_spi1: spi@40310000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x40310000 0x0 0x400>; - interrupts = ; - clocks = <&k3_clks 143 1>; - power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - }; - - mcu_spi2: spi@40320000 { - compatible = "ti,am654-mcspi","ti,omap4-mcspi"; - reg = <0x0 0x40320000 0x0 0x400>; - interrupts = ; - clocks = <&k3_clks 144 1>; - power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - }; - - tscadc0: tscadc@40200000 { - compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; - reg = <0x0 0x40200000 0x0 0x1000>; - interrupts = ; - clocks = <&k3_clks 0 2>; - assigned-clocks = <&k3_clks 0 2>; - assigned-clock-rates = <60000000>; - clock-names = "adc_tsc_fck"; - dmas = <&mcu_udmap 0x7100>, - <&mcu_udmap 0x7101 >; - dma-names = "fifo0", "fifo1"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am654-adc", "ti,am3359-adc"; - }; - }; - - tscadc1: tscadc@40210000 { - compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; - reg = <0x0 0x40210000 0x0 0x1000>; - interrupts = ; - clocks = <&k3_clks 1 2>; - assigned-clocks = <&k3_clks 1 2>; - assigned-clock-rates = <60000000>; - clock-names = "adc_tsc_fck"; - dmas = <&mcu_udmap 0x7102>, - <&mcu_udmap 0x7103>; - dma-names = "fifo0", "fifo1"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am654-adc", "ti,am3359-adc"; - }; - }; - - mcu-navss { - compatible = "simple-mfd"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-coherent; - dma-ranges; - - ti,sci-dev-id = <119>; - - mcu_ringacc: ringacc@2b800000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x2b800000 0x0 0x400000>, - <0x0 0x2b000000 0x0 0x400000>, - <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; - ti,num-rings = <286>; - ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,dma-ring-reset-quirk; - ti,sci = <&dmsc>; - ti,sci-dev-id = <195>; - msi-parent = <&inta_main_udmass>; - }; - - mcu_udmap: dma-controller@285c0000 { - compatible = "ti,am654-navss-mcu-udmap"; - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x2aa00000 0x0 0x40000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&inta_main_udmass>; - #dma-cells = <1>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <194>; - ti,ringacc = <&mcu_ringacc>; - - ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ - <0xd>; /* TX_CHAN */ - ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ - <0xa>; /* RX_CHAN */ - ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ - }; - }; - - fss: fss@47000000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ospi0: spi@47040000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x0 0x47040000 0x0 0x100>, - <0x5 0x00000000 0x1 0x0000000>; - interrupts = ; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 248 0>; - assigned-clocks = <&k3_clks 248 0>; - assigned-clock-parents = <&k3_clks 248 2>; - assigned-clock-rates = <166666666>; - power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - }; - - ospi1: spi@47050000 { - compatible = "ti,am654-ospi", "cdns,qspi-nor"; - reg = <0x0 0x47050000 0x0 0x100>, - <0x7 0x00000000 0x1 0x00000000>; - interrupts = ; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 249 6>; - power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - mcu_cpsw: ethernet@46000000 { - compatible = "ti,am654-cpsw-nuss"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x46000000 0x0 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; - dma-coherent; - clocks = <&k3_clks 5 10>; - clock-names = "fck"; - power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&mcu_udmap 0xf000>, - <&mcu_udmap 0xf001>, - <&mcu_udmap 0xf002>, - <&mcu_udmap 0xf003>, - <&mcu_udmap 0xf004>, - <&mcu_udmap 0xf005>, - <&mcu_udmap 0xf006>, - <&mcu_udmap 0xf007>, - <&mcu_udmap 0x7000>; - dma-names = "tx0", "tx1", "tx2", "tx3", - "tx4", "tx5", "tx6", "tx7", - "rx"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - cpsw_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - ti,syscon-efuse = <&mcu_conf 0x200>; - phys = <&phy_gmii_sel 1>; - }; - }; - - davinci_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x0 0xf00 0x0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 5 10>; - clock-names = "fck"; - bus_freq = <1000000>; - }; - - cpts@3d000 { - compatible = "ti,am65-cpts"; - reg = <0x0 0x3d000 0x0 0x400>; - clocks = <&mcu_cpsw_cpts_mux>; - clock-names = "cpts"; - interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - - mcu_cpsw_cpts_mux: refclk-mux { - #clock-cells = <0>; - clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, - <&k3_clks 118 6>, <&k3_clks 118 3>, - <&k3_clks 118 8>, <&k3_clks 118 14>, - <&k3_clks 120 3>, <&k3_clks 121 3>; - assigned-clocks = <&mcu_cpsw_cpts_mux>; - assigned-clock-parents = <&k3_clks 118 5>; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi deleted file mode 100644 index ed42f13e7..000000000 --- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM6 SoC Family Wakeup Domain peripherals - * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_wakeup { - dmsc: dmsc { - compatible = "ti,am654-sci"; - ti,host-id = <12>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mbox-names = "rx", "tx"; - - mboxes= <&secure_proxy_main 11>, - <&secure_proxy_main 13>; - - k3_pds: power-controller { - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <2>; - }; - - k3_clks: clocks { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; - - k3_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; - }; - - chipid@43000014 { - compatible = "ti,am654-chipid"; - reg = <0x43000014 0x4>; - }; - - wkup_pmx0: pinctrl@4301c000 { - compatible = "pinctrl-single"; - reg = <0x4301c000 0x118>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - wkup_uart0: serial@42300000 { - compatible = "ti,am654-uart"; - reg = <0x42300000 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>; - }; - - wkup_i2c0: i2c@42120000 { - compatible = "ti,am654-i2c", "ti,omap4-i2c"; - reg = <0x42120000 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 115 1>; - power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; - }; - - intr_wkup_gpio: interrupt-controller2 { - compatible = "ti,sci-intr"; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <156>; - ti,interrupt-ranges = <0 712 16>; - }; - - wkup_gpio0: gpio@42110000 { - compatible = "ti,am654-gpio", "ti,keystone-gpio"; - reg = <0x42110000 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&intr_wkup_gpio>; - interrupts = <60>, <61>, <62>, <63>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <56>; - ti,davinci-gpio-unbanked = <0>; - clocks = <&k3_clks 59 0>; - clock-names = "gpio"; - }; - - wkup_vtm0: temperature-sensor@42050000 { - compatible = "ti,am654-vtm"; - reg = <0x42050000 0x25c>; - power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; - #thermal-sensor-cells = <1>; - }; - - thermal_zones: thermal-zones { - #include "k3-am654-industrial-thermal.dtsi" - }; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi deleted file mode 100644 index c6a3fecc7..000000000 --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM6 SoC Family - * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include -#include -#include -#include -#include - -/ { - model = "Texas Instruments K3 AM654 SoC"; - compatible = "ti,am654"; - interrupt-parent = <&gic500>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - i2c0 = &wkup_i2c0; - i2c1 = &mcu_i2c0; - i2c2 = &main_i2c0; - i2c3 = &main_i2c1; - i2c4 = &main_i2c2; - i2c5 = &main_i2c3; - ethernet0 = &cpsw_port1; - }; - - chosen { }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - psci: psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - }; - - a53_timer0: timer-cl0-cpu0 { - compatible = "arm,armv8-timer"; - interrupts = , /* cntpsirq */ - , /* cntpnsirq */ - , /* cntvirq */ - ; /* cnthpirq */ - }; - - pmu: pmu { - compatible = "arm,armv8-pmuv3"; - /* Recommendation from GIC500 TRM Table A.3 */ - interrupts = ; - }; - - cbass_main: bus@100000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ - <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ - <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ - <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ - <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */ - <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */ - <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ - /* MCUSS Range */ - <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, - <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, - <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, - <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */ - <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>, - <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, - <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; - - cbass_mcu: bus@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ - <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */ - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */ - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */ - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */ - <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /* FSS OSPI0 data region 1 */ - <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/ - <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/ - - cbass_wakeup: bus@42040000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - /* WKUP Basic peripherals */ - ranges = <0x42040000 0x00 0x42040000 0x03ac2400>; - }; - }; - }; -}; - -/* Now include the peripherals for each bus segments */ -#include "k3-am65-main.dtsi" -#include "k3-am65-mcu.dtsi" -#include "k3-am65-wakeup.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts deleted file mode 100644 index 937dd7280..000000000 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ /dev/null @@ -1,488 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-am654.dtsi" -#include -#include - -/ { - compatible = "ti,am654-evm", "ti,am654"; - model = "Texas Instruments AM654 Base Board"; - - chosen { - stdout-path = "serial2:115200n8"; - bootargs = "earlycon=ns16550a,mmio32,0x02800000"; - }; - - memory@80000000 { - device_type = "memory"; - /* 4G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>, - <0x00000008 0x80000000 0x00000000 0x80000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - secure_ddr: secure-ddr@9e800000 { - reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */ - alignment = <0x1000>; - no-map; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&push_button_pins_default>; - - sw5 { - label = "GPIO Key USER1"; - linux,code = ; - gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>; - }; - - sw6 { - label = "GPIO Key USER2"; - linux,code = ; - gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>; - }; - }; - - clk_ov5640_fixed: clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; -}; - -&wkup_pmx0 { - wkup_i2c0_pins_default: wkup-i2c0-pins-default { - pinctrl-single,pins = < - AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */ - AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */ - >; - }; - - push_button_pins_default: push-button-pins-default { - pinctrl-single,pins = < - AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */ - AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */ - >; - }; - - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { - pinctrl-single,pins = < - AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */ - AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */ - AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */ - AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */ - AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */ - AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */ - AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */ - AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */ - AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */ - AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */ - AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */ - >; - }; - - wkup_pca554_default: wkup-pca554-default { - pinctrl-single,pins = < - AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ - >; - }; - - mcu_cpsw_pins_default: mcu-cpsw-pins-default { - pinctrl-single,pins = < - AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */ - AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */ - AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */ - AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */ - AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */ - AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */ - AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */ - AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */ - AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */ - AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */ - AM65X_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* (N1) MCU_RGMII1_TXC */ - AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */ - >; - }; - - mcu_mdio_pins_default: mcu-mdio1-pins-default { - pinctrl-single,pins = < - AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ - AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ - >; - }; -}; - -&main_pmx0 { - main_uart0_pins_default: main-uart0-pins-default { - pinctrl-single,pins = < - AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */ - AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */ - AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */ - AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */ - >; - }; - - main_i2c2_pins_default: main-i2c2-pins-default { - pinctrl-single,pins = < - AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */ - AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */ - >; - }; - - main_spi0_pins_default: main-spi0-pins-default { - pinctrl-single,pins = < - AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */ - AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */ - AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */ - AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */ - >; - }; - - main_mmc0_pins_default: main-mmc0-pins-default { - pinctrl-single,pins = < - AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ - AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ - AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */ - AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */ - AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */ - AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */ - AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */ - AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */ - AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */ - AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */ - AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */ - AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ - >; - }; - - main_mmc1_pins_default: main-mmc1-pins-default { - pinctrl-single,pins = < - AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ - AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ - AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */ - AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */ - AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */ - AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */ - AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */ - AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */ - >; - }; - - usb1_pins_default: usb1-pins-default { - pinctrl-single,pins = < - AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ - >; - }; -}; - -&main_pmx1 { - main_i2c0_pins_default: main-i2c0-pins-default { - pinctrl-single,pins = < - AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */ - AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */ - >; - }; - - main_i2c1_pins_default: main-i2c1-pins-default { - pinctrl-single,pins = < - AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */ - AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */ - >; - }; - - ecap0_pins_default: ecap0-pins-default { - pinctrl-single,pins = < - AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */ - >; - }; -}; - -&wkup_uart0 { - /* Wakeup UART is used by System firmware */ - status = "disabled"; -}; - -&main_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; - power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; -}; - -&wkup_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - pca9554: gpio@39 { - compatible = "nxp,pca9554"; - reg = <0x39>; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_pca554_default>; - interrupt-parent = <&wkup_gpio0>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&main_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - pca9555: gpio@21 { - compatible = "nxp,pca9555"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&main_i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; - - ov5640: camera@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - - clocks = <&clk_ov5640_fixed>; - clock-names = "xclk"; - - port { - csi2_cam0: endpoint { - remote-endpoint = <&csi2_phy0>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - -}; - -&main_i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c2_pins_default>; - clock-frequency = <400000>; -}; - -&ecap0 { - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins_default>; -}; - -&main_spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_spi0_pins_default>; - #address-cells = <1>; - #size-cells= <0>; - ti,pindir-d0-out-d1-in = <1>; - - flash@0{ - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - spi-max-frequency = <48000000>; - #address-cells = <1>; - #size-cells= <1>; - }; -}; - -&sdhci0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc0_pins_default>; - bus-width = <8>; - non-removable; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -/* - * Because of erratas i2025 and i2026 for silicon revision 1.0, the - * SD card interface might fail. Boards with sr1.0 are recommended to - * disable sdhci1 - */ -&sdhci1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&dwc3_1 { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins_default>; - dr_mode = "otg"; -}; - -&dwc3_0 { - status = "disabled"; -}; - -&usb0_phy { - status = "disabled"; -}; - -&tscadc0 { - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&tscadc1 { - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&serdes0 { - status = "disabled"; -}; - -&serdes1 { - status = "disabled"; -}; - -&pcie0_rc { - status = "disabled"; -}; - -&pcie0_ep { - status = "disabled"; -}; - -&pcie1_rc { - status = "disabled"; -}; - -&pcie1_ep { - status = "disabled"; -}; - -&mailbox0_cluster0 { - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-tx = <1 0 0>; - ti,mbox-rx = <0 0 0>; - }; -}; - -&mailbox0_cluster1 { - interrupts = <432>; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-tx = <1 0 0>; - ti,mbox-rx = <0 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "disabled"; -}; - -&mailbox0_cluster3 { - status = "disabled"; -}; - -&mailbox0_cluster4 { - status = "disabled"; -}; - -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - -&mailbox0_cluster8 { - status = "disabled"; -}; - -&mailbox0_cluster9 { - status = "disabled"; -}; - -&mailbox0_cluster10 { - status = "disabled"; -}; - -&mailbox0_cluster11 { - status = "disabled"; -}; - -&ospi0 { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - - flash@0{ - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <8>; - spi-max-frequency = <40000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <0>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&csi2_0 { - csi2_phy0: endpoint { - remote-endpoint = <&csi2_cam0>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; -}; - -&mcu_cpsw { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; -}; - -&davinci_mdio { - phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = ; - ti,fifo-depth = ; - }; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&phy0>; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am654-industrial-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-am654-industrial-thermal.dtsi deleted file mode 100644 index 9021c7380..000000000 --- a/arch/arm64/boot/dts/ti/k3-am654-industrial-thermal.dtsi +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include - -mpu0_thermal: mpu0-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 0>; - - trips { - mpu0_crit: mpu0-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; - -mpu1_thermal: mpu1-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 1>; - - trips { - mpu1_crit: mpu1-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; - -mcu_thermal: mcu-thermal { - polling-delay-passive = <250>; /* milliseconds */ - polling-delay = <500>; /* milliseconds */ - thermal-sensors = <&wkup_vtm0 2>; - - trips { - mcu_crit: mcu-crit { - temperature = <125000>; /* milliCelsius */ - hysteresis = <2000>; /* milliCelsius */ - type = "critical"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am654.dtsi b/arch/arm64/boot/dts/ti/k3-am654.dtsi deleted file mode 100644 index f0a6541b8..000000000 --- a/arch/arm64/boot/dts/ti/k3-am654.dtsi +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for AM6 SoC family in Quad core configuration - * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include "k3-am65.dtsi" - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu-map { - cluster0: cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - }; - - cluster1: cluster1 { - core0 { - cpu = <&cpu2>; - }; - - core1 { - cpu = <&cpu3>; - }; - }; - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - reg = <0x000>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&L2_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - reg = <0x001>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&L2_0>; - }; - - cpu2: cpu@100 { - compatible = "arm,cortex-a53"; - reg = <0x100>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&L2_1>; - }; - - cpu3: cpu@101 { - compatible = "arm,cortex-a53"; - reg = <0x101>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&L2_1>; - }; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-size = <0x80000>; - cache-line-size = <64>; - cache-sets = <512>; - next-level-cache = <&msmc_l3>; - }; - - L2_1: l2-cache1 { - compatible = "cache"; - cache-level = <2>; - cache-size = <0x80000>; - cache-line-size = <64>; - cache-sets = <512>; - next-level-cache = <&msmc_l3>; - }; - - msmc_l3: l3-cache0 { - compatible = "cache"; - cache-level = <3>; - }; -}; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts deleted file mode 100644 index e8a4143e1..000000000 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ /dev/null @@ -1,215 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-j7200-som-p0.dtsi" -#include -#include - -/ { - chosen { - stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; - }; -}; - -&wkup_pmx0 { - mcu_cpsw_pins_default: mcu-cpsw-pins-default { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ - J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ - J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ - J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ - J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ - J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ - J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ - J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ - J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ - J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ - J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ - J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ - >; - }; - - mcu_mdio_pins_default: mcu-mdio1-pins-default { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ - J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ - >; - }; -}; - -&main_pmx0 { - main_i2c0_pins_default: main-i2c0-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ - J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ - >; - }; - - main_i2c1_pins_default: main-i2c1-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ - J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */ - >; - }; - - main_mmc1_pins_default: main-mmc1-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */ - J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */ - J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ - J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */ - J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */ - J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */ - J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */ - J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ - >; - }; - - main_usbss0_pins_default: main-usbss0-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ - >; - }; -}; - -&wkup_uart0 { - /* Wakeup UART is used by System firmware */ - status = "disabled"; -}; - -&main_uart0 { - /* Shared with ATF on this platform */ - power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; -}; - -&main_uart2 { - /* MAIN UART 2 is used by R5F firmware */ - status = "disabled"; -}; - -&main_uart3 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart4 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart5 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart6 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart7 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart8 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart9 { - /* UART not brought out */ - status = "disabled"; -}; - -&mcu_cpsw { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; -}; - -&davinci_mdio { - phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = ; - ti,fifo-depth = ; - }; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&phy0>; -}; - -&main_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - exp1: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - exp2: gpio@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&main_i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; - - exp4: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&main_sdhci0 { - /* eMMC */ - non-removable; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&main_sdhci1 { - /* SD card */ - pinctrl-0 = <&main_mmc1_pins_default>; - pinctrl-names = "default"; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&serdes_ln_ctrl { - idle-states = , , - , ; -}; - -&usb_serdes_mux { - idle-states = <1>; /* USB0 to SERDES lane 3 */ -}; - -&usbss0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss0_pins_default>; - ti,vbus-divider; - ti,usb2-only; -}; - -&usb0 { - dr_mode = "otg"; - maximum-speed = "high-speed"; -}; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi deleted file mode 100644 index bef47f963..000000000 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ /dev/null @@ -1,455 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J7200 SoC Family Main Domain peripherals - * - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_main { - msmc_ram: sram@70000000 { - compatible = "mmio-sram"; - reg = <0x00 0x70000000 0x00 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x70000000 0x100000>; - - atf-sram@0 { - reg = <0x00 0x20000>; - }; - }; - - scm_conf: scm-conf@100000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00 0x00100000 0x00 0x1c000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x00100000 0x1c000>; - - serdes_ln_ctrl: mux-controller@4080 { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ - <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ - }; - - usb_serdes_mux: mux-controller@4000 { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ - }; - }; - - gic500: interrupt-controller@1800000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>, /* GICR */ - <0x00 0x6f000000 0x00 0x2000>, /* GICC */ - <0x00 0x6f010000 0x00 0x1000>, /* GICH */ - <0x00 0x6f020000 0x00 0x2000>; /* GICV */ - - /* vcpumntirq: virtual CPU interface maintenance interrupt */ - interrupts = ; - - gic_its: msi-controller@1820000 { - compatible = "arm,gic-v3-its"; - reg = <0x00 0x01820000 0x00 0x10000>; - socionext,synquacer-pre-its = <0x1000000 0x400000>; - msi-controller; - #msi-cells = <1>; - }; - }; - - main_gpio_intr: interrupt-controller0 { - compatible = "ti,sci-intr"; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <131>; - ti,interrupt-ranges = <8 392 56>; - }; - - main_navss: bus@30000000 { - compatible = "simple-mfd"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; - ti,sci-dev-id = <199>; - dma-coherent; - dma-ranges; - - main_navss_intr: interrupt-controller1 { - compatible = "ti,sci-intr"; - ti,intr-trigger-type = <4>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <213>; - ti,interrupt-ranges = <0 64 64>, - <64 448 64>, - <128 672 64>; - }; - - main_udmass_inta: msi-controller@33d00000 { - compatible = "ti,sci-inta"; - reg = <0x00 0x33d00000 0x00 0x100000>; - interrupt-controller; - #interrupt-cells = <0>; - interrupt-parent = <&main_navss_intr>; - msi-controller; - ti,sci = <&dmsc>; - ti,sci-dev-id = <209>; - ti,interrupt-ranges = <0 0 256>; - }; - - secure_proxy_main: mailbox@32c00000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x32c00000 0x00 0x100000>, - <0x00 0x32400000 0x00 0x100000>, - <0x00 0x32800000 0x00 0x100000>; - interrupt-names = "rx_011"; - interrupts = ; - }; - - main_ringacc: ringacc@3c000000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x00 0x3c000000 0x00 0x400000>, - <0x00 0x38000000 0x00 0x400000>, - <0x00 0x31120000 0x00 0x100>, - <0x00 0x33000000 0x00 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; - ti,num-rings = <1024>; - ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,sci = <&dmsc>; - ti,sci-dev-id = <211>; - msi-parent = <&main_udmass_inta>; - }; - - main_udmap: dma-controller@31150000 { - compatible = "ti,j721e-navss-main-udmap"; - reg = <0x00 0x31150000 0x00 0x100>, - <0x00 0x34000000 0x00 0x100000>, - <0x00 0x35000000 0x00 0x100000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <212>; - ti,ringacc = <&main_ringacc>; - - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>, /* TX_HCHAN */ - <0x10>; /* TX_UHCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>, /* RX_HCHAN */ - <0x0c>; /* RX_UHCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - - cpts@310d0000 { - compatible = "ti,j721e-cpts"; - reg = <0x00 0x310d0000 0x00 0x400>; - reg-names = "cpts"; - clocks = <&k3_clks 201 1>; - clock-names = "cpts"; - interrupts-extended = <&main_navss_intr 391>; - interrupt-names = "cpts"; - ti,cpts-periodic-outputs = <6>; - ti,cpts-ext-ts-inputs = <8>; - }; - }; - - main_pmx0: pinctrl@11c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x11c000 0x00 0x2b4>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - main_uart0: serial@2800000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02800000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 146 2>; - clock-names = "fclk"; - }; - - main_uart1: serial@2810000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02810000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 278 2>; - clock-names = "fclk"; - }; - - main_uart2: serial@2820000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02820000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 279 2>; - clock-names = "fclk"; - }; - - main_uart3: serial@2830000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02830000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 280 2>; - clock-names = "fclk"; - }; - - main_uart4: serial@2840000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02840000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 281 2>; - clock-names = "fclk"; - }; - - main_uart5: serial@2850000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02850000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 282 2>; - clock-names = "fclk"; - }; - - main_uart6: serial@2860000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02860000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 283 2>; - clock-names = "fclk"; - }; - - main_uart7: serial@2870000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02870000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 284 2>; - clock-names = "fclk"; - }; - - main_uart8: serial@2880000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02880000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 285 2>; - clock-names = "fclk"; - }; - - main_uart9: serial@2890000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02890000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 286 2>; - clock-names = "fclk"; - }; - - main_i2c0: i2c@2000000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2000000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 187 1>; - power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; - }; - - main_i2c1: i2c@2010000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2010000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 188 1>; - power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c2: i2c@2020000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2020000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 189 1>; - power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c3: i2c@2030000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2030000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 190 1>; - power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c4: i2c@2040000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2040000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 191 1>; - power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c5: i2c@2050000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2050000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 192 1>; - power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c6: i2c@2060000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x2060000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 193 1>; - power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; - }; - - main_sdhci0: mmc@4f80000 { - compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; - reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; - interrupts = ; - power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&k3_clks 91 3>, <&k3_clks 91 0>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-ddr52 = <0x6>; - ti,otap-del-sel-hs200 = <0x8>; - ti,otap-del-sel-hs400 = <0x0>; - ti,strobe-sel = <0x77>; - ti,trm-icp = <0x8>; - bus-width = <8>; - mmc-ddr-1_8v; - dma-coherent; - }; - - main_sdhci1: mmc@4fb0000 { - compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; - reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; - interrupts = ; - power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&k3_clks 92 2>, <&k3_clks 92 1>; - ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0xf>; - ti,otap-del-sel-sdr25 = <0xf>; - ti,otap-del-sel-sdr50 = <0xc>; - ti,otap-del-sel-sdr104 = <0x5>; - ti,otap-del-sel-ddr50 = <0xc>; - no-1-8-v; - dma-coherent; - }; - - usbss0: cdns-usb@4104000 { - compatible = "ti,j721e-usb"; - reg = <0x00 0x4104000 0x00 0x100>; - dma-coherent; - power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; - clock-names = "ref", "lpm"; - assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ - assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ - #address-cells = <2>; - #size-cells = <2>; - ranges; - - usb0: usb@6000000 { - compatible = "cdns,usb3"; - reg = <0x00 0x6000000 0x00 0x10000>, - <0x00 0x6010000 0x00 0x10000>, - <0x00 0x6020000 0x00 0x10000>; - reg-names = "otg", "xhci", "dev"; - interrupts = , /* irq.0 */ - , /* irq.6 */ - ; /* otgirq.0 */ - interrupt-names = "host", - "peripheral", - "otg"; - maximum-speed = "super-speed"; - dr_mode = "otg"; - cdns,phyrst-a-enable; - }; - }; -}; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi deleted file mode 100644 index eb2a78a53..000000000 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ /dev/null @@ -1,273 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals - * - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_mcu_wakeup { - dmsc: dmsc@44083000 { - compatible = "ti,k2g-sci"; - ti,host-id = <12>; - - mbox-names = "rx", "tx"; - - mboxes= <&secure_proxy_main 11>, - <&secure_proxy_main 13>; - - reg-names = "debug_messages"; - reg = <0x00 0x44083000 0x00 0x1000>; - - k3_pds: power-controller { - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <2>; - }; - - k3_clks: clocks { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; - - k3_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; - }; - - mcu_conf: syscon@40f00000 { - compatible = "syscon", "simple-mfd"; - reg = <0x00 0x40f00000 0x00 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x40f00000 0x20000>; - - phy_gmii_sel: phy@4040 { - compatible = "ti,am654-phy-gmii-sel"; - reg = <0x4040 0x4>; - #phy-cells = <1>; - }; - }; - - chipid@43000014 { - compatible = "ti,am654-chipid"; - reg = <0x00 0x43000014 0x00 0x4>; - }; - - wkup_pmx0: pinctrl@4301c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x178>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - mcu_ram: sram@41c00000 { - compatible = "mmio-sram"; - reg = <0x00 0x41c00000 0x00 0x100000>; - ranges = <0x00 0x00 0x41c00000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - wkup_uart0: serial@42300000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x42300000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 287 2>; - clock-names = "fclk"; - }; - - mcu_uart0: serial@40a00000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x40a00000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <96000000>; - current-speed = <115200>; - power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 149 2>; - clock-names = "fclk"; - }; - - wkup_gpio_intr: interrupt-controller2 { - compatible = "ti,sci-intr"; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <137>; - ti,interrupt-ranges = <16 960 16>; - }; - - mcu_navss: bus@28380000 { - compatible = "simple-mfd"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; - dma-coherent; - dma-ranges; - ti,sci-dev-id = <232>; - - mcu_ringacc: ringacc@2b800000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x00 0x2b800000 0x00 0x400000>, - <0x00 0x2b000000 0x00 0x400000>, - <0x00 0x28590000 0x00 0x100>, - <0x00 0x2a500000 0x00 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; - ti,num-rings = <286>; - ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,sci = <&dmsc>; - ti,sci-dev-id = <235>; - msi-parent = <&main_udmass_inta>; - }; - - mcu_udmap: dma-controller@285c0000 { - compatible = "ti,j721e-navss-mcu-udmap"; - reg = <0x00 0x285c0000 0x00 0x100>, - <0x00 0x2a800000 0x00 0x40000>, - <0x00 0x2aa00000 0x00 0x40000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <236>; - ti,ringacc = <&mcu_ringacc>; - - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>; /* TX_HCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>; /* RX_HCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - }; - - mcu_cpsw: ethernet@46000000 { - compatible = "ti,j721e-cpsw-nuss"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x00 0x46000000 0x00 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; - dma-coherent; - clocks = <&k3_clks 18 21>; - clock-names = "fck"; - power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&mcu_udmap 0xf000>, - <&mcu_udmap 0xf001>, - <&mcu_udmap 0xf002>, - <&mcu_udmap 0xf003>, - <&mcu_udmap 0xf004>, - <&mcu_udmap 0xf005>, - <&mcu_udmap 0xf006>, - <&mcu_udmap 0xf007>, - <&mcu_udmap 0x7000>; - dma-names = "tx0", "tx1", "tx2", "tx3", - "tx4", "tx5", "tx6", "tx7", - "rx"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - cpsw_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - ti,syscon-efuse = <&mcu_conf 0x200>; - phys = <&phy_gmii_sel 1>; - }; - }; - - davinci_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x00 0xf00 0x00 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 18 21>; - clock-names = "fck"; - bus_freq = <1000000>; - }; - - cpts@3d000 { - compatible = "ti,am65-cpts"; - reg = <0x00 0x3d000 0x00 0x400>; - clocks = <&k3_clks 18 2>; - clock-names = "cpts"; - interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; - - mcu_i2c0: i2c@40b00000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x40b00000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 194 1>; - power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; - }; - - mcu_i2c1: i2c@40b10000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x40b10000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 195 1>; - power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; - }; - - wkup_i2c0: i2c@42120000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x00 0x42120000 0x00 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 197 1>; - power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; - }; - - fss: syscon@47000000 { - compatible = "syscon", "simple-mfd"; - reg = <0x00 0x47000000 0x00 0x100>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hbmc_mux: hbmc-mux { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4 0x2>; /* HBMC select */ - }; - - hbmc: hyperbus@47034000 { - compatible = "ti,am654-hbmc"; - reg = <0x00 0x47034000 0x00 0x100>, - <0x05 0x00000000 0x01 0x0000000>; - power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 102 0>; - assigned-clocks = <&k3_clks 102 5>; - assigned-clock-rates = <333333333>; - #address-cells = <2>; - #size-cells = <1>; - mux-controls = <&hbmc_mux 0>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi deleted file mode 100644 index 6a98ba499..000000000 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-j7200.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - /* 4G RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x00 0x80000000>; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - alignment = <0x1000>; - no-map; - }; - }; -}; - -&wkup_pmx0 { - mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ - J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ - J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ - J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ - J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ - J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ - J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ - J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ - J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ - J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ - J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ - J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ - J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ - >; - }; -}; - -&hbmc { - /* OSPI and HBMC are muxed inside FSS, Bootloader will enable - * appropriate node based on board detection - */ - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; - ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ - <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ - - flash@0,0 { - compatible = "cypress,hyperflash", "cfi-flash"; - reg = <0x00 0x00 0x4000000>; - }; -}; diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi deleted file mode 100644 index 59f5113e6..000000000 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ /dev/null @@ -1,173 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J7200 SoC Family - * - * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include -#include -#include -#include - -/ { - model = "Texas Instruments K3 J7200 SoC"; - compatible = "ti,j7200"; - interrupt-parent = <&gic500>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - serial5 = &main_uart3; - serial6 = &main_uart4; - serial7 = &main_uart5; - serial8 = &main_uart6; - serial9 = &main_uart7; - serial10 = &main_uart8; - serial11 = &main_uart9; - }; - - chosen { }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu-map { - cluster0: cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - }; - - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a72"; - reg = <0x000>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a72"; - reg = <0x001>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xc000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - next-level-cache = <&msmc_l3>; - }; - - msmc_l3: l3-cache0 { - compatible = "cache"; - cache-level = <3>; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - psci: psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - }; - - a72_timer0: timer-cl0-cpu0 { - compatible = "arm,armv8-timer"; - interrupts = , /* cntpsirq */ - , /* cntpnsirq */ - , /* cntvirq */ - ; /* cnthpirq */ - }; - - pmu: pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - cbass_main: bus@100000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ - <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ - <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ - <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ - <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ - <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ - <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ - <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ - <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ - - /* MCUSS_WKUP Range */ - <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; - - cbass_mcu_wakeup: bus@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */ - }; - }; -}; - -/* Now include the peripherals for each bus segments */ -#include "k3-j7200-main.dtsi" -#include "k3-j7200-mcu-wakeup.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts deleted file mode 100644 index 479abff9c..000000000 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ /dev/null @@ -1,645 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-j721e-som-p0.dtsi" -#include -#include -#include - -/ { - chosen { - stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>; - - sw10: sw10 { - label = "GPIO Key USER1"; - linux,code = ; - gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>; - }; - - sw11: sw11 { - label = "GPIO Key USER2"; - linux,code = ; - gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>; - }; - }; - - evm_12v0: fixedregulator-evm12v0 { - /* main supply */ - compatible = "regulator-fixed"; - regulator-name = "evm_12v0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_3v3: fixedregulator-vsys3v3 { - /* Output of LMS140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - vsys_5v0: fixedregulator-vsys5v0 { - /* Output of LM5140 */ - compatible = "regulator-fixed"; - regulator-name = "vsys_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&evm_12v0>; - regulator-always-on; - regulator-boot-on; - }; - - sound0: sound@0 { - compatible = "ti,j721e-cpb-audio"; - model = "j721e-cpb"; - - ti,cpb-mcasp = <&mcasp10>; - ti,cpb-codec = <&pcm3168a_1>; - - clocks = <&k3_clks 184 1>, - <&k3_clks 184 2>, <&k3_clks 184 4>, - <&k3_clks 157 371>, - <&k3_clks 157 400>, <&k3_clks 157 401>; - clock-names = "cpb-mcasp-auxclk", - "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100", - "cpb-codec-scki", - "cpb-codec-scki-48000", "cpb-codec-scki-44100"; - }; -}; - -&main_pmx0 { - sw10_button_pins_default: sw10-button-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ - >; - }; - - main_mmc1_pins_default: main-mmc1-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ - J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ - J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ - J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ - J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ - J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ - J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ - J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ - J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ - >; - }; - - main_usbss0_pins_default: main-usbss0-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ - J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ - >; - }; - - main_usbss1_pins_default: main-usbss1-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ - >; - }; - - main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ - >; - }; - - main_i2c0_pins_default: main-i2c0-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ - J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ - >; - }; - - main_i2c1_pins_default: main-i2c1-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ - J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ - >; - }; - - main_i2c3_pins_default: main-i2c3-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ - J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ - >; - }; - - main_i2c6_pins_default: main-i2c6-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ - J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ - >; - }; - - mcasp10_pins_default: mcasp10-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */ - J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */ - J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */ - J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */ - J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */ - J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */ - J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */ - J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */ - J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */ - >; - }; - - audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */ - >; - }; -}; - -&wkup_pmx0 { - sw11_button_pins_default: sw11-button-pins-default { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ - >; - }; - - mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */ - J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */ - J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */ - J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */ - J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */ - J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */ - J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */ - J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ - >; - }; - - mcu_cpsw_pins_default: mcu-cpsw-pins-default { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ - J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ - J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ - J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ - J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ - J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ - J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ - J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ - J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ - J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ - J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ - J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ - >; - }; - - mcu_mdio_pins_default: mcu-mdio1-pins-default { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */ - J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */ - >; - }; -}; - -&wkup_uart0 { - /* Wakeup UART is used by System firmware */ - status = "disabled"; -}; - -&main_uart0 { - power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; -}; - -&main_uart3 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart5 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart6 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart7 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart8 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart9 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_gpio2 { - status = "disabled"; -}; - -&main_gpio3 { - status = "disabled"; -}; - -&main_gpio4 { - status = "disabled"; -}; - -&main_gpio5 { - status = "disabled"; -}; - -&main_gpio6 { - status = "disabled"; -}; - -&main_gpio7 { - status = "disabled"; -}; - -&wkup_gpio1 { - status = "disabled"; -}; - -&main_sdhci0 { - /* eMMC */ - non-removable; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&main_sdhci1 { - /* SD/MMC */ - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - -&main_sdhci2 { - /* Unused */ - status = "disabled"; -}; - -&usb_serdes_mux { - idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ -}; - -&serdes_ln_ctrl { - idle-states = , , - , , - , , - , , - , , - , ; -}; - -&serdes_wiz3 { - typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; - typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ -}; - -&serdes3 { - serdes3_usb_link: link@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = ; - resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; - }; -}; - -&usbss0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss0_pins_default>; - ti,vbus-divider; -}; - -&usb0 { - dr_mode = "otg"; - maximum-speed = "super-speed"; - phys = <&serdes3_usb_link>; - phy-names = "cdns3,usb3-phy"; -}; - -&usbss1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_usbss1_pins_default>; - ti,usb2-only; -}; - -&usb1 { - dr_mode = "host"; - maximum-speed = "high-speed"; -}; - -&ospi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; - - flash@0{ - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - spi-max-frequency = <40000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <2>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&tscadc0 { - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&tscadc1 { - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&main_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - - exp1: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - exp2: gpio@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - - p09-hog { - /* P11 - MCASP/TRACE_MUX_S0 */ - gpio-hog; - gpios = <9 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "MCASP/TRACE_MUX_S0"; - }; - - p10-hog { - /* P12 - MCASP/TRACE_MUX_S1 */ - gpio-hog; - gpios = <10 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "MCASP/TRACE_MUX_S1"; - }; - }; -}; - -&main_i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; - - exp4: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_exp4_pins_default>; - interrupt-parent = <&main_gpio1>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - -&k3_clks { - /* Confiure AUDIO_EXT_REFCLK2 pin as output */ - pinctrl-names = "default"; - pinctrl-0 = <&audi_ext_refclk2_pins_default>; -}; - -&main_i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c3_pins_default>; - clock-frequency = <400000>; - - exp3: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - pcm3168a_1: audio-codec@44 { - compatible = "ti,pcm3168a"; - reg = <0x44>; - - #sound-dai-cells = <1>; - - reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>; - - /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */ - clocks = <&k3_clks 157 371>; - clock-names = "scki"; - - /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */ - assigned-clocks = <&k3_clks 157 371>; - assigned-clock-parents = <&k3_clks 157 400>; - assigned-clock-rates = <24576000>; /* for 48KHz */ - - VDD1-supply = <&vsys_3v3>; - VDD2-supply = <&vsys_3v3>; - VCCAD1-supply = <&vsys_5v0>; - VCCAD2-supply = <&vsys_5v0>; - VCCDA1-supply = <&vsys_5v0>; - VCCDA2-supply = <&vsys_5v0>; - }; -}; - -&main_i2c6 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c6_pins_default>; - clock-frequency = <400000>; - - exp5: gpio@20 { - compatible = "ti,tca6408"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&mcu_cpsw { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; -}; - -&davinci_mdio { - phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = ; - ti,fifo-depth = ; - }; -}; - -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&phy0>; -}; - -&dss { - /* - * These clock assignments are chosen to enable the following outputs: - * - * VP0 - DisplayPort SST - * VP1 - DPI0 - * VP2 - DSI - * VP3 - DPI1 - */ - - assigned-clocks = <&k3_clks 152 1>, - <&k3_clks 152 4>, - <&k3_clks 152 9>, - <&k3_clks 152 13>; - assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ - <&k3_clks 152 6>, /* PLL19_HSDIV0 */ - <&k3_clks 152 11>, /* PLL18_HSDIV0 */ - <&k3_clks 152 18>; /* PLL23_HSDIV0 */ -}; - -&mcasp10 { - #sound-dai-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&mcasp10_pins_default>; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - auxclk-fs-ratio = <256>; - - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 1 1 1 - 2 2 2 0 - >; - tx-num-evt = <0>; - rx-num-evt = <0>; - - status = "okay"; -}; - -&cmn_refclk1 { - clock-frequency = <100000000>; -}; - -&serdes0 { - serdes0_pcie_link: link@0 { - reg = <0>; - cdns,num-lanes = <1>; - #phy-cells = <0>; - cdns,phy-type = ; - resets = <&serdes_wiz0 1>; - }; -}; - -&serdes1 { - serdes1_pcie_link: link@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = ; - resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; - }; -}; - -&serdes2 { - serdes2_pcie_link: link@0 { - reg = <0>; - cdns,num-lanes = <2>; - #phy-cells = <0>; - cdns,phy-type = ; - resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>; - }; -}; - -&pcie0_rc { - reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; -}; - -&pcie1_rc { - reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; - phys = <&serdes1_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&pcie2_rc { - reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; - phys = <&serdes2_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&pcie0_ep { - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; - status = "disabled"; -}; - -&pcie1_ep { - phys = <&serdes1_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; - status = "disabled"; -}; - -&pcie2_ep { - phys = <&serdes2_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; - status = "disabled"; -}; - -&pcie3_rc { - status = "disabled"; -}; - -&pcie3_ep { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi deleted file mode 100644 index 0350ddfe2..000000000 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ /dev/null @@ -1,1626 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721E SoC Family Main Domain peripherals - * - * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ - */ -#include -#include -#include - -/ { - cmn_refclk: clock-cmnrefclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - cmn_refclk1: clock-cmnrefclk1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; -}; - -&cbass_main { - msmc_ram: sram@70000000 { - compatible = "mmio-sram"; - reg = <0x0 0x70000000 0x0 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x70000000 0x800000>; - - atf-sram@0 { - reg = <0x0 0x20000>; - }; - }; - - scm_conf: scm-conf@100000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x00100000 0x1c000>; - - pcie0_ctrl: syscon@4070 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00004070 0x4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x4070 0x4070 0x4>; - }; - - pcie1_ctrl: syscon@4074 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00004074 0x4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x4074 0x4074 0x4>; - }; - - pcie2_ctrl: syscon@4078 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00004078 0x4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x4078 0x4078 0x4>; - }; - - pcie3_ctrl: syscon@407c { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x0000407c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x407c 0x407c 0x4>; - }; - - serdes_ln_ctrl: mux@4080 { - compatible = "mmio-mux"; - reg = <0x00004080 0x50>; - #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ - <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ - <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ - <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ - <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; - /* SERDES4 lane0/1/2/3 select */ - idle-states = , , - , , - , , - , , - , , - , ; - }; - - usb_serdes_mux: mux-controller@4000 { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ - <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ - }; - }; - - gic500: interrupt-controller@1800000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>, /* GICR */ - <0x00 0x6f000000 0x00 0x2000>, /* GICC */ - <0x00 0x6f010000 0x00 0x1000>, /* GICH */ - <0x00 0x6f020000 0x00 0x2000>; /* GICV */ - - /* vcpumntirq: virtual CPU interface maintenance interrupt */ - interrupts = ; - - gic_its: msi-controller@1820000 { - compatible = "arm,gic-v3-its"; - reg = <0x00 0x01820000 0x00 0x10000>; - socionext,synquacer-pre-its = <0x1000000 0x400000>; - msi-controller; - #msi-cells = <1>; - }; - }; - - main_gpio_intr: interrupt-controller0 { - compatible = "ti,sci-intr"; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <131>; - ti,interrupt-ranges = <8 392 56>; - }; - - main-navss { - compatible = "simple-mfd"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-coherent; - dma-ranges; - - ti,sci-dev-id = <199>; - - main_navss_intr: interrupt-controller1 { - compatible = "ti,sci-intr"; - ti,intr-trigger-type = <4>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <213>; - ti,interrupt-ranges = <0 64 64>, - <64 448 64>, - <128 672 64>; - }; - - main_udmass_inta: interrupt-controller@33d00000 { - compatible = "ti,sci-inta"; - reg = <0x0 0x33d00000 0x0 0x100000>; - interrupt-controller; - interrupt-parent = <&main_navss_intr>; - msi-controller; - ti,sci = <&dmsc>; - ti,sci-dev-id = <209>; - ti,interrupt-ranges = <0 0 256>; - }; - - secure_proxy_main: mailbox@32c00000 { - compatible = "ti,am654-secure-proxy"; - #mbox-cells = <1>; - reg-names = "target_data", "rt", "scfg"; - reg = <0x00 0x32c00000 0x00 0x100000>, - <0x00 0x32400000 0x00 0x100000>, - <0x00 0x32800000 0x00 0x100000>; - interrupt-names = "rx_011"; - interrupts = ; - }; - - smmu0: iommu@36600000 { - compatible = "arm,smmu-v3"; - reg = <0x0 0x36600000 0x0 0x100000>; - interrupt-parent = <&gic500>; - interrupts = , - ; - interrupt-names = "eventq", "gerror"; - #iommu-cells = <1>; - }; - - hwspinlock: spinlock@30e00000 { - compatible = "ti,am654-hwspinlock"; - reg = <0x00 0x30e00000 0x00 0x1000>; - #hwlock-cells = <1>; - }; - - mailbox0_cluster0: mailbox@31f80000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f80000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - mailbox0_cluster1: mailbox@31f81000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f81000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - mailbox0_cluster2: mailbox@31f82000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f82000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - mailbox0_cluster3: mailbox@31f83000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f83000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - mailbox0_cluster4: mailbox@31f84000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f84000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - mailbox0_cluster5: mailbox@31f85000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f85000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - mailbox0_cluster6: mailbox@31f86000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f86000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - mailbox0_cluster7: mailbox@31f87000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f87000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - mailbox0_cluster8: mailbox@31f88000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f88000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - mailbox0_cluster9: mailbox@31f89000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f89000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - mailbox0_cluster10: mailbox@31f8a000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8a000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - mailbox0_cluster11: mailbox@31f8b000 { - compatible = "ti,am654-mailbox"; - reg = <0x00 0x31f8b000 0x00 0x200>; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <16>; - interrupt-parent = <&main_navss_intr>; - }; - - main_ringacc: ringacc@3c000000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x3c000000 0x0 0x400000>, - <0x0 0x38000000 0x0 0x400000>, - <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; - ti,num-rings = <1024>; - ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,sci = <&dmsc>; - ti,sci-dev-id = <211>; - msi-parent = <&main_udmass_inta>; - }; - - main_udmap: dma-controller@31150000 { - compatible = "ti,j721e-navss-main-udmap"; - reg = <0x0 0x31150000 0x0 0x100>, - <0x0 0x34000000 0x0 0x100000>, - <0x0 0x35000000 0x0 0x100000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <212>; - ti,ringacc = <&main_ringacc>; - - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>, /* TX_HCHAN */ - <0x10>; /* TX_UHCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>, /* RX_HCHAN */ - <0x0c>; /* RX_UHCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - - cpts@310d0000 { - compatible = "ti,j721e-cpts"; - reg = <0x0 0x310d0000 0x0 0x400>; - reg-names = "cpts"; - clocks = <&k3_clks 201 1>; - clock-names = "cpts"; - interrupts-extended = <&main_navss_intr 391>; - interrupt-names = "cpts"; - ti,cpts-periodic-outputs = <6>; - ti,cpts-ext-ts-inputs = <8>; - }; - }; - - main_crypto: crypto@4e00000 { - compatible = "ti,j721e-sa2ul"; - reg = <0x0 0x4e00000 0x0 0x1200>; - power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; - - status = "okay"; - - dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, - <&main_udmap 0x4001>; - dma-names = "tx", "rx1", "rx2"; - dma-coherent; - - rng: rng@4e10000 { - compatible = "inside-secure,safexcel-eip76"; - reg = <0x0 0x4e10000 0x0 0x7d>; - interrupts = ; - clocks = <&k3_clks 264 1>; - }; - }; - - main_pmx0: pinctrl@11c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x0 0x11c000 0x0 0x2b4>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - serdes_wiz0: wiz@5000000 { - compatible = "ti,j721e-wiz-16g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; - assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; - num-lanes = <2>; - #reset-cells = <1>; - ranges = <0x5000000 0x0 0x5000000 0x10000>; - - wiz0_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 292 11>, <&cmn_refclk>; - #clock-cells = <0>; - assigned-clocks = <&wiz0_pll0_refclk>; - assigned-clock-parents = <&k3_clks 292 11>; - }; - - wiz0_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 292 0>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz0_pll1_refclk>; - assigned-clock-parents = <&k3_clks 292 0>; - }; - - wiz0_refclk_dig: refclk-dig { - clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz0_refclk_dig>; - assigned-clock-parents = <&k3_clks 292 11>; - }; - - wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { - clocks = <&wiz0_refclk_dig>; - #clock-cells = <0>; - }; - - wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { - clocks = <&wiz0_pll1_refclk>; - #clock-cells = <0>; - }; - - serdes0: serdes@5000000 { - compatible = "ti,sierra-phy-t0"; - reg-names = "serdes"; - reg = <0x5000000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&serdes_wiz0 0>; - reset-names = "sierra_reset"; - clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; - }; - }; - - serdes_wiz1: wiz@5010000 { - compatible = "ti,j721e-wiz-16g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; - assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; - num-lanes = <2>; - #reset-cells = <1>; - ranges = <0x5010000 0x0 0x5010000 0x10000>; - - wiz1_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 293 13>, <&cmn_refclk>; - #clock-cells = <0>; - assigned-clocks = <&wiz1_pll0_refclk>; - assigned-clock-parents = <&k3_clks 293 13>; - }; - - wiz1_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 293 0>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz1_pll1_refclk>; - assigned-clock-parents = <&k3_clks 293 0>; - }; - - wiz1_refclk_dig: refclk-dig { - clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz1_refclk_dig>; - assigned-clock-parents = <&k3_clks 293 13>; - }; - - wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{ - clocks = <&wiz1_refclk_dig>; - #clock-cells = <0>; - }; - - wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { - clocks = <&wiz1_pll1_refclk>; - #clock-cells = <0>; - }; - - serdes1: serdes@5010000 { - compatible = "ti,sierra-phy-t0"; - reg-names = "serdes"; - reg = <0x5010000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&serdes_wiz1 0>; - reset-names = "sierra_reset"; - clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; - }; - }; - - serdes_wiz2: wiz@5020000 { - compatible = "ti,j721e-wiz-16g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; - assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; - num-lanes = <2>; - #reset-cells = <1>; - ranges = <0x5020000 0x0 0x5020000 0x10000>; - - wiz2_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 294 11>, <&cmn_refclk>; - #clock-cells = <0>; - assigned-clocks = <&wiz2_pll0_refclk>; - assigned-clock-parents = <&k3_clks 294 11>; - }; - - wiz2_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 294 0>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz2_pll1_refclk>; - assigned-clock-parents = <&k3_clks 294 0>; - }; - - wiz2_refclk_dig: refclk-dig { - clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz2_refclk_dig>; - assigned-clock-parents = <&k3_clks 294 11>; - }; - - wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { - clocks = <&wiz2_refclk_dig>; - #clock-cells = <0>; - }; - - wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { - clocks = <&wiz2_pll1_refclk>; - #clock-cells = <0>; - }; - - serdes2: serdes@5020000 { - compatible = "ti,sierra-phy-t0"; - reg-names = "serdes"; - reg = <0x5020000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&serdes_wiz2 0>; - reset-names = "sierra_reset"; - clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; - }; - }; - - serdes_wiz3: wiz@5030000 { - compatible = "ti,j721e-wiz-16g"; - #address-cells = <1>; - #size-cells = <1>; - power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; - clock-names = "fck", "core_ref_clk", "ext_ref_clk"; - assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; - assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; - num-lanes = <2>; - #reset-cells = <1>; - ranges = <0x5030000 0x0 0x5030000 0x10000>; - - wiz3_pll0_refclk: pll0-refclk { - clocks = <&k3_clks 295 9>, <&cmn_refclk>; - #clock-cells = <0>; - assigned-clocks = <&wiz3_pll0_refclk>; - assigned-clock-parents = <&k3_clks 295 9>; - }; - - wiz3_pll1_refclk: pll1-refclk { - clocks = <&k3_clks 295 0>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz3_pll1_refclk>; - assigned-clock-parents = <&k3_clks 295 0>; - }; - - wiz3_refclk_dig: refclk-dig { - clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; - #clock-cells = <0>; - assigned-clocks = <&wiz3_refclk_dig>; - assigned-clock-parents = <&k3_clks 295 9>; - }; - - wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { - clocks = <&wiz3_refclk_dig>; - #clock-cells = <0>; - }; - - wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { - clocks = <&wiz3_pll1_refclk>; - #clock-cells = <0>; - }; - - serdes3: serdes@5030000 { - compatible = "ti,sierra-phy-t0"; - reg-names = "serdes"; - reg = <0x5030000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - resets = <&serdes_wiz3 0>; - reset-names = "sierra_reset"; - clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>; - clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; - }; - }; - - pcie0_rc: pcie@2900000 { - compatible = "ti,j721e-pcie-host"; - reg = <0x00 0x02900000 0x00 0x1000>, - <0x00 0x02907000 0x00 0x400>, - <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x10000000 0x00 0x00001000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = ; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&pcie0_ctrl>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 239 1>; - clock-names = "fck"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - vendor-id = <0x104c>; - device-id = <0xb00d>; - msi-map = <0x0 &gic_its 0x0 0x10000>; - dma-coherent; - ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, - <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - }; - - pcie0_ep: pcie-ep@2900000 { - compatible = "ti,j721e-pcie-ep"; - reg = <0x00 0x02900000 0x00 0x1000>, - <0x00 0x02907000 0x00 0x400>, - <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x10000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&pcie0_ctrl>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 239 1>; - clock-names = "fck"; - cdns,max-outbound-regions = <16>; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; - }; - - pcie1_rc: pcie@2910000 { - compatible = "ti,j721e-pcie-host"; - reg = <0x00 0x02910000 0x00 0x1000>, - <0x00 0x02917000 0x00 0x400>, - <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x00001000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = ; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&pcie1_ctrl>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 240 1>; - clock-names = "fck"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - vendor-id = <0x104c>; - device-id = <0xb00d>; - msi-map = <0x0 &gic_its 0x10000 0x10000>; - dma-coherent; - ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - }; - - pcie1_ep: pcie-ep@2910000 { - compatible = "ti,j721e-pcie-ep"; - reg = <0x00 0x02910000 0x00 0x1000>, - <0x00 0x02917000 0x00 0x400>, - <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&pcie1_ctrl>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 240 1>; - clock-names = "fck"; - cdns,max-outbound-regions = <16>; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; - }; - - pcie2_rc: pcie@2920000 { - compatible = "ti,j721e-pcie-host"; - reg = <0x00 0x02920000 0x00 0x1000>, - <0x00 0x02927000 0x00 0x400>, - <0x00 0x0e000000 0x00 0x00800000>, - <0x44 0x00000000 0x00 0x00001000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = ; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&pcie2_ctrl>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 241 1>; - clock-names = "fck"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - vendor-id = <0x104c>; - device-id = <0xb00d>; - msi-map = <0x0 &gic_its 0x20000 0x10000>; - dma-coherent; - ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, - <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - }; - - pcie2_ep: pcie-ep@2920000 { - compatible = "ti,j721e-pcie-ep"; - reg = <0x00 0x02920000 0x00 0x1000>, - <0x00 0x02927000 0x00 0x400>, - <0x00 0x0e000000 0x00 0x00800000>, - <0x44 0x00000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&pcie2_ctrl>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 241 1>; - clock-names = "fck"; - cdns,max-outbound-regions = <16>; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; - }; - - pcie3_rc: pcie@2930000 { - compatible = "ti,j721e-pcie-host"; - reg = <0x00 0x02930000 0x00 0x1000>, - <0x00 0x02937000 0x00 0x400>, - <0x00 0x0e800000 0x00 0x00800000>, - <0x44 0x10000000 0x00 0x00001000>; - reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; - interrupt-names = "link_state"; - interrupts = ; - device_type = "pci"; - ti,syscon-pcie-ctrl = <&pcie3_ctrl>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 242 1>; - clock-names = "fck"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xff>; - vendor-id = <0x104c>; - device-id = <0xb00d>; - msi-map = <0x0 &gic_its 0x30000 0x10000>; - dma-coherent; - ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, - <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; - dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - }; - - pcie3_ep: pcie-ep@2930000 { - compatible = "ti,j721e-pcie-ep"; - reg = <0x00 0x02930000 0x00 0x1000>, - <0x00 0x02937000 0x00 0x400>, - <0x00 0x0e800000 0x00 0x00800000>, - <0x44 0x10000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&pcie3_ctrl>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 242 1>; - clock-names = "fck"; - cdns,max-outbound-regions = <16>; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; - #address-cells = <2>; - #size-cells = <2>; - }; - - main_uart0: serial@2800000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02800000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 146 0>; - clock-names = "fclk"; - }; - - main_uart1: serial@2810000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02810000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 278 0>; - clock-names = "fclk"; - }; - - main_uart2: serial@2820000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02820000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 279 0>; - clock-names = "fclk"; - }; - - main_uart3: serial@2830000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02830000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 280 0>; - clock-names = "fclk"; - }; - - main_uart4: serial@2840000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02840000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 281 0>; - clock-names = "fclk"; - }; - - main_uart5: serial@2850000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02850000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 282 0>; - clock-names = "fclk"; - }; - - main_uart6: serial@2860000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02860000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 283 0>; - clock-names = "fclk"; - }; - - main_uart7: serial@2870000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02870000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 284 0>; - clock-names = "fclk"; - }; - - main_uart8: serial@2880000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02880000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 285 0>; - clock-names = "fclk"; - }; - - main_uart9: serial@2890000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x02890000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 286 0>; - clock-names = "fclk"; - }; - - main_gpio0: gpio@600000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00600000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <256>, <257>, <258>, <259>, - <260>, <261>, <262>, <263>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <128>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 105 0>; - clock-names = "gpio"; - }; - - main_gpio1: gpio@601000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00601000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <288>, <289>, <290>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <36>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 106 0>; - clock-names = "gpio"; - }; - - main_gpio2: gpio@610000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00610000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <264>, <265>, <266>, <267>, - <268>, <269>, <270>, <271>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <128>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 107 0>; - clock-names = "gpio"; - }; - - main_gpio3: gpio@611000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00611000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <292>, <293>, <294>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <36>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 108 0>; - clock-names = "gpio"; - }; - - main_gpio4: gpio@620000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00620000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <272>, <273>, <274>, <275>, - <276>, <277>, <278>, <279>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <128>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 109 0>; - clock-names = "gpio"; - }; - - main_gpio5: gpio@621000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00621000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <296>, <297>, <298>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <36>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 110 0>; - clock-names = "gpio"; - }; - - main_gpio6: gpio@630000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00630000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <280>, <281>, <282>, <283>, - <284>, <285>, <286>, <287>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <128>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 111 0>; - clock-names = "gpio"; - }; - - main_gpio7: gpio@631000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x00631000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; - interrupts = <300>, <301>, <302>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <36>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 112 0>; - clock-names = "gpio"; - }; - - main_sdhci0: sdhci@4f80000 { - compatible = "ti,j721e-sdhci-8bit"; - reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; - interrupts = ; - power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&k3_clks 91 1>, <&k3_clks 91 0>; - assigned-clocks = <&k3_clks 91 1>; - assigned-clock-parents = <&k3_clks 91 2>; - bus-width = <8>; - mmc-hs400-1_8v; - mmc-ddr-1_8v; - ti,otap-del-sel = <0x2>; - ti,trm-icp = <0x8>; - ti,strobe-sel = <0x77>; - dma-coherent; - }; - - main_sdhci1: sdhci@4fb0000 { - compatible = "ti,j721e-sdhci-4bit"; - reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; - interrupts = ; - power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&k3_clks 92 0>, <&k3_clks 92 5>; - assigned-clocks = <&k3_clks 92 0>; - assigned-clock-parents = <&k3_clks 92 1>; - ti,otap-del-sel = <0x2>; - ti,trm-icp = <0x8>; - ti,clkbuf-sel = <0x7>; - dma-coherent; - no-1-8-v; - }; - - main_sdhci2: sdhci@4f98000 { - compatible = "ti,j721e-sdhci-4bit"; - reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; - interrupts = ; - power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&k3_clks 93 0>, <&k3_clks 93 5>; - assigned-clocks = <&k3_clks 93 0>; - assigned-clock-parents = <&k3_clks 93 1>; - ti,otap-del-sel = <0x2>; - ti,trm-icp = <0x8>; - ti,clkbuf-sel = <0x7>; - dma-coherent; - no-1-8-v; - }; - - usbss0: cdns-usb@4104000 { - compatible = "ti,j721e-usb"; - reg = <0x00 0x4104000 0x00 0x100>; - dma-coherent; - power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; - clock-names = "ref", "lpm"; - assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ - assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ - #address-cells = <2>; - #size-cells = <2>; - ranges; - - usb0: usb@6000000 { - compatible = "cdns,usb3"; - reg = <0x00 0x6000000 0x00 0x10000>, - <0x00 0x6010000 0x00 0x10000>, - <0x00 0x6020000 0x00 0x10000>; - reg-names = "otg", "xhci", "dev"; - interrupts = , /* irq.0 */ - , /* irq.6 */ - ; /* otgirq.0 */ - interrupt-names = "host", - "peripheral", - "otg"; - maximum-speed = "super-speed"; - dr_mode = "otg"; - }; - }; - - usbss1: cdns-usb@4114000 { - compatible = "ti,j721e-usb"; - reg = <0x00 0x4114000 0x00 0x100>; - dma-coherent; - power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; - clock-names = "ref", "lpm"; - assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ - assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ - #address-cells = <2>; - #size-cells = <2>; - ranges; - - usb1: usb@6400000 { - compatible = "cdns,usb3"; - reg = <0x00 0x6400000 0x00 0x10000>, - <0x00 0x6410000 0x00 0x10000>, - <0x00 0x6420000 0x00 0x10000>; - reg-names = "otg", "xhci", "dev"; - interrupts = , /* irq.0 */ - , /* irq.6 */ - ; /* otgirq.0 */ - interrupt-names = "host", - "peripheral", - "otg"; - maximum-speed = "super-speed"; - dr_mode = "otg"; - }; - }; - - main_i2c0: i2c@2000000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2000000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 187 0>; - power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; - }; - - main_i2c1: i2c@2010000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2010000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 188 0>; - power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c2: i2c@2020000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2020000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 189 0>; - power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c3: i2c@2030000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2030000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 190 0>; - power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c4: i2c@2040000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2040000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 191 0>; - power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c5: i2c@2050000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2050000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 192 0>; - power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; - }; - - main_i2c6: i2c@2060000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x2060000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 193 0>; - power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; - }; - - ufs_wrapper: ufs-wrapper@4e80000 { - compatible = "ti,j721e-ufs"; - reg = <0x0 0x4e80000 0x0 0x100>; - power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 277 1>; - assigned-clocks = <&k3_clks 277 1>; - assigned-clock-parents = <&k3_clks 277 4>; - ranges; - #address-cells = <2>; - #size-cells = <2>; - - ufs@4e84000 { - compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; - reg = <0x0 0x4e84000 0x0 0x10000>; - interrupts = ; - freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; - clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; - clock-names = "core_clk", "phy_clk", "ref_clk"; - dma-coherent; - }; - }; - - dss: dss@4a00000 { - compatible = "ti,j721e-dss"; - reg = - <0x00 0x04a00000 0x00 0x10000>, /* common_m */ - <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ - <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ - <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ - - <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ - <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ - <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ - <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ - - <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ - <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ - <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ - <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ - - <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ - <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ - <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ - <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ - <0x00 0x04af0000 0x00 0x10000>; /* wb */ - - reg-names = "common_m", "common_s0", - "common_s1", "common_s2", - "vidl1", "vidl2","vid1","vid2", - "ovr1", "ovr2", "ovr3", "ovr4", - "vp1", "vp2", "vp3", "vp4", - "wb"; - - clocks = <&k3_clks 152 0>, - <&k3_clks 152 1>, - <&k3_clks 152 4>, - <&k3_clks 152 9>, - <&k3_clks 152 13>; - clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; - - power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; - - interrupts = , - , - , - ; - interrupt-names = "common_m", - "common_s0", - "common_s1", - "common_s2"; - - status = "disabled"; - - dss_ports: ports { - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - mcasp0: mcasp@2b00000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b00000 0x0 0x2000>, - <0x0 0x02b08000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 174 1>; - clock-names = "fck"; - power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp1: mcasp@2b10000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b10000 0x0 0x2000>, - <0x0 0x02b18000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 175 1>; - clock-names = "fck"; - power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp2: mcasp@2b20000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b20000 0x0 0x2000>, - <0x0 0x02b28000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 176 1>; - clock-names = "fck"; - power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp3: mcasp@2b30000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b30000 0x0 0x2000>, - <0x0 0x02b38000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 177 1>; - clock-names = "fck"; - power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp4: mcasp@2b40000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b40000 0x0 0x2000>, - <0x0 0x02b48000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 178 1>; - clock-names = "fck"; - power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp5: mcasp@2b50000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b50000 0x0 0x2000>, - <0x0 0x02b58000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 179 1>; - clock-names = "fck"; - power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp6: mcasp@2b60000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b60000 0x0 0x2000>, - <0x0 0x02b68000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 180 1>; - clock-names = "fck"; - power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp7: mcasp@2b70000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b70000 0x0 0x2000>, - <0x0 0x02b78000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 181 1>; - clock-names = "fck"; - power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp8: mcasp@2b80000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b80000 0x0 0x2000>, - <0x0 0x02b88000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 182 1>; - clock-names = "fck"; - power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp9: mcasp@2b90000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02b90000 0x0 0x2000>, - <0x0 0x02b98000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 183 1>; - clock-names = "fck"; - power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp10: mcasp@2ba0000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02ba0000 0x0 0x2000>, - <0x0 0x02ba8000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 184 1>; - clock-names = "fck"; - power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - mcasp11: mcasp@2bb0000 { - compatible = "ti,am33xx-mcasp-audio"; - reg = <0x0 0x02bb0000 0x0 0x2000>, - <0x0 0x02bb8000 0x0 0x1000>; - reg-names = "mpu","dat"; - interrupts = , - ; - interrupt-names = "tx", "rx"; - - dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; - dma-names = "tx", "rx"; - - clocks = <&k3_clks 185 1>; - clock-names = "fck"; - power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; - }; - - watchdog0: watchdog@2200000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x0 0x2200000 0x0 0x100>; - clocks = <&k3_clks 252 1>; - power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 252 1>; - assigned-clock-parents = <&k3_clks 252 5>; - }; - - watchdog1: watchdog@2210000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x0 0x2210000 0x0 0x100>; - clocks = <&k3_clks 253 1>; - power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 253 1>; - assigned-clock-parents = <&k3_clks 253 5>; - }; - - c66_0: dsp@4d80800000 { - compatible = "ti,j721e-c66-dsp"; - reg = <0x4d 0x80800000 0x00 0x00048000>, - <0x4d 0x80e00000 0x00 0x00008000>, - <0x4d 0x80f00000 0x00 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <142>; - ti,sci-proc-ids = <0x03 0xff>; - resets = <&k3_reset 142 1>; - firmware-name = "j7-c66_0-fw"; - }; - - c66_1: dsp@4d81800000 { - compatible = "ti,j721e-c66-dsp"; - reg = <0x4d 0x81800000 0x00 0x00048000>, - <0x4d 0x81e00000 0x00 0x00008000>, - <0x4d 0x81f00000 0x00 0x00008000>; - reg-names = "l2sram", "l1pram", "l1dram"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <143>; - ti,sci-proc-ids = <0x04 0xff>; - resets = <&k3_reset 143 1>; - firmware-name = "j7-c66_1-fw"; - }; - - c71_0: dsp@64800000 { - compatible = "ti,j721e-c71-dsp"; - reg = <0x00 0x64800000 0x00 0x00080000>, - <0x00 0x64e00000 0x00 0x0000c000>; - reg-names = "l2sram", "l1dram"; - ti,sci = <&dmsc>; - ti,sci-dev-id = <15>; - ti,sci-proc-ids = <0x30 0xff>; - resets = <&k3_reset 15 1>; - firmware-name = "j7-c71_0-fw"; - }; -}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi deleted file mode 100644 index e581cb1d8..000000000 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ /dev/null @@ -1,356 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals - * - * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&cbass_mcu_wakeup { - dmsc: dmsc@44083000 { - compatible = "ti,k2g-sci"; - ti,host-id = <12>; - - mbox-names = "rx", "tx"; - - mboxes= <&secure_proxy_main 11>, - <&secure_proxy_main 13>; - - reg-names = "debug_messages"; - reg = <0x00 0x44083000 0x0 0x1000>; - - k3_pds: power-controller { - compatible = "ti,sci-pm-domain"; - #power-domain-cells = <2>; - }; - - k3_clks: clocks { - compatible = "ti,k2g-sci-clk"; - #clock-cells = <2>; - }; - - k3_reset: reset-controller { - compatible = "ti,sci-reset"; - #reset-cells = <2>; - }; - }; - - mcu_conf: syscon@40f00000 { - compatible = "syscon", "simple-mfd"; - reg = <0x0 0x40f00000 0x0 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x40f00000 0x20000>; - - phy_gmii_sel: phy@4040 { - compatible = "ti,am654-phy-gmii-sel"; - reg = <0x4040 0x4>; - #phy-cells = <1>; - }; - }; - - chipid@43000014 { - compatible = "ti,am654-chipid"; - reg = <0x0 0x43000014 0x0 0x4>; - }; - - wkup_pmx0: pinctrl@4301c000 { - compatible = "pinctrl-single"; - /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x178>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - - mcu_ram: sram@41c00000 { - compatible = "mmio-sram"; - reg = <0x00 0x41c00000 0x00 0x100000>; - ranges = <0x0 0x00 0x41c00000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - wkup_uart0: serial@42300000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x42300000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <48000000>; - current-speed = <115200>; - power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 287 0>; - clock-names = "fclk"; - }; - - mcu_uart0: serial@40a00000 { - compatible = "ti,j721e-uart", "ti,am654-uart"; - reg = <0x00 0x40a00000 0x00 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - interrupts = ; - clock-frequency = <96000000>; - current-speed = <115200>; - power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 149 0>; - clock-names = "fclk"; - }; - - wkup_gpio_intr: interrupt-controller2 { - compatible = "ti,sci-intr"; - ti,intr-trigger-type = <1>; - interrupt-controller; - interrupt-parent = <&gic500>; - #interrupt-cells = <1>; - ti,sci = <&dmsc>; - ti,sci-dev-id = <137>; - ti,interrupt-ranges = <16 960 16>; - }; - - wkup_gpio0: gpio@42110000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x42110000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&wkup_gpio_intr>; - interrupts = <103>, <104>, <105>, <106>, <107>, <108>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <84>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 113 0>; - clock-names = "gpio"; - }; - - wkup_gpio1: gpio@42100000 { - compatible = "ti,j721e-gpio", "ti,keystone-gpio"; - reg = <0x0 0x42100000 0x0 0x100>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&wkup_gpio_intr>; - interrupts = <112>, <113>, <114>, <115>, <116>, <117>; - interrupt-controller; - #interrupt-cells = <2>; - ti,ngpio = <84>; - ti,davinci-gpio-unbanked = <0>; - power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 114 0>; - clock-names = "gpio"; - }; - - mcu_i2c0: i2c@40b00000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x40b00000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 194 0>; - power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; - }; - - mcu_i2c1: i2c@40b10000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x40b10000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 195 0>; - power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; - }; - - wkup_i2c0: i2c@42120000 { - compatible = "ti,j721e-i2c", "ti,omap4-i2c"; - reg = <0x0 0x42120000 0x0 0x100>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "fck"; - clocks = <&k3_clks 197 0>; - power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; - }; - - fss: fss@47000000 { - compatible = "simple-bus"; - reg = <0x0 0x47000000 0x0 0x100>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ospi0: spi@47040000 { - compatible = "ti,am654-ospi"; - reg = <0x0 0x47040000 0x0 0x100>, - <0x5 0x00000000 0x1 0x0000000>; - interrupts = ; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 103 0>; - assigned-clocks = <&k3_clks 103 0>; - assigned-clock-parents = <&k3_clks 103 2>; - assigned-clock-rates = <166666666>; - power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - }; - - ospi1: spi@47050000 { - compatible = "ti,am654-ospi"; - reg = <0x0 0x47050000 0x0 0x100>, - <0x7 0x00000000 0x1 0x00000000>; - interrupts = ; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x0>; - clocks = <&k3_clks 104 0>; - power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - tscadc0: tscadc@40200000 { - compatible = "ti,am3359-tscadc"; - reg = <0x0 0x40200000 0x0 0x1000>; - interrupts = ; - power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 0 1>; - assigned-clocks = <&k3_clks 0 3>; - assigned-clock-rates = <60000000>; - clock-names = "adc_tsc_fck"; - dmas = <&main_udmap 0x7400>, - <&main_udmap 0x7401>; - dma-names = "fifo0", "fifo1"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - - tscadc1: tscadc@40210000 { - compatible = "ti,am3359-tscadc"; - reg = <0x0 0x40210000 0x0 0x1000>; - interrupts = ; - power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 1 1>; - assigned-clocks = <&k3_clks 1 3>; - assigned-clock-rates = <60000000>; - clock-names = "adc_tsc_fck"; - dmas = <&main_udmap 0x7402>, - <&main_udmap 0x7403>; - dma-names = "fifo0", "fifo1"; - - adc { - #io-channel-cells = <1>; - compatible = "ti,am3359-adc"; - }; - }; - - mcu-navss { - compatible = "simple-mfd"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-coherent; - dma-ranges; - - ti,sci-dev-id = <232>; - - mcu_ringacc: ringacc@2b800000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x2b800000 0x0 0x400000>, - <0x0 0x2b000000 0x0 0x400000>, - <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; - ti,num-rings = <286>; - ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,sci = <&dmsc>; - ti,sci-dev-id = <235>; - msi-parent = <&main_udmass_inta>; - }; - - mcu_udmap: dma-controller@285c0000 { - compatible = "ti,j721e-navss-mcu-udmap"; - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x2aa00000 0x0 0x40000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; - msi-parent = <&main_udmass_inta>; - #dma-cells = <1>; - - ti,sci = <&dmsc>; - ti,sci-dev-id = <236>; - ti,ringacc = <&mcu_ringacc>; - - ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ - <0x0f>; /* TX_HCHAN */ - ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ - <0x0b>; /* RX_HCHAN */ - ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ - }; - }; - - mcu_cpsw: ethernet@46000000 { - compatible = "ti,j721e-cpsw-nuss"; - #address-cells = <2>; - #size-cells = <2>; - reg = <0x0 0x46000000 0x0 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; - dma-coherent; - clocks = <&k3_clks 18 22>; - clock-names = "fck"; - power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; - - dmas = <&mcu_udmap 0xf000>, - <&mcu_udmap 0xf001>, - <&mcu_udmap 0xf002>, - <&mcu_udmap 0xf003>, - <&mcu_udmap 0xf004>, - <&mcu_udmap 0xf005>, - <&mcu_udmap 0xf006>, - <&mcu_udmap 0xf007>, - <&mcu_udmap 0x7000>; - dma-names = "tx0", "tx1", "tx2", "tx3", - "tx4", "tx5", "tx6", "tx7", - "rx"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - cpsw_port1: port@1 { - reg = <1>; - ti,mac-only; - label = "port1"; - ti,syscon-efuse = <&mcu_conf 0x200>; - phys = <&phy_gmii_sel 1>; - }; - }; - - davinci_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x0 0xf00 0x0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 18 22>; - clock-names = "fck"; - bus_freq = <1000000>; - }; - - cpts@3d000 { - compatible = "ti,am65-cpts"; - reg = <0x0 0x3d000 0x0 0x400>; - clocks = <&k3_clks 18 2>; - clock-names = "cpts"; - interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cpts"; - ti,cpts-ext-ts-inputs = <4>; - ti,cpts-periodic-outputs = <2>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi deleted file mode 100644 index 5dc3ba739..000000000 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ /dev/null @@ -1,227 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "k3-j721e.dtsi" - -/ { - memory@80000000 { - device_type = "memory"; - /* 4G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>, - <0x00000008 0x80000000 0x00000000 0x80000000>; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - alignment = <0x1000>; - no-map; - }; - - c66_1_dma_memory_region: c66-dma-memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c66_0_memory_region: c66-memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c66_0_dma_memory_region: c66-dma-memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c66_1_memory_region: c66-memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: c71-dma-memory@a8000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: c71-memory@a8100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@aa000000 { - reg = <0x00 0xaa000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; - }; -}; - -&wkup_pmx0 { - wkup_i2c0_pins_default: wkup-i2c0-pins-default { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ - J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ - >; - }; - - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { - pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ - J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ - J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ - J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ - J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ - J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ - J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ - J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ - J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ - J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ - J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ - >; - }; -}; - -&ospi0 { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - - flash@0{ - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <8>; - spi-max-frequency = <40000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <0>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&mailbox0_cluster0 { - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - interrupts = <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - interrupts = <424>; - - mbox_c66_0: mbox-c66-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c66_1: mbox-c66-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - interrupts = <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - -&mailbox0_cluster8 { - status = "disabled"; -}; - -&mailbox0_cluster9 { - status = "disabled"; -}; - -&mailbox0_cluster10 { - status = "disabled"; -}; - -&mailbox0_cluster11 { - status = "disabled"; -}; - -&c66_0 { - mboxes = <&mailbox0_cluster3 &mbox_c66_0>; - memory-region = <&c66_0_dma_memory_region>, - <&c66_0_memory_region>; -}; - -&c66_1 { - mboxes = <&mailbox0_cluster3 &mbox_c66_1>; - memory-region = <&c66_1_dma_memory_region>, - <&c66_1_memory_region>; -}; - -&c71_0 { - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi deleted file mode 100644 index ba4fe3f98..000000000 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ /dev/null @@ -1,185 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for J721E SoC Family - * - * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include -#include -#include -#include - -/ { - model = "Texas Instruments K3 J721E SoC"; - compatible = "ti,j721e"; - interrupt-parent = <&gic500>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - serial5 = &main_uart3; - serial6 = &main_uart4; - serial7 = &main_uart5; - serial8 = &main_uart6; - serial9 = &main_uart7; - serial10 = &main_uart8; - serial11 = &main_uart9; - ethernet0 = &cpsw_port1; - }; - - chosen { }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu-map { - cluster0: cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - }; - - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a72"; - reg = <0x000>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a72"; - reg = <0x001>; - device_type = "cpu"; - enable-method = "psci"; - i-cache-size = <0xC000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&L2_0>; - }; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - next-level-cache = <&msmc_l3>; - }; - - msmc_l3: l3-cache0 { - compatible = "cache"; - cache-level = <3>; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - psci: psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - }; - - a72_timer0: timer-cl0-cpu0 { - compatible = "arm,armv8-timer"; - interrupts = , /* cntpsirq */ - , /* cntpnsirq */ - , /* cntvirq */ - ; /* cnthpirq */ - }; - - pmu: pmu { - compatible = "arm,armv8-pmuv3"; - /* Recommendation from GIC500 TRM Table A.3 */ - interrupts = ; - }; - - cbass_main: bus@100000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ - <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ - <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ - <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ - <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ - <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ - <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ - <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ - <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/ - <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/ - <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ - <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ - <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ - <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */ - <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */ - <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ - <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */ - <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ - <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ - - /* MCUSS_WKUP Range */ - <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; - - cbass_mcu_wakeup: bus@28380000 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ - <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ - <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ - <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ - <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ - <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ - <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ - <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ - <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ - <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ - <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ - <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ - <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ - }; - }; -}; - -/* Now include the peripherals for each bus segments */ -#include "k3-j721e-main.dtsi" -#include "k3-j721e-mcu-wakeup.dtsi" diff --git a/arch/arm64/boot/dts/toshiba/Makefile b/arch/arm64/boot/dts/toshiba/Makefile deleted file mode 100644 index 8cd460d5b..000000000 --- a/arch/arm64/boot/dts/toshiba/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_VISCONTI) += tmpv7708-rm-mbrc.dtb diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts deleted file mode 100644 index ed0bf7f13..000000000 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree File for TMPV7708 RM main board - * - * (C) Copyright 2020, Toshiba Corporation. - * (C) Copyright 2020, Nobuhiro Iwamatsu - */ - -/dts-v1/; - -#include "tmpv7708.dtsi" - -/ { - model = "Toshiba TMPV7708 RM main board"; - compatible = "toshiba,tmpv7708-rm-mbrc", "toshiba,tmpv7708"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - /* 768MB memory */ - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x30000000>; - }; -}; - -&uart0 { - status = "okay"; - clocks = <&uart_clk>; - clock-names = "apb_pclk"; -}; - -&uart1 { - status = "okay"; - clocks = <&uart_clk>; - clock-names = "apb_pclk"; -}; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi deleted file mode 100644 index 242f25f4e..000000000 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ /dev/null @@ -1,390 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Source for the TMPV7708 - * - * (C) Copyright 2018 - 2020, Toshiba Corporation. - * (C) Copyright 2020, Nobuhiro Iwamatsu - * - */ - -#include -#include - -/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ - -/ { - compatible = "toshiba,tmpv7708"; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu4>; - }; - core1 { - cpu = <&cpu5>; - }; - core2 { - cpu = <&cpu6>; - }; - core3 { - cpu = <&cpu7>; - }; - }; - }; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x81100000>; - reg = <0x00>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x81100000>; - reg = <0x01>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x81100000>; - reg = <0x02>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x81100000>; - reg = <0x03>; - }; - - cpu4: cpu@100 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x81100000>; - reg = <0x100>; - }; - - cpu5: cpu@101 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x81100000>; - reg = <0x101>; - }; - - cpu6: cpu@102 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x81100000>; - reg = <0x102>; - }; - - cpu7: cpu@103 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x81100000>; - reg = <0x103>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = - , - , - , - ; - }; - - uart_clk: uart-clk { - compatible = "fixed-clock"; - clock-frequency = <150000000>; - #clock-cells = <0>; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - - gic: interrupt-controller@24001000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - reg = <0 0x24001000 0 0x1000>, - <0 0x24002000 0 0x2000>, - <0 0x24004000 0 0x2000>, - <0 0x24006000 0 0x2000>; - }; - - pmux: pmux@24190000 { - compatible = "toshiba,tmpv7708-pinctrl"; - reg = <0 0x24190000 0 0x10000>; - }; - - uart0: serial@28200000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0 0x28200000 0 0x1000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "disabled"; - }; - - uart1: serial@28201000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0 0x28201000 0 0x1000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "disabled"; - }; - - uart2: serial@28202000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0 0x28202000 0 0x1000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "disabled"; - }; - - uart3: serial@28203000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0 0x28203000 0 0x1000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "disabled"; - }; - - i2c0: i2c@28030000 { - compatible = "snps,designware-i2c"; - reg = <0 0x28030000 0 0x1000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@28031000 { - compatible = "snps,designware-i2c"; - reg = <0 0x28031000 0 0x1000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@28032000 { - compatible = "snps,designware-i2c"; - reg = <0 0x28032000 0 0x1000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@28033000 { - compatible = "snps,designware-i2c"; - reg = <0 0x28033000 0 0x1000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@28034000 { - compatible = "snps,designware-i2c"; - reg = <0 0x28034000 0 0x1000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@28035000 { - compatible = "snps,designware-i2c"; - reg = <0 0x28035000 0 0x1000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c6: i2c@28036000 { - compatible = "snps,designware-i2c"; - reg = <0 0x28036000 0 0x1000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_pins>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c7: i2c@28037000 { - compatible = "snps,designware-i2c"; - reg = <0 0x28037000 0 0x1000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7_pins>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c8: i2c@28038000 { - compatible = "snps,designware-i2c"; - reg = <0 0x28038000 0 0x1000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8_pins>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@28140000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0 0x28140000 0 0x1000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@28141000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0 0x28141000 0 0x1000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@28142000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0 0x28142000 0 0x1000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@28143000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0 0x28143000 0 0x1000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi3_pins>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@28144000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0 0x28144000 0 0x1000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi4_pins>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi5: spi@28145000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0 0x28145000 0 0x1000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi5_pins>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi6: spi@28146000 { - compatible = "arm,pl022", "arm,primecell"; - reg = <0 0x28146000 0 0x1000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&spi6_pins>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; -}; - -#include "tmpv7708_pins.dtsi" diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi deleted file mode 100644 index 34de00015..000000000 --- a/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -&pmux { - spi0_pins: spi0-pins { - function = "spi0"; - groups = "spi0_grp"; - }; - spi1_pins: spi1-pins { - function = "spi1"; - groups = "spi1_grp"; - }; - spi2_pins: spi2-pins { - function = "spi2"; - groups = "spi2_grp"; - }; - spi3_pins: spi3-pins { - function = "spi3"; - groups = "spi3_grp"; - }; - spi4_pins: spi4-pins { - function = "spi4"; - groups = "spi4_grp"; - }; - spi5_pins: spi5-pins { - function = "spi5"; - groups = "spi5_grp"; - }; - spi6_pins: spi6-pins { - function = "spi6"; - groups = "spi6_grp"; - }; - uart0_pins: uart0-pins { - function = "uart0"; - groups = "uart0_grp"; - }; - uart1_pins: uart1-pins { - function = "uart1"; - groups = "uart1_grp"; - }; - uart2_pins: uart2-pins { - function = "uart2"; - groups = "uart2_grp"; - }; - uart3_pins: uart3-pins { - function = "uart3"; - groups = "uart3_grp"; - }; - i2c0_pins: i2c0-pins { - function = "i2c0"; - groups = "i2c0_grp"; - bias-pull-up; - }; - i2c1_pins: i2c1-pins { - function = "i2c1"; - groups = "i2c1_grp"; - bias-pull-up; - }; - i2c2_pins: i2c2-pins { - function = "i2c2"; - groups = "i2c2_grp"; - bias-pull-up; - }; - i2c3_pins: i2c3-pins { - function = "i2c3"; - groups = "i2c3_grp"; - bias-pull-up; - }; - i2c4_pins: i2c4-pins { - function = "i2c4"; - groups = "i2c4_grp"; - bias-pull-up; - }; - i2c5_pins: i2c5-pins { - function = "i2c5"; - groups = "i2c5_grp"; - bias-pull-up; - }; - i2c6_pins: i2c6-pins { - function = "i2c6"; - groups = "i2c6_grp"; - bias-pull-up; - }; - i2c7_pins: i2c7-pins { - function = "i2c7"; - groups = "i2c7_grp"; - bias-pull-up; - }; - i2c8_pins: i2c8-pins { - function = "i2c8"; - groups = "i2c8_grp"; - bias-pull-up; - }; -}; diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile deleted file mode 100644 index 60f5443f3..000000000 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_ZYNQMP) += avnet-ultra96-rev1.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm015-dc1.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm016-dc2.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm017-dc3.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm018-dc4.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm019-dc5.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb -dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu111-revA.dtb diff --git a/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts b/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts deleted file mode 100644 index 88aa06fa7..000000000 --- a/arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Avnet Ultra96 rev1 - * - * (C) Copyright 2018, Xilinx, Inc. - * - * Michal Simek - */ - -/dts-v1/; - -#include "zynqmp-zcu100-revC.dts" - -/ { - model = "Avnet Ultra96 Rev1"; - compatible = "avnet,ultra96-rev1", "avnet,ultra96", - "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", - "xlnx,zynqmp"; -}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi deleted file mode 100644 index c94c3bb67..000000000 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ /dev/null @@ -1,217 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Clock specification for Xilinx ZynqMP - * - * (C) Copyright 2017 - 2019, Xilinx, Inc. - * - * Michal Simek - */ - -#include -/ { - pss_ref_clk: pss_ref_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <33333333>; - }; - - video_clk: video_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; - - pss_alt_ref_clk: pss_alt_ref_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - gt_crx_ref_clk: gt_crx_ref_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <108000000>; - }; - - aux_ref_clk: aux_ref_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; -}; - -&can0 { - clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&can1 { - clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&cpu0 { - clocks = <&zynqmp_clk ACPU>; -}; - -&fpd_dma_chan1 { - clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&fpd_dma_chan2 { - clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&fpd_dma_chan3 { - clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&fpd_dma_chan4 { - clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&fpd_dma_chan5 { - clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&fpd_dma_chan6 { - clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&fpd_dma_chan7 { - clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&fpd_dma_chan8 { - clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&lpd_dma_chan1 { - clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&lpd_dma_chan2 { - clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&lpd_dma_chan3 { - clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&lpd_dma_chan4 { - clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&lpd_dma_chan5 { - clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&lpd_dma_chan6 { - clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&lpd_dma_chan7 { - clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&lpd_dma_chan8 { - clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&gem0 { - clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, - <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, - <&zynqmp_clk GEM_TSU>; - clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; -}; - -&gem1 { - clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, - <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, - <&zynqmp_clk GEM_TSU>; - clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; -}; - -&gem2 { - clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, - <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, - <&zynqmp_clk GEM_TSU>; - clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; -}; - -&gem3 { - clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, - <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, - <&zynqmp_clk GEM_TSU>; - clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; -}; - -&gpio { - clocks = <&zynqmp_clk LPD_LSBUS>; -}; - -&i2c0 { - clocks = <&zynqmp_clk I2C0_REF>; -}; - -&i2c1 { - clocks = <&zynqmp_clk I2C1_REF>; -}; - -&pcie { - clocks = <&zynqmp_clk PCIE_REF>; -}; - -&sata { - clocks = <&zynqmp_clk SATA_REF>; -}; - -&sdhci0 { - clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&sdhci1 { - clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&spi0 { - clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&spi1 { - clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&ttc0 { - clocks = <&zynqmp_clk LPD_LSBUS>; -}; - -&ttc1 { - clocks = <&zynqmp_clk LPD_LSBUS>; -}; - -&ttc2 { - clocks = <&zynqmp_clk LPD_LSBUS>; -}; - -&ttc3 { - clocks = <&zynqmp_clk LPD_LSBUS>; -}; - -&uart0 { - clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&uart1 { - clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; -}; - -&usb0 { - clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; -}; - -&usb1 { - clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; -}; - -&watchdog0 { - clocks = <&zynqmp_clk WDT>; -}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts deleted file mode 100644 index 2e05fa416..000000000 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP ZC1232 - * - * (C) Copyright 2017 - 2019, Xilinx, Inc. - * - * Michal Simek - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" - -/ { - model = "ZynqMP ZC1232 RevA"; - compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; - - aliases { - serial0 = &uart0; - serial1 = &dcc; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; -}; - -&dcc { - status = "okay"; -}; - -&sata { - status = "okay"; - /* SATA OOB timing settings */ - ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts deleted file mode 100644 index 3d0aaa02f..000000000 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP ZC1254 - * - * (C) Copyright 2015 - 2019, Xilinx, Inc. - * - * Michal Simek - * Siva Durga Prasad Paladugu - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" - -/ { - model = "ZynqMP ZC1254 RevA"; - compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; - - aliases { - serial0 = &uart0; - serial1 = &dcc; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; -}; - -&dcc { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts deleted file mode 100644 index 66a90483b..000000000 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP ZC1275 - * - * (C) Copyright 2017 - 2019, Xilinx, Inc. - * - * Michal Simek - * Siva Durga Prasad Paladugu - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" - -/ { - model = "ZynqMP ZC1275 RevA"; - compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; - - aliases { - serial0 = &uart0; - serial1 = &dcc; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; -}; - -&dcc { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts deleted file mode 100644 index 69f6e4610..000000000 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP zc1751-xm015-dc1 - * - * (C) Copyright 2015 - 2019, Xilinx, Inc. - * - * Michal Simek - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" -#include - -/ { - model = "ZynqMP zc1751-xm015-dc1 RevA"; - compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; - - aliases { - ethernet0 = &gem3; - i2c0 = &i2c1; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - rtc0 = &rtc; - serial0 = &uart0; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; - }; -}; - -&fpd_dma_chan1 { - status = "okay"; -}; - -&fpd_dma_chan2 { - status = "okay"; -}; - -&fpd_dma_chan3 { - status = "okay"; -}; - -&fpd_dma_chan4 { - status = "okay"; -}; - -&fpd_dma_chan5 { - status = "okay"; -}; - -&fpd_dma_chan6 { - status = "okay"; -}; - -&fpd_dma_chan7 { - status = "okay"; -}; - -&fpd_dma_chan8 { - status = "okay"; -}; - -&gem3 { - status = "okay"; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&gpio { - status = "okay"; -}; - - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - eeprom: eeprom@55 { - compatible = "atmel,24c64"; /* 24AA64 */ - reg = <0x55>; - }; -}; - -&rtc { - status = "okay"; -}; - -&sata { - status = "okay"; - /* SATA phy OOB timing settings */ - ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; - ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; - ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; - ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; - ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; -}; - -/* eMMC */ -&sdhci0 { - status = "okay"; - bus-width = <8>; -}; - -/* SD1 with level shifter */ -&sdhci1 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -/* ULPI SMSC USB3320 */ -&usb0 { - status = "okay"; - dr_mode = "host"; -}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts deleted file mode 100644 index f7124e15f..000000000 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ /dev/null @@ -1,170 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP zc1751-xm016-dc2 - * - * (C) Copyright 2015 - 2019, Xilinx, Inc. - * - * Michal Simek - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" -#include - -/ { - model = "ZynqMP zc1751-xm016-dc2 RevA"; - compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; - - aliases { - can0 = &can0; - can1 = &can1; - ethernet0 = &gem2; - i2c0 = &i2c0; - rtc0 = &rtc; - serial0 = &uart0; - serial1 = &uart1; - spi0 = &spi0; - spi1 = &spi1; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; - }; -}; - -&can0 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&fpd_dma_chan1 { - status = "okay"; -}; - -&fpd_dma_chan2 { - status = "okay"; -}; - -&fpd_dma_chan3 { - status = "okay"; -}; - -&fpd_dma_chan4 { - status = "okay"; -}; - -&fpd_dma_chan5 { - status = "okay"; -}; - -&fpd_dma_chan6 { - status = "okay"; -}; - -&fpd_dma_chan7 { - status = "okay"; -}; - -&fpd_dma_chan8 { - status = "okay"; -}; - -&gem2 { - status = "okay"; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - phy0: ethernet-phy@5 { - reg = <5>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - }; -}; - -&gpio { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - tca6416_u26: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - /* IRQ not connected */ - }; - - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&rtc { - status = "okay"; -}; - -&spi0 { - status = "okay"; - num-cs = <1>; - - spi0_flash0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "sst,sst25wf080", "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - - partition@0 { - label = "spi0-data"; - reg = <0x0 0x100000>; - }; - }; -}; - -&spi1 { - status = "okay"; - num-cs = <1>; - - spi1_flash0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <20000000>; - reg = <0>; - - partition@0 { - label = "spi1-data"; - reg = <0x0 0x84000>; - }; - }; -}; - -/* ULPI SMSC USB3320 */ -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts deleted file mode 100644 index 4ea6ef5a7..000000000 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts +++ /dev/null @@ -1,150 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP zc1751-xm017-dc3 - * - * (C) Copyright 2016 - 2019, Xilinx, Inc. - * - * Michal Simek - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" - -/ { - model = "ZynqMP zc1751-xm017-dc3 RevA"; - compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; - - aliases { - ethernet0 = &gem0; - i2c0 = &i2c0; - i2c1 = &i2c1; - mmc0 = &sdhci1; - rtc0 = &rtc; - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; - }; -}; - -&fpd_dma_chan1 { - status = "okay"; -}; - -&fpd_dma_chan2 { - status = "okay"; -}; - -&fpd_dma_chan3 { - status = "okay"; -}; - -&fpd_dma_chan4 { - status = "okay"; -}; - -&fpd_dma_chan5 { - status = "okay"; -}; - -&fpd_dma_chan6 { - status = "okay"; -}; - -&fpd_dma_chan7 { - status = "okay"; -}; - -&fpd_dma_chan8 { - status = "okay"; -}; - -&gem0 { - status = "okay"; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - phy0: ethernet-phy@0 { /* VSC8211 */ - reg = <0>; - }; -}; - -&gpio { - status = "okay"; -}; - -/* just eeprom here */ -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - tca6416_u26: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - /* IRQ not connected */ - }; - - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -/* eeprom24c02 and SE98A temp chip pca9306 */ -&i2c1 { - status = "okay"; - clock-frequency = <400000>; -}; - -&rtc { - status = "okay"; -}; - -&sata { - status = "okay"; - /* SATA phy OOB timing settings */ - ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; - ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; - ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; - ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; - ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; -}; - -&sdhci1 { /* emmc with some settings */ - status = "okay"; -}; - -/* main */ -&uart0 { - status = "okay"; -}; - -/* DB9 */ -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -/* ULPI SMSC USB3320 */ -&usb1 { - status = "okay"; - dr_mode = "host"; -}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts deleted file mode 100644 index 2366cd9f0..000000000 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +++ /dev/null @@ -1,178 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP zc1751-xm018-dc4 - * - * (C) Copyright 2015 - 2019, Xilinx, Inc. - * - * Michal Simek - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" - -/ { - model = "ZynqMP zc1751-xm018-dc4"; - compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; - - aliases { - ethernet0 = &gem0; - ethernet1 = &gem1; - ethernet2 = &gem2; - ethernet3 = &gem3; - i2c0 = &i2c0; - i2c1 = &i2c1; - rtc0 = &rtc; - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; - }; -}; - -&can0 { - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&fpd_dma_chan1 { - status = "okay"; -}; - -&fpd_dma_chan2 { - status = "okay"; -}; - -&fpd_dma_chan3 { - status = "okay"; -}; - -&fpd_dma_chan4 { - status = "okay"; -}; - -&fpd_dma_chan5 { - status = "okay"; -}; - -&fpd_dma_chan6 { - status = "okay"; -}; - -&fpd_dma_chan7 { - status = "okay"; -}; - -&fpd_dma_chan8 { - status = "okay"; -}; - -&lpd_dma_chan1 { - status = "okay"; -}; - -&lpd_dma_chan2 { - status = "okay"; -}; - -&lpd_dma_chan3 { - status = "okay"; -}; - -&lpd_dma_chan4 { - status = "okay"; -}; - -&lpd_dma_chan5 { - status = "okay"; -}; - -&lpd_dma_chan6 { - status = "okay"; -}; - -&lpd_dma_chan7 { - status = "okay"; -}; - -&lpd_dma_chan8 { - status = "okay"; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy0>; - ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ - reg = <0>; - }; - ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ - reg = <7>; - }; - ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ - reg = <3>; - }; - ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ - reg = <8>; - }; -}; - -&gem1 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy7>; -}; - -&gem2 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy3>; -}; - -&gem3 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy8>; -}; - -&gpio { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&watchdog0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts deleted file mode 100644 index 41934e352..000000000 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP zc1751-xm019-dc5 - * - * (C) Copyright 2015 - 2019, Xilinx, Inc. - * - * Siva Durga Prasad - * Michal Simek - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" -#include - -/ { - model = "ZynqMP zc1751-xm019-dc5 RevA"; - compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; - - aliases { - ethernet0 = &gem1; - i2c0 = &i2c0; - i2c1 = &i2c1; - mmc0 = &sdhci0; - serial0 = &uart0; - serial1 = &uart1; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; - }; -}; - -&fpd_dma_chan1 { - status = "okay"; -}; - -&fpd_dma_chan2 { - status = "okay"; -}; - -&fpd_dma_chan3 { - status = "okay"; -}; - -&fpd_dma_chan4 { - status = "okay"; -}; - -&fpd_dma_chan5 { - status = "okay"; -}; - -&fpd_dma_chan6 { - status = "okay"; -}; - -&fpd_dma_chan7 { - status = "okay"; -}; - -&fpd_dma_chan8 { - status = "okay"; -}; - -&gem1 { - status = "okay"; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&gpio { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&sdhci0 { - status = "okay"; - no-1-8-v; -}; - -&ttc0 { - status = "okay"; -}; - -&ttc1 { - status = "okay"; -}; - -&ttc2 { - status = "okay"; -}; - -&ttc3 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&watchdog0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts deleted file mode 100644 index 68ecd0f7b..000000000 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ /dev/null @@ -1,295 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP ZCU100 revC - * - * (C) Copyright 2016 - 2019, Xilinx, Inc. - * - * Michal Simek - * Nathalie Chan King Choy - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" -#include -#include -#include - -/ { - model = "ZynqMP ZCU100 RevC"; - compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; - - aliases { - i2c0 = &i2c1; - rtc0 = &rtc; - serial0 = &uart1; - serial1 = &uart0; - serial2 = &dcc; - spi0 = &spi0; - spi1 = &spi1; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - sw4 { - label = "sw4"; - gpios = <&gpio 23 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - autorepeat; - }; - }; - - leds { - compatible = "gpio-leds"; - led-ds2 { - label = "ds2"; - gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-ds3 { - label = "ds3"; - gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; /* WLAN tx */ - default-state = "off"; - }; - - led-ds4 { - label = "ds4"; - gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0rx"; /* WLAN rx */ - default-state = "off"; - }; - - led-ds5 { - label = "ds5"; - gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "bluetooth-power"; - }; - - vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ - label = "vbus_det"; - gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - wmmcsdio_fixed: fixedregulator-mmcsdio { - compatible = "regulator-fixed"; - regulator-name = "wmmcsdio_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ - post-power-on-delay-ms = <10>; - }; - - ina226 { - compatible = "iio-hwmon"; - io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; - }; -}; - -&dcc { - status = "okay"; -}; - -&gpio { - status = "okay"; - gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", - "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", - "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", - "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", - "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", - "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", - "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", - "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", - "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", - "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", - "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", - "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", - "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", - "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", - "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", - "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ - "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", - "", "", "", ""; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <100000>; - i2c-mux@75 { /* u11 */ - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - i2csw_0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - label = "LS-I2C0"; - }; - i2csw_1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - label = "LS-I2C1"; - }; - i2csw_2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - label = "HS-I2C2"; - }; - i2csw_3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - label = "HS-I2C3"; - }; - i2csw_4: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4>; - - pmic: pmic@5e { /* Custom TI PMIC u33 */ - compatible = "ti,tps65086"; - reg = <0x5e>; - interrupt-parent = <&gpio>; - interrupts = <77 IRQ_TYPE_LEVEL_LOW>; - #gpio-cells = <2>; - gpio-controller; - }; - }; - i2csw_5: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - /* PS_PMBUS */ - u35: ina226@40 { /* u35 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - reg = <0x40>; - shunt-resistor = <10000>; - /* MIO31 is alert which should be routed to PMUFW */ - }; - }; - i2csw_6: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - /* - * Not Connected - */ - }; - i2csw_7: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - /* - * usb5744 (DNP) - U5 - * 100kHz - this is default freq for us - */ - }; - }; -}; - -&rtc { - status = "okay"; -}; - -/* SD0 only supports 3.3V, no level shifter */ -&sdhci0 { - status = "okay"; - no-1-8-v; - disable-wp; -}; - -&sdhci1 { - status = "okay"; - bus-width = <0x4>; - non-removable; - disable-wp; - cap-power-off-card; - mmc-pwrseq = <&sdio_pwrseq>; - vqmmc-supply = <&wmmcsdio_fixed>; - #address-cells = <1>; - #size-cells = <0>; - wlcore: wifi@2 { - compatible = "ti,wl1831"; - reg = <2>; - interrupt-parent = <&gpio>; - interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ - }; -}; - -&spi0 { /* Low Speed connector */ - status = "okay"; - label = "LS-SPI0"; - num-cs = <1>; -}; - -&spi1 { /* High Speed connector */ - status = "okay"; - label = "HS-SPI1"; - num-cs = <1>; -}; - -&uart0 { - status = "okay"; - bluetooth { - compatible = "ti,wl1831-st"; - enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart1 { - status = "okay"; - -}; - -/* ULPI SMSC USB3320 */ -&usb0 { - status = "okay"; - dr_mode = "peripheral"; -}; - -/* ULPI SMSC USB3320 */ -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&watchdog0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts deleted file mode 100644 index 6647e97ed..000000000 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP ZCU102 Rev1.0 - * - * (C) Copyright 2016 - 2018, Xilinx, Inc. - * - * Michal Simek - */ - -#include "zynqmp-zcu102-revB.dts" - -/ { - model = "ZynqMP ZCU102 Rev1.0"; - compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; -}; - -&eeprom { - #address-cells = <1>; - #size-cells = <1>; - - board_sn: board-sn@0 { - reg = <0x0 0x14>; - }; - - eth_mac: eth-mac@20 { - reg = <0x20 0x6>; - }; - - board_name: board-name@d0 { - reg = <0xd0 0x6>; - }; - - board_revision: board-revision@e0 { - reg = <0xe0 0x3>; - }; -}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts deleted file mode 100644 index f1255f635..000000000 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ /dev/null @@ -1,634 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP ZCU102 RevA - * - * (C) Copyright 2015 - 2019, Xilinx, Inc. - * - * Michal Simek - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" -#include -#include - -/ { - model = "ZynqMP ZCU102 RevA"; - compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; - - aliases { - ethernet0 = &gem3; - i2c0 = &i2c0; - i2c1 = &i2c1; - mmc0 = &sdhci1; - rtc0 = &rtc; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &dcc; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - sw19 { - label = "sw19"; - gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; - linux,code = ; - wakeup-source; - autorepeat; - }; - }; - - leds { - compatible = "gpio-leds"; - heartbeat-led { - label = "heartbeat"; - gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - ina226-u76 { - compatible = "iio-hwmon"; - io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; - }; - ina226-u77 { - compatible = "iio-hwmon"; - io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; - }; - ina226-u78 { - compatible = "iio-hwmon"; - io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; - }; - ina226-u87 { - compatible = "iio-hwmon"; - io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; - }; - ina226-u85 { - compatible = "iio-hwmon"; - io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; - }; - ina226-u86 { - compatible = "iio-hwmon"; - io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; - }; - ina226-u93 { - compatible = "iio-hwmon"; - io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; - }; - ina226-u88 { - compatible = "iio-hwmon"; - io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; - }; - ina226-u15 { - compatible = "iio-hwmon"; - io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; - }; - ina226-u92 { - compatible = "iio-hwmon"; - io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; - }; - ina226-u79 { - compatible = "iio-hwmon"; - io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; - }; - ina226-u81 { - compatible = "iio-hwmon"; - io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; - }; - ina226-u80 { - compatible = "iio-hwmon"; - io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; - }; - ina226-u84 { - compatible = "iio-hwmon"; - io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; - }; - ina226-u16 { - compatible = "iio-hwmon"; - io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; - }; - ina226-u65 { - compatible = "iio-hwmon"; - io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; - }; - ina226-u74 { - compatible = "iio-hwmon"; - io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; - }; - ina226-u75 { - compatible = "iio-hwmon"; - io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; - }; -}; - -&can1 { - status = "okay"; -}; - -&dcc { - status = "okay"; -}; - -&fpd_dma_chan1 { - status = "okay"; -}; - -&fpd_dma_chan2 { - status = "okay"; -}; - -&fpd_dma_chan3 { - status = "okay"; -}; - -&fpd_dma_chan4 { - status = "okay"; -}; - -&fpd_dma_chan5 { - status = "okay"; -}; - -&fpd_dma_chan6 { - status = "okay"; -}; - -&fpd_dma_chan7 { - status = "okay"; -}; - -&fpd_dma_chan8 { - status = "okay"; -}; - -&gem3 { - status = "okay"; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - phy0: ethernet-phy@21 { - reg = <21>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - }; -}; - -&gpio { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - tca6416_u97: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; /* IRQ not connected */ - #gpio-cells = <2>; - gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", - "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", - "", "", "", "", "", "", "", "", ""; - gtr-sel0-hog { - gpio-hog; - gpios = <0 0>; - output-low; /* PCIE = 0, DP = 1 */ - line-name = "sel0"; - }; - gtr-sel1-hog { - gpio-hog; - gpios = <1 0>; - output-high; /* PCIE = 0, DP = 1 */ - line-name = "sel1"; - }; - gtr-sel2-hog { - gpio-hog; - gpios = <2 0>; - output-high; /* PCIE = 0, USB0 = 1 */ - line-name = "sel2"; - }; - gtr-sel3-hog { - gpio-hog; - gpios = <3 0>; - output-high; /* PCIE = 0, SATA = 1 */ - line-name = "sel3"; - }; - }; - - tca6416_u61: gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; /* IRQ not connected */ - #gpio-cells = <2>; - gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", - "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", - "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", - "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; - }; - - i2c-mux@75 { /* u60 */ - compatible = "nxp,pca9544"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* PS_PMBUS */ - u76: ina226@40 { /* u76 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u76"; - reg = <0x40>; - shunt-resistor = <5000>; - }; - u77: ina226@41 { /* u77 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u77"; - reg = <0x41>; - shunt-resistor = <5000>; - }; - u78: ina226@42 { /* u78 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u78"; - reg = <0x42>; - shunt-resistor = <5000>; - }; - u87: ina226@43 { /* u87 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u87"; - reg = <0x43>; - shunt-resistor = <5000>; - }; - u85: ina226@44 { /* u85 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u85"; - reg = <0x44>; - shunt-resistor = <5000>; - }; - u86: ina226@45 { /* u86 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u86"; - reg = <0x45>; - shunt-resistor = <5000>; - }; - u93: ina226@46 { /* u93 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u93"; - reg = <0x46>; - shunt-resistor = <5000>; - }; - u88: ina226@47 { /* u88 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u88"; - reg = <0x47>; - shunt-resistor = <5000>; - }; - u15: ina226@4a { /* u15 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u15"; - reg = <0x4a>; - shunt-resistor = <5000>; - }; - u92: ina226@4b { /* u92 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u92"; - reg = <0x4b>; - shunt-resistor = <5000>; - }; - }; - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - /* PL_PMBUS */ - u79: ina226@40 { /* u79 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u79"; - reg = <0x40>; - shunt-resistor = <2000>; - }; - u81: ina226@41 { /* u81 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u81"; - reg = <0x41>; - shunt-resistor = <5000>; - }; - u80: ina226@42 { /* u80 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u80"; - reg = <0x42>; - shunt-resistor = <5000>; - }; - u84: ina226@43 { /* u84 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u84"; - reg = <0x43>; - shunt-resistor = <5000>; - }; - u16: ina226@44 { /* u16 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u16"; - reg = <0x44>; - shunt-resistor = <5000>; - }; - u65: ina226@45 { /* u65 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u65"; - reg = <0x45>; - shunt-resistor = <5000>; - }; - u74: ina226@46 { /* u74 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u74"; - reg = <0x46>; - shunt-resistor = <5000>; - }; - u75: ina226@47 { /* u75 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u75"; - reg = <0x47>; - shunt-resistor = <5000>; - }; - }; - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - /* MAXIM_PMBUS - 00 */ - max15301@a { /* u46 */ - compatible = "maxim,max15301"; - reg = <0xa>; - }; - max15303@b { /* u4 */ - compatible = "maxim,max15303"; - reg = <0xb>; - }; - max15303@10 { /* u13 */ - compatible = "maxim,max15303"; - reg = <0x10>; - }; - max15301@13 { /* u47 */ - compatible = "maxim,max15301"; - reg = <0x13>; - }; - max15303@14 { /* u7 */ - compatible = "maxim,max15303"; - reg = <0x14>; - }; - max15303@15 { /* u6 */ - compatible = "maxim,max15303"; - reg = <0x15>; - }; - max15303@16 { /* u10 */ - compatible = "maxim,max15303"; - reg = <0x16>; - }; - max15303@17 { /* u9 */ - compatible = "maxim,max15303"; - reg = <0x17>; - }; - max15301@18 { /* u63 */ - compatible = "maxim,max15301"; - reg = <0x18>; - }; - max15303@1a { /* u49 */ - compatible = "maxim,max15303"; - reg = <0x1a>; - }; - max15303@1d { /* u18 */ - compatible = "maxim,max15303"; - reg = <0x1d>; - }; - max15303@20 { /* u8 */ - compatible = "maxim,max15303"; - status = "disabled"; /* unreachable */ - reg = <0x20>; - }; - - max20751@72 { /* u95 */ - compatible = "maxim,max20751"; - reg = <0x72>; - }; - max20751@73 { /* u96 */ - compatible = "maxim,max20751"; - reg = <0x73>; - }; - }; - /* Bus 3 is not connected */ - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - /* PL i2c via PCA9306 - u45 */ - i2c-mux@74 { /* u34 */ - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x74>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* - * IIC_EEPROM 1kB memory which uses 256B blocks - * where every block has different address. - * 0 - 256B address 0x54 - * 256B - 512B address 0x55 - * 512B - 768B address 0x56 - * 768B - 1024B address 0x57 - */ - eeprom: eeprom@54 { /* u23 */ - compatible = "atmel,24c08"; - reg = <0x54>; - }; - }; - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - si5341: clock-generator@36 { /* SI5341 - u69 */ - reg = <0x36>; - }; - - }; - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - si570_1: clock-generator@5d { /* USER SI570 - u42 */ - #clock-cells = <0>; - compatible = "silabs,si570"; - reg = <0x5d>; - temperature-stability = <50>; - factory-fout = <300000000>; - clock-frequency = <300000000>; - clock-output-names = "si570_user"; - }; - }; - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ - #clock-cells = <0>; - compatible = "silabs,si570"; - reg = <0x5d>; - temperature-stability = <50>; /* copy from zc702 */ - factory-fout = <156250000>; - clock-frequency = <148500000>; - clock-output-names = "si570_mgt"; - }; - }; - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - si5328: clock-generator@69 {/* SI5328 - u20 */ - reg = <0x69>; - /* - * Chip has interrupt present connected to PL - * interrupt-parent = <&>; - * interrupts = <>; - */ - }; - }; - /* 5 - 7 unconnected */ - }; - - i2c-mux@75 { - compatible = "nxp,pca9548"; /* u135 */ - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* HPC0_IIC */ - }; - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - /* HPC1_IIC */ - }; - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - /* SYSMON */ - }; - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - /* DDR4 SODIMM */ - }; - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - /* SEP 3 */ - }; - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - /* SEP 2 */ - }; - i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - /* SEP 1 */ - }; - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - /* SEP 0 */ - }; - }; -}; - -&pcie { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sata { - status = "okay"; - /* SATA OOB timing settings */ - ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; -}; - -/* SD1 with level shifter */ -&sdhci1 { - status = "okay"; - no-1-8-v; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -/* ULPI SMSC USB3320 */ -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&watchdog0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts deleted file mode 100644 index d9ad8a4b2..000000000 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP ZCU102 RevB - * - * (C) Copyright 2016 - 2018, Xilinx, Inc. - * - * Michal Simek - */ - -#include "zynqmp-zcu102-revA.dts" - -/ { - model = "ZynqMP ZCU102 RevB"; - compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; -}; - -&gem3 { - phy-handle = <&phyc>; - phyc: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - }; - /* Cleanup from RevA */ - /delete-node/ ethernet-phy@21; -}; - -/* Fix collision with u61 */ -&i2c0 { - i2c-mux@75 { - i2c@2 { - max15303@1b { /* u8 */ - compatible = "maxim,max15303"; - reg = <0x1b>; - }; - /delete-node/ max15303@20; - }; - }; -}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts deleted file mode 100644 index 7a4614e3f..000000000 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ /dev/null @@ -1,197 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP ZCU104 - * - * (C) Copyright 2017 - 2019, Xilinx, Inc. - * - * Michal Simek - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" -#include - -/ { - model = "ZynqMP ZCU104 RevA"; - compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; - - aliases { - ethernet0 = &gem3; - i2c0 = &i2c1; - mmc0 = &sdhci1; - rtc0 = &rtc; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &dcc; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>; - }; -}; - -&can1 { - status = "okay"; -}; - -&dcc { - status = "okay"; -}; - -&gem3 { - status = "okay"; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - }; -}; - -&gpio { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - /* Another connection to this bus via PL i2c via PCA9306 - u45 */ - i2c-mux@74 { /* u34 */ - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x74>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* - * IIC_EEPROM 1kB memory which uses 256B blocks - * where every block has different address. - * 0 - 256B address 0x54 - * 256B - 512B address 0x55 - * 512B - 768B address 0x56 - * 768B - 1024B address 0x57 - */ - eeprom@54 { /* u23 */ - compatible = "atmel,24c08"; - reg = <0x54>; - #address-cells = <1>; - #size-cells = <1>; - }; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ - reg = <0x6c>; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ - reg = <0x43>; - }; - irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ - reg = <0x4d>; - }; - }; - - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - tca6416_u97: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - /* - * IRQ not connected - * Lines: - * 0 - IRPS5401_ALERT_B - * 1 - HDMI_8T49N241_INT_ALM - * 2 - MAX6643_OT_B - * 3 - MAX6643_FANFAIL_B - * 5 - IIC_MUX_RESET_B - * 6 - GEM3_EXP_RESET_B - * 7 - FMC_LPC_PRSNT_M2C_B - * 4, 10 - 17 - not connected - */ - }; - }; - - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - - /* 3, 6 not connected */ - }; -}; - -&rtc { - status = "okay"; -}; - -&sata { - status = "okay"; - /* SATA OOB timing settings */ - ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; -}; - -/* SD1 with level shifter */ -&sdhci1 { - status = "okay"; - no-1-8-v; - disable-wp; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -/* ULPI SMSC USB3320 */ -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&watchdog0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts deleted file mode 100644 index 6e9efe233..000000000 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ /dev/null @@ -1,633 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP ZCU106 - * - * (C) Copyright 2016 - 2019, Xilinx, Inc. - * - * Michal Simek - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" -#include -#include - -/ { - model = "ZynqMP ZCU106 RevA"; - compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; - - aliases { - ethernet0 = &gem3; - i2c0 = &i2c0; - i2c1 = &i2c1; - mmc0 = &sdhci1; - rtc0 = &rtc; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &dcc; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - sw19 { - label = "sw19"; - gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; - linux,code = ; - wakeup-source; - autorepeat; - }; - }; - - leds { - compatible = "gpio-leds"; - heartbeat-led { - label = "heartbeat"; - gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - ina226-u76 { - compatible = "iio-hwmon"; - io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; - }; - ina226-u77 { - compatible = "iio-hwmon"; - io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; - }; - ina226-u78 { - compatible = "iio-hwmon"; - io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; - }; - ina226-u87 { - compatible = "iio-hwmon"; - io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; - }; - ina226-u85 { - compatible = "iio-hwmon"; - io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; - }; - ina226-u86 { - compatible = "iio-hwmon"; - io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; - }; - ina226-u93 { - compatible = "iio-hwmon"; - io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; - }; - ina226-u88 { - compatible = "iio-hwmon"; - io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; - }; - ina226-u15 { - compatible = "iio-hwmon"; - io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; - }; - ina226-u92 { - compatible = "iio-hwmon"; - io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; - }; - ina226-u79 { - compatible = "iio-hwmon"; - io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; - }; - ina226-u81 { - compatible = "iio-hwmon"; - io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; - }; - ina226-u80 { - compatible = "iio-hwmon"; - io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; - }; - ina226-u84 { - compatible = "iio-hwmon"; - io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; - }; - ina226-u16 { - compatible = "iio-hwmon"; - io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; - }; - ina226-u65 { - compatible = "iio-hwmon"; - io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; - }; - ina226-u74 { - compatible = "iio-hwmon"; - io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; - }; - ina226-u75 { - compatible = "iio-hwmon"; - io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; - }; -}; - -&can1 { - status = "okay"; -}; - -&dcc { - status = "okay"; -}; - -/* fpd_dma clk 667MHz, lpd_dma 500MHz */ -&fpd_dma_chan1 { - status = "okay"; -}; - -&fpd_dma_chan2 { - status = "okay"; -}; - -&fpd_dma_chan3 { - status = "okay"; -}; - -&fpd_dma_chan4 { - status = "okay"; -}; - -&fpd_dma_chan5 { - status = "okay"; -}; - -&fpd_dma_chan6 { - status = "okay"; -}; - -&fpd_dma_chan7 { - status = "okay"; -}; - -&fpd_dma_chan8 { - status = "okay"; -}; - -&gem3 { - status = "okay"; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - }; -}; - -&gpio { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - tca6416_u97: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; /* interrupt not connected */ - #gpio-cells = <2>; - /* - * IRQ not connected - * Lines: - * 0 - SFP_SI5328_INT_ALM - * 1 - HDMI_SI5328_INT_ALM - * 5 - IIC_MUX_RESET_B - * 6 - GEM3_EXP_RESET_B - * 10 - FMC_HPC0_PRSNT_M2C_B - * 11 - FMC_HPC1_PRSNT_M2C_B - * 2-4, 7, 12-17 - not connected - */ - }; - - tca6416_u61: gpio@21 { - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - /* - * IRQ not connected - * Lines: - * 0 - VCCPSPLL_EN - * 1 - MGTRAVCC_EN - * 2 - MGTRAVTT_EN - * 3 - VCCPSDDRPLL_EN - * 4 - MIO26_PMU_INPUT_LS - * 5 - PL_PMBUS_ALERT - * 6 - PS_PMBUS_ALERT - * 7 - MAXIM_PMBUS_ALERT - * 10 - PL_DDR4_VTERM_EN - * 11 - PL_DDR4_VPP_2V5_EN - * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON - * 13 - PS_DIMM_SUSPEND_EN - * 14 - PS_DDR4_VTERM_EN - * 15 - PS_DDR4_VPP_2V5_EN - * 16 - 17 - not connected - */ - }; - - i2c-mux@75 { /* u60 */ - compatible = "nxp,pca9544"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* PS_PMBUS */ - u76: ina226@40 { /* u76 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u76"; - reg = <0x40>; - shunt-resistor = <5000>; - }; - u77: ina226@41 { /* u77 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u77"; - reg = <0x41>; - shunt-resistor = <5000>; - }; - u78: ina226@42 { /* u78 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u78"; - reg = <0x42>; - shunt-resistor = <5000>; - }; - u87: ina226@43 { /* u87 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u87"; - reg = <0x43>; - shunt-resistor = <5000>; - }; - u85: ina226@44 { /* u85 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u85"; - reg = <0x44>; - shunt-resistor = <5000>; - }; - u86: ina226@45 { /* u86 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u86"; - reg = <0x45>; - shunt-resistor = <5000>; - }; - u93: ina226@46 { /* u93 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u93"; - reg = <0x46>; - shunt-resistor = <5000>; - }; - u88: ina226@47 { /* u88 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u88"; - reg = <0x47>; - shunt-resistor = <5000>; - }; - u15: ina226@4a { /* u15 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u15"; - reg = <0x4a>; - shunt-resistor = <5000>; - }; - u92: ina226@4b { /* u92 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u92"; - reg = <0x4b>; - shunt-resistor = <5000>; - }; - }; - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - /* PL_PMBUS */ - u79: ina226@40 { /* u79 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u79"; - reg = <0x40>; - shunt-resistor = <2000>; - }; - u81: ina226@41 { /* u81 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u81"; - reg = <0x41>; - shunt-resistor = <5000>; - }; - u80: ina226@42 { /* u80 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u80"; - reg = <0x42>; - shunt-resistor = <5000>; - }; - u84: ina226@43 { /* u84 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u84"; - reg = <0x43>; - shunt-resistor = <5000>; - }; - u16: ina226@44 { /* u16 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u16"; - reg = <0x44>; - shunt-resistor = <5000>; - }; - u65: ina226@45 { /* u65 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u65"; - reg = <0x45>; - shunt-resistor = <5000>; - }; - u74: ina226@46 { /* u74 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u74"; - reg = <0x46>; - shunt-resistor = <5000>; - }; - u75: ina226@47 { /* u75 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u75"; - reg = <0x47>; - shunt-resistor = <5000>; - }; - }; - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - /* MAXIM_PMBUS - 00 */ - max15301@a { /* u46 */ - compatible = "maxim,max15301"; - reg = <0xa>; - }; - max15303@b { /* u4 */ - compatible = "maxim,max15303"; - reg = <0xb>; - }; - max15303@10 { /* u13 */ - compatible = "maxim,max15303"; - reg = <0x10>; - }; - max15301@13 { /* u47 */ - compatible = "maxim,max15301"; - reg = <0x13>; - }; - max15303@14 { /* u7 */ - compatible = "maxim,max15303"; - reg = <0x14>; - }; - max15303@15 { /* u6 */ - compatible = "maxim,max15303"; - reg = <0x15>; - }; - max15303@16 { /* u10 */ - compatible = "maxim,max15303"; - reg = <0x16>; - }; - max15303@17 { /* u9 */ - compatible = "maxim,max15303"; - reg = <0x17>; - }; - max15301@18 { /* u63 */ - compatible = "maxim,max15301"; - reg = <0x18>; - }; - max15303@1a { /* u49 */ - compatible = "maxim,max15303"; - reg = <0x1a>; - }; - max15303@1b { /* u8 */ - compatible = "maxim,max15303"; - reg = <0x1b>; - }; - max15303@1d { /* u18 */ - compatible = "maxim,max15303"; - reg = <0x1d>; - }; - - max20751@72 { /* u95 */ - compatible = "maxim,max20751"; - reg = <0x72>; - }; - max20751@73 { /* u96 */ - compatible = "maxim,max20751"; - reg = <0x73>; - }; - }; - /* Bus 3 is not connected */ - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - /* PL i2c via PCA9306 - u45 */ - i2c-mux@74 { /* u34 */ - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x74>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* - * IIC_EEPROM 1kB memory which uses 256B blocks - * where every block has different address. - * 0 - 256B address 0x54 - * 256B - 512B address 0x55 - * 512B - 768B address 0x56 - * 768B - 1024B address 0x57 - */ - eeprom: eeprom@54 { /* u23 */ - compatible = "atmel,24c08"; - reg = <0x54>; - }; - }; - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - si5341: clock-generator@36 { /* SI5341 - u69 */ - reg = <0x36>; - }; - - }; - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - si570_1: clock-generator@5d { /* USER SI570 - u42 */ - #clock-cells = <0>; - compatible = "silabs,si570"; - reg = <0x5d>; - temperature-stability = <50>; - factory-fout = <300000000>; - clock-frequency = <300000000>; - clock-output-names = "si570_user"; - }; - }; - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ - #clock-cells = <0>; - compatible = "silabs,si570"; - reg = <0x5d>; - temperature-stability = <50>; /* copy from zc702 */ - factory-fout = <156250000>; - clock-frequency = <148500000>; - clock-output-names = "si570_mgt"; - }; - }; - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - si5328: clock-generator@69 {/* SI5328 - u20 */ - reg = <0x69>; - }; - }; - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; /* FAN controller */ - temp@4c {/* lm96163 - u128 */ - compatible = "national,lm96163"; - reg = <0x4c>; - }; - }; - /* 6 - 7 unconnected */ - }; - - i2c-mux@75 { - compatible = "nxp,pca9548"; /* u135 */ - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* HPC0_IIC */ - }; - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - /* HPC1_IIC */ - }; - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - /* SYSMON */ - }; - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - /* DDR4 SODIMM */ - }; - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - /* SEP 3 */ - }; - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - /* SEP 2 */ - }; - i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - /* SEP 1 */ - }; - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - /* SEP 0 */ - }; - }; -}; - -&rtc { - status = "okay"; -}; - -&sata { - status = "okay"; - /* SATA OOB timing settings */ - ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; -}; - -/* SD1 with level shifter */ -&sdhci1 { - status = "okay"; - no-1-8-v; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -/* ULPI SMSC USB3320 */ -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&watchdog0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts deleted file mode 100644 index 2e92634c7..000000000 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ /dev/null @@ -1,531 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP ZCU111 - * - * (C) Copyright 2017 - 2019, Xilinx, Inc. - * - * Michal Simek - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk-ccf.dtsi" -#include -#include - -/ { - model = "ZynqMP ZCU111 RevA"; - compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; - - aliases { - ethernet0 = &gem3; - i2c0 = &i2c0; - i2c1 = &i2c1; - mmc0 = &sdhci1; - rtc0 = &rtc; - serial0 = &uart0; - serial1 = &dcc; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; - /* Another 4GB connected to PL */ - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - sw19 { - label = "sw19"; - gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; - linux,code = ; - wakeup-source; - autorepeat; - }; - }; - - leds { - compatible = "gpio-leds"; - heartbeat-led { - label = "heartbeat"; - gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - ina226-u67 { - compatible = "iio-hwmon"; - io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; - }; - ina226-u59 { - compatible = "iio-hwmon"; - io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; - }; - ina226-u61 { - compatible = "iio-hwmon"; - io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; - }; - ina226-u60 { - compatible = "iio-hwmon"; - io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; - }; - ina226-u64 { - compatible = "iio-hwmon"; - io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; - }; - ina226-u69 { - compatible = "iio-hwmon"; - io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; - }; - ina226-u66 { - compatible = "iio-hwmon"; - io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; - }; - ina226-u65 { - compatible = "iio-hwmon"; - io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; - }; - ina226-u63 { - compatible = "iio-hwmon"; - io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; - }; - ina226-u3 { - compatible = "iio-hwmon"; - io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; - }; - ina226-u71 { - compatible = "iio-hwmon"; - io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; - }; - ina226-u77 { - compatible = "iio-hwmon"; - io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; - }; - ina226-u73 { - compatible = "iio-hwmon"; - io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; - }; - ina226-u79 { - compatible = "iio-hwmon"; - io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; - }; -}; - -&dcc { - status = "okay"; -}; - -&fpd_dma_chan1 { - status = "okay"; -}; - -&fpd_dma_chan2 { - status = "okay"; -}; - -&fpd_dma_chan3 { - status = "okay"; -}; - -&fpd_dma_chan4 { - status = "okay"; -}; - -&fpd_dma_chan5 { - status = "okay"; -}; - -&fpd_dma_chan6 { - status = "okay"; -}; - -&fpd_dma_chan7 { - status = "okay"; -}; - -&fpd_dma_chan8 { - status = "okay"; -}; - -&gem3 { - status = "okay"; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - }; -}; - -&gpio { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - tca6416_u22: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; /* interrupt not connected */ - #gpio-cells = <2>; - /* - * IRQ not connected - * Lines: - * 0 - MAX6643_OT_B - * 1 - MAX6643_FANFAIL_B - * 2 - MIO26_PMU_INPUT_LS - * 4 - SFP_SI5382_INT_ALM - * 5 - IIC_MUX_RESET_B - * 6 - GEM3_EXP_RESET_B - * 10 - FMCP_HSPC_PRSNT_M2C_B - * 11 - CLK_SPI_MUX_SEL0 - * 12 - CLK_SPI_MUX_SEL1 - * 16 - IRPS5401_ALERT_B - * 17 - INA226_PMBUS_ALERT - * 3, 7, 13-15 - not connected - */ - }; - - i2c-mux@75 { /* u23 */ - compatible = "nxp,pca9544"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* PS_PMBUS */ - /* PMBUS_ALERT done via pca9544 */ - u67: ina226@40 { /* u67 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u67"; - reg = <0x40>; - shunt-resistor = <2000>; - }; - u59: ina226@41 { /* u59 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u59"; - reg = <0x41>; - shunt-resistor = <5000>; - }; - u61: ina226@42 { /* u61 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u61"; - reg = <0x42>; - shunt-resistor = <5000>; - }; - u60: ina226@43 { /* u60 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u60"; - reg = <0x43>; - shunt-resistor = <5000>; - }; - u64: ina226@45 { /* u64 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u64"; - reg = <0x45>; - shunt-resistor = <5000>; - }; - u69: ina226@46 { /* u69 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u69"; - reg = <0x46>; - shunt-resistor = <2000>; - }; - u66: ina226@47 { /* u66 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u66"; - reg = <0x47>; - shunt-resistor = <5000>; - }; - u65: ina226@48 { /* u65 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u65"; - reg = <0x48>; - shunt-resistor = <5000>; - }; - u63: ina226@49 { /* u63 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u63"; - reg = <0x49>; - shunt-resistor = <5000>; - }; - u3: ina226@4a { /* u3 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u3"; - reg = <0x4a>; - shunt-resistor = <5000>; - }; - u71: ina226@4b { /* u71 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u71"; - reg = <0x4b>; - shunt-resistor = <5000>; - }; - u77: ina226@4c { /* u77 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u77"; - reg = <0x4c>; - shunt-resistor = <5000>; - }; - u73: ina226@4d { /* u73 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u73"; - reg = <0x4d>; - shunt-resistor = <5000>; - }; - u79: ina226@4e { /* u79 */ - compatible = "ti,ina226"; - #io-channel-cells = <1>; - label = "ina226-u79"; - reg = <0x4e>; - shunt-resistor = <5000>; - }; - }; - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - /* NC */ - }; - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ - reg = <0x43>; - }; - irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ - reg = <0x44>; - }; - irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ - reg = <0x45>; - }; - /* u68 IR38064 +0 */ - /* u70 IR38060 +1 */ - /* u74 IR38060 +2 */ - /* u75 IR38060 +6 */ - /* J19 header too */ - - }; - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - /* SYSMON */ - }; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - i2c-mux@74 { /* u26 */ - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x74>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* - * IIC_EEPROM 1kB memory which uses 256B blocks - * where every block has different address. - * 0 - 256B address 0x54 - * 256B - 512B address 0x55 - * 512B - 768B address 0x56 - * 768B - 1024B address 0x57 - */ - eeprom: eeprom@54 { /* u88 */ - compatible = "atmel,24c08"; - reg = <0x54>; - }; - }; - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - si5341: clock-generator@36 { /* SI5341 - u46 */ - reg = <0x36>; - }; - - }; - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - si570_1: clock-generator@5d { /* USER SI570 - u47 */ - #clock-cells = <0>; - compatible = "silabs,si570"; - reg = <0x5d>; - temperature-stability = <50>; - factory-fout = <300000000>; - clock-frequency = <300000000>; - clock-output-names = "si570_user"; - }; - }; - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ - #clock-cells = <0>; - compatible = "silabs,si570"; - reg = <0x5d>; - temperature-stability = <50>; - factory-fout = <156250000>; - clock-frequency = <156250000>; - clock-output-names = "si570_mgt"; - }; - }; - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - si5328: clock-generator@69 { /* SI5328 - u48 */ - reg = <0x69>; - }; - }; - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - sc18is603@2f { /* sc18is602 - u93 */ - compatible = "nxp,sc18is603"; - reg = <0x2f>; - /* 4 gpios for CS not handled by driver */ - /* - * USB2ANY cable or - * LMK04208 - u90 or - * LMX2594 - u102 or - * LMX2594 - u103 or - * LMX2594 - u104 - */ - }; - }; - i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - /* FMC connector */ - }; - /* 7 NC */ - }; - - i2c-mux@75 { - compatible = "nxp,pca9548"; /* u27 */ - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* FMCP_HSPC_IIC */ - }; - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - /* NC */ - }; - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - /* SYSMON */ - }; - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - /* DDR4 SODIMM */ - }; - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - /* SFP3 */ - }; - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - /* SFP2 */ - }; - i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - /* SFP1 */ - }; - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - /* SFP0 */ - }; - }; -}; - -&rtc { - status = "okay"; -}; - -&sata { - status = "okay"; - /* SATA OOB timing settings */ - ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; -}; - -/* SD1 with level shifter */ -&sdhci1 { - status = "okay"; - no-1-8-v; -}; - -&uart0 { - status = "okay"; -}; - -/* ULPI SMSC USB3320 */ -&usb0 { - status = "okay"; - dr_mode = "host"; -}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi deleted file mode 100644 index 9e198cacc..000000000 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ /dev/null @@ -1,739 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dts file for Xilinx ZynqMP - * - * (C) Copyright 2014 - 2019, Xilinx, Inc. - * - * Michal Simek - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#include -#include - -/ { - compatible = "xlnx,zynqmp"; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - operating-points-v2 = <&cpu_opp_table>; - reg = <0x0>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x1>; - operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x2>; - operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x3>; - operating-points-v2 = <&cpu_opp_table>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x40000000>; - local-timer-stop; - entry-latency-us = <300>; - exit-latency-us = <600>; - min-residency-us = <10000>; - }; - }; - }; - - cpu_opp_table: cpu-opp-table { - compatible = "operating-points-v2"; - opp-shared; - opp00 { - opp-hz = /bits/ 64 <1199999988>; - opp-microvolt = <1000000>; - clock-latency-ns = <500000>; - }; - opp01 { - opp-hz = /bits/ 64 <599999994>; - opp-microvolt = <1000000>; - clock-latency-ns = <500000>; - }; - opp02 { - opp-hz = /bits/ 64 <399999996>; - opp-microvolt = <1000000>; - clock-latency-ns = <500000>; - }; - opp03 { - opp-hz = /bits/ 64 <299999997>; - opp-microvolt = <1000000>; - clock-latency-ns = <500000>; - }; - }; - - dcc: dcc { - compatible = "arm,dcc"; - status = "disabled"; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupt-parent = <&gic>; - interrupts = <0 143 4>, - <0 144 4>, - <0 145 4>, - <0 146 4>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - firmware { - zynqmp_firmware: zynqmp-firmware { - compatible = "xlnx,zynqmp-firmware"; - #power-domain-cells = <1>; - method = "smc"; - - zynqmp_power: zynqmp-power { - compatible = "xlnx,zynqmp-power"; - interrupt-parent = <&gic>; - interrupts = <0 35 4>; - }; - - zynqmp_clk: clock-controller { - #clock-cells = <1>; - compatible = "xlnx,zynqmp-clk"; - clocks = <&pss_ref_clk>, - <&video_clk>, - <&pss_alt_ref_clk>, - <&aux_ref_clk>, - <>_crx_ref_clk>; - clock-names = "pss_ref_clk", - "video_clk", - "pss_alt_ref_clk", - "aux_ref_clk", - "gt_crx_ref_clk"; - }; - - nvmem_firmware { - compatible = "xlnx,zynqmp-nvmem-fw"; - #address-cells = <1>; - #size-cells = <1>; - - soc_revision: soc_revision@0 { - reg = <0x0 0x4>; - }; - }; - - zynqmp_pcap: pcap { - compatible = "xlnx,zynqmp-pcap-fpga"; - }; - - xlnx_aes: zynqmp-aes { - compatible = "xlnx,zynqmp-aes"; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - fpga_full: fpga-full { - compatible = "fpga-region"; - fpga-mgr = <&zynqmp_pcap>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - }; - - amba_apu: axi@0 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0 0xffffffff>; - - gic: interrupt-controller@f9010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - reg = <0x0 0xf9010000 0x10000>, - <0x0 0xf9020000 0x20000>, - <0x0 0xf9040000 0x20000>, - <0x0 0xf9060000 0x20000>; - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <1 9 0xf04>; - }; - }; - - amba: axi { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - can0: can@ff060000 { - compatible = "xlnx,zynq-can-1.0"; - status = "disabled"; - clock-names = "can_clk", "pclk"; - reg = <0x0 0xff060000 0x0 0x1000>; - interrupts = <0 23 4>; - interrupt-parent = <&gic>; - tx-fifo-depth = <0x40>; - rx-fifo-depth = <0x40>; - power-domains = <&zynqmp_firmware PD_CAN_0>; - }; - - can1: can@ff070000 { - compatible = "xlnx,zynq-can-1.0"; - status = "disabled"; - clock-names = "can_clk", "pclk"; - reg = <0x0 0xff070000 0x0 0x1000>; - interrupts = <0 24 4>; - interrupt-parent = <&gic>; - tx-fifo-depth = <0x40>; - rx-fifo-depth = <0x40>; - power-domains = <&zynqmp_firmware PD_CAN_1>; - }; - - cci: cci@fd6e0000 { - compatible = "arm,cci-400"; - reg = <0x0 0xfd6e0000 0x0 0x9000>; - ranges = <0x0 0x0 0xfd6e0000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - - pmu@9000 { - compatible = "arm,cci-400-pmu,r1"; - reg = <0x9000 0x5000>; - interrupt-parent = <&gic>; - interrupts = <0 123 4>, - <0 123 4>, - <0 123 4>, - <0 123 4>, - <0 123 4>; - }; - }; - - /* GDMA */ - fpd_dma_chan1: dma@fd500000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd500000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 124 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <128>; - power-domains = <&zynqmp_firmware PD_GDMA>; - }; - - fpd_dma_chan2: dma@fd510000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd510000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 125 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <128>; - power-domains = <&zynqmp_firmware PD_GDMA>; - }; - - fpd_dma_chan3: dma@fd520000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd520000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 126 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <128>; - power-domains = <&zynqmp_firmware PD_GDMA>; - }; - - fpd_dma_chan4: dma@fd530000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd530000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 127 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <128>; - power-domains = <&zynqmp_firmware PD_GDMA>; - }; - - fpd_dma_chan5: dma@fd540000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd540000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 128 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <128>; - power-domains = <&zynqmp_firmware PD_GDMA>; - }; - - fpd_dma_chan6: dma@fd550000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd550000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 129 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <128>; - power-domains = <&zynqmp_firmware PD_GDMA>; - }; - - fpd_dma_chan7: dma@fd560000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd560000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 130 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <128>; - power-domains = <&zynqmp_firmware PD_GDMA>; - }; - - fpd_dma_chan8: dma@fd570000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xfd570000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 131 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <128>; - power-domains = <&zynqmp_firmware PD_GDMA>; - }; - - /* LPDDMA default allows only secured access. inorder to enable - * These dma channels, Users should ensure that these dma - * Channels are allowed for non secure access. - */ - lpd_dma_chan1: dma@ffa80000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffa80000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 77 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <64>; - power-domains = <&zynqmp_firmware PD_ADMA>; - }; - - lpd_dma_chan2: dma@ffa90000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffa90000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 78 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <64>; - power-domains = <&zynqmp_firmware PD_ADMA>; - }; - - lpd_dma_chan3: dma@ffaa0000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffaa0000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 79 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <64>; - power-domains = <&zynqmp_firmware PD_ADMA>; - }; - - lpd_dma_chan4: dma@ffab0000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffab0000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 80 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <64>; - power-domains = <&zynqmp_firmware PD_ADMA>; - }; - - lpd_dma_chan5: dma@ffac0000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffac0000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 81 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <64>; - power-domains = <&zynqmp_firmware PD_ADMA>; - }; - - lpd_dma_chan6: dma@ffad0000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffad0000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 82 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <64>; - power-domains = <&zynqmp_firmware PD_ADMA>; - }; - - lpd_dma_chan7: dma@ffae0000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffae0000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 83 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <64>; - power-domains = <&zynqmp_firmware PD_ADMA>; - }; - - lpd_dma_chan8: dma@ffaf0000 { - status = "disabled"; - compatible = "xlnx,zynqmp-dma-1.0"; - reg = <0x0 0xffaf0000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = <0 84 4>; - clock-names = "clk_main", "clk_apb"; - xlnx,bus-width = <64>; - power-domains = <&zynqmp_firmware PD_ADMA>; - }; - - mc: memory-controller@fd070000 { - compatible = "xlnx,zynqmp-ddrc-2.40a"; - reg = <0x0 0xfd070000 0x0 0x30000>; - interrupt-parent = <&gic>; - interrupts = <0 112 4>; - }; - - gem0: ethernet@ff0b0000 { - compatible = "cdns,zynqmp-gem", "cdns,gem"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 57 4>, <0 57 4>; - reg = <0x0 0xff0b0000 0x0 0x1000>; - clock-names = "pclk", "hclk", "tx_clk"; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&zynqmp_firmware PD_ETH_0>; - }; - - gem1: ethernet@ff0c0000 { - compatible = "cdns,zynqmp-gem", "cdns,gem"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 59 4>, <0 59 4>; - reg = <0x0 0xff0c0000 0x0 0x1000>; - clock-names = "pclk", "hclk", "tx_clk"; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&zynqmp_firmware PD_ETH_1>; - }; - - gem2: ethernet@ff0d0000 { - compatible = "cdns,zynqmp-gem", "cdns,gem"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 61 4>, <0 61 4>; - reg = <0x0 0xff0d0000 0x0 0x1000>; - clock-names = "pclk", "hclk", "tx_clk"; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&zynqmp_firmware PD_ETH_2>; - }; - - gem3: ethernet@ff0e0000 { - compatible = "cdns,zynqmp-gem", "cdns,gem"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 63 4>, <0 63 4>; - reg = <0x0 0xff0e0000 0x0 0x1000>; - clock-names = "pclk", "hclk", "tx_clk"; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&zynqmp_firmware PD_ETH_3>; - }; - - gpio: gpio@ff0a0000 { - compatible = "xlnx,zynqmp-gpio-1.0"; - status = "disabled"; - #gpio-cells = <0x2>; - gpio-controller; - interrupt-parent = <&gic>; - interrupts = <0 16 4>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0xff0a0000 0x0 0x1000>; - power-domains = <&zynqmp_firmware PD_GPIO>; - }; - - i2c0: i2c@ff020000 { - compatible = "cdns,i2c-r1p14"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 17 4>; - reg = <0x0 0xff020000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&zynqmp_firmware PD_I2C_0>; - }; - - i2c1: i2c@ff030000 { - compatible = "cdns,i2c-r1p14"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 18 4>; - reg = <0x0 0xff030000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&zynqmp_firmware PD_I2C_1>; - }; - - pcie: pcie@fd0e0000 { - compatible = "xlnx,nwl-pcie-2.11"; - status = "disabled"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - msi-controller; - device_type = "pci"; - interrupt-parent = <&gic>; - interrupts = <0 118 4>, - <0 117 4>, - <0 116 4>, - <0 115 4>, /* MSI_1 [63...32] */ - <0 114 4>; /* MSI_0 [31...0] */ - interrupt-names = "misc", "dummy", "intx", - "msi1", "msi0"; - msi-parent = <&pcie>; - reg = <0x0 0xfd0e0000 0x0 0x1000>, - <0x0 0xfd480000 0x0 0x1000>, - <0x80 0x00000000 0x0 0x1000000>; - reg-names = "breg", "pcireg", "cfg"; - ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ - 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ - bus-range = <0x00 0xff>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, - <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, - <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, - <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; - power-domains = <&zynqmp_firmware PD_PCIE>; - pcie_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - psgtr: phy@fd400000 { - compatible = "xlnx,zynqmp-psgtr-v1.1"; - status = "disabled"; - reg = <0x0 0xfd400000 0x0 0x40000>, - <0x0 0xfd3d0000 0x0 0x1000>; - reg-names = "serdes", "siou"; - #phy-cells = <4>; - }; - - rtc: rtc@ffa60000 { - compatible = "xlnx,zynqmp-rtc"; - status = "disabled"; - reg = <0x0 0xffa60000 0x0 0x100>; - interrupt-parent = <&gic>; - interrupts = <0 26 4>, <0 27 4>; - interrupt-names = "alarm", "sec"; - calibration = <0x8000>; - }; - - sata: ahci@fd0c0000 { - compatible = "ceva,ahci-1v84"; - status = "disabled"; - reg = <0x0 0xfd0c0000 0x0 0x2000>; - interrupt-parent = <&gic>; - interrupts = <0 133 4>; - power-domains = <&zynqmp_firmware PD_SATA>; - }; - - sdhci0: mmc@ff160000 { - compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 48 4>; - reg = <0x0 0xff160000 0x0 0x1000>; - clock-names = "clk_xin", "clk_ahb"; - #clock-cells = <1>; - clock-output-names = "clk_out_sd0", "clk_in_sd0"; - power-domains = <&zynqmp_firmware PD_SD_0>; - }; - - sdhci1: mmc@ff170000 { - compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 49 4>; - reg = <0x0 0xff170000 0x0 0x1000>; - clock-names = "clk_xin", "clk_ahb"; - #clock-cells = <1>; - clock-output-names = "clk_out_sd1", "clk_in_sd1"; - power-domains = <&zynqmp_firmware PD_SD_1>; - }; - - smmu: iommu@fd800000 { - compatible = "arm,mmu-500"; - reg = <0x0 0xfd800000 0x0 0x20000>; - status = "disabled"; - #global-interrupts = <1>; - interrupt-parent = <&gic>; - interrupts = <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; - }; - - spi0: spi@ff040000 { - compatible = "cdns,spi-r1p6"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 19 4>; - reg = <0x0 0xff040000 0x0 0x1000>; - clock-names = "ref_clk", "pclk"; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&zynqmp_firmware PD_SPI_0>; - }; - - spi1: spi@ff050000 { - compatible = "cdns,spi-r1p6"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 20 4>; - reg = <0x0 0xff050000 0x0 0x1000>; - clock-names = "ref_clk", "pclk"; - #address-cells = <1>; - #size-cells = <0>; - power-domains = <&zynqmp_firmware PD_SPI_1>; - }; - - ttc0: timer@ff110000 { - compatible = "cdns,ttc"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 36 4>, <0 37 4>, <0 38 4>; - reg = <0x0 0xff110000 0x0 0x1000>; - timer-width = <32>; - power-domains = <&zynqmp_firmware PD_TTC_0>; - }; - - ttc1: timer@ff120000 { - compatible = "cdns,ttc"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 39 4>, <0 40 4>, <0 41 4>; - reg = <0x0 0xff120000 0x0 0x1000>; - timer-width = <32>; - power-domains = <&zynqmp_firmware PD_TTC_1>; - }; - - ttc2: timer@ff130000 { - compatible = "cdns,ttc"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 42 4>, <0 43 4>, <0 44 4>; - reg = <0x0 0xff130000 0x0 0x1000>; - timer-width = <32>; - power-domains = <&zynqmp_firmware PD_TTC_2>; - }; - - ttc3: timer@ff140000 { - compatible = "cdns,ttc"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 45 4>, <0 46 4>, <0 47 4>; - reg = <0x0 0xff140000 0x0 0x1000>; - timer-width = <32>; - power-domains = <&zynqmp_firmware PD_TTC_3>; - }; - - uart0: serial@ff000000 { - compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 21 4>; - reg = <0x0 0xff000000 0x0 0x1000>; - clock-names = "uart_clk", "pclk"; - power-domains = <&zynqmp_firmware PD_UART_0>; - }; - - uart1: serial@ff010000 { - compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 22 4>; - reg = <0x0 0xff010000 0x0 0x1000>; - clock-names = "uart_clk", "pclk"; - power-domains = <&zynqmp_firmware PD_UART_1>; - }; - - usb0: usb@fe200000 { - compatible = "snps,dwc3"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 65 4>; - reg = <0x0 0xfe200000 0x0 0x40000>; - clock-names = "clk_xin", "clk_ahb"; - power-domains = <&zynqmp_firmware PD_USB_0>; - }; - - usb1: usb@fe300000 { - compatible = "snps,dwc3"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 70 4>; - reg = <0x0 0xfe300000 0x0 0x40000>; - clock-names = "clk_xin", "clk_ahb"; - power-domains = <&zynqmp_firmware PD_USB_1>; - }; - - watchdog0: watchdog@fd4d0000 { - compatible = "cdns,wdt-r1p2"; - status = "disabled"; - interrupt-parent = <&gic>; - interrupts = <0 113 1>; - reg = <0x0 0xfd4d0000 0x0 0x1000>; - timeout-sec = <10>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/zte/Makefile b/arch/arm64/boot/dts/zte/Makefile deleted file mode 100644 index 126896144..000000000 --- a/arch/arm64/boot/dts/zte/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -dtb-$(CONFIG_ARCH_ZX) += zx296718-evb.dtb -dtb-$(CONFIG_ARCH_ZX) += zx296718-pcbox.dtb diff --git a/arch/arm64/boot/dts/zte/zx296718-evb.dts b/arch/arm64/boot/dts/zte/zx296718-evb.dts deleted file mode 100644 index cb2519ecd..000000000 --- a/arch/arm64/boot/dts/zte/zx296718-evb.dts +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright 2016 ZTE Corporation. - * Copyright 2016 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "zx296718.dtsi" - -/ { - model = "ZTE zx296718 evaluation board"; - compatible = "zte,zx296718-evb", "zte,zx296718"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x40000000>; - }; - - sound-spdif0 { - compatible = "audio-graph-card"; - dais = <&spdif0_port>; - }; - - sound-i2s0 { - compatible = "audio-graph-card"; - dais = <&i2s0_port>; - pinctrl-names = "default"; - pinctrl-0 = <&lifier_pins>; - pa-gpios = <&bgpio4 0 GPIO_ACTIVE_HIGH>; - widgets = "Line", "Line Out Jack"; - routing = "Amplifier", "LINEOUTL", - "Amplifier", "LINEOUTR", - "Line Out Jack", "Amplifier"; - }; -}; - -&aud96p22 { - port { - aud96p22_endpoint: endpoint { - remote-endpoint = <&i2s0_endpoint>; - }; - }; -}; - -&emmc { - status = "okay"; -}; - -&hdmi { - status = "okay"; - - port { - hdmi_endpoint: endpoint { - remote-endpoint = <&spdif0_endpoint>; - }; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&i2s0 { - status = "okay"; - - i2s0_port: port { - i2s0_endpoint: endpoint { - remote-endpoint = <&aud96p22_endpoint>; - dai-format = "i2s"; - frame-master; - bitclock-master; - }; - }; -}; - -&pmm { - amplifier_pins: amplifier { - pins = "TSI3_DATA"; - function = "BGPIO"; - }; -}; - -&sd1 { - status = "okay"; -}; - -&spdif0 { - status = "okay"; - - spdif0_port: port { - spdif0_endpoint: endpoint { - remote-endpoint = <&hdmi_endpoint>; - }; - }; -}; - -&tvenc { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/zte/zx296718-pcbox.dts b/arch/arm64/boot/dts/zte/zx296718-pcbox.dts deleted file mode 100644 index e02509f70..000000000 --- a/arch/arm64/boot/dts/zte/zx296718-pcbox.dts +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (C) 2017 Sanechips Technology Co., Ltd. - * Copyright 2017 Linaro Ltd. - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -/dts-v1/; -#include "zx296718.dtsi" -#include - -/ { - model = "ZTE ZX296718 PCBOX Board"; - compatible = "zte,zx296718-pcbox", "zte,zx296718"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - a53_vdd0v9: regulator-a53 { - compatible = "pwm-regulator"; - pwms = <&pwm 3 1250 PWM_POLARITY_INVERTED>; - regulator-name = "A53_VDD0V9"; - regulator-min-microvolt = <855000>; - regulator-max-microvolt = <1183000>; - pwm-dutycycle-unit = <100>; - pwm-dutycycle-range = <0 100>; - regulator-always-on; - regulator-boot-on; - }; - - sound-spdif0 { - compatible = "audio-graph-card"; - dais = <&spdif0_port>; - }; - - sound-i2s0 { - compatible = "audio-graph-card"; - dais = <&i2s0_port>; - }; -}; - -&aud96p22 { - port { - aud96p22_endpoint: endpoint { - remote-endpoint = <&i2s0_endpoint>; - }; - }; -}; - -&cpu0 { - cpu-supply = <&a53_vdd0v9>; -}; - -&emmc { - status = "okay"; -}; - -&hdmi { - status = "disabled"; - - port { - hdmi_endpoint: endpoint { - remote-endpoint = <&spdif0_endpoint>; - }; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&i2s0 { - status = "okay"; - - i2s0_port: port { - i2s0_endpoint: endpoint { - remote-endpoint = <&aud96p22_endpoint>; - dai-format = "i2s"; - frame-master; - bitclock-master; - }; - }; -}; - -&irdec { - status = "okay"; -}; - -&pmm { - pwm3_pins: pwm3 { - pins = "KEY_ROW2"; - function = "PWM"; - }; - - vga_pins: vga { - pins = "KEY_COL1", "KEY_COL2", "VGA_HS", "VGA_VS"; - function = "VGA"; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins>; - status = "okay"; -}; - -&sd0 { - status = "okay"; -}; - -&sd1 { - status = "okay"; -}; - -&spdif0 { - status = "okay"; - - spdif0_port: port { - spdif0_endpoint: endpoint { - remote-endpoint = <&hdmi_endpoint>; - }; - }; -}; - -&tvenc { - status = "disabled"; -}; - -&uart0 { - status = "okay"; -}; - -&vga { - pinctrl-names = "default"; - pinctrl-0 = <&vga_pins>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi deleted file mode 100644 index cc54837ff..000000000 --- a/arch/arm64/boot/dts/zte/zx296718.dtsi +++ /dev/null @@ -1,627 +0,0 @@ -/* - * Copyright 2016 ZTE Corporation. - * Copyright 2016 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include - -/ { - compatible = "zte,zx296718"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - aliases { - gpio0 = &bgpio0; - gpio1 = &bgpio1; - gpio2 = &bgpio2; - gpio3 = &bgpio3; - gpio4 = &bgpio4; - gpio5 = &bgpio5; - gpio6 = &bgpio6; - serial0 = &uart0; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - core1 { - cpu = <&cpu1>; - }; - core2 { - cpu = <&cpu2>; - }; - core3 { - cpu = <&cpu3>; - }; - }; - }; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - enable-method = "psci"; - clocks = <&topcrm A53_GATE>; - operating-points-v2 = <&cluster0_opp>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - enable-method = "psci"; - clocks = <&topcrm A53_GATE>; - operating-points-v2 = <&cluster0_opp>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - enable-method = "psci"; - clocks = <&topcrm A53_GATE>; - operating-points-v2 = <&cluster0_opp>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - enable-method = "psci"; - clocks = <&topcrm A53_GATE>; - operating-points-v2 = <&cluster0_opp>; - }; - }; - - cluster0_opp: opp-table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <866000>; - clock-latency-ns = <500000>; - }; - - opp-648000000 { - opp-hz = /bits/ 64 <648000000>; - opp-microvolt = <866000>; - clock-latency-ns = <500000>; - }; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <888000>; - clock-latency-ns = <500000>; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <898000>; - clock-latency-ns = <500000>; - }; - - opp-1188000000 { - opp-hz = /bits/ 64 <1188000000>; - opp-microvolt = <1015000>; - clock-latency-ns = <500000>; - }; - }; - - clk24k: clk-24k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000>; - clock-output-names = "rtcclk"; - }; - - osc32k: clk-osc32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - clock-output-names = "osc32k"; - }; - - osc12m: clk-osc12m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - clock-output-names = "osc12m"; - }; - - osc24m: clk-osc24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc24m"; - }; - - osc25m: clk-osc25m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "osc25m"; - }; - - osc60m: clk-osc60m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <60000000>; - clock-output-names = "osc60m"; - }; - - osc99m: clk-osc99m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <99000000>; - clock-output-names = "osc99m"; - }; - - osc125m: clk-osc125m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "osc125m"; - }; - - osc198m: clk-osc198m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <198000000>; - clock-output-names = "osc198m"; - }; - - pll_audio: clk-pll-884m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <884000000>; - clock-output-names = "pll_audio"; - }; - - pll_ddr: clk-pll-932m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <932000000>; - clock-output-names = "pll_ddr"; - }; - - pll_hsic: clk-pll-960m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <960000000>; - clock-output-names = "pll_hsic"; - }; - - pll_mac: clk-pll-1000m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000000>; - clock-output-names = "pll_mac"; - }; - - pll_mm0: clk-pll-1188m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1188000000>; - clock-output-names = "pll_mm0"; - }; - - pll_mm1: clk-pll-1296m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1296000000>; - clock-output-names = "pll_mm1"; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - }; - - gic: interrupt-controller@2a00000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x02a00000 0x10000>, - <0x02b00000 0xc0000>; - interrupts = ; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - irdec: ir-decoder@111000 { - compatible = "zte,zx296718-irdec"; - reg = <0x111000 0x1000>; - interrupts = ; - status = "disabled"; - }; - - aon_sysctrl: aon-sysctrl@116000 { - compatible = "zte,zx296718-aon-sysctrl", "syscon"; - reg = <0x116000 0x1000>; - }; - - iocfg: pin-controller@119000 { - compatible = "zte,zx296718-iocfg"; - reg = <0x119000 0x1000>; - }; - - uart0: uart@11f000 { - compatible = "arm,pl011", "arm,primecell"; - arm,primecell-periphid = <0x001feffe>; - reg = <0x11f000 0x1000>; - interrupts = ; - clocks = <&osc24m>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - sd0: mmc@1110000 { - compatible = "zte,zx296718-dw-mshc"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x01110000 0x1000>; - interrupts = ; - fifo-depth = <32>; - data-addr = <0x200>; - fifo-watermark-aligned; - bus-width = <4>; - clock-frequency = <50000000>; - clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>; - clock-names = "biu", "ciu"; - max-frequency = <50000000>; - cap-sdio-irq; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - sd-uhs-ddr50; - status = "disabled"; - }; - - sd1: mmc@1111000 { - compatible = "zte,zx296718-dw-mshc"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x01111000 0x1000>; - interrupts = ; - fifo-depth = <32>; - data-addr = <0x200>; - fifo-watermark-aligned; - bus-width = <4>; - clock-frequency = <167000000>; - clocks = <&topcrm SD1_AHB>, <&topcrm SD1_WCLK>; - clock-names = "biu", "ciu"; - max-frequency = <167000000>; - cap-sdio-irq; - cap-sd-highspeed; - status = "disabled"; - }; - - dma: dma-controller@1460000 { - compatible = "zte,zx296702-dma"; - reg = <0x01460000 0x1000>; - interrupts = ; - clocks = <&osc24m>; - clock-names = "dmaclk"; - #dma-cells = <1>; - dma-channels = <32>; - dma-requests = <32>; - }; - - lsp0crm: clock-controller@1420000 { - compatible = "zte,zx296718-lsp0crm"; - reg = <0x01420000 0x1000>; - #clock-cells = <1>; - }; - - bgpio0: gpio@142d000 { - compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; - reg = <0x142d000 0x40>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmm 0 48 16>; - interrupts = ; - interrupt-parent = <&gic>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - bgpio1: gpio@142d040 { - compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; - reg = <0x142d040 0x40>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmm 0 80 16>; - interrupts = ; - interrupt-parent = <&gic>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - bgpio2: gpio@142d080 { - compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; - reg = <0x142d080 0x40>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmm 0 80 3 - &pmm 3 32 4 - &pmm 7 83 9>; - interrupts = ; - interrupt-parent = <&gic>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - bgpio3: gpio@142d0c0 { - compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; - reg = <0x142d0c0 0x40>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmm 0 92 16>; - interrupts = ; - interrupt-parent = <&gic>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - bgpio4: gpio@142d100 { - compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; - reg = <0x142d100 0x40>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmm 0 108 12 - &pmm 12 121 4>; - interrupts = ; - interrupt-parent = <&gic>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - bgpio5: gpio@142d140 { - compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; - reg = <0x142d140 0x40>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmm 0 125 16>; - interrupts = ; - interrupt-parent = <&gic>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - bgpio6: gpio@142d180 { - compatible = "zte,zx296718-gpio", "zte,zx296702-gpio"; - reg = <0x142d180 0x40>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pmm 0 141 2>; - interrupts = ; - interrupt-parent = <&gic>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - lsp1crm: clock-controller@1430000 { - compatible = "zte,zx296718-lsp1crm"; - reg = <0x01430000 0x1000>; - #clock-cells = <1>; - }; - - pwm: pwm@1439000 { - compatible = "zte,zx296718-pwm"; - reg = <0x1439000 0x1000>; - clocks = <&lsp1crm LSP1_PWM_PCLK>, - <&lsp1crm LSP1_PWM_WCLK>; - clock-names = "pclk", "wclk"; - #pwm-cells = <3>; - status = "disabled"; - }; - - vou: vou@1440000 { - compatible = "zte,zx296718-vou"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x1440000 0x10000>; - - dpc: dpc@0 { - compatible = "zte,zx296718-dpc"; - reg = <0x0000 0x1000>, <0x1000 0x1000>, - <0x5000 0x1000>, <0x6000 0x1000>, - <0xa000 0x1000>; - reg-names = "osd", "timing_ctrl", - "dtrc", "vou_ctrl", - "otfppu"; - interrupts = ; - clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>, - <&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>; - clock-names = "aclk", "ppu_wclk", - "main_wclk", "aux_wclk"; - }; - - vga: vga@8000 { - compatible = "zte,zx296718-vga"; - reg = <0x8000 0x1000>; - interrupts = ; - clocks = <&topcrm VGA_I2C_WCLK>; - clock-names = "i2c_wclk"; - zte,vga-power-control = <&sysctrl 0x170 0xe0>; - status = "disabled"; - }; - - hdmi: hdmi@c000 { - compatible = "zte,zx296718-hdmi"; - reg = <0xc000 0x4000>; - interrupts = ; - clocks = <&topcrm HDMI_OSC_CEC>, - <&topcrm HDMI_OSC_CLK>, - <&topcrm HDMI_XCLK>; - clock-names = "osc_cec", "osc_clk", "xclk"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - tvenc: tvenc@2000 { - compatible = "zte,zx296718-tvenc"; - reg = <0x2000 0x1000>; - zte,tvenc-power-control = <&sysctrl 0x170 0x10>; - status = "disabled"; - }; - }; - - topcrm: clock-controller@1461000 { - compatible = "zte,zx296718-topcrm"; - reg = <0x01461000 0x1000>; - #clock-cells = <1>; - }; - - pmm: pin-controller@1462000 { - compatible = "zte,zx296718-pmm"; - reg = <0x1462000 0x1000>; - zte,auxiliary-controller = <&iocfg>; - }; - - sysctrl: sysctrl@1463000 { - compatible = "zte,zx296718-sysctrl", "syscon"; - reg = <0x1463000 0x1000>; - }; - - emmc: mmc@1470000{ - compatible = "zte,zx296718-dw-mshc"; - reg = <0x01470000 0x1000>; - interrupts = ; - zte,aon-syscon = <&aon_sysctrl>; - bus-width = <8>; - fifo-depth = <128>; - data-addr = <0x200>; - fifo-watermark-aligned; - clock-frequency = <167000000>; - clocks = <&topcrm EMMC_NAND_AHB>, <&topcrm EMMC_WCLK>; - clock-names = "biu", "ciu"; - max-frequency = <167000000>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - disable-wp; - status = "disabled"; - }; - - audiocrm: clock-controller@1480000 { - compatible = "zte,zx296718-audiocrm"; - reg = <0x01480000 0x1000>; - #clock-cells = <1>; - }; - - i2s0: i2s@1482000 { - compatible = "zte,zx296718-i2s", "zte,zx296702-i2s"; - reg = <0x01482000 0x1000>; - clocks = <&audiocrm AUDIO_I2S0_WCLK>, - <&audiocrm AUDIO_I2S0_PCLK>; - clock-names = "wclk", "pclk"; - assigned-clocks = <&audiocrm I2S0_WCLK_MUX>; - assigned-clock-parents = <&topcrm AUDIO_99M>; - interrupts = ; - dmas = <&dma 22>, <&dma 23>; - dma-names = "tx", "rx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2c0: i2c@1486000 { - compatible = "zte,zx296718-i2c"; - reg = <0x01486000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&audiocrm AUDIO_I2C0_WCLK>; - clock-frequency = <1600000>; - status = "disabled"; - - aud96p22: codec@22 { - compatible = "zte,zx-aud96p22"; - #sound-dai-cells = <0>; - reg = <0x22>; - }; - }; - - spdif0: spdif@1488000 { - compatible = "zte,zx296702-spdif"; - reg = <0x1488000 0x1000>; - clocks = <&audiocrm AUDIO_SPDIF0_WCLK>; - clock-names = "tx"; - interrupts = ; - #sound-dai-cells = <0>; - dmas = <&dma 30>; - dma-names = "tx"; - status = "disabled"; - }; - }; -};