diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi deleted file mode 100644 index cd7b5fdfd..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ /dev/null @@ -1,3707 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Rockchip Electronics Co., Ltd. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rk3568-dram-default-timing.dtsi" - -/ { - compatible = "rockchip,rk3568"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - csi2dphy0 = &csi2_dphy0; - csi2dphy1 = &csi2_dphy1; - csi2dphy2 = &csi2_dphy2; - dsi0 = &dsi0; - dsi1 = &dsi1; - ethernet0 = &gmac0; - ethernet1 = &gmac1; - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - mmc0 = &sdhci; - mmc1 = &sdmmc0; - mmc2 = &sdmmc1; - mmc3 = &sdmmc2; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - serial6 = &uart6; - serial7 = &uart7; - serial8 = &uart8; - serial9 = &uart9; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x0>; - enable-method = "psci"; - clocks = <&scmi_clk 0>; - operating-points-v2 = <&cpu0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - #cooling-cells = <2>; - dynamic-power-coefficient = <187>; - }; - - cpu1: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x100>; - enable-method = "psci"; - clocks = <&scmi_clk 0>; - operating-points-v2 = <&cpu0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - }; - - cpu2: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x200>; - enable-method = "psci"; - clocks = <&scmi_clk 0>; - operating-points-v2 = <&cpu0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - }; - - cpu3: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x300>; - enable-method = "psci"; - clocks = <&scmi_clk 0>; - operating-points-v2 = <&cpu0_opp_table>; - cpu-idle-states = <&CPU_SLEEP>; - }; - - idle-states { - entry-method = "psci"; - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <100>; - exit-latency-us = <120>; - min-residency-us = <1000>; - }; - }; - }; - - cpu0_opp_table: cpu0-opp-table { - compatible = "operating-points-v2"; - opp-shared; - - mbist-vmin = <825000 900000 950000>; - nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&cpu_opp_info>; - nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info"; - rockchip,max-volt = <1150000>; - rockchip,pvtm-voltage-sel = < - 0 84000 0 - 84001 87000 1 - 87001 91000 2 - 91001 100000 3 - >; - rockchip,pvtm-freq = <408000>; - rockchip,pvtm-volt = <900000>; - rockchip,pvtm-ch = <0 5>; - rockchip,pvtm-sample-time = <1000>; - rockchip,pvtm-number = <10>; - rockchip,pvtm-error = <1000>; - rockchip,pvtm-ref-temp = <40>; - rockchip,pvtm-temp-prop = <26 26>; - rockchip,thermal-zone = "soc-thermal"; - rockchip,temp-hysteresis = <5000>; - rockchip,low-temp = <0>; - rockchip,low-temp-adjust-volt = < - /* MHz MHz uV */ - 0 1992 75000 - >; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <850000 850000 1150000>; - clock-latency-ns = <40000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <850000 850000 1150000>; - clock-latency-ns = <40000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <850000 850000 1150000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-1104000000 { - opp-hz = /bits/ 64 <1104000000>; - opp-microvolt = <900000 900000 1150000>; - opp-microvolt-L0 = <900000 900000 1150000>; - opp-microvolt-L1 = <850000 850000 1150000>; - opp-microvolt-L2 = <850000 850000 1150000>; - opp-microvolt-L3 = <850000 850000 1150000>; - clock-latency-ns = <40000>; - }; - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1025000 1025000 1150000>; - opp-microvolt-L0 = <1025000 1025000 1150000>; - opp-microvolt-L1 = <975000 975000 1150000>; - opp-microvolt-L2 = <950000 950000 1150000>; - opp-microvolt-L3 = <925000 925000 1150000>; - clock-latency-ns = <40000>; - }; - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <1100000 1100000 1150000>; - opp-microvolt-L0 = <1100000 1100000 1150000>; - opp-microvolt-L1 = <1050000 1050000 1150000>; - opp-microvolt-L2 = <1025000 1025000 1150000>; - opp-microvolt-L3 = <1000000 1000000 1150000>; - clock-latency-ns = <40000>; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1150000 1150000 1150000>; - opp-microvolt-L0 = <1150000 1150000 1150000>; - opp-microvolt-L1 = <1100000 1100000 1150000>; - opp-microvolt-L2 = <1075000 1075000 1150000>; - opp-microvolt-L3 = <1050000 1050000 1150000>; - clock-latency-ns = <40000>; - }; - opp-1992000000 { - opp-hz = /bits/ 64 <1992000000>; - opp-microvolt = <1150000 1150000 1150000>; - opp-microvolt-L0 = <1150000 1150000 1150000>; - opp-microvolt-L1 = <1150000 1150000 1150000>; - opp-microvolt-L2 = <1125000 1125000 1150000>; - opp-microvolt-L3 = <1100000 1100000 1150000>; - clock-latency-ns = <40000>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - cpuinfo { - compatible = "rockchip,cpuinfo"; - nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; - nvmem-cell-names = "id", "cpu-version", "cpu-code"; - }; - - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - memory-region = <&drm_logo>, <&drm_cubic_lut>; - memory-region-names = "drm-logo", "drm-cubic-lut"; - ports = <&vop_out>; - devfreq = <&dmc>; - - route { - route_dsi0: route-dsi0 { - status = "disabled"; - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <&vp0_out_dsi0>; - }; - route_dsi1: route-dsi1 { - status = "disabled"; - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <&vp0_out_dsi1>; - }; - route_edp: route-edp { - status = "disabled"; - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <&vp0_out_edp>; - }; - route_hdmi: route-hdmi { - status = "disabled"; - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <&vp1_out_hdmi>; - }; - route_lvds: route-lvds { - status = "disabled"; - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <&vp1_out_lvds>; - }; - route_rgb: route-rgb { - status = "disabled"; - logo,uboot = "logo.bmp"; - logo,kernel = "logo_kernel.bmp"; - logo,mode = "center"; - charge_logo,mode = "center"; - connect = <&vp2_out_rgb>; - }; - }; - }; - - firmware { - scmi: scmi { - compatible = "arm,scmi-smc"; - shmem = <&scmi_shmem>; - arm,smc-id = <0x82000010>; - #address-cells = <1>; - #size-cells = <0>; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - - rockchip,clk-init = <1104000000>; - }; - }; - - sdei: sdei { - compatible = "arm,sdei-1.0"; - method = "smc"; - }; - }; - - mipi_csi2: mipi-csi2 { - compatible = "rockchip,rk3568-mipi-csi2"; - rockchip,hw = <&mipi_csi2_hw>; - status = "disabled"; - }; - - mpp_srv: mpp-srv { - compatible = "rockchip,mpp-service"; - rockchip,taskqueue-count = <6>; - rockchip,resetgroup-count = <6>; - status = "disabled"; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - drm_logo: drm-logo@00000000 { - compatible = "rockchip,drm-logo"; - reg = <0x0 0x0 0x0 0x0>; - }; - - drm_cubic_lut: drm-cubic-lut@00000000 { - compatible = "rockchip,drm-cubic-lut"; - reg = <0x0 0x0 0x0 0x0>; - }; - }; - - rockchip_suspend: rockchip-suspend { - compatible = "rockchip,pm-rk3568"; - status = "disabled"; - rockchip,sleep-debug-en = <1>; - rockchip,sleep-mode-config = < - (0 - | RKPM_SLP_ARMOFF_LOGOFF - | RKPM_SLP_CENTER_OFF - | RKPM_SLP_HW_PLLS_OFF - | RKPM_SLP_PMUALIVE_32K - | RKPM_SLP_OSC_DIS - | RKPM_SLP_PMIC_LP - | RKPM_SLP_32K_PVTM - ) - >; - rockchip,wakeup-config = < - (0 - | RKPM_GPIO_WKUP_EN - ) - >; - }; - - rockchip_system_monitor: rockchip-system-monitor { - compatible = "rockchip,system-monitor"; - - rockchip,thermal-zone = "soc-thermal"; - }; - - thermal_zones: thermal-zones { - soc_thermal: soc-thermal { - polling-delay-passive = <20>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - sustainable-power = <905>; /* milliwatts */ - - thermal-sensors = <&tsadc 0>; - trips { - threshold: trip-point-0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - target: trip-point-1 { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - soc_crit: soc-crit { - /* millicelsius */ - temperature = <115000>; - /* millicelsius */ - hysteresis = <2000>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <1024>; - }; - map1 { - trip = <&target>; - cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <1024>; - }; - }; - }; - - gpu_thermal: gpu-thermal { - polling-delay-passive = <20>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - - thermal-sensors = <&tsadc 1>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - arm,no-tick-in-suspend; - }; - - gmac0_clkin: external-gmac0-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac0_clkin"; - #clock-cells = <0>; - }; - - gmac1_clkin: external-gmac1-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac1_clkin"; - #clock-cells = <0>; - }; - - gmac0_xpcsclk: xpcs-gmac0-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clk_gmac0_xpcs_mii"; - #clock-cells = <0>; - }; - - gmac1_xpcsclk: xpcs-gmac1-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "clk_gmac1_xpcs_mii"; - #clock-cells = <0>; - }; - - i2s1_mclkin_rx: i2s1-mclkin-rx { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12288000>; - clock-output-names = "i2s1_mclkin_rx"; - }; - - i2s1_mclkin_tx: i2s1-mclkin-tx { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12288000>; - clock-output-names = "i2s1_mclkin_tx"; - }; - - i2s2_mclkin: i2s2-mclkin { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12288000>; - clock-output-names = "i2s2_mclkin"; - }; - - i2s3_mclkin: i2s3-mclkin { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12288000>; - clock-output-names = "i2s3_mclkin"; - }; - - mpll: mpll { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <800000000>; - clock-output-names = "mpll"; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - }; - - xin32k: xin32k { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - #clock-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&clk32k_out0>; - }; - - scmi_shmem: scmi-shmem@10f000 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x0010f000 0x0 0x100>; - }; - - sata0: sata@fc000000 { - compatible = "snps,dwc-ahci"; - reg = <0 0xfc000000 0 0x1000>; - clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, - <&cru CLK_SATA0_RXOOB>; - clock-names = "sata", "pmalive", "rxoob"; - interrupts = ; - interrupt-names = "hostc"; - phys = <&combphy0_us PHY_TYPE_SATA>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - power-domains = <&power RK3568_PD_PIPE>; - status = "disabled"; - }; - - sata1: sata@fc400000 { - compatible = "snps,dwc-ahci"; - reg = <0 0xfc400000 0 0x1000>; - clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, - <&cru CLK_SATA1_RXOOB>; - clock-names = "sata", "pmalive", "rxoob"; - interrupts = ; - interrupt-names = "hostc"; - phys = <&combphy1_usq PHY_TYPE_SATA>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - power-domains = <&power RK3568_PD_PIPE>; - status = "disabled"; - }; - - sata2: sata@fc800000 { - compatible = "snps,dwc-ahci"; - reg = <0 0xfc800000 0 0x1000>; - clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, - <&cru CLK_SATA2_RXOOB>; - clock-names = "sata", "pmalive", "rxoob"; - interrupts = ; - interrupt-names = "hostc"; - phys = <&combphy2_psq PHY_TYPE_SATA>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - power-domains = <&power RK3568_PD_PIPE>; - status = "disabled"; - }; - - usbdrd30: usbdrd { - compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3"; - clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, - <&cru ACLK_USB3OTG0>, <&cru PCLK_PIPE>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk", "pipe_clk"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - usbdrd_dwc3: dwc3@fcc00000 { - compatible = "snps,dwc3"; - reg = <0x0 0xfcc00000 0x0 0x400000>; - interrupts = ; - dr_mode = "otg"; - phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - power-domains = <&power RK3568_PD_PIPE>; - resets = <&cru SRST_USB3OTG0>; - reset-names = "usb3-otg"; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - snps,dis_rxdet_inp3_quirk; - snps,xhci-trb-ent-quirk; - snps,parkmode-disable-ss-quirk; - quirk-skip-phy-init; - status = "disabled"; - }; - }; - - usbhost30: usbhost { - compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3"; - clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, - <&cru ACLK_USB3OTG1>, <&cru PCLK_PIPE>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk", "pipe_clk"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - usbhost_dwc3: dwc3@fd000000 { - compatible = "snps,dwc3"; - reg = <0x0 0xfd000000 0x0 0x400000>; - interrupts = ; - dr_mode = "host"; - phys = <&u2phy0_host>, <&combphy1_usq PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - power-domains = <&power RK3568_PD_PIPE>; - resets = <&cru SRST_USB3OTG1>; - reset-names = "usb3-host"; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - snps,dis_rxdet_inp3_quirk; - snps,xhci-trb-ent-quirk; - snps,parkmode-disable-ss-quirk; - status = "disabled"; - }; - }; - - gic: interrupt-controller@fd400000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - - reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ - <0x0 0xfd460000 0 0xc0000>; /* GICR */ - interrupts = ; - its: interrupt-controller@fd440000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0xfd440000 0x0 0x20000>; - }; - }; - - usb_host0_ehci: usb@fd800000 { - compatible = "generic-ehci"; - reg = <0x0 0xfd800000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, - <&cru PCLK_USB>, <&usb2phy1>; - clock-names = "usbhost", "arbiter", "pclk", "utmi"; - phys = <&u2phy1_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host0_ohci: usb@fd840000 { - compatible = "generic-ohci"; - reg = <0x0 0xfd840000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, - <&cru PCLK_USB>, <&usb2phy1>; - clock-names = "usbhost", "arbiter", "pclk", "utmi"; - phys = <&u2phy1_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host1_ehci: usb@fd880000 { - compatible = "generic-ehci"; - reg = <0x0 0xfd880000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, - <&cru PCLK_USB>, <&usb2phy1>; - clock-names = "usbhost", "arbiter", "pclk", "utmi"; - phys = <&u2phy1_host>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host1_ohci: usb@fd8c0000 { - compatible = "generic-ohci"; - reg = <0x0 0xfd8c0000 0x0 0x40000>; - interrupts = ; - clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, - <&cru PCLK_USB>, <&usb2phy1>; - clock-names = "usbhost", "arbiter", "pclk", "utmi"; - phys = <&u2phy1_host>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - xpcs: syscon@fda00000 { - compatible = "rockchip,rk3568-xpcs", "syscon"; - reg = <0x0 0xfda00000 0x0 0x200000>; - status = "disabled"; - }; - - pmugrf: syscon@fdc20000 { - compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xfdc20000 0x0 0x10000>; - - pmu_io_domains: io-domains { - compatible = "rockchip,rk3568-pmu-io-voltage-domain"; - status = "disabled"; - }; - - reboot_mode: reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x200>; - mode-bootloader = ; - mode-charge = ; - mode-fastboot = ; - mode-loader = ; - mode-normal = ; - mode-recovery = ; - mode-ums = ; - mode-panic = ; - mode-watchdog = ; - }; - }; - - pipegrf: syscon@fdc50000 { - compatible = "rockchip,rk3568-pipegrf", "syscon"; - reg = <0x0 0xfdc50000 0x0 0x1000>; - }; - - grf: syscon@fdc60000 { - compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfdc60000 0x0 0x10000>; - - io_domains: io-domains { - compatible = "rockchip,rk3568-io-voltage-domain"; - status = "disabled"; - }; - - lvds: lvds { - compatible = "rockchip,rk3568-lvds"; - phys = <&video_phy0>; - phy-names = "phy"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - lvds_in_vp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vp1_out_lvds>; - status = "disabled"; - }; - - lvds_in_vp2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vp2_out_lvds>; - status = "disabled"; - }; - }; - }; - }; - - rgb: rgb { - compatible = "rockchip,rk3568-rgb"; - pinctrl-names = "default"; - pinctrl-0 = <&lcdc_ctl>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - rgb_in_vp2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vp2_out_rgb>; - status = "disabled"; - }; - }; - }; - }; - - }; - - pipe_phy_grf0: syscon@fdc70000 { - compatible = "rockchip,pipe-phy-grf", "syscon"; - reg = <0x0 0xfdc70000 0x0 0x1000>; - }; - - pipe_phy_grf1: syscon@fdc80000 { - compatible = "rockchip,pipe-phy-grf", "syscon"; - reg = <0x0 0xfdc80000 0x0 0x1000>; - }; - - pipe_phy_grf2: syscon@fdc90000 { - compatible = "rockchip,pipe-phy-grf", "syscon"; - reg = <0x0 0xfdc90000 0x0 0x1000>; - }; - - usb2phy0_grf: syscon@fdca0000 { - compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; - reg = <0x0 0xfdca0000 0x0 0x8000>; - }; - - usb2phy1_grf: syscon@fdca8000 { - compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; - reg = <0x0 0xfdca8000 0x0 0x8000>; - }; - - edp_phy_grf: syscon@fdcb0000 { - compatible = "rockchip,rk3568-edp-phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfdcb0000 0x0 0x100>; - clocks = <&cru PCLK_EDPPHY_GRF>; - - edp_phy: edp-phy { - compatible = "rockchip,rk3568-edp-phy"; - clocks = <&pmucru XIN_OSC0_EDPPHY_G>; - clock-names = "refclk"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - pcie30_phy_grf: syscon@fdcb8000 { - compatible = "rockchip,pcie30-phy-grf", "syscon"; - reg = <0x0 0xfdcb8000 0x0 0x10000>; - }; - - sram: sram@fdcc0000 { - compatible = "mmio-sram"; - reg = <0x0 0xfdcc0000 0x0 0xb000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0xfdcc0000 0xb000>; - - /* start address and size should be 4k algin */ - rkvdec_sram: rkvdec-sram@0 { - reg = <0x0 0xb000>; - }; - }; - - pmucru: clock-controller@fdd00000 { - compatible = "rockchip,rk3568-pmucru"; - reg = <0x0 0xfdd00000 0x0 0x1000>; - rockchip,grf = <&grf>; - rockchip,pmugrf = <&pmugrf>; - #clock-cells = <1>; - #reset-cells = <1>; - - assigned-clocks = <&pmucru SCLK_32K_IOE>; - assigned-clock-parents = <&pmucru CLK_RTC_32K>; - }; - - cru: clock-controller@fdd20000 { - compatible = "rockchip,rk3568-cru"; - reg = <0x0 0xfdd20000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - - assigned-clocks = - <&pmucru CLK_RTC_32K>, <&cru ACLK_RKVDEC_PRE>, - <&cru CLK_RKVDEC_CORE>, <&pmucru PLL_PPLL>, - <&pmucru PCLK_PMU>, <&cru PLL_CPLL>, - <&cru CPLL_500M>, <&cru CPLL_333M>, - <&cru CPLL_250M>, <&cru CPLL_125M>, - <&cru CPLL_100M>, <&cru CPLL_62P5M>, - <&cru CPLL_50M>, <&cru CPLL_25M>, - <&cru PLL_GPLL>, - <&cru ACLK_BUS>, <&cru PCLK_BUS>, - <&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>, - <&cru HCLK_TOP>, <&cru PCLK_TOP>, - <&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>, - <&cru PLL_NPLL>, <&cru ACLK_PIPE>, - <&cru PCLK_PIPE>, <&cru CLK_I2S0_8CH_TX_SRC>, - <&cru CLK_I2S0_8CH_RX_SRC>, <&cru CLK_I2S1_8CH_TX_SRC>, - <&cru CLK_I2S1_8CH_RX_SRC>, <&cru CLK_I2S2_2CH_SRC>, - <&cru CLK_I2S2_2CH_SRC>, <&cru CLK_I2S3_2CH_RX_SRC>, - <&cru CLK_I2S3_2CH_TX_SRC>, <&cru MCLK_SPDIF_8CH_SRC>, - <&cru ACLK_VOP>; - assigned-clock-rates = - <32768>, <300000000>, - <300000000>, <200000000>, - <100000000>, <1000000000>, - <500000000>, <333000000>, - <250000000>, <125000000>, - <100000000>, <62500000>, - <50000000>, <25000000>, - <1188000000>, - <150000000>, <100000000>, - <500000000>, <400000000>, - <150000000>, <100000000>, - <300000000>, <150000000>, - <1200000000>, <400000000>, - <100000000>, <1188000000>, - <1188000000>, <1188000000>, - <1188000000>, <1188000000>, - <1188000000>, <1188000000>, - <1188000000>, <1188000000>, - <500000000>; - assigned-clock-parents = - <&pmucru CLK_RTC32K_FRAC>, <&cru PLL_GPLL>, - <&cru PLL_GPLL>; - }; - - i2c0: i2c@fdd40000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xfdd40000 0x0 0x1000>; - clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart0: serial@fdd50000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfdd50000 0x0 0x100>; - interrupts = ; - clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac0 0>, <&dmac0 1>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer>; - status = "disabled"; - }; - - pwm0: pwm@fdd70000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70000 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm0m0_pins>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm1: pwm@fdd70010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70010 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm1m0_pins>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm2: pwm@fdd70020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70020 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm2m0_pins>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm3: pwm@fdd70030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfdd70030 0x0 0x10>; - interrupts = , - ; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm3_pins>; - clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pmu: power-management@fdd90000 { - compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; - reg = <0x0 0xfdd90000 0x0 0x1000>; - - power: power-controller { - compatible = "rockchip,rk3568-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - /* These power domains are grouped by VD_NPU */ - pd_npu@RK3568_PD_NPU { - reg = ; - clocks = <&cru ACLK_NPU_PRE>, - <&cru HCLK_NPU_PRE>, - <&cru PCLK_NPU_PRE>; - pm_qos = <&qos_npu>; - }; - /* These power domains are grouped by VD_GPU */ - pd_gpu@RK3568_PD_GPU { - reg = ; - clocks = <&cru ACLK_GPU_PRE>, - <&cru PCLK_GPU_PRE>; - pm_qos = <&qos_gpu>; - }; - /* These power domains are grouped by VD_LOGIC */ - pd_vi@RK3568_PD_VI { - reg = ; - clocks = <&cru HCLK_VI>, - <&cru PCLK_VI>; - pm_qos = <&qos_isp>, - <&qos_vicap0>, - <&qos_vicap1>; - }; - pd_vo@RK3568_PD_VO { - reg = ; - clocks = <&cru HCLK_VO>, - <&cru PCLK_VO>, - <&cru ACLK_VOP_PRE>; - pm_qos = <&qos_hdcp>, - <&qos_vop_m0>, - <&qos_vop_m1>; - }; - pd_rga@RK3568_PD_RGA { - reg = ; - clocks = <&cru HCLK_RGA_PRE>, - <&cru PCLK_RGA_PRE>; - pm_qos = <&qos_ebc>, - <&qos_iep>, - <&qos_jpeg_dec>, - <&qos_jpeg_enc>, - <&qos_rga_rd>, - <&qos_rga_wr>; - }; - pd_vpu@RK3568_PD_VPU { - reg = ; - clocks = <&cru HCLK_VPU_PRE>; - pm_qos = <&qos_vpu>; - }; - pd_rkvdec@RK3568_PD_RKVDEC { - clocks = <&cru HCLK_RKVDEC_PRE>; - reg = ; - pm_qos = <&qos_rkvdec>; - }; - pd_rkvenc@RK3568_PD_RKVENC { - reg = ; - clocks = <&cru HCLK_RKVENC_PRE>; - pm_qos = <&qos_rkvenc_rd_m0>, - <&qos_rkvenc_rd_m1>, - <&qos_rkvenc_wr_m0>; - }; - pd_pipe@RK3568_PD_PIPE { - reg = ; - clocks = <&cru PCLK_PIPE>; - pm_qos = <&qos_pcie2x1>, - <&qos_pcie3x1>, - <&qos_pcie3x2>, - <&qos_sata0>, - <&qos_sata1>, - <&qos_sata2>, - <&qos_usb3_0>, - <&qos_usb3_1>; - }; - }; - }; - - pvtm@fde00000 { - compatible = "rockchip,rk3568-core-pvtm"; - reg = <0x0 0xfde00000 0x0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - pvtm@0 { - reg = <0>; - clocks = <&cru CLK_CORE_PVTM>, <&cru PCLK_CORE_PVTM>; - clock-names = "clk", "pclk"; - resets = <&cru SRST_CORE_PVTM>, <&cru SRST_P_CORE_PVTM>; - reset-names = "rts", "rst-p"; - thermal-zone = "soc-thermal"; - }; - }; - - rknpu: npu@fde40000 { - compatible = "rockchip,rk3568-rknpu", "rockchip,rknpu"; - reg = <0x0 0xfde40000 0x0 0x10000>; - interrupts = ; - clocks = <&scmi_clk 2>, <&cru CLK_NPU>, <&cru ACLK_NPU>, <&cru HCLK_NPU>; - clock-names = "scmi_clk", "clk", "aclk", "hclk"; - assigned-clocks = <&cru CLK_NPU>; - assigned-clock-rates = <600000000>; - resets = <&cru SRST_A_NPU>, <&cru SRST_H_NPU>; - reset-names = "srst_a", "srst_h"; - power-domains = <&power RK3568_PD_NPU>; - operating-points-v2 = <&npu_opp_table>; - iommus = <&rknpu_mmu>; - status = "disabled"; - }; - - npu_opp_table: npu-opp-table { - compatible = "operating-points-v2"; - - mbist-vmin = <825000 900000 950000>; - nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&npu_opp_info>; - nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info"; - rockchip,max-volt = <1000000>; - rockchip,temp-hysteresis = <5000>; - rockchip,low-temp = <0>; - rockchip,low-temp-adjust-volt = < - /* MHz MHz uV */ - 0 1000 50000 - >; - rockchip,pvtm-voltage-sel = < - 0 84000 0 - 84001 87000 1 - 87001 91000 2 - 91001 100000 3 - >; - rockchip,pvtm-ch = <0 5>; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <850000 850000 1000000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <297000000>; - opp-microvolt = <850000 850000 1000000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <850000 850000 1000000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <850000 850000 1000000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <875000 875000 1000000>; - opp-microvolt-L0 = <875000 875000 1000000>; - opp-microvolt-L1 = <850000 850000 1000000>; - opp-microvolt-L2 = <850000 850000 1000000>; - opp-microvolt-L3 = <850000 850000 1000000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <925000 925000 1000000>; - opp-microvolt-L0 = <925000 925000 1000000>; - opp-microvolt-L1 = <900000 900000 1000000>; - opp-microvolt-L2 = <875000 875000 1000000>; - opp-microvolt-L3 = <875000 875000 1000000>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <975000 975000 1000000>; - opp-microvolt-L0 = <975000 975000 1000000>; - opp-microvolt-L1 = <950000 950000 1000000>; - opp-microvolt-L2 = <925000 925000 1000000>; - opp-microvolt-L3 = <900000 900000 1000000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1000000 1000000 1000000>; - opp-microvolt-L0 = <1000000 1000000 1000000>; - opp-microvolt-L1 = <975000 975000 1000000>; - opp-microvolt-L2 = <950000 950000 1000000>; - opp-microvolt-L3 = <925000 925000 1000000>; - status = "disabled"; - }; - }; - - bus_npu: bus-npu { - compatible = "rockchip,rk3568-bus"; - rockchip,busfreq-policy = "clkfreq"; - clocks = <&scmi_clk 2>; - clock-names = "bus"; - operating-points-v2 = <&bus_npu_opp_table>; - status = "disabled"; - }; - - bus_npu_opp_table: bus-npu-opp-table { - compatible = "operating-points-v2"; - opp-shared; - - nvmem-cells = <&core_pvtm>; - nvmem-cell-names = "pvtm"; - rockchip,pvtm-voltage-sel = < - 0 84000 0 - 84001 91000 1 - 91001 100000 2 - >; - rockchip,pvtm-ch = <0 5>; - - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <900000>; - opp-microvolt-L0 = <900000>; - opp-microvolt-L1 = <875000>; - opp-microvolt-L2 = <875000>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <900000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <950000>; - opp-microvolt-L0 = <950000>; - opp-microvolt-L1 = <925000>; - opp-microvolt-L2 = <900000>; - }; - }; - - rknpu_mmu: iommu@fde4b000 { - compatible = "rockchip,iommu-v2"; - reg = <0x0 0xfde4b000 0x0 0x40>; - interrupts = ; - interrupt-names = "rknpu_mmu"; - clocks = <&cru ACLK_NPU>, <&cru HCLK_NPU>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3568_PD_NPU>; - #iommu-cells = <0>; - status = "disabled"; - }; - - gpu: gpu@fde60000 { - compatible = "arm,mali-bifrost"; - reg = <0x0 0xfde60000 0x0 0x4000>; - - interrupts = , - , - ; - interrupt-names = "GPU", "MMU", "JOB"; - - upthreshold = <40>; - downdifferential = <10>; - - clocks = <&scmi_clk 1>, <&cru CLK_GPU>; - clock-names = "clk_mali", "clk_gpu"; - power-domains = <&power RK3568_PD_GPU>; - #cooling-cells = <2>; - operating-points-v2 = <&gpu_opp_table>; - - status = "disabled"; - gpu_power_model: power-model { - compatible = "simple-power-model"; - leakage-range= <5 15>; - ls = <(-24002) 22823 0>; - static-coefficient = <100000>; - dynamic-coefficient = <953>; - ts = <(-108890) 63610 (-1355) 20>; - thermal-zone = "gpu-thermal"; - }; - }; - - gpu_opp_table: opp-table2 { - compatible = "operating-points-v2"; - - mbist-vmin = <825000 900000 950000>; - nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&gpu_opp_info>; - nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info"; - rockchip,max-volt = <1000000>; - rockchip,temp-hysteresis = <5000>; - rockchip,low-temp = <0>; - rockchip,low-temp-adjust-volt = < - /* MHz MHz uV */ - 0 800 50000 - >; - rockchip,pvtm-voltage-sel = < - 0 84000 0 - 84001 87000 1 - 87001 91000 2 - 91001 100000 3 - >; - rockchip,pvtm-ch = <0 5>; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <850000 850000 1000000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <850000 850000 1000000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <850000 850000 1000000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <900000 900000 1000000>; - opp-microvolt-L0 = <900000 900000 1000000>; - opp-microvolt-L1 = <875000 875000 1000000>; - opp-microvolt-L2 = <850000 850000 1000000>; - opp-microvolt-L3 = <850000 850000 1000000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <950000 950000 1000000>; - opp-microvolt-L0 = <950000 950000 1000000>; - opp-microvolt-L1 = <925000 925000 1000000>; - opp-microvolt-L2 = <900000 900000 1000000>; - opp-microvolt-L3 = <875000 875000 1000000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1000000 1000000 1000000>; - opp-microvolt-L0 = <1000000 1000000 1000000>; - opp-microvolt-L1 = <975000 975000 1000000>; - opp-microvolt-L2 = <950000 950000 1000000>; - opp-microvolt-L3 = <925000 925000 1000000>; - }; - }; - - pvtm@fde80000 { - compatible = "rockchip,rk3568-gpu-pvtm"; - reg = <0x0 0xfde80000 0x0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - pvtm@1 { - reg = <1>; - clocks = <&cru CLK_GPU_PVTM>, <&cru PCLK_GPU_PVTM>; - clock-names = "clk", "pclk"; - resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>; - reset-names = "rts", "rst-p"; - thermal-zone = "gpu-thermal"; - }; - }; - - pvtm@fde90000 { - compatible = "rockchip,rk3568-npu-pvtm"; - reg = <0x0 0xfde90000 0x0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - pvtm@2 { - reg = <2>; - clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>, - <&cru HCLK_NPU_PRE>; - clock-names = "clk", "pclk", "hclk"; - resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>; - reset-names = "rts", "rst-p"; - thermal-zone = "soc-thermal"; - }; - }; - - vdpu: vdpu@fdea0400 { - compatible = "rockchip,vpu-decoder-v2"; - reg = <0x0 0xfdea0400 0x0 0x400>; - interrupts = ; - interrupt-names = "irq_dec"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk_vcodec", "hclk_vcodec"; - resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>; - reset-names = "video_a", "video_h"; - iommus = <&vdpu_mmu>; - power-domains = <&power RK3568_PD_VPU>; - rockchip,srv = <&mpp_srv>; - rockchip,taskqueue-node = <0>; - rockchip,resetgroup-node = <0>; - status = "disabled"; - }; - - vdpu_mmu: iommu@fdea0800 { - compatible = "rockchip,iommu-v2"; - reg = <0x0 0xfdea0800 0x0 0x40>; - interrupts = ; - interrupt-names = "vdpu_mmu"; - clock-names = "aclk", "iface"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - power-domains = <&power RK3568_PD_VPU>; - #iommu-cells = <0>; - status = "disabled"; - }; - - rk_rga: rk_rga@fdeb0000 { - compatible = "rockchip,rga2"; - reg = <0x0 0xfdeb0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; - clock-names = "aclk_rga", "hclk_rga", "clk_rga"; - power-domains = <&power RK3568_PD_RGA>; - status = "disabled"; - }; - - ebc: ebc@fdec0000 { - compatible = "rockchip,rk3568-ebc-tcon"; - reg = <0x0 0xfdec0000 0x0 0x5000>; - interrupts = ; - clocks = <&cru HCLK_EBC>, <&cru DCLK_EBC>; - clock-names = "hclk", "dclk"; - power-domains = <&power RK3568_PD_RGA>; - rockchip,grf = <&grf>; - pinctrl-names = "default"; - pinctrl-0 = <&ebc_pins>; - status = "disabled"; - }; - - jpegd: jpegd@fded0000 { - compatible = "rockchip,rkv-jpeg-decoder-v1"; - reg = <0x0 0xfded0000 0x0 0x400>; - interrupts = ; - clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>; - clock-names = "aclk_vcodec", "hclk_vcodec"; - rockchip,disable-auto-freq; - resets = <&cru SRST_A_JDEC>, <&cru SRST_H_JDEC>; - reset-names = "video_a", "video_h"; - iommus = <&jpegd_mmu>; - rockchip,srv = <&mpp_srv>; - rockchip,taskqueue-node = <1>; - rockchip,resetgroup-node = <1>; - power-domains = <&power RK3568_PD_RGA>; - status = "disabled"; - }; - - jpegd_mmu: iommu@fded0480 { - compatible = "rockchip,iommu-v2"; - reg = <0x0 0xfded0480 0x0 0x40>; - interrupts = ; - interrupt-names = "jpegd_mmu"; - clock-names = "aclk", "iface"; - clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>; - power-domains = <&power RK3568_PD_RGA>; - #iommu-cells = <0>; - status = "disabled"; - }; - - vepu: vepu@fdee0000 { - compatible = "rockchip,vpu-encoder-v2"; - reg = <0x0 0xfdee0000 0x0 0x400>; - interrupts = ; - clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; - clock-names = "aclk_vcodec", "hclk_vcodec"; - rockchip,disable-auto-freq; - resets = <&cru SRST_A_JENC>, <&cru SRST_H_JENC>; - reset-names = "video_a", "video_h"; - iommus = <&vepu_mmu>; - rockchip,srv = <&mpp_srv>; - rockchip,taskqueue-node = <2>; - rockchip,resetgroup-node = <2>; - power-domains = <&power RK3568_PD_RGA>; - status = "disabled"; - }; - - vepu_mmu: iommu@fdee0800 { - compatible = "rockchip,iommu-v2"; - reg = <0x0 0xfdee0800 0x0 0x40>; - interrupts = ; - interrupt-names = "vepu_mmu"; - clock-names = "aclk", "iface"; - clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; - power-domains = <&power RK3568_PD_RGA>; - #iommu-cells = <0>; - status = "disabled"; - }; - - iep: iep@fdef0000 { - compatible = "rockchip,iep-v2"; - reg = <0x0 0xfdef0000 0x0 0x500>; - interrupts = ; - clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>, <&cru CLK_IEP_CORE>; - clock-names = "aclk", "hclk", "sclk"; - resets = <&cru SRST_A_IEP>, <&cru SRST_H_IEP>, - <&cru SRST_IEP_CORE>; - reset-names = "rst_a", "rst_h", "rst_s"; - power-domains = <&power RK3568_PD_RGA>; - rockchip,srv = <&mpp_srv>; - rockchip,taskqueue-node = <5>; - rockchip,resetgroup-node = <5>; - iommus = <&iep_mmu>; - status = "disabled"; - }; - - iep_mmu: iommu@fdef0800 { - compatible = "rockchip,iommu-v2"; - reg = <0x0 0xfdef0800 0x0 0x100>; - interrupts = ; - interrupt-names = "iep_mmu"; - clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3568_PD_RGA>; - //rockchip,disable-device-link-resume; - status = "disabled"; - }; - - eink: eink@fdf00000 { - compatible = "rockchip,rk3568-eink-tcon"; - reg = <0x0 0xfdf00000 0x0 0x74>; - interrupts = ; - clocks = <&cru PCLK_EINK>, <&cru HCLK_EINK>; - clock-names = "pclk", "hclk"; - status = "disabled"; - }; - - rkvenc: rkvenc@fdf40000 { - compatible = "rockchip,rkv-encoder-v1"; - reg = <0x0 0xfdf40000 0x0 0x400>; - interrupts = ; - interrupt-names = "irq_enc"; - clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, - <&cru CLK_RKVENC_CORE>; - clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; - rockchip,normal-rates = <297000000>, <0>, <297000000>; - resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>, - <&cru SRST_RKVENC_CORE>; - reset-names = "video_a", "video_h", "video_core"; - assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>; - assigned-clock-rates = <297000000>, <297000000>; - iommus = <&rkvenc_mmu>; - node-name = "rkvenc"; - rockchip,srv = <&mpp_srv>; - rockchip,taskqueue-node = <3>; - rockchip,resetgroup-node = <3>; - power-domains = <&power RK3568_PD_RKVENC>; - operating-points-v2 = <&rkvenc_opp_table>; - status = "disabled"; - }; - - rkvenc_opp_table: rkvenc-opp-table { - compatible = "operating-points-v2"; - - nvmem-cells = <&core_pvtm>; - nvmem-cell-names = "pvtm"; - rockchip,pvtm-voltage-sel = < - 0 84000 0 - 84001 91000 1 - 91001 100000 2 - >; - rockchip,pvtm-ch = <0 5>; - - opp-297000000 { - opp-hz = /bits/ 64 <297000000>; - opp-microvolt = <900000>; - opp-microvolt-L0 = <900000>; - opp-microvolt-L1 = <875000>; - opp-microvolt-L2 = <875000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <950000>; - opp-microvolt-L0 = <950000>; - opp-microvolt-L1 = <925000>; - opp-microvolt-L2 = <900000>; - }; - }; - - rkvenc_mmu: iommu@fdf40f00 { - compatible = "rockchip,iommu-v2"; - reg = <0x0 0xfdf40f00 0x0 0x40>, <0x0 0xfdf40f40 0x0 0x40>; - interrupts = , - ; - interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1"; - clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>; - clock-names = "aclk", "iface"; - rockchip,disable-mmu-reset; - rockchip,enable-cmd-retry; - #iommu-cells = <0>; - power-domains = <&power RK3568_PD_RKVENC>; - status = "disabled"; - }; - - rkvdec: rkvdec@fdf80200 { - compatible = "rockchip,rkv-decoder-rk3568", "rockchip,rkv-decoder-v2"; - reg = <0x0 0xfdf80200 0x0 0x400>, <0x0 0xfdf80100 0x0 0x100>; - reg-names = "regs", "link"; - interrupts = ; - interrupt-names = "irq_dec"; - clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, - <&cru CLK_RKVDEC_CA>, <&cru CLK_RKVDEC_CORE>, - <&cru CLK_RKVDEC_HEVC_CA>; - clock-names = "aclk_vcodec", "hclk_vcodec","clk_cabac", - "clk_core", "clk_hevc_cabac"; - rockchip,normal-rates = <297000000>, <0>, <297000000>, - <297000000>, <600000000>; - rockchip,advanced-rates = <396000000>, <0>, <396000000>, - <396000000>, <600000000>; - rockchip,default-max-load = <2088960>; - resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>, - <&cru SRST_RKVDEC_CA>, <&cru SRST_RKVDEC_CORE>, - <&cru SRST_RKVDEC_HEVC_CA>; - assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_CA>, - <&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>; - assigned-clock-rates = <297000000>, <297000000>, <297000000>, <297000000>; - reset-names = "video_a", "video_h", "video_cabac", - "video_core", "video_hevc_cabac"; - power-domains = <&power RK3568_PD_RKVDEC>; - operating-points-v2 = <&rkvdec_opp_table>; - vdec-supply = <&vdd_logic>; - iommus = <&rkvdec_mmu>; - rockchip,srv = <&mpp_srv>; - rockchip,taskqueue-node = <4>; - rockchip,resetgroup-node = <4>; - rockchip,sram = <&rkvdec_sram>; - /* rcb_iova: start and size */ - rockchip,rcb-iova = <0x10000000 65536>; - rockchip,rcb-min-width = <512>; - rockchip,task-capacity = <16>; - status = "disabled"; - }; - - rkvdec_opp_table: rkvdec-opp-table { - compatible = "operating-points-v2"; - - nvmem-cells = <&log_leakage>, <&core_pvtm>; - nvmem-cell-names = "leakage", "pvtm"; - rockchip,leakage-voltage-sel = < - 1 80 0 - 81 254 1 - >; - rockchip,pvtm-voltage-sel = < - 0 84000 0 - 84001 100000 1 - >; - rockchip,pvtm-ch = <0 5>; - - opp-297000000 { - opp-hz = /bits/ 64 <297000000>; - opp-microvolt = <900000>; - opp-microvolt-L0 = <900000>; - opp-microvolt-L1 = <875000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <900000>; - }; - }; - - rkvdec_mmu: iommu@fdf80800 { - compatible = "rockchip,iommu-v2"; - reg = <0x0 0xfdf80800 0x0 0x40>, <0x0 0xfdf80840 0x0 0x40>; - interrupts = ; - interrupt-names = "rkvdec_mmu"; - clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3568_PD_RKVDEC>; - #iommu-cells = <0>; - status = "disabled"; - }; - - mipi_csi2_hw: mipi-csi2-hw@fdfb0000 { - compatible = "rockchip,rk3568-mipi-csi2-hw"; - reg = <0x0 0xfdfb0000 0x0 0x10000>; - reg-names = "csihost_regs"; - interrupts = , - ; - interrupt-names = "csi-intr1", "csi-intr2"; - clocks = <&cru PCLK_CSI2HOST1>; - clock-names = "pclk_csi2host"; - resets = <&cru SRST_P_CSI2HOST1>; - reset-names = "srst_csihost_p"; - status = "disabled"; - }; - - rkcif: rkcif@fdfe0000 { - compatible = "rockchip,rk3568-cif"; - reg = <0x0 0xfdfe0000 0x0 0x8000>; - reg-names = "cif_regs"; - interrupts = ; - interrupt-names = "cif-intr"; - - clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, - <&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>; - clock-names = "aclk_cif", "hclk_cif", - "dclk_cif", "iclk_cif_g"; - resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, - <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>, - <&cru SRST_I_VICAP>; - reset-names = "rst_cif_a", "rst_cif_h", - "rst_cif_d", "rst_cif_p", - "rst_cif_i"; - assigned-clocks = <&cru DCLK_VICAP>; - assigned-clock-rates = <300000000>; - power-domains = <&power RK3568_PD_VI>; - rockchip,grf = <&grf>; - iommus = <&rkcif_mmu>; - status = "disabled"; - }; - - rkcif_mmu: iommu@fdfe0800 { - compatible = "rockchip,iommu-v2"; - reg = <0x0 0xfdfe0800 0x0 0x100>; - interrupts = ; - interrupt-names = "cif_mmu"; - clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3568_PD_VI>; - rockchip,disable-mmu-reset; - #iommu-cells = <0>; - status = "disabled"; - }; - - rkcif_dvp: rkcif_dvp { - compatible = "rockchip,rkcif-dvp"; - rockchip,hw = <&rkcif>; - status = "disabled"; - }; - - rkcif_dvp_sditf: rkcif_dvp_sditf { - compatible = "rockchip,rkcif-sditf"; - rockchip,cif = <&rkcif_dvp>; - status = "disabled"; - }; - - rkcif_mipi_lvds: rkcif_mipi_lvds { - compatible = "rockchip,rkcif-mipi-lvds"; - rockchip,hw = <&rkcif>; - status = "disabled"; - }; - - rkcif_mipi_lvds_sditf: rkcif_mipi_lvds_sditf { - compatible = "rockchip,rkcif-sditf"; - rockchip,cif = <&rkcif_mipi_lvds>; - status = "disabled"; - }; - - rkisp: rkisp@fdff0000 { - compatible = "rockchip,rk3568-rkisp"; - reg = <0x0 0xfdff0000 0x0 0x10000>; - interrupts = , - , - ; - interrupt-names = "mipi_irq", "mi_irq", "isp_irq"; - clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru CLK_ISP>; - clock-names = "aclk_isp", "hclk_isp", "clk_isp"; - resets = <&cru SRST_ISP>, <&cru SRST_H_ISP>; - reset-names = "isp", "isp-h"; - rockchip,grf = <&grf>; - power-domains = <&power RK3568_PD_VI>; - iommus = <&rkisp_mmu>; - rockchip,iq-feature = /bits/ 64 <0x1BFBFFFE67FF>; - status = "disabled"; - }; - - rkisp_mmu: iommu@fdff1a00 { - compatible = "rockchip,iommu-v2"; - reg = <0x0 0xfdff1a00 0x0 0x100>; - interrupts = ; - interrupt-names = "isp_mmu"; - clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3568_PD_VI>; - #iommu-cells = <0>; - rockchip,disable-mmu-reset; - status = "disabled"; - }; - - rkisp_vir0: rkisp-vir0 { - compatible = "rockchip,rkisp-vir"; - rockchip,hw = <&rkisp>; - status = "disabled"; - }; - - rkisp_vir1: rkisp-vir1 { - compatible = "rockchip,rkisp-vir"; - rockchip,hw = <&rkisp>; - status = "disabled"; - }; - - gmac_uio1: uio@fe010000 { - compatible = "rockchip,uio-gmac"; - reg = <0x0 0xfe010000 0x0 0x10000>; - rockchip,ethernet = <&gmac1>; - status = "disabled"; - }; - - gmac1: ethernet@fe010000 { - compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe010000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - rockchip,grf = <&grf>; - clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, - <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, - <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, - <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>, - <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_refout", - "aclk_mac", "pclk_mac", - "clk_mac_speed", "ptp_ref", - "pclk_xpcs", "clk_xpcs_eee"; - resets = <&cru SRST_A_GMAC1>; - reset-names = "stmmaceth"; - - snps,mixed-burst; - snps,tso; - - snps,axi-config = <&gmac1_stmmac_axi_setup>; - snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; - status = "disabled"; - - mdio1: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - gmac1_stmmac_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <4>; - snps,rd_osr_lmt = <8>; - snps,blen = <0 0 0 0 16 8 4>; - }; - - gmac1_mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <1>; - queue0 {}; - }; - - gmac1_mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <1>; - queue0 {}; - }; - }; - - vop: vop@fe040000 { - compatible = "rockchip,rk3568-vop"; - reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; - reg-names = "regs", "gamma_lut"; - rockchip,grf = <&grf>; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; - clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2"; - iommus = <&vop_mmu>; - power-domains = <&power RK3568_PD_VO>; - status = "disabled"; - - vop_out: ports { - #address-cells = <1>; - #size-cells = <0>; - - vp0: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - vp0_out_dsi0: endpoint@0 { - reg = <0>; - remote-endpoint = <&dsi0_in_vp0>; - }; - - vp0_out_dsi1: endpoint@1 { - reg = <1>; - remote-endpoint = <&dsi1_in_vp0>; - }; - - vp0_out_edp: endpoint@2 { - reg = <2>; - remote-endpoint = <&edp_in_vp0>; - }; - - vp0_out_hdmi: endpoint@3 { - reg = <3>; - remote-endpoint = <&hdmi_in_vp0>; - }; - }; - - vp1: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - vp1_out_dsi0: endpoint@0 { - reg = <0>; - remote-endpoint = <&dsi0_in_vp1>; - }; - - vp1_out_dsi1: endpoint@1 { - reg = <1>; - remote-endpoint = <&dsi1_in_vp1>; - }; - - vp1_out_edp: endpoint@2 { - reg = <2>; - remote-endpoint = <&edp_in_vp1>; - }; - - vp1_out_hdmi: endpoint@3 { - reg = <3>; - remote-endpoint = <&hdmi_in_vp1>; - }; - - vp1_out_lvds: endpoint@4 { - reg = <4>; - remote-endpoint = <&lvds_in_vp1>; - }; - }; - - vp2: port@2 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <2>; - - vp2_out_lvds: endpoint@0 { - reg = <0>; - remote-endpoint = <&lvds_in_vp2>; - }; - - vp2_out_rgb: endpoint@1 { - reg = <1>; - remote-endpoint = <&rgb_in_vp2>; - }; - }; - }; - }; - - vop_mmu: iommu@fe043e00 { - compatible = "rockchip,iommu-v2"; - reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; - interrupts = ; - interrupt-names = "vop_mmu"; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - rockchip,disable-device-link-resume; - status = "disabled"; - }; - - dsi0: dsi@fe060000 { - compatible = "rockchip,rk3568-mipi-dsi"; - reg = <0x0 0xfe060000 0x0 0x10000>; - interrupts = ; - clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>; - clock-names = "pclk", "hclk"; - resets = <&cru SRST_P_DSITX_0>; - reset-names = "apb"; - phys = <&video_phy0>; - phy-names = "dphy"; - power-domains = <&power RK3568_PD_VO>; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - dsi0_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dsi0_in_vp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vp0_out_dsi0>; - status = "disabled"; - }; - - dsi0_in_vp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vp1_out_dsi0>; - status = "disabled"; - }; - }; - }; - }; - - dsi1: dsi@fe070000 { - compatible = "rockchip,rk3568-mipi-dsi"; - reg = <0x0 0xfe070000 0x0 0x10000>; - interrupts = ; - clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>; - clock-names = "pclk", "hclk"; - resets = <&cru SRST_P_DSITX_1>; - reset-names = "apb"; - phys = <&video_phy1>; - phy-names = "dphy"; - power-domains = <&power RK3568_PD_VO>; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - dsi1_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dsi1_in_vp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vp0_out_dsi1>; - status = "disabled"; - }; - - dsi1_in_vp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vp1_out_dsi1>; - status = "disabled"; - }; - }; - }; - }; - - hdmi: hdmi@fe0a0000 { - compatible = "rockchip,rk3568-dw-hdmi"; - reg = <0x0 0xfe0a0000 0x0 0x20000>; - interrupts = ; - clocks = <&cru PCLK_HDMI_HOST>, - <&cru CLK_HDMI_SFR>, - <&cru CLK_HDMI_CEC>, - <&pmucru PLL_HPLL>, - <&cru HCLK_VOP>; - clock-names = "iahb", "isfr", "cec", "ref", "hclk"; - power-domains = <&power RK3568_PD_VO>; - reg-io-width = <4>; - rockchip,grf = <&grf>; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - hdmi_in_vp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vp0_out_hdmi>; - status = "disabled"; - }; - - hdmi_in_vp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vp1_out_hdmi>; - status = "disabled"; - }; - }; - }; - }; - - edp: edp@fe0c0000 { - compatible = "rockchip,rk3568-edp"; - reg = <0x0 0xfe0c0000 0x0 0x10000>; - interrupts = ; - clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDP_CTRL>, - <&cru CLK_EDP_200M>, <&cru HCLK_VO>; - clock-names = "dp", "pclk", "spdif", "hclk"; - resets = <&cru SRST_EDP_24M>, <&cru SRST_P_EDP_CTRL>; - reset-names = "dp", "apb"; - phys = <&edp_phy>; - phy-names = "dp"; - power-domains = <&power RK3568_PD_VO>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - edp_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - edp_in_vp0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vp0_out_edp>; - status = "disabled"; - }; - - edp_in_vp1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vp1_out_edp>; - status = "disabled"; - }; - }; - }; - }; - - nocp_cpu: nocp-cpu@fe102000 { - compatible = "rockchip,rk3568-nocp"; - reg = <0x0 0xfe102000 0x0 0x400>; - }; - - nocp_gpu_vpu_rga_venc: nocp-gpu-vpu-rga-venc@fe102400 { - compatible = "rockchip,rk3568-nocp"; - reg = <0x0 0xfe102400 0x0 0x400>; - }; - - nocp_npu_vdec: nocp-vdec@fe102800 { - compatible = "rockchip,rk3568-nocp"; - reg = <0x0 0xfe102800 0x0 0x400>; - }; - - nocp_vi_usb_peri_pipe: nocp-vi-usb-peri-pipe@fe102c00 { - compatible = "rockchip,rk3568-nocp"; - reg = <0x0 0xfe102c00 0x0 0x400>; - }; - - nocp_vo: nocp-vo@fe103000 { - compatible = "rockchip,rk3568-nocp"; - reg = <0x0 0xfe103000 0x0 0x400>; - }; - - qos_gpu: qos@fe128000 { - compatible = "syscon"; - reg = <0x0 0xfe128000 0x0 0x20>; - }; - - qos_rkvenc_rd_m0: qos@fe138080 { - compatible = "syscon"; - reg = <0x0 0xfe138080 0x0 0x20>; - }; - - qos_rkvenc_rd_m1: qos@fe138100 { - compatible = "syscon"; - reg = <0x0 0xfe138100 0x0 0x20>; - }; - - qos_rkvenc_wr_m0: qos@fe138180 { - compatible = "syscon"; - reg = <0x0 0xfe138180 0x0 0x20>; - }; - - qos_isp: qos@fe148000 { - compatible = "syscon"; - reg = <0x0 0xfe148000 0x0 0x20>; - }; - - qos_vicap0: qos@fe148080 { - compatible = "syscon"; - reg = <0x0 0xfe148080 0x0 0x20>; - }; - - qos_vicap1: qos@fe148100 { - compatible = "syscon"; - reg = <0x0 0xfe148100 0x0 0x20>; - }; - - qos_vpu: qos@fe150000 { - compatible = "syscon"; - reg = <0x0 0xfe150000 0x0 0x20>; - }; - - qos_ebc: qos@fe158000 { - compatible = "syscon"; - reg = <0x0 0xfe158000 0x0 0x20>; - }; - - qos_iep: qos@fe158100 { - compatible = "syscon"; - reg = <0x0 0xfe158100 0x0 0x20>; - }; - - qos_jpeg_dec: qos@fe158180 { - compatible = "syscon"; - reg = <0x0 0xfe158180 0x0 0x20>; - }; - - qos_jpeg_enc: qos@fe158200 { - compatible = "syscon"; - reg = <0x0 0xfe158200 0x0 0x20>; - }; - - qos_rga_rd: qos@fe158280 { - compatible = "syscon"; - reg = <0x0 0xfe158280 0x0 0x20>; - }; - - qos_rga_wr: qos@fe158300 { - compatible = "syscon"; - reg = <0x0 0xfe158300 0x0 0x20>; - }; - - qos_npu: qos@fe180000 { - compatible = "syscon"; - reg = <0x0 0xfe180000 0x0 0x20>; - }; - - qos_pcie2x1: qos@fe190000 { - compatible = "syscon"; - reg = <0x0 0xfe190000 0x0 0x20>; - }; - - qos_pcie3x1: qos@fe190080 { - compatible = "syscon"; - reg = <0x0 0xfe190080 0x0 0x20>; - }; - - qos_pcie3x2: qos@fe190100 { - compatible = "syscon"; - reg = <0x0 0xfe190100 0x0 0x20>; - }; - - qos_sata0: qos@fe190200 { - compatible = "syscon"; - reg = <0x0 0xfe190200 0x0 0x20>; - }; - - qos_sata1: qos@fe190280 { - compatible = "syscon"; - reg = <0x0 0xfe190280 0x0 0x20>; - }; - - qos_sata2: qos@fe190300 { - compatible = "syscon"; - reg = <0x0 0xfe190300 0x0 0x20>; - }; - - qos_usb3_0: qos@fe190380 { - compatible = "syscon"; - reg = <0x0 0xfe190380 0x0 0x20>; - }; - - qos_usb3_1: qos@fe190400 { - compatible = "syscon"; - reg = <0x0 0xfe190400 0x0 0x20>; - }; - - qos_rkvdec: qos@fe198000 { - compatible = "syscon"; - reg = <0x0 0xfe198000 0x0 0x20>; - }; - - qos_hdcp: qos@fe1a8000 { - compatible = "syscon"; - reg = <0x0 0xfe1a8000 0x0 0x20>; - }; - - qos_vop_m0: qos@fe1a8080 { - compatible = "syscon"; - reg = <0x0 0xfe1a8080 0x0 0x20>; - }; - - qos_vop_m1: qos@fe1a8100 { - compatible = "syscon"; - reg = <0x0 0xfe1a8100 0x0 0x20>; - }; - - sdmmc2: dwmmc@fe000000 { - compatible = "rockchip,rk3568-dw-mshc", - "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe000000 0x0 0x4000>; - interrupts = ; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, - <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - resets = <&cru SRST_SDMMC2>; - reset-names = "reset"; - status = "disabled"; - }; - - dfi: dfi@fe230000 { - reg = <0x00 0xfe230000 0x00 0x400>; - compatible = "rockchip,rk3568-dfi"; - rockchip,pmugrf = <&pmugrf>; - status = "disabled"; - }; - - dmc: dmc { - compatible = "rockchip,rk3568-dmc"; - interrupts = ; - interrupt-names = "complete"; - devfreq-events = <&dfi>, <&nocp_cpu>; - clocks = <&scmi_clk 3>; - clock-names = "dmc_clk"; - operating-points-v2 = <&dmc_opp_table>; - vop-bw-dmc-freq = < - /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ - 0 286 324000 - 287 99999 528000 - >; - vop-frame-bw-dmc-freq = < - /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ - 0 620 324000 - 621 99999 780000 - >; - cpu-bw-dmc-freq = < - /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ - 0 350 324000 - 351 400 528000 - 401 99999 780000 - >; - upthreshold = <40>; - downdifferential = <20>; - system-status-level = < - /*system status freq level*/ - SYS_STATUS_NORMAL DMC_FREQ_LEVEL_MID_HIGH - SYS_STATUS_REBOOT DMC_FREQ_LEVEL_HIGH - SYS_STATUS_SUSPEND DMC_FREQ_LEVEL_LOW - SYS_STATUS_VIDEO_4K DMC_FREQ_LEVEL_MID_HIGH - SYS_STATUS_VIDEO_4K_10B DMC_FREQ_LEVEL_MID_HIGH - SYS_STATUS_BOOST DMC_FREQ_LEVEL_HIGH - SYS_STATUS_ISP DMC_FREQ_LEVEL_HIGH - SYS_STATUS_PERFORMANCE DMC_FREQ_LEVEL_HIGH - SYS_STATUS_DUALVIEW DMC_FREQ_LEVEL_HIGH - >; - auto-min-freq = <324000>; - auto-freq-en = <1>; - #cooling-cells = <2>; - status = "disabled"; - }; - - dmc_fsp: dmc-fsp { - compatible = "rockchip,rk3568-dmc-fsp"; - - debug_print_level = <0>; - ddr3_params = <&ddr3_params>; - ddr4_params = <&ddr4_params>; - lpddr3_params = <&lpddr3_params>; - lpddr4_params = <&lpddr4_params>; - lpddr4x_params = <&lpddr4x_params>; - - status = "okay"; - }; - - dmc_opp_table: dmc-opp-table { - compatible = "operating-points-v2"; - - mbist-vmin = <825000 900000 950000>; - nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>, <&dmc_opp_info>; - nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info"; - rockchip,max-volt = <1000000>; - rockchip,temp-hysteresis = <5000>; - rockchip,low-temp = <0>; - rockchip,low-temp-adjust-volt = < - /* MHz MHz uV */ - 0 1560 75000 - >; - rockchip,leakage-voltage-sel = < - 1 80 0 - 81 254 1 - >; - rockchip,pvtm-voltage-sel = < - 0 84000 0 - 84001 100000 1 - >; - rockchip,pvtm-ch = <0 5>; - - opp-1560000000 { - opp-hz = /bits/ 64 <1560000000>; - opp-microvolt = <900000 900000 1000000>; - opp-microvolt-L0 = <900000 900000 1000000>; - opp-microvolt-L1 = <875000 875000 1000000>; - }; - }; - - pcie2x1: pcie@fe260000 { - compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x0 0xf>; - clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, - <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, - <&cru CLK_PCIE20_AUX_NDFT>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; - device_type = "pci"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2x1_intc 0>, - <0 0 0 2 &pcie2x1_intc 1>, - <0 0 0 3 &pcie2x1_intc 2>, - <0 0 0 4 &pcie2x1_intc 3>; - linux,pci-domain = <0>; - num-ib-windows = <6>; - num-viewport = <8>; - num-ob-windows = <2>; - max-link-speed = <2>; - msi-map = <0x0 &its 0x0 0x1000>; - num-lanes = <1>; - phys = <&combphy2_psq PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3568_PD_PIPE>; - ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000 - 0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000 - 0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x1e00000 - 0xc3000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>; - reg = <0x3 0xc0000000 0x0 0x400000>, - <0x0 0xfe260000 0x0 0x10000>; - reg-names = "pcie-dbi", "pcie-apb"; - resets = <&cru SRST_PCIE20_POWERUP>; - reset-names = "pipe"; - status = "disabled"; - - pcie2x1_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pcie3x1: pcie@fe270000 { - compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x10 0x1f>; - clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, - <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, - <&cru CLK_PCIE30X1_AUX_NDFT>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; - device_type = "pci"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3x1_intc 0>, - <0 0 0 2 &pcie3x1_intc 1>, - <0 0 0 3 &pcie3x1_intc 2>, - <0 0 0 4 &pcie3x1_intc 3>; - linux,pci-domain = <1>; - num-ib-windows = <6>; - num-ob-windows = <2>; - num-viewport = <8>; - max-link-speed = <3>; - msi-map = <0x1000 &its 0x1000 0x1000>; - num-lanes = <1>; - phys = <&pcie30phy>; - phy-names = "pcie-phy"; - power-domains = <&power RK3568_PD_PIPE>; - ranges = <0x00000800 0x0 0xf2000000 0x0 0xf2000000 0x0 0x100000 - 0x81000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x100000 - 0x82000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x1e00000 - 0xc3000000 0x3 0x40000000 0x3 0x40000000 0x0 0x40000000>; - reg = <0x3 0xc0400000 0x0 0x400000>, - <0x0 0xfe270000 0x0 0x10000>; - reg-names = "pcie-dbi", "pcie-apb"; - resets = <&cru SRST_PCIE30X1_POWERUP>; - reset-names = "pipe"; - /* rockchip,bifurcation; lane1 when using 1+1 */ - status = "disabled"; - - pcie3x1_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pcie3x2: pcie@fe280000 { - compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x20 0x2f>; - clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, - <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, - <&cru CLK_PCIE30X2_AUX_NDFT>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; - device_type = "pci"; - interrupts = , - , - , - , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, - <0 0 0 2 &pcie3x2_intc 1>, - <0 0 0 3 &pcie3x2_intc 2>, - <0 0 0 4 &pcie3x2_intc 3>; - linux,pci-domain = <2>; - num-ib-windows = <6>; - num-viewport = <8>; - num-ob-windows = <2>; - max-link-speed = <3>; - msi-map = <0x2000 &its 0x2000 0x1000>; - num-lanes = <2>; - phys = <&pcie30phy>; - phy-names = "pcie-phy"; - power-domains = <&power RK3568_PD_PIPE>; - ranges = <0x00000800 0x0 0xf0000000 0x0 0xf0000000 0x0 0x100000 - 0x81000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x100000 - 0x82000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x1e00000 - 0xc3000000 0x3 0x80000000 0x3 0x80000000 0x0 0x40000000>; - reg = <0x3 0xc0800000 0x0 0x400000>, - <0x0 0xfe280000 0x0 0x10000>; - reg-names = "pcie-dbi", "pcie-apb"; - resets = <&cru SRST_PCIE30X2_POWERUP>; - reset-names = "pipe"; - /* rockchip,bifurcation; lane0 when using 1+1 */ - status = "disabled"; - - pcie3x2_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - gmac_uio0: uio@fe2a0000 { - compatible = "rockchip,uio-gmac"; - reg = <0x0 0xfe2a0000 0x0 0x10000>; - rockchip,ethernet = <&gmac0>; - status = "disabled"; - }; - - gmac0: ethernet@fe2a0000 { - compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe2a0000 0x0 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - rockchip,grf = <&grf>; - clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, - <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, - <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, - <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>, - <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_refout", - "aclk_mac", "pclk_mac", - "clk_mac_speed", "ptp_ref", - "pclk_xpcs", "clk_xpcs_eee"; - resets = <&cru SRST_A_GMAC0>; - reset-names = "stmmaceth"; - - snps,mixed-burst; - snps,tso; - - snps,axi-config = <&gmac0_stmmac_axi_setup>; - snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; - status = "disabled"; - - mdio0: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - gmac0_stmmac_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <4>; - snps,rd_osr_lmt = <8>; - snps,blen = <0 0 0 0 16 8 4>; - }; - - gmac0_mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <1>; - queue0 {}; - }; - - gmac0_mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <1>; - queue0 {}; - }; - }; - - sdmmc0: dwmmc@fe2b0000 { - compatible = "rockchip,rk3568-dw-mshc", - "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe2b0000 0x0 0x4000>; - interrupts = ; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, - <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - resets = <&cru SRST_SDMMC0>; - reset-names = "reset"; - status = "disabled"; - }; - - sdmmc1: dwmmc@fe2c0000 { - compatible = "rockchip,rk3568-dw-mshc", - "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe2c0000 0x0 0x4000>; - interrupts = ; - max-frequency = <150000000>; - clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, - <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - resets = <&cru SRST_SDMMC1>; - reset-names = "reset"; - status = "disabled"; - }; - - sfc: spi@fe300000 { - compatible = "rockchip,sfc"; - reg = <0x0 0xfe300000 0x0 0x4000>; - interrupts = ; - clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; - clock-names = "clk_sfc", "hclk_sfc"; - assigned-clocks = <&cru SCLK_SFC>; - assigned-clock-rates = <100000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sdhci: sdhci@fe310000 { - compatible = "rockchip,rk3568-dwcmshc", "rockchip,dwcmshc-sdhci"; - reg = <0x0 0xfe310000 0x0 0x10000>; - interrupts = ; - assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, - <&cru CCLK_EMMC>; - assigned-clock-rates = <200000000>, <24000000>, <200000000>; - clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, - <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, - <&cru TCLK_EMMC>; - clock-names = "core", "bus", "axi", "block", "timer"; - resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, - <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, - <&cru SRST_T_EMMC>; - reset-names = "core", "bus", "axi", "block", "timer"; - status = "disabled"; - }; - - nandc0: nandc@fe330000 { - compatible = "rockchip,rk-nandc-v9"; - reg = <0x0 0xfe330000 0x0 0x4000>; - interrupts = ; - nandc_id = <0>; - clocks = <&cru NCLK_NANDC>, <&cru HCLK_NANDC>; - clock-names = "clk_nandc", "hclk_nandc"; - status = "disabled"; - }; - - crypto: crypto@fe380000 { - compatible = "rockchip,rk3568-crypto"; - reg = <0x0 0xfe380000 0x0 0x4000>; - interrupts = ; - clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>, - <&cru CLK_CRYPTO_NS_CORE>, <&cru CLK_CRYPTO_NS_PKA>; - clock-names = "aclk", "hclk", "sclk", "apb_pclk"; - assigned-clocks = <&cru CLK_CRYPTO_NS_CORE>; - assigned-clock-rates = <200000000>; - resets = <&cru SRST_CRYPTO_NS_CORE>; - reset-names = "crypto-rst"; - status = "disabled"; - }; - - rng: rng@fe388000 { - compatible = "rockchip,cryptov2-rng"; - reg = <0x0 0xfe388000 0x0 0x2000>; - clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>; - clock-names = "clk_trng", "hclk_trng"; - resets = <&cru SRST_TRNG_NS>; - reset-names = "reset"; - status = "disabled"; - }; - - otp: otp@fe38c000 { - compatible = "rockchip,rk3568-otp"; - reg = <0x0 0xfe38c000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru CLK_OTPC_NS_USR>, <&cru CLK_OTPC_NS_SBPI>, - <&cru PCLK_OTPC_NS>, <&cru PCLK_OTPPHY>; - clock-names = "usr", "sbpi", "apb", "phy"; - resets = <&cru SRST_OTPPHY>; - reset-names = "otp_phy"; - - /* Data cells */ - cpu_code: cpu-code@2 { - reg = <0x02 0x2>; - }; - otp_cpu_version: cpu-version@8 { - reg = <0x08 0x1>; - bits = <3 3>; - }; - mbist_vmin: mbist-vmin@9 { - reg = <0x09 0x1>; - bits = <0 4>; - }; - otp_id: id@a { - reg = <0x0a 0x10>; - }; - cpu_leakage: cpu-leakage@1a { - reg = <0x1a 0x1>; - }; - log_leakage: log-leakage@1b { - reg = <0x1b 0x1>; - }; - npu_leakage: npu-leakage@1c { - reg = <0x1c 0x1>; - }; - gpu_leakage: gpu-leakage@1d { - reg = <0x1d 0x1>; - }; - core_pvtm:core-pvtm@2a { - reg = <0x2a 0x2>; - }; - cpu_tsadc_trim_l: cpu-tsadc-trim-l@2e { - reg = <0x2e 0x1>; - }; - cpu_tsadc_trim_h: cpu-tsadc-trim-h@2f { - reg = <0x2f 0x1>; - bits = <0 4>; - }; - gpu_tsadc_trim_l: npu-tsadc-trim-l@30 { - reg = <0x30 0x1>; - }; - gpu_tsadc_trim_h: npu-tsadc-trim-h@31 { - reg = <0x31 0x1>; - bits = <0 4>; - }; - tsadc_trim_base_frac: tsadc-trim-base-frac@31 { - reg = <0x31 0x1>; - bits = <4 4>; - }; - tsadc_trim_base: tsadc-trim-base@32 { - reg = <0x32 0x1>; - }; - cpu_opp_info: cpu-opp-info@36 { - reg = <0x36 0x6>; - }; - gpu_opp_info: gpu-opp-info@3c { - reg = <0x3c 0x6>; - }; - npu_opp_info: npu-opp-info@42 { - reg = <0x42 0x6>; - }; - dmc_opp_info: dmc-opp-info@48 { - reg = <0x48 0x6>; - }; - }; - - i2s0_8ch: i2s@fe400000 { - compatible = "rockchip,rk3568-i2s-tdm"; - reg = <0x0 0xfe400000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - dmas = <&dmac1 0>; - dma-names = "tx"; - resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,cru = <&cru>; - rockchip,grf = <&grf>; - rockchip,playback-only; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s1_8ch: i2s@fe410000 { - compatible = "rockchip,rk3568-i2s-tdm"; - reg = <0x0 0xfe410000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - dmas = <&dmac1 2>, <&dmac1 3>; - dma-names = "tx", "rx"; - resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,cru = <&cru>; - rockchip,grf = <&grf>; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_sclktx - &i2s1m0_sclkrx - &i2s1m0_lrcktx - &i2s1m0_lrckrx - &i2s1m0_sdi0 - &i2s1m0_sdi1 - &i2s1m0_sdi2 - &i2s1m0_sdi3 - &i2s1m0_sdo0 - &i2s1m0_sdo1 - &i2s1m0_sdo2 - &i2s1m0_sdo3>; - status = "disabled"; - }; - - i2s2_2ch: i2s@fe420000 { - compatible = "rockchip,rk3568-i2s-tdm"; - reg = <0x0 0xfe420000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - dmas = <&dmac1 4>, <&dmac1 5>; - dma-names = "tx", "rx"; - rockchip,cru = <&cru>; - rockchip,grf = <&grf>; - rockchip,clk-trcm = <1>; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2m0_sclktx - &i2s2m0_lrcktx - &i2s2m0_sdi - &i2s2m0_sdo>; - status = "disabled"; - }; - - i2s3_2ch: i2s@fe430000 { - compatible = "rockchip,rk3568-i2s-tdm"; - reg = <0x0 0xfe430000 0x0 0x1000>; - interrupts = ; - clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, <&cru HCLK_I2S3_2CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - dmas = <&dmac1 6>, <&dmac1 7>; - dma-names = "tx", "rx"; - resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,cru = <&cru>; - rockchip,grf = <&grf>; - rockchip,clk-trcm = <1>; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s3m0_sclk - &i2s3m0_lrck - &i2s3m0_sdi - &i2s3m0_sdo>; - status = "disabled"; - }; - - pdm: pdm@fe440000 { - compatible = "rockchip,rk3568-pdm", "rockchip,pdm"; - reg = <0x0 0xfe440000 0x0 0x1000>; - clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; - clock-names = "pdm_clk", "pdm_hclk"; - dmas = <&dmac1 9>; - dma-names = "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pdmm0_clk - &pdmm0_clk1 - &pdmm0_sdi0 - &pdmm0_sdi1 - &pdmm0_sdi2 - &pdmm0_sdi3>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - vad: vad@fe450000 { - compatible = "rockchip,rk3568-vad"; - reg = <0x0 0xfe450000 0x0 0x10000>; - reg-names = "vad"; - clocks = <&cru HCLK_VAD>; - clock-names = "hclk"; - interrupts = ; - rockchip,audio-src = <0>; - rockchip,det-channel = <0>; - rockchip,mode = <0>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - spdif_8ch: spdif@fe460000 { - compatible = "rockchip,rk3568-spdif"; - reg = <0x0 0xfe460000 0x0 0x1000>; - interrupts = ; - dmas = <&dmac1 1>; - dma-names = "tx"; - clock-names = "mclk", "hclk"; - clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spdifm0_tx>; - status = "disabled"; - }; - - audpwm: audpwm@fe470000 { - compatible = "rockchip,rk3568-audio-pwm", "rockchip,audio-pwm-v1"; - reg = <0x0 0xfe470000 0x0 0x1000>; - clocks = <&cru SCLK_AUDPWM>, <&cru HCLK_AUDPWM>; - clock-names = "clk", "hclk"; - dmas = <&dmac1 8>; - dma-names = "tx"; - #sound-dai-cells = <0>; - rockchip,sample-width-bits = <11>; - rockchip,interpolat-points = <1>; - status = "disabled"; - }; - - dig_acodec: codec-digital@fe478000 { - compatible = "rockchip,rk3568-codec-digital", "rockchip,codec-digital-v1"; - reg = <0x0 0xfe478000 0x0 0x1000>; - clocks = <&cru CLK_ACDCDIG_ADC>, <&cru CLK_ACDCDIG_DAC>, - <&cru CLK_ACDCDIG_I2C>, <&cru HCLK_ACDCDIG>; - clock-names = "adc", "dac", "i2c", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&acodec_pins>; - resets = <&cru SRST_ACDCDIG>; - reset-names = "reset" ; - rockchip,grf = <&grf>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - dmac0: dmac@fe530000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfe530000 0x0 0x4000>; - interrupts = , - ; - clocks = <&cru ACLK_BUS>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - arm,pl330-periph-burst; - }; - - dmac1: dmac@fe550000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfe550000 0x0 0x4000>; - interrupts = , - ; - clocks = <&cru ACLK_BUS>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - arm,pl330-periph-burst; - }; - - scr: rkscr@fe560000 { - compatible = "rockchip-scr"; - reg = <0x0 0xfe560000 0x0 0x10000>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&scr_pins>; - clocks = <&cru PCLK_SCR>; - clock-names = "g_pclk_sim_card"; - status = "disabled"; - }; - - can0: can@fe570000 { - compatible = "rockchip,rk3568-can-2.0"; - reg = <0x0 0xfe570000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; - clock-names = "baudclk", "apb_pclk"; - resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>; - reset-names = "can", "can-apb"; - tx-fifo-depth = <1>; - rx-fifo-depth = <6>; - status = "disabled"; - }; - - can1: can@fe580000 { - compatible = "rockchip,rk3568-can-2.0"; - reg = <0x0 0xfe580000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; - clock-names = "baudclk", "apb_pclk"; - resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>; - reset-names = "can", "can-apb"; - tx-fifo-depth = <1>; - rx-fifo-depth = <6>; - status = "disabled"; - }; - - can2: can@fe590000 { - compatible = "rockchip,rk3568-can-2.0"; - reg = <0x0 0xfe590000 0x0 0x1000>; - interrupts = ; - clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>; - clock-names = "baudclk", "apb_pclk"; - resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>; - reset-names = "can", "can-apb"; - tx-fifo-depth = <1>; - rx-fifo-depth = <6>; - status = "disabled"; - }; - - i2c1: i2c@fe5a0000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5a0000 0x0 0x1000>; - clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@fe5b0000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5b0000 0x0 0x1000>; - clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2m0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@fe5c0000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5c0000 0x0 0x1000>; - clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3m0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@fe5d0000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5d0000 0x0 0x1000>; - clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c4m0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@fe5e0000 { - compatible = "rockchip,rk3399-i2c"; - reg = <0x0 0xfe5e0000 0x0 0x1000>; - clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; - clock-names = "i2c", "pclk"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5m0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - rktimer: timer@fe5f0000 { - compatible = "rockchip,rk3568-timer", "rockchip,rk3288-timer"; - reg = <0x0 0xfe5f0000 0x0 0x1000>; - interrupts = ; - clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; - clock-names = "pclk", "timer"; - }; - - wdt: watchdog@fe600000 { - compatible = "snps,dw-wdt"; - reg = <0x0 0xfe600000 0x0 0x100>; - clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; - clock-names = "tclk", "pclk"; - interrupts = ; - status = "okay"; - }; - - spi0: spi@fe610000 { - compatible = "rockchip,rk3066-spi"; - reg = <0x0 0xfe610000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 20>, <&dmac0 21>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "high_speed"; - pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; - pinctrl-1 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins_hs>; - num-cs = <2>; - status = "disabled"; - }; - - spi1: spi@fe620000 { - compatible = "rockchip,rk3066-spi"; - reg = <0x0 0xfe620000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 22>, <&dmac0 23>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "high_speed"; - pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; - pinctrl-1 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins_hs>; - num-cs = <2>; - status = "disabled"; - }; - - spi2: spi@fe630000 { - compatible = "rockchip,rk3066-spi"; - reg = <0x0 0xfe630000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 24>, <&dmac0 25>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "high_speed"; - pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; - pinctrl-1 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins_hs>; - num-cs = <2>; - status = "disabled"; - }; - - spi3: spi@fe640000 { - compatible = "rockchip,rk3066-spi"; - reg = <0x0 0xfe640000 0x0 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 26>, <&dmac0 27>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "high_speed"; - pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; - pinctrl-1 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins_hs>; - num-cs = <2>; - status = "disabled"; - }; - - uart1: serial@fe650000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe650000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac0 2>, <&dmac0 3>; - pinctrl-names = "default"; - pinctrl-0 = <&uart1m0_xfer>; - status = "disabled"; - }; - - uart2: serial@fe660000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe660000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac0 4>, <&dmac0 5>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer>; - status = "disabled"; - }; - - uart3: serial@fe670000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe670000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac0 6>, <&dmac0 7>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3m0_xfer>; - status = "disabled"; - }; - - uart4: serial@fe680000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe680000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac0 8>, <&dmac0 9>; - pinctrl-names = "default"; - pinctrl-0 = <&uart4m0_xfer>; - status = "disabled"; - }; - - uart5: serial@fe690000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe690000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac0 10>, <&dmac0 11>; - pinctrl-names = "default"; - pinctrl-0 = <&uart5m0_xfer>; - status = "disabled"; - }; - - uart6: serial@fe6a0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6a0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac0 12>, <&dmac0 13>; - pinctrl-names = "default"; - pinctrl-0 = <&uart6m0_xfer>; - status = "disabled"; - }; - - uart7: serial@fe6b0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6b0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac0 14>, <&dmac0 15>; - pinctrl-names = "default"; - pinctrl-0 = <&uart7m0_xfer>; - status = "disabled"; - }; - - uart8: serial@fe6c0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6c0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac0 16>, <&dmac0 17>; - pinctrl-names = "default"; - pinctrl-0 = <&uart8m0_xfer>; - status = "disabled"; - }; - - uart9: serial@fe6d0000 { - compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfe6d0000 0x0 0x100>; - interrupts = ; - clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&dmac0 18>, <&dmac0 19>; - pinctrl-names = "default"; - pinctrl-0 = <&uart9m0_xfer>; - status = "disabled"; - }; - - pwm4: pwm@fe6e0000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0000 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm4_pins>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm5: pwm@fe6e0010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0010 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm5_pins>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm6: pwm@fe6e0020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0020 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm6_pins>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm7: pwm@fe6e0030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6e0030 0x0 0x10>; - interrupts = , - ; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm7_pins>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm8: pwm@fe6f0000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0000 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm8m0_pins>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm9: pwm@fe6f0010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0010 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm9m0_pins>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm10: pwm@fe6f0020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0020 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm10m0_pins>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm11: pwm@fe6f0030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe6f0030 0x0 0x10>; - interrupts = , - ; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm11m0_pins>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm12: pwm@fe700000 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700000 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm12m0_pins>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm13: pwm@fe700010 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700010 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm13m0_pins>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm14: pwm@fe700020 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700020 0x0 0x10>; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm14m0_pins>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - pwm15: pwm@fe700030 { - compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfe700030 0x0 0x10>; - interrupts = , - ; - #pwm-cells = <3>; - pinctrl-names = "active"; - pinctrl-0 = <&pwm15m0_pins>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - status = "disabled"; - }; - - tsadc: tsadc@fe710000 { - compatible = "rockchip,rk3568-tsadc"; - reg = <0x0 0xfe710000 0x0 0x100>; - interrupts = ; - rockchip,grf = <&grf>; - clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; - assigned-clock-rates = <17000000>, <700000>; - resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, - <&cru SRST_TSADCPHY>; - reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; - #thermal-sensor-cells = <1>; - nvmem-cells = <&tsadc_trim_base>, <&tsadc_trim_base_frac>; - nvmem-cell-names = "trim_base", "trim_base_frac"; - rockchip,hw-tshut-temp = <120000>; - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - pinctrl-names = "gpio", "otpout"; - pinctrl-0 = <&tsadc_gpio_func>; - pinctrl-1 = <&tsadc_shutorg>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - tsadc@0 { - reg = <0>; - nvmem-cells = <&cpu_tsadc_trim_l>, <&cpu_tsadc_trim_h>; - nvmem-cell-names = "trim_l", "trim_h"; - }; - tsadc@1 { - reg = <1>; - nvmem-cells = <&gpu_tsadc_trim_l>, <&gpu_tsadc_trim_h>; - nvmem-cell-names = "trim_l", "trim_h"; - }; - }; - - saradc: saradc@fe720000 { - compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; - reg = <0x0 0xfe720000 0x0 0x100>; - interrupts = ; - #io-channel-cells = <1>; - clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_P_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - mailbox: mailbox@fe780000 { - compatible = "rockchip,rk3568-mailbox", - "rockchip,rk3368-mailbox"; - reg = <0x0 0xfe780000 0x0 0x1000>; - interrupts = , - , - , - ; - clocks = <&cru PCLK_MAILBOX>; - clock-names = "pclk_mailbox"; - #mbox-cells = <1>; - status = "disabled"; - }; - - combphy0_us: phy@fe820000 { - compatible = "rockchip,rk3568-naneng-combphy"; - reg = <0x0 0xfe820000 0x0 0x100>; - #phy-cells = <1>; - clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>, - <&cru PCLK_PIPE>; - clock-names = "refclk", "apbclk", "pipe_clk"; - assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; - assigned-clock-rates = <100000000>; - resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; - reset-names = "combphy-apb", "combphy"; - rockchip,pipe-grf = <&pipegrf>; - rockchip,pipe-phy-grf = <&pipe_phy_grf0>; - status = "disabled"; - }; - - combphy1_usq: phy@fe830000 { - compatible = "rockchip,rk3568-naneng-combphy"; - reg = <0x0 0xfe830000 0x0 0x100>; - #phy-cells = <1>; - clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>, - <&cru PCLK_PIPE>; - clock-names = "refclk", "apbclk", "pipe_clk"; - assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; - assigned-clock-rates = <100000000>; - resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>; - reset-names = "combphy-apb", "combphy"; - rockchip,pipe-grf = <&pipegrf>; - rockchip,pipe-phy-grf = <&pipe_phy_grf1>; - status = "disabled"; - }; - - combphy2_psq: phy@fe840000 { - compatible = "rockchip,rk3568-naneng-combphy"; - reg = <0x0 0xfe840000 0x0 0x100>; - #phy-cells = <1>; - clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>, - <&cru PCLK_PIPE>; - clock-names = "refclk", "apbclk", "pipe_clk"; - assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; - assigned-clock-rates = <100000000>; - resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>; - reset-names = "combphy-apb", "combphy"; - rockchip,pipe-grf = <&pipegrf>; - rockchip,pipe-phy-grf = <&pipe_phy_grf2>; - status = "disabled"; - }; - - video_phy0: phy@fe850000 { - compatible = "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy"; - reg = <0x0 0xfe850000 0x0 0x10000>, - <0x0 0xfe060000 0x0 0x10000>; - reg-names = "phy", "host"; - clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, - <&cru PCLK_MIPIDSIPHY0>, <&cru PCLK_DSITX_0>; - clock-names = "ref", "pclk", "pclk_host"; - #clock-cells = <0>; - resets = <&cru SRST_P_MIPIDSIPHY0>; - reset-names = "apb"; - power-domains = <&power RK3568_PD_VO>; - #phy-cells = <0>; - status = "disabled"; - }; - - video_phy1: phy@fe860000 { - compatible = "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy"; - reg = <0x0 0xfe860000 0x0 0x10000>, - <0x0 0xfe070000 0x0 0x10000>; - reg-names = "phy", "host"; - clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, - <&cru PCLK_MIPIDSIPHY1>, <&cru PCLK_DSITX_1>; - clock-names = "ref", "pclk", "pclk_host"; - #clock-cells = <0>; - resets = <&cru SRST_P_MIPIDSIPHY1>; - reset-names = "apb"; - power-domains = <&power RK3568_PD_VO>; - #phy-cells = <0>; - status = "disabled"; - }; - - csi2_dphy_hw: csi2-dphy-hw@fe870000 { - compatible = "rockchip,rk3568-csi2-dphy-hw"; - reg = <0x0 0xfe870000 0x0 0x1000>; - clocks = <&cru PCLK_MIPICSIPHY>; - clock-names = "pclk"; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - /* - * csi2_dphy0: used for csi2 dphy full mode, - is mutually exclusive with - csi2_dphy1 and csi2_dphy2 - * csi2_dphy1: used for csi2 dphy split mode, - physical lanes use lane0 and lane1, - can be used with csi2_dphy2 parallel - * csi2_dphy2: used for csi2 dphy split mode, - physical lanes use lane2 and lane3, - can be used with csi2_dphy1 parallel - */ - csi2_dphy0: csi2-dphy0 { - compatible = "rockchip,rk3568-csi2-dphy"; - rockchip,hw = <&csi2_dphy_hw>; - status = "disabled"; - }; - - csi2_dphy1: csi2-dphy1 { - compatible = "rockchip,rk3568-csi2-dphy"; - rockchip,hw = <&csi2_dphy_hw>; - status = "disabled"; - }; - - csi2_dphy2: csi2-dphy2 { - compatible = "rockchip,rk3568-csi2-dphy"; - rockchip,hw = <&csi2_dphy_hw>; - status = "disabled"; - }; - - usb2phy0: usb2-phy@fe8a0000 { - compatible = "rockchip,rk3568-usb2phy"; - reg = <0x0 0xfe8a0000 0x0 0x10000>; - interrupts = ; - clocks = <&pmucru CLK_USBPHY0_REF>; - clock-names = "phyclk"; - #clock-cells = <0>; - assigned-clocks = <&cru USB480M>; - assigned-clock-parents = <&usb2phy0>; - clock-output-names = "usb480m_phy"; - rockchip,usbgrf = <&usb2phy0_grf>; - status = "disabled"; - - u2phy0_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy0_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - - usb2phy1: usb2-phy@fe8b0000 { - compatible = "rockchip,rk3568-usb2phy"; - reg = <0x0 0xfe8b0000 0x0 0x10000>; - interrupts = ; - clocks = <&pmucru CLK_USBPHY1_REF>; - clock-names = "phyclk"; - #clock-cells = <0>; - rockchip,usbgrf = <&usb2phy1_grf>; - status = "disabled"; - - u2phy1_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy1_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - - pcie30phy: phy@fe8c0000 { - compatible = "rockchip,rk3568-pcie3-phy"; - reg = <0x0 0xfe8c0000 0x0 0x20000>; - #phy-cells = <0>; - clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, - <&cru PCLK_PCIE30PHY>; - clock-names = "refclk_m", "refclk_n", "pclk"; - resets = <&cru SRST_PCIE30PHY>; - reset-names = "phy"; - rockchip,phy-grf = <&pcie30_phy_grf>; - status = "disabled"; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3568-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio0@fdd60000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfdd60000 0x0 0x100>; - interrupts = ; - clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@fe740000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe740000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@fe750000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe750000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@fe760000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe760000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio4@fe770000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfe770000 0x0 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; - - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; -}; - -#include "rk3568-pinctrl.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam0.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam0.dtsi deleted file mode 100644 index a287e4bcf..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam0.dtsi +++ /dev/null @@ -1,79 +0,0 @@ -&i2c0 { - status = "okay"; -}; - -&dcphy0_dw9714 { - status = "disabled"; -}; - -&dcphy0_ov5647 { - status = "disabled"; -}; - -&dcphy0_ov5648 { - status = "disabled"; -}; - -&dcphy0_ov8858 { - status = "disabled"; -}; - -&dcphy0_ov13850 { - status = "disabled"; -}; - -&dcphy0_imx415 { - status = "okay"; -}; - -&dcphy0_gc08a8 { - status = "disabled"; -}; - -&dcphy0_gc2053 { - status = "disabled"; -}; - -&dcphy0_gc4653 { - status = "disabled"; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&csi2_dcphy0 { - status = "okay"; -}; - -&mipi0_csi2 { - status = "okay"; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds { - status = "okay"; -}; - -&rkcif_mipi_lvds_sditf { - status = "okay"; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp0 { - status = "okay"; -}; - -&isp0_mmu { - status = "okay"; -}; - -&rkisp0_vir0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam1.dtsi deleted file mode 100644 index 391a6735d..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam1.dtsi +++ /dev/null @@ -1,79 +0,0 @@ -&i2c1 { - status = "okay"; -}; - -&dcphy1_dw9714 { - status = "disabled"; -}; - -&dcphy1_ov5647 { - status = "disabled"; -}; - -&dcphy1_ov5648 { - status = "disabled"; -}; - -&dcphy1_ov8858 { - status = "disabled"; -}; - -&dcphy1_ov13850 { - status = "disabled"; -}; - -&dcphy1_imx415 { - status = "okay"; -}; - -&dcphy1_gc08a8 { - status = "disabled"; -}; - -&dcphy1_gc2053 { - status = "disabled"; -}; - -&dcphy1_gc4653 { - status = "disabled"; -}; - -&csi2_dcphy1 { - status = "okay"; -}; - -&mipi1_csi2 { - status = "okay"; -}; - -&mipi_dcphy1 { - status = "okay"; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds1 { - status = "okay"; -}; - -&rkcif_mipi_lvds1_sditf { - status = "okay"; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp1 { - status = "okay"; -}; - -&isp1_mmu { - status = "okay"; -}; - -&rkisp1_vir0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam2.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam2.dtsi deleted file mode 100644 index 4bc8faa45..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam2.dtsi +++ /dev/null @@ -1,79 +0,0 @@ -&i2c2 { - status = "okay"; -}; - -&dphy1_dw9714 { - status = "disabled"; -}; - -&dphy1_ov5647 { - status = "disabled"; -}; - -&dphy1_ov5648 { - status = "disabled"; -}; - -&dphy1_ov8858 { - status = "disabled"; -}; - -&dphy1_ov13850 { - status = "disabled"; -}; - -&dphy1_imx415 { - status = "okay"; -}; - -&dphy1_gc08a8 { - status = "disabled"; -}; - -&dphy1_gc2053 { - status = "disabled"; -}; - -&dphy1_gc4653 { - status = "disabled"; -}; - -&csi2_dphy0_hw { - status = "okay"; -}; - -&csi2_dphy1 { - status = "okay"; -}; - -&mipi2_csi2 { - status = "okay"; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds2 { - status = "okay"; -}; - -&rkcif_mipi_lvds2_sditf { - status = "okay"; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp0 { - status = "okay"; -}; - -&isp0_mmu { - status = "okay"; -}; - -&rkisp0_vir2 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam3.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam3.dtsi deleted file mode 100644 index 01e8db69d..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam3.dtsi +++ /dev/null @@ -1,79 +0,0 @@ -&i2c5 { - status = "okay"; -}; - -&dphy2_dw9714 { - status = "disabled"; -}; - -&dphy2_ov5647 { - status = "disabled"; -}; - -&dphy2_ov5648 { - status = "disabled"; -}; - -&dphy2_ov8858 { - status = "disabled"; -}; - -&dphy2_ov13850 { - status = "disabled"; -}; - -&dphy2_imx415 { - status = "okay"; -}; - -&dphy2_gc08a8 { - status = "disabled"; -}; - -&dphy2_gc2053 { - status = "disabled"; -}; - -&dphy2_gc4653 { - status = "disabled"; -}; - -&csi2_dphy0_hw { - status = "okay"; -}; - -&csi2_dphy2 { - status = "okay"; -}; - -&mipi3_csi2 { - status = "okay"; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds3 { - status = "okay"; -}; - -&rkcif_mipi_lvds3_sditf { - status = "okay"; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp0 { - status = "okay"; -}; - -&isp0_mmu { - status = "okay"; -}; - -&rkisp0_vir1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam4.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam4.dtsi deleted file mode 100644 index 233807c3b..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam4.dtsi +++ /dev/null @@ -1,79 +0,0 @@ -&i2c7 { - status = "okay"; -}; - -&dphy4_dw9714 { - status = "disabled"; -}; - -&dphy4_ov5647 { - status = "disabled"; -}; - -&dphy4_ov5648 { - status = "disabled"; -}; - -&dphy4_ov8858 { - status = "disabled"; -}; - -&dphy4_ov13850 { - status = "disabled"; -}; - -&dphy4_imx415 { - status = "okay"; -}; - -&dphy4_gc08a8 { - status = "disabled"; -}; - -&dphy4_gc2053 { - status = "disabled"; -}; - -&dphy4_gc4653 { - status = "disabled"; -}; - -&csi2_dphy1_hw { - status = "okay"; -}; - -&csi2_dphy4 { - status = "okay"; -}; - -&mipi4_csi2 { - status = "okay"; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds4 { - status = "okay"; -}; - -&rkcif_mipi_lvds4_sditf { - status = "okay"; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp1 { - status = "okay"; -}; - -&isp1_mmu { - status = "okay"; -}; - -&rkisp1_vir1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam5.dtsi deleted file mode 100644 index 683e9f70b..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam5.dtsi +++ /dev/null @@ -1,79 +0,0 @@ -&i2c8 { - status = "okay"; -}; - -&dphy5_dw9714 { - status = "disabled"; -}; - -&dphy5_ov5647 { - status = "disabled"; -}; - -&dphy5_ov5648 { - status = "disabled"; -}; - -&dphy5_ov8858 { - status = "disabled"; -}; - -&dphy5_ov13850 { - status = "disabled"; -}; - -&dphy5_imx415 { - status = "okay"; -}; - -&dphy5_gc08a8 { - status = "disabled"; -}; - -&dphy5_gc2053 { - status = "disabled"; -}; - -&dphy5_gc4653 { - status = "disabled"; -}; - -&csi2_dphy1_hw { - status = "okay"; -}; - -&csi2_dphy5 { - status = "okay"; -}; - -&mipi5_csi2 { - status = "okay"; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds5 { - status = "okay"; -}; - -&rkcif_mipi_lvds5_sditf { - status = "okay"; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp1 { - status = "okay"; -}; - -&isp1_mmu { - status = "okay"; -}; - -&rkisp1_vir2 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-csi.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-csi.dtsi deleted file mode 100644 index f38c1b7ea..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-csi.dtsi +++ /dev/null @@ -1,2269 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Rockchip Electronics Co., Ltd. - * - */ - - -#include "rk3588-lubancat-cam.dtsi" - -//CAM 0 -/* Link path: sensor->csi2_dcphy0->mipi0_csi2->rkcif_mipi_lvds--->rkcif_mipi_lvds_sditf->rkisp0_vir0 */ -&i2c0 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - - dcphy0_dw9714: dcphy0-dw9714@c { - status = "disabled"; - compatible = "dongwoon,dw9714"; - reg = <0xc>; - rockchip,camera-module-index = <0>; - rockchip,vcm-max-current = <100>; - rockchip,vcm-start-current = <0>; - rockchip,vcm-rated-current = <100>; - rockchip,vcm-step-mode = <0xd>; - rockchip,vcm-dlc-enable = <0>; - rockchip,vcm-mclk = <0>; - rockchip,vcm-t-src = <0>; - rockchip,camera-module-facing = "back"; - }; - - dcphy0_ov5647: dcphy0-ov5647@36 { - compatible = "ovti,ov5647"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_25m_clk>; - clock-names = "ext_cam_25m_clk"; - pwdn-gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; - lens-focus = <&dcphy0_dw9714>; - - port { - ov5647_dcphy0_out: endpoint { - remote-endpoint = <&dcphy0_in_ov5647>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy0_ov5648: dcphy0-ov5648@36 { - compatible = "ovti,ov5648"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 1 GPIO_ACTIVE_LOW>; - rotation = <180>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "THDS11073"; - rockchip,camera-module-lens-name = "Largan-40122a1"; - lens-focus = <&dcphy0_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov5648_dcphy0_out: endpoint { - remote-endpoint = <&dcphy0_in_ov5648>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy0_ov8858: dcphy0-ov8858@36 { - compatible = "ovti,ov8858"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>; - rotation = <180>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "HS5885-BNSM1018-V01"; - rockchip,camera-module-lens-name = "default"; - lens-focus = <&dcphy0_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov8858_dcphy0_out: endpoint { - remote-endpoint = <&dcphy0_in_ov8858>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy0_ov13850: dcphy0-ov13850@10 { - compatible = "ovti,ov13850"; - status = "disabled"; - reg = <0x10>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>; - rotation = <180>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "ZC-OV13850R2A-V1"; - rockchip,camera-module-lens-name = "Largan-50064B31"; - lens-focus = <&dcphy0_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov13850_dcphy0_out: endpoint { - remote-endpoint = <&dcphy0_in_ov13850>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy0_imx415: dcphy0-imx415@1a { - compatible = "sony,imx415"; - status = "disabled"; - reg = <0x1a>; - clocks = <&ext_cam_37m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - avdd-supply = <&cam_avdd>; - dovdd-supply = <&cam_dovdd>; - dvdd-supply = <&cam_dvdd>; - pwdn-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 1 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT2022-PX1"; - rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; - // NO_HDR:0 HDR_X2:5 HDR_X3:6 - // rockchip,camera-hdr-mode = <0>; - port { - imx415_dcphy0_out: endpoint { - remote-endpoint = <&dcphy0_in_imx415>; - data-lanes = <1 2 3 4>; - }; - }; - }; - - dcphy0_gc08a8: dcphy0-gc08a8@31 { - compatible = "galaxycore,gc08a8"; - status = "disabled"; - reg = <0x31>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - avdd-supply = <&cam_avdd>; - dovdd-supply = <&cam_dovdd>; - dvdd-supply = <&cam_dvdd>; - pwdn-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 1 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "YT10120"; - rockchip,camera-module-lens-name = "30IRC-4M-F20"; - - port { - gc08a8_dcphy0_out: endpoint { - remote-endpoint = <&dcphy0_in_gc08a8>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy0_gc2053: dcphy0-gc2053@37 { - compatible = "galaxycore,gc2053"; - status = "disabled"; - reg = <0x37>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - avdd-supply = <&cam_avdd>; - dovdd-supply = <&cam_dovdd>; - dvdd-supply = <&cam_dvdd>; - pwdn-gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio6 1 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "SIDA205300461"; - rockchip,camera-module-lens-name = "60IRC-F20"; - - port { - gc2053_dcphy0_out: endpoint { - remote-endpoint = <&dcphy0_in_gc2053>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy0_gc4653: dcphy0-gc4653@29 { - compatible = "galaxycore,gc4653"; - status = "disabled"; - reg = <0x29>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - avdd-supply = <&cam_avdd>; - dovdd-supply = <&cam_dovdd>; - dvdd-supply = <&cam_dvdd>; - pwdn-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "YT10120"; - rockchip,camera-module-lens-name = "30IRC-4M-F20"; - - port { - gc4653_dcphy0_out: endpoint { - remote-endpoint = <&dcphy0_in_gc4653>; - data-lanes = <1 2>; - }; - }; - }; -}; - - -//CAM 1 -/* Link path: sensor->csi2_dcphy1->mipi1_csi2->rkcif_mipi_lvds1--->rkcif_mipi_lvds1_sditf->rkisp0_vir1 */ -&i2c1 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1m2_xfer>; - - dcphy1_dw9714: dcphy1-dw9714@c { - status = "disabled"; - compatible = "dongwoon,dw9714"; - reg = <0xc>; - rockchip,camera-module-index = <1>; - rockchip,vcm-max-current = <100>; - rockchip,vcm-start-current = <0>; - rockchip,vcm-rated-current = <100>; - rockchip,vcm-step-mode = <0xd>; - rockchip,vcm-dlc-enable = <0>; - rockchip,vcm-mclk = <0>; - rockchip,vcm-t-src = <0>; - rockchip,camera-module-facing = "back"; - }; - - dcphy1_ov5647: dcphy1-ov5647@36 { - compatible = "ovti,ov5647"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_25m_clk>; - clock-names = "ext_cam_25m_clk"; - pwdn-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; - lens-focus = <&dcphy1_dw9714>; - - port { - ov5647_dcphy1_out: endpoint { - remote-endpoint = <&dcphy1_in_ov5647>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy1_ov5648: dcphy1-ov5648@36 { - compatible = "ovti,ov5648"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; - rotation = <180>; - - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "THDS11073"; - rockchip,camera-module-lens-name = "Largan-40122a1"; - lens-focus = <&dcphy1_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov5648_dcphy1_out: endpoint { - remote-endpoint = <&dcphy1_in_ov5648>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy1_ov8858: dcphy1-ov8858@36 { - compatible = "ovti,ov8858"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; - rotation = <180>; - - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "HS5885-BNSM1018-V01"; - rockchip,camera-module-lens-name = "default"; - lens-focus = <&dcphy1_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov8858_dcphy1_out: endpoint { - remote-endpoint = <&dcphy1_in_ov8858>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy1_ov13850: dcphy1-ov13850@10 { - compatible = "ovti,ov13850"; - status = "disabled"; - reg = <0x10>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; - rotation = <180>; - - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "ZC-OV13850R2A-V1"; - rockchip,camera-module-lens-name = "Largan-50064B31"; - lens-focus = <&dcphy1_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov13850_dcphy1_out: endpoint { - remote-endpoint = <&dcphy1_in_ov13850>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy1_imx415: dcphy1-imx415@1a { - compatible = "sony,imx415"; - status = "disabled"; - reg = <0x1a>; - clocks = <&ext_cam_37m_clk>; - clock-names = "xvclk"; - // power-domains = <&power RK3588_PD_VI>; - avdd-supply = <&cam_avdd>; - dovdd-supply = <&cam_dovdd>; - dvdd-supply = <&cam_dvdd>; - pwdn-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT2022-PX1"; - rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; - port { - imx415_dcphy1_out: endpoint { - remote-endpoint = <&dcphy1_in_imx415>; - data-lanes = <1 2 3 4>; - }; - }; - }; - - dcphy1_gc08a8: dcphy1-gc08a8@31 { - compatible = "galaxycore,gc08a8"; - status = "disabled"; - reg = <0x31>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - avdd-supply = <&cam_avdd>; - dovdd-supply = <&cam_dovdd>; - dvdd-supply = <&cam_dvdd>; - pwdn-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "YT10120"; - rockchip,camera-module-lens-name = "30IRC-4M-F20"; - port { - gc08a8_dcphy1_out: endpoint { - remote-endpoint = <&dcphy1_in_gc08a8>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy1_gc2053: dcphy1-gc2053@37 { - compatible = "galaxycore,gc2053"; - status = "disabled"; - reg = <0x37>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - avdd-supply = <&cam_avdd>; - dovdd-supply = <&cam_dovdd>; - dvdd-supply = <&cam_dvdd>; - pwdn-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "SIDA205300461"; - rockchip,camera-module-lens-name = "60IRC-F20"; - port { - gc2053_dcphy1_out: endpoint { - remote-endpoint = <&dcphy1_in_gc2053>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy1_gc4653: dcphy1-gc4653@29 { - compatible = "galaxycore,gc4653"; - status = "disabled"; - reg = <0x29>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - avdd-supply = <&cam_avdd>; - dovdd-supply = <&cam_dovdd>; - dvdd-supply = <&cam_dvdd>; - pwdn-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; - - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "YT10120"; - rockchip,camera-module-lens-name = "30IRC-4M-F20"; - port { - gc4653_dcphy1_out: endpoint { - remote-endpoint = <&dcphy1_in_gc4653>; - data-lanes = <1 2>; - }; - }; - }; -}; - -//CAM 2 -/* Link path: sensor->csi2_dphy1->mipi2_csi2->rkcif_mipi_lvds2--->rkcif_mipi_lvds2_sditf->rkisp0_vir2 */ -&i2c2 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2m4_xfer>; - - - dphy1_dw9714: dphy1-dw9714@c { - status = "disabled"; - compatible = "dongwoon,dw9714"; - reg = <0xc>; - rockchip,camera-module-index = <2>; - rockchip,vcm-max-current = <100>; - rockchip,vcm-start-current = <0>; - rockchip,vcm-rated-current = <100>; - rockchip,vcm-step-mode = <0xd>; - rockchip,vcm-dlc-enable = <0>; - rockchip,vcm-mclk = <0>; - rockchip,vcm-t-src = <0>; - rockchip,camera-module-facing = "back"; - }; - - dphy1_ov5647: dphy1-ov5647@36 { - compatible = "ovti,ov5647"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_25m_clk>; - clock-names = "ext_cam_25m_clk"; - pwdn-gpios = <&gpio6 4 GPIO_ACTIVE_LOW>; - lens-focus = <&dphy1_dw9714>; - - port { - ov5647_dphy1_out: endpoint { - remote-endpoint = <&dphy1_in_ov5647>; - data-lanes = <1 2>; - }; - }; - }; - - dphy1_ov5648: dphy1-ov5648@36 { - compatible = "ovti,ov5648"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 5 GPIO_ACTIVE_LOW>; - rotation = <180>; - - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "THDS11073"; - rockchip,camera-module-lens-name = "Largan-40122a1"; - lens-focus = <&dphy1_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov5648_dphy1_out: endpoint { - remote-endpoint = <&dphy1_in_ov5648>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dphy1_ov8858: dphy1-ov8858@36 { - compatible = "ovti,ov8858"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 4 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio6 5 GPIO_ACTIVE_LOW>; - rotation = <180>; - - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "HS5885-BNSM1018-V01"; - rockchip,camera-module-lens-name = "default"; - lens-focus = <&dphy1_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov8858_dphy1_out: endpoint { - remote-endpoint = <&dphy1_in_ov8858>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dphy1_ov13850: dphy1-ov13850@10 { - compatible = "ovti,ov13850"; - status = "disabled"; - reg = <0x10>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>; - rotation = <180>; - - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "ZC-OV13850R2A-V1"; - rockchip,camera-module-lens-name = "Largan-50064B31"; - lens-focus = <&dphy1_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov13850_dphy1_out: endpoint { - remote-endpoint = <&dphy1_in_ov13850>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dphy1_imx415: dphy1-imx415@1a { - compatible = "sony,imx415"; - status = "disabled"; - reg = <0x1a>; - clocks = <&ext_cam_37m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - // pwdn-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 5 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT2022-PX1"; - rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; - rockchip,imx415-data-lanes=<2>; - // NO_HDR:0 HDR_X2:5 HDR_X3:6 - // rockchip,camera-hdr-mode = <0>; - port { - imx415_dphy1_out: endpoint { - remote-endpoint = <&dphy1_in_imx415>; - data-lanes = <1 2>; - }; - }; - }; - - dphy1_gc08a8: dphy1-gc2053@31 { - compatible = "galaxycore,gc08a8"; - status = "disabled"; - reg = <0x31>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 5 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "YT10120"; - rockchip,camera-module-lens-name = "30IRC-4M-F20"; - - port { - gc08a8_dphy1_out: endpoint { - remote-endpoint = <&dphy1_in_gc08a8>; - data-lanes = <1 2>; - }; - }; - }; - - dphy1_gc2053: dphy1-gc2053@37 { - compatible = "galaxycore,gc2053"; - status = "disabled"; - reg = <0x37>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 4 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio6 5 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "SIDA205300461"; - rockchip,camera-module-lens-name = "60IRC-F20"; - - port { - gc2053_dphy1_out: endpoint { - remote-endpoint = <&dphy1_in_gc2053>; - data-lanes = <1 2>; - }; - }; - }; - - dphy1_gc4653: dphy1-gc4653@29 { - compatible = "galaxycore,gc4653"; - status = "disabled"; - reg = <0x29>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - avdd-supply = <&cam_avdd>; - dovdd-supply = <&cam_dovdd>; - dvdd-supply = <&cam_dvdd>; - pwdn-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>; - - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "YT10120"; - rockchip,camera-module-lens-name = "30IRC-4M-F20"; - - port { - gc4653_dphy1_out: endpoint { - remote-endpoint = <&dphy1_in_gc4653>; - data-lanes = <1 2>; - }; - }; - }; -}; - -//CAM 3 -/* Link path: sensor->csi2_dphy2->mipi3_csi2->rkcif_mipi_lvds3--->rkcif_mipi_lvds3_sditf->rkisp1_vir0 */ -&i2c5 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5m3_xfer>; - - dphy2_dw9714: dphy2-dw9714@c { - status = "disabled"; - compatible = "dongwoon,dw9714"; - reg = <0xc>; - rockchip,camera-module-index = <3>; - rockchip,vcm-max-current = <100>; - rockchip,vcm-start-current = <0>; - rockchip,vcm-rated-current = <100>; - rockchip,vcm-step-mode = <0xd>; - rockchip,vcm-dlc-enable = <0>; - rockchip,vcm-mclk = <0>; - rockchip,vcm-t-src = <0>; - rockchip,camera-module-facing = "back"; - }; - - dphy2_ov5647: dphy2-ov5647@36 { - compatible = "ovti,ov5647"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_25m_clk>; - clock-names = "ext_cam_25m_clk"; - pwdn-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - lens-focus = <&dphy2_dw9714>; - - port { - ov5647_dphy2_out: endpoint { - remote-endpoint = <&dphy2_in_ov5647>; - data-lanes = <1 2>; - }; - }; - }; - - dphy2_ov5648: dphy2-ov5648@36 { - compatible = "ovti,ov5648"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 6 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; - rotation = <180>; - - rockchip,camera-module-index = <3>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "THDS11073"; - rockchip,camera-module-lens-name = "Largan-40122a1"; - lens-focus = <&dphy2_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov5648_dphy2_out: endpoint { - remote-endpoint = <&dphy2_in_ov5648>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dphy2_ov8858: dphy2-ov8858@36 { - compatible = "ovti,ov8858"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 6 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; - rotation = <180>; - - rockchip,camera-module-index = <3>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "HS5885-BNSM1018-V01"; - rockchip,camera-module-lens-name = "default"; - lens-focus = <&dphy2_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov8858_dphy2_out: endpoint { - remote-endpoint = <&dphy2_in_ov8858>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dphy2_ov13850: dphy2-ov13850@10 { - compatible = "ovti,ov13850"; - status = "disabled"; - reg = <0x10>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 6 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; - rotation = <180>; - - rockchip,camera-module-index = <3>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "ZC-OV13850R2A-V1"; - rockchip,camera-module-lens-name = "Largan-50064B31"; - lens-focus = <&dphy2_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov13850_dphy2_out: endpoint { - remote-endpoint = <&dphy2_in_ov13850>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dphy2_imx415: dphy2-imx415@1a { - compatible = "sony,imx415"; - status = "disabled"; - reg = <0x1a>; - clocks = <&ext_cam_37m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 6 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <3>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT2022-PX1"; - rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; - rockchip,imx415-data-lanes=<2>; - // NO_HDR:0 HDR_X2:5 HDR_X3:6 - // rockchip,camera-hdr-mode = <0>; - port { - imx415_dphy2_out: endpoint { - remote-endpoint = <&dphy2_in_imx415>; - data-lanes = <1 2>; - }; - }; - }; - - dphy2_gc08a8: dphy2-gc08a8@31 { - compatible = "galaxycore,gc08a8"; - status = "disabled"; - reg = <0x31>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 6 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <3>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "YT10120"; - rockchip,camera-module-lens-name = "30IRC-4M-F20"; - - port { - gc08a8_dphy2_out: endpoint { - remote-endpoint = <&dphy2_in_gc08a8>; - data-lanes = <1 2>; - }; - }; - }; - - dphy2_gc2053: dphy2-gc2053@37 { - compatible = "galaxycore,gc2053"; - status = "disabled"; - reg = <0x37>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <3>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "SIDA205300461"; - rockchip,camera-module-lens-name = "60IRC-F20"; - - port { - gc2053_dphy2_out: endpoint { - remote-endpoint = <&dphy2_in_gc2053>; - data-lanes = <1 2>; - }; - }; - }; - - dphy2_gc4653: dphy2-gc4653@29 { - compatible = "galaxycore,gc4653"; - status = "disabled"; - reg = <0x29>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 6 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; - - rockchip,camera-module-index = <3>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "YT10120"; - rockchip,camera-module-lens-name = "30IRC-4M-F20"; - - port { - gc4653_dphy2_out: endpoint { - remote-endpoint = <&dphy2_in_gc4653>; - data-lanes = <1 2>; - }; - }; - }; -}; - -//CAM 4 -/* Link path: sensor->csi2_dphy4->mipi4_csi2->rkcif_mipi_lvds4--->rkcif_mipi_lvds4_sditf->rkisp1_vir1 */ -&i2c7 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c7m0_xfer>; - - - dphy4_dw9714: dphy4-dw9714@c { - status = "disabled"; - compatible = "dongwoon,dw9714"; - reg = <0xc>; - rockchip,camera-module-index = <4>; - rockchip,vcm-max-current = <100>; - rockchip,vcm-start-current = <0>; - rockchip,vcm-rated-current = <100>; - rockchip,vcm-step-mode = <0xd>; - rockchip,vcm-dlc-enable = <0>; - rockchip,vcm-mclk = <0>; - rockchip,vcm-t-src = <0>; - rockchip,camera-module-facing = "back"; - }; - - dphy4_ov5647: dphy4-ov5647@36 { - compatible = "ovti,ov5647"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_25m_clk>; - clock-names = "ext_cam_25m_clk"; - pwdn-gpios = <&gpio6 8 GPIO_ACTIVE_LOW>; - lens-focus = <&dphy4_dw9714>; - - port { - ov5647_dphy4_out: endpoint { - remote-endpoint = <&dphy4_in_ov5647>; - data-lanes = <1 2>; - }; - }; - }; - - dphy4_ov5648: dphy4-ov5648@36 { - compatible = "ovti,ov5648"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; - rotation = <180>; - - rockchip,camera-module-index = <4>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "THDS11073"; - rockchip,camera-module-lens-name = "Largan-40122a1"; - lens-focus = <&dphy4_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov5648_dphy4_out: endpoint { - remote-endpoint = <&dphy4_in_ov5648>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dphy4_ov8858: dphy4-ov8858@36 { - compatible = "ovti,ov8858"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; - rotation = <180>; - - rockchip,camera-module-index = <4>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "HS5885-BNSM1018-V01"; - rockchip,camera-module-lens-name = "default"; - lens-focus = <&dphy4_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov8858_dphy4_out: endpoint { - remote-endpoint = <&dphy4_in_ov8858>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dphy4_ov13850: dphy4-ov13850@10 { - compatible = "ovti,ov13850"; - status = "disabled"; - reg = <0x10>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; - rotation = <180>; - - rockchip,camera-module-index = <4>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "ZC-OV13850R2A-V1"; - rockchip,camera-module-lens-name = "Largan-50064B31"; - lens-focus = <&dphy4_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov13850_dphy4_out: endpoint { - remote-endpoint = <&dphy4_in_ov13850>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dphy4_imx415: dphy4-imx415@1a { - compatible = "sony,imx415"; - status = "disabled"; - reg = <0x1a>; - clocks = <&ext_cam_37m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <4>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT2022-PX1"; - rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; - rockchip,imx415-data-lanes=<2>; - // NO_HDR:0 HDR_X2:5 HDR_X3:6 - // rockchip,camera-hdr-mode = <0>; - port { - imx415_dphy4_out: endpoint { - remote-endpoint = <&dphy4_in_imx415>; - data-lanes = <1 2>; - }; - }; - }; - - dphy4_gc08a8: dphy4-gc08a8@31 { - compatible = "galaxycore,gc08a8"; - status = "disabled"; - reg = <0x31>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <4>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "YT10120"; - rockchip,camera-module-lens-name = "30IRC-4M-F20"; - - port { - gc08a8_dphy4_out: endpoint { - remote-endpoint = <&dphy4_in_gc08a8>; - data-lanes = <1 2>; - }; - }; - }; - - dphy4_gc2053: dphy4-gc2053@37 { - compatible = "galaxycore,gc2053"; - status = "disabled"; - reg = <0x37>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 8 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <4>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "SIDA205300461"; - rockchip,camera-module-lens-name = "60IRC-F20"; - - port { - gc2053_dphy4_out: endpoint { - remote-endpoint = <&dphy4_in_gc2053>; - data-lanes = <1 2>; - }; - }; - }; - - dphy4_gc4653: dphy4-gc4653@29 { - compatible = "galaxycore,gc4653"; - status = "disabled"; - reg = <0x29>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; - - rockchip,camera-module-index = <4>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "YT10120"; - rockchip,camera-module-lens-name = "30IRC-4M-F20"; - - port { - gc4653_dphy4_out: endpoint { - remote-endpoint = <&dphy4_in_gc4653>; - data-lanes = <1 2>; - }; - }; - }; -}; - -//CAM 5 -/* Link path: sensor->csi2_dphy5->mipi5_csi2->rkcif_mipi_lvds5--->rkcif_mipi_lvds5_sditf->rkisp0_vir2 */ -&i2c8 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8m2_xfer>; - - dphy5_dw9714: dphy5-dw9714@c { - status = "disabled"; - compatible = "dongwoon,dw9714"; - reg = <0xc>; - rockchip,camera-module-index = <5>; - rockchip,vcm-max-current = <100>; - rockchip,vcm-start-current = <0>; - rockchip,vcm-rated-current = <100>; - rockchip,vcm-step-mode = <0xd>; - rockchip,vcm-dlc-enable = <0>; - rockchip,vcm-mclk = <0>; - rockchip,vcm-t-src = <0>; - rockchip,camera-module-facing = "back"; - }; - - dphy5_ov5647: dphy5-ov5647@36 { - compatible = "ovti,ov5647"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_25m_clk>; - clock-names = "ext_cam_25m_clk"; - pwdn-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; - lens-focus = <&dphy5_dw9714>; - - port { - ov5647_dphy5_out: endpoint { - remote-endpoint = <&dphy5_in_ov5647>; - data-lanes = <1 2>; - }; - }; - }; - - dphy5_ov5648: dphy5-camera@36 { - compatible = "ovti,ov5648"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - rotation = <180>; - - rockchip,camera-module-index = <5>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "THDS11073"; - rockchip,camera-module-lens-name = "Largan-40122a1"; - lens-focus = <&dphy5_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov5648_dphy5_out: endpoint { - remote-endpoint = <&dphy5_in_ov5648>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dphy5_ov8858: dphy5-ov8858@36 { - compatible = "ovti,ov8858"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - rotation = <180>; - - rockchip,camera-module-index = <5>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "HS5885-BNSM1018-V01"; - rockchip,camera-module-lens-name = "default"; - lens-focus = <&dphy5_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov8858_dphy5_out: endpoint { - remote-endpoint = <&dphy5_in_ov8858>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dphy5_ov13850: dphy5-ov13850@10 { - compatible = "ovti,ov13850"; - status = "disabled"; - reg = <0x10>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - rotation = <180>; - - rockchip,camera-module-index = <5>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "ZC-OV13850R2A-V1"; - rockchip,camera-module-lens-name = "Largan-50064B31"; - lens-focus = <&dphy5_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov13850_dphy5_out: endpoint { - remote-endpoint = <&dphy5_in_ov13850>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dphy5_imx415: dphy5-imx415@1a { - compatible = "sony,imx415"; - status = "disabled"; - reg = <0x1a>; - clocks = <&ext_cam_37m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <5>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT2022-PX1"; - rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; - rockchip,imx415-data-lanes=<2>; - // NO_HDR:0 HDR_X2:5 HDR_X3:6 - // rockchip,camera-hdr-mode = <0>; - port { - imx415_dphy5_out: endpoint { - remote-endpoint = <&dphy5_in_imx415>; - data-lanes = <1 2>; - }; - }; - }; - - dphy5_gc08a8: dphy5-gc08a8@31 { - compatible = "galaxycore,gc08a8"; - status = "disabled"; - reg = <0x31>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <5>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "YT10120"; - rockchip,camera-module-lens-name = "30IRC-4M-F20"; - - port { - gc08a8_dphy5_out: endpoint { - remote-endpoint = <&dphy5_in_gc08a8>; - data-lanes = <1 2>; - }; - }; - }; - - dphy5_gc2053: dphy5-gc2053@37 { - compatible = "galaxycore,gc2053"; - status = "disabled"; - reg = <0x37>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <5>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "SIDA205300461"; - rockchip,camera-module-lens-name = "60IRC-F20"; - - port { - gc2053_dphy5_out: endpoint { - remote-endpoint = <&dphy5_in_gc2053>; - data-lanes = <1 2>; - }; - }; - }; - - dphy5_gc4653: dphy5-gc4653@29 { - compatible = "galaxycore,gc4653"; - status = "disabled"; - reg = <0x29>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>; - - rockchip,camera-module-index = <5>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "YT10120"; - rockchip,camera-module-lens-name = "30IRC-4M-F20"; - - port { - gc4653_dphy5_out: endpoint { - remote-endpoint = <&dphy5_in_gc4653>; - data-lanes = <1 2>; - }; - }; - }; -}; - -//CAM 0 -&mipi_dcphy0 { - status = "disabled"; -}; - -&csi2_dcphy0 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dcphy0_in_ov5647: endpoint@0 { - reg = <0>; - remote-endpoint = <&ov5647_dcphy0_out>; - data-lanes = <1 2>; - }; - - dcphy0_in_ov5648: endpoint@1 { - reg = <1>; - remote-endpoint = <&ov5648_dcphy0_out>; - data-lanes = <1 2>; - }; - - dcphy0_in_ov8858: endpoint@2 { - reg = <2>; - remote-endpoint = <&ov8858_dcphy0_out>; - data-lanes = <1 2>; - }; - - dcphy0_in_ov13850: endpoint@3 { - reg = <3>; - remote-endpoint = <&ov13850_dcphy0_out>; - data-lanes = <1 2>; - }; - - dcphy0_in_imx415: endpoint@4 { - reg = <4>; - remote-endpoint = <&imx415_dcphy0_out>; - data-lanes = <1 2 3 4>; - }; - - dcphy0_in_gc08a8: endpoint@5 { - reg = <5>; - remote-endpoint = <&gc08a8_dcphy0_out>; - data-lanes = <1 2>; - }; - - dcphy0_in_gc2053: endpoint@6 { - reg = <6>; - remote-endpoint = <&gc2053_dcphy0_out>; - data-lanes = <1 2>; - }; - - dcphy0_in_gc4653: endpoint@7 { - reg = <7>; - remote-endpoint = <&gc4653_dcphy0_out>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidcphy0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi0_csi2_input>; - }; - }; - }; -}; - -&mipi0_csi2 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidcphy0_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in0>; - }; - }; - }; -}; - -//CAM 1 -&mipi_dcphy1 { - status = "disabled"; -}; - -&csi2_dcphy1 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dcphy1_in_ov5647: endpoint@0 { - reg = <0>; - remote-endpoint = <&ov5647_dcphy1_out>; - data-lanes = <1 2>; - }; - - dcphy1_in_ov5648: endpoint@1 { - reg = <1>; - remote-endpoint = <&ov5648_dcphy1_out>; - data-lanes = <1 2>; - }; - - dcphy1_in_ov8858: endpoint@2 { - reg = <2>; - remote-endpoint = <&ov8858_dcphy1_out>; - data-lanes = <1 2>; - }; - - dcphy1_in_ov13850: endpoint@3 { - reg = <3>; - remote-endpoint = <&ov13850_dcphy1_out>; - data-lanes = <1 2>; - }; - - dcphy1_in_imx415: endpoint@4 { - reg = <4>; - remote-endpoint = <&imx415_dcphy1_out>; - data-lanes = <1 2 3 4>; - }; - - dcphy1_in_gc08a8: endpoint@5 { - reg = <5>; - remote-endpoint = <&gc08a8_dcphy1_out>; - data-lanes = <1 2>; - }; - - dcphy1_in_gc2053: endpoint@6 { - reg = <6>; - remote-endpoint = <&gc2053_dcphy1_out>; - data-lanes = <1 2>; - }; - - dcphy1_in_gc4653: endpoint@7 { - reg = <7>; - remote-endpoint = <&gc4653_dcphy1_out>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidcphy1_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi1_csi2_input>; - }; - }; - }; -}; - -&mipi1_csi2 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi1_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidcphy1_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi1_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in1>; - }; - }; - }; -}; - -&csi2_dphy0_hw { - status = "okay"; -}; - -&csi2_dphy1 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dphy1_in_ov5647: endpoint@0 { - reg = <0>; - remote-endpoint = <&ov5647_dphy1_out>; - data-lanes = <1 2>; - }; - - dphy1_in_ov5648: endpoint@1 { - reg = <1>; - remote-endpoint = <&ov5648_dphy1_out>; - data-lanes = <1 2>; - }; - - dphy1_in_ov8858: endpoint@2 { - reg = <2>; - remote-endpoint = <&ov8858_dphy1_out>; - data-lanes = <1 2>; - }; - - dphy1_in_ov13850: endpoint@3 { - reg = <3>; - remote-endpoint = <&ov13850_dphy1_out>; - data-lanes = <1 2>; - }; - - dphy1_in_imx415: endpoint@4 { - reg = <4>; - remote-endpoint = <&imx415_dphy1_out>; - data-lanes = <1 2>; - }; - - dphy1_in_gc08a8: endpoint@5 { - reg = <5>; - remote-endpoint = <&gc08a8_dphy1_out>; - data-lanes = <1 2>; - }; - - dphy1_in_gc2053: endpoint@6 { - reg = <6>; - remote-endpoint = <&gc2053_dphy1_out>; - data-lanes = <1 2>; - }; - - dphy1_in_gc4653: endpoint@7 { - reg = <7>; - remote-endpoint = <&gc4653_dphy1_out>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy1_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi2_csi2_input>; - }; - }; - }; -}; - -&mipi2_csi2 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy1_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in2>; - }; - }; - }; -}; - -&csi2_dphy2 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dphy2_in_ov5647: endpoint@0 { - reg = <0>; - remote-endpoint = <&ov5647_dphy2_out>; - data-lanes = <1 2>; - }; - - dphy2_in_ov5648: endpoint@1 { - reg = <1>; - remote-endpoint = <&ov5648_dphy2_out>; - data-lanes = <1 2>; - }; - - dphy2_in_ov8858: endpoint@2 { - reg = <2>; - remote-endpoint = <&ov8858_dphy2_out>; - data-lanes = <1 2>; - }; - - dphy2_in_ov13850: endpoint@3 { - reg = <3>; - remote-endpoint = <&ov13850_dphy2_out>; - data-lanes = <1 2>; - }; - - dphy2_in_imx415: endpoint@4 { - reg = <4>; - remote-endpoint = <&imx415_dphy2_out>; - data-lanes = <1 2>; - }; - - dphy2_in_gc08a8: endpoint@5 { - reg = <5>; - remote-endpoint = <&gc08a8_dphy2_out>; - data-lanes = <1 2>; - }; - - dphy2_in_gc2053: endpoint@6 { - reg = <6>; - remote-endpoint = <&gc2053_dphy2_out>; - data-lanes = <1 2>; - }; - - dphy2_in_gc4653: endpoint@7 { - reg = <7>; - remote-endpoint = <&gc4653_dphy2_out>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy2_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi3_csi2_input>; - }; - }; - }; -}; - -&mipi3_csi2 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi3_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy2_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi3_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi0_in3>; - }; - }; - }; -}; - -&csi2_dphy1_hw { - status = "okay"; -}; - -&csi2_dphy4 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dphy4_in_ov5647: endpoint@0 { - reg = <0>; - remote-endpoint = <&ov5647_dphy4_out>; - data-lanes = <1 2>; - }; - - dphy4_in_ov5648: endpoint@1 { - reg = <1>; - remote-endpoint = <&ov5648_dphy4_out>; - data-lanes = <1 2>; - }; - - dphy4_in_ov8858: endpoint@2 { - reg = <2>; - remote-endpoint = <&ov8858_dphy4_out>; - data-lanes = <1 2>; - }; - - dphy4_in_ov13850: endpoint@3 { - reg = <3>; - remote-endpoint = <&ov13850_dphy4_out>; - data-lanes = <1 2>; - }; - - dphy4_in_imx415: endpoint@4 { - reg = <4>; - remote-endpoint = <&imx415_dphy4_out>; - data-lanes = <1 2>; - }; - - dphy4_in_gc08a8: endpoint@5 { - reg = <5>; - remote-endpoint = <&gc08a8_dphy4_out>; - data-lanes = <1 2>; - }; - - dphy4_in_gc2053: endpoint@6 { - reg = <6>; - remote-endpoint = <&gc2053_dphy4_out>; - data-lanes = <1 2>; - }; - - dphy4_in_gc4653: endpoint@7 { - reg = <7>; - remote-endpoint = <&gc4653_dphy4_out>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy4_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi4_csi2_input>; - }; - }; - }; -}; - -&mipi4_csi2 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi4_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy4_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi4_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in4>; - }; - }; - }; -}; - -&csi2_dphy5 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dphy5_in_ov5647: endpoint@0 { - reg = <0>; - remote-endpoint = <&ov5647_dphy5_out>; - data-lanes = <1 2>; - }; - - dphy5_in_ov5648: endpoint@1 { - reg = <1>; - remote-endpoint = <&ov5648_dphy5_out>; - data-lanes = <1 2>; - }; - - dphy5_in_ov8858: endpoint@2 { - reg = <2>; - remote-endpoint = <&ov8858_dphy5_out>; - data-lanes = <1 2>; - }; - - dphy5_in_ov13850: endpoint@3 { - reg = <3>; - remote-endpoint = <&ov13850_dphy5_out>; - data-lanes = <1 2>; - }; - - dphy5_in_imx415: endpoint@4 { - reg = <4>; - remote-endpoint = <&imx415_dphy5_out>; - data-lanes = <1 2>; - }; - - dphy5_in_gc08a8: endpoint@5 { - reg = <5>; - remote-endpoint = <&gc08a8_dphy5_out>; - data-lanes = <1 2>; - }; - - dphy5_in_gc2053: endpoint@6 { - reg = <6>; - remote-endpoint = <&gc2053_dphy5_out>; - data-lanes = <1 2>; - }; - - dphy5_in_gc4653: endpoint@7 { - reg = <7>; - remote-endpoint = <&gc4653_dphy5_out>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy5_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi5_csi2_input>; - }; - }; - }; -}; - -&mipi5_csi2 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi5_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy5_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi5_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in5>; - }; - }; - }; -}; - -&rkcif { - status = "disabled"; -}; - -&rkcif_mmu { - status = "disabled"; -}; - -&rkcif_mipi_lvds { - status = "disabled"; - - port { - cif_mipi_in0: endpoint { - remote-endpoint = <&mipi0_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds_sditf { - status = "disabled"; - - port { - mipi_lvds_sditf: endpoint { - remote-endpoint = <&isp0_vir0>; - }; - }; -}; - -&rkcif_mipi_lvds1 { - status = "disabled"; - - port { - cif_mipi_in1: endpoint { - remote-endpoint = <&mipi1_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds1_sditf { - status = "disabled"; - - port { - mipi_lvds1_sditf: endpoint { - remote-endpoint = <&isp1_vir0>; - }; - }; -}; - -&rkcif_mipi_lvds2 { - status = "disabled"; - - port { - cif_mipi_in2: endpoint { - remote-endpoint = <&mipi2_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds2_sditf { - status = "disabled"; - - port { - mipi_lvds2_sditf: endpoint { - remote-endpoint = <&isp0_vir2>; - }; - }; -}; - -&rkcif_mipi_lvds3 { - status = "disabled"; - - port { - cif_mipi0_in3: endpoint { - remote-endpoint = <&mipi3_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds3_sditf { - status = "disabled"; - - port { - mipi_lvds3_sditf: endpoint { - remote-endpoint = <&isp0_vir1>; - }; - }; -}; - -&rkcif_mipi_lvds4 { - status = "disabled"; - - port { - cif_mipi_in4: endpoint { - remote-endpoint = <&mipi4_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds4_sditf { - status = "disabled"; - - port { - mipi_lvds4_sditf: endpoint { - remote-endpoint = <&isp1_vir1>; - }; - }; -}; - -&rkcif_mipi_lvds5 { - status = "disabled"; - - port { - cif_mipi_in5: endpoint { - remote-endpoint = <&mipi5_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds5_sditf { - status = "disabled"; - - port { - mipi_lvds5_sditf: endpoint { - remote-endpoint = <&isp1_vir2>; - }; - }; -}; - -&rkisp0 { - status = "disabled"; -}; - -&isp0_mmu { - status = "disabled"; -}; - -&rkisp0_vir0 { - status = "disabled"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds_sditf>; - }; - }; -}; - -&rkisp0_vir1 { - status = "disabled"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir1: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds3_sditf>; - }; - }; -}; - -&rkisp0_vir2 { - status = "disabled"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir2: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds2_sditf>; - }; - }; -}; - -&rkisp1 { - status = "disabled"; -}; - -&isp1_mmu { - status = "disabled"; -}; - -&rkisp1_vir0 { - status = "disabled"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp1_vir0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds1_sditf>; - }; - }; -}; - -&rkisp1_vir1 { - status = "disabled"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp1_vir1: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds4_sditf>; - }; - }; -}; - -&rkisp1_vir2 { - status = "disabled"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp1_vir2: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds5_sditf>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-dp0-vp1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-dp0-vp1.dtsi deleted file mode 100644 index d30f930e0..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-dp0-vp1.dtsi +++ /dev/null @@ -1,37 +0,0 @@ - -/ { - dp0_sound: dp0-sound { - status = "okay"; - compatible = "rockchip,hdmi"; - rockchip,card-name = "rockchip-dp0"; - rockchip,mclk-fs = <512>; - rockchip,cpu = <&spdif_tx2>; - rockchip,codec = <&dp0 1>; - rockchip,jack-det; - }; -}; - -&spdif_tx2 { - status = "okay"; -}; - -&dp0 { - status = "okay"; -}; - -&route_dp0 { - status = "okay"; - connect = <&vp1_out_dp0>; -}; - -&dp0_in_vp0 { - status = "disabled"; -}; - -&dp0_in_vp1 { - status = "okay"; -}; - -&dp0_in_vp2 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-dsi0-vp2-1080x1920-5.5inch-ebf410125.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-dsi0-vp2-1080x1920-5.5inch-ebf410125.dtsi deleted file mode 100644 index ecb9035cc..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-dsi0-vp2-1080x1920-5.5inch-ebf410125.dtsi +++ /dev/null @@ -1,126 +0,0 @@ -&dsi0 { - status = "okay"; - - dsi0_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight_dsi0>; - power-supply = <&mipi_dsi0_power>; - reset-gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; - - enable-delay-ms = <35>; - prepare-delay-ms = <6>; - reset-delay-ms = <10>; - init-delay-ms = <50>; - unprepare-delay-ms = <0>; - disable-delay-ms = <20>; - - size,width = <74>; - size,height = <133>; - - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - - panel-init-sequence = [ - 39 00 04 B9 FF 83 99 - 15 00 02 D2 77 - 39 00 10 B1 02 04 74 94 01 32 33 11 11 AB 4D 56 73 02 02 - 39 00 10 B2 00 80 80 AE 05 07 5A 11 00 00 10 1E 70 03 D4 - 15 00 02 36 02 - 39 00 2D B4 00 FF 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 21 03 01 00 0F B8 8B 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 01 00 0F B8 01 - 39 05 22 D3 00 00 00 00 00 00 06 00 00 10 04 00 04 00 00 00 00 00 00 00 00 00 00 01 00 05 05 07 00 00 00 05 40 - 39 05 21 D5 18 18 19 19 18 18 21 20 01 00 07 06 05 04 03 02 18 18 18 18 18 18 2F 2F 30 30 31 31 18 18 18 18 - 39 05 21 D6 18 18 19 19 40 40 20 21 06 07 00 01 02 03 04 05 40 40 40 40 40 40 2F 2F 30 30 31 31 40 40 40 40 - 39 00 11 D8 A2 AA 02 A0 A2 A8 02 A0 B0 00 00 00 B0 00 00 00 - 15 00 02 BD 01 - 39 00 11 D8 B0 00 00 00 B0 00 00 00 E2 AA 03 F0 E2 AA 03 F0 - 15 00 02 BD 02 - 39 00 09 D8 E2 AA 03 F0 E2 AA 03 F0 - 15 00 02 BD 00 - 39 00 03 B6 8D 8D - 39 05 37 E0 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77 - 05 C8 01 11 - 05 C8 01 29 - ]; - - panel-exit-sequence = [ - 05 78 01 28 - 05 00 01 10 - ]; - - disp0_timings0: display-timings { - native-mode = <&dsi0_timing0>; - dsi0_timing0: timing0 { - clock-frequency = <131376000>; - hactive = <1080>; - vactive = <1920>; - hsync-len = <10>; - hback-porch = <20>; - hfront-porch = <10>; - vsync-len = <5>; - vback-porch = <20>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in_dsi0: endpoint { - remote-endpoint = <&dsi0_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi0_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi0>; - }; - }; - }; -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2m4_xfer>; - - gt911_dsi0: gt911@5d { - status = "okay"; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio3>; - interrupts = ; - reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; - irq-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; - touchscreen-inverted-x = <1>; - touchscreen-inverted-y = <1>; - }; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp2_out_dsi0>; -}; - -&dsi0_in_vp2 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-dsi1-vp3-1080x1920-5.5inch-ebf410125.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-dsi1-vp3-1080x1920-5.5inch-ebf410125.dtsi deleted file mode 100644 index 0c4445319..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-dsi1-vp3-1080x1920-5.5inch-ebf410125.dtsi +++ /dev/null @@ -1,126 +0,0 @@ -&dsi1 { - status = "okay"; - - dsi1_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight_dsi1>; - power-supply = <&mipi_dsi1_power>; - reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; - - enable-delay-ms = <35>; - prepare-delay-ms = <6>; - reset-delay-ms = <10>; - init-delay-ms = <50>; - unprepare-delay-ms = <0>; - disable-delay-ms = <20>; - - size,width = <74>; - size,height = <133>; - - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - - panel-init-sequence = [ - 39 00 04 B9 FF 83 99 - 15 00 02 D2 77 - 39 00 10 B1 02 04 74 94 01 32 33 11 11 AB 4D 56 73 02 02 - 39 00 10 B2 00 80 80 AE 05 07 5A 11 00 00 10 1E 70 03 D4 - 15 00 02 36 02 - 39 00 2D B4 00 FF 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 21 03 01 00 0F B8 8B 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 01 00 0F B8 01 - 39 05 22 D3 00 00 00 00 00 00 06 00 00 10 04 00 04 00 00 00 00 00 00 00 00 00 00 01 00 05 05 07 00 00 00 05 40 - 39 05 21 D5 18 18 19 19 18 18 21 20 01 00 07 06 05 04 03 02 18 18 18 18 18 18 2F 2F 30 30 31 31 18 18 18 18 - 39 05 21 D6 18 18 19 19 40 40 20 21 06 07 00 01 02 03 04 05 40 40 40 40 40 40 2F 2F 30 30 31 31 40 40 40 40 - 39 00 11 D8 A2 AA 02 A0 A2 A8 02 A0 B0 00 00 00 B0 00 00 00 - 15 00 02 BD 01 - 39 00 11 D8 B0 00 00 00 B0 00 00 00 E2 AA 03 F0 E2 AA 03 F0 - 15 00 02 BD 02 - 39 00 09 D8 E2 AA 03 F0 E2 AA 03 F0 - 15 00 02 BD 00 - 39 00 03 B6 8D 8D - 39 05 37 E0 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77 - 05 C8 01 11 - 05 C8 01 29 - ]; - - panel-exit-sequence = [ - 05 78 01 28 - 05 00 01 10 - ]; - - disp1_timings0: display-timings { - native-mode = <&dsi1_timing0>; - dsi1_timing0: timing0 { - clock-frequency = <131376000>; - hactive = <1080>; - vactive = <1920>; - hsync-len = <10>; - hback-porch = <20>; - hfront-porch = <10>; - vsync-len = <5>; - vback-porch = <20>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in_dsi1: endpoint { - remote-endpoint = <&dsi1_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi1_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi1>; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5m3_xfer>; - - gt911_dsi1: gt911@5d { - status = "okay"; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio3>; - interrupts = ; - reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - irq-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; - touchscreen-inverted-x = <1>; - touchscreen-inverted-y = <1>; - }; -}; - -&mipi_dcphy1 { - status = "okay"; -}; - -&route_dsi1 { - status = "okay"; - connect = <&vp3_out_dsi1>; -}; - -&dsi1_in_vp3 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-hdmi0-vp0.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-hdmi0-vp0.dtsi deleted file mode 100644 index 96dc0db05..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-hdmi0-vp0.dtsi +++ /dev/null @@ -1,43 +0,0 @@ - -/ { - hdmi0_sound: hdmi0-sound { - status = "okay"; - compatible = "rockchip,hdmi"; - rockchip,mclk-fs = <128>; - rockchip,card-name = "rockchip-hdmi0"; - rockchip,cpu = <&i2s5_8ch>; - rockchip,codec = <&hdmi0>; - rockchip,jack-det; - }; -}; - -&i2s5_8ch { - status = "okay"; -}; - -&route_hdmi0{ - status = "okay"; - connect = <&vp0_out_hdmi0>; -}; - -&hdmi0 { - enable-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - cec-enable = "true"; - status = "okay"; -}; - -&hdmi0_in_vp0 { - status = "okay"; -}; - -&hdmi0_in_vp1 { - status = "disabled"; -}; - -&hdmi0_in_vp2 { - status = "disabled"; -}; - -&hdptxphy_hdmi0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-hdmi1-vp0.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-hdmi1-vp0.dtsi deleted file mode 100644 index 429b660ca..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-hdmi1-vp0.dtsi +++ /dev/null @@ -1,45 +0,0 @@ - -/ { - hdmi1_sound: hdmi1-sound { - status = "okay"; - compatible = "rockchip,hdmi"; - rockchip,mclk-fs = <128>; - rockchip,card-name = "rockchip-hdmi1"; - rockchip,cpu = <&i2s6_8ch>; - rockchip,codec = <&hdmi1>; - rockchip,jack-det; - }; -}; - -&i2s6_8ch { - status = "okay"; -}; - -&route_hdmi1{ - status = "okay"; - connect = <&vp0_out_hdmi1>; -}; - -&hdmi1 { - enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; - cec-enable = "true"; - pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd &hdmim0_tx1_scl &hdmim0_tx1_sda>; - pinctrl-names = "default"; - status = "okay"; -}; - -&hdmi1_in_vp0 { - status = "okay"; -}; - -&hdmi1_in_vp1 { - status = "disabled"; -}; - -&hdmi1_in_vp2 { - status = "disabled"; -}; - -&hdptxphy_hdmi1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-hdmi1-vp2.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-hdmi1-vp2.dtsi deleted file mode 100644 index 743e58e77..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-hdmi1-vp2.dtsi +++ /dev/null @@ -1,45 +0,0 @@ - -/ { - hdmi1_sound: hdmi1-sound { - status = "okay"; - compatible = "rockchip,hdmi"; - rockchip,mclk-fs = <128>; - rockchip,card-name = "rockchip-hdmi1"; - rockchip,cpu = <&i2s6_8ch>; - rockchip,codec = <&hdmi1>; - rockchip,jack-det; - }; -}; - -&i2s6_8ch { - status = "okay"; -}; - -&route_hdmi1{ - status = "okay"; - connect = <&vp2_out_hdmi1>; -}; - -&hdmi1 { - enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; - cec-enable = "true"; - pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd &hdmim0_tx1_scl &hdmim0_tx1_sda>; - pinctrl-names = "default"; - status = "okay"; -}; - -&hdmi1_in_vp0 { - status = "disabled"; -}; - -&hdmi1_in_vp1 { - status = "disabled"; -}; - -&hdmi1_in_vp2 { - status = "okay"; -}; - -&hdptxphy_hdmi1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-hdmirx.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-hdmirx.dtsi deleted file mode 100644 index 3277d28e8..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-hdmirx.dtsi +++ /dev/null @@ -1,29 +0,0 @@ - -/ { - hdmiin_sound: hdmiin-sound { - status = "okay"; - compatible = "rockchip,hdmi"; - rockchip,mclk-fs = <128>; - rockchip,format = "i2s"; - rockchip,bitclock-master = <&hdmirx_ctrler>; - rockchip,frame-master = <&hdmirx_ctrler>; - rockchip,card-name = "rockchip-hdmiin"; - rockchip,cpu = <&i2s7_8ch>; - rockchip,codec = <&hdmirx_ctrler 0>; - rockchip,jack-det; - }; -}; - -&i2s7_8ch { - status = "okay"; -}; - -&hdmirx_ctrler { - status = "okay"; - #sound-dai-cells = <1>; - /* Effective level used to trigger HPD: 0-low, 1-high */ - hpd-trigger-level = <1>; - hdmirx-det-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_det>; - pinctrl-names = "default"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io.dts b/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io.dts deleted file mode 100644 index ef385260c..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io.dts +++ /dev/null @@ -1,1736 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * Copyright (c) 2023 EmbedFire - */ - -/dts-v1/; - -#include -#include -#include -#include -//#include -#include -#include -#include -#include -#include -#include "rk3588.dtsi" -#include "rk3588-linux.dtsi" - -//vp0 -// #include "rk3588-lubancat-5io-hdmi0-vp0.dtsi" -// #include "rk3588-lubancat-5io-hdmi1-vp0.dtsi" - -//vp1 -// #include "rk3588-lubancat-5-dp0-vp1.dtsi" - -//vp2 二选一 -// #include "rk3588-lubancat-5io-hdmi1-vp2.dtsi" -// #include "rk3588-lubancat-5io-dsi0-vp2-1080x1920-5.5inch-ebf410125.dtsi" - -//vp3 -// #include "rk3588-lubancat-5io-dsi1-vp3-1080x1920-5.5inch-ebf410125.dtsi" - -/* HDMI-RX */ -// #include "rk3588-lubancat-5io-hdmirx.dtsi" - -/* Camera */ -#include "rk3588-lubancat-5io-csi.dtsi" -// #include "rk3588-lubancat-5io-cam0.dtsi" -// #include "rk3588-lubancat-5io-cam1.dtsi" -// #include "rk3588-lubancat-5io-cam2.dtsi" -// #include "rk3588-lubancat-5io-cam3.dtsi" -// #include "rk3588-lubancat-5io-cam4.dtsi" -// #include "rk3588-lubancat-5io-cam5.dtsi" - -/ { - model = "Embedfire LubanCat-5IO"; - compatible = "embedfire,rk3588-lubancat-5io", "rockchip,rk3588"; - - /* If hdmirx node is disabled, delete the reserved-memory node here. */ - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ - cma { - compatible = "shared-dma-pool"; - reusable; - reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; - linux,cma-default; - }; - }; - - leds: leds { - status = "okay"; - compatible = "gpio-leds"; - - sys_led: sys-led { - label = "sys_led"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sys_led_pin>; - }; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-name = "vcc12v_dcin"; - }; - - vcc4v0_sys: vcc4v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc4v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <4000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc_5v0_s0: vcc-5v0-s0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v0_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb_s0: vcc5v0-usb-s0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - combophy_avdd0v85: combophy-avdd0v85 { - compatible = "regulator-fixed"; - regulator-name = "combophy_avdd0v85"; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&avdd_0v85_s0>; - }; - - combophy_avdd1v8: combophy-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "combophy_avdd1v8"; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc4v0_sys>; - }; - - vcc_3v3_s0: vcc-3v3-s0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc_3v3_sd_s3: vcc-3v3-sd-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_sd_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_s3>; - }; - - vbus5v0_typec: vbus5v0-typec { - compatible = "regulator-fixed"; - regulator-name = "vbus5v0_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb_s0>; - pinctrl-names = "default"; - pinctrl-0 = <&typec_vbus_en>; - }; - - vcc5v0_usb30_otg: vcc5v0-usb30-otg { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb30_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - enable-active-high; - regulator-boot-on; - gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb_s0>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb30_otg_en>; - }; - - vcc5v0_usb20_hub: vcc5v0-usb20-hub { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb20_hub"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - enable-active-high; - regulator-boot-on; - gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb_s0>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb20_hub_en>; - }; - - vcc5v0_usb20_host: vcc5v0-usb20-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb20_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - enable-active-high; - regulator-boot-on; - gpio = <&gpio2 RK_PC3 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb_s0>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb20_host_en>; - }; - - vcc3v3_m2_pcie: vcc3v3-m2-pcie { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_m2_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - enable-active-high; - regulator-boot-on; - gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc12v_dcin>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc3v3_m2_pcie_en>; - }; - - vcc3v3_pciex4: vcc3v3-pciex4 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pciex4"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - enable-active-high; - regulator-boot-on; - gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc12v_dcin>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc3v3_pcie_en>; - }; - - vcc3v3_mini_pcie: vcc3v3-mini-pcie { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_mini_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - enable-active-high; - regulator-boot-on; - gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc12v_dcin>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc3v3_mini_pcie_en>; - }; - - vcc3v3_ekey_pcie: vcc3v3-ekey-pcie { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_ekey_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - enable-active-high; - regulator-boot-on; - gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc12v_dcin>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc3v3_ekey_pcie_en>; - }; - - sata_power: sata-power { - compatible = "regulator-fixed"; - regulator-name = "sata_power"; - regulator-always-on; - enable-active-high; - regulator-boot-on; - gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc12v_dcin>; - pinctrl-names = "default"; - pinctrl-0 = <&sata_power_en>; - }; - - mipi_dsi0_power: mipi-dsi0-power-regulator { - compatible = "regulator-fixed"; - regulator-name = "mipi_dsi0_power"; - gpio = <&gpio1 RK_PC0 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - vin-supply = <&vcc_5v0_s0>; - pinctrl-names = "default"; - pinctrl-0 = <&mipi_dsi0_power_en>; - }; - - mipi_dsi1_power: mipi-dsi1-power-regulator { - compatible = "regulator-fixed"; - regulator-name = "mipi_dsi1_power"; - gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - vin-supply = <&vcc_5v0_s0>; - pinctrl-names = "default"; - pinctrl-0 = <&mipi_dsi1_power_en>; - }; - - es8388_sound: es8388-sound { - status = "okay"; - compatible = "rockchip,multicodecs-card"; - rockchip,card-name = "rockchip-es8388"; - hp-det-gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; - hp-con-gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; - spk-con-gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; - io-channels = <&saradc 4>; - io-channel-names = "adc-detect"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - rockchip,format = "i2s"; - rockchip,mclk-fs = <256>; - rockchip,cpu = <&i2s0_8ch>; - rockchip,codec = <&es8388>; - rockchip,audio-routing = - "Headphone", "LOUT1", - "Headphone", "ROUT1", - "Speaker", "LOUT2", - "Speaker", "ROUT2", - "Headphone", "Headphone Power", - "Headphone", "Headphone Power", - "Speaker", "Speaker Power", - "Speaker", "Speaker Power", - "LINPUT1", "Main Mic", - "LINPUT2", "Main Mic", - "RINPUT1", "Headset Mic", - "RINPUT2", "Headset Mic"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - play-pause-key { - label = "playpause"; - linux,code = ; - press-threshold-microvolt = <2000>; - }; - - previous-song-key { - label = "previoussong"; - linux,code = ; - press-threshold-microvolt = <145000>; - }; - - next-song-key { - label = "nextsong"; - linux,code = ; - press-threshold-microvolt = <290000>; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - pwms = <&pwm11 0 5000 0>; - cooling-levels = <0 100 150 200 255>; - rockchip,temp-trips = < - 35000 1 - 40000 2 - 45000 3 - 50000 4 - >; - }; - - backlight_dsi0: backlight-dsi0 { - status = "okay"; - compatible = "pwm-backlight"; - pwms = <&pwm0 0 25000 0>; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - backlight_dsi1: backlight-dsi1 { - status = "okay"; - compatible = "pwm-backlight"; - pwms = <&pwm1 0 25000 0>; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - test-power { - status = "okay"; - }; -}; - -&pwm0 { - pinctrl-0 = <&pwm0m2_pins>; - status = "okay"; -}; - -&pwm1 { - pinctrl-0 = <&pwm1m2_pins>; - status = "okay"; -}; - -&pwm11 { - pinctrl-0 = <&pwm11m2_pins>; - status = "okay"; -}; - -&av1d { - status = "okay"; -}; - -&av1d_mmu { - status = "okay"; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - mem-supply = <&vdd_gpu_mem_s0>; - upthreshold = <60>; - downdifferential = <30>; - status = "okay"; -}; - -&dfi { - status = "okay"; -}; - -&dmc { - status = "okay"; - center-supply = <&vdd_ddr_s0>; - mem-supply = <&vdd_log_s0>; -}; - -&rockchip_suspend { - status = "okay"; - rockchip,sleep-debug-en = <1>; - rockchip,sleep-mode-config = < - (0 - | RKPM_SLP_ARMOFF_DDRPD - | RKPM_SLP_PMU_PMUALIVE_32K - | RKPM_SLP_PMU_DIS_OSC - | RKPM_SLP_32K_EXT - ) - >; - rockchip,wakeup-config = < - (0 - | RKPM_GPIO_WKUP_EN - | RKPM_CPU0_WKUP_EN - ) - >; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; - - vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc4v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big0_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { - compatible = "rockchip,rk8603"; - reg = <0x43>; - vin-supply = <&vcc4v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big1_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - gpio6: gpio-expander@21 { - compatible = "nxp,pca9535"; - status = "okay"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1m2_xfer>; - status = "okay"; - - vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc4v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_npu_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* Typec Controller Fusb302 */ - usbc0: fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&fusb302_int>; - vbus-supply = <&vbus5v0_typec>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - ; - source-pdos = - ; - - altmodes { - #address-cells = <1>; - #size-cells = <0>; - - altmode@0 { - reg = <0>; - svid = <0xff01>; - vdo = <0xffffffff>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; - }; - }; - - port@1 { - reg = <1>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; - }; - }; - }; - }; - }; -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2m4_xfer>; -}; - -&i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c5m3_xfer>; - status = "okay"; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - num-cs = <1>; - - rk806single@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - - interrupt-parent = <&gpio0>; - interrupts = ; - - pinctrl-names = "default", "pmic-power-off"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; - pinctrl-1 = <&rk806_dvs1_pwrdn>; - - /* 2800mv-3500mv */ - low_voltage_threshold = <3000>; - /* 2700mv-3400mv */ - shutdown_voltage_threshold = <2700>; - /* 140 160 */ - shutdown_temperture_threshold = <160>; - hotdie_temperture_threshold = <115>; - - /* 0: restart PMU; - * 1: reset all the power off reset registers, - * forcing the state to switch to ACTIVE mode; - * 2: Reset all the power off reset registers, - * forcing the state to switch to ACTIVE mode, - * and simultaneously pull down the RESETB PIN for 5mS before releasing - */ - pmic-reset-func = <1>; - - vcc1-supply = <&vcc4v0_sys>; - vcc2-supply = <&vcc4v0_sys>; - vcc3-supply = <&vcc4v0_sys>; - vcc4-supply = <&vcc4v0_sys>; - vcc5-supply = <&vcc4v0_sys>; - vcc6-supply = <&vcc4v0_sys>; - vcc7-supply = <&vcc4v0_sys>; - vcc8-supply = <&vcc4v0_sys>; - vcc9-supply = <&vcc4v0_sys>; - vcc10-supply = <&vcc4v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc4v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc4v0_sys>; - - pwrkey { - status = "okay"; - }; - - pinctrl_rk806: pinctrl_rk806 { - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: rk806_dvs1_null { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs1_slp: rk806_dvs1_slp { - pins = "gpio_pwrctrl1"; - function = "pin_fun1"; - }; - - rk806_dvs1_pwrdn: rk806_dvs1_pwrdn { - pins = "gpio_pwrctrl1"; - function = "pin_fun2"; - }; - - rk806_dvs1_rst: rk806_dvs1_rst { - pins = "gpio_pwrctrl1"; - function = "pin_fun3"; - }; - - rk806_dvs2_null: rk806_dvs2_null { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_slp: rk806_dvs2_slp { - pins = "gpio_pwrctrl2"; - function = "pin_fun1"; - }; - - rk806_dvs2_pwrdn: rk806_dvs2_pwrdn { - pins = "gpio_pwrctrl2"; - function = "pin_fun2"; - }; - - rk806_dvs2_rst: rk806_dvs2_rst { - pins = "gpio_pwrctrl2"; - function = "pin_fun3"; - }; - - rk806_dvs2_dvs: rk806_dvs2_dvs { - pins = "gpio_pwrctrl2"; - function = "pin_fun4"; - }; - - rk806_dvs2_gpio: rk806_dvs2_gpio { - pins = "gpio_pwrctrl2"; - function = "pin_fun5"; - }; - - rk806_dvs3_null: rk806_dvs3_null { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - rk806_dvs3_slp: rk806_dvs3_slp { - pins = "gpio_pwrctrl3"; - function = "pin_fun1"; - }; - - rk806_dvs3_pwrdn: rk806_dvs3_pwrdn { - pins = "gpio_pwrctrl3"; - function = "pin_fun2"; - }; - - rk806_dvs3_rst: rk806_dvs3_rst { - pins = "gpio_pwrctrl3"; - function = "pin_fun3"; - }; - - rk806_dvs3_dvs: rk806_dvs3_dvs { - pins = "gpio_pwrctrl3"; - function = "pin_fun4"; - }; - - rk806_dvs3_gpio: rk806_dvs3_gpio { - pins = "gpio_pwrctrl3"; - function = "pin_fun5"; - }; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: DCDC_REG1 { - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-enable-ramp-delay = <400>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-init-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: DCDC_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: DCDC_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: DCDC_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-name = "vdd_2v0_pldo_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: DCDC_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_3v3_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: DCDC_REG9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: DCDC_REG10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avcc_1v8_s0: PLDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "avcc_1v8_s0"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_1v8_s0: PLDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd_1v2_s0: PLDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "avdd_1v2_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avcc_3v3_s0: PLDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc_3v3_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: PLDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: PLDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: NLDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - avdd_ddr_pll_s0: NLDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "avdd_ddr_pll_s0"; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: NLDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <837500>; - regulator-max-microvolt = <837500>; - regulator-name = "avdd_0v75_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd_0v85_s0: NLDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "avdd_0v85_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: NLDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2c7 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c7m0_xfer>; - status = "okay"; - - es8388: es8388@11 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "everest,es8388", "everest,es8323"; - reg = <0x11>; - clocks = <&mclkout_i2s0>; - clock-names = "mclk"; - assigned-clocks = <&mclkout_i2s0>; - assigned-clock-rates = <12288000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk>; - }; -}; - -&i2s0_8ch { - status = "okay"; - rockchip,clk-trcm = <1>; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; -}; - -&saradc { - status = "okay"; - vref-supply = <&avcc_1v8_s0>; -}; - -&tsadc { - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - max-frequency = <200000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - full-pwr-cycle-in-suspend; - status = "okay"; -}; - -&sdmmc { - max-frequency = <200000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_sd_s3>; - vqmmc-supply = <&vccio_sd_s0>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; - status = "okay"; -}; - -&iep { - status = "okay"; -}; - -&iep_mmu { - status = "okay"; -}; - -&jpegd { - status = "okay"; -}; - -&jpegd_mmu { - status = "okay"; -}; - -&jpege_ccu { - status = "okay"; -}; - -&jpege0 { - status = "okay"; -}; - -&jpege0_mmu { - status = "okay"; -}; - -&jpege1 { - status = "okay"; -}; - -&jpege1_mmu { - status = "okay"; -}; - -&jpege2 { - status = "okay"; -}; - -&jpege2_mmu { - status = "okay"; -}; - -&jpege3 { - status = "okay"; -}; - -&jpege3_mmu { - status = "okay"; -}; - -&mpp_srv { - status = "okay"; -}; - -&pwm4 { - pinctrl-0 = <&pwm4m0_pins>; - status = "okay"; -}; - -&pwm2 { - pinctrl-0 = <&pwm2m0_pins>; - status = "okay"; -}; - -&pwm6 { - pinctrl-0 = <&pwm6m0_pins>; - status = "okay"; -}; - -&pwm7 { - compatible = "rockchip,remotectl-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm7m0_pins>; - remote_pwm_id = <3>; - handle_cpu_id = <1>; - remote_support_psci = <0>; - status = "okay"; - - ir_key_lubancat{ - rockchip,usercode = <0xff00>; - rockchip,key_table = - <0xba KEY_POWER>, //电源按键 - <0xb8 KEY_MENU>, //菜单按键 - <0xbc KEY_BACK>, //返回按键 - <0xbb KEY_HOME>, //home键按键 - <0xea KEY_PLAY>, //播放按键 - <0xbf KEY_VOLUMEUP>, //音量加按键 - <0xe6 KEY_VOLUMEDOWN>, //音量键按键 - <0xf6 KEY_FASTFORWARD>, //快进按键 - <0xf8 KEY_FASTREVERSE>, //快退按键 - <0xf2 KEY_BACKSPACE>, //BaskSpace按键 - <0xf3 KEY_1>, //按键1 - <0xe7 KEY_2>, - <0xa1 KEY_3>, - <0xf7 KEY_4>, - <0xe3 KEY_5>, - <0xa5 KEY_6>, - <0xbd KEY_7>, - <0xad KEY_8>, - <0xb5 KEY_9>, - <0xe9 KEY_0>; //按键0 - }; -}; - -&rga3_core0 { - status = "okay"; -}; - -&rga3_0_mmu { - status = "okay"; -}; - -&rga3_core1 { - status = "okay"; -}; - -&rga3_1_mmu { - status = "okay"; -}; - -&rga2 { - status = "okay"; -}; - -&rknpu { - rknpu-supply = <&vdd_npu_s0>; - mem-supply = <&vdd_npu_mem_s0>; - status = "okay"; -}; - -&rknpu_mmu { - status = "okay"; -}; - -&rkvdec_ccu { - status = "okay"; -}; - -&rkvdec0 { - status = "okay"; -}; - -&rkvdec0_mmu { - status = "okay"; -}; - -&rkvdec1 { - status = "okay"; -}; - -&rkvdec1_mmu { - status = "okay"; -}; - -&rkvenc_ccu { - status = "okay"; -}; - -&rkvenc0 { - status = "okay"; -}; - -&rkvenc0_mmu { - status = "okay"; -}; - -&rkvenc1 { - status = "okay"; -}; - -&rkvenc1_mmu { - status = "okay"; -}; - -/* this is a watchdog */ -&wdt { - status = "okay"; -}; - -&gmac0 { - /* Use rgmii-rxid mode to disable rx delay inside Soc */ - phy-mode = "rgmii-rxid"; - clock_in_out = "output"; - - snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - - tx_delay = <0x26>; - /* rx_delay = <0x4f>; */ - - phy-handle = <&rgmii_phy0>; - status = "okay"; -}; - -&gmac1 { - /* Use rgmii-rxid mode to disable rx delay inside Soc */ - phy-mode = "rgmii-rxid"; - clock_in_out = "output"; - - snps,reset-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac1_miim - &gmac1_tx_bus2 - &gmac1_rx_bus2 - &gmac1_rgmii_clk - &gmac1_rgmii_bus>; - - tx_delay = <0x30>; - /* rx_delay = <0x4f>; */ - - phy-handle = <&rgmii_phy1>; - status = "okay"; -}; - -&mdio0 { - rgmii_phy0: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - jl2xxx,led-enable = <(JL2XXX_LED_STATIC_OP_EN | JL1XXX_LED_MODE_EN)>; - jl2xxx,led-mode = <(JL2XXX_LED1_LINK10 | \ - JL2XXX_LED1_LINK100 | \ - JL2XXX_LED1_LINK1000 | \ - JL2XXX_LED2_LINK10 | \ - JL2XXX_LED2_LINK100 | \ - JL2XXX_LED2_LINK1000 | \ - JL2XXX_LED2_ACTIVITY )>; //JL PHY - realtek,led-data = <0x6d60>; //8211F phy - }; -}; - -&mdio1 { - rgmii_phy1: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - jl2xxx,led-enable = <(JL2XXX_LED_STATIC_OP_EN | JL1XXX_LED_MODE_EN)>; - jl2xxx,led-mode = <(JL2XXX_LED1_LINK10 | \ - JL2XXX_LED1_LINK100 | \ - JL2XXX_LED1_LINK1000 | \ - JL2XXX_LED2_LINK10 | \ - JL2XXX_LED2_LINK100 | \ - JL2XXX_LED2_LINK1000 | \ - JL2XXX_LED2_ACTIVITY )>; //JL PHY - realtek,led-data = <0x6d60>; //8211F phy - }; -}; - -/* PCIe30 PHY Port0 & Port1 */ -&pcie30phy { - rockchip,pcie30-phymode = ; - status = "okay"; -}; - -// PCIe30 Port0: M.2 M-Key -&pcie3x4 { - num-lanes = <2>; - vpcie3v3-supply = <&vcc3v3_m2_pcie>; - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -// PCIe30 Port1: PCIe-64P -&pcie3x2 { - vpcie3v3-supply = <&vcc3v3_pciex4>; - reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -/* SATA30_HOST0/PCIe20x1_2 Combo PHY */ -&combphy0_ps { - status = "okay"; -}; - -// SATA -&sata0{ - status = "okay"; -}; - -/* SATA30_HOST1/PCIe20x1_0 Combo PHY */ -&combphy1_ps { - status = "okay"; -}; - -// M.2 E-Key -&pcie2x1l0 { - reset-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - disable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_ekey_pcie>; - status = "okay"; -}; - -/* USB30_HOST2/SATA30_HOST2/PCIe20x1_1 Combo PHY */ -&combphy2_psu { - status = "okay"; -}; - -// Mini-PCIe -&pcie2x1l1 { - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - disable-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_mini_pcie>; - status = "okay"; -}; - -/* USB3.0_OTG/DP1.4 Combo PHY0 */ -&usbdp_phy0 { - orientation-switch; - svid = <0xff01>; - sbu1-dc-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - usbdp_phy0_orientation_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; - }; - - usbdp_phy0_dp_altmode_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&dp_altmode_mux>; - }; - }; -}; - -&usbdp_phy0_u3 { - status = "okay"; -}; - -&usbdp_phy0_dp { - status = "okay"; -}; - -/* USB3.0 OTG0 Controller */ -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - usb-role-switch; - - status = "okay"; - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -/* USB2.0 PHY0 */ -&u2phy0 { - status = "okay"; -}; - -&u2phy0_otg { - rockchip,typec-vbus-det; - status = "okay"; -}; - -/* USB3.0_OTG/DP1.4 Combo PHY1 */ -&usbdp_phy1 { - rockchip,dp-lane-mux = <2 3>; - status = "okay"; -}; - -&usbdp_phy1_u3 { - status = "okay"; -}; - -&usbdrd3_1 { - status = "okay"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -/* USB2.0 PHY1 */ -&u2phy1 { - status = "okay"; -}; - -&u2phy1_otg { - phy-supply = <&vcc5v0_usb30_otg>; - status = "okay"; -}; - -/* USB2.0 HOST0 PHY2 */ -&u2phy2 { - status = "okay"; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_usb20_host>; - status = "okay"; -}; - -/* USB2.0 HOST0 Controller */ -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -/* USB2.0 HOST1 PHY3 */ -&u2phy3 { - status = "okay"; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_usb20_hub>; - status = "okay"; -}; - -/* USB2.0 HOST1 Controller */ -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&vdpu { - status = "okay"; -}; - -&vdpu_mmu { - status = "okay"; -}; - -&vepu { - status = "okay"; -}; - -&vop { - status = "okay"; - // disable-win-move; -}; - -&vop_mmu { - status = "okay"; -}; - -/* vp0 & vp1 splice for 8K output */ -&vp0 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; - rockchip,primary-plane = ; - cursor-win-id = ; -}; - -&vp1 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; - rockchip,primary-plane = ; - cursor-win-id = ; -}; - -&vp2 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; - rockchip,primary-plane = ; - cursor-win-id = ; -}; - -&vp3 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; - rockchip,primary-plane = ; - cursor-win-id = ; -}; - -&display_subsystem { - clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>; - clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; -}; - -&hdptxphy_hdmi_clk0 { - status = "okay"; -}; - -&hdptxphy_hdmi_clk1 { - status = "okay"; -}; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - headphone { - hp_det: hp-det { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - fusb302_int: fusb302-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - typec_vbus_en: typec-vbus-en { - rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_usb30_otg_en: vcc5v0-usb30-otg-en { - rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_usb20_hub_en: vcc5v0-usb20-hub-en { - rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_usb20_host_en: vcc5v0-usb20-host-en { - rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc3v3_m2_pcie_en: vcc3v3-m2-pcie-en { - rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc3v3_pcie_en: vcc3v3-pcie-en { - rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc3v3_mini_pcie_en: vcc3v3-mini-pcie-en { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc3v3_ekey_pcie_en: vcc3v3-ekey-pcie-en { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - sys_led_pin: sys-led-pin { - rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmirx { - hdmirx_det: hdmirx-det { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - mipi { - mipi_dsi0_power_en: mipi-dsi0-power-en { - rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - mipi_dsi1_power_en: mipi-dsi1-power-en { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sata { - sata_power_en: sata-power-en { - rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5ioi.dts b/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5ioi.dts deleted file mode 100644 index 33d6795e0..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588-lubancat-5ioi.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * Copyright (c) 2025 EmbedFire - */ - -/dts-v1/; - - -#include "rk3588-lubancat-5io.dts" -// #include "rk3588j.dtsi" - -/ { - /* RK3588 LubanCat-5IO Industrial */ - model = "Embedfire LubanCat-5IOI"; - compatible = "rockchip,rk3588-lubancat-5ioi", "rockchip,rk3588"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-cam0.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-cam0.dtsi deleted file mode 100644 index af7a48266..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-cam0.dtsi +++ /dev/null @@ -1,83 +0,0 @@ -/* Link path: - * sensor->csi2_dcphy0->mipi0_csi2->rkcif_mipi_lvds->rkcif_mipi_lvds_sditf->rkisp0_vir0 - */ - -&i2c1 { - status = "okay"; -}; - -&dcphy0_dw9714 { - status = "disabled"; -}; - -&dcphy0_ov5647 { - status = "disabled"; -}; - -&dcphy0_ov5648 { - status = "disabled"; -}; - -&dcphy0_ov8858 { - status = "disabled"; -}; - -&dcphy0_ov13850 { - status = "disabled"; -}; - -&dcphy0_imx415 { - status = "okay"; -}; - -&dcphy0_gc08a8 { - status = "disabled"; -}; - -&dcphy0_gc2053 { - status = "disabled"; -}; - -&dcphy0_gc4653 { - status = "disabled"; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&csi2_dcphy0 { - status = "okay"; -}; - -&mipi0_csi2 { - status = "okay"; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds { - status = "okay"; -}; - -&rkcif_mipi_lvds_sditf { - status = "okay"; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp0 { - status = "okay"; -}; - -&isp0_mmu { - status = "okay"; -}; - -&rkisp0_vir0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-cam1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-cam1.dtsi deleted file mode 100644 index 9caf2325c..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-cam1.dtsi +++ /dev/null @@ -1,83 +0,0 @@ -/* Link path: - * sensor->csi2_dcphy1->mipi1_csi2->rkcif_mipi_lvds1->rkcif_mipi_lvds1_sditf->rkisp0_vir1 - */ - -&i2c5 { - status = "okay"; -}; - -&dcphy1_dw9714 { - status = "disabled"; -}; - -&dcphy1_ov5647 { - status = "disabled"; -}; - -&dcphy1_ov5648 { - status = "disabled"; -}; - -&dcphy1_ov8858 { - status = "disabled"; -}; - -&dcphy1_ov13850 { - status = "disabled"; -}; - -&dcphy1_imx415 { - status = "okay"; -}; - -&dcphy1_gc08a8 { - status = "disabled"; -}; - -&dcphy1_gc2053 { - status = "disabled"; -}; - -&dcphy1_gc4653 { - status = "disabled"; -}; - -&csi2_dcphy1 { - status = "okay"; -}; - -&mipi1_csi2 { - status = "okay"; -}; - -&mipi_dcphy1 { - status = "okay"; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds1 { - status = "okay"; -}; - -&rkcif_mipi_lvds1_sditf { - status = "okay"; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp0 { - status = "okay"; -}; - -&isp0_mmu { - status = "okay"; -}; - -&rkisp0_vir1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-cam2.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-cam2.dtsi deleted file mode 100644 index 45991ed06..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-cam2.dtsi +++ /dev/null @@ -1,79 +0,0 @@ -/* Link path: - * sensor->csi2_dphy0->mipi2_csi2->rkcif_mipi_lvds2->rkcif_mipi_lvds2_sditf->rkisp1_vir0 - */ - -&i2c6 { - status = "okay"; -}; - -&dphy0_dw9714 { - status = "disabled"; -}; - -&dphy0_ov5647 { - status = "disabled"; -}; - -&dphy0_ov5648 { - status = "disabled"; -}; - -&dphy0_ov8858 { - status = "disabled"; -}; - -&dphy0_ov13850 { - status = "disabled"; -}; - -&dphy0_imx415 { - status = "okay"; -}; - -&dphy0_gc08a8 { - status = "disabled"; -}; - -&dphy0_gc2053 { - status = "disabled"; -}; - -&dphy0_gc4653 { - status = "disabled"; -}; - -&csi2_dphy0 { - status = "okay"; -}; - -&mipi2_csi2 { - status = "okay"; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds2 { - status = "okay"; -}; - -&rkcif_mipi_lvds2_sditf { - status = "okay"; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp1 { - status = "okay"; -}; - -&isp1_mmu { - status = "okay"; -}; - -&rkisp1_vir0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-csi.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-csi.dtsi deleted file mode 100644 index 7eeda6b46..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-csi.dtsi +++ /dev/null @@ -1,1149 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Rockchip Electronics Co., Ltd. - * - */ - -#include "rk3588-lubancat-cam.dtsi" - - -&i2c1 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1m2_xfer>; - - dcphy0_dw9714: dcphy0-dw9714@c { - status = "disabled"; - compatible = "dongwoon,dw9714"; - reg = <0xc>; - rockchip,camera-module-index = <0>; - rockchip,vcm-max-current = <100>; - rockchip,vcm-start-current = <0>; - rockchip,vcm-rated-current = <100>; - rockchip,vcm-step-mode = <0xd>; - rockchip,vcm-dlc-enable = <0>; - rockchip,vcm-mclk = <0>; - rockchip,vcm-t-src = <0>; - rockchip,camera-module-facing = "back"; - }; - - dcphy0_ov5647: dcphy0-ov5647@36 { - compatible = "ovti,ov5647"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_25m_clk>; - clock-names = "ext_cam_25m_clk"; - pwdn-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_LOW>; - lens-focus = <&dcphy0_dw9714>; - - port { - ov5647_dcphy0_out: endpoint { - remote-endpoint = <&dcphy0_in_ov5647>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy0_ov5648: dcphy0-ov5648@36 { - compatible = "ovti,ov5648"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; - rotation = <180>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "THDS11073"; - rockchip,camera-module-lens-name = "Largan-40122a1"; - lens-focus = <&dcphy0_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov5648_dcphy0_out: endpoint { - remote-endpoint = <&dcphy0_in_ov5648>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy0_ov8858: dcphy0-ov8858@36 { - compatible = "ovti,ov8858"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - rotation = <180>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "HS5885-BNSM1018-V01"; - rockchip,camera-module-lens-name = "default"; - lens-focus = <&dcphy0_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov8858_dcphy0_out: endpoint { - remote-endpoint = <&dcphy0_in_ov8858>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy0_ov13850: dcphy0-ov13850@10 { - compatible = "ovti,ov13850"; - status = "disabled"; - reg = <0x10>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - rotation = <180>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "ZC-OV13850R2A-V1"; - rockchip,camera-module-lens-name = "Largan-50064B31"; - lens-focus = <&dcphy0_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov13850_dcphy0_out: endpoint { - remote-endpoint = <&dcphy0_in_ov13850>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy0_imx415: dcphy0-imx415@1a { - compatible = "sony,imx415"; - status = "disabled"; - reg = <0x1a>; - clocks = <&ext_cam_37m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - avdd-supply = <&cam_avdd>; - dovdd-supply = <&cam_dovdd>; - dvdd-supply = <&cam_dvdd>; - - reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT2022-PX1"; - rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; - // NO_HDR:0 HDR_X2:5 HDR_X3:6 - // rockchip,camera-hdr-mode = <0>; - port { - imx415_dcphy0_out: endpoint { - remote-endpoint = <&dcphy0_in_imx415>; - data-lanes = <1 2 3 4>; - }; - }; - }; - - dcphy0_gc08a8: dcphy0-gc08a8@31 { - compatible = "galaxycore,gc08a8"; - status = "disabled"; - reg = <0x31>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - avdd-supply = <&cam_avdd>; - dovdd-supply = <&cam_dovdd>; - dvdd-supply = <&cam_dvdd>; - pwdn-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "YT10120"; - rockchip,camera-module-lens-name = "30IRC-4M-F20"; - - port { - gc08a8_dcphy0_out: endpoint { - remote-endpoint = <&dcphy0_in_gc08a8>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy0_gc2053: dcphy0-gc2053@37 { - compatible = "galaxycore,gc2053"; - status = "disabled"; - reg = <0x37>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - avdd-supply = <&cam_avdd>; - dovdd-supply = <&cam_dovdd>; - dvdd-supply = <&cam_dvdd>; - pwdn-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "SIDA205300461"; - rockchip,camera-module-lens-name = "60IRC-F20"; - - port { - gc2053_dcphy0_out: endpoint { - remote-endpoint = <&dcphy0_in_gc2053>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy0_gc4653: dcphy0-gc4653@29 { - compatible = "galaxycore,gc4653"; - status = "disabled"; - reg = <0x29>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - avdd-supply = <&cam_avdd>; - dovdd-supply = <&cam_dovdd>; - dvdd-supply = <&cam_dvdd>; - pwdn-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "YT10120"; - rockchip,camera-module-lens-name = "30IRC-4M-F20"; - - port { - gc4653_dcphy0_out: endpoint { - remote-endpoint = <&dcphy0_in_gc4653>; - data-lanes = <1 2>; - }; - }; - }; -}; - - -&i2c5 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5m3_xfer>; - - dcphy1_dw9714: dcphy1-dw9714@c { - status = "disabled"; - compatible = "dongwoon,dw9714"; - reg = <0xc>; - rockchip,camera-module-index = <1>; - rockchip,vcm-max-current = <100>; - rockchip,vcm-start-current = <0>; - rockchip,vcm-rated-current = <100>; - rockchip,vcm-step-mode = <0xd>; - rockchip,vcm-dlc-enable = <0>; - rockchip,vcm-mclk = <0>; - rockchip,vcm-t-src = <0>; - rockchip,camera-module-facing = "back"; - }; - - dcphy1_ov5647: dcphy1-ov5647@36 { - compatible = "ovti,ov5647"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_25m_clk>; - clock-names = "ext_cam_25m_clk"; - pwdn-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>; - lens-focus = <&dcphy1_dw9714>; - - port { - ov5647_dcphy1_out: endpoint { - remote-endpoint = <&dcphy1_in_ov5647>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy1_ov5648: dcphy1-ov5648@36 { - compatible = "ovti,ov5648"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_LOW>; - rotation = <180>; - - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "THDS11073"; - rockchip,camera-module-lens-name = "Largan-40122a1"; - lens-focus = <&dcphy1_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov5648_dcphy1_out: endpoint { - remote-endpoint = <&dcphy1_in_ov5648>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy1_ov8858: dcphy1-ov8858@36 { - compatible = "ovti,ov8858"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - rotation = <180>; - - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "HS5885-BNSM1018-V01"; - rockchip,camera-module-lens-name = "default"; - lens-focus = <&dcphy1_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov8858_dcphy1_out: endpoint { - remote-endpoint = <&dcphy1_in_ov8858>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy1_ov13850: dcphy1-ov13850@10 { - compatible = "ovti,ov13850"; - status = "disabled"; - reg = <0x10>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - rotation = <180>; - - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "ZC-OV13850R2A-V1"; - rockchip,camera-module-lens-name = "Largan-50064B31"; - lens-focus = <&dcphy1_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov13850_dcphy1_out: endpoint { - remote-endpoint = <&dcphy1_in_ov13850>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy1_imx415: dcphy1-imx415@1a { - compatible = "sony,imx415"; - status = "disabled"; - reg = <0x1a>; - clocks = <&ext_cam_37m_clk>; - clock-names = "xvclk"; - // power-domains = <&power RK3588_PD_VI>; - avdd-supply = <&cam_avdd>; - dovdd-supply = <&cam_dovdd>; - dvdd-supply = <&cam_dvdd>; - - reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT2022-PX1"; - rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; - port { - imx415_dcphy1_out: endpoint { - remote-endpoint = <&dcphy1_in_imx415>; - data-lanes = <1 2 3 4>; - }; - }; - }; - - dcphy1_gc08a8: dcphy1-gc08a8@31 { - compatible = "galaxycore,gc08a8"; - status = "disabled"; - reg = <0x31>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "YT10120"; - rockchip,camera-module-lens-name = "30IRC-4M-F20"; - - port { - gc08a8_dcphy1_out: endpoint { - remote-endpoint = <&dcphy1_in_gc08a8>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy1_gc2053: dcphy1-gc2053@37 { - compatible = "galaxycore,gc2053"; - status = "disabled"; - reg = <0x37>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "SIDA205300461"; - rockchip,camera-module-lens-name = "60IRC-F20"; - - port { - gc2053_dcphy1_out: endpoint { - remote-endpoint = <&dcphy1_in_gc2053>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy1_gc4653: dcphy1-gc4653@29 { - compatible = "galaxycore,gc4653"; - status = "disabled"; - reg = <0x29>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "YT10120"; - rockchip,camera-module-lens-name = "30IRC-4M-F20"; - - port { - gc4653_dcphy1_out: endpoint { - remote-endpoint = <&dcphy1_in_gc4653>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&i2c6 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6m3_xfer>; - - - dphy0_dw9714: dphy0-dw9714@c { - status = "disabled"; - compatible = "dongwoon,dw9714"; - reg = <0xc>; - rockchip,camera-module-index = <2>; - rockchip,vcm-max-current = <100>; - rockchip,vcm-start-current = <0>; - rockchip,vcm-rated-current = <100>; - rockchip,vcm-step-mode = <0xd>; - rockchip,vcm-dlc-enable = <0>; - rockchip,vcm-mclk = <0>; - rockchip,vcm-t-src = <0>; - rockchip,camera-module-facing = "back"; - }; - - dphy0_ov5647: dphy0-ov5647@36 { - compatible = "ovti,ov5647"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_25m_clk>; - clock-names = "ext_cam_25m_clk"; - pwdn-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>; - lens-focus = <&dphy0_dw9714>; - - port { - ov5647_dphy0_out: endpoint { - remote-endpoint = <&dphy0_in_ov5647>; - data-lanes = <1 2>; - }; - }; - }; - - dphy0_ov5648: dphy0-ov5648@36 { - compatible = "ovti,ov5648"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; - rotation = <180>; - - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "THDS11073"; - rockchip,camera-module-lens-name = "Largan-40122a1"; - lens-focus = <&dphy0_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov5648_dphy0_out: endpoint { - remote-endpoint = <&dphy0_in_ov5648>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dphy0_ov8858: dphy0-ov8858@36 { - compatible = "ovti,ov8858"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - rotation = <180>; - - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "HS5885-BNSM1018-V01"; - rockchip,camera-module-lens-name = "default"; - lens-focus = <&dphy0_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov8858_dphy0_out: endpoint { - remote-endpoint = <&dphy0_in_ov8858>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dphy0_ov13850: dphy0-ov13850@10 { - compatible = "ovti,ov13850"; - status = "disabled"; - reg = <0x10>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - rotation = <180>; - - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "ZC-OV13850R2A-V1"; - rockchip,camera-module-lens-name = "Largan-50064B31"; - lens-focus = <&dphy0_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov13850_dphy0_out: endpoint { - remote-endpoint = <&dphy0_in_ov13850>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dphy0_imx415: dphy0-imx415@1a { - compatible = "sony,imx415"; - status = "disabled"; - reg = <0x1a>; - clocks = <&ext_cam_37m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - - reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT2022-PX1"; - rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; - // rockchip,imx415-data-lanes=<2>; - // NO_HDR:0 HDR_X2:5 HDR_X3:6 - // rockchip,camera-hdr-mode = <0>; - port { - imx415_dphy0_out: endpoint { - remote-endpoint = <&dphy0_in_imx415>; - data-lanes = <1 2 3 4>; - }; - }; - }; - - dphy0_gc08a8: dphy0-gc08a8@31 { - compatible = "galaxycore,gc08a8"; - status = "disabled"; - reg = <0x31>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "YT10120"; - rockchip,camera-module-lens-name = "30IRC-4M-F20"; - - port { - gc08a8_dphy0_out: endpoint { - remote-endpoint = <&dphy0_in_gc08a8>; - data-lanes = <1 2>; - }; - }; - }; - - dphy0_gc2053: dphy0-gc2053@37 { - compatible = "galaxycore,gc2053"; - status = "disabled"; - reg = <0x37>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "SIDA205300461"; - rockchip,camera-module-lens-name = "60IRC-F20"; - - port { - gc2053_dphy0_out: endpoint { - remote-endpoint = <&dphy0_in_gc2053>; - data-lanes = <1 2>; - }; - }; - }; - - dphy0_gc4653: dphy0-gc4653@29 { - compatible = "galaxycore,gc4653"; - status = "disabled"; - reg = <0x29>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "YT10120"; - rockchip,camera-module-lens-name = "30IRC-4M-F20"; - - port { - gc4653_dphy0_out: endpoint { - remote-endpoint = <&dphy0_in_gc4653>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&mipi_dcphy0 { - status = "disabled"; -}; - -&csi2_dcphy0 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dcphy0_in_ov5647: endpoint@0 { - reg = <0>; - remote-endpoint = <&ov5647_dcphy0_out>; - data-lanes = <1 2>; - }; - - dcphy0_in_ov5648: endpoint@1 { - reg = <1>; - remote-endpoint = <&ov5648_dcphy0_out>; - data-lanes = <1 2>; - }; - - dcphy0_in_ov8858: endpoint@2 { - reg = <2>; - remote-endpoint = <&ov8858_dcphy0_out>; - data-lanes = <1 2>; - }; - - dcphy0_in_ov13850: endpoint@3 { - reg = <3>; - remote-endpoint = <&ov13850_dcphy0_out>; - data-lanes = <1 2>; - }; - - dcphy0_in_imx415: endpoint@4 { - reg = <4>; - remote-endpoint = <&imx415_dcphy0_out>; - data-lanes = <1 2 3 4>; - }; - - dcphy0_in_gc08a8: endpoint@5 { - reg = <5>; - remote-endpoint = <&gc08a8_dcphy0_out>; - data-lanes = <1 2>; - }; - - dcphy0_in_gc2053: endpoint@6 { - reg = <6>; - remote-endpoint = <&gc2053_dcphy0_out>; - data-lanes = <1 2>; - }; - - dcphy0_in_gc4653: endpoint@7 { - reg = <7>; - remote-endpoint = <&gc4653_dcphy0_out>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidcphy0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi0_csi2_input>; - }; - }; - }; -}; - -&mipi_dcphy1 { - status = "disabled"; -}; - -&csi2_dcphy1 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dcphy1_in_ov5647: endpoint@0 { - reg = <0>; - remote-endpoint = <&ov5647_dcphy1_out>; - data-lanes = <1 2>; - }; - - dcphy1_in_ov5648: endpoint@1 { - reg = <1>; - remote-endpoint = <&ov5648_dcphy1_out>; - data-lanes = <1 2>; - }; - - dcphy1_in_ov8858: endpoint@2 { - reg = <2>; - remote-endpoint = <&ov8858_dcphy1_out>; - data-lanes = <1 2>; - }; - - dcphy1_in_ov13850: endpoint@3 { - reg = <3>; - remote-endpoint = <&ov13850_dcphy1_out>; - data-lanes = <1 2>; - }; - - dcphy1_in_imx415: endpoint@4 { - reg = <4>; - remote-endpoint = <&imx415_dcphy1_out>; - data-lanes = <1 2 3 4>; - }; - - dcphy1_in_gc08a8: endpoint@5 { - reg = <5>; - remote-endpoint = <&gc08a8_dcphy1_out>; - data-lanes = <1 2>; - }; - - dcphy1_in_gc2053: endpoint@6 { - reg = <6>; - remote-endpoint = <&gc2053_dcphy1_out>; - data-lanes = <1 2>; - }; - - dcphy1_in_gc4653: endpoint@7 { - reg = <7>; - remote-endpoint = <&gc4653_dcphy1_out>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidcphy1_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi1_csi2_input>; - }; - }; - }; -}; - -&csi2_dphy0_hw { - status = "okay"; -}; - -&csi2_dphy0 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dphy0_in_ov5647: endpoint@0 { - reg = <0>; - remote-endpoint = <&ov5647_dphy0_out>; - data-lanes = <1 2>; - }; - - dphy0_in_ov5648: endpoint@1 { - reg = <1>; - remote-endpoint = <&ov5648_dphy0_out>; - data-lanes = <1 2>; - }; - - dphy0_in_ov8858: endpoint@2 { - reg = <2>; - remote-endpoint = <&ov8858_dphy0_out>; - data-lanes = <1 2>; - }; - - dphy0_in_ov13850: endpoint@3 { - reg = <3>; - remote-endpoint = <&ov13850_dphy0_out>; - data-lanes = <1 2>; - }; - - dphy0_in_imx415: endpoint@4 { - reg = <4>; - remote-endpoint = <&imx415_dphy0_out>; - data-lanes = <1 2 3 4>; - }; - - dphy0_in_gc08a8: endpoint@5 { - reg = <5>; - remote-endpoint = <&gc08a8_dphy0_out>; - data-lanes = <1 2>; - }; - - dphy0_in_gc2053: endpoint@6 { - reg = <6>; - remote-endpoint = <&gc2053_dphy0_out>; - data-lanes = <1 2>; - }; - - dphy0_in_gc4653: endpoint@7 { - reg = <7>; - remote-endpoint = <&gc4653_dphy0_out>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi2_csi2_input>; - }; - }; - }; -}; - -&mipi0_csi2 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidcphy0_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in0>; - }; - }; - }; -}; - -&mipi1_csi2 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi1_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidcphy1_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi1_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in1>; - }; - }; - }; -}; - -&mipi2_csi2 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy0_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in2>; - }; - }; - }; -}; - -&rkcif { - status = "disabled"; -}; - -&rkcif_mmu { - status = "disabled"; -}; - -&rkcif_mipi_lvds { - status = "disabled"; - - port { - cif_mipi_in0: endpoint { - remote-endpoint = <&mipi0_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds_sditf { - status = "disabled"; - - port { - mipi_lvds_sditf: endpoint { - remote-endpoint = <&isp0_vir0>; - }; - }; -}; - -&rkcif_mipi_lvds1 { - status = "disabled"; - - port { - cif_mipi_in1: endpoint { - remote-endpoint = <&mipi1_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds1_sditf { - status = "disabled"; - - port { - mipi_lvds1_sditf: endpoint { - remote-endpoint = <&isp0_vir1>; - }; - }; -}; - -&rkcif_mipi_lvds2 { - status = "disabled"; - - port { - cif_mipi_in2: endpoint { - remote-endpoint = <&mipi2_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds2_sditf { - status = "disabled"; - - port { - mipi_lvds2_sditf: endpoint { - remote-endpoint = <&isp1_vir0>; - }; - }; -}; - -&rkisp0 { - status = "disabled"; -}; - -&isp0_mmu { - status = "disabled"; -}; - -&rkisp0_vir0 { - status = "disabled"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds_sditf>; - }; - }; -}; - -&rkisp0_vir1 { - status = "disabled"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir1: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds1_sditf>; - }; - }; -}; - -&rkisp1 { - status = "disabled"; -}; - -&isp1_mmu { - status = "disabled"; -}; - -&rkisp1_vir0 { - status = "disabled"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp1_vir0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds2_sditf>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dp0-vp1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dp0-vp1.dtsi deleted file mode 100644 index 16e5ebc67..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dp0-vp1.dtsi +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * Copyright (c) 2023 EmbedFire - */ - -/ { - dp0_sound: dp0-sound { - status = "okay"; - compatible = "rockchip,hdmi"; - rockchip,card-name = "rockchip-dp0"; - rockchip,mclk-fs = <512>; - rockchip,cpu = <&spdif_tx2>; - rockchip,codec = <&dp0 1>; - rockchip,jack-det; - }; -}; - -&spdif_tx2 { - status = "okay"; -}; - -&dp0 { - status = "okay"; -}; - -&route_dp0 { - status = "okay"; - connect = <&vp1_out_dp0>; -}; - -&dp0_in_vp0 { - status = "disabled"; -}; - -&dp0_in_vp1 { - status = "okay"; -}; - -&dp0_in_vp2 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi0-vp2-1024x600-7inch-ebf410173.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi0-vp2-1024x600-7inch-ebf410173.dtsi deleted file mode 100644 index 8967adae4..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi0-vp2-1024x600-7inch-ebf410173.dtsi +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -&mipi_dcphy0 { - status = "okay"; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp2_out_dsi0>; -}; - -&dsi0_in_vp2 { - status = "okay"; -}; - -&dsi0 { - status = "okay"; - - dsi0_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight_dsi0>; - power-supply = <&mipi_dsi0_power>; - reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; - - enable-delay-ms = <35>; - prepare-delay-ms = <6>; - reset-delay-ms = <0>; - init-delay-ms = <20>; - unprepare-delay-ms = <0>; - disable-delay-ms = <20>; - - size,width = <74>; - size,height = <133>; - - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - - panel-init-sequence = [ - 15 00 02 80 AC - 15 00 02 81 B8 - 15 00 02 82 09 - 15 00 02 83 78 - 15 00 02 84 7F - 15 00 02 85 BB - 15 00 02 86 70 - 05 C8 01 11 - 05 C8 01 29 - ]; - - panel-exit-sequence = [ - 05 78 01 28 - 05 00 01 10 - ]; - - disp0_timings0: display-timings { - native-mode = <&dsi0_timing0>; - dsi0_timing0: timing0 { - clock-frequency = <51668640>; - hactive = <1024>; - vactive = <600>; - hsync-len = <10>; - hback-porch = <160>; - hfront-porch = <160>; - vsync-len = <1>; - vback-porch = <23>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in_dsi0: endpoint { - remote-endpoint = <&dsi0_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi0_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi0>; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5m3_xfer>; - - gt911_dsi0: gt911@5d { - status = "okay"; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio0>; - interrupts = ; - reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; - irq-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - touchscreen-inverted-x = <1>; - touchscreen-inverted-y = <1>; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi0-vp2-1080x1920-5.5inch-ebf410125.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi0-vp2-1080x1920-5.5inch-ebf410125.dtsi deleted file mode 100644 index 896691549..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi0-vp2-1080x1920-5.5inch-ebf410125.dtsi +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -&mipi_dcphy0 { - status = "okay"; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp2_out_dsi0>; -}; - -&dsi0_in_vp2 { - status = "okay"; -}; - -&dsi0 { - status = "okay"; - - dsi0_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight_dsi0>; - power-supply = <&mipi_dsi0_power>; - reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; - - enable-delay-ms = <35>; - prepare-delay-ms = <6>; - reset-delay-ms = <10>; - init-delay-ms = <50>; - unprepare-delay-ms = <0>; - disable-delay-ms = <20>; - - size,width = <74>; - size,height = <133>; - - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - - panel-init-sequence = [ - 39 00 04 B9 FF 83 99 - 15 00 02 D2 77 - 39 00 10 B1 02 04 74 94 01 32 33 11 11 AB 4D 56 73 02 02 - 39 00 10 B2 00 80 80 AE 05 07 5A 11 00 00 10 1E 70 03 D4 - 15 00 02 36 02 - 39 00 2D B4 00 FF 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 21 03 01 00 0F B8 8B 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 01 00 0F B8 01 - 39 05 22 D3 00 00 00 00 00 00 06 00 00 10 04 00 04 00 00 00 00 00 00 00 00 00 00 01 00 05 05 07 00 00 00 05 40 - 39 05 21 D5 18 18 19 19 18 18 21 20 01 00 07 06 05 04 03 02 18 18 18 18 18 18 2F 2F 30 30 31 31 18 18 18 18 - 39 05 21 D6 18 18 19 19 40 40 20 21 06 07 00 01 02 03 04 05 40 40 40 40 40 40 2F 2F 30 30 31 31 40 40 40 40 - 39 00 11 D8 A2 AA 02 A0 A2 A8 02 A0 B0 00 00 00 B0 00 00 00 - 15 00 02 BD 01 - 39 00 11 D8 B0 00 00 00 B0 00 00 00 E2 AA 03 F0 E2 AA 03 F0 - 15 00 02 BD 02 - 39 00 09 D8 E2 AA 03 F0 E2 AA 03 F0 - 15 00 02 BD 00 - 39 00 03 B6 8D 8D - 39 05 37 E0 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77 - 05 C8 01 11 - 05 C8 01 29 - ]; - - panel-exit-sequence = [ - 05 78 01 28 - 05 00 01 10 - ]; - - disp0_timings0: display-timings { - native-mode = <&dsi0_timing0>; - dsi0_timing0: timing0 { - clock-frequency = <131376000>; - hactive = <1080>; - vactive = <1920>; - hsync-len = <10>; - hback-porch = <20>; - hfront-porch = <10>; - vsync-len = <5>; - vback-porch = <20>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in_dsi0: endpoint { - remote-endpoint = <&dsi0_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi0_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi0>; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5m3_xfer>; - - gt911_dsi0: gt911@5d { - status = "okay"; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio0>; - interrupts = ; - reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; - irq-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - touchscreen-inverted-x = <1>; - touchscreen-inverted-y = <1>; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi0-vp2-800x1280-10.1inch-ebf410177.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi0-vp2-800x1280-10.1inch-ebf410177.dtsi deleted file mode 100644 index 22264939a..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi0-vp2-800x1280-10.1inch-ebf410177.dtsi +++ /dev/null @@ -1,303 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -&mipi_dcphy0 { - status = "okay"; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp2_out_dsi0>; -}; - -&dsi0_in_vp2 { - status = "okay"; -}; - -&dsi0 { - status = "okay"; - - dsi0_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight_dsi0>; - power-supply = <&mipi_dsi0_power>; - reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; - - enable-delay-ms = <35>; - prepare-delay-ms = <6>; - reset-delay-ms = <0>; - init-delay-ms = <20>; - unprepare-delay-ms = <0>; - disable-delay-ms = <20>; - - size,width = <74>; - size,height = <133>; - - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - - panel-init-sequence = [ - 39 05 04 FF 98 81 03 - 15 05 02 01 00 - 15 05 02 02 00 - 15 05 02 03 53 - 15 05 02 04 D3 - 15 05 02 05 00 - 15 05 02 06 0D - 15 05 02 07 08 - 15 05 02 08 00 - 15 05 02 09 00 - 15 05 02 0a 00 - 15 05 02 0b 00 - 15 05 02 0c 00 - 15 05 02 0d 00 - 15 05 02 0e 00 - 15 05 02 0f 28 - 15 05 02 10 28 - 15 05 02 11 00 - 15 05 02 12 00 - 15 05 02 13 00 - 15 05 02 14 00 - 15 05 02 15 00 - 15 05 02 16 00 - 15 05 02 17 00 - 15 05 02 18 00 - 15 05 02 19 00 - 15 05 02 1a 00 - 15 05 02 1b 00 - 15 05 02 1d 00 - 15 05 02 1e 40 - 15 05 02 1f 80 - 15 05 02 20 06 - 15 05 02 21 01 - 15 05 02 22 00 - 15 05 02 23 00 - 15 05 02 24 00 - 15 05 02 25 00 - 15 05 02 26 00 - 15 05 02 27 00 - 15 05 02 28 33 - 15 05 02 29 33 - 15 05 02 2a 00 - 15 05 02 2b 00 - 15 05 02 2c 00 - 15 05 02 2d 00 - 15 05 02 2e 00 - 15 05 02 2f 00 - 15 05 02 30 00 - 15 05 02 31 00 - 15 05 02 32 00 - 15 05 02 33 00 - 15 05 02 34 03 - 15 05 02 35 00 - 15 05 02 36 00 - 15 05 02 37 00 - 15 05 02 38 96 - 15 05 02 39 00 - 15 05 02 3a 00 - 15 05 02 3b 00 - 15 05 02 3c 00 - 15 05 02 3d 00 - 15 05 02 3e 00 - 15 05 02 3f 00 - 15 05 02 40 00 - 15 05 02 41 00 - 15 05 02 42 00 - 15 05 02 43 00 - 15 05 02 44 00 - 15 05 02 50 00 - 15 05 02 51 23 - 15 05 02 52 45 - 15 05 02 53 67 - 15 05 02 54 89 - 15 05 02 55 AB - 15 05 02 56 01 - 15 05 02 57 23 - 15 05 02 58 45 - 15 05 02 59 67 - 15 05 02 5a 89 - 15 05 02 5b AB - 15 05 02 5c CD - 15 05 02 5d EF - 15 05 02 5e 00 - 15 05 02 5f 08 - 15 05 02 60 08 - 15 05 02 61 06 - 15 05 02 62 06 - 15 05 02 63 01 - 15 05 02 64 01 - 15 05 02 65 00 - 15 05 02 66 00 - 15 05 02 67 02 - 15 05 02 68 15 - 15 05 02 69 15 - 15 05 02 6a 14 - 15 05 02 6b 14 - 15 05 02 6c 0D - 15 05 02 6d 0D - 15 05 02 6e 0C - 15 05 02 6f 0C - 15 05 02 70 0F - 15 05 02 71 0F - 15 05 02 72 0E - 15 05 02 73 0E - 15 05 02 74 02 - 15 05 02 75 08 - 15 05 02 76 08 - 15 05 02 77 06 - 15 05 02 78 06 - 15 05 02 79 01 - 15 05 02 7a 01 - 15 05 02 7b 00 - 15 05 02 7c 00 - 15 05 02 7d 02 - 15 05 02 7e 15 - 15 05 02 7f 15 - 15 05 02 80 14 - 15 05 02 81 14 - 15 05 02 82 0D - 15 05 02 83 0D - 15 05 02 84 0C - 15 05 02 85 0C - 15 05 02 86 0F - 15 05 02 87 0F - 15 05 02 88 0E - 15 05 02 89 0E - 15 05 02 8A 02 - 39 05 04 FF 98 81 04 - 15 05 02 6E 2B - 15 05 02 6F 37 - 15 05 02 3A 24 - 15 05 02 8D 1A - 15 05 02 87 BA - 15 05 02 B2 D1 - 15 05 02 88 0B - 15 05 02 38 01 - 15 05 02 39 00 - 15 05 02 B5 02 - 15 05 02 31 25 - 15 05 02 3B 98 - 39 05 04 FF 98 81 01 - 15 05 02 22 0A - 15 05 02 31 00 - 15 05 02 53 3D - 15 05 02 55 3D - 15 05 02 50 B5 - 15 05 02 51 AD - 15 05 02 60 06 - 15 05 02 62 20 - 15 05 02 A0 00 - 15 05 02 A1 21 - 15 05 02 A2 35 - 15 05 02 A3 19 - 15 05 02 A4 1E - 15 05 02 A5 33 - 15 05 02 A6 27 - 15 05 02 A7 26 - 15 05 02 A8 AF - 15 05 02 A9 1B - 15 05 02 AA 27 - 15 05 02 AB 8D - 15 05 02 AC 1A - 15 05 02 AD 1B - 15 05 02 AE 50 - 15 05 02 AF 26 - 15 05 02 B0 2B - 15 05 02 B1 54 - 15 05 02 B2 5E - 15 05 02 B3 23 - 15 05 02 C0 00 - 15 05 02 C1 21 - 15 05 02 C2 35 - 15 05 02 C3 19 - 15 05 02 C4 1E - 15 05 02 C5 33 - 15 05 02 C6 27 - 15 05 02 C7 26 - 15 05 02 C8 AF - 15 05 02 C9 1B - 15 05 02 CA 27 - 15 05 02 CB 8D - 15 05 02 CC 1A - 15 05 02 CD 1B - 15 05 02 CE 50 - 15 05 02 CF 26 - 15 05 02 D0 2B - 15 05 02 D1 54 - 15 05 02 D2 5E - 15 05 02 D3 23 - 39 05 04 FF 98 81 00 - 15 78 02 11 00 - 15 05 02 29 00 - ]; - - panel-exit-sequence = [ - 05 78 01 28 - 05 00 01 10 - ]; - - disp0_timings0: display-timings { - native-mode = <&dsi0_timing0>; - dsi0_timing0: timing0 { - clock-frequency = <67000000>; - hactive = <800>; - vactive = <1280>; - hsync-len = <24>; - hback-porch = <24>; - hfront-porch = <12>; - vsync-len = <2>; - vback-porch = <9>; - vfront-porch = <7>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in_dsi0: endpoint { - remote-endpoint = <&dsi0_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi0_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi0>; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5m3_xfer>; - - gt911_dsi0: gt911@5d { - status = "okay"; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio0>; - interrupts = ; - reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; - irq-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi1-vp3-1024x600-7inch-ebf410173.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi1-vp3-1024x600-7inch-ebf410173.dtsi deleted file mode 100644 index bb9d0f7fd..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi1-vp3-1024x600-7inch-ebf410173.dtsi +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -&mipi_dcphy1 { - status = "okay"; -}; - -&route_dsi1 { - status = "okay"; - connect = <&vp3_out_dsi1>; -}; - -&dsi1_in_vp3 { - status = "okay"; -}; - -&dsi1 { - status = "okay"; - - dsi1_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight_dsi1>; - power-supply = <&mipi_dsi1_power>; - reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; - - enable-delay-ms = <35>; - prepare-delay-ms = <6>; - reset-delay-ms = <0>; - init-delay-ms = <20>; - unprepare-delay-ms = <0>; - disable-delay-ms = <20>; - - size,width = <74>; - size,height = <133>; - - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - - panel-init-sequence = [ - 15 00 02 80 AC - 15 00 02 81 B8 - 15 00 02 82 09 - 15 00 02 83 78 - 15 00 02 84 7F - 15 00 02 85 BB - 15 00 02 86 70 - 05 C8 01 11 - 05 C8 01 29 - ]; - - panel-exit-sequence = [ - 05 78 01 28 - 05 00 01 10 - ]; - - disp1_timings0: display-timings { - native-mode = <&dsi1_timing0>; - dsi1_timing0: timing0 { - clock-frequency = <51668640>; - hactive = <1024>; - vactive = <600>; - hsync-len = <10>; - hback-porch = <160>; - hfront-porch = <160>; - vsync-len = <1>; - vback-porch = <23>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in_dsi1: endpoint { - remote-endpoint = <&dsi1_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi1_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi1>; - }; - }; - }; -}; - -&i2c6 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6m3_xfer>; - - gt911_dsi1: gt911@5d { - status = "okay"; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio3>; - interrupts = ; - reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>; - irq-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; - touchscreen-inverted-x = <1>; - touchscreen-inverted-y = <1>; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi1-vp3-1080x1920-5.5inch-ebf410125.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi1-vp3-1080x1920-5.5inch-ebf410125.dtsi deleted file mode 100644 index f5d7f7b27..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi1-vp3-1080x1920-5.5inch-ebf410125.dtsi +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -&mipi_dcphy1 { - status = "okay"; -}; - -&route_dsi1 { - status = "okay"; - connect = <&vp3_out_dsi1>; -}; - -&dsi1_in_vp3 { - status = "okay"; -}; - -&dsi1 { - status = "okay"; - - dsi1_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight_dsi1>; - power-supply = <&mipi_dsi1_power>; - reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; - - enable-delay-ms = <35>; - prepare-delay-ms = <6>; - reset-delay-ms = <10>; - init-delay-ms = <50>; - unprepare-delay-ms = <0>; - disable-delay-ms = <20>; - - size,width = <74>; - size,height = <133>; - - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - - panel-init-sequence = [ - 39 00 04 B9 FF 83 99 - 15 00 02 D2 77 - 39 00 10 B1 02 04 74 94 01 32 33 11 11 AB 4D 56 73 02 02 - 39 00 10 B2 00 80 80 AE 05 07 5A 11 00 00 10 1E 70 03 D4 - 15 00 02 36 02 - 39 00 2D B4 00 FF 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 21 03 01 00 0F B8 8B 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 01 00 0F B8 01 - 39 05 22 D3 00 00 00 00 00 00 06 00 00 10 04 00 04 00 00 00 00 00 00 00 00 00 00 01 00 05 05 07 00 00 00 05 40 - 39 05 21 D5 18 18 19 19 18 18 21 20 01 00 07 06 05 04 03 02 18 18 18 18 18 18 2F 2F 30 30 31 31 18 18 18 18 - 39 05 21 D6 18 18 19 19 40 40 20 21 06 07 00 01 02 03 04 05 40 40 40 40 40 40 2F 2F 30 30 31 31 40 40 40 40 - 39 00 11 D8 A2 AA 02 A0 A2 A8 02 A0 B0 00 00 00 B0 00 00 00 - 15 00 02 BD 01 - 39 00 11 D8 B0 00 00 00 B0 00 00 00 E2 AA 03 F0 E2 AA 03 F0 - 15 00 02 BD 02 - 39 00 09 D8 E2 AA 03 F0 E2 AA 03 F0 - 15 00 02 BD 00 - 39 00 03 B6 8D 8D - 39 05 37 E0 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77 - 05 C8 01 11 - 05 C8 01 29 - ]; - - panel-exit-sequence = [ - 05 78 01 28 - 05 00 01 10 - ]; - - disp1_timings0: display-timings { - native-mode = <&dsi1_timing0>; - dsi1_timing0: timing0 { - clock-frequency = <131376000>; - hactive = <1080>; - vactive = <1920>; - hsync-len = <10>; - hback-porch = <20>; - hfront-porch = <10>; - vsync-len = <5>; - vback-porch = <20>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in_dsi1: endpoint { - remote-endpoint = <&dsi1_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi1_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi1>; - }; - }; - }; -}; - -&i2c6 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6m3_xfer>; - - gt911_dsi1: gt911@5d { - status = "okay"; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio3>; - interrupts = ; - reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>; - irq-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; - touchscreen-inverted-x = <1>; - touchscreen-inverted-y = <1>; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi1-vp3-800x1280-10.1inch-ebf410177.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi1-vp3-800x1280-10.1inch-ebf410177.dtsi deleted file mode 100644 index 8f3f45ff8..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi1-vp3-800x1280-10.1inch-ebf410177.dtsi +++ /dev/null @@ -1,303 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -&mipi_dcphy1 { - status = "okay"; -}; - -&route_dsi1 { - status = "okay"; - connect = <&vp3_out_dsi1>; -}; - -&dsi1_in_vp3 { - status = "okay"; -}; - -&dsi1 { - status = "okay"; - - dsi1_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight_dsi1>; - power-supply = <&mipi_dsi1_power>; - reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; - - enable-delay-ms = <35>; - prepare-delay-ms = <6>; - reset-delay-ms = <0>; - init-delay-ms = <20>; - unprepare-delay-ms = <0>; - disable-delay-ms = <20>; - - size,width = <74>; - size,height = <133>; - - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - - panel-init-sequence = [ - 39 05 04 FF 98 81 03 - 15 05 02 01 00 - 15 05 02 02 00 - 15 05 02 03 53 - 15 05 02 04 D3 - 15 05 02 05 00 - 15 05 02 06 0D - 15 05 02 07 08 - 15 05 02 08 00 - 15 05 02 09 00 - 15 05 02 0a 00 - 15 05 02 0b 00 - 15 05 02 0c 00 - 15 05 02 0d 00 - 15 05 02 0e 00 - 15 05 02 0f 28 - 15 05 02 10 28 - 15 05 02 11 00 - 15 05 02 12 00 - 15 05 02 13 00 - 15 05 02 14 00 - 15 05 02 15 00 - 15 05 02 16 00 - 15 05 02 17 00 - 15 05 02 18 00 - 15 05 02 19 00 - 15 05 02 1a 00 - 15 05 02 1b 00 - 15 05 02 1d 00 - 15 05 02 1e 40 - 15 05 02 1f 80 - 15 05 02 20 06 - 15 05 02 21 01 - 15 05 02 22 00 - 15 05 02 23 00 - 15 05 02 24 00 - 15 05 02 25 00 - 15 05 02 26 00 - 15 05 02 27 00 - 15 05 02 28 33 - 15 05 02 29 33 - 15 05 02 2a 00 - 15 05 02 2b 00 - 15 05 02 2c 00 - 15 05 02 2d 00 - 15 05 02 2e 00 - 15 05 02 2f 00 - 15 05 02 30 00 - 15 05 02 31 00 - 15 05 02 32 00 - 15 05 02 33 00 - 15 05 02 34 03 - 15 05 02 35 00 - 15 05 02 36 00 - 15 05 02 37 00 - 15 05 02 38 96 - 15 05 02 39 00 - 15 05 02 3a 00 - 15 05 02 3b 00 - 15 05 02 3c 00 - 15 05 02 3d 00 - 15 05 02 3e 00 - 15 05 02 3f 00 - 15 05 02 40 00 - 15 05 02 41 00 - 15 05 02 42 00 - 15 05 02 43 00 - 15 05 02 44 00 - 15 05 02 50 00 - 15 05 02 51 23 - 15 05 02 52 45 - 15 05 02 53 67 - 15 05 02 54 89 - 15 05 02 55 AB - 15 05 02 56 01 - 15 05 02 57 23 - 15 05 02 58 45 - 15 05 02 59 67 - 15 05 02 5a 89 - 15 05 02 5b AB - 15 05 02 5c CD - 15 05 02 5d EF - 15 05 02 5e 00 - 15 05 02 5f 08 - 15 05 02 60 08 - 15 05 02 61 06 - 15 05 02 62 06 - 15 05 02 63 01 - 15 05 02 64 01 - 15 05 02 65 00 - 15 05 02 66 00 - 15 05 02 67 02 - 15 05 02 68 15 - 15 05 02 69 15 - 15 05 02 6a 14 - 15 05 02 6b 14 - 15 05 02 6c 0D - 15 05 02 6d 0D - 15 05 02 6e 0C - 15 05 02 6f 0C - 15 05 02 70 0F - 15 05 02 71 0F - 15 05 02 72 0E - 15 05 02 73 0E - 15 05 02 74 02 - 15 05 02 75 08 - 15 05 02 76 08 - 15 05 02 77 06 - 15 05 02 78 06 - 15 05 02 79 01 - 15 05 02 7a 01 - 15 05 02 7b 00 - 15 05 02 7c 00 - 15 05 02 7d 02 - 15 05 02 7e 15 - 15 05 02 7f 15 - 15 05 02 80 14 - 15 05 02 81 14 - 15 05 02 82 0D - 15 05 02 83 0D - 15 05 02 84 0C - 15 05 02 85 0C - 15 05 02 86 0F - 15 05 02 87 0F - 15 05 02 88 0E - 15 05 02 89 0E - 15 05 02 8A 02 - 39 05 04 FF 98 81 04 - 15 05 02 6E 2B - 15 05 02 6F 37 - 15 05 02 3A 24 - 15 05 02 8D 1A - 15 05 02 87 BA - 15 05 02 B2 D1 - 15 05 02 88 0B - 15 05 02 38 01 - 15 05 02 39 00 - 15 05 02 B5 02 - 15 05 02 31 25 - 15 05 02 3B 98 - 39 05 04 FF 98 81 01 - 15 05 02 22 0A - 15 05 02 31 00 - 15 05 02 53 3D - 15 05 02 55 3D - 15 05 02 50 B5 - 15 05 02 51 AD - 15 05 02 60 06 - 15 05 02 62 20 - 15 05 02 A0 00 - 15 05 02 A1 21 - 15 05 02 A2 35 - 15 05 02 A3 19 - 15 05 02 A4 1E - 15 05 02 A5 33 - 15 05 02 A6 27 - 15 05 02 A7 26 - 15 05 02 A8 AF - 15 05 02 A9 1B - 15 05 02 AA 27 - 15 05 02 AB 8D - 15 05 02 AC 1A - 15 05 02 AD 1B - 15 05 02 AE 50 - 15 05 02 AF 26 - 15 05 02 B0 2B - 15 05 02 B1 54 - 15 05 02 B2 5E - 15 05 02 B3 23 - 15 05 02 C0 00 - 15 05 02 C1 21 - 15 05 02 C2 35 - 15 05 02 C3 19 - 15 05 02 C4 1E - 15 05 02 C5 33 - 15 05 02 C6 27 - 15 05 02 C7 26 - 15 05 02 C8 AF - 15 05 02 C9 1B - 15 05 02 CA 27 - 15 05 02 CB 8D - 15 05 02 CC 1A - 15 05 02 CD 1B - 15 05 02 CE 50 - 15 05 02 CF 26 - 15 05 02 D0 2B - 15 05 02 D1 54 - 15 05 02 D2 5E - 15 05 02 D3 23 - 39 05 04 FF 98 81 00 - 15 78 02 11 00 - 15 05 02 29 00 - ]; - - panel-exit-sequence = [ - 05 78 01 28 - 05 00 01 10 - ]; - - disp1_timings0: display-timings { - native-mode = <&dsi1_timing0>; - dsi1_timing0: timing0 { - clock-frequency = <67000000>; - hactive = <800>; - vactive = <1280>; - hsync-len = <24>; - hback-porch = <24>; - hfront-porch = <12>; - vsync-len = <2>; - vback-porch = <9>; - vfront-porch = <7>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in_dsi1: endpoint { - remote-endpoint = <&dsi1_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi1_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi1>; - }; - }; - }; -}; - -&i2c6 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6m3_xfer>; - - gt911_dsi1: gt911@5d { - status = "okay"; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio3>; - interrupts = ; - reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>; - irq-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-hdmi0-vp0.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-hdmi0-vp0.dtsi deleted file mode 100644 index 189bddef0..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-hdmi0-vp0.dtsi +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * Copyright (c) 2023 EmbedFire - */ - -/ { - hdmi0_sound: hdmi0-sound { - status = "okay"; - compatible = "rockchip,hdmi"; - rockchip,mclk-fs = <128>; - rockchip,card-name = "rockchip-hdmi0"; - rockchip,cpu = <&i2s5_8ch>; - rockchip,codec = <&hdmi0>; - rockchip,jack-det; - }; -}; - -&i2s5_8ch { - status = "okay"; -}; - -&hdmi0 { - enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - cec-enable = "true"; - status = "okay"; -}; - -&route_hdmi0{ - status = "okay"; - connect = <&vp0_out_hdmi0>; -}; - -&hdmi0_in_vp0 { - status = "okay"; -}; - -&hdmi0_in_vp1 { - status = "disabled"; -}; - -&hdmi0_in_vp2 { - status = "disabled"; -}; - -&hdptxphy_hdmi0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-v1.dts b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-v1.dts deleted file mode 100644 index 548d7d79d..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-v1.dts +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * Copyright (c) 2023 EmbedFire - */ - -/dts-v1/; - -#include "rk3588s-lubancat-4.dts" - -/ { - model = "Embedfire LubanCat-4 V1"; - compatible = "embedfire,rk3588s-lubancat-4-v1", "rockchip,rk3588"; -}; - -&pinctrl{ - dsi { - dsi0_reset: dsi0-reset { - rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - tp1_irq: tp1-irq { - rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4.dts b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4.dts deleted file mode 100644 index ce3298667..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4.dts +++ /dev/null @@ -1,1530 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * Copyright (c) 2023 EmbedFire - */ - -/dts-v1/; - -#include -#include -#include -#include -//#include -#include -#include -#include -#include -#include -#include "rk3588s.dtsi" -#include "rk3588-linux.dtsi" - -/* MIPI CSI 节点配置 */ -#include "rk3588s-lubancat-4-csi.dtsi" -/* IMX415 示例, 开启链路节点 */ -// #include "rk3588s-lubancat-4-cam0.dtsi" -// #include "rk3588s-lubancat-4-cam1.dtsi" -// #include "rk3588s-lubancat-4-cam2.dtsi" - -/* 显示输出配置， - * 同一个vp同时只能开启一个配置 - * 最多可以同时开启4个vp - * mipi屏幕默认使用设备树插件开启 - */ -/***** vp0 *****/ -/* hdmi0 display */ -// #include "rk3588s-lubancat-4-hdmi0-vp0.dtsi" - -/***** vp1 *****/ -/* dp0 display */ -// #include "rk3588s-lubancat-4-dp0-vp1.dtsi" - -/***** vp2 *****/ -// #include "rk3588s-lubancat-4-dsi0-vp2-1080x1920-5.5inch-ebf410125.dtsi" -// #include "rk3588s-lubancat-4-dsi0-vp2-1024x600-7inch-ebf410173.dtsi" -// #include "rk3588s-lubancat-4-dsi0-vp2-800x1280-10.1inch-ebf410177.dtsi" - -/***** vp3 *****/ -// #include "rk3588s-lubancat-4-dsi1-vp3-1080x1920-5.5inch-ebf410125.dtsi" -// #include "rk3588s-lubancat-4-dsi1-vp3-1024x600-7inch-ebf410173.dtsi" -// #include "rk3588s-lubancat-4-dsi1-vp3-800x1280-10.1inch-ebf410177.dtsi" - -/ { - model = "Embedfire LubanCat-4"; - compatible = "embedfire,rk3588s-lubancat-4", "rockchip,rk3588"; - - leds: leds { - status = "okay"; - compatible = "gpio-leds"; - - sys_led: sys-led { - label = "sys_led"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&sys_led_pin>; - }; - }; - - vcc5v0_dcin: vcc5v0-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc5v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_dcin>; - }; - - vcc_5v0: vcc-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; - - combophy_avdd0v85: combophy-avdd0v85 { - compatible = "regulator-fixed"; - regulator-name = "combophy_avdd0v85"; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&avdd_0v85_s0>; - }; - - combophy_avdd1v8: combophy-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "combophy_avdd1v8"; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_3v3_s0: vcc-3v3-s0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc_3v3_sd_s3: vcc-3v3-sd-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_sd_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_s3>; - }; - - vbus5v0_typec: vbus5v0-typec { - compatible = "regulator-fixed"; - regulator-name = "vbus5v0_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&typec_vbus_en>; - }; - - vcc5v0_usb30_host: vcc5v0-usb30-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb30_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&usb30_host_pwr_en>; - }; - - vcc5v0_usb20_host: vcc5v0-usb20-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb20_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&usb20_host_pwr_en>; - }; - - vcc3v3_pcie20: vcc3v3-pcie20 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie20"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - regulator-always-on; - gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - vin-supply = <&vcc5v0_sys>; - }; - - mipi_dsi0_power: mipi-dsi0-power-regulator { - compatible = "regulator-fixed"; - regulator-name = "mipi_dsi0_power"; - gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - }; - - mipi_dsi1_power: mipi-dsi1-power-regulator { - compatible = "regulator-fixed"; - regulator-name = "mipi_dsi1_power"; - gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - }; - - es8388_sound: es8388-sound { - status = "okay"; - compatible = "rockchip,multicodecs-card"; - rockchip,card-name = "rockchip-es8388"; - hp-det-gpio = <&gpio1 RK_PC0 GPIO_ACTIVE_HIGH>; - hp-con-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; - io-channels = <&saradc 4>; - io-channel-names = "adc-detect"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - rockchip,format = "i2s"; - rockchip,mclk-fs = <256>; - rockchip,cpu = <&i2s0_8ch>; - rockchip,codec = <&es8388>; - rockchip,audio-routing = - "Headphone", "LOUT1", - "Headphone", "ROUT1", - "Headphone", "Headphone Power", - "Headphone", "Headphone Power", - "LINPUT1", "Headset Mic", - "RINPUT1", "Headset Mic", - "LINPUT2", "Main Mic", - "RINPUT2", "Main Mic"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - play-pause-key { - label = "playpause"; - linux,code = ; - press-threshold-microvolt = <2000>; - }; - - previous-song-key { - label = "previoussong"; - linux,code = ; - press-threshold-microvolt = <145000>; - }; - - next-song-key { - label = "nextsong"; - linux,code = ; - press-threshold-microvolt = <290000>; - }; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - pwms = <&pwm0 0 5000 0>; - cooling-levels = <0 100 150 200 255>; - rockchip,temp-trips = < - 40000 1 - 55000 2 - 60000 3 - 65000 4 - >; - }; - - backlight_dsi0: backlight-dsi0 { - status = "okay"; - compatible = "pwm-backlight"; - pwms = <&pwm2 0 25000 0>; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - backlight_dsi1: backlight-dsi1 { - status = "okay"; - compatible = "pwm-backlight"; - pwms = <&pwm6 0 25000 0>; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - test-power { - status = "okay"; - }; -}; - -&av1d { - status = "okay"; -}; - -&av1d_mmu { - status = "okay"; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - mem-supply = <&vdd_gpu_mem_s0>; - upthreshold = <60>; - downdifferential = <30>; - status = "okay"; -}; - -&dfi { - status = "okay"; -}; - -&dmc { - status = "okay"; - center-supply = <&vdd_ddr_s0>; - mem-supply = <&vdd_log_s0>; -}; - -&rockchip_suspend { - status = "okay"; - rockchip,sleep-debug-en = <1>; - rockchip,sleep-mode-config = < - (0 - | RKPM_SLP_ARMOFF_DDRPD - | RKPM_SLP_PMU_PMUALIVE_32K - | RKPM_SLP_PMU_DIS_OSC - | RKPM_SLP_32K_EXT - ) - >; - rockchip,wakeup-config = < - (0 - | RKPM_GPIO_WKUP_EN - | RKPM_CPU0_WKUP_EN - ) - >; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; - - vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big0_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { - compatible = "rockchip,rk8603"; - reg = <0x43>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big1_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1m2_xfer>; - status = "okay"; - - vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_npu_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* Typec Controller Fusb302 */ - usbc0: fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&fusb302_int>; - vbus-supply = <&vbus5v0_typec>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - ; - source-pdos = - ; - - altmodes { - #address-cells = <1>; - #size-cells = <0>; - - altmode@0 { - reg = <0>; - svid = <0xff01>; - vdo = <0xffffffff>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; - }; - }; - - port@1 { - reg = <1>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; - }; - }; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5m3_xfer>; -}; - -&i2c6 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6m3_xfer>; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - num-cs = <1>; - - rk806single@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - - interrupt-parent = <&gpio0>; - interrupts = ; - - pinctrl-names = "default", "pmic-power-off"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; - pinctrl-1 = <&rk806_dvs1_pwrdn>; - - /* 2800mv-3500mv */ - low_voltage_threshold = <3000>; - /* 2700mv-3400mv */ - shutdown_voltage_threshold = <2700>; - /* 140 160 */ - shutdown_temperture_threshold = <160>; - hotdie_temperture_threshold = <115>; - - /* 0: restart PMU; - * 1: reset all the power off reset registers, - * forcing the state to switch to ACTIVE mode; - * 2: Reset all the power off reset registers, - * forcing the state to switch to ACTIVE mode, - * and simultaneously pull down the RESETB PIN for 5mS before releasing - */ - pmic-reset-func = <1>; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - pwrkey { - status = "okay"; - }; - - pinctrl_rk806: pinctrl_rk806 { - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: rk806_dvs1_null { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs1_slp: rk806_dvs1_slp { - pins = "gpio_pwrctrl1"; - function = "pin_fun1"; - }; - - rk806_dvs1_pwrdn: rk806_dvs1_pwrdn { - pins = "gpio_pwrctrl1"; - function = "pin_fun2"; - }; - - rk806_dvs1_rst: rk806_dvs1_rst { - pins = "gpio_pwrctrl1"; - function = "pin_fun3"; - }; - - rk806_dvs2_null: rk806_dvs2_null { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_slp: rk806_dvs2_slp { - pins = "gpio_pwrctrl2"; - function = "pin_fun1"; - }; - - rk806_dvs2_pwrdn: rk806_dvs2_pwrdn { - pins = "gpio_pwrctrl2"; - function = "pin_fun2"; - }; - - rk806_dvs2_rst: rk806_dvs2_rst { - pins = "gpio_pwrctrl2"; - function = "pin_fun3"; - }; - - rk806_dvs2_dvs: rk806_dvs2_dvs { - pins = "gpio_pwrctrl2"; - function = "pin_fun4"; - }; - - rk806_dvs2_gpio: rk806_dvs2_gpio { - pins = "gpio_pwrctrl2"; - function = "pin_fun5"; - }; - - rk806_dvs3_null: rk806_dvs3_null { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - rk806_dvs3_slp: rk806_dvs3_slp { - pins = "gpio_pwrctrl3"; - function = "pin_fun1"; - }; - - rk806_dvs3_pwrdn: rk806_dvs3_pwrdn { - pins = "gpio_pwrctrl3"; - function = "pin_fun2"; - }; - - rk806_dvs3_rst: rk806_dvs3_rst { - pins = "gpio_pwrctrl3"; - function = "pin_fun3"; - }; - - rk806_dvs3_dvs: rk806_dvs3_dvs { - pins = "gpio_pwrctrl3"; - function = "pin_fun4"; - }; - - rk806_dvs3_gpio: rk806_dvs3_gpio { - pins = "gpio_pwrctrl3"; - function = "pin_fun5"; - }; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: DCDC_REG1 { - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-enable-ramp-delay = <400>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-init-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: DCDC_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <900000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: DCDC_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: DCDC_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-name = "vdd_2v0_pldo_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: DCDC_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_3v3_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vddq_ddr_s0: DCDC_REG9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: DCDC_REG10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_1v8_s0: PLDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s0"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - avcc_1v8_s0: PLDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "avcc_1v8_s0"; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: PLDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "avdd_1v2_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avcc_3v3_s0: PLDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc_3v3_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: PLDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: PLDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: NLDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - avdd_ddr_pll_s0: NLDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "avdd_ddr_pll_s0"; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: NLDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "avdd_0v75_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd_0v85_s0: NLDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "avdd_0v85_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2c7 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c7m0_xfer>; - status = "okay"; - - es8388: es8388@11 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "everest,es8388", "everest,es8323"; - reg = <0x11>; - clocks = <&mclkout_i2s0>; - clock-names = "mclk"; - assigned-clocks = <&mclkout_i2s0>; - assigned-clock-rates = <12288000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk>; - }; -}; - -&i2s0_8ch { - status = "okay"; - rockchip,clk-trcm = <1>; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; -}; - -&saradc { - status = "okay"; - vref-supply = <&avcc_1v8_s0>; -}; - -&tsadc { - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - max-frequency = <200000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - full-pwr-cycle-in-suspend; - status = "okay"; -}; - -&sdmmc { - max-frequency = <200000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_sd_s3>; - vqmmc-supply = <&vccio_sd_s0>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; - status = "okay"; -}; - -&iep { - status = "okay"; -}; - -&iep_mmu { - status = "okay"; -}; - -&jpegd { - status = "okay"; -}; - -&jpegd_mmu { - status = "okay"; -}; - -&jpege_ccu { - status = "okay"; -}; - -&jpege0 { - status = "okay"; -}; - -&jpege0_mmu { - status = "okay"; -}; - -&jpege1 { - status = "okay"; -}; - -&jpege1_mmu { - status = "okay"; -}; - -&jpege2 { - status = "okay"; -}; - -&jpege2_mmu { - status = "okay"; -}; - -&jpege3 { - status = "okay"; -}; - -&jpege3_mmu { - status = "okay"; -}; - -&mpp_srv { - status = "okay"; -}; - -&pwm0 { - pinctrl-0 = <&pwm0m2_pins>; - status = "okay"; -}; - -&pwm2 { - pinctrl-0 = <&pwm2m0_pins>; - status = "okay"; -}; - -&pwm6 { - pinctrl-0 = <&pwm6m0_pins>; - status = "okay"; -}; - -&pwm7 { - compatible = "rockchip,remotectl-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm7m0_pins>; - remote_pwm_id = <3>; - handle_cpu_id = <1>; - remote_support_psci = <0>; - status = "okay"; - - ir_key_lubancat{ - rockchip,usercode = <0xff00>; - rockchip,key_table = - <0xba KEY_POWER>, //电源按键 - <0xb8 KEY_MENU>, //菜单按键 - <0xbc KEY_BACK>, //返回按键 - <0xbb KEY_HOME>, //home键按键 - <0xea KEY_PLAY>, //播放按键 - <0xbf KEY_VOLUMEUP>, //音量加按键 - <0xe6 KEY_VOLUMEDOWN>, //音量键按键 - <0xf6 KEY_FASTFORWARD>, //快进按键 - <0xf8 KEY_FASTREVERSE>, //快退按键 - <0xf2 KEY_BACKSPACE>, //BaskSpace按键 - <0xf3 KEY_1>, //按键1 - <0xe7 KEY_2>, - <0xa1 KEY_3>, - <0xf7 KEY_4>, - <0xe3 KEY_5>, - <0xa5 KEY_6>, - <0xbd KEY_7>, - <0xad KEY_8>, - <0xb5 KEY_9>, - <0xe9 KEY_0>; //按键0 - }; - - ir_key2 { - rockchip,usercode = <0xf708>; - rockchip,key_table = - <0x28 KEY_POWER>, - <0xfe KEY_SETUP>, - <0xa4 KEY_MUTE>, - <0x6d KEY_UP>, - <0x68 KEY_LEFT>, - <0x64 KEY_ENTER>, - <0x60 KEY_RIGHT>, - <0x27 KEY_DOWN>, - <0x3c KEY_MENU>, - <0x7d KEY_HOME>, - <0x2b KEY_BACK>, - <0x7c KEY_VOLUMEDOWN>, - <0x79 KEY_VOLUMEUP>, - <0x57 KEY_AUDIO>, - <0x5d KEY_SUBTITLE>, - <0x99 KEY_PHONE>, - <0xfd KEY_WWW>, - <0xfc KEY_F1>, - <0x7e KEY_TV>; - }; - - ir_key3 { - rockchip,usercode = <0x1dcc>; - rockchip,key_table = - <0xee KEY_REPLY>, - <0xf0 KEY_BACK>, - <0xf8 KEY_UP>, - <0xbb KEY_DOWN>, - <0xef KEY_LEFT>, - <0xed KEY_RIGHT>, - <0xfc KEY_HOME>, - <0xf1 KEY_VOLUMEUP>, - <0xfd KEY_VOLUMEDOWN>, - <0xb7 KEY_SEARCH>, - <0xff KEY_POWER>, - <0xf3 KEY_MUTE>, - <0xbf KEY_MENU>, - <0xf9 0x191>, - <0xf5 0x192>, - <0xb3 388>, - <0xbe KEY_1>, - <0xba KEY_2>, - <0xb2 KEY_3>, - <0xbd KEY_4>, - <0xf9 KEY_5>, - <0xb1 KEY_6>, - <0xfc KEY_7>, - <0xf8 KEY_8>, - <0xb0 KEY_9>, - <0xb6 KEY_0>, - <0xb5 KEY_BACKSPACE>; - }; -}; - -&rga3_core0 { - status = "okay"; -}; - -&rga3_0_mmu { - status = "okay"; -}; - -&rga3_core1 { - status = "okay"; -}; - -&rga3_1_mmu { - status = "okay"; -}; - -&rga2 { - status = "okay"; -}; - -&rknpu { - rknpu-supply = <&vdd_npu_s0>; - mem-supply = <&vdd_npu_mem_s0>; - status = "okay"; -}; - -&rknpu_mmu { - status = "okay"; -}; - -&rkvdec_ccu { - status = "okay"; -}; - -&rkvdec0 { - status = "okay"; -}; - -&rkvdec0_mmu { - status = "okay"; -}; - -&rkvdec1 { - status = "okay"; -}; - -&rkvdec1_mmu { - status = "okay"; -}; - -&rkvenc_ccu { - status = "okay"; -}; - -&rkvenc0 { - status = "okay"; -}; - -&rkvenc0_mmu { - status = "okay"; -}; - -&rkvenc1 { - status = "okay"; -}; - -&rkvenc1_mmu { - status = "okay"; -}; - -/* this is a watchdog */ -&wdt { - status = "okay"; -}; - -&gmac1 { - /* Use rgmii-rxid mode to disable rx delay inside Soc */ - phy-mode = "rgmii-rxid"; - clock_in_out = "output"; - - snps,reset-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac1_miim - &gmac1_tx_bus2 - &gmac1_rx_bus2 - &gmac1_rgmii_clk - &gmac1_rgmii_bus>; - - tx_delay = <0x1b>; - /* rx_delay = <0x00>; */ - - phy-handle = <&rgmii_phy1>; - status = "okay"; -}; - -&mdio1 { - rgmii_phy1: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - jl2xxx,led-enable = <(JL2XXX_LED_STATIC_OP_EN | JL1XXX_LED_MODE_EN)>; - jl2xxx,led-mode = <(JL2XXX_LED1_LINK10 | \ - JL2XXX_LED1_LINK100 | \ - JL2XXX_LED1_LINK1000 | \ - JL2XXX_LED2_LINK10 | \ - JL2XXX_LED2_LINK100 | \ - JL2XXX_LED2_LINK1000 | \ - JL2XXX_LED2_ACTIVITY )>; //JL PHY - realtek,led-data = <0x6d60>; //8211F phy - }; -}; - -/* SATA30_HOST0/PCIe20x1_2 Combo PHY */ -&combphy0_ps { - status = "okay"; -}; - -&pcie2x1l2 { - reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; - disable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie20>; - status = "okay"; -}; - -/* USB3.1/DP Combo PHY0 */ -&usbdp_phy0 { - orientation-switch; - svid = <0xff01>; - sbu1-dc-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - usbdp_phy0_orientation_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; - }; - - usbdp_phy0_dp_altmode_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&dp_altmode_mux>; - }; - }; -}; - -&usbdp_phy0_u3 { - status = "okay"; -}; - -&usbdp_phy0_dp { - status = "okay"; -}; - -/* USB3.1 OTG0 Controller */ -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - usb-role-switch; - - status = "okay"; - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -/* USB2.0 PHY0 */ -&u2phy0 { - status = "okay"; -}; - -&u2phy0_otg { - rockchip,typec-vbus-det; - status = "okay"; -}; - -/* USB30_HOST2/SATA30_HOST2/PCIe20x1_1 Combo PHY */ -&combphy2_psu { - status = "okay"; -}; - -/* USB3.1 HOST2 Controller */ -&usbhost3_0 { - status = "okay"; -}; - -&usbhost_dwc3_0 { - dr_mode = "host"; - status = "okay"; -}; - -/* USB2.0 HOST0 PHY2 */ -&u2phy2 { - status = "okay"; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_usb30_host>; - status = "okay"; -}; - -/* USB2.0 HOST0 Controller */ -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -/* USB2.0 HOST1 PHY3 */ -&u2phy3 { - status = "okay"; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_usb20_host>; - status = "okay"; -}; - -/* USB2.0 HOST1 Controller */ -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&vdpu { - status = "okay"; -}; - -&vdpu_mmu { - status = "okay"; -}; - -&vepu { - status = "okay"; -}; - -&vop { - status = "okay"; - // disable-win-move; -}; - -&vop_mmu { - status = "okay"; -}; - -/* vp0 & vp1 splice for 8K output */ -&vp0 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; - rockchip,primary-plane = ; - // cursor-win-id = ; -}; - -&vp1 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; - rockchip,primary-plane = ; - cursor-win-id = ; -}; - -&vp2 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; - rockchip,primary-plane = ; - cursor-win-id = ; -}; - -&vp3 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; - rockchip,primary-plane = ; - cursor-win-id = ; -}; - -&display_subsystem { - clocks = <&hdptxphy_hdmi_clk0>; - clock-names = "hdmi0_phy_pll"; -}; - -&hdptxphy_hdmi_clk0 { - status = "okay"; -}; - -&pinctrl { - dsi { - dsi0_reset: dsi0-reset { - rockchip,pins = <0 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - tp1_irq: tp1-irq { - rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - headphone { - hp_det: hp-det { - rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { - fusb302_int: fusb302-int { - rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - typec_vbus_en: typec-vbus-en { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - usb30_host_pwr_en: usb30-host-pwr-en { - rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usb20_host_pwr_en: usb20-host-pwr-en { - rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - sys_led_pin: sys-led-pin { - rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-cam0.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-cam0.dtsi deleted file mode 100644 index 62ac0c17d..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-cam0.dtsi +++ /dev/null @@ -1,77 +0,0 @@ -/* Link path: - * sensor->csi2_dcphy0->mipi0_csi2->rkcif_mipi_lvds->rkcif_mipi_lvds_sditf->rkisp0_vir0 - */ - -&i2c2 { - status = "okay"; -}; - -/* 对焦马达 可选 */ -&dcphy0_dw9714 { - status = "disabled"; -}; - -/* 摄像头 只能开启一个 */ -&dcphy0_ov5647 { - status = "disabled"; -}; - -&dcphy0_ov5648 { - status = "disabled"; -}; - -&dcphy0_ov8858 { - status = "disabled"; -}; - -&dcphy0_ov13850 { - status = "disabled"; -}; - -&dcphy0_imx415 { - status = "okay"; -}; - -&dcphy0_gc2093 { - status = "disabled"; -}; - -&mipi_dcphy0 { - status = "okay"; -}; - -&csi2_dcphy0 { - status = "okay"; -}; - -&mipi0_csi2 { - status = "okay"; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds { - status = "okay"; -}; - -&rkcif_mipi_lvds_sditf { - status = "okay"; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp0 { - status = "okay"; -}; - -&isp0_mmu { - status = "okay"; -}; - -&rkisp0_vir0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-cam1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-cam1.dtsi deleted file mode 100644 index d43f1c453..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-cam1.dtsi +++ /dev/null @@ -1,77 +0,0 @@ -/* Link path: - * sensor->csi2_dcphy1->mipi1_csi2->rkcif_mipi_lvds1->rkcif_mipi_lvds1_sditf->rkisp0_vir1 - */ - -&i2c5 { - status = "okay"; -}; - -/* 对焦马达 可选 */ -&dcphy1_dw9714 { - status = "disabled"; -}; - -/* 摄像头 只能开启一个 */ -&dcphy1_ov5647 { - status = "disabled"; -}; - -&dcphy1_ov5648 { - status = "disabled"; -}; - -&dcphy1_ov8858 { - status = "disabled"; -}; - -&dcphy1_ov13850 { - status = "disabled"; -}; - -&dcphy1_imx415 { - status = "okay"; -}; - -&dcphy1_gc2093 { - status = "disabled"; -}; - -&csi2_dcphy1 { - status = "okay"; -}; - -&mipi1_csi2 { - status = "okay"; -}; - -&mipi_dcphy1 { - status = "okay"; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds1 { - status = "okay"; -}; - -&rkcif_mipi_lvds1_sditf { - status = "okay"; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp0 { - status = "okay"; -}; - -&isp0_mmu { - status = "okay"; -}; - -&rkisp0_vir1 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-cam2.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-cam2.dtsi deleted file mode 100644 index b1bc36e01..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-cam2.dtsi +++ /dev/null @@ -1,77 +0,0 @@ -/* Link path: - * sensor->csi2_dphy1->mipi2_csi2->rkcif_mipi_lvds2->rkcif_mipi_lvds2_sditf->rkisp0_vir2 - */ - -&i2c1 { - status = "okay"; -}; - -/* 对焦马达 可选 */ -&dphy1_dw9714 { - status = "okay"; -}; - -/* 摄像头 只能开启一个 */ -&dphy1_ov5647 { - status = "disabled"; -}; - -&dphy1_ov5648 { - status = "disabled"; -}; - -&dphy1_ov8858 { - status = "disabled"; -}; - -&dphy1_ov13850 { - status = "disabled"; -}; - -&dphy1_imx415 { - status = "okay"; -}; - -&dphy1_gc2093 { - status = "disabled"; -}; - -&csi2_dphy0_hw { - status = "okay"; -}; - -&csi2_dphy1 { - status = "okay"; -}; - -&mipi2_csi2 { - status = "okay"; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds2 { - status = "okay"; -}; - -&rkcif_mipi_lvds2_sditf { - status = "okay"; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp0 { - status = "okay"; -}; - -&isp0_mmu { - status = "okay"; -}; - -&rkisp0_vir2 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-cam3.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-cam3.dtsi deleted file mode 100644 index b3d96a47b..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-cam3.dtsi +++ /dev/null @@ -1,77 +0,0 @@ -/* Link path: - * sensor->csi2_dphy2->mipi3_csi2->rkcif_mipi_lvds3->rkcif_mipi_lvds3_sditf->rkisp1_vir0 - */ - -&i2c8 { - status = "okay"; -}; - -/* 对焦马达 可选 */ -&dphy2_dw9714 { - status = "disabled"; -}; - -/* 摄像头 只能开启一个 */ -&dphy2_ov5647 { - status = "disabled"; -}; - -&dphy2_ov5648 { - status = "disabled"; -}; - -&dphy2_ov8858 { - status = "disabled"; -}; - -&dphy2_ov13850 { - status = "disabled"; -}; - -&dphy2_imx415 { - status = "okay"; -}; - -&dphy2_gc2093 { - status = "disabled"; -}; - -&csi2_dphy0_hw { - status = "okay"; -}; - -&csi2_dphy2 { - status = "okay"; -}; - -&mipi3_csi2 { - status = "okay"; -}; - -&rkcif { - status = "okay"; -}; - -&rkcif_mipi_lvds3 { - status = "okay"; -}; - -&rkcif_mipi_lvds3_sditf { - status = "okay"; -}; - -&rkcif_mmu { - status = "okay"; -}; - -&rkisp1 { - status = "okay"; -}; - -&isp1_mmu { - status = "okay"; -}; - -&rkisp1_vir0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-csi.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-csi.dtsi deleted file mode 100644 index 6e7478117..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-csi.dtsi +++ /dev/null @@ -1,1280 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Rockchip Electronics Co., Ltd. - * - */ - -#include "rk3588-lubancat-cam.dtsi" - -/* CAM0 */ -&i2c2 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2m4_xfer>; - - dcphy0_dw9714: dcphy0-dw9714@c { - status = "disabled"; - compatible = "dongwoon,dw9714"; - reg = <0xc>; - rockchip,camera-module-index = <0>; - rockchip,vcm-max-current = <100>; - rockchip,vcm-start-current = <0>; - rockchip,vcm-rated-current = <100>; - rockchip,vcm-step-mode = <0xd>; - rockchip,vcm-dlc-enable = <0>; - rockchip,vcm-mclk = <0>; - rockchip,vcm-t-src = <0>; - rockchip,camera-module-facing = "back"; - }; - - dcphy0_ov5647: dcphy0-ov5647@36 { - compatible = "ovti,ov5647"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_25m_clk>; - clock-names = "ext_cam_25m_clk"; - pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_LOW>; - lens-focus = <&dcphy0_dw9714>; - - port { - ov5647_dcphy0_out: endpoint { - remote-endpoint = <&dcphy0_in_ov5647>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy0_ov5648: dcphy0-ov5648@36 { - compatible = "ovti,ov5648"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>; - rotation = <180>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "THDS11073"; - rockchip,camera-module-lens-name = "Largan-40122a1"; - lens-focus = <&dcphy0_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov5648_dcphy0_out: endpoint { - remote-endpoint = <&dcphy0_in_ov5648>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy0_ov8858: dcphy0-ov8858@36 { - compatible = "ovti,ov8858"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - rotation = <180>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "HS5885-BNSM1018-V01"; - rockchip,camera-module-lens-name = "default"; - lens-focus = <&dcphy0_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov8858_dcphy0_out: endpoint { - remote-endpoint = <&dcphy0_in_ov8858>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy0_ov13850: dcphy0-ov13850@10 { - compatible = "ovti,ov13850"; - status = "disabled"; - reg = <0x10>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; - rotation = <180>; - - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "ZC-OV13850R2A-V1"; - rockchip,camera-module-lens-name = "Largan-50064B31"; - lens-focus = <&dcphy0_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov13850_dcphy0_out: endpoint { - remote-endpoint = <&dcphy0_in_ov13850>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy0_imx415: dcphy0-imx415@1a { - compatible = "sony,imx415"; - status = "disabled"; - reg = <0x1a>; - clocks = <&ext_cam_37m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - avdd-supply = <&cam_avdd>; - dovdd-supply = <&cam_dovdd>; - dvdd-supply = <&cam_dvdd>; - pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT2022-PX1"; - rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; - // NO_HDR:0 HDR_X2:5 HDR_X3:6 - // rockchip,camera-hdr-mode = <0>; - port { - imx415_dcphy0_out: endpoint { - remote-endpoint = <&dcphy0_in_imx415>; - data-lanes = <1 2 3 4>; - }; - }; - }; - - dcphy0_gc2093: dcphy0-gc2093@37 { - compatible = "galaxycore,gc2093"; - status = "disabled"; - reg = <0x37>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - //power-domains = <&power RK3588_PD_VI>; - - avdd-supply = <&cam_avdd>; - dovdd-supply = <&cam_dovdd>; - dvdd-supply = <&cam_dvdd>; - pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "front"; - rockchip,camera-module-name = "SIDA209300461"; - rockchip,camera-module-lens-name = "60IRC-F20"; - - // NO_HDR:0 HDR_X2:5 HDR_X3:6 - // rockchip,camera-hdr-mode = <0>; - port { - gc2093_dcphy0_out: endpoint { - remote-endpoint = <&dcphy0_in_gc2093>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -/* CAM1 */ -&i2c5 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5m3_xfer>; - - dcphy1_dw9714: dcphy1-dw9714@c { - status = "disabled"; - compatible = "dongwoon,dw9714"; - reg = <0xc>; - rockchip,camera-module-index = <1>; - rockchip,vcm-max-current = <100>; - rockchip,vcm-start-current = <0>; - rockchip,vcm-rated-current = <100>; - rockchip,vcm-step-mode = <0xd>; - rockchip,vcm-dlc-enable = <0>; - rockchip,vcm-mclk = <0>; - rockchip,vcm-t-src = <0>; - rockchip,camera-module-facing = "back"; - }; - - dcphy1_ov5647: dcphy1-ov5647@36 { - compatible = "ovti,ov5647"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_25m_clk>; - clock-names = "ext_cam_25m_clk"; - pwdn-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; - lens-focus = <&dcphy1_dw9714>; - - port { - ov5647_dcphy1_out: endpoint { - remote-endpoint = <&dcphy1_in_ov5647>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy1_ov5648: dcphy1-ov5648@36 { - compatible = "ovti,ov5648"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; - rotation = <180>; - - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "THDS11073"; - rockchip,camera-module-lens-name = "Largan-40122a1"; - lens-focus = <&dcphy1_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov5648_dcphy1_out: endpoint { - remote-endpoint = <&dcphy1_in_ov5648>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy1_ov8858: dcphy1-ov8858@36 { - compatible = "ovti,ov8858"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; - rotation = <180>; - - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "HS5885-BNSM1018-V01"; - rockchip,camera-module-lens-name = "default"; - lens-focus = <&dcphy1_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov8858_dcphy1_out: endpoint { - remote-endpoint = <&dcphy1_in_ov8858>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy1_ov13850: dcphy1-ov13850@10 { - compatible = "ovti,ov13850"; - status = "disabled"; - reg = <0x10>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; - rotation = <180>; - - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "ZC-OV13850R2A-V1"; - rockchip,camera-module-lens-name = "Largan-50064B31"; - lens-focus = <&dcphy1_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov13850_dcphy1_out: endpoint { - remote-endpoint = <&dcphy1_in_ov13850>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dcphy1_imx415: dcphy1-imx415@1a { - compatible = "sony,imx415"; - status = "disabled"; - reg = <0x1a>; - clocks = <&ext_cam_37m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - avdd-supply = <&cam_avdd>; - dovdd-supply = <&cam_dovdd>; - dvdd-supply = <&cam_dvdd>; - pwdn-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <1>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT2022-PX1"; - rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; - port { - imx415_dcphy1_out: endpoint { - remote-endpoint = <&dcphy1_in_imx415>; - data-lanes = <1 2 3 4>; - }; - }; - }; - - dcphy1_gc2093: dcphy1-gc2093@37 { - compatible = "galaxycore,gc2093"; - status = "disabled"; - reg = <0x37>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - //power-domains = <&power RK3588_PD_VI>; - - avdd-supply = <&cam_avdd>; - dovdd-supply = <&cam_dovdd>; - dvdd-supply = <&cam_dvdd>; - pwdn-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "front"; - rockchip,camera-module-name = "SIDA209300461"; - rockchip,camera-module-lens-name = "60IRC-F20"; - - // NO_HDR:0 HDR_X2:5 HDR_X3:6 - // rockchip,camera-hdr-mode = <0>; - port { - gc2093_dcphy1_out: endpoint { - remote-endpoint = <&dcphy1_in_gc2093>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -/* CAM2 */ -&i2c1 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1m2_xfer>; - - dphy1_dw9714: dphy1-dw9714@c { - status = "disabled"; - compatible = "dongwoon,dw9714"; - reg = <0xc>; - rockchip,camera-module-index = <2>; - rockchip,vcm-max-current = <100>; - rockchip,vcm-start-current = <0>; - rockchip,vcm-rated-current = <100>; - rockchip,vcm-step-mode = <0xd>; - rockchip,vcm-dlc-enable = <0>; - rockchip,vcm-mclk = <0>; - rockchip,vcm-t-src = <0>; - rockchip,camera-module-facing = "back"; - }; - - dphy1_ov5647: dphy1-ov5647@36 { - compatible = "ovti,ov5647"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_25m_clk>; - clock-names = "ext_cam_25m_clk"; - pwdn-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; - lens-focus = <&dphy1_dw9714>; - - port { - ov5647_dphy1_out: endpoint { - remote-endpoint = <&dphy1_in_ov5647>; - data-lanes = <1 2>; - }; - }; - }; - - dphy1_ov5648: dphy1-ov5648@36 { - compatible = "ovti,ov5648"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>; - rotation = <180>; - - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "THDS11073"; - rockchip,camera-module-lens-name = "Largan-40122a1"; - lens-focus = <&dphy1_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov5648_dphy1_out: endpoint { - remote-endpoint = <&dphy1_in_ov5648>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dphy1_ov8858: dphy1-ov8858@36 { - compatible = "ovti,ov8858"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - rotation = <180>; - - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "HS5885-BNSM1018-V01"; - rockchip,camera-module-lens-name = "default"; - lens-focus = <&dphy1_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov8858_dphy1_out: endpoint { - remote-endpoint = <&dphy1_in_ov8858>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dphy1_ov13850: dphy1-ov13850@10 { - compatible = "ovti,ov13850"; - status = "disabled"; - reg = <0x10>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - rotation = <180>; - - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "ZC-OV13850R2A-V1"; - rockchip,camera-module-lens-name = "Largan-50064B31"; - lens-focus = <&dphy1_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov13850_dphy1_out: endpoint { - remote-endpoint = <&dphy1_in_ov13850>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dphy1_imx415: dphy1-imx415@1a { - compatible = "sony,imx415"; - status = "disabled"; - reg = <0x1a>; - clocks = <&ext_cam_37m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - avdd-supply = <&cam_avdd>; - dovdd-supply = <&cam_dovdd>; - dvdd-supply = <&cam_dvdd>; - pwdn-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT2022-PX1"; - rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; - rockchip,imx415-data-lanes = <2>; - // NO_HDR:0 HDR_X2:5 HDR_X3:6 - // rockchip,camera-hdr-mode = <0>; - port { - imx415_dphy1_out: endpoint { - remote-endpoint = <&dphy1_in_imx415>; - data-lanes = <1 2>; - }; - }; - }; - - dphy1_gc2093: dphy1-gc2093@37 { - compatible = "galaxycore,gc2093"; - status = "disabled"; - reg = <0x37>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - //power-domains = <&power RK3588_PD_VI>; - - avdd-supply = <&cam_avdd>; - dovdd-supply = <&cam_dovdd>; - dvdd-supply = <&cam_dvdd>; - pwdn-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "front"; - rockchip,camera-module-name = "SIDA209300461"; - rockchip,camera-module-lens-name = "60IRC-F20"; - - // NO_HDR:0 HDR_X2:5 HDR_X3:6 - // rockchip,camera-hdr-mode = <0>; - port { - gc2093_dphy1_out: endpoint { - remote-endpoint = <&dphy1_in_gc2093>; - data-lanes = <1 2>; - }; - }; - }; -}; - -/* CAM3 */ -&i2c8 { - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c8m2_xfer>; - - dphy2_dw9714: dphy2-dw9714@c { - status = "disabled"; - compatible = "dongwoon,dw9714"; - reg = <0xc>; - rockchip,camera-module-index = <0>; - rockchip,vcm-max-current = <100>; - rockchip,vcm-start-current = <0>; - rockchip,vcm-rated-current = <100>; - rockchip,vcm-step-mode = <0xd>; - rockchip,vcm-dlc-enable = <0>; - rockchip,vcm-mclk = <0>; - rockchip,vcm-t-src = <0>; - rockchip,camera-module-facing = "back"; - }; - - dphy2_ov5647: dphy2-ov5647@36 { - compatible = "ovti,ov5647"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_25m_clk>; - clock-names = "ext_cam_25m_clk"; - pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>; - lens-focus = <&dphy2_dw9714>; - - port { - ov5647_dphy2_out: endpoint { - remote-endpoint = <&dphy2_in_ov5647>; - data-lanes = <1 2>; - }; - }; - }; - - dphy2_ov5648: dphy2-ov5648@36 { - compatible = "ovti,ov5648"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; - rotation = <180>; - - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "THDS11073"; - rockchip,camera-module-lens-name = "Largan-40122a1"; - lens-focus = <&dphy2_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov5648_dphy2_out: endpoint { - remote-endpoint = <&dphy2_in_ov5648>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dphy2_ov8858: dphy2-ov8858@36 { - compatible = "ovti,ov8858"; - status = "disabled"; - reg = <0x36>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; - rotation = <180>; - - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "HS5885-BNSM1018-V01"; - rockchip,camera-module-lens-name = "default"; - lens-focus = <&dphy2_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov8858_dphy2_out: endpoint { - remote-endpoint = <&dphy2_in_ov8858>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dphy2_ov13850: dphy2-ov13850@10 { - compatible = "ovti,ov13850"; - status = "disabled"; - reg = <0x10>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - dovdd-supply= <&cam_dovdd>; /* 1.8v */ - avdd-supply = <&cam_avdd>; /* 2.8v */ - dvdd-supply = <&cam_dvdd>; /* 1.2v */ - pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; - rotation = <180>; - - rockchip,camera-module-index = <2>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "ZC-OV13850R2A-V1"; - rockchip,camera-module-lens-name = "Largan-50064B31"; - lens-focus = <&dphy2_dw9714>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov13850_dphy2_out: endpoint { - remote-endpoint = <&dphy2_in_ov13850>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; - - dphy2_imx415: dphy2-imx415@1a { - compatible = "sony,imx415"; - status = "disabled"; - reg = <0x1a>; - clocks = <&ext_cam_37m_clk>; - clock-names = "xvclk"; - power-domains = <&power RK3588_PD_VI>; - avdd-supply = <&cam_avdd>; - dovdd-supply = <&cam_dovdd>; - dvdd-supply = <&cam_dvdd>; - pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "back"; - rockchip,camera-module-name = "CMK-OT2022-PX1"; - rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; - rockchip,imx415-data-lanes = <2>; - // NO_HDR:0 HDR_X2:5 HDR_X3:6 - // rockchip,camera-hdr-mode = <0>; - port { - imx415_dphy2_out: endpoint { - remote-endpoint = <&dphy2_in_imx415>; - data-lanes = <1 2>; - }; - }; - }; - - dphy2_gc2093: dphy2-gc2093@37 { - compatible = "galaxycore,gc2093"; - status = "disabled"; - reg = <0x37>; - clocks = <&ext_cam_24m_clk>; - clock-names = "xvclk"; - //power-domains = <&power RK3588_PD_VI>; - - avdd-supply = <&cam_avdd>; - dovdd-supply = <&cam_dovdd>; - dvdd-supply = <&cam_dvdd>; - pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; - - rockchip,camera-module-index = <0>; - rockchip,camera-module-facing = "front"; - rockchip,camera-module-name = "SIDA209300461"; - rockchip,camera-module-lens-name = "60IRC-F20"; - - // NO_HDR:0 HDR_X2:5 HDR_X3:6 - // rockchip,camera-hdr-mode = <0>; - port { - gc2093_dphy2_out: endpoint { - remote-endpoint = <&dphy2_in_gc2093>; - data-lanes = <1 2>; - }; - }; - }; -}; - - -&mipi_dcphy0 { - status = "disabled"; -}; - -&csi2_dcphy0 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dcphy0_in_ov5647: endpoint@0 { - reg = <0>; - remote-endpoint = <&ov5647_dcphy0_out>; - data-lanes = <1 2>; - }; - - dcphy0_in_ov5648: endpoint@1 { - reg = <1>; - remote-endpoint = <&ov5648_dcphy0_out>; - data-lanes = <1 2>; - }; - - dcphy0_in_ov8858: endpoint@2 { - reg = <2>; - remote-endpoint = <&ov8858_dcphy0_out>; - data-lanes = <1 2>; - }; - - dcphy0_in_ov13850: endpoint@3 { - reg = <3>; - remote-endpoint = <&ov13850_dcphy0_out>; - data-lanes = <1 2>; - }; - - dcphy0_in_imx415: endpoint@4 { - reg = <4>; - remote-endpoint = <&imx415_dcphy0_out>; - data-lanes = <1 2 3 4>; - }; - - dcphy0_in_gc2093: endpoint@5 { - reg = <5>; - remote-endpoint = <&gc2093_dcphy0_out>; - data-lanes = <1 2 3 4>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidcphy0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi0_csi2_input>; - }; - }; - }; -}; - -&mipi_dcphy1 { - status = "disabled"; -}; - -&csi2_dcphy1 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dcphy1_in_ov5647: endpoint@0 { - reg = <0>; - remote-endpoint = <&ov5647_dcphy1_out>; - data-lanes = <1 2>; - }; - - dcphy1_in_ov5648: endpoint@1 { - reg = <1>; - remote-endpoint = <&ov5648_dcphy1_out>; - data-lanes = <1 2>; - }; - - dcphy1_in_ov8858: endpoint@2 { - reg = <2>; - remote-endpoint = <&ov8858_dcphy1_out>; - data-lanes = <1 2>; - }; - - dcphy1_in_ov13850: endpoint@3 { - reg = <3>; - remote-endpoint = <&ov13850_dcphy1_out>; - data-lanes = <1 2>; - }; - - dcphy1_in_imx415: endpoint@4 { - reg = <4>; - remote-endpoint = <&imx415_dcphy1_out>; - data-lanes = <1 2 3 4>; - }; - - dcphy1_in_gc2093: endpoint@5 { - reg = <5>; - remote-endpoint = <&gc2093_dcphy1_out>; - data-lanes = <1 2 3 4>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidcphy1_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi1_csi2_input>; - }; - }; - }; -}; - -&csi2_dphy0_hw { - status = "okay"; -}; - -&csi2_dphy1 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dphy1_in_ov5647: endpoint@0 { - reg = <0>; - remote-endpoint = <&ov5647_dphy1_out>; - data-lanes = <1 2>; - }; - - dphy1_in_ov5648: endpoint@1 { - reg = <1>; - remote-endpoint = <&ov5648_dphy1_out>; - data-lanes = <1 2>; - }; - - dphy1_in_ov8858: endpoint@2 { - reg = <2>; - remote-endpoint = <&ov8858_dphy1_out>; - data-lanes = <1 2>; - }; - - dphy1_in_ov13850: endpoint@3 { - reg = <3>; - remote-endpoint = <&ov13850_dphy1_out>; - data-lanes = <1 2>; - }; - - dphy1_in_imx415: endpoint@4 { - reg = <4>; - remote-endpoint = <&imx415_dphy1_out>; - data-lanes = <1 2>; - }; - - dphy1_in_gc2093: endpoint@5 { - reg = <5>; - remote-endpoint = <&gc2093_dphy1_out>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy1_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi2_csi2_input>; - }; - }; - }; -}; - -&csi2_dphy2 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dphy2_in_ov5647: endpoint@0 { - reg = <0>; - remote-endpoint = <&ov5647_dphy2_out>; - data-lanes = <1 2>; - }; - - dphy2_in_ov5648: endpoint@1 { - reg = <1>; - remote-endpoint = <&ov5648_dphy2_out>; - data-lanes = <1 2>; - }; - - dphy2_in_ov8858: endpoint@2 { - reg = <2>; - remote-endpoint = <&ov8858_dphy2_out>; - data-lanes = <1 2>; - }; - - dphy2_in_ov13850: endpoint@3 { - reg = <3>; - remote-endpoint = <&ov13850_dphy2_out>; - data-lanes = <1 2>; - }; - - dphy2_in_imx415: endpoint@4 { - reg = <4>; - remote-endpoint = <&imx415_dphy2_out>; - data-lanes = <1 2>; - }; - - dphy2_in_gc2093: endpoint@5 { - reg = <5>; - remote-endpoint = <&gc2093_dphy2_out>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - csidphy2_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi3_csi2_input>; - }; - }; - }; -}; - -&mipi0_csi2 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidcphy0_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi0_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in0>; - }; - }; - }; -}; - -&mipi1_csi2 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi1_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidcphy1_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi1_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in1>; - }; - }; - }; -}; - -&mipi2_csi2 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy1_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi2_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi_in2>; - }; - }; - }; -}; - -&mipi3_csi2 { - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - mipi3_csi2_input: endpoint@1 { - reg = <1>; - remote-endpoint = <&csidphy2_out>; - }; - }; - - port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mipi3_csi2_output: endpoint@0 { - reg = <0>; - remote-endpoint = <&cif_mipi0_in3>; - }; - }; - }; -}; - -&rkcif { - status = "disabled"; -}; - -&rkcif_mmu { - status = "disabled"; -}; - -&rkcif_mipi_lvds { - status = "disabled"; - - port { - cif_mipi_in0: endpoint { - remote-endpoint = <&mipi0_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds_sditf { - status = "disabled"; - - port { - mipi_lvds_sditf: endpoint { - remote-endpoint = <&isp0_vir0>; - }; - }; -}; - -&rkcif_mipi_lvds1 { - status = "disabled"; - - port { - cif_mipi_in1: endpoint { - remote-endpoint = <&mipi1_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds1_sditf { - status = "disabled"; - - port { - mipi_lvds1_sditf: endpoint { - remote-endpoint = <&isp0_vir1>; - }; - }; -}; - -&rkcif_mipi_lvds2 { - status = "disabled"; - - port { - cif_mipi_in2: endpoint { - remote-endpoint = <&mipi2_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds2_sditf { - status = "disabled"; - - port { - mipi_lvds2_sditf: endpoint { - remote-endpoint = <&isp0_vir2>; - }; - }; -}; - -&rkcif_mipi_lvds3 { - status = "disabled"; - - port { - cif_mipi0_in3: endpoint { - remote-endpoint = <&mipi3_csi2_output>; - }; - }; -}; - -&rkcif_mipi_lvds3_sditf { - status = "disabled"; - - port { - mipi_lvds3_sditf: endpoint { - remote-endpoint = <&isp1_vir0>; - }; - }; -}; - -&rkisp0 { - status = "disabled"; -}; - -&isp0_mmu { - status = "disabled"; -}; - -&rkisp0_vir0 { - status = "disabled"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds_sditf>; - }; - }; -}; - -&rkisp0_vir1 { - status = "disabled"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir1: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds1_sditf>; - }; - }; -}; - -&rkisp0_vir2 { - status = "disabled"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp0_vir2: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds2_sditf>; - }; - }; -}; - -&rkisp1 { - status = "disabled"; -}; - -&isp1_mmu { - status = "disabled"; -}; - -&rkisp1_vir0 { - status = "disabled"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - isp1_vir0: endpoint@0 { - reg = <0>; - remote-endpoint = <&mipi_lvds3_sditf>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dp0-vp1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dp0-vp1.dtsi deleted file mode 100644 index 16e5ebc67..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dp0-vp1.dtsi +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * Copyright (c) 2023 EmbedFire - */ - -/ { - dp0_sound: dp0-sound { - status = "okay"; - compatible = "rockchip,hdmi"; - rockchip,card-name = "rockchip-dp0"; - rockchip,mclk-fs = <512>; - rockchip,cpu = <&spdif_tx2>; - rockchip,codec = <&dp0 1>; - rockchip,jack-det; - }; -}; - -&spdif_tx2 { - status = "okay"; -}; - -&dp0 { - status = "okay"; -}; - -&route_dp0 { - status = "okay"; - connect = <&vp1_out_dp0>; -}; - -&dp0_in_vp0 { - status = "disabled"; -}; - -&dp0_in_vp1 { - status = "okay"; -}; - -&dp0_in_vp2 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi0-vp2-1024x600-7inch-ebf410173.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi0-vp2-1024x600-7inch-ebf410173.dtsi deleted file mode 100644 index 05d3db20b..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi0-vp2-1024x600-7inch-ebf410173.dtsi +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -&mipi_dcphy0 { - status = "okay"; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp2_out_dsi0>; -}; - -&dsi0_in_vp2 { - status = "okay"; -}; - -&dsi0 { - status = "okay"; - - dsi0_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight_dsi0>; - power-supply = <&mipi_dsi0_power>; - reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; - - enable-delay-ms = <35>; - prepare-delay-ms = <6>; - reset-delay-ms = <0>; - init-delay-ms = <20>; - unprepare-delay-ms = <0>; - disable-delay-ms = <20>; - - size,width = <74>; - size,height = <133>; - - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - - panel-init-sequence = [ - 15 00 02 80 AC - 15 00 02 81 B8 - 15 00 02 82 09 - 15 00 02 83 78 - 15 00 02 84 7F - 15 00 02 85 BB - 15 00 02 86 70 - 05 C8 01 11 - 05 C8 01 29 - ]; - - panel-exit-sequence = [ - 05 78 01 28 - 05 00 01 10 - ]; - - disp0_timings0: display-timings { - native-mode = <&dsi0_timing0>; - dsi0_timing0: timing0 { - clock-frequency = <51668640>; - hactive = <1024>; - vactive = <600>; - hsync-len = <10>; - hback-porch = <160>; - hfront-porch = <160>; - vsync-len = <1>; - vback-porch = <23>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in_dsi0: endpoint { - remote-endpoint = <&dsi0_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi0_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi0>; - }; - }; - }; -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2m4_xfer>; - - gt911_dsi0: gt911@5d { - status = "okay"; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio3>; - interrupts = ; - reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; - irq-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; - touchscreen-inverted-x = <1>; - touchscreen-inverted-y = <1>; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi0-vp2-1080x1920-5.5inch-ebf410125.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi0-vp2-1080x1920-5.5inch-ebf410125.dtsi deleted file mode 100644 index 592f5e180..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi0-vp2-1080x1920-5.5inch-ebf410125.dtsi +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -&mipi_dcphy0 { - status = "okay"; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp2_out_dsi0>; -}; - -&dsi0_in_vp2 { - status = "okay"; -}; - -&dsi0 { - status = "okay"; - - dsi0_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight_dsi0>; - power-supply = <&mipi_dsi0_power>; - reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; - - enable-delay-ms = <35>; - prepare-delay-ms = <6>; - reset-delay-ms = <10>; - init-delay-ms = <50>; - unprepare-delay-ms = <0>; - disable-delay-ms = <20>; - - size,width = <74>; - size,height = <133>; - - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - - panel-init-sequence = [ - 39 00 04 B9 FF 83 99 - 15 00 02 D2 77 - 39 00 10 B1 02 04 74 94 01 32 33 11 11 AB 4D 56 73 02 02 - 39 00 10 B2 00 80 80 AE 05 07 5A 11 00 00 10 1E 70 03 D4 - 15 00 02 36 02 - 39 00 2D B4 00 FF 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 21 03 01 00 0F B8 8B 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 01 00 0F B8 01 - 39 05 22 D3 00 00 00 00 00 00 06 00 00 10 04 00 04 00 00 00 00 00 00 00 00 00 00 01 00 05 05 07 00 00 00 05 40 - 39 05 21 D5 18 18 19 19 18 18 21 20 01 00 07 06 05 04 03 02 18 18 18 18 18 18 2F 2F 30 30 31 31 18 18 18 18 - 39 05 21 D6 18 18 19 19 40 40 20 21 06 07 00 01 02 03 04 05 40 40 40 40 40 40 2F 2F 30 30 31 31 40 40 40 40 - 39 00 11 D8 A2 AA 02 A0 A2 A8 02 A0 B0 00 00 00 B0 00 00 00 - 15 00 02 BD 01 - 39 00 11 D8 B0 00 00 00 B0 00 00 00 E2 AA 03 F0 E2 AA 03 F0 - 15 00 02 BD 02 - 39 00 09 D8 E2 AA 03 F0 E2 AA 03 F0 - 15 00 02 BD 00 - 39 00 03 B6 8D 8D - 39 05 37 E0 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77 - 05 C8 01 11 - 05 C8 01 29 - ]; - - panel-exit-sequence = [ - 05 78 01 28 - 05 00 01 10 - ]; - - disp0_timings0: display-timings { - native-mode = <&dsi0_timing0>; - dsi0_timing0: timing0 { - clock-frequency = <131376000>; - hactive = <1080>; - vactive = <1920>; - hsync-len = <10>; - hback-porch = <20>; - hfront-porch = <10>; - vsync-len = <5>; - vback-porch = <20>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in_dsi0: endpoint { - remote-endpoint = <&dsi0_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi0_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi0>; - }; - }; - }; -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2m4_xfer>; - - gt911_dsi0: gt911@5d { - status = "okay"; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio3>; - interrupts = ; - reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; - irq-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; - touchscreen-inverted-x = <1>; - touchscreen-inverted-y = <1>; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi0-vp2-800x1280-10.1inch-ebf410177.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi0-vp2-800x1280-10.1inch-ebf410177.dtsi deleted file mode 100644 index 837e93f86..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi0-vp2-800x1280-10.1inch-ebf410177.dtsi +++ /dev/null @@ -1,303 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -&mipi_dcphy0 { - status = "okay"; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp2_out_dsi0>; -}; - -&dsi0_in_vp2 { - status = "okay"; -}; - -&dsi0 { - status = "okay"; - - dsi0_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight_dsi0>; - power-supply = <&mipi_dsi0_power>; - reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; - - enable-delay-ms = <35>; - prepare-delay-ms = <6>; - reset-delay-ms = <0>; - init-delay-ms = <20>; - unprepare-delay-ms = <0>; - disable-delay-ms = <20>; - - size,width = <74>; - size,height = <133>; - - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - - panel-init-sequence = [ - 39 05 04 FF 98 81 03 - 15 05 02 01 00 - 15 05 02 02 00 - 15 05 02 03 53 - 15 05 02 04 D3 - 15 05 02 05 00 - 15 05 02 06 0D - 15 05 02 07 08 - 15 05 02 08 00 - 15 05 02 09 00 - 15 05 02 0a 00 - 15 05 02 0b 00 - 15 05 02 0c 00 - 15 05 02 0d 00 - 15 05 02 0e 00 - 15 05 02 0f 28 - 15 05 02 10 28 - 15 05 02 11 00 - 15 05 02 12 00 - 15 05 02 13 00 - 15 05 02 14 00 - 15 05 02 15 00 - 15 05 02 16 00 - 15 05 02 17 00 - 15 05 02 18 00 - 15 05 02 19 00 - 15 05 02 1a 00 - 15 05 02 1b 00 - 15 05 02 1d 00 - 15 05 02 1e 40 - 15 05 02 1f 80 - 15 05 02 20 06 - 15 05 02 21 01 - 15 05 02 22 00 - 15 05 02 23 00 - 15 05 02 24 00 - 15 05 02 25 00 - 15 05 02 26 00 - 15 05 02 27 00 - 15 05 02 28 33 - 15 05 02 29 33 - 15 05 02 2a 00 - 15 05 02 2b 00 - 15 05 02 2c 00 - 15 05 02 2d 00 - 15 05 02 2e 00 - 15 05 02 2f 00 - 15 05 02 30 00 - 15 05 02 31 00 - 15 05 02 32 00 - 15 05 02 33 00 - 15 05 02 34 03 - 15 05 02 35 00 - 15 05 02 36 00 - 15 05 02 37 00 - 15 05 02 38 96 - 15 05 02 39 00 - 15 05 02 3a 00 - 15 05 02 3b 00 - 15 05 02 3c 00 - 15 05 02 3d 00 - 15 05 02 3e 00 - 15 05 02 3f 00 - 15 05 02 40 00 - 15 05 02 41 00 - 15 05 02 42 00 - 15 05 02 43 00 - 15 05 02 44 00 - 15 05 02 50 00 - 15 05 02 51 23 - 15 05 02 52 45 - 15 05 02 53 67 - 15 05 02 54 89 - 15 05 02 55 AB - 15 05 02 56 01 - 15 05 02 57 23 - 15 05 02 58 45 - 15 05 02 59 67 - 15 05 02 5a 89 - 15 05 02 5b AB - 15 05 02 5c CD - 15 05 02 5d EF - 15 05 02 5e 00 - 15 05 02 5f 08 - 15 05 02 60 08 - 15 05 02 61 06 - 15 05 02 62 06 - 15 05 02 63 01 - 15 05 02 64 01 - 15 05 02 65 00 - 15 05 02 66 00 - 15 05 02 67 02 - 15 05 02 68 15 - 15 05 02 69 15 - 15 05 02 6a 14 - 15 05 02 6b 14 - 15 05 02 6c 0D - 15 05 02 6d 0D - 15 05 02 6e 0C - 15 05 02 6f 0C - 15 05 02 70 0F - 15 05 02 71 0F - 15 05 02 72 0E - 15 05 02 73 0E - 15 05 02 74 02 - 15 05 02 75 08 - 15 05 02 76 08 - 15 05 02 77 06 - 15 05 02 78 06 - 15 05 02 79 01 - 15 05 02 7a 01 - 15 05 02 7b 00 - 15 05 02 7c 00 - 15 05 02 7d 02 - 15 05 02 7e 15 - 15 05 02 7f 15 - 15 05 02 80 14 - 15 05 02 81 14 - 15 05 02 82 0D - 15 05 02 83 0D - 15 05 02 84 0C - 15 05 02 85 0C - 15 05 02 86 0F - 15 05 02 87 0F - 15 05 02 88 0E - 15 05 02 89 0E - 15 05 02 8A 02 - 39 05 04 FF 98 81 04 - 15 05 02 6E 2B - 15 05 02 6F 37 - 15 05 02 3A 24 - 15 05 02 8D 1A - 15 05 02 87 BA - 15 05 02 B2 D1 - 15 05 02 88 0B - 15 05 02 38 01 - 15 05 02 39 00 - 15 05 02 B5 02 - 15 05 02 31 25 - 15 05 02 3B 98 - 39 05 04 FF 98 81 01 - 15 05 02 22 0A - 15 05 02 31 00 - 15 05 02 53 3D - 15 05 02 55 3D - 15 05 02 50 B5 - 15 05 02 51 AD - 15 05 02 60 06 - 15 05 02 62 20 - 15 05 02 A0 00 - 15 05 02 A1 21 - 15 05 02 A2 35 - 15 05 02 A3 19 - 15 05 02 A4 1E - 15 05 02 A5 33 - 15 05 02 A6 27 - 15 05 02 A7 26 - 15 05 02 A8 AF - 15 05 02 A9 1B - 15 05 02 AA 27 - 15 05 02 AB 8D - 15 05 02 AC 1A - 15 05 02 AD 1B - 15 05 02 AE 50 - 15 05 02 AF 26 - 15 05 02 B0 2B - 15 05 02 B1 54 - 15 05 02 B2 5E - 15 05 02 B3 23 - 15 05 02 C0 00 - 15 05 02 C1 21 - 15 05 02 C2 35 - 15 05 02 C3 19 - 15 05 02 C4 1E - 15 05 02 C5 33 - 15 05 02 C6 27 - 15 05 02 C7 26 - 15 05 02 C8 AF - 15 05 02 C9 1B - 15 05 02 CA 27 - 15 05 02 CB 8D - 15 05 02 CC 1A - 15 05 02 CD 1B - 15 05 02 CE 50 - 15 05 02 CF 26 - 15 05 02 D0 2B - 15 05 02 D1 54 - 15 05 02 D2 5E - 15 05 02 D3 23 - 39 05 04 FF 98 81 00 - 15 78 02 11 00 - 15 05 02 29 00 - ]; - - panel-exit-sequence = [ - 05 78 01 28 - 05 00 01 10 - ]; - - disp0_timings0: display-timings { - native-mode = <&dsi0_timing0>; - dsi0_timing0: timing0 { - clock-frequency = <67000000>; - hactive = <800>; - vactive = <1280>; - hsync-len = <24>; - hback-porch = <24>; - hfront-porch = <12>; - vsync-len = <2>; - vback-porch = <9>; - vfront-porch = <7>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in_dsi0: endpoint { - remote-endpoint = <&dsi0_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi0_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi0>; - }; - }; - }; -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2m4_xfer>; - - gt911_dsi0: gt911@5d { - status = "okay"; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio3>; - interrupts = ; - reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; - irq-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi0-vp2-800x1280-10.1inch-s8001280b1060b.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi0-vp2-800x1280-10.1inch-s8001280b1060b.dtsi deleted file mode 100644 index d3f3d0c00..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi0-vp2-800x1280-10.1inch-s8001280b1060b.dtsi +++ /dev/null @@ -1,310 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -&mipi_dcphy0 { - status = "okay"; -}; - -&route_dsi0 { - status = "okay"; - connect = <&vp2_out_dsi0>; -}; - -&dsi0_in_vp2 { - status = "okay"; -}; - -&dsi0 { - status = "okay"; - - dsi0_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight_dsi0>; - power-supply = <&mipi_dsi0_power>; - reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; - - enable-delay-ms = <35>; - prepare-delay-ms = <6>; - reset-delay-ms = <0>; - init-delay-ms = <20>; - unprepare-delay-ms = <0>; - disable-delay-ms = <20>; - - size,width = <74>; - size,height = <133>; - - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - - panel-init-sequence = [ - 15 00 02 E0 00 - 15 00 02 E1 93 - 15 00 02 E2 65 - 15 00 02 E3 F8 - 15 00 02 80 03 - 15 00 02 E0 01 - 15 00 02 00 00 - 15 00 02 01 3B - 15 00 02 0C 74 - 15 00 02 17 00 - 15 00 02 18 AF - 15 00 02 19 00 - 15 00 02 1A 00 - 15 00 02 1B AF - 15 00 02 1C 00 - 15 00 02 35 26 - 15 00 02 37 09 - 15 00 02 38 04 - 15 00 02 39 00 - 15 00 02 3A 01 - 15 00 02 3C 78 - 15 00 02 3D FF - 15 00 02 3E FF - 15 00 02 3F 7F - 15 00 02 40 06 - 15 00 02 41 A0 - 15 00 02 42 81 - 15 00 02 43 1E - 15 00 02 44 0B - 15 00 02 45 28 - 15 00 02 55 02 - 15 00 02 57 69 - 15 00 02 59 0A - 15 00 02 5A 2A - 15 00 02 5B 17 - 15 00 02 5D 7F - 15 00 02 5E 6B - 15 00 02 5F 5C - 15 00 02 60 4F - 15 00 02 61 4D - 15 00 02 62 3F - 15 00 02 63 42 - 15 00 02 64 2B - 15 00 02 65 44 - 15 00 02 66 43 - 15 00 02 67 43 - 15 00 02 68 63 - 15 00 02 69 52 - 15 00 02 6A 5A - 15 00 02 6B 4F - 15 00 02 6C 4E - 15 00 02 6D 20 - 15 00 02 6E 0F - 15 00 02 6F 00 - 15 00 02 70 7F - 15 00 02 71 6B - 15 00 02 72 5C - 15 00 02 73 4F - 15 00 02 74 4D - 15 00 02 75 3F - 15 00 02 76 42 - 15 00 02 77 2B - 15 00 02 78 44 - 15 00 02 79 43 - 15 00 02 7A 43 - 15 00 02 7B 63 - 15 00 02 7C 52 - 15 00 02 7D 5A - 15 00 02 7E 4F - 15 00 02 7F 4E - 15 00 02 80 20 - 15 00 02 81 0F - 15 00 02 82 00 - 15 00 02 E0 02 - 15 00 02 00 42 - 15 00 02 01 42 - 15 00 02 02 40 - 15 00 02 03 40 - 15 00 02 04 5E - 15 00 02 05 5E - 15 00 02 06 5F - 15 00 02 07 5F - 15 00 02 08 5F - 15 00 02 09 57 - 15 00 02 0A 57 - 15 00 02 0B 77 - 15 00 02 0C 77 - 15 00 02 0D 47 - 15 00 02 0E 47 - 15 00 02 0F 45 - 15 00 02 10 45 - 15 00 02 11 4B - 15 00 02 12 4B - 15 00 02 13 49 - 15 00 02 14 49 - 15 00 02 15 5F - 15 00 02 16 41 - 15 00 02 17 41 - 15 00 02 18 40 - 15 00 02 19 40 - 15 00 02 1A 5E - 15 00 02 1B 5E - 15 00 02 1C 5F - 15 00 02 1D 5F - 15 00 02 1E 5F - 15 00 02 1F 57 - 15 00 02 20 57 - 15 00 02 21 77 - 15 00 02 22 77 - 15 00 02 23 46 - 15 00 02 24 46 - 15 00 02 25 44 - 15 00 02 26 44 - 15 00 02 27 4A - 15 00 02 28 4A - 15 00 02 29 48 - 15 00 02 2A 48 - 15 00 02 2B 5F - 15 00 02 2C 01 - 15 00 02 2D 01 - 15 00 02 2E 00 - 15 00 02 2F 00 - 15 00 02 30 1F - 15 00 02 31 1F - 15 00 02 32 1E - 15 00 02 33 1E - 15 00 02 34 1F - 15 00 02 35 17 - 15 00 02 36 17 - 15 00 02 37 37 - 15 00 02 38 37 - 15 00 02 39 08 - 15 00 02 3A 08 - 15 00 02 3B 0A - 15 00 02 3C 0A - 15 00 02 3D 04 - 15 00 02 3E 04 - 15 00 02 3F 06 - 15 00 02 40 06 - 15 00 02 41 1F - 15 00 02 42 02 - 15 00 02 43 02 - 15 00 02 44 00 - 15 00 02 45 00 - 15 00 02 46 1F - 15 00 02 47 1F - 15 00 02 48 1E - 15 00 02 49 1E - 15 00 02 4A 1F - 15 00 02 4B 17 - 15 00 02 4C 17 - 15 00 02 4D 37 - 15 00 02 4E 37 - 15 00 02 4F 09 - 15 00 02 50 09 - 15 00 02 51 0B - 15 00 02 52 0B - 15 00 02 53 05 - 15 00 02 54 05 - 15 00 02 55 07 - 15 00 02 56 07 - 15 00 02 57 1F - 15 00 02 58 40 - 15 00 02 5B 30 - 15 00 02 5C 00 - 15 00 02 5D 34 - 15 00 02 5E 05 - 15 00 02 5F 02 - 15 00 02 63 00 - 15 00 02 64 6A - 15 00 02 67 73 - 15 00 02 68 05 - 15 00 02 69 08 - 15 00 02 6A 6A - 15 00 02 6B 08 - 15 00 02 6C 00 - 15 00 02 6D 00 - 15 00 02 6E 00 - 15 00 02 6F 88 - 15 00 02 75 FF - 15 00 02 77 DD - 15 00 02 78 2A - 15 00 02 79 15 - 15 00 02 7A 17 - 15 00 02 7D 14 - 15 00 02 7E 82 - 15 00 02 E0 04 - 15 00 02 00 0E - 15 00 02 02 B3 - 15 00 02 09 61 - 15 00 02 0E 48 - 15 00 02 E0 00 - 15 00 02 E6 02 - 15 00 02 E7 0C - 15 78 02 11 00 - 15 00 02 E0 00 - 15 05 02 29 00 - ]; - - panel-exit-sequence = [ - 05 78 01 28 - 05 00 01 10 - ]; - - disp0_timings0: display-timings { - native-mode = <&dsi0_timing0>; - dsi0_timing0: timing0 { - clock-frequency = <69801600>; - hactive = <800>; - vactive = <1280>; - hsync-len = <20>; - hback-porch = <20>; - hfront-porch = <40>; - vsync-len = <4>; - vback-porch = <8>; - vfront-porch = <30>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in_dsi0: endpoint { - remote-endpoint = <&dsi0_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi0_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi0>; - }; - }; - }; -}; - -&i2c2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2m4_xfer>; - - gt911_dsi0: gt911@5d { - status = "okay"; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio3>; - interrupts = ; - reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; - irq-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; - touchscreen-inverted-x = <1>; - touchscreen-swapped-x-y = <1>; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi1-vp3-1024x600-7inch-ebf410173.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi1-vp3-1024x600-7inch-ebf410173.dtsi deleted file mode 100644 index 4bb7c282b..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi1-vp3-1024x600-7inch-ebf410173.dtsi +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -&mipi_dcphy1 { - status = "okay"; -}; - -&route_dsi1 { - status = "okay"; - connect = <&vp3_out_dsi1>; -}; - -&dsi1_in_vp3 { - status = "okay"; -}; - -&dsi1 { - status = "okay"; - - dsi1_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight_dsi1>; - power-supply = <&mipi_dsi1_power>; - reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>; - - enable-delay-ms = <35>; - prepare-delay-ms = <6>; - reset-delay-ms = <0>; - init-delay-ms = <20>; - unprepare-delay-ms = <0>; - disable-delay-ms = <20>; - - size,width = <74>; - size,height = <133>; - - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - - panel-init-sequence = [ - 15 00 02 80 AC - 15 00 02 81 B8 - 15 00 02 82 09 - 15 00 02 83 78 - 15 00 02 84 7F - 15 00 02 85 BB - 15 00 02 86 70 - 05 C8 01 11 - 05 C8 01 29 - ]; - - panel-exit-sequence = [ - 05 78 01 28 - 05 00 01 10 - ]; - - disp1_timings0: display-timings { - native-mode = <&dsi1_timing0>; - dsi1_timing0: timing0 { - clock-frequency = <51668640>; - hactive = <1024>; - vactive = <600>; - hsync-len = <10>; - hback-porch = <160>; - hfront-porch = <160>; - vsync-len = <1>; - vback-porch = <23>; - vfront-porch = <12>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in_dsi1: endpoint { - remote-endpoint = <&dsi1_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi1_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi1>; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5m3_xfer>; - - gt911_dsi1: gt911@5d { - status = "okay"; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio3>; - interrupts = ; - reset-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; - irq-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; - touchscreen-inverted-x = <1>; - touchscreen-inverted-y = <1>; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi1-vp3-1080x1920-5.5inch-ebf410125.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi1-vp3-1080x1920-5.5inch-ebf410125.dtsi deleted file mode 100644 index 6a52fedcb..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi1-vp3-1080x1920-5.5inch-ebf410125.dtsi +++ /dev/null @@ -1,132 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -&mipi_dcphy1 { - status = "okay"; -}; - -&route_dsi1 { - status = "okay"; - connect = <&vp3_out_dsi1>; -}; - -&dsi1_in_vp3 { - status = "okay"; -}; - -&dsi1 { - status = "okay"; - - dsi1_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight_dsi1>; - power-supply = <&mipi_dsi1_power>; - reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>; - - enable-delay-ms = <35>; - prepare-delay-ms = <6>; - reset-delay-ms = <10>; - init-delay-ms = <50>; - unprepare-delay-ms = <0>; - disable-delay-ms = <20>; - - size,width = <74>; - size,height = <133>; - - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - - panel-init-sequence = [ - 39 00 04 B9 FF 83 99 - 15 00 02 D2 77 - 39 00 10 B1 02 04 74 94 01 32 33 11 11 AB 4D 56 73 02 02 - 39 00 10 B2 00 80 80 AE 05 07 5A 11 00 00 10 1E 70 03 D4 - 15 00 02 36 02 - 39 00 2D B4 00 FF 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 21 03 01 00 0F B8 8B 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 01 00 0F B8 01 - 39 05 22 D3 00 00 00 00 00 00 06 00 00 10 04 00 04 00 00 00 00 00 00 00 00 00 00 01 00 05 05 07 00 00 00 05 40 - 39 05 21 D5 18 18 19 19 18 18 21 20 01 00 07 06 05 04 03 02 18 18 18 18 18 18 2F 2F 30 30 31 31 18 18 18 18 - 39 05 21 D6 18 18 19 19 40 40 20 21 06 07 00 01 02 03 04 05 40 40 40 40 40 40 2F 2F 30 30 31 31 40 40 40 40 - 39 00 11 D8 A2 AA 02 A0 A2 A8 02 A0 B0 00 00 00 B0 00 00 00 - 15 00 02 BD 01 - 39 00 11 D8 B0 00 00 00 B0 00 00 00 E2 AA 03 F0 E2 AA 03 F0 - 15 00 02 BD 02 - 39 00 09 D8 E2 AA 03 F0 E2 AA 03 F0 - 15 00 02 BD 00 - 39 00 03 B6 8D 8D - 39 05 37 E0 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77 - 05 C8 01 11 - 05 C8 01 29 - ]; - - panel-exit-sequence = [ - 05 78 01 28 - 05 00 01 10 - ]; - - disp1_timings0: display-timings { - native-mode = <&dsi1_timing0>; - dsi1_timing0: timing0 { - clock-frequency = <131376000>; - hactive = <1080>; - vactive = <1920>; - hsync-len = <10>; - hback-porch = <20>; - hfront-porch = <10>; - vsync-len = <5>; - vback-porch = <20>; - vfront-porch = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in_dsi1: endpoint { - remote-endpoint = <&dsi1_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi1_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi1>; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5m3_xfer>; - - gt911_dsi1: gt911@5d { - status = "okay"; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio3>; - interrupts = ; - reset-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; - irq-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; - touchscreen-inverted-x = <1>; - touchscreen-inverted-y = <1>; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi1-vp3-800x1280-10.1inch-ebf410177.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi1-vp3-800x1280-10.1inch-ebf410177.dtsi deleted file mode 100644 index 6784ac03d..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi1-vp3-800x1280-10.1inch-ebf410177.dtsi +++ /dev/null @@ -1,303 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -&mipi_dcphy1 { - status = "okay"; -}; - -&route_dsi1 { - status = "okay"; - connect = <&vp3_out_dsi1>; -}; - -&dsi1_in_vp3 { - status = "okay"; -}; - -&dsi1 { - status = "okay"; - - dsi1_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight_dsi1>; - power-supply = <&mipi_dsi1_power>; - reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>; - - enable-delay-ms = <35>; - prepare-delay-ms = <6>; - reset-delay-ms = <0>; - init-delay-ms = <20>; - unprepare-delay-ms = <0>; - disable-delay-ms = <20>; - - size,width = <74>; - size,height = <133>; - - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - - panel-init-sequence = [ - 39 05 04 FF 98 81 03 - 15 05 02 01 00 - 15 05 02 02 00 - 15 05 02 03 53 - 15 05 02 04 D3 - 15 05 02 05 00 - 15 05 02 06 0D - 15 05 02 07 08 - 15 05 02 08 00 - 15 05 02 09 00 - 15 05 02 0a 00 - 15 05 02 0b 00 - 15 05 02 0c 00 - 15 05 02 0d 00 - 15 05 02 0e 00 - 15 05 02 0f 28 - 15 05 02 10 28 - 15 05 02 11 00 - 15 05 02 12 00 - 15 05 02 13 00 - 15 05 02 14 00 - 15 05 02 15 00 - 15 05 02 16 00 - 15 05 02 17 00 - 15 05 02 18 00 - 15 05 02 19 00 - 15 05 02 1a 00 - 15 05 02 1b 00 - 15 05 02 1d 00 - 15 05 02 1e 40 - 15 05 02 1f 80 - 15 05 02 20 06 - 15 05 02 21 01 - 15 05 02 22 00 - 15 05 02 23 00 - 15 05 02 24 00 - 15 05 02 25 00 - 15 05 02 26 00 - 15 05 02 27 00 - 15 05 02 28 33 - 15 05 02 29 33 - 15 05 02 2a 00 - 15 05 02 2b 00 - 15 05 02 2c 00 - 15 05 02 2d 00 - 15 05 02 2e 00 - 15 05 02 2f 00 - 15 05 02 30 00 - 15 05 02 31 00 - 15 05 02 32 00 - 15 05 02 33 00 - 15 05 02 34 03 - 15 05 02 35 00 - 15 05 02 36 00 - 15 05 02 37 00 - 15 05 02 38 96 - 15 05 02 39 00 - 15 05 02 3a 00 - 15 05 02 3b 00 - 15 05 02 3c 00 - 15 05 02 3d 00 - 15 05 02 3e 00 - 15 05 02 3f 00 - 15 05 02 40 00 - 15 05 02 41 00 - 15 05 02 42 00 - 15 05 02 43 00 - 15 05 02 44 00 - 15 05 02 50 00 - 15 05 02 51 23 - 15 05 02 52 45 - 15 05 02 53 67 - 15 05 02 54 89 - 15 05 02 55 AB - 15 05 02 56 01 - 15 05 02 57 23 - 15 05 02 58 45 - 15 05 02 59 67 - 15 05 02 5a 89 - 15 05 02 5b AB - 15 05 02 5c CD - 15 05 02 5d EF - 15 05 02 5e 00 - 15 05 02 5f 08 - 15 05 02 60 08 - 15 05 02 61 06 - 15 05 02 62 06 - 15 05 02 63 01 - 15 05 02 64 01 - 15 05 02 65 00 - 15 05 02 66 00 - 15 05 02 67 02 - 15 05 02 68 15 - 15 05 02 69 15 - 15 05 02 6a 14 - 15 05 02 6b 14 - 15 05 02 6c 0D - 15 05 02 6d 0D - 15 05 02 6e 0C - 15 05 02 6f 0C - 15 05 02 70 0F - 15 05 02 71 0F - 15 05 02 72 0E - 15 05 02 73 0E - 15 05 02 74 02 - 15 05 02 75 08 - 15 05 02 76 08 - 15 05 02 77 06 - 15 05 02 78 06 - 15 05 02 79 01 - 15 05 02 7a 01 - 15 05 02 7b 00 - 15 05 02 7c 00 - 15 05 02 7d 02 - 15 05 02 7e 15 - 15 05 02 7f 15 - 15 05 02 80 14 - 15 05 02 81 14 - 15 05 02 82 0D - 15 05 02 83 0D - 15 05 02 84 0C - 15 05 02 85 0C - 15 05 02 86 0F - 15 05 02 87 0F - 15 05 02 88 0E - 15 05 02 89 0E - 15 05 02 8A 02 - 39 05 04 FF 98 81 04 - 15 05 02 6E 2B - 15 05 02 6F 37 - 15 05 02 3A 24 - 15 05 02 8D 1A - 15 05 02 87 BA - 15 05 02 B2 D1 - 15 05 02 88 0B - 15 05 02 38 01 - 15 05 02 39 00 - 15 05 02 B5 02 - 15 05 02 31 25 - 15 05 02 3B 98 - 39 05 04 FF 98 81 01 - 15 05 02 22 0A - 15 05 02 31 00 - 15 05 02 53 3D - 15 05 02 55 3D - 15 05 02 50 B5 - 15 05 02 51 AD - 15 05 02 60 06 - 15 05 02 62 20 - 15 05 02 A0 00 - 15 05 02 A1 21 - 15 05 02 A2 35 - 15 05 02 A3 19 - 15 05 02 A4 1E - 15 05 02 A5 33 - 15 05 02 A6 27 - 15 05 02 A7 26 - 15 05 02 A8 AF - 15 05 02 A9 1B - 15 05 02 AA 27 - 15 05 02 AB 8D - 15 05 02 AC 1A - 15 05 02 AD 1B - 15 05 02 AE 50 - 15 05 02 AF 26 - 15 05 02 B0 2B - 15 05 02 B1 54 - 15 05 02 B2 5E - 15 05 02 B3 23 - 15 05 02 C0 00 - 15 05 02 C1 21 - 15 05 02 C2 35 - 15 05 02 C3 19 - 15 05 02 C4 1E - 15 05 02 C5 33 - 15 05 02 C6 27 - 15 05 02 C7 26 - 15 05 02 C8 AF - 15 05 02 C9 1B - 15 05 02 CA 27 - 15 05 02 CB 8D - 15 05 02 CC 1A - 15 05 02 CD 1B - 15 05 02 CE 50 - 15 05 02 CF 26 - 15 05 02 D0 2B - 15 05 02 D1 54 - 15 05 02 D2 5E - 15 05 02 D3 23 - 39 05 04 FF 98 81 00 - 15 78 02 11 00 - 15 05 02 29 00 - ]; - - panel-exit-sequence = [ - 05 78 01 28 - 05 00 01 10 - ]; - - disp1_timings0: display-timings { - native-mode = <&dsi1_timing0>; - dsi1_timing0: timing0 { - clock-frequency = <67000000>; - hactive = <800>; - vactive = <1280>; - hsync-len = <24>; - hback-porch = <24>; - hfront-porch = <12>; - vsync-len = <2>; - vback-porch = <9>; - vfront-porch = <7>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in_dsi1: endpoint { - remote-endpoint = <&dsi1_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi1_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi1>; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5m3_xfer>; - - gt911_dsi1: gt911@5d { - status = "okay"; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio3>; - interrupts = ; - reset-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; - irq-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi1-vp3-800x1280-10.1inch-s8001280b1060b.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi1-vp3-800x1280-10.1inch-s8001280b1060b.dtsi deleted file mode 100644 index 38f8835c1..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi1-vp3-800x1280-10.1inch-s8001280b1060b.dtsi +++ /dev/null @@ -1,310 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * - */ - -&mipi_dcphy1 { - status = "okay"; -}; - -&route_dsi1 { - status = "okay"; - connect = <&vp3_out_dsi1>; -}; - -&dsi1_in_vp3 { - status = "okay"; -}; - -&dsi1 { - status = "okay"; - - dsi1_panel: panel@0 { - status = "okay"; - compatible = "simple-panel-dsi"; - reg = <0>; - backlight = <&backlight_dsi1>; - power-supply = <&mipi_dsi1_power>; - reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>; - - enable-delay-ms = <35>; - prepare-delay-ms = <6>; - reset-delay-ms = <0>; - init-delay-ms = <20>; - unprepare-delay-ms = <0>; - disable-delay-ms = <20>; - - size,width = <74>; - size,height = <133>; - - dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; - dsi,format = ; - dsi,lanes = <4>; - - panel-init-sequence = [ - 15 00 02 E0 00 - 15 00 02 E1 93 - 15 00 02 E2 65 - 15 00 02 E3 F8 - 15 00 02 80 03 - 15 00 02 E0 01 - 15 00 02 00 00 - 15 00 02 01 3B - 15 00 02 0C 74 - 15 00 02 17 00 - 15 00 02 18 AF - 15 00 02 19 00 - 15 00 02 1A 00 - 15 00 02 1B AF - 15 00 02 1C 00 - 15 00 02 35 26 - 15 00 02 37 09 - 15 00 02 38 04 - 15 00 02 39 00 - 15 00 02 3A 01 - 15 00 02 3C 78 - 15 00 02 3D FF - 15 00 02 3E FF - 15 00 02 3F 7F - 15 00 02 40 06 - 15 00 02 41 A0 - 15 00 02 42 81 - 15 00 02 43 1E - 15 00 02 44 0B - 15 00 02 45 28 - 15 00 02 55 02 - 15 00 02 57 69 - 15 00 02 59 0A - 15 00 02 5A 2A - 15 00 02 5B 17 - 15 00 02 5D 7F - 15 00 02 5E 6B - 15 00 02 5F 5C - 15 00 02 60 4F - 15 00 02 61 4D - 15 00 02 62 3F - 15 00 02 63 42 - 15 00 02 64 2B - 15 00 02 65 44 - 15 00 02 66 43 - 15 00 02 67 43 - 15 00 02 68 63 - 15 00 02 69 52 - 15 00 02 6A 5A - 15 00 02 6B 4F - 15 00 02 6C 4E - 15 00 02 6D 20 - 15 00 02 6E 0F - 15 00 02 6F 00 - 15 00 02 70 7F - 15 00 02 71 6B - 15 00 02 72 5C - 15 00 02 73 4F - 15 00 02 74 4D - 15 00 02 75 3F - 15 00 02 76 42 - 15 00 02 77 2B - 15 00 02 78 44 - 15 00 02 79 43 - 15 00 02 7A 43 - 15 00 02 7B 63 - 15 00 02 7C 52 - 15 00 02 7D 5A - 15 00 02 7E 4F - 15 00 02 7F 4E - 15 00 02 80 20 - 15 00 02 81 0F - 15 00 02 82 00 - 15 00 02 E0 02 - 15 00 02 00 42 - 15 00 02 01 42 - 15 00 02 02 40 - 15 00 02 03 40 - 15 00 02 04 5E - 15 00 02 05 5E - 15 00 02 06 5F - 15 00 02 07 5F - 15 00 02 08 5F - 15 00 02 09 57 - 15 00 02 0A 57 - 15 00 02 0B 77 - 15 00 02 0C 77 - 15 00 02 0D 47 - 15 00 02 0E 47 - 15 00 02 0F 45 - 15 00 02 10 45 - 15 00 02 11 4B - 15 00 02 12 4B - 15 00 02 13 49 - 15 00 02 14 49 - 15 00 02 15 5F - 15 00 02 16 41 - 15 00 02 17 41 - 15 00 02 18 40 - 15 00 02 19 40 - 15 00 02 1A 5E - 15 00 02 1B 5E - 15 00 02 1C 5F - 15 00 02 1D 5F - 15 00 02 1E 5F - 15 00 02 1F 57 - 15 00 02 20 57 - 15 00 02 21 77 - 15 00 02 22 77 - 15 00 02 23 46 - 15 00 02 24 46 - 15 00 02 25 44 - 15 00 02 26 44 - 15 00 02 27 4A - 15 00 02 28 4A - 15 00 02 29 48 - 15 00 02 2A 48 - 15 00 02 2B 5F - 15 00 02 2C 01 - 15 00 02 2D 01 - 15 00 02 2E 00 - 15 00 02 2F 00 - 15 00 02 30 1F - 15 00 02 31 1F - 15 00 02 32 1E - 15 00 02 33 1E - 15 00 02 34 1F - 15 00 02 35 17 - 15 00 02 36 17 - 15 00 02 37 37 - 15 00 02 38 37 - 15 00 02 39 08 - 15 00 02 3A 08 - 15 00 02 3B 0A - 15 00 02 3C 0A - 15 00 02 3D 04 - 15 00 02 3E 04 - 15 00 02 3F 06 - 15 00 02 40 06 - 15 00 02 41 1F - 15 00 02 42 02 - 15 00 02 43 02 - 15 00 02 44 00 - 15 00 02 45 00 - 15 00 02 46 1F - 15 00 02 47 1F - 15 00 02 48 1E - 15 00 02 49 1E - 15 00 02 4A 1F - 15 00 02 4B 17 - 15 00 02 4C 17 - 15 00 02 4D 37 - 15 00 02 4E 37 - 15 00 02 4F 09 - 15 00 02 50 09 - 15 00 02 51 0B - 15 00 02 52 0B - 15 00 02 53 05 - 15 00 02 54 05 - 15 00 02 55 07 - 15 00 02 56 07 - 15 00 02 57 1F - 15 00 02 58 40 - 15 00 02 5B 30 - 15 00 02 5C 00 - 15 00 02 5D 34 - 15 00 02 5E 05 - 15 00 02 5F 02 - 15 00 02 63 00 - 15 00 02 64 6A - 15 00 02 67 73 - 15 00 02 68 05 - 15 00 02 69 08 - 15 00 02 6A 6A - 15 00 02 6B 08 - 15 00 02 6C 00 - 15 00 02 6D 00 - 15 00 02 6E 00 - 15 00 02 6F 88 - 15 00 02 75 FF - 15 00 02 77 DD - 15 00 02 78 2A - 15 00 02 79 15 - 15 00 02 7A 17 - 15 00 02 7D 14 - 15 00 02 7E 82 - 15 00 02 E0 04 - 15 00 02 00 0E - 15 00 02 02 B3 - 15 00 02 09 61 - 15 00 02 0E 48 - 15 00 02 E0 00 - 15 00 02 E6 02 - 15 00 02 E7 0C - 15 78 02 11 00 - 15 00 02 E0 00 - 15 05 02 29 00 - ]; - - panel-exit-sequence = [ - 05 78 01 28 - 05 00 01 10 - ]; - - disp1_timings0: display-timings { - native-mode = <&dsi1_timing0>; - dsi1_timing0: timing0 { - clock-frequency = <69801600>; - hactive = <800>; - vactive = <1280>; - hsync-len = <20>; - hback-porch = <20>; - hfront-porch = <40>; - vsync-len = <4>; - vback-porch = <8>; - vfront-porch = <30>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in_dsi1: endpoint { - remote-endpoint = <&dsi1_out_panel>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - dsi1_out_panel: endpoint { - remote-endpoint = <&panel_in_dsi1>; - }; - }; - }; -}; - -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5m3_xfer>; - - gt911_dsi1: gt911@5d { - status = "okay"; - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio3>; - interrupts = ; - reset-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; - irq-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; - touchscreen-inverted-x = <1>; - touchscreen-swapped-x-y = <1>; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-hdmi0-vp0.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-hdmi0-vp0.dtsi deleted file mode 100644 index ae75c6d18..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-hdmi0-vp0.dtsi +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * Copyright (c) 2023 EmbedFire - */ - -/ { - hdmi0_sound: hdmi0-sound { - status = "okay"; - compatible = "rockchip,hdmi"; - rockchip,mclk-fs = <128>; - rockchip,card-name = "rockchip-hdmi0"; - rockchip,cpu = <&i2s5_8ch>; - rockchip,codec = <&hdmi0>; - rockchip,jack-det; - }; -}; - -&i2s5_8ch { - status = "okay"; -}; - -&hdmi0 { - enable-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - cec-enable = "true"; - status = "okay"; -}; - -&route_hdmi0{ - status = "okay"; - connect = <&vp0_out_hdmi0>; -}; - -&hdmi0_in_vp0 { - status = "okay"; -}; - -&hdmi0_in_vp1 { - status = "disabled"; -}; - -&hdmi0_in_vp2 { - status = "disabled"; -}; - -&hdptxphy_hdmi0 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io.dts b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io.dts deleted file mode 100644 index fda084f46..000000000 --- a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io.dts +++ /dev/null @@ -1,1732 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * Copyright (c) 2023 EmbedFire - */ - -/dts-v1/; - -#include -#include -#include -#include -//#include -#include -#include -#include -#include -#include -#include "rk3588s.dtsi" -#include "rk3588-linux.dtsi" - -/* MIPI CSI 节点配置 */ -#include "rk3588s-lubancat-4io-csi.dtsi" -/* 开启链路节点 */ -// #include "rk3588s-lubancat-4io-cam0.dtsi" -// #include "rk3588s-lubancat-4io-cam1.dtsi" -// #include "rk3588s-lubancat-4io-cam2.dtsi" -// #include "rk3588s-lubancat-4io-cam3.dtsi" - -/* 显示输出配置， - * 同一个vp同时只能开启一个配置 - * 最多可以同时开启4个vp - * mipi屏幕默认使用设备树插件开启 - */ -/***** vp0 *****/ -/* hdmi0 display */ -// #include "rk3588s-lubancat-4io-hdmi0-vp0.dtsi" - -/***** vp1 *****/ -/* dp0 display */ -// #include "rk3588s-lubancat-4io-dp0-vp1.dtsi" - -/***** vp2 *****/ -// #include "rk3588s-lubancat-4io-dsi0-vp2-1080x1920-5.5inch-ebf410125.dtsi" -// #include "rk3588s-lubancat-4io-dsi0-vp2-1024x600-7inch-ebf410173.dtsi" -// #include "rk3588s-lubancat-4io-dsi0-vp2-800x1280-10.1inch-ebf410177.dtsi" -// #include "rk3588s-lubancat-4io-dsi0-vp2-800x1280-10.1inch-s8001280b1060b.dtsi" - -/***** vp3 *****/ -// #include "rk3588s-lubancat-4io-dsi1-vp3-1080x1920-5.5inch-ebf410125.dtsi" -// #include "rk3588s-lubancat-4io-dsi1-vp3-1024x600-7inch-ebf410173.dtsi" -// #include "rk3588s-lubancat-4io-dsi1-vp3-800x1280-10.1inch-ebf410177.dtsi" -// #include "rk3588s-lubancat-4io-dsi1-vp3-800x1280-10.1inch-s8001280b1060b.dtsi" - -/ { - model = "Embedfire LubanCat-4IO"; - compatible = "embedfire,rk3588s-lubancat-4io", "rockchip,rk3588"; - - leds: leds { - status = "okay"; - compatible = "gpio-leds"; - - sys_led: sys-led { - label = "sys_led"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sys_led_pin>; - }; - - user_led: user-led { - label = "user_led"; - linux,default-trigger = "none"; - default-state = "on"; - gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&user_led_pin>; - }; - }; - - adc4-keys { - compatible = "adc-keys"; - io-channels = <&saradc 4>; - io-channel-names = "buttons"; - poll-interval = <100>; - keyup-threshold-microvolt = <1800000>; - adc-power-key { - linux,code = ; - label = "KEY DOWN"; - press-threshold-microvolt = <1750>; - }; - }; - - adc5-keys { - compatible = "adc-keys"; - io-channels = <&saradc 5>; - io-channel-names = "buttons"; - poll-interval = <100>; - keyup-threshold-microvolt = <1800000>; - adc-power-key { - linux,code = ; - label = "KEY UP"; - press-threshold-microvolt = <1750>; - }; - }; - - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-name = "vcc12v_dcin"; - }; - - vdd_5v:vdd_5v { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; - }; - - vdd_3v3:vdd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc5v0_sys: vcc5v0-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc3v3_sys: vcc3v3-sys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc12v_dcin>; - }; - - combophy_avdd0v85: combophy-avdd0v85 { - compatible = "regulator-fixed"; - regulator-name = "combophy_avdd0v85"; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&avdd_0v85_s0>; - }; - - combophy_avdd1v8: combophy-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "combophy_avdd1v8"; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc_3v3_s0: vcc-3v3-s0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_s3>; - }; - - vcc_3v3_sd_s3: vcc-3v3-sd-s3 { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_sd_s3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_s3>; - }; - - vbus5v0_typec: vbus5v0-typec { - compatible = "regulator-fixed"; - regulator-name = "vbus5v0_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&typec_vbus_en>; - }; - - vcc5v0_usb30_host: vcc5v0-usb30-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb30_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&usb30_host_pwr_en>; - }; - - vcc5v0_usb20_host: vcc5v0-usb20-host { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb20_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&usb20_host_pwr_en>; - }; - - minipcie_3v3: minipcie-3v3{ - compatible = "regulator-fixed"; - regulator-name = "minipcie_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&minipcie_3v3_en>; - }; - - wlan_3v3: wlan-3v3 { - compatible = "regulator-fixed"; - regulator-name = "wlan_3v3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&wlan_3v3_en>; - }; - - cam1_2_5v0: cam1-2-5v0 { - compatible = "regulator-fixed"; - regulator-name = "cam1_2_5v0"; - regulator-always-on; - regulator-boot-on; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cam1_2_5v0_en>; - }; - - cam3_4_5v0: cam3-4-5v0 { - compatible = "regulator-fixed"; - regulator-name = "cam3_4_5v0"; - regulator-always-on; - regulator-boot-on; - enable-active-high; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&cam3_4_5v0_en>; - }; - - mipi_dsi0_power: mipi-dsi0-power-regulator { - compatible = "regulator-fixed"; - regulator-name = "mipi_dsi0_power"; - gpio = <&gpio1 RK_PC0 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&mipi_dsi0_power_en>; - }; - - mipi_dsi1_power: mipi-dsi1-power-regulator { - compatible = "regulator-fixed"; - regulator-name = "mipi_dsi1_power"; - gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - vin-supply = <&vcc5v0_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&mipi_dsi1_power_en>; - }; - - es8388_sound: es8388-sound { - status = "okay"; - compatible = "rockchip,multicodecs-card"; - rockchip,card-name = "rockchip-es8388"; - hp-det-gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; - hp-con-gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; - spk-con-gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - //io-channels = <&saradc 4>; - //io-channel-names = "adc-detect"; - //keyup-threshold-microvolt = <1800000>; - //poll-interval = <100>; - rockchip,format = "i2s"; - rockchip,mclk-fs = <256>; - rockchip,cpu = <&i2s0_8ch>; - rockchip,codec = <&es8388>; - rockchip,audio-routing = - "Headphone", "LOUT1", - "Headphone", "ROUT1", - "Headphone", "Headphone Power", - "Headphone", "Headphone Power", - "LINPUT1", "Headset Mic", - "RINPUT1", "Headset Mic", - "LINPUT2", "Main Mic", - "RINPUT2", "Main Mic"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det>; - /* - play-pause-key { - label = "playpause"; - linux,code = ; - press-threshold-microvolt = <2000>; - }; - - previous-song-key { - label = "previoussong"; - linux,code = ; - press-threshold-microvolt = <145000>; - }; - - next-song-key { - label = "nextsong"; - linux,code = ; - press-threshold-microvolt = <290000>; - }; - */ - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - #cooling-cells = <2>; - pwms = <&pwm11 0 5000 0>; - cooling-levels = <0 100 150 200 255>; - rockchip,temp-trips = < - 35000 1 - 40000 2 - 45000 3 - 50000 4 - >; - }; - - backlight_dsi0: backlight-dsi0 { - status = "okay"; - compatible = "pwm-backlight"; - pwms = <&pwm0 0 25000 0>; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - backlight_dsi1: backlight-dsi1 { - status = "okay"; - compatible = "pwm-backlight"; - pwms = <&pwm1 0 25000 0>; - brightness-levels = < - 0 20 20 21 21 22 22 23 - 23 24 24 25 25 26 26 27 - 27 28 28 29 29 30 30 31 - 31 32 32 33 33 34 34 35 - 35 36 36 37 37 38 38 39 - 40 41 42 43 44 45 46 47 - 48 49 50 51 52 53 54 55 - 56 57 58 59 60 61 62 63 - 64 65 66 67 68 69 70 71 - 72 73 74 75 76 77 78 79 - 80 81 82 83 84 85 86 87 - 88 89 90 91 92 93 94 95 - 96 97 98 99 100 101 102 103 - 104 105 106 107 108 109 110 111 - 112 113 114 115 116 117 118 119 - 120 121 122 123 124 125 126 127 - 128 129 130 131 132 133 134 135 - 136 137 138 139 140 141 142 143 - 144 145 146 147 148 149 150 151 - 152 153 154 155 156 157 158 159 - 160 161 162 163 164 165 166 167 - 168 169 170 171 172 173 174 175 - 176 177 178 179 180 181 182 183 - 184 185 186 187 188 189 190 191 - 192 193 194 195 196 197 198 199 - 200 201 202 203 204 205 206 207 - 208 209 210 211 212 213 214 215 - 216 217 218 219 220 221 222 223 - 224 225 226 227 228 229 230 231 - 232 233 234 235 236 237 238 239 - 240 241 242 243 244 245 246 247 - 248 249 250 251 252 253 254 255 - >; - default-brightness-level = <200>; - }; - - test-power { - status = "okay"; - }; -}; - -&av1d { - status = "okay"; -}; - -&av1d_mmu { - status = "okay"; -}; - -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; - mem-supply = <&vdd_cpu_lit_mem_s0>; -}; - -&cpu_b0 { - cpu-supply = <&vdd_cpu_big0_s0>; - mem-supply = <&vdd_cpu_big0_mem_s0>; -}; - -&cpu_b2 { - cpu-supply = <&vdd_cpu_big1_s0>; - mem-supply = <&vdd_cpu_big1_mem_s0>; -}; - -&gpu { - mali-supply = <&vdd_gpu_s0>; - mem-supply = <&vdd_gpu_mem_s0>; - upthreshold = <60>; - downdifferential = <30>; - status = "okay"; -}; - -&dfi { - status = "okay"; -}; - -&dmc { - status = "okay"; - center-supply = <&vdd_ddr_s0>; - mem-supply = <&vdd_log_s0>; -}; - -&rockchip_suspend { - status = "okay"; - rockchip,sleep-debug-en = <1>; - rockchip,sleep-mode-config = < - (0 - | RKPM_SLP_ARMOFF_DDRPD - | RKPM_SLP_PMU_PMUALIVE_32K - | RKPM_SLP_PMU_DIS_OSC - | RKPM_SLP_32K_EXT - ) - >; - rockchip,wakeup-config = < - (0 - | RKPM_GPIO_WKUP_EN - | RKPM_CPU0_WKUP_EN - ) - >; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; - status = "okay"; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "hym8563"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - interrupt-parent = <&gpio0>; - interrupts = ; - wakeup-source; - }; - - vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big0_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { - compatible = "rockchip,rk8603"; - reg = <0x43>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_cpu_big1_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <1050000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1m2_xfer>; - status = "okay"; - - vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { - compatible = "rockchip,rk8602"; - reg = <0x42>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "rk860x-reg"; - regulator-name = "vdd_npu_s0"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <2300>; - rockchip,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - /* Typec Controller Fusb302 */ - usbc0: fusb302@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&fusb302_int>; - vbus-supply = <&vbus5v0_typec>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - ; - source-pdos = - ; - - altmodes { - #address-cells = <1>; - #size-cells = <0>; - - altmode@0 { - reg = <0>; - svid = <0xff01>; - vdo = <0xffffffff>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; - }; - }; - - port@1 { - reg = <1>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; - }; - }; - }; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2m4_xfer>; - status = "okay"; -}; - -&i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c5m3_xfer>; - status = "okay"; -}; - -&spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - num-cs = <1>; - - rk806single@0 { - compatible = "rockchip,rk806"; - spi-max-frequency = <1000000>; - reg = <0x0>; - - interrupt-parent = <&gpio0>; - interrupts = ; - - pinctrl-names = "default", "pmic-power-off"; - pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; - pinctrl-1 = <&rk806_dvs1_pwrdn>; - - /* 2800mv-3500mv */ - low_voltage_threshold = <3000>; - /* 2700mv-3400mv */ - shutdown_voltage_threshold = <2700>; - /* 140 160 */ - shutdown_temperture_threshold = <160>; - hotdie_temperture_threshold = <115>; - - /* 0: restart PMU; - * 1: reset all the power off reset registers, - * forcing the state to switch to ACTIVE mode; - * 2: Reset all the power off reset registers, - * forcing the state to switch to ACTIVE mode, - * and simultaneously pull down the RESETB PIN for 5mS before releasing - */ - pmic-reset-func = <1>; - - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; - vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; - vcc13-supply = <&vcc_1v1_nldo_s3>; - vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; - - pwrkey { - status = "okay"; - }; - - pinctrl_rk806: pinctrl_rk806 { - gpio-controller; - #gpio-cells = <2>; - - rk806_dvs1_null: rk806_dvs1_null { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs1_slp: rk806_dvs1_slp { - pins = "gpio_pwrctrl1"; - function = "pin_fun1"; - }; - - rk806_dvs1_pwrdn: rk806_dvs1_pwrdn { - pins = "gpio_pwrctrl1"; - function = "pin_fun2"; - }; - - rk806_dvs1_rst: rk806_dvs1_rst { - pins = "gpio_pwrctrl1"; - function = "pin_fun3"; - }; - - rk806_dvs2_null: rk806_dvs2_null { - pins = "gpio_pwrctrl2"; - function = "pin_fun0"; - }; - - rk806_dvs2_slp: rk806_dvs2_slp { - pins = "gpio_pwrctrl2"; - function = "pin_fun1"; - }; - - rk806_dvs2_pwrdn: rk806_dvs2_pwrdn { - pins = "gpio_pwrctrl2"; - function = "pin_fun2"; - }; - - rk806_dvs2_rst: rk806_dvs2_rst { - pins = "gpio_pwrctrl2"; - function = "pin_fun3"; - }; - - rk806_dvs2_dvs: rk806_dvs2_dvs { - pins = "gpio_pwrctrl2"; - function = "pin_fun4"; - }; - - rk806_dvs2_gpio: rk806_dvs2_gpio { - pins = "gpio_pwrctrl2"; - function = "pin_fun5"; - }; - - rk806_dvs3_null: rk806_dvs3_null { - pins = "gpio_pwrctrl3"; - function = "pin_fun0"; - }; - - rk806_dvs3_slp: rk806_dvs3_slp { - pins = "gpio_pwrctrl3"; - function = "pin_fun1"; - }; - - rk806_dvs3_pwrdn: rk806_dvs3_pwrdn { - pins = "gpio_pwrctrl3"; - function = "pin_fun2"; - }; - - rk806_dvs3_rst: rk806_dvs3_rst { - pins = "gpio_pwrctrl3"; - function = "pin_fun3"; - }; - - rk806_dvs3_dvs: rk806_dvs3_dvs { - pins = "gpio_pwrctrl3"; - function = "pin_fun4"; - }; - - rk806_dvs3_gpio: rk806_dvs3_gpio { - pins = "gpio_pwrctrl3"; - function = "pin_fun5"; - }; - }; - - regulators { - vdd_gpu_s0: vdd_gpu_mem_s0: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_gpu_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_cpu_lit_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_log_s0: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_log_s0"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_vdenc_s0: vdd_vdenc_mem_s0: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <950000>; - regulator-init-microvolt = <750000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_vdenc_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_ddr_s0: DCDC_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-ramp-delay = <12500>; - regulator-name = "vdd_ddr_s0"; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - vdd2_ddr_s3: DCDC_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vdd2_ddr_s3"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_2v0_pldo_s3: DCDC_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-name = "vdd_2v0_pldo_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <2000000>; - }; - }; - - vcc_3v3_s3: DCDC_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_3v3_s3"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vddq_ddr_s0: DCDC_REG9 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vddq_ddr_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8_s3: DCDC_REG10 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcc_1v8_s0: PLDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8_s0"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - avcc_1v8_s0: PLDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "avcc_1v8_s0"; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - avdd_1v2_s0: PLDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "avdd_1v2_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avcc_3v3_s0: PLDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc_3v3_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd_s0: PLDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - pldo6_s3: PLDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "pldo6_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_0v75_s3: NLDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s3"; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <750000>; - }; - }; - - avdd_ddr_pll_s0: NLDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "avdd_ddr_pll_s0"; - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <850000>; - }; - }; - - avdd_0v75_s0: NLDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "avdd_0v75_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - avdd_0v85_s0: NLDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-name = "avdd_0v85_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_0v75_s0: NLDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - regulator-name = "vdd_0v75_s0"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - }; -}; - -&i2c7 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c7m0_xfer>; - status = "okay"; - - es8388: es8388@11 { - status = "okay"; - #sound-dai-cells = <0>; - compatible = "everest,es8388", "everest,es8323"; - reg = <0x11>; - clocks = <&mclkout_i2s0>; - clock-names = "mclk"; - assigned-clocks = <&mclkout_i2s0>; - assigned-clock-rates = <12288000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_mclk>; - }; -}; - -&i2s0_8ch { - status = "okay"; - rockchip,clk-trcm = <1>; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdo0>; -}; - -&saradc { - status = "okay"; - vref-supply = <&avcc_1v8_s0>; -}; - -&tsadc { - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - max-frequency = <200000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - full-pwr-cycle-in-suspend; - status = "okay"; -}; - -&sdmmc { - max-frequency = <200000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_sd_s3>; - vqmmc-supply = <&vccio_sd_s0>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; - status = "okay"; -}; - -&iep { - status = "okay"; -}; - -&iep_mmu { - status = "okay"; -}; - -&jpegd { - status = "okay"; -}; - -&jpegd_mmu { - status = "okay"; -}; - -&jpege_ccu { - status = "okay"; -}; - -&jpege0 { - status = "okay"; -}; - -&jpege0_mmu { - status = "okay"; -}; - -&jpege1 { - status = "okay"; -}; - -&jpege1_mmu { - status = "okay"; -}; - -&jpege2 { - status = "okay"; -}; - -&jpege2_mmu { - status = "okay"; -}; - -&jpege3 { - status = "okay"; -}; - -&jpege3_mmu { - status = "okay"; -}; - -&mpp_srv { - status = "okay"; -}; - -&pwm0 { - pinctrl-0 = <&pwm0m2_pins>; - status = "okay"; -}; - -&pwm1 { - pinctrl-0 = <&pwm1m2_pins>; - status = "okay"; -}; - -&pwm2 { - pinctrl-0 = <&pwm2m0_pins>; - status = "disabled"; -}; - -&pwm4 { - pinctrl-0 = <&pwm4m0_pins>; - status = "disabled"; -}; - -&pwm6 { - pinctrl-0 = <&pwm6m0_pins>; - status = "disabled"; -}; - -&pwm7 { - compatible = "rockchip,remotectl-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm7m0_pins>; - remote_pwm_id = <3>; - handle_cpu_id = <1>; - remote_support_psci = <0>; - status = "okay"; - - ir_key_lubancat{ - rockchip,usercode = <0xff00>; - rockchip,key_table = - <0xba KEY_POWER>, //电源按键 - <0xb8 KEY_MENU>, //菜单按键 - <0xbc KEY_BACK>, //返回按键 - <0xbb KEY_HOME>, //home键按键 - <0xea KEY_PLAY>, //播放按键 - <0xbf KEY_VOLUMEUP>, //音量加按键 - <0xe6 KEY_VOLUMEDOWN>, //音量键按键 - <0xf6 KEY_FASTFORWARD>, //快进按键 - <0xf8 KEY_FASTREVERSE>, //快退按键 - <0xf2 KEY_BACKSPACE>, //BaskSpace按键 - <0xf3 KEY_1>, //按键1 - <0xe7 KEY_2>, - <0xa1 KEY_3>, - <0xf7 KEY_4>, - <0xe3 KEY_5>, - <0xa5 KEY_6>, - <0xbd KEY_7>, - <0xad KEY_8>, - <0xb5 KEY_9>, - <0xe9 KEY_0>; //按键0 - }; - - ir_key2 { - rockchip,usercode = <0xf708>; - rockchip,key_table = - <0x28 KEY_POWER>, - <0xfe KEY_SETUP>, - <0xa4 KEY_MUTE>, - <0x6d KEY_UP>, - <0x68 KEY_LEFT>, - <0x64 KEY_ENTER>, - <0x60 KEY_RIGHT>, - <0x27 KEY_DOWN>, - <0x3c KEY_MENU>, - <0x7d KEY_HOME>, - <0x2b KEY_BACK>, - <0x7c KEY_VOLUMEDOWN>, - <0x79 KEY_VOLUMEUP>, - <0x57 KEY_AUDIO>, - <0x5d KEY_SUBTITLE>, - <0x99 KEY_PHONE>, - <0xfd KEY_WWW>, - <0xfc KEY_F1>, - <0x7e KEY_TV>; - }; - - ir_key3 { - rockchip,usercode = <0x1dcc>; - rockchip,key_table = - <0xee KEY_REPLY>, - <0xf0 KEY_BACK>, - <0xf8 KEY_UP>, - <0xbb KEY_DOWN>, - <0xef KEY_LEFT>, - <0xed KEY_RIGHT>, - <0xfc KEY_HOME>, - <0xf1 KEY_VOLUMEUP>, - <0xfd KEY_VOLUMEDOWN>, - <0xb7 KEY_SEARCH>, - <0xff KEY_POWER>, - <0xf3 KEY_MUTE>, - <0xbf KEY_MENU>, - <0xf9 0x191>, - <0xf5 0x192>, - <0xb3 388>, - <0xbe KEY_1>, - <0xba KEY_2>, - <0xb2 KEY_3>, - <0xbd KEY_4>, - <0xf9 KEY_5>, - <0xb1 KEY_6>, - <0xfc KEY_7>, - <0xf8 KEY_8>, - <0xb0 KEY_9>, - <0xb6 KEY_0>, - <0xb5 KEY_BACKSPACE>; - }; -}; - -&pwm11 { - pinctrl-0 = <&pwm11m2_pins>; - status = "okay"; -}; - -&rga3_core0 { - status = "okay"; -}; - -&rga3_0_mmu { - status = "okay"; -}; - -&rga3_core1 { - status = "okay"; -}; - -&rga3_1_mmu { - status = "okay"; -}; - -&rga2 { - status = "okay"; -}; - -&rknpu { - rknpu-supply = <&vdd_npu_s0>; - mem-supply = <&vdd_npu_mem_s0>; - status = "okay"; -}; - -&rknpu_mmu { - status = "okay"; -}; - -&rkvdec_ccu { - status = "okay"; -}; - -&rkvdec0 { - status = "okay"; -}; - -&rkvdec0_mmu { - status = "okay"; -}; - -&rkvdec1 { - status = "okay"; -}; - -&rkvdec1_mmu { - status = "okay"; -}; - -&rkvenc_ccu { - status = "okay"; -}; - -&rkvenc0 { - status = "okay"; -}; - -&rkvenc0_mmu { - status = "okay"; -}; - -&rkvenc1 { - status = "okay"; -}; - -&rkvenc1_mmu { - status = "okay"; -}; - -/* this is a watchdog */ -&wdt { - status = "okay"; -}; - -&gmac1 { - /* Use rgmii-rxid mode to disable rx delay inside Soc */ - phy-mode = "rgmii-rxid"; - clock_in_out = "output"; - - snps,reset-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - - pinctrl-names = "default"; - pinctrl-0 = <&gmac1_miim - &gmac1_tx_bus2 - &gmac1_rx_bus2 - &gmac1_rgmii_clk - &gmac1_rgmii_bus>; - - tx_delay = <0x18>; - /* rx_delay = <0x4f>; */ - - phy-handle = <&rgmii_phy1>; - status = "okay"; -}; - -&mdio1 { - rgmii_phy1: phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0>; - jl2xxx,led-enable = <(JL2XXX_LED_STATIC_OP_EN | JL1XXX_LED_MODE_EN)>; - jl2xxx,led-mode = <(JL2XXX_LED1_LINK10 | \ - JL2XXX_LED1_LINK100 | \ - JL2XXX_LED1_LINK1000 | \ - JL2XXX_LED2_LINK10 | \ - JL2XXX_LED2_LINK100 | \ - JL2XXX_LED2_LINK1000 | \ - JL2XXX_LED2_ACTIVITY )>; //JL PHY - realtek,led-data = <0x6d60>; //8211F phy - }; -}; - -/* SATA30_HOST0/PCIe20x1_2 Combo PHY */ -&combphy0_ps { - status = "okay"; -}; - -&pcie2x1l2 { - reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; - disable-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&minipcie_3v3>; - status = "okay"; -}; - -/* USB3.0_OTG/DP1.4 Combo PHY0 */ -&usbdp_phy0 { - orientation-switch; - svid = <0xff01>; - sbu1-dc-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - usbdp_phy0_orientation_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; - }; - - usbdp_phy0_dp_altmode_mux: endpoint@1 { - reg = <1>; - remote-endpoint = <&dp_altmode_mux>; - }; - }; -}; - -&usbdp_phy0_u3 { - status = "okay"; -}; - -&usbdp_phy0_dp { - status = "okay"; -}; - -/* USB3.0 OTG0 Controller */ -&usbdrd3_0 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "otg"; - usb-role-switch; - - status = "okay"; - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -/* USB2.0 PHY0 */ -&u2phy0 { - status = "okay"; -}; - -&u2phy0_otg { - rockchip,typec-vbus-det; - status = "okay"; -}; - -/* USB30_HOST2/SATA30_HOST2/PCIe20x1_1 Combo PHY */ -&combphy2_psu { - status = "okay"; -}; - -/* USB3.1 HOST2 Controller */ -&usbhost3_0 { - status = "okay"; -}; - -&usbhost_dwc3_0 { - dr_mode = "host"; - status = "okay"; -}; - -/* USB2.0 HOST0 PHY2 */ -&u2phy2 { - status = "okay"; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_usb30_host>; - status = "okay"; -}; - -/* USB2.0 HOST0 Controller */ -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -/* USB2.0 HOST1 PHY3 */ -&u2phy3 { - status = "okay"; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_usb20_host>; - status = "okay"; -}; - -/* USB2.0 HOST1 Controller */ -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&vdpu { - status = "okay"; -}; - -&vdpu_mmu { - status = "okay"; -}; - -&vepu { - status = "okay"; -}; - -&vop { - status = "okay"; - // disable-win-move; -}; - -&vop_mmu { - status = "okay"; -}; - -/* vp0 & vp1 splice for 8K output */ -&vp0 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; - rockchip,primary-plane = ; - // cursor-win-id = ; -}; - -&vp1 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; - rockchip,primary-plane = ; - cursor-win-id = ; -}; - -&vp2 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; - rockchip,primary-plane = ; - cursor-win-id = ; -}; - -&vp3 { - rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; - rockchip,primary-plane = ; - cursor-win-id = ; -}; - -&display_subsystem { - clocks = <&hdptxphy_hdmi_clk0>; - clock-names = "hdmi0_phy_pll"; -}; - -&hdptxphy_hdmi_clk0 { - status = "okay"; -}; - -/* RS485 */ -&uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4m2_xfer &rs485_1_rts>; - rs485-de-gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>; - linux,rs485-enabled-at-boot-time; -}; - -&uart7 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart7m2_xfer &rs485_2_rts>; - rs485-de-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; - linux,rs485-enabled-at-boot-time; -}; - -/* RS232 */ -&uart0 { - status = "okay"; - pinctrl-0 = <&uart0m0_xfer>; -}; - -&uart9 { - status = "okay"; - pinctrl-0 = <&uart9m2_xfer>; -}; - -&can1 { - assigned-clocks = <&cru CLK_CAN1>; - assigned-clock-rates = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&can1m1_pins>; - status = "okay"; -}; - -&can2 { - assigned-clocks = <&cru CLK_CAN2>; - assigned-clock-rates = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&can2m0_pins>; - status = "okay"; -}; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - headphone { - hp_det: hp-det { - rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb-typec { - fusb302_int: fusb302-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - typec_vbus_en: typec-vbus-en { - rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - usb30_host_pwr_en: usb30-host-pwr-en { - rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - usb20_host_pwr_en: usb20-host-pwr-en { - rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pcie { - minipcie_3v3_en: minipcie-3v3-en{ - rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - mipi { - mipi_dsi0_power_en: mipi-dsi0-5v0-image0-en { - rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - mipi_dsi1_power_en: mipi-dsi1-5v0-image1-en { - rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - leds { - sys_led_pin: sys-led-pin { - rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - user_led_pin: user-led-pin { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wlan { - wlan_3v3_en: wlan-3v3-en { - rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - cam { - cam1_2_5v0_en: cam1-2-5v0-en { - rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - cam3_4_5v0_en: cam3-4-5v0-en { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - rs485_rts { - rs485_1_rts: rs485_1_rts { - rockchip,pins = - <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - rs485_2_rts: rs485_2_rts { - rockchip,pins = - <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index f67fe7550..175bf0633 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1397,7 +1397,6 @@ SYS_STATUS_SUSPEND DMC_FREQ_LEVEL_LOW SYS_STATUS_VIDEO_4K DMC_FREQ_LEVEL_MID_HIGH SYS_STATUS_VIDEO_4K_10B DMC_FREQ_LEVEL_MID_HIGH - SYS_STATUS_VIDEO_SVEP DMC_FREQ_LEVEL_MID_HIGH SYS_STATUS_BOOST DMC_FREQ_LEVEL_HIGH SYS_STATUS_ISP DMC_FREQ_LEVEL_HIGH SYS_STATUS_PERFORMANCE DMC_FREQ_LEVEL_HIGH