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chang rk3588s.dts

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This commit is contained in:
ardu 2026-01-27 15:17:13 +08:00
parent f87f0f95b2
commit 2ee59fd56a
48 changed files with 0 additions and 17953 deletions
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3707
arch/arm64/boot/dts/rockchip/rk3568.dtsi
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79
arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam0.dtsi
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@ -1,79 +0,0 @@
&i2c0 {
status = "okay";
};
&dcphy0_dw9714 {
status = "disabled";
};
&dcphy0_ov5647 {
status = "disabled";
};
&dcphy0_ov5648 {
status = "disabled";
};
&dcphy0_ov8858 {
status = "disabled";
};
&dcphy0_ov13850 {
status = "disabled";
};
&dcphy0_imx415 {
status = "okay";
};
&dcphy0_gc08a8 {
status = "disabled";
};
&dcphy0_gc2053 {
status = "disabled";
};
&dcphy0_gc4653 {
status = "disabled";
};
&mipi_dcphy0 {
status = "okay";
};
&csi2_dcphy0 {
status = "okay";
};
&mipi0_csi2 {
status = "okay";
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds {
status = "okay";
};
&rkcif_mipi_lvds_sditf {
status = "okay";
};
&rkcif_mmu {
status = "okay";
};
&rkisp0 {
status = "okay";
};
&isp0_mmu {
status = "okay";
};
&rkisp0_vir0 {
status = "okay";
};

79
arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam1.dtsi
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@ -1,79 +0,0 @@
&i2c1 {
status = "okay";
};
&dcphy1_dw9714 {
status = "disabled";
};
&dcphy1_ov5647 {
status = "disabled";
};
&dcphy1_ov5648 {
status = "disabled";
};
&dcphy1_ov8858 {
status = "disabled";
};
&dcphy1_ov13850 {
status = "disabled";
};
&dcphy1_imx415 {
status = "okay";
};
&dcphy1_gc08a8 {
status = "disabled";
};
&dcphy1_gc2053 {
status = "disabled";
};
&dcphy1_gc4653 {
status = "disabled";
};
&csi2_dcphy1 {
status = "okay";
};
&mipi1_csi2 {
status = "okay";
};
&mipi_dcphy1 {
status = "okay";
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds1 {
status = "okay";
};
&rkcif_mipi_lvds1_sditf {
status = "okay";
};
&rkcif_mmu {
status = "okay";
};
&rkisp1 {
status = "okay";
};
&isp1_mmu {
status = "okay";
};
&rkisp1_vir0 {
status = "okay";
};

79
arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam2.dtsi
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@ -1,79 +0,0 @@
&i2c2 {
status = "okay";
};
&dphy1_dw9714 {
status = "disabled";
};
&dphy1_ov5647 {
status = "disabled";
};
&dphy1_ov5648 {
status = "disabled";
};
&dphy1_ov8858 {
status = "disabled";
};
&dphy1_ov13850 {
status = "disabled";
};
&dphy1_imx415 {
status = "okay";
};
&dphy1_gc08a8 {
status = "disabled";
};
&dphy1_gc2053 {
status = "disabled";
};
&dphy1_gc4653 {
status = "disabled";
};
&csi2_dphy0_hw {
status = "okay";
};
&csi2_dphy1 {
status = "okay";
};
&mipi2_csi2 {
status = "okay";
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds2 {
status = "okay";
};
&rkcif_mipi_lvds2_sditf {
status = "okay";
};
&rkcif_mmu {
status = "okay";
};
&rkisp0 {
status = "okay";
};
&isp0_mmu {
status = "okay";
};
&rkisp0_vir2 {
status = "okay";
};

79
arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam3.dtsi
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@ -1,79 +0,0 @@
&i2c5 {
status = "okay";
};
&dphy2_dw9714 {
status = "disabled";
};
&dphy2_ov5647 {
status = "disabled";
};
&dphy2_ov5648 {
status = "disabled";
};
&dphy2_ov8858 {
status = "disabled";
};
&dphy2_ov13850 {
status = "disabled";
};
&dphy2_imx415 {
status = "okay";
};
&dphy2_gc08a8 {
status = "disabled";
};
&dphy2_gc2053 {
status = "disabled";
};
&dphy2_gc4653 {
status = "disabled";
};
&csi2_dphy0_hw {
status = "okay";
};
&csi2_dphy2 {
status = "okay";
};
&mipi3_csi2 {
status = "okay";
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds3 {
status = "okay";
};
&rkcif_mipi_lvds3_sditf {
status = "okay";
};
&rkcif_mmu {
status = "okay";
};
&rkisp0 {
status = "okay";
};
&isp0_mmu {
status = "okay";
};
&rkisp0_vir1 {
status = "okay";
};

79
arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam4.dtsi
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@ -1,79 +0,0 @@
&i2c7 {
status = "okay";
};
&dphy4_dw9714 {
status = "disabled";
};
&dphy4_ov5647 {
status = "disabled";
};
&dphy4_ov5648 {
status = "disabled";
};
&dphy4_ov8858 {
status = "disabled";
};
&dphy4_ov13850 {
status = "disabled";
};
&dphy4_imx415 {
status = "okay";
};
&dphy4_gc08a8 {
status = "disabled";
};
&dphy4_gc2053 {
status = "disabled";
};
&dphy4_gc4653 {
status = "disabled";
};
&csi2_dphy1_hw {
status = "okay";
};
&csi2_dphy4 {
status = "okay";
};
&mipi4_csi2 {
status = "okay";
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds4 {
status = "okay";
};
&rkcif_mipi_lvds4_sditf {
status = "okay";
};
&rkcif_mmu {
status = "okay";
};
&rkisp1 {
status = "okay";
};
&isp1_mmu {
status = "okay";
};
&rkisp1_vir1 {
status = "okay";
};

79
arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-cam5.dtsi
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@ -1,79 +0,0 @@
&i2c8 {
status = "okay";
};
&dphy5_dw9714 {
status = "disabled";
};
&dphy5_ov5647 {
status = "disabled";
};
&dphy5_ov5648 {
status = "disabled";
};
&dphy5_ov8858 {
status = "disabled";
};
&dphy5_ov13850 {
status = "disabled";
};
&dphy5_imx415 {
status = "okay";
};
&dphy5_gc08a8 {
status = "disabled";
};
&dphy5_gc2053 {
status = "disabled";
};
&dphy5_gc4653 {
status = "disabled";
};
&csi2_dphy1_hw {
status = "okay";
};
&csi2_dphy5 {
status = "okay";
};
&mipi5_csi2 {
status = "okay";
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds5 {
status = "okay";
};
&rkcif_mipi_lvds5_sditf {
status = "okay";
};
&rkcif_mmu {
status = "okay";
};
&rkisp1 {
status = "okay";
};
&isp1_mmu {
status = "okay";
};
&rkisp1_vir2 {
status = "okay";
};

2269
arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-csi.dtsi
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37
arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-dp0-vp1.dtsi
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@ -1,37 +0,0 @@
/ {
dp0_sound: dp0-sound {
status = "okay";
compatible = "rockchip,hdmi";
rockchip,card-name = "rockchip-dp0";
rockchip,mclk-fs = <512>;
rockchip,cpu = <&spdif_tx2>;
rockchip,codec = <&dp0 1>;
rockchip,jack-det;
};
};
&spdif_tx2 {
status = "okay";
};
&dp0 {
status = "okay";
};
&route_dp0 {
status = "okay";
connect = <&vp1_out_dp0>;
};
&dp0_in_vp0 {
status = "disabled";
};
&dp0_in_vp1 {
status = "okay";
};
&dp0_in_vp2 {
status = "disabled";
};

126
arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-dsi0-vp2-1080x1920-5.5inch-ebf410125.dtsi
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@ -1,126 +0,0 @@
&dsi0 {
status = "okay";
dsi0_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
backlight = <&backlight_dsi0>;
power-supply = <&mipi_dsi0_power>;
reset-gpios = <&gpio6 13 GPIO_ACTIVE_LOW>;
enable-delay-ms = <35>;
prepare-delay-ms = <6>;
reset-delay-ms = <10>;
init-delay-ms = <50>;
unprepare-delay-ms = <0>;
disable-delay-ms = <20>;
size,width = <74>;
size,height = <133>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
39 00 04 B9 FF 83 99
15 00 02 D2 77
39 00 10 B1 02 04 74 94 01 32 33 11 11 AB 4D 56 73 02 02
39 00 10 B2 00 80 80 AE 05 07 5A 11 00 00 10 1E 70 03 D4
15 00 02 36 02
39 00 2D B4 00 FF 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 21 03 01 00 0F B8 8B 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 01 00 0F B8 01
39 05 22 D3 00 00 00 00 00 00 06 00 00 10 04 00 04 00 00 00 00 00 00 00 00 00 00 01 00 05 05 07 00 00 00 05 40
39 05 21 D5 18 18 19 19 18 18 21 20 01 00 07 06 05 04 03 02 18 18 18 18 18 18 2F 2F 30 30 31 31 18 18 18 18
39 05 21 D6 18 18 19 19 40 40 20 21 06 07 00 01 02 03 04 05 40 40 40 40 40 40 2F 2F 30 30 31 31 40 40 40 40
39 00 11 D8 A2 AA 02 A0 A2 A8 02 A0 B0 00 00 00 B0 00 00 00
15 00 02 BD 01
39 00 11 D8 B0 00 00 00 B0 00 00 00 E2 AA 03 F0 E2 AA 03 F0
15 00 02 BD 02
39 00 09 D8 E2 AA 03 F0 E2 AA 03 F0
15 00 02 BD 00
39 00 03 B6 8D 8D
39 05 37 E0 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77
05 C8 01 11
05 C8 01 29
];
panel-exit-sequence = [
05 78 01 28
05 00 01 10
];
disp0_timings0: display-timings {
native-mode = <&dsi0_timing0>;
dsi0_timing0: timing0 {
clock-frequency = <131376000>;
hactive = <1080>;
vactive = <1920>;
hsync-len = <10>;
hback-porch = <20>;
hfront-porch = <10>;
vsync-len = <5>;
vback-porch = <20>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi0: endpoint {
remote-endpoint = <&dsi0_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi0_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi0>;
};
};
};
};
&i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c2m4_xfer>;
gt911_dsi0: gt911@5d {
status = "okay";
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>;
irq-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>;
touchscreen-inverted-x = <1>;
touchscreen-inverted-y = <1>;
};
};
&mipi_dcphy0 {
status = "okay";
};
&route_dsi0 {
status = "okay";
connect = <&vp2_out_dsi0>;
};
&dsi0_in_vp2 {
status = "okay";
};

126
arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-dsi1-vp3-1080x1920-5.5inch-ebf410125.dtsi
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@ -1,126 +0,0 @@
&dsi1 {
status = "okay";
dsi1_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
backlight = <&backlight_dsi1>;
power-supply = <&mipi_dsi1_power>;
reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
enable-delay-ms = <35>;
prepare-delay-ms = <6>;
reset-delay-ms = <10>;
init-delay-ms = <50>;
unprepare-delay-ms = <0>;
disable-delay-ms = <20>;
size,width = <74>;
size,height = <133>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
39 00 04 B9 FF 83 99
15 00 02 D2 77
39 00 10 B1 02 04 74 94 01 32 33 11 11 AB 4D 56 73 02 02
39 00 10 B2 00 80 80 AE 05 07 5A 11 00 00 10 1E 70 03 D4
15 00 02 36 02
39 00 2D B4 00 FF 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 21 03 01 00 0F B8 8B 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 01 00 0F B8 01
39 05 22 D3 00 00 00 00 00 00 06 00 00 10 04 00 04 00 00 00 00 00 00 00 00 00 00 01 00 05 05 07 00 00 00 05 40
39 05 21 D5 18 18 19 19 18 18 21 20 01 00 07 06 05 04 03 02 18 18 18 18 18 18 2F 2F 30 30 31 31 18 18 18 18
39 05 21 D6 18 18 19 19 40 40 20 21 06 07 00 01 02 03 04 05 40 40 40 40 40 40 2F 2F 30 30 31 31 40 40 40 40
39 00 11 D8 A2 AA 02 A0 A2 A8 02 A0 B0 00 00 00 B0 00 00 00
15 00 02 BD 01
39 00 11 D8 B0 00 00 00 B0 00 00 00 E2 AA 03 F0 E2 AA 03 F0
15 00 02 BD 02
39 00 09 D8 E2 AA 03 F0 E2 AA 03 F0
15 00 02 BD 00
39 00 03 B6 8D 8D
39 05 37 E0 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77
05 C8 01 11
05 C8 01 29
];
panel-exit-sequence = [
05 78 01 28
05 00 01 10
];
disp1_timings0: display-timings {
native-mode = <&dsi1_timing0>;
dsi1_timing0: timing0 {
clock-frequency = <131376000>;
hactive = <1080>;
vactive = <1920>;
hsync-len = <10>;
hback-porch = <20>;
hfront-porch = <10>;
vsync-len = <5>;
vback-porch = <20>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi1: endpoint {
remote-endpoint = <&dsi1_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi1_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi1>;
};
};
};
};
&i2c5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c5m3_xfer>;
gt911_dsi1: gt911@5d {
status = "okay";
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PB7 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
irq-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
touchscreen-inverted-x = <1>;
touchscreen-inverted-y = <1>;
};
};
&mipi_dcphy1 {
status = "okay";
};
&route_dsi1 {
status = "okay";
connect = <&vp3_out_dsi1>;
};
&dsi1_in_vp3 {
status = "okay";
};

43
arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-hdmi0-vp0.dtsi
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@ -1,43 +0,0 @@
/ {
hdmi0_sound: hdmi0-sound {
status = "okay";
compatible = "rockchip,hdmi";
rockchip,mclk-fs = <128>;
rockchip,card-name = "rockchip-hdmi0";
rockchip,cpu = <&i2s5_8ch>;
rockchip,codec = <&hdmi0>;
rockchip,jack-det;
};
};
&i2s5_8ch {
status = "okay";
};
&route_hdmi0{
status = "okay";
connect = <&vp0_out_hdmi0>;
};
&hdmi0 {
enable-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
cec-enable = "true";
status = "okay";
};
&hdmi0_in_vp0 {
status = "okay";
};
&hdmi0_in_vp1 {
status = "disabled";
};
&hdmi0_in_vp2 {
status = "disabled";
};
&hdptxphy_hdmi0 {
status = "okay";
};

45
arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-hdmi1-vp0.dtsi
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@ -1,45 +0,0 @@
/ {
hdmi1_sound: hdmi1-sound {
status = "okay";
compatible = "rockchip,hdmi";
rockchip,mclk-fs = <128>;
rockchip,card-name = "rockchip-hdmi1";
rockchip,cpu = <&i2s6_8ch>;
rockchip,codec = <&hdmi1>;
rockchip,jack-det;
};
};
&i2s6_8ch {
status = "okay";
};
&route_hdmi1{
status = "okay";
connect = <&vp0_out_hdmi1>;
};
&hdmi1 {
enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
cec-enable = "true";
pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd &hdmim0_tx1_scl &hdmim0_tx1_sda>;
pinctrl-names = "default";
status = "okay";
};
&hdmi1_in_vp0 {
status = "okay";
};
&hdmi1_in_vp1 {
status = "disabled";
};
&hdmi1_in_vp2 {
status = "disabled";
};
&hdptxphy_hdmi1 {
status = "okay";
};

45
arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-hdmi1-vp2.dtsi
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@ -1,45 +0,0 @@
/ {
hdmi1_sound: hdmi1-sound {
status = "okay";
compatible = "rockchip,hdmi";
rockchip,mclk-fs = <128>;
rockchip,card-name = "rockchip-hdmi1";
rockchip,cpu = <&i2s6_8ch>;
rockchip,codec = <&hdmi1>;
rockchip,jack-det;
};
};
&i2s6_8ch {
status = "okay";
};
&route_hdmi1{
status = "okay";
connect = <&vp2_out_hdmi1>;
};
&hdmi1 {
enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
cec-enable = "true";
pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd &hdmim0_tx1_scl &hdmim0_tx1_sda>;
pinctrl-names = "default";
status = "okay";
};
&hdmi1_in_vp0 {
status = "disabled";
};
&hdmi1_in_vp1 {
status = "disabled";
};
&hdmi1_in_vp2 {
status = "okay";
};
&hdptxphy_hdmi1 {
status = "okay";
};

29
arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io-hdmirx.dtsi
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@ -1,29 +0,0 @@
/ {
hdmiin_sound: hdmiin-sound {
status = "okay";
compatible = "rockchip,hdmi";
rockchip,mclk-fs = <128>;
rockchip,format = "i2s";
rockchip,bitclock-master = <&hdmirx_ctrler>;
rockchip,frame-master = <&hdmirx_ctrler>;
rockchip,card-name = "rockchip-hdmiin";
rockchip,cpu = <&i2s7_8ch>;
rockchip,codec = <&hdmirx_ctrler 0>;
rockchip,jack-det;
};
};
&i2s7_8ch {
status = "okay";
};
&hdmirx_ctrler {
status = "okay";
#sound-dai-cells = <1>;
/* Effective level used to trigger HPD: 0-low, 1-high */
hpd-trigger-level = <1>;
hdmirx-det-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_det>;
pinctrl-names = "default";
};

1736
arch/arm64/boot/dts/rockchip/rk3588-lubancat-5io.dts
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17
arch/arm64/boot/dts/rockchip/rk3588-lubancat-5ioi.dts
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@ -1,17 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
* Copyright (c) 2025 EmbedFire <embedfire@embedfire.com>
*/
/dts-v1/;
#include "rk3588-lubancat-5io.dts"
// #include "rk3588j.dtsi"
/ {
/* RK3588 LubanCat-5IO Industrial */
model = "Embedfire LubanCat-5IOI";
compatible = "rockchip,rk3588-lubancat-5ioi", "rockchip,rk3588";
};

83
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-cam0.dtsi
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@ -1,83 +0,0 @@
/* Link path:
* sensor->csi2_dcphy0->mipi0_csi2->rkcif_mipi_lvds->rkcif_mipi_lvds_sditf->rkisp0_vir0
*/
&i2c1 {
status = "okay";
};
&dcphy0_dw9714 {
status = "disabled";
};
&dcphy0_ov5647 {
status = "disabled";
};
&dcphy0_ov5648 {
status = "disabled";
};
&dcphy0_ov8858 {
status = "disabled";
};
&dcphy0_ov13850 {
status = "disabled";
};
&dcphy0_imx415 {
status = "okay";
};
&dcphy0_gc08a8 {
status = "disabled";
};
&dcphy0_gc2053 {
status = "disabled";
};
&dcphy0_gc4653 {
status = "disabled";
};
&mipi_dcphy0 {
status = "okay";
};
&csi2_dcphy0 {
status = "okay";
};
&mipi0_csi2 {
status = "okay";
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds {
status = "okay";
};
&rkcif_mipi_lvds_sditf {
status = "okay";
};
&rkcif_mmu {
status = "okay";
};
&rkisp0 {
status = "okay";
};
&isp0_mmu {
status = "okay";
};
&rkisp0_vir0 {
status = "okay";
};

83
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-cam1.dtsi
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@ -1,83 +0,0 @@
/* Link path:
* sensor->csi2_dcphy1->mipi1_csi2->rkcif_mipi_lvds1->rkcif_mipi_lvds1_sditf->rkisp0_vir1
*/
&i2c5 {
status = "okay";
};
&dcphy1_dw9714 {
status = "disabled";
};
&dcphy1_ov5647 {
status = "disabled";
};
&dcphy1_ov5648 {
status = "disabled";
};
&dcphy1_ov8858 {
status = "disabled";
};
&dcphy1_ov13850 {
status = "disabled";
};
&dcphy1_imx415 {
status = "okay";
};
&dcphy1_gc08a8 {
status = "disabled";
};
&dcphy1_gc2053 {
status = "disabled";
};
&dcphy1_gc4653 {
status = "disabled";
};
&csi2_dcphy1 {
status = "okay";
};
&mipi1_csi2 {
status = "okay";
};
&mipi_dcphy1 {
status = "okay";
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds1 {
status = "okay";
};
&rkcif_mipi_lvds1_sditf {
status = "okay";
};
&rkcif_mmu {
status = "okay";
};
&rkisp0 {
status = "okay";
};
&isp0_mmu {
status = "okay";
};
&rkisp0_vir1 {
status = "okay";
};

79
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-cam2.dtsi
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@ -1,79 +0,0 @@
/* Link path:
* sensor->csi2_dphy0->mipi2_csi2->rkcif_mipi_lvds2->rkcif_mipi_lvds2_sditf->rkisp1_vir0
*/
&i2c6 {
status = "okay";
};
&dphy0_dw9714 {
status = "disabled";
};
&dphy0_ov5647 {
status = "disabled";
};
&dphy0_ov5648 {
status = "disabled";
};
&dphy0_ov8858 {
status = "disabled";
};
&dphy0_ov13850 {
status = "disabled";
};
&dphy0_imx415 {
status = "okay";
};
&dphy0_gc08a8 {
status = "disabled";
};
&dphy0_gc2053 {
status = "disabled";
};
&dphy0_gc4653 {
status = "disabled";
};
&csi2_dphy0 {
status = "okay";
};
&mipi2_csi2 {
status = "okay";
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds2 {
status = "okay";
};
&rkcif_mipi_lvds2_sditf {
status = "okay";
};
&rkcif_mmu {
status = "okay";
};
&rkisp1 {
status = "okay";
};
&isp1_mmu {
status = "okay";
};
&rkisp1_vir0 {
status = "okay";
};

1149
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-csi.dtsi
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42
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dp0-vp1.dtsi
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@ -1,42 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
* Copyright (c) 2023 EmbedFire <embedfire@embedfire.com>
*/
/ {
dp0_sound: dp0-sound {
status = "okay";
compatible = "rockchip,hdmi";
rockchip,card-name = "rockchip-dp0";
rockchip,mclk-fs = <512>;
rockchip,cpu = <&spdif_tx2>;
rockchip,codec = <&dp0 1>;
rockchip,jack-det;
};
};
&spdif_tx2 {
status = "okay";
};
&dp0 {
status = "okay";
};
&route_dp0 {
status = "okay";
connect = <&vp1_out_dp0>;
};
&dp0_in_vp0 {
status = "disabled";
};
&dp0_in_vp1 {
status = "okay";
};
&dp0_in_vp2 {
status = "disabled";
};

122
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi0-vp2-1024x600-7inch-ebf410173.dtsi
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@ -1,122 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*
*/
&mipi_dcphy0 {
status = "okay";
};
&route_dsi0 {
status = "okay";
connect = <&vp2_out_dsi0>;
};
&dsi0_in_vp2 {
status = "okay";
};
&dsi0 {
status = "okay";
dsi0_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
backlight = <&backlight_dsi0>;
power-supply = <&mipi_dsi0_power>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
enable-delay-ms = <35>;
prepare-delay-ms = <6>;
reset-delay-ms = <0>;
init-delay-ms = <20>;
unprepare-delay-ms = <0>;
disable-delay-ms = <20>;
size,width = <74>;
size,height = <133>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
15 00 02 80 AC
15 00 02 81 B8
15 00 02 82 09
15 00 02 83 78
15 00 02 84 7F
15 00 02 85 BB
15 00 02 86 70
05 C8 01 11
05 C8 01 29
];
panel-exit-sequence = [
05 78 01 28
05 00 01 10
];
disp0_timings0: display-timings {
native-mode = <&dsi0_timing0>;
dsi0_timing0: timing0 {
clock-frequency = <51668640>;
hactive = <1024>;
vactive = <600>;
hsync-len = <10>;
hback-porch = <160>;
hfront-porch = <160>;
vsync-len = <1>;
vback-porch = <23>;
vfront-porch = <12>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi0: endpoint {
remote-endpoint = <&dsi0_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi0_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi0>;
};
};
};
};
&i2c5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c5m3_xfer>;
gt911_dsi0: gt911@5d {
status = "okay";
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
irq-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
touchscreen-inverted-x = <1>;
touchscreen-inverted-y = <1>;
};
};

132
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi0-vp2-1080x1920-5.5inch-ebf410125.dtsi
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@ -1,132 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*
*/
&mipi_dcphy0 {
status = "okay";
};
&route_dsi0 {
status = "okay";
connect = <&vp2_out_dsi0>;
};
&dsi0_in_vp2 {
status = "okay";
};
&dsi0 {
status = "okay";
dsi0_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
backlight = <&backlight_dsi0>;
power-supply = <&mipi_dsi0_power>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
enable-delay-ms = <35>;
prepare-delay-ms = <6>;
reset-delay-ms = <10>;
init-delay-ms = <50>;
unprepare-delay-ms = <0>;
disable-delay-ms = <20>;
size,width = <74>;
size,height = <133>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
39 00 04 B9 FF 83 99
15 00 02 D2 77
39 00 10 B1 02 04 74 94 01 32 33 11 11 AB 4D 56 73 02 02
39 00 10 B2 00 80 80 AE 05 07 5A 11 00 00 10 1E 70 03 D4
15 00 02 36 02
39 00 2D B4 00 FF 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 21 03 01 00 0F B8 8B 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 01 00 0F B8 01
39 05 22 D3 00 00 00 00 00 00 06 00 00 10 04 00 04 00 00 00 00 00 00 00 00 00 00 01 00 05 05 07 00 00 00 05 40
39 05 21 D5 18 18 19 19 18 18 21 20 01 00 07 06 05 04 03 02 18 18 18 18 18 18 2F 2F 30 30 31 31 18 18 18 18
39 05 21 D6 18 18 19 19 40 40 20 21 06 07 00 01 02 03 04 05 40 40 40 40 40 40 2F 2F 30 30 31 31 40 40 40 40
39 00 11 D8 A2 AA 02 A0 A2 A8 02 A0 B0 00 00 00 B0 00 00 00
15 00 02 BD 01
39 00 11 D8 B0 00 00 00 B0 00 00 00 E2 AA 03 F0 E2 AA 03 F0
15 00 02 BD 02
39 00 09 D8 E2 AA 03 F0 E2 AA 03 F0
15 00 02 BD 00
39 00 03 B6 8D 8D
39 05 37 E0 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77
05 C8 01 11
05 C8 01 29
];
panel-exit-sequence = [
05 78 01 28
05 00 01 10
];
disp0_timings0: display-timings {
native-mode = <&dsi0_timing0>;
dsi0_timing0: timing0 {
clock-frequency = <131376000>;
hactive = <1080>;
vactive = <1920>;
hsync-len = <10>;
hback-porch = <20>;
hfront-porch = <10>;
vsync-len = <5>;
vback-porch = <20>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi0: endpoint {
remote-endpoint = <&dsi0_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi0_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi0>;
};
};
};
};
&i2c5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c5m3_xfer>;
gt911_dsi0: gt911@5d {
status = "okay";
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
irq-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
touchscreen-inverted-x = <1>;
touchscreen-inverted-y = <1>;
};
};

303
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi0-vp2-800x1280-10.1inch-ebf410177.dtsi
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@ -1,303 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*
*/
&mipi_dcphy0 {
status = "okay";
};
&route_dsi0 {
status = "okay";
connect = <&vp2_out_dsi0>;
};
&dsi0_in_vp2 {
status = "okay";
};
&dsi0 {
status = "okay";
dsi0_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
backlight = <&backlight_dsi0>;
power-supply = <&mipi_dsi0_power>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
enable-delay-ms = <35>;
prepare-delay-ms = <6>;
reset-delay-ms = <0>;
init-delay-ms = <20>;
unprepare-delay-ms = <0>;
disable-delay-ms = <20>;
size,width = <74>;
size,height = <133>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
39 05 04 FF 98 81 03
15 05 02 01 00
15 05 02 02 00
15 05 02 03 53
15 05 02 04 D3
15 05 02 05 00
15 05 02 06 0D
15 05 02 07 08
15 05 02 08 00
15 05 02 09 00
15 05 02 0a 00
15 05 02 0b 00
15 05 02 0c 00
15 05 02 0d 00
15 05 02 0e 00
15 05 02 0f 28
15 05 02 10 28
15 05 02 11 00
15 05 02 12 00
15 05 02 13 00
15 05 02 14 00
15 05 02 15 00
15 05 02 16 00
15 05 02 17 00
15 05 02 18 00
15 05 02 19 00
15 05 02 1a 00
15 05 02 1b 00
15 05 02 1d 00
15 05 02 1e 40
15 05 02 1f 80
15 05 02 20 06
15 05 02 21 01
15 05 02 22 00
15 05 02 23 00
15 05 02 24 00
15 05 02 25 00
15 05 02 26 00
15 05 02 27 00
15 05 02 28 33
15 05 02 29 33
15 05 02 2a 00
15 05 02 2b 00
15 05 02 2c 00
15 05 02 2d 00
15 05 02 2e 00
15 05 02 2f 00
15 05 02 30 00
15 05 02 31 00
15 05 02 32 00
15 05 02 33 00
15 05 02 34 03
15 05 02 35 00
15 05 02 36 00
15 05 02 37 00
15 05 02 38 96
15 05 02 39 00
15 05 02 3a 00
15 05 02 3b 00
15 05 02 3c 00
15 05 02 3d 00
15 05 02 3e 00
15 05 02 3f 00
15 05 02 40 00
15 05 02 41 00
15 05 02 42 00
15 05 02 43 00
15 05 02 44 00
15 05 02 50 00
15 05 02 51 23
15 05 02 52 45
15 05 02 53 67
15 05 02 54 89
15 05 02 55 AB
15 05 02 56 01
15 05 02 57 23
15 05 02 58 45
15 05 02 59 67
15 05 02 5a 89
15 05 02 5b AB
15 05 02 5c CD
15 05 02 5d EF
15 05 02 5e 00
15 05 02 5f 08
15 05 02 60 08
15 05 02 61 06
15 05 02 62 06
15 05 02 63 01
15 05 02 64 01
15 05 02 65 00
15 05 02 66 00
15 05 02 67 02
15 05 02 68 15
15 05 02 69 15
15 05 02 6a 14
15 05 02 6b 14
15 05 02 6c 0D
15 05 02 6d 0D
15 05 02 6e 0C
15 05 02 6f 0C
15 05 02 70 0F
15 05 02 71 0F
15 05 02 72 0E
15 05 02 73 0E
15 05 02 74 02
15 05 02 75 08
15 05 02 76 08
15 05 02 77 06
15 05 02 78 06
15 05 02 79 01
15 05 02 7a 01
15 05 02 7b 00
15 05 02 7c 00
15 05 02 7d 02
15 05 02 7e 15
15 05 02 7f 15
15 05 02 80 14
15 05 02 81 14
15 05 02 82 0D
15 05 02 83 0D
15 05 02 84 0C
15 05 02 85 0C
15 05 02 86 0F
15 05 02 87 0F
15 05 02 88 0E
15 05 02 89 0E
15 05 02 8A 02
39 05 04 FF 98 81 04
15 05 02 6E 2B
15 05 02 6F 37
15 05 02 3A 24
15 05 02 8D 1A
15 05 02 87 BA
15 05 02 B2 D1
15 05 02 88 0B
15 05 02 38 01
15 05 02 39 00
15 05 02 B5 02
15 05 02 31 25
15 05 02 3B 98
39 05 04 FF 98 81 01
15 05 02 22 0A
15 05 02 31 00
15 05 02 53 3D
15 05 02 55 3D
15 05 02 50 B5
15 05 02 51 AD
15 05 02 60 06
15 05 02 62 20
15 05 02 A0 00
15 05 02 A1 21
15 05 02 A2 35
15 05 02 A3 19
15 05 02 A4 1E
15 05 02 A5 33
15 05 02 A6 27
15 05 02 A7 26
15 05 02 A8 AF
15 05 02 A9 1B
15 05 02 AA 27
15 05 02 AB 8D
15 05 02 AC 1A
15 05 02 AD 1B
15 05 02 AE 50
15 05 02 AF 26
15 05 02 B0 2B
15 05 02 B1 54
15 05 02 B2 5E
15 05 02 B3 23
15 05 02 C0 00
15 05 02 C1 21
15 05 02 C2 35
15 05 02 C3 19
15 05 02 C4 1E
15 05 02 C5 33
15 05 02 C6 27
15 05 02 C7 26
15 05 02 C8 AF
15 05 02 C9 1B
15 05 02 CA 27
15 05 02 CB 8D
15 05 02 CC 1A
15 05 02 CD 1B
15 05 02 CE 50
15 05 02 CF 26
15 05 02 D0 2B
15 05 02 D1 54
15 05 02 D2 5E
15 05 02 D3 23
39 05 04 FF 98 81 00
15 78 02 11 00
15 05 02 29 00
];
panel-exit-sequence = [
05 78 01 28
05 00 01 10
];
disp0_timings0: display-timings {
native-mode = <&dsi0_timing0>;
dsi0_timing0: timing0 {
clock-frequency = <67000000>;
hactive = <800>;
vactive = <1280>;
hsync-len = <24>;
hback-porch = <24>;
hfront-porch = <12>;
vsync-len = <2>;
vback-porch = <9>;
vfront-porch = <7>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi0: endpoint {
remote-endpoint = <&dsi0_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi0_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi0>;
};
};
};
};
&i2c5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c5m3_xfer>;
gt911_dsi0: gt911@5d {
status = "okay";
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
irq-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
};
};

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arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi1-vp3-1024x600-7inch-ebf410173.dtsi
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@ -1,122 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*
*/
&mipi_dcphy1 {
status = "okay";
};
&route_dsi1 {
status = "okay";
connect = <&vp3_out_dsi1>;
};
&dsi1_in_vp3 {
status = "okay";
};
&dsi1 {
status = "okay";
dsi1_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
backlight = <&backlight_dsi1>;
power-supply = <&mipi_dsi1_power>;
reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
enable-delay-ms = <35>;
prepare-delay-ms = <6>;
reset-delay-ms = <0>;
init-delay-ms = <20>;
unprepare-delay-ms = <0>;
disable-delay-ms = <20>;
size,width = <74>;
size,height = <133>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
15 00 02 80 AC
15 00 02 81 B8
15 00 02 82 09
15 00 02 83 78
15 00 02 84 7F
15 00 02 85 BB
15 00 02 86 70
05 C8 01 11
05 C8 01 29
];
panel-exit-sequence = [
05 78 01 28
05 00 01 10
];
disp1_timings0: display-timings {
native-mode = <&dsi1_timing0>;
dsi1_timing0: timing0 {
clock-frequency = <51668640>;
hactive = <1024>;
vactive = <600>;
hsync-len = <10>;
hback-porch = <160>;
hfront-porch = <160>;
vsync-len = <1>;
vback-porch = <23>;
vfront-porch = <12>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi1: endpoint {
remote-endpoint = <&dsi1_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi1_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi1>;
};
};
};
};
&i2c6 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c6m3_xfer>;
gt911_dsi1: gt911@5d {
status = "okay";
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
irq-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
touchscreen-inverted-x = <1>;
touchscreen-inverted-y = <1>;
};
};

132
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi1-vp3-1080x1920-5.5inch-ebf410125.dtsi
View File

@ -1,132 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*
*/
&mipi_dcphy1 {
status = "okay";
};
&route_dsi1 {
status = "okay";
connect = <&vp3_out_dsi1>;
};
&dsi1_in_vp3 {
status = "okay";
};
&dsi1 {
status = "okay";
dsi1_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
backlight = <&backlight_dsi1>;
power-supply = <&mipi_dsi1_power>;
reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
enable-delay-ms = <35>;
prepare-delay-ms = <6>;
reset-delay-ms = <10>;
init-delay-ms = <50>;
unprepare-delay-ms = <0>;
disable-delay-ms = <20>;
size,width = <74>;
size,height = <133>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
39 00 04 B9 FF 83 99
15 00 02 D2 77
39 00 10 B1 02 04 74 94 01 32 33 11 11 AB 4D 56 73 02 02
39 00 10 B2 00 80 80 AE 05 07 5A 11 00 00 10 1E 70 03 D4
15 00 02 36 02
39 00 2D B4 00 FF 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 21 03 01 00 0F B8 8B 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 01 00 0F B8 01
39 05 22 D3 00 00 00 00 00 00 06 00 00 10 04 00 04 00 00 00 00 00 00 00 00 00 00 01 00 05 05 07 00 00 00 05 40
39 05 21 D5 18 18 19 19 18 18 21 20 01 00 07 06 05 04 03 02 18 18 18 18 18 18 2F 2F 30 30 31 31 18 18 18 18
39 05 21 D6 18 18 19 19 40 40 20 21 06 07 00 01 02 03 04 05 40 40 40 40 40 40 2F 2F 30 30 31 31 40 40 40 40
39 00 11 D8 A2 AA 02 A0 A2 A8 02 A0 B0 00 00 00 B0 00 00 00
15 00 02 BD 01
39 00 11 D8 B0 00 00 00 B0 00 00 00 E2 AA 03 F0 E2 AA 03 F0
15 00 02 BD 02
39 00 09 D8 E2 AA 03 F0 E2 AA 03 F0
15 00 02 BD 00
39 00 03 B6 8D 8D
39 05 37 E0 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77
05 C8 01 11
05 C8 01 29
];
panel-exit-sequence = [
05 78 01 28
05 00 01 10
];
disp1_timings0: display-timings {
native-mode = <&dsi1_timing0>;
dsi1_timing0: timing0 {
clock-frequency = <131376000>;
hactive = <1080>;
vactive = <1920>;
hsync-len = <10>;
hback-porch = <20>;
hfront-porch = <10>;
vsync-len = <5>;
vback-porch = <20>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi1: endpoint {
remote-endpoint = <&dsi1_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi1_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi1>;
};
};
};
};
&i2c6 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c6m3_xfer>;
gt911_dsi1: gt911@5d {
status = "okay";
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
irq-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
touchscreen-inverted-x = <1>;
touchscreen-inverted-y = <1>;
};
};

303
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-dsi1-vp3-800x1280-10.1inch-ebf410177.dtsi
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@ -1,303 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*
*/
&mipi_dcphy1 {
status = "okay";
};
&route_dsi1 {
status = "okay";
connect = <&vp3_out_dsi1>;
};
&dsi1_in_vp3 {
status = "okay";
};
&dsi1 {
status = "okay";
dsi1_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
backlight = <&backlight_dsi1>;
power-supply = <&mipi_dsi1_power>;
reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
enable-delay-ms = <35>;
prepare-delay-ms = <6>;
reset-delay-ms = <0>;
init-delay-ms = <20>;
unprepare-delay-ms = <0>;
disable-delay-ms = <20>;
size,width = <74>;
size,height = <133>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
39 05 04 FF 98 81 03
15 05 02 01 00
15 05 02 02 00
15 05 02 03 53
15 05 02 04 D3
15 05 02 05 00
15 05 02 06 0D
15 05 02 07 08
15 05 02 08 00
15 05 02 09 00
15 05 02 0a 00
15 05 02 0b 00
15 05 02 0c 00
15 05 02 0d 00
15 05 02 0e 00
15 05 02 0f 28
15 05 02 10 28
15 05 02 11 00
15 05 02 12 00
15 05 02 13 00
15 05 02 14 00
15 05 02 15 00
15 05 02 16 00
15 05 02 17 00
15 05 02 18 00
15 05 02 19 00
15 05 02 1a 00
15 05 02 1b 00
15 05 02 1d 00
15 05 02 1e 40
15 05 02 1f 80
15 05 02 20 06
15 05 02 21 01
15 05 02 22 00
15 05 02 23 00
15 05 02 24 00
15 05 02 25 00
15 05 02 26 00
15 05 02 27 00
15 05 02 28 33
15 05 02 29 33
15 05 02 2a 00
15 05 02 2b 00
15 05 02 2c 00
15 05 02 2d 00
15 05 02 2e 00
15 05 02 2f 00
15 05 02 30 00
15 05 02 31 00
15 05 02 32 00
15 05 02 33 00
15 05 02 34 03
15 05 02 35 00
15 05 02 36 00
15 05 02 37 00
15 05 02 38 96
15 05 02 39 00
15 05 02 3a 00
15 05 02 3b 00
15 05 02 3c 00
15 05 02 3d 00
15 05 02 3e 00
15 05 02 3f 00
15 05 02 40 00
15 05 02 41 00
15 05 02 42 00
15 05 02 43 00
15 05 02 44 00
15 05 02 50 00
15 05 02 51 23
15 05 02 52 45
15 05 02 53 67
15 05 02 54 89
15 05 02 55 AB
15 05 02 56 01
15 05 02 57 23
15 05 02 58 45
15 05 02 59 67
15 05 02 5a 89
15 05 02 5b AB
15 05 02 5c CD
15 05 02 5d EF
15 05 02 5e 00
15 05 02 5f 08
15 05 02 60 08
15 05 02 61 06
15 05 02 62 06
15 05 02 63 01
15 05 02 64 01
15 05 02 65 00
15 05 02 66 00
15 05 02 67 02
15 05 02 68 15
15 05 02 69 15
15 05 02 6a 14
15 05 02 6b 14
15 05 02 6c 0D
15 05 02 6d 0D
15 05 02 6e 0C
15 05 02 6f 0C
15 05 02 70 0F
15 05 02 71 0F
15 05 02 72 0E
15 05 02 73 0E
15 05 02 74 02
15 05 02 75 08
15 05 02 76 08
15 05 02 77 06
15 05 02 78 06
15 05 02 79 01
15 05 02 7a 01
15 05 02 7b 00
15 05 02 7c 00
15 05 02 7d 02
15 05 02 7e 15
15 05 02 7f 15
15 05 02 80 14
15 05 02 81 14
15 05 02 82 0D
15 05 02 83 0D
15 05 02 84 0C
15 05 02 85 0C
15 05 02 86 0F
15 05 02 87 0F
15 05 02 88 0E
15 05 02 89 0E
15 05 02 8A 02
39 05 04 FF 98 81 04
15 05 02 6E 2B
15 05 02 6F 37
15 05 02 3A 24
15 05 02 8D 1A
15 05 02 87 BA
15 05 02 B2 D1
15 05 02 88 0B
15 05 02 38 01
15 05 02 39 00
15 05 02 B5 02
15 05 02 31 25
15 05 02 3B 98
39 05 04 FF 98 81 01
15 05 02 22 0A
15 05 02 31 00
15 05 02 53 3D
15 05 02 55 3D
15 05 02 50 B5
15 05 02 51 AD
15 05 02 60 06
15 05 02 62 20
15 05 02 A0 00
15 05 02 A1 21
15 05 02 A2 35
15 05 02 A3 19
15 05 02 A4 1E
15 05 02 A5 33
15 05 02 A6 27
15 05 02 A7 26
15 05 02 A8 AF
15 05 02 A9 1B
15 05 02 AA 27
15 05 02 AB 8D
15 05 02 AC 1A
15 05 02 AD 1B
15 05 02 AE 50
15 05 02 AF 26
15 05 02 B0 2B
15 05 02 B1 54
15 05 02 B2 5E
15 05 02 B3 23
15 05 02 C0 00
15 05 02 C1 21
15 05 02 C2 35
15 05 02 C3 19
15 05 02 C4 1E
15 05 02 C5 33
15 05 02 C6 27
15 05 02 C7 26
15 05 02 C8 AF
15 05 02 C9 1B
15 05 02 CA 27
15 05 02 CB 8D
15 05 02 CC 1A
15 05 02 CD 1B
15 05 02 CE 50
15 05 02 CF 26
15 05 02 D0 2B
15 05 02 D1 54
15 05 02 D2 5E
15 05 02 D3 23
39 05 04 FF 98 81 00
15 78 02 11 00
15 05 02 29 00
];
panel-exit-sequence = [
05 78 01 28
05 00 01 10
];
disp1_timings0: display-timings {
native-mode = <&dsi1_timing0>;
dsi1_timing0: timing0 {
clock-frequency = <67000000>;
hactive = <800>;
vactive = <1280>;
hsync-len = <24>;
hback-porch = <24>;
hfront-porch = <12>;
vsync-len = <2>;
vback-porch = <9>;
vfront-porch = <7>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi1: endpoint {
remote-endpoint = <&dsi1_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi1_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi1>;
};
};
};
};
&i2c6 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c6m3_xfer>;
gt911_dsi1: gt911@5d {
status = "okay";
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
irq-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
};
};

48
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-hdmi0-vp0.dtsi
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@ -1,48 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
* Copyright (c) 2023 EmbedFire <embedfire@embedfire.com>
*/
/ {
hdmi0_sound: hdmi0-sound {
status = "okay";
compatible = "rockchip,hdmi";
rockchip,mclk-fs = <128>;
rockchip,card-name = "rockchip-hdmi0";
rockchip,cpu = <&i2s5_8ch>;
rockchip,codec = <&hdmi0>;
rockchip,jack-det;
};
};
&i2s5_8ch {
status = "okay";
};
&hdmi0 {
enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
cec-enable = "true";
status = "okay";
};
&route_hdmi0{
status = "okay";
connect = <&vp0_out_hdmi0>;
};
&hdmi0_in_vp0 {
status = "okay";
};
&hdmi0_in_vp1 {
status = "disabled";
};
&hdmi0_in_vp2 {
status = "disabled";
};
&hdptxphy_hdmi0 {
status = "okay";
};

26
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4-v1.dts
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@ -1,26 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
* Copyright (c) 2023 EmbedFire <embedfire@embedfire.com>
*/
/dts-v1/;
#include "rk3588s-lubancat-4.dts"
/ {
model = "Embedfire LubanCat-4 V1";
compatible = "embedfire,rk3588s-lubancat-4-v1", "rockchip,rk3588";
};
&pinctrl{
dsi {
dsi0_reset: dsi0-reset {
rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
};
tp1_irq: tp1-irq {
rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};

1530
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4.dts
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File diff suppressed because it is too large Load Diff

77
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-cam0.dtsi
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@ -1,77 +0,0 @@
/* Link path:
* sensor->csi2_dcphy0->mipi0_csi2->rkcif_mipi_lvds->rkcif_mipi_lvds_sditf->rkisp0_vir0
*/
&i2c2 {
status = "okay";
};
/* 对焦马达 可选 */
&dcphy0_dw9714 {
status = "disabled";
};
/* 摄像头 只能开启一个 */
&dcphy0_ov5647 {
status = "disabled";
};
&dcphy0_ov5648 {
status = "disabled";
};
&dcphy0_ov8858 {
status = "disabled";
};
&dcphy0_ov13850 {
status = "disabled";
};
&dcphy0_imx415 {
status = "okay";
};
&dcphy0_gc2093 {
status = "disabled";
};
&mipi_dcphy0 {
status = "okay";
};
&csi2_dcphy0 {
status = "okay";
};
&mipi0_csi2 {
status = "okay";
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds {
status = "okay";
};
&rkcif_mipi_lvds_sditf {
status = "okay";
};
&rkcif_mmu {
status = "okay";
};
&rkisp0 {
status = "okay";
};
&isp0_mmu {
status = "okay";
};
&rkisp0_vir0 {
status = "okay";
};

77
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-cam1.dtsi
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@ -1,77 +0,0 @@
/* Link path:
* sensor->csi2_dcphy1->mipi1_csi2->rkcif_mipi_lvds1->rkcif_mipi_lvds1_sditf->rkisp0_vir1
*/
&i2c5 {
status = "okay";
};
/* 对焦马达 可选 */
&dcphy1_dw9714 {
status = "disabled";
};
/* 摄像头 只能开启一个 */
&dcphy1_ov5647 {
status = "disabled";
};
&dcphy1_ov5648 {
status = "disabled";
};
&dcphy1_ov8858 {
status = "disabled";
};
&dcphy1_ov13850 {
status = "disabled";
};
&dcphy1_imx415 {
status = "okay";
};
&dcphy1_gc2093 {
status = "disabled";
};
&csi2_dcphy1 {
status = "okay";
};
&mipi1_csi2 {
status = "okay";
};
&mipi_dcphy1 {
status = "okay";
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds1 {
status = "okay";
};
&rkcif_mipi_lvds1_sditf {
status = "okay";
};
&rkcif_mmu {
status = "okay";
};
&rkisp0 {
status = "okay";
};
&isp0_mmu {
status = "okay";
};
&rkisp0_vir1 {
status = "okay";
};

77
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-cam2.dtsi
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@ -1,77 +0,0 @@
/* Link path:
* sensor->csi2_dphy1->mipi2_csi2->rkcif_mipi_lvds2->rkcif_mipi_lvds2_sditf->rkisp0_vir2
*/
&i2c1 {
status = "okay";
};
/* 对焦马达 可选 */
&dphy1_dw9714 {
status = "okay";
};
/* 摄像头 只能开启一个 */
&dphy1_ov5647 {
status = "disabled";
};
&dphy1_ov5648 {
status = "disabled";
};
&dphy1_ov8858 {
status = "disabled";
};
&dphy1_ov13850 {
status = "disabled";
};
&dphy1_imx415 {
status = "okay";
};
&dphy1_gc2093 {
status = "disabled";
};
&csi2_dphy0_hw {
status = "okay";
};
&csi2_dphy1 {
status = "okay";
};
&mipi2_csi2 {
status = "okay";
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds2 {
status = "okay";
};
&rkcif_mipi_lvds2_sditf {
status = "okay";
};
&rkcif_mmu {
status = "okay";
};
&rkisp0 {
status = "okay";
};
&isp0_mmu {
status = "okay";
};
&rkisp0_vir2 {
status = "okay";
};

77
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-cam3.dtsi
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@ -1,77 +0,0 @@
/* Link path:
* sensor->csi2_dphy2->mipi3_csi2->rkcif_mipi_lvds3->rkcif_mipi_lvds3_sditf->rkisp1_vir0
*/
&i2c8 {
status = "okay";
};
/* 对焦马达 可选 */
&dphy2_dw9714 {
status = "disabled";
};
/* 摄像头 只能开启一个 */
&dphy2_ov5647 {
status = "disabled";
};
&dphy2_ov5648 {
status = "disabled";
};
&dphy2_ov8858 {
status = "disabled";
};
&dphy2_ov13850 {
status = "disabled";
};
&dphy2_imx415 {
status = "okay";
};
&dphy2_gc2093 {
status = "disabled";
};
&csi2_dphy0_hw {
status = "okay";
};
&csi2_dphy2 {
status = "okay";
};
&mipi3_csi2 {
status = "okay";
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds3 {
status = "okay";
};
&rkcif_mipi_lvds3_sditf {
status = "okay";
};
&rkcif_mmu {
status = "okay";
};
&rkisp1 {
status = "okay";
};
&isp1_mmu {
status = "okay";
};
&rkisp1_vir0 {
status = "okay";
};

1280
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-csi.dtsi
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File diff suppressed because it is too large Load Diff

42
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dp0-vp1.dtsi
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@ -1,42 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
* Copyright (c) 2023 EmbedFire <embedfire@embedfire.com>
*/
/ {
dp0_sound: dp0-sound {
status = "okay";
compatible = "rockchip,hdmi";
rockchip,card-name = "rockchip-dp0";
rockchip,mclk-fs = <512>;
rockchip,cpu = <&spdif_tx2>;
rockchip,codec = <&dp0 1>;
rockchip,jack-det;
};
};
&spdif_tx2 {
status = "okay";
};
&dp0 {
status = "okay";
};
&route_dp0 {
status = "okay";
connect = <&vp1_out_dp0>;
};
&dp0_in_vp0 {
status = "disabled";
};
&dp0_in_vp1 {
status = "okay";
};
&dp0_in_vp2 {
status = "disabled";
};

122
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi0-vp2-1024x600-7inch-ebf410173.dtsi
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@ -1,122 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*
*/
&mipi_dcphy0 {
status = "okay";
};
&route_dsi0 {
status = "okay";
connect = <&vp2_out_dsi0>;
};
&dsi0_in_vp2 {
status = "okay";
};
&dsi0 {
status = "okay";
dsi0_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
backlight = <&backlight_dsi0>;
power-supply = <&mipi_dsi0_power>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
enable-delay-ms = <35>;
prepare-delay-ms = <6>;
reset-delay-ms = <0>;
init-delay-ms = <20>;
unprepare-delay-ms = <0>;
disable-delay-ms = <20>;
size,width = <74>;
size,height = <133>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
15 00 02 80 AC
15 00 02 81 B8
15 00 02 82 09
15 00 02 83 78
15 00 02 84 7F
15 00 02 85 BB
15 00 02 86 70
05 C8 01 11
05 C8 01 29
];
panel-exit-sequence = [
05 78 01 28
05 00 01 10
];
disp0_timings0: display-timings {
native-mode = <&dsi0_timing0>;
dsi0_timing0: timing0 {
clock-frequency = <51668640>;
hactive = <1024>;
vactive = <600>;
hsync-len = <10>;
hback-porch = <160>;
hfront-porch = <160>;
vsync-len = <1>;
vback-porch = <23>;
vfront-porch = <12>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi0: endpoint {
remote-endpoint = <&dsi0_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi0_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi0>;
};
};
};
};
&i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c2m4_xfer>;
gt911_dsi0: gt911@5d {
status = "okay";
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
irq-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>;
touchscreen-inverted-x = <1>;
touchscreen-inverted-y = <1>;
};
};

132
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi0-vp2-1080x1920-5.5inch-ebf410125.dtsi
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@ -1,132 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*
*/
&mipi_dcphy0 {
status = "okay";
};
&route_dsi0 {
status = "okay";
connect = <&vp2_out_dsi0>;
};
&dsi0_in_vp2 {
status = "okay";
};
&dsi0 {
status = "okay";
dsi0_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
backlight = <&backlight_dsi0>;
power-supply = <&mipi_dsi0_power>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
enable-delay-ms = <35>;
prepare-delay-ms = <6>;
reset-delay-ms = <10>;
init-delay-ms = <50>;
unprepare-delay-ms = <0>;
disable-delay-ms = <20>;
size,width = <74>;
size,height = <133>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
39 00 04 B9 FF 83 99
15 00 02 D2 77
39 00 10 B1 02 04 74 94 01 32 33 11 11 AB 4D 56 73 02 02
39 00 10 B2 00 80 80 AE 05 07 5A 11 00 00 10 1E 70 03 D4
15 00 02 36 02
39 00 2D B4 00 FF 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 21 03 01 00 0F B8 8B 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 01 00 0F B8 01
39 05 22 D3 00 00 00 00 00 00 06 00 00 10 04 00 04 00 00 00 00 00 00 00 00 00 00 01 00 05 05 07 00 00 00 05 40
39 05 21 D5 18 18 19 19 18 18 21 20 01 00 07 06 05 04 03 02 18 18 18 18 18 18 2F 2F 30 30 31 31 18 18 18 18
39 05 21 D6 18 18 19 19 40 40 20 21 06 07 00 01 02 03 04 05 40 40 40 40 40 40 2F 2F 30 30 31 31 40 40 40 40
39 00 11 D8 A2 AA 02 A0 A2 A8 02 A0 B0 00 00 00 B0 00 00 00
15 00 02 BD 01
39 00 11 D8 B0 00 00 00 B0 00 00 00 E2 AA 03 F0 E2 AA 03 F0
15 00 02 BD 02
39 00 09 D8 E2 AA 03 F0 E2 AA 03 F0
15 00 02 BD 00
39 00 03 B6 8D 8D
39 05 37 E0 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77
05 C8 01 11
05 C8 01 29
];
panel-exit-sequence = [
05 78 01 28
05 00 01 10
];
disp0_timings0: display-timings {
native-mode = <&dsi0_timing0>;
dsi0_timing0: timing0 {
clock-frequency = <131376000>;
hactive = <1080>;
vactive = <1920>;
hsync-len = <10>;
hback-porch = <20>;
hfront-porch = <10>;
vsync-len = <5>;
vback-porch = <20>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi0: endpoint {
remote-endpoint = <&dsi0_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi0_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi0>;
};
};
};
};
&i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c2m4_xfer>;
gt911_dsi0: gt911@5d {
status = "okay";
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
irq-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>;
touchscreen-inverted-x = <1>;
touchscreen-inverted-y = <1>;
};
};

303
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi0-vp2-800x1280-10.1inch-ebf410177.dtsi
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@ -1,303 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*
*/
&mipi_dcphy0 {
status = "okay";
};
&route_dsi0 {
status = "okay";
connect = <&vp2_out_dsi0>;
};
&dsi0_in_vp2 {
status = "okay";
};
&dsi0 {
status = "okay";
dsi0_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
backlight = <&backlight_dsi0>;
power-supply = <&mipi_dsi0_power>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
enable-delay-ms = <35>;
prepare-delay-ms = <6>;
reset-delay-ms = <0>;
init-delay-ms = <20>;
unprepare-delay-ms = <0>;
disable-delay-ms = <20>;
size,width = <74>;
size,height = <133>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
39 05 04 FF 98 81 03
15 05 02 01 00
15 05 02 02 00
15 05 02 03 53
15 05 02 04 D3
15 05 02 05 00
15 05 02 06 0D
15 05 02 07 08
15 05 02 08 00
15 05 02 09 00
15 05 02 0a 00
15 05 02 0b 00
15 05 02 0c 00
15 05 02 0d 00
15 05 02 0e 00
15 05 02 0f 28
15 05 02 10 28
15 05 02 11 00
15 05 02 12 00
15 05 02 13 00
15 05 02 14 00
15 05 02 15 00
15 05 02 16 00
15 05 02 17 00
15 05 02 18 00
15 05 02 19 00
15 05 02 1a 00
15 05 02 1b 00
15 05 02 1d 00
15 05 02 1e 40
15 05 02 1f 80
15 05 02 20 06
15 05 02 21 01
15 05 02 22 00
15 05 02 23 00
15 05 02 24 00
15 05 02 25 00
15 05 02 26 00
15 05 02 27 00
15 05 02 28 33
15 05 02 29 33
15 05 02 2a 00
15 05 02 2b 00
15 05 02 2c 00
15 05 02 2d 00
15 05 02 2e 00
15 05 02 2f 00
15 05 02 30 00
15 05 02 31 00
15 05 02 32 00
15 05 02 33 00
15 05 02 34 03
15 05 02 35 00
15 05 02 36 00
15 05 02 37 00
15 05 02 38 96
15 05 02 39 00
15 05 02 3a 00
15 05 02 3b 00
15 05 02 3c 00
15 05 02 3d 00
15 05 02 3e 00
15 05 02 3f 00
15 05 02 40 00
15 05 02 41 00
15 05 02 42 00
15 05 02 43 00
15 05 02 44 00
15 05 02 50 00
15 05 02 51 23
15 05 02 52 45
15 05 02 53 67
15 05 02 54 89
15 05 02 55 AB
15 05 02 56 01
15 05 02 57 23
15 05 02 58 45
15 05 02 59 67
15 05 02 5a 89
15 05 02 5b AB
15 05 02 5c CD
15 05 02 5d EF
15 05 02 5e 00
15 05 02 5f 08
15 05 02 60 08
15 05 02 61 06
15 05 02 62 06
15 05 02 63 01
15 05 02 64 01
15 05 02 65 00
15 05 02 66 00
15 05 02 67 02
15 05 02 68 15
15 05 02 69 15
15 05 02 6a 14
15 05 02 6b 14
15 05 02 6c 0D
15 05 02 6d 0D
15 05 02 6e 0C
15 05 02 6f 0C
15 05 02 70 0F
15 05 02 71 0F
15 05 02 72 0E
15 05 02 73 0E
15 05 02 74 02
15 05 02 75 08
15 05 02 76 08
15 05 02 77 06
15 05 02 78 06
15 05 02 79 01
15 05 02 7a 01
15 05 02 7b 00
15 05 02 7c 00
15 05 02 7d 02
15 05 02 7e 15
15 05 02 7f 15
15 05 02 80 14
15 05 02 81 14
15 05 02 82 0D
15 05 02 83 0D
15 05 02 84 0C
15 05 02 85 0C
15 05 02 86 0F
15 05 02 87 0F
15 05 02 88 0E
15 05 02 89 0E
15 05 02 8A 02
39 05 04 FF 98 81 04
15 05 02 6E 2B
15 05 02 6F 37
15 05 02 3A 24
15 05 02 8D 1A
15 05 02 87 BA
15 05 02 B2 D1
15 05 02 88 0B
15 05 02 38 01
15 05 02 39 00
15 05 02 B5 02
15 05 02 31 25
15 05 02 3B 98
39 05 04 FF 98 81 01
15 05 02 22 0A
15 05 02 31 00
15 05 02 53 3D
15 05 02 55 3D
15 05 02 50 B5
15 05 02 51 AD
15 05 02 60 06
15 05 02 62 20
15 05 02 A0 00
15 05 02 A1 21
15 05 02 A2 35
15 05 02 A3 19
15 05 02 A4 1E
15 05 02 A5 33
15 05 02 A6 27
15 05 02 A7 26
15 05 02 A8 AF
15 05 02 A9 1B
15 05 02 AA 27
15 05 02 AB 8D
15 05 02 AC 1A
15 05 02 AD 1B
15 05 02 AE 50
15 05 02 AF 26
15 05 02 B0 2B
15 05 02 B1 54
15 05 02 B2 5E
15 05 02 B3 23
15 05 02 C0 00
15 05 02 C1 21
15 05 02 C2 35
15 05 02 C3 19
15 05 02 C4 1E
15 05 02 C5 33
15 05 02 C6 27
15 05 02 C7 26
15 05 02 C8 AF
15 05 02 C9 1B
15 05 02 CA 27
15 05 02 CB 8D
15 05 02 CC 1A
15 05 02 CD 1B
15 05 02 CE 50
15 05 02 CF 26
15 05 02 D0 2B
15 05 02 D1 54
15 05 02 D2 5E
15 05 02 D3 23
39 05 04 FF 98 81 00
15 78 02 11 00
15 05 02 29 00
];
panel-exit-sequence = [
05 78 01 28
05 00 01 10
];
disp0_timings0: display-timings {
native-mode = <&dsi0_timing0>;
dsi0_timing0: timing0 {
clock-frequency = <67000000>;
hactive = <800>;
vactive = <1280>;
hsync-len = <24>;
hback-porch = <24>;
hfront-porch = <12>;
vsync-len = <2>;
vback-porch = <9>;
vfront-porch = <7>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi0: endpoint {
remote-endpoint = <&dsi0_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi0_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi0>;
};
};
};
};
&i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c2m4_xfer>;
gt911_dsi0: gt911@5d {
status = "okay";
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
irq-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>;
};
};

310
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi0-vp2-800x1280-10.1inch-s8001280b1060b.dtsi
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@ -1,310 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*
*/
&mipi_dcphy0 {
status = "okay";
};
&route_dsi0 {
status = "okay";
connect = <&vp2_out_dsi0>;
};
&dsi0_in_vp2 {
status = "okay";
};
&dsi0 {
status = "okay";
dsi0_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
backlight = <&backlight_dsi0>;
power-supply = <&mipi_dsi0_power>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
enable-delay-ms = <35>;
prepare-delay-ms = <6>;
reset-delay-ms = <0>;
init-delay-ms = <20>;
unprepare-delay-ms = <0>;
disable-delay-ms = <20>;
size,width = <74>;
size,height = <133>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
15 00 02 E0 00
15 00 02 E1 93
15 00 02 E2 65
15 00 02 E3 F8
15 00 02 80 03
15 00 02 E0 01
15 00 02 00 00
15 00 02 01 3B
15 00 02 0C 74
15 00 02 17 00
15 00 02 18 AF
15 00 02 19 00
15 00 02 1A 00
15 00 02 1B AF
15 00 02 1C 00
15 00 02 35 26
15 00 02 37 09
15 00 02 38 04
15 00 02 39 00
15 00 02 3A 01
15 00 02 3C 78
15 00 02 3D FF
15 00 02 3E FF
15 00 02 3F 7F
15 00 02 40 06
15 00 02 41 A0
15 00 02 42 81
15 00 02 43 1E
15 00 02 44 0B
15 00 02 45 28
15 00 02 55 02
15 00 02 57 69
15 00 02 59 0A
15 00 02 5A 2A
15 00 02 5B 17
15 00 02 5D 7F
15 00 02 5E 6B
15 00 02 5F 5C
15 00 02 60 4F
15 00 02 61 4D
15 00 02 62 3F
15 00 02 63 42
15 00 02 64 2B
15 00 02 65 44
15 00 02 66 43
15 00 02 67 43
15 00 02 68 63
15 00 02 69 52
15 00 02 6A 5A
15 00 02 6B 4F
15 00 02 6C 4E
15 00 02 6D 20
15 00 02 6E 0F
15 00 02 6F 00
15 00 02 70 7F
15 00 02 71 6B
15 00 02 72 5C
15 00 02 73 4F
15 00 02 74 4D
15 00 02 75 3F
15 00 02 76 42
15 00 02 77 2B
15 00 02 78 44
15 00 02 79 43
15 00 02 7A 43
15 00 02 7B 63
15 00 02 7C 52
15 00 02 7D 5A
15 00 02 7E 4F
15 00 02 7F 4E
15 00 02 80 20
15 00 02 81 0F
15 00 02 82 00
15 00 02 E0 02
15 00 02 00 42
15 00 02 01 42
15 00 02 02 40
15 00 02 03 40
15 00 02 04 5E
15 00 02 05 5E
15 00 02 06 5F
15 00 02 07 5F
15 00 02 08 5F
15 00 02 09 57
15 00 02 0A 57
15 00 02 0B 77
15 00 02 0C 77
15 00 02 0D 47
15 00 02 0E 47
15 00 02 0F 45
15 00 02 10 45
15 00 02 11 4B
15 00 02 12 4B
15 00 02 13 49
15 00 02 14 49
15 00 02 15 5F
15 00 02 16 41
15 00 02 17 41
15 00 02 18 40
15 00 02 19 40
15 00 02 1A 5E
15 00 02 1B 5E
15 00 02 1C 5F
15 00 02 1D 5F
15 00 02 1E 5F
15 00 02 1F 57
15 00 02 20 57
15 00 02 21 77
15 00 02 22 77
15 00 02 23 46
15 00 02 24 46
15 00 02 25 44
15 00 02 26 44
15 00 02 27 4A
15 00 02 28 4A
15 00 02 29 48
15 00 02 2A 48
15 00 02 2B 5F
15 00 02 2C 01
15 00 02 2D 01
15 00 02 2E 00
15 00 02 2F 00
15 00 02 30 1F
15 00 02 31 1F
15 00 02 32 1E
15 00 02 33 1E
15 00 02 34 1F
15 00 02 35 17
15 00 02 36 17
15 00 02 37 37
15 00 02 38 37
15 00 02 39 08
15 00 02 3A 08
15 00 02 3B 0A
15 00 02 3C 0A
15 00 02 3D 04
15 00 02 3E 04
15 00 02 3F 06
15 00 02 40 06
15 00 02 41 1F
15 00 02 42 02
15 00 02 43 02
15 00 02 44 00
15 00 02 45 00
15 00 02 46 1F
15 00 02 47 1F
15 00 02 48 1E
15 00 02 49 1E
15 00 02 4A 1F
15 00 02 4B 17
15 00 02 4C 17
15 00 02 4D 37
15 00 02 4E 37
15 00 02 4F 09
15 00 02 50 09
15 00 02 51 0B
15 00 02 52 0B
15 00 02 53 05
15 00 02 54 05
15 00 02 55 07
15 00 02 56 07
15 00 02 57 1F
15 00 02 58 40
15 00 02 5B 30
15 00 02 5C 00
15 00 02 5D 34
15 00 02 5E 05
15 00 02 5F 02
15 00 02 63 00
15 00 02 64 6A
15 00 02 67 73
15 00 02 68 05
15 00 02 69 08
15 00 02 6A 6A
15 00 02 6B 08
15 00 02 6C 00
15 00 02 6D 00
15 00 02 6E 00
15 00 02 6F 88
15 00 02 75 FF
15 00 02 77 DD
15 00 02 78 2A
15 00 02 79 15
15 00 02 7A 17
15 00 02 7D 14
15 00 02 7E 82
15 00 02 E0 04
15 00 02 00 0E
15 00 02 02 B3
15 00 02 09 61
15 00 02 0E 48
15 00 02 E0 00
15 00 02 E6 02
15 00 02 E7 0C
15 78 02 11 00
15 00 02 E0 00
15 05 02 29 00
];
panel-exit-sequence = [
05 78 01 28
05 00 01 10
];
disp0_timings0: display-timings {
native-mode = <&dsi0_timing0>;
dsi0_timing0: timing0 {
clock-frequency = <69801600>;
hactive = <800>;
vactive = <1280>;
hsync-len = <20>;
hback-porch = <20>;
hfront-porch = <40>;
vsync-len = <4>;
vback-porch = <8>;
vfront-porch = <30>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi0: endpoint {
remote-endpoint = <&dsi0_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi0_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi0>;
};
};
};
};
&i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c2m4_xfer>;
gt911_dsi0: gt911@5d {
status = "okay";
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
irq-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>;
touchscreen-inverted-x = <1>;
touchscreen-swapped-x-y = <1>;
};
};

122
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi1-vp3-1024x600-7inch-ebf410173.dtsi
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@ -1,122 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*
*/
&mipi_dcphy1 {
status = "okay";
};
&route_dsi1 {
status = "okay";
connect = <&vp3_out_dsi1>;
};
&dsi1_in_vp3 {
status = "okay";
};
&dsi1 {
status = "okay";
dsi1_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
backlight = <&backlight_dsi1>;
power-supply = <&mipi_dsi1_power>;
reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>;
enable-delay-ms = <35>;
prepare-delay-ms = <6>;
reset-delay-ms = <0>;
init-delay-ms = <20>;
unprepare-delay-ms = <0>;
disable-delay-ms = <20>;
size,width = <74>;
size,height = <133>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
15 00 02 80 AC
15 00 02 81 B8
15 00 02 82 09
15 00 02 83 78
15 00 02 84 7F
15 00 02 85 BB
15 00 02 86 70
05 C8 01 11
05 C8 01 29
];
panel-exit-sequence = [
05 78 01 28
05 00 01 10
];
disp1_timings0: display-timings {
native-mode = <&dsi1_timing0>;
dsi1_timing0: timing0 {
clock-frequency = <51668640>;
hactive = <1024>;
vactive = <600>;
hsync-len = <10>;
hback-porch = <160>;
hfront-porch = <160>;
vsync-len = <1>;
vback-porch = <23>;
vfront-porch = <12>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi1: endpoint {
remote-endpoint = <&dsi1_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi1_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi1>;
};
};
};
};
&i2c5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c5m3_xfer>;
gt911_dsi1: gt911@5d {
status = "okay";
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PB7 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>;
irq-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
touchscreen-inverted-x = <1>;
touchscreen-inverted-y = <1>;
};
};

132
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi1-vp3-1080x1920-5.5inch-ebf410125.dtsi
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@ -1,132 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*
*/
&mipi_dcphy1 {
status = "okay";
};
&route_dsi1 {
status = "okay";
connect = <&vp3_out_dsi1>;
};
&dsi1_in_vp3 {
status = "okay";
};
&dsi1 {
status = "okay";
dsi1_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
backlight = <&backlight_dsi1>;
power-supply = <&mipi_dsi1_power>;
reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>;
enable-delay-ms = <35>;
prepare-delay-ms = <6>;
reset-delay-ms = <10>;
init-delay-ms = <50>;
unprepare-delay-ms = <0>;
disable-delay-ms = <20>;
size,width = <74>;
size,height = <133>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
39 00 04 B9 FF 83 99
15 00 02 D2 77
39 00 10 B1 02 04 74 94 01 32 33 11 11 AB 4D 56 73 02 02
39 00 10 B2 00 80 80 AE 05 07 5A 11 00 00 10 1E 70 03 D4
15 00 02 36 02
39 00 2D B4 00 FF 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 21 03 01 00 0F B8 8B 02 C0 02 C0 00 00 08 00 04 06 00 32 04 0A 08 01 00 0F B8 01
39 05 22 D3 00 00 00 00 00 00 06 00 00 10 04 00 04 00 00 00 00 00 00 00 00 00 00 01 00 05 05 07 00 00 00 05 40
39 05 21 D5 18 18 19 19 18 18 21 20 01 00 07 06 05 04 03 02 18 18 18 18 18 18 2F 2F 30 30 31 31 18 18 18 18
39 05 21 D6 18 18 19 19 40 40 20 21 06 07 00 01 02 03 04 05 40 40 40 40 40 40 2F 2F 30 30 31 31 40 40 40 40
39 00 11 D8 A2 AA 02 A0 A2 A8 02 A0 B0 00 00 00 B0 00 00 00
15 00 02 BD 01
39 00 11 D8 B0 00 00 00 B0 00 00 00 E2 AA 03 F0 E2 AA 03 F0
15 00 02 BD 02
39 00 09 D8 E2 AA 03 F0 E2 AA 03 F0
15 00 02 BD 00
39 00 03 B6 8D 8D
39 05 37 E0 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77 00 0E 19 13 2E 39 48 44 4D 57 5F 66 6C 76 7F 85 8A 95 9A A4 9B AB B0 5C 58 64 77
05 C8 01 11
05 C8 01 29
];
panel-exit-sequence = [
05 78 01 28
05 00 01 10
];
disp1_timings0: display-timings {
native-mode = <&dsi1_timing0>;
dsi1_timing0: timing0 {
clock-frequency = <131376000>;
hactive = <1080>;
vactive = <1920>;
hsync-len = <10>;
hback-porch = <20>;
hfront-porch = <10>;
vsync-len = <5>;
vback-porch = <20>;
vfront-porch = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi1: endpoint {
remote-endpoint = <&dsi1_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi1_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi1>;
};
};
};
};
&i2c5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c5m3_xfer>;
gt911_dsi1: gt911@5d {
status = "okay";
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PB7 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>;
irq-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
touchscreen-inverted-x = <1>;
touchscreen-inverted-y = <1>;
};
};

303
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi1-vp3-800x1280-10.1inch-ebf410177.dtsi
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@ -1,303 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*
*/
&mipi_dcphy1 {
status = "okay";
};
&route_dsi1 {
status = "okay";
connect = <&vp3_out_dsi1>;
};
&dsi1_in_vp3 {
status = "okay";
};
&dsi1 {
status = "okay";
dsi1_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
backlight = <&backlight_dsi1>;
power-supply = <&mipi_dsi1_power>;
reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>;
enable-delay-ms = <35>;
prepare-delay-ms = <6>;
reset-delay-ms = <0>;
init-delay-ms = <20>;
unprepare-delay-ms = <0>;
disable-delay-ms = <20>;
size,width = <74>;
size,height = <133>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
39 05 04 FF 98 81 03
15 05 02 01 00
15 05 02 02 00
15 05 02 03 53
15 05 02 04 D3
15 05 02 05 00
15 05 02 06 0D
15 05 02 07 08
15 05 02 08 00
15 05 02 09 00
15 05 02 0a 00
15 05 02 0b 00
15 05 02 0c 00
15 05 02 0d 00
15 05 02 0e 00
15 05 02 0f 28
15 05 02 10 28
15 05 02 11 00
15 05 02 12 00
15 05 02 13 00
15 05 02 14 00
15 05 02 15 00
15 05 02 16 00
15 05 02 17 00
15 05 02 18 00
15 05 02 19 00
15 05 02 1a 00
15 05 02 1b 00
15 05 02 1d 00
15 05 02 1e 40
15 05 02 1f 80
15 05 02 20 06
15 05 02 21 01
15 05 02 22 00
15 05 02 23 00
15 05 02 24 00
15 05 02 25 00
15 05 02 26 00
15 05 02 27 00
15 05 02 28 33
15 05 02 29 33
15 05 02 2a 00
15 05 02 2b 00
15 05 02 2c 00
15 05 02 2d 00
15 05 02 2e 00
15 05 02 2f 00
15 05 02 30 00
15 05 02 31 00
15 05 02 32 00
15 05 02 33 00
15 05 02 34 03
15 05 02 35 00
15 05 02 36 00
15 05 02 37 00
15 05 02 38 96
15 05 02 39 00
15 05 02 3a 00
15 05 02 3b 00
15 05 02 3c 00
15 05 02 3d 00
15 05 02 3e 00
15 05 02 3f 00
15 05 02 40 00
15 05 02 41 00
15 05 02 42 00
15 05 02 43 00
15 05 02 44 00
15 05 02 50 00
15 05 02 51 23
15 05 02 52 45
15 05 02 53 67
15 05 02 54 89
15 05 02 55 AB
15 05 02 56 01
15 05 02 57 23
15 05 02 58 45
15 05 02 59 67
15 05 02 5a 89
15 05 02 5b AB
15 05 02 5c CD
15 05 02 5d EF
15 05 02 5e 00
15 05 02 5f 08
15 05 02 60 08
15 05 02 61 06
15 05 02 62 06
15 05 02 63 01
15 05 02 64 01
15 05 02 65 00
15 05 02 66 00
15 05 02 67 02
15 05 02 68 15
15 05 02 69 15
15 05 02 6a 14
15 05 02 6b 14
15 05 02 6c 0D
15 05 02 6d 0D
15 05 02 6e 0C
15 05 02 6f 0C
15 05 02 70 0F
15 05 02 71 0F
15 05 02 72 0E
15 05 02 73 0E
15 05 02 74 02
15 05 02 75 08
15 05 02 76 08
15 05 02 77 06
15 05 02 78 06
15 05 02 79 01
15 05 02 7a 01
15 05 02 7b 00
15 05 02 7c 00
15 05 02 7d 02
15 05 02 7e 15
15 05 02 7f 15
15 05 02 80 14
15 05 02 81 14
15 05 02 82 0D
15 05 02 83 0D
15 05 02 84 0C
15 05 02 85 0C
15 05 02 86 0F
15 05 02 87 0F
15 05 02 88 0E
15 05 02 89 0E
15 05 02 8A 02
39 05 04 FF 98 81 04
15 05 02 6E 2B
15 05 02 6F 37
15 05 02 3A 24
15 05 02 8D 1A
15 05 02 87 BA
15 05 02 B2 D1
15 05 02 88 0B
15 05 02 38 01
15 05 02 39 00
15 05 02 B5 02
15 05 02 31 25
15 05 02 3B 98
39 05 04 FF 98 81 01
15 05 02 22 0A
15 05 02 31 00
15 05 02 53 3D
15 05 02 55 3D
15 05 02 50 B5
15 05 02 51 AD
15 05 02 60 06
15 05 02 62 20
15 05 02 A0 00
15 05 02 A1 21
15 05 02 A2 35
15 05 02 A3 19
15 05 02 A4 1E
15 05 02 A5 33
15 05 02 A6 27
15 05 02 A7 26
15 05 02 A8 AF
15 05 02 A9 1B
15 05 02 AA 27
15 05 02 AB 8D
15 05 02 AC 1A
15 05 02 AD 1B
15 05 02 AE 50
15 05 02 AF 26
15 05 02 B0 2B
15 05 02 B1 54
15 05 02 B2 5E
15 05 02 B3 23
15 05 02 C0 00
15 05 02 C1 21
15 05 02 C2 35
15 05 02 C3 19
15 05 02 C4 1E
15 05 02 C5 33
15 05 02 C6 27
15 05 02 C7 26
15 05 02 C8 AF
15 05 02 C9 1B
15 05 02 CA 27
15 05 02 CB 8D
15 05 02 CC 1A
15 05 02 CD 1B
15 05 02 CE 50
15 05 02 CF 26
15 05 02 D0 2B
15 05 02 D1 54
15 05 02 D2 5E
15 05 02 D3 23
39 05 04 FF 98 81 00
15 78 02 11 00
15 05 02 29 00
];
panel-exit-sequence = [
05 78 01 28
05 00 01 10
];
disp1_timings0: display-timings {
native-mode = <&dsi1_timing0>;
dsi1_timing0: timing0 {
clock-frequency = <67000000>;
hactive = <800>;
vactive = <1280>;
hsync-len = <24>;
hback-porch = <24>;
hfront-porch = <12>;
vsync-len = <2>;
vback-porch = <9>;
vfront-porch = <7>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi1: endpoint {
remote-endpoint = <&dsi1_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi1_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi1>;
};
};
};
};
&i2c5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c5m3_xfer>;
gt911_dsi1: gt911@5d {
status = "okay";
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PB7 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>;
irq-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
};
};

310
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-dsi1-vp3-800x1280-10.1inch-s8001280b1060b.dtsi
View File

@ -1,310 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*
*/
&mipi_dcphy1 {
status = "okay";
};
&route_dsi1 {
status = "okay";
connect = <&vp3_out_dsi1>;
};
&dsi1_in_vp3 {
status = "okay";
};
&dsi1 {
status = "okay";
dsi1_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
backlight = <&backlight_dsi1>;
power-supply = <&mipi_dsi1_power>;
reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>;
enable-delay-ms = <35>;
prepare-delay-ms = <6>;
reset-delay-ms = <0>;
init-delay-ms = <20>;
unprepare-delay-ms = <0>;
disable-delay-ms = <20>;
size,width = <74>;
size,height = <133>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
15 00 02 E0 00
15 00 02 E1 93
15 00 02 E2 65
15 00 02 E3 F8
15 00 02 80 03
15 00 02 E0 01
15 00 02 00 00
15 00 02 01 3B
15 00 02 0C 74
15 00 02 17 00
15 00 02 18 AF
15 00 02 19 00
15 00 02 1A 00
15 00 02 1B AF
15 00 02 1C 00
15 00 02 35 26
15 00 02 37 09
15 00 02 38 04
15 00 02 39 00
15 00 02 3A 01
15 00 02 3C 78
15 00 02 3D FF
15 00 02 3E FF
15 00 02 3F 7F
15 00 02 40 06
15 00 02 41 A0
15 00 02 42 81
15 00 02 43 1E
15 00 02 44 0B
15 00 02 45 28
15 00 02 55 02
15 00 02 57 69
15 00 02 59 0A
15 00 02 5A 2A
15 00 02 5B 17
15 00 02 5D 7F
15 00 02 5E 6B
15 00 02 5F 5C
15 00 02 60 4F
15 00 02 61 4D
15 00 02 62 3F
15 00 02 63 42
15 00 02 64 2B
15 00 02 65 44
15 00 02 66 43
15 00 02 67 43
15 00 02 68 63
15 00 02 69 52
15 00 02 6A 5A
15 00 02 6B 4F
15 00 02 6C 4E
15 00 02 6D 20
15 00 02 6E 0F
15 00 02 6F 00
15 00 02 70 7F
15 00 02 71 6B
15 00 02 72 5C
15 00 02 73 4F
15 00 02 74 4D
15 00 02 75 3F
15 00 02 76 42
15 00 02 77 2B
15 00 02 78 44
15 00 02 79 43
15 00 02 7A 43
15 00 02 7B 63
15 00 02 7C 52
15 00 02 7D 5A
15 00 02 7E 4F
15 00 02 7F 4E
15 00 02 80 20
15 00 02 81 0F
15 00 02 82 00
15 00 02 E0 02
15 00 02 00 42
15 00 02 01 42
15 00 02 02 40
15 00 02 03 40
15 00 02 04 5E
15 00 02 05 5E
15 00 02 06 5F
15 00 02 07 5F
15 00 02 08 5F
15 00 02 09 57
15 00 02 0A 57
15 00 02 0B 77
15 00 02 0C 77
15 00 02 0D 47
15 00 02 0E 47
15 00 02 0F 45
15 00 02 10 45
15 00 02 11 4B
15 00 02 12 4B
15 00 02 13 49
15 00 02 14 49
15 00 02 15 5F
15 00 02 16 41
15 00 02 17 41
15 00 02 18 40
15 00 02 19 40
15 00 02 1A 5E
15 00 02 1B 5E
15 00 02 1C 5F
15 00 02 1D 5F
15 00 02 1E 5F
15 00 02 1F 57
15 00 02 20 57
15 00 02 21 77
15 00 02 22 77
15 00 02 23 46
15 00 02 24 46
15 00 02 25 44
15 00 02 26 44
15 00 02 27 4A
15 00 02 28 4A
15 00 02 29 48
15 00 02 2A 48
15 00 02 2B 5F
15 00 02 2C 01
15 00 02 2D 01
15 00 02 2E 00
15 00 02 2F 00
15 00 02 30 1F
15 00 02 31 1F
15 00 02 32 1E
15 00 02 33 1E
15 00 02 34 1F
15 00 02 35 17
15 00 02 36 17
15 00 02 37 37
15 00 02 38 37
15 00 02 39 08
15 00 02 3A 08
15 00 02 3B 0A
15 00 02 3C 0A
15 00 02 3D 04
15 00 02 3E 04
15 00 02 3F 06
15 00 02 40 06
15 00 02 41 1F
15 00 02 42 02
15 00 02 43 02
15 00 02 44 00
15 00 02 45 00
15 00 02 46 1F
15 00 02 47 1F
15 00 02 48 1E
15 00 02 49 1E
15 00 02 4A 1F
15 00 02 4B 17
15 00 02 4C 17
15 00 02 4D 37
15 00 02 4E 37
15 00 02 4F 09
15 00 02 50 09
15 00 02 51 0B
15 00 02 52 0B
15 00 02 53 05
15 00 02 54 05
15 00 02 55 07
15 00 02 56 07
15 00 02 57 1F
15 00 02 58 40
15 00 02 5B 30
15 00 02 5C 00
15 00 02 5D 34
15 00 02 5E 05
15 00 02 5F 02
15 00 02 63 00
15 00 02 64 6A
15 00 02 67 73
15 00 02 68 05
15 00 02 69 08
15 00 02 6A 6A
15 00 02 6B 08
15 00 02 6C 00
15 00 02 6D 00
15 00 02 6E 00
15 00 02 6F 88
15 00 02 75 FF
15 00 02 77 DD
15 00 02 78 2A
15 00 02 79 15
15 00 02 7A 17
15 00 02 7D 14
15 00 02 7E 82
15 00 02 E0 04
15 00 02 00 0E
15 00 02 02 B3
15 00 02 09 61
15 00 02 0E 48
15 00 02 E0 00
15 00 02 E6 02
15 00 02 E7 0C
15 78 02 11 00
15 00 02 E0 00
15 05 02 29 00
];
panel-exit-sequence = [
05 78 01 28
05 00 01 10
];
disp1_timings0: display-timings {
native-mode = <&dsi1_timing0>;
dsi1_timing0: timing0 {
clock-frequency = <69801600>;
hactive = <800>;
vactive = <1280>;
hsync-len = <20>;
hback-porch = <20>;
hfront-porch = <40>;
vsync-len = <4>;
vback-porch = <8>;
vfront-porch = <30>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi1: endpoint {
remote-endpoint = <&dsi1_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi1_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi1>;
};
};
};
};
&i2c5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c5m3_xfer>;
gt911_dsi1: gt911@5d {
status = "okay";
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PB7 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>;
irq-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
touchscreen-inverted-x = <1>;
touchscreen-swapped-x-y = <1>;
};
};

48
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io-hdmi0-vp0.dtsi
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@ -1,48 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
* Copyright (c) 2023 EmbedFire <embedfire@embedfire.com>
*/
/ {
hdmi0_sound: hdmi0-sound {
status = "okay";
compatible = "rockchip,hdmi";
rockchip,mclk-fs = <128>;
rockchip,card-name = "rockchip-hdmi0";
rockchip,cpu = <&i2s5_8ch>;
rockchip,codec = <&hdmi0>;
rockchip,jack-det;
};
};
&i2s5_8ch {
status = "okay";
};
&hdmi0 {
enable-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
cec-enable = "true";
status = "okay";
};
&route_hdmi0{
status = "okay";
connect = <&vp0_out_hdmi0>;
};
&hdmi0_in_vp0 {
status = "okay";
};
&hdmi0_in_vp1 {
status = "disabled";
};
&hdmi0_in_vp2 {
status = "disabled";
};
&hdptxphy_hdmi0 {
status = "okay";
};

1732
arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4io.dts
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File diff suppressed because it is too large Load Diff

1
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@ -1397,7 +1397,6 @@
SYS_STATUS_SUSPEND DMC_FREQ_LEVEL_LOW
SYS_STATUS_VIDEO_4K DMC_FREQ_LEVEL_MID_HIGH
SYS_STATUS_VIDEO_4K_10B DMC_FREQ_LEVEL_MID_HIGH
SYS_STATUS_VIDEO_SVEP DMC_FREQ_LEVEL_MID_HIGH
SYS_STATUS_BOOST DMC_FREQ_LEVEL_HIGH
SYS_STATUS_ISP DMC_FREQ_LEVEL_HIGH
SYS_STATUS_PERFORMANCE DMC_FREQ_LEVEL_HIGH